From: Hans de Goede Date: Mon, 6 Apr 2015 18:55:39 +0000 (+0200) Subject: sunxi: s/sun8i/sun8i_a23/ X-Git-Tag: v2015.07-rc1~6^2~37 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=5e6bacdb84dbf5cb3b24498784807c3f3c7bdeb4;p=u-boot sunxi: s/sun8i/sun8i_a23/ This is a preparation patch for adding A33 support, which will have a mach name of sun8i-a33. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 4bb12ad8bd..59c26ae786 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -38,6 +38,6 @@ obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o -obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o +obj-$(CONFIG_MACH_SUN8I_A23) += dram_sun8i_a23.o obj-y += fel_utils.o endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 260b42d2cf..873f8b31f7 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -89,7 +89,7 @@ void spl_board_load_image(void) void s_init(void) { -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23 /* Magic (undocmented) value taken from boot0, without this DRAM * access gets messed up (seems cache related) */ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800); diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index b6cb9dea64..77435f39f3 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -64,7 +64,7 @@ int print_cpuinfo(void) } #elif defined CONFIG_MACH_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); -#elif defined CONFIG_MACH_SUN8I +#elif defined CONFIG_MACH_SUN8I_A23 puts("CPU: Allwinner A23 (SUN8I)\n"); #else #warning Please update cpu_info.c with correct CPU information @@ -76,7 +76,7 @@ int print_cpuinfo(void) int sunxi_get_sid(unsigned int *sid) { -#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23 #ifdef CONFIG_AXP221_POWER return axp221_get_sid(sid); #else diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i.c deleted file mode 100644 index 3d7964d1af..0000000000 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * Sun8i platform dram controller init. - * - * (C) Copyright 2014 Hans de Goede - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Note this code uses a lot of magic hex values, that is because this code - * simply replays the init sequence as done by the Allwinner boot0 code, so - * we do not know what these values mean. There are no symbolic constants for - * these magic values, since we do not know how to name them and making up - * names for them is not useful. - * - * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one - * found in the TI Keystone2 documentation: - * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf - * "Table4-2 DDR3 PHY Registers" - * This may be used as a (possible) reference for future work / cleanups. - */ - -#include -#include -#include -#include -#include -#include - -static const struct dram_para dram_para = { - .clock = CONFIG_DRAM_CLK, - .type = 3, - .zq = CONFIG_DRAM_ZQ, - .odt_en = 1, - .para1 = 0, /* not used (only used when tpr13 bit 31 is set */ - .para2 = 0, /* not used (only used when tpr13 bit 31 is set */ - .mr0 = 6736, - .mr1 = 4, - .mr2 = 16, - .mr3 = 0, - /* tpr0 - 10 contain timing constants or-ed together in u32 vals */ - .tpr0 = 0x2ab83def, - .tpr1 = 0x18082356, - .tpr2 = 0x00034156, - .tpr3 = 0x448c5533, - .tpr4 = 0x08010d00, - .tpr5 = 0x0340b20f, - .tpr6 = 0x20d118cc, - .tpr7 = 0x14062485, - .tpr8 = 0x220d1d52, - .tpr9 = 0x1e078c22, - .tpr10 = 0x3c, - .tpr11 = 0, /* not used */ - .tpr12 = 0, /* not used */ - .tpr13 = 0x30000, -}; - -static void mctl_sys_init(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - - /* enable pll5, note the divide by 2 is deliberate! */ - clock_set_pll5(dram_para.clock * 1000000 / 2, - dram_para.tpr13 & 0x40000); - - /* deassert ahb mctl reset */ - setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); - - /* enable ahb mctl clock */ - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); -} - -static void mctl_apply_odt_correction(u32 *reg, int correction) -{ - int val; - - val = (readl(reg) >> 8) & 0xff; - val += correction; - - /* clamp */ - if (val < 0) - val = 0; - else if (val > 255) - val = 255; - - clrsetbits_le32(reg, 0xff00, val << 8); -} - -static void mctl_init(u32 *bus_width) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - struct sunxi_mctl_ctl_reg * const mctl_ctl = - (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - struct sunxi_mctl_phy_reg * const mctl_phy = - (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; - int correction; - - if (dram_para.tpr13 & 0x20) - writel(0x40b, &mctl_phy->dcr); - else - writel(0x1000040b, &mctl_phy->dcr); - - if (dram_para.clock >= 480) - writel(0x5c000, &mctl_phy->dllgcr); - else - writel(0xdc000, &mctl_phy->dllgcr); - - writel(0x0a003e3f, &mctl_phy->pgcr0); - writel(0x03008421, &mctl_phy->pgcr1); - - writel(dram_para.mr0, &mctl_phy->mr0); - writel(dram_para.mr1, &mctl_phy->mr1); - writel(dram_para.mr2, &mctl_phy->mr2); - writel(dram_para.mr3, &mctl_phy->mr3); - - if (!(dram_para.tpr13 & 0x10000)) { - clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000); - clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000); - } - - /* - * All the masking and shifting below converts what I assume are DDR - * timing constants from Allwinner dram_para tpr format to the actual - * timing registers format. - */ - - writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2); - writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3); - writel((dram_para.tpr0 & 0x3ff00000) >> 2 | - (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4); - - writel(dram_para.tpr3, &mctl_phy->dtpr0); - writel(dram_para.tpr4, &mctl_phy->dtpr2); - - writel(0x01000081, &mctl_phy->dtcr); - - if (dram_para.clock <= 240 || !(dram_para.odt_en & 0x01)) { - clrbits_le32(&mctl_phy->dx0gcr, 0x600); - clrbits_le32(&mctl_phy->dx1gcr, 0x600); - } - if (dram_para.clock <= 240) { - writel(0, &mctl_phy->odtcr); - writel(0, &mctl_ctl->odtmap); - } - - writel(((dram_para.tpr5 & 0x0f00) << 12) | - ((dram_para.tpr5 & 0x00f8) << 9) | - ((dram_para.tpr5 & 0x0007) << 8), - &mctl_ctl->rfshctl0); - - writel(((dram_para.tpr5 & 0x0003f000) << 12) | - ((dram_para.tpr5 & 0x00fc0000) >> 2) | - ((dram_para.tpr5 & 0x3f000000) >> 16) | - ((dram_para.tpr6 & 0x0000003f) >> 0), - &mctl_ctl->dramtmg0); - - writel(((dram_para.tpr6 & 0x000007c0) << 10) | - ((dram_para.tpr6 & 0x0000f800) >> 3) | - ((dram_para.tpr6 & 0x003f0000) >> 16), - &mctl_ctl->dramtmg1); - - writel(((dram_para.tpr6 & 0x0fc00000) << 2) | - ((dram_para.tpr7 & 0x0000001f) << 16) | - ((dram_para.tpr7 & 0x000003e0) << 3) | - ((dram_para.tpr7 & 0x0000fc00) >> 10), - &mctl_ctl->dramtmg2); - - writel(((dram_para.tpr7 & 0x03ff0000) >> 16) | - ((dram_para.tpr6 & 0xf0000000) >> 16), - &mctl_ctl->dramtmg3); - - writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) | - ((dram_para.tpr8 & 0x00000007) << 16) | - ((dram_para.tpr8 & 0x00000038) << 5) | - ((dram_para.tpr8 & 0x000003c0) >> 6), - &mctl_ctl->dramtmg4); - - writel(((dram_para.tpr8 & 0x00003c00) << 14) | - ((dram_para.tpr8 & 0x0003c000) << 2) | - ((dram_para.tpr8 & 0x00fc0000) >> 10) | - ((dram_para.tpr8 & 0x0f000000) >> 24), - &mctl_ctl->dramtmg5); - - writel(0x00000008, &mctl_ctl->dramtmg8); - - writel(((dram_para.tpr8 & 0xf0000000) >> 4) | - ((dram_para.tpr9 & 0x00007c00) << 6) | - ((dram_para.tpr9 & 0x000003e0) << 3) | - ((dram_para.tpr9 & 0x0000001f) >> 0), - &mctl_ctl->pitmg0); - - setbits_le32(&mctl_ctl->pitmg1, 0x80000); - - writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001, - &mctl_ctl->sched); - - writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3); - writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); - - writel(0x00000000, &mctl_ctl->pimisc); - writel(0x80000000, &mctl_ctl->upd0); - - writel(((dram_para.tpr9 & 0xffc00000) >> 22) | - ((dram_para.tpr10 & 0x00000fff) << 16), - &mctl_ctl->rfshtmg); - - if (dram_para.tpr13 & 0x20) - writel(0x01040001, &mctl_ctl->mstr); - else - writel(0x01040401, &mctl_ctl->mstr); - - if (!(dram_para.tpr13 & 0x20000)) { - writel(0x00000002, &mctl_ctl->pwrctl); - writel(0x00008001, &mctl_ctl->pwrtmg); - } - - writel(0x00000001, &mctl_ctl->rfshctl3); - writel(0x00000001, &mctl_ctl->pimisc); - - /* deassert dram_clk_cfg reset */ - setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); - - setbits_le32(&mctl_com->ccr, 0x80000); - - /* zq stuff */ - writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1); - - writel(0x00000003, &mctl_phy->pir); - udelay(10); - mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09); - - writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2); - writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); - - /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */ - writel(0x000005f3, &mctl_phy->pir); - udelay(10); - mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03); - - if (readl(&mctl_phy->dx1gsr0) & 0x1000000) { - *bus_width = 8; - writel(0, &mctl_phy->dx1gcr); - writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); - writel(0x5f3, &mctl_phy->pir); - udelay(10000); - setbits_le32(&mctl_ctl->mstr, 0x1000); - } else - *bus_width = 16; - - correction = (dram_para.odt_en >> 8) & 0xff; - if (correction) { - if (dram_para.odt_en & 0x80000000) - correction = -correction; - - mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, correction); - mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, correction); - } - - mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01); - - writel(0x08003e3f, &mctl_phy->pgcr0); - writel(0x00000000, &mctl_ctl->rfshctl3); -} - -unsigned long sunxi_dram_init(void) -{ - struct sunxi_mctl_com_reg * const mctl_com = - (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; - const u32 columns = 13; - u32 bus, bus_width, offset, page_size, rows; - - mctl_sys_init(); - mctl_init(&bus_width); - - if (bus_width == 16) { - page_size = 8; - bus = 1; - } else { - page_size = 7; - bus = 0; - } - - if (!(dram_para.tpr13 & 0x80000000)) { - /* Detect and set rows */ - writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size), - &mctl_com->cr); - setbits_le32(&mctl_com->swonr, 0x0003ffff); - for (rows = 11; rows < 16; rows++) { - offset = 1 << (rows + columns + bus); - if (mctl_mem_matches(offset)) - break; - } - clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, - MCTL_CR_ROW(rows)); - } else { - rows = (dram_para.para1 >> 16) & 0xff; - writel(((dram_para.para2 & 0x000000f0) << 11) | - ((rows - 1) << 4) | - ((dram_para.para1 & 0x0f000000) >> 22) | - 0x31000 | MCTL_CR_PAGE_SIZE(page_size), - &mctl_com->cr); - setbits_le32(&mctl_com->swonr, 0x0003ffff); - } - - /* Setup DRAM master priority? If this is left out things still work */ - writel(0x00000008, &mctl_com->mcr0_0); - writel(0x0001000d, &mctl_com->mcr1_0); - writel(0x00000004, &mctl_com->mcr0_1); - writel(0x00000080, &mctl_com->mcr1_1); - writel(0x00000004, &mctl_com->mcr0_2); - writel(0x00000019, &mctl_com->mcr1_2); - writel(0x00000004, &mctl_com->mcr0_3); - writel(0x00000080, &mctl_com->mcr1_3); - writel(0x00000004, &mctl_com->mcr0_4); - writel(0x01010040, &mctl_com->mcr1_4); - writel(0x00000004, &mctl_com->mcr0_5); - writel(0x0001002f, &mctl_com->mcr1_5); - writel(0x00000004, &mctl_com->mcr0_6); - writel(0x00010020, &mctl_com->mcr1_6); - writel(0x00000004, &mctl_com->mcr0_7); - writel(0x00010020, &mctl_com->mcr1_7); - writel(0x00000008, &mctl_com->mcr0_8); - writel(0x00000001, &mctl_com->mcr1_8); - writel(0x00000008, &mctl_com->mcr0_9); - writel(0x00000005, &mctl_com->mcr1_9); - writel(0x00000008, &mctl_com->mcr0_10); - writel(0x00000003, &mctl_com->mcr1_10); - writel(0x00000008, &mctl_com->mcr0_11); - writel(0x00000005, &mctl_com->mcr1_11); - writel(0x00000008, &mctl_com->mcr0_12); - writel(0x00000003, &mctl_com->mcr1_12); - writel(0x00000008, &mctl_com->mcr0_13); - writel(0x00000004, &mctl_com->mcr1_13); - writel(0x00000008, &mctl_com->mcr0_14); - writel(0x00000002, &mctl_com->mcr1_14); - writel(0x00000008, &mctl_com->mcr0_15); - writel(0x00000003, &mctl_com->mcr1_15); - writel(0x00010138, &mctl_com->bwcr); - - return 1 << (rows + columns + bus); -} diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c new file mode 100644 index 0000000000..3d7964d1af --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c @@ -0,0 +1,345 @@ +/* + * Sun8i platform dram controller init. + * + * (C) Copyright 2014 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Note this code uses a lot of magic hex values, that is because this code + * simply replays the init sequence as done by the Allwinner boot0 code, so + * we do not know what these values mean. There are no symbolic constants for + * these magic values, since we do not know how to name them and making up + * names for them is not useful. + * + * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one + * found in the TI Keystone2 documentation: + * http://www.ti.com/lit/ug/spruhn7a/spruhn7a.pdf + * "Table4-2 DDR3 PHY Registers" + * This may be used as a (possible) reference for future work / cleanups. + */ + +#include +#include +#include +#include +#include +#include + +static const struct dram_para dram_para = { + .clock = CONFIG_DRAM_CLK, + .type = 3, + .zq = CONFIG_DRAM_ZQ, + .odt_en = 1, + .para1 = 0, /* not used (only used when tpr13 bit 31 is set */ + .para2 = 0, /* not used (only used when tpr13 bit 31 is set */ + .mr0 = 6736, + .mr1 = 4, + .mr2 = 16, + .mr3 = 0, + /* tpr0 - 10 contain timing constants or-ed together in u32 vals */ + .tpr0 = 0x2ab83def, + .tpr1 = 0x18082356, + .tpr2 = 0x00034156, + .tpr3 = 0x448c5533, + .tpr4 = 0x08010d00, + .tpr5 = 0x0340b20f, + .tpr6 = 0x20d118cc, + .tpr7 = 0x14062485, + .tpr8 = 0x220d1d52, + .tpr9 = 0x1e078c22, + .tpr10 = 0x3c, + .tpr11 = 0, /* not used */ + .tpr12 = 0, /* not used */ + .tpr13 = 0x30000, +}; + +static void mctl_sys_init(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* enable pll5, note the divide by 2 is deliberate! */ + clock_set_pll5(dram_para.clock * 1000000 / 2, + dram_para.tpr13 & 0x40000); + + /* deassert ahb mctl reset */ + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); + + /* enable ahb mctl clock */ + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); +} + +static void mctl_apply_odt_correction(u32 *reg, int correction) +{ + int val; + + val = (readl(reg) >> 8) & 0xff; + val += correction; + + /* clamp */ + if (val < 0) + val = 0; + else if (val > 255) + val = 255; + + clrsetbits_le32(reg, 0xff00, val << 8); +} + +static void mctl_init(u32 *bus_width) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + struct sunxi_mctl_ctl_reg * const mctl_ctl = + (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; + struct sunxi_mctl_phy_reg * const mctl_phy = + (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE; + int correction; + + if (dram_para.tpr13 & 0x20) + writel(0x40b, &mctl_phy->dcr); + else + writel(0x1000040b, &mctl_phy->dcr); + + if (dram_para.clock >= 480) + writel(0x5c000, &mctl_phy->dllgcr); + else + writel(0xdc000, &mctl_phy->dllgcr); + + writel(0x0a003e3f, &mctl_phy->pgcr0); + writel(0x03008421, &mctl_phy->pgcr1); + + writel(dram_para.mr0, &mctl_phy->mr0); + writel(dram_para.mr1, &mctl_phy->mr1); + writel(dram_para.mr2, &mctl_phy->mr2); + writel(dram_para.mr3, &mctl_phy->mr3); + + if (!(dram_para.tpr13 & 0x10000)) { + clrsetbits_le32(&mctl_phy->dx0gcr, 0x3800, 0x2000); + clrsetbits_le32(&mctl_phy->dx1gcr, 0x3800, 0x2000); + } + + /* + * All the masking and shifting below converts what I assume are DDR + * timing constants from Allwinner dram_para tpr format to the actual + * timing registers format. + */ + + writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2); + writel((dram_para.tpr1 & 0x1fffffff), &mctl_phy->ptr3); + writel((dram_para.tpr0 & 0x3ff00000) >> 2 | + (dram_para.tpr2 & 0x0003ffff), &mctl_phy->ptr4); + + writel(dram_para.tpr3, &mctl_phy->dtpr0); + writel(dram_para.tpr4, &mctl_phy->dtpr2); + + writel(0x01000081, &mctl_phy->dtcr); + + if (dram_para.clock <= 240 || !(dram_para.odt_en & 0x01)) { + clrbits_le32(&mctl_phy->dx0gcr, 0x600); + clrbits_le32(&mctl_phy->dx1gcr, 0x600); + } + if (dram_para.clock <= 240) { + writel(0, &mctl_phy->odtcr); + writel(0, &mctl_ctl->odtmap); + } + + writel(((dram_para.tpr5 & 0x0f00) << 12) | + ((dram_para.tpr5 & 0x00f8) << 9) | + ((dram_para.tpr5 & 0x0007) << 8), + &mctl_ctl->rfshctl0); + + writel(((dram_para.tpr5 & 0x0003f000) << 12) | + ((dram_para.tpr5 & 0x00fc0000) >> 2) | + ((dram_para.tpr5 & 0x3f000000) >> 16) | + ((dram_para.tpr6 & 0x0000003f) >> 0), + &mctl_ctl->dramtmg0); + + writel(((dram_para.tpr6 & 0x000007c0) << 10) | + ((dram_para.tpr6 & 0x0000f800) >> 3) | + ((dram_para.tpr6 & 0x003f0000) >> 16), + &mctl_ctl->dramtmg1); + + writel(((dram_para.tpr6 & 0x0fc00000) << 2) | + ((dram_para.tpr7 & 0x0000001f) << 16) | + ((dram_para.tpr7 & 0x000003e0) << 3) | + ((dram_para.tpr7 & 0x0000fc00) >> 10), + &mctl_ctl->dramtmg2); + + writel(((dram_para.tpr7 & 0x03ff0000) >> 16) | + ((dram_para.tpr6 & 0xf0000000) >> 16), + &mctl_ctl->dramtmg3); + + writel(((dram_para.tpr7 & 0x3c000000) >> 2 ) | + ((dram_para.tpr8 & 0x00000007) << 16) | + ((dram_para.tpr8 & 0x00000038) << 5) | + ((dram_para.tpr8 & 0x000003c0) >> 6), + &mctl_ctl->dramtmg4); + + writel(((dram_para.tpr8 & 0x00003c00) << 14) | + ((dram_para.tpr8 & 0x0003c000) << 2) | + ((dram_para.tpr8 & 0x00fc0000) >> 10) | + ((dram_para.tpr8 & 0x0f000000) >> 24), + &mctl_ctl->dramtmg5); + + writel(0x00000008, &mctl_ctl->dramtmg8); + + writel(((dram_para.tpr8 & 0xf0000000) >> 4) | + ((dram_para.tpr9 & 0x00007c00) << 6) | + ((dram_para.tpr9 & 0x000003e0) << 3) | + ((dram_para.tpr9 & 0x0000001f) >> 0), + &mctl_ctl->pitmg0); + + setbits_le32(&mctl_ctl->pitmg1, 0x80000); + + writel(((dram_para.tpr9 & 0x003f8000) << 9) | 0x2001, + &mctl_ctl->sched); + + writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3); + writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); + + writel(0x00000000, &mctl_ctl->pimisc); + writel(0x80000000, &mctl_ctl->upd0); + + writel(((dram_para.tpr9 & 0xffc00000) >> 22) | + ((dram_para.tpr10 & 0x00000fff) << 16), + &mctl_ctl->rfshtmg); + + if (dram_para.tpr13 & 0x20) + writel(0x01040001, &mctl_ctl->mstr); + else + writel(0x01040401, &mctl_ctl->mstr); + + if (!(dram_para.tpr13 & 0x20000)) { + writel(0x00000002, &mctl_ctl->pwrctl); + writel(0x00008001, &mctl_ctl->pwrtmg); + } + + writel(0x00000001, &mctl_ctl->rfshctl3); + writel(0x00000001, &mctl_ctl->pimisc); + + /* deassert dram_clk_cfg reset */ + setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); + + setbits_le32(&mctl_com->ccr, 0x80000); + + /* zq stuff */ + writel((dram_para.zq >> 8) & 0xff, &mctl_phy->zqcr1); + + writel(0x00000003, &mctl_phy->pir); + udelay(10); + mctl_await_completion(&mctl_phy->pgsr0, 0x09, 0x09); + + writel(readl(&mctl_phy->zqsr0) | 0x10000000, &mctl_phy->zqcr2); + writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); + + /* A23-v1.0 SDK uses 0xfdf3, A23-v2.0 SDK uses 0x5f3 */ + writel(0x000005f3, &mctl_phy->pir); + udelay(10); + mctl_await_completion(&mctl_phy->pgsr0, 0x03, 0x03); + + if (readl(&mctl_phy->dx1gsr0) & 0x1000000) { + *bus_width = 8; + writel(0, &mctl_phy->dx1gcr); + writel(dram_para.zq & 0xff, &mctl_phy->zqcr1); + writel(0x5f3, &mctl_phy->pir); + udelay(10000); + setbits_le32(&mctl_ctl->mstr, 0x1000); + } else + *bus_width = 16; + + correction = (dram_para.odt_en >> 8) & 0xff; + if (correction) { + if (dram_para.odt_en & 0x80000000) + correction = -correction; + + mctl_apply_odt_correction(&mctl_phy->dx0lcdlr1, correction); + mctl_apply_odt_correction(&mctl_phy->dx1lcdlr1, correction); + } + + mctl_await_completion(&mctl_ctl->statr, 0x01, 0x01); + + writel(0x08003e3f, &mctl_phy->pgcr0); + writel(0x00000000, &mctl_ctl->rfshctl3); +} + +unsigned long sunxi_dram_init(void) +{ + struct sunxi_mctl_com_reg * const mctl_com = + (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; + const u32 columns = 13; + u32 bus, bus_width, offset, page_size, rows; + + mctl_sys_init(); + mctl_init(&bus_width); + + if (bus_width == 16) { + page_size = 8; + bus = 1; + } else { + page_size = 7; + bus = 0; + } + + if (!(dram_para.tpr13 & 0x80000000)) { + /* Detect and set rows */ + writel(0x000310f4 | MCTL_CR_PAGE_SIZE(page_size), + &mctl_com->cr); + setbits_le32(&mctl_com->swonr, 0x0003ffff); + for (rows = 11; rows < 16; rows++) { + offset = 1 << (rows + columns + bus); + if (mctl_mem_matches(offset)) + break; + } + clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK, + MCTL_CR_ROW(rows)); + } else { + rows = (dram_para.para1 >> 16) & 0xff; + writel(((dram_para.para2 & 0x000000f0) << 11) | + ((rows - 1) << 4) | + ((dram_para.para1 & 0x0f000000) >> 22) | + 0x31000 | MCTL_CR_PAGE_SIZE(page_size), + &mctl_com->cr); + setbits_le32(&mctl_com->swonr, 0x0003ffff); + } + + /* Setup DRAM master priority? If this is left out things still work */ + writel(0x00000008, &mctl_com->mcr0_0); + writel(0x0001000d, &mctl_com->mcr1_0); + writel(0x00000004, &mctl_com->mcr0_1); + writel(0x00000080, &mctl_com->mcr1_1); + writel(0x00000004, &mctl_com->mcr0_2); + writel(0x00000019, &mctl_com->mcr1_2); + writel(0x00000004, &mctl_com->mcr0_3); + writel(0x00000080, &mctl_com->mcr1_3); + writel(0x00000004, &mctl_com->mcr0_4); + writel(0x01010040, &mctl_com->mcr1_4); + writel(0x00000004, &mctl_com->mcr0_5); + writel(0x0001002f, &mctl_com->mcr1_5); + writel(0x00000004, &mctl_com->mcr0_6); + writel(0x00010020, &mctl_com->mcr1_6); + writel(0x00000004, &mctl_com->mcr0_7); + writel(0x00010020, &mctl_com->mcr1_7); + writel(0x00000008, &mctl_com->mcr0_8); + writel(0x00000001, &mctl_com->mcr1_8); + writel(0x00000008, &mctl_com->mcr0_9); + writel(0x00000005, &mctl_com->mcr1_9); + writel(0x00000008, &mctl_com->mcr0_10); + writel(0x00000003, &mctl_com->mcr1_10); + writel(0x00000008, &mctl_com->mcr0_11); + writel(0x00000005, &mctl_com->mcr1_11); + writel(0x00000008, &mctl_com->mcr0_12); + writel(0x00000003, &mctl_com->mcr1_12); + writel(0x00000008, &mctl_com->mcr0_13); + writel(0x00000004, &mctl_com->mcr1_13); + writel(0x00000008, &mctl_com->mcr0_14); + writel(0x00000002, &mctl_com->mcr1_14); + writel(0x00000008, &mctl_com->mcr0_15); + writel(0x00000003, &mctl_com->mcr1_15); + writel(0x00010138, &mctl_com->bwcr); + + return 1 << (rows + columns + bus); +} diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index aedd1941d5..bb96cc572a 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -18,8 +18,8 @@ /* dram regs definition */ #if defined(CONFIG_MACH_SUN6I) #include -#elif defined(CONFIG_MACH_SUN8I) -#include +#elif defined(CONFIG_MACH_SUN8I_A23) +#include #else #include #endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i.h deleted file mode 100644 index 06adee2723..0000000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i.h +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Sun8i platform dram controller register and constant defines - * - * (C) Copyright 2007-2013 - * Allwinner Technology Co., Ltd. - * CPL - * Jerry Wang - * - * (C) Copyright 2014 Hans de Goede - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SUNXI_DRAM_SUN8I_H -#define _SUNXI_DRAM_SUN8I_H - -struct dram_para { - u32 clock; - u32 type; - u32 zq; - u32 odt_en; - u32 para1; - u32 para2; - u32 mr0; - u32 mr1; - u32 mr2; - u32 mr3; - u32 tpr0; - u32 tpr1; - u32 tpr2; - u32 tpr3; - u32 tpr4; - u32 tpr5; - u32 tpr6; - u32 tpr7; - u32 tpr8; - u32 tpr9; - u32 tpr10; - u32 tpr11; - u32 tpr12; - u32 tpr13; -}; - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 */ - u32 ccr; /* 0x04 controller configuration register */ - u32 dbgcr; /* 0x08 */ - u8 res0[0x4]; /* 0x0c */ - u32 mcr0_0; /* 0x10 */ - u32 mcr1_0; /* 0x14 */ - u32 mcr0_1; /* 0x18 */ - u32 mcr1_1; /* 0x1c */ - u32 mcr0_2; /* 0x20 */ - u32 mcr1_2; /* 0x24 */ - u32 mcr0_3; /* 0x28 */ - u32 mcr1_3; /* 0x2c */ - u32 mcr0_4; /* 0x30 */ - u32 mcr1_4; /* 0x34 */ - u32 mcr0_5; /* 0x38 */ - u32 mcr1_5; /* 0x3c */ - u32 mcr0_6; /* 0x40 */ - u32 mcr1_6; /* 0x44 */ - u32 mcr0_7; /* 0x48 */ - u32 mcr1_7; /* 0x4c */ - u32 mcr0_8; /* 0x50 */ - u32 mcr1_8; /* 0x54 */ - u32 mcr0_9; /* 0x58 */ - u32 mcr1_9; /* 0x5c */ - u32 mcr0_10; /* 0x60 */ - u32 mcr1_10; /* 0x64 */ - u32 mcr0_11; /* 0x68 */ - u32 mcr1_11; /* 0x6c */ - u32 mcr0_12; /* 0x70 */ - u32 mcr1_12; /* 0x74 */ - u32 mcr0_13; /* 0x78 */ - u32 mcr1_13; /* 0x7c */ - u32 mcr0_14; /* 0x80 */ - u32 mcr1_14; /* 0x84 */ - u32 mcr0_15; /* 0x88 */ - u32 mcr1_15; /* 0x8c */ - u32 bwcr; /* 0x90 */ - u32 maer; /* 0x94 */ - u8 res1[0x4]; /* 0x98 */ - u32 mcgcr; /* 0x9c */ - u32 bwctr; /* 0xa0 */ - u8 res2[0x4]; /* 0xa4 */ - u32 swonr; /* 0xa8 */ - u32 swoffr; /* 0xac */ -}; - -struct sunxi_mctl_ctl_reg { - u32 mstr; /* 0x00 */ - u32 statr; /* 0x04 */ - u8 res0[0x08]; /* 0x08 */ - u32 mrctrl0; /* 0x10 */ - u32 mrctrl1; /* 0x14 */ - u32 mrstatr; /* 0x18 */ - u8 res1[0x04]; /* 0x1c */ - u32 derateen; /* 0x20 */ - u32 deratenint; /* 0x24 */ - u8 res2[0x08]; /* 0x28 */ - u32 pwrctl; /* 0x30 */ - u32 pwrtmg; /* 0x34 */ - u8 res3[0x18]; /* 0x38 */ - u32 rfshctl0; /* 0x50 */ - u32 rfshctl1; /* 0x54 */ - u8 res4[0x8]; /* 0x58 */ - u32 rfshctl3; /* 0x60 */ - u32 rfshtmg; /* 0x64 */ - u8 res6[0x68]; /* 0x68 */ - u32 init0; /* 0xd0 */ - u32 init1; /* 0xd4 */ - u32 init2; /* 0xd8 */ - u32 init3; /* 0xdc */ - u32 init4; /* 0xe0 */ - u32 init5; /* 0xe4 */ - u8 res7[0x0c]; /* 0xe8 */ - u32 rankctl; /* 0xf4 */ - u8 res8[0x08]; /* 0xf8 */ - u32 dramtmg0; /* 0x100 */ - u32 dramtmg1; /* 0x104 */ - u32 dramtmg2; /* 0x108 */ - u32 dramtmg3; /* 0x10c */ - u32 dramtmg4; /* 0x110 */ - u32 dramtmg5; /* 0x114 */ - u32 dramtmg6; /* 0x118 */ - u32 dramtmg7; /* 0x11c */ - u32 dramtmg8; /* 0x120 */ - u8 res9[0x5c]; /* 0x124 */ - u32 zqctl0; /* 0x180 */ - u32 zqctl1; /* 0x184 */ - u32 zqctl2; /* 0x188 */ - u32 zqstat; /* 0x18c */ - u32 pitmg0; /* 0x190 */ - u32 pitmg1; /* 0x194 */ - u32 plpcfg0; /* 0x198 */ - u8 res10[0x04]; /* 0x19c */ - u32 upd0; /* 0x1a0 */ - u32 upd1; /* 0x1a4 */ - u32 upd2; /* 0x1a8 */ - u32 upd3; /* 0x1ac */ - u32 pimisc; /* 0x1b0 */ - u8 res11[0x1c]; /* 0x1b4 */ - u32 trainctl0; /* 0x1d0 */ - u32 trainctl1; /* 0x1d4 */ - u32 trainctl2; /* 0x1d8 */ - u32 trainstat; /* 0x1dc */ - u8 res12[0x60]; /* 0x1e0 */ - u32 odtcfg; /* 0x240 */ - u32 odtmap; /* 0x244 */ - u8 res13[0x08]; /* 0x248 */ - u32 sched; /* 0x250 */ - u8 res14[0x04]; /* 0x254 */ - u32 perfshpr0; /* 0x258 */ - u32 perfshpr1; /* 0x25c */ - u32 perflpr0; /* 0x260 */ - u32 perflpr1; /* 0x264 */ - u32 perfwr0; /* 0x268 */ - u32 perfwr1; /* 0x26c */ -}; - -struct sunxi_mctl_phy_reg { - u8 res0[0x04]; /* 0x00 */ - u32 pir; /* 0x04 */ - u32 pgcr0; /* 0x08 phy general configuration register */ - u32 pgcr1; /* 0x0c phy general configuration register */ - u32 pgsr0; /* 0x10 */ - u32 pgsr1; /* 0x14 */ - u32 dllgcr; /* 0x18 */ - u32 ptr0; /* 0x1c */ - u32 ptr1; /* 0x20 */ - u32 ptr2; /* 0x24 */ - u32 ptr3; /* 0x28 */ - u32 ptr4; /* 0x2c */ - u32 acmdlr; /* 0x30 */ - u32 acbdlr; /* 0x34 */ - u32 aciocr; /* 0x38 */ - u32 dxccr; /* 0x3c DATX8 common configuration register */ - u32 dsgcr; /* 0x40 dram system general config register */ - u32 dcr; /* 0x44 */ - u32 dtpr0; /* 0x48 dram timing parameters register 0 */ - u32 dtpr1; /* 0x4c dram timing parameters register 1 */ - u32 dtpr2; /* 0x50 dram timing parameters register 2 */ - u32 mr0; /* 0x54 mode register 0 */ - u32 mr1; /* 0x58 mode register 1 */ - u32 mr2; /* 0x5c mode register 2 */ - u32 mr3; /* 0x60 mode register 3 */ - u32 odtcr; /* 0x64 */ - u32 dtcr; /* 0x68 */ - u32 dtar0; /* 0x6c data training address register 0 */ - u32 dtar1; /* 0x70 data training address register 1 */ - u32 dtar2; /* 0x74 data training address register 2 */ - u32 dtar3; /* 0x78 data training address register 3 */ - u32 dtdr0; /* 0x7c */ - u32 dtdr1; /* 0x80 */ - u32 dtedr0; /* 0x84 */ - u32 dtedr1; /* 0x88 */ - u32 pgcr2; /* 0x8c */ - u8 res1[0x70]; /* 0x90 */ - u32 bistrr; /* 0x100 */ - u32 bistwcr; /* 0x104 */ - u32 bistmskr0; /* 0x108 */ - u32 bistmskr1; /* 0x10c */ - u32 bistmskr2; /* 0x110 */ - u32 bistlsr; /* 0x114 */ - u32 bistar0; /* 0x118 */ - u32 bistar1; /* 0x11c */ - u32 bistar2; /* 0x120 */ - u32 bistupdr; /* 0x124 */ - u32 bistgsr; /* 0x128 */ - u32 bistwer; /* 0x12c */ - u32 bistber0; /* 0x130 */ - u32 bistber1; /* 0x134 */ - u32 bistber2; /* 0x138 */ - u32 bistber3; /* 0x13c */ - u32 bistwcsr; /* 0x140 */ - u32 bistfwr0; /* 0x144 */ - u32 bistfwr1; /* 0x148 */ - u32 bistfwr2; /* 0x14c */ - u8 res2[0x30]; /* 0x150 */ - u32 zqcr0; /* 0x180 zq control register 0 */ - u32 zqcr1; /* 0x184 zq control register 1 */ - u32 zqsr0; /* 0x188 zq status register 0 */ - u32 zqsr1; /* 0x18c zq status register 1 */ - u32 zqcr2; /* 0x190 zq control register 2 */ - u8 res3[0x2c]; /* 0x194 */ - u32 dx0gcr; /* 0x1c0 */ - u32 dx0gsr0; /* 0x1c4 */ - u32 dx0gsr1; /* 0x1c8 */ - u32 dx0bdlr0; /* 0x1cc */ - u32 dx0bdlr1; /* 0x1d0 */ - u32 dx0bdlr2; /* 0x1d4 */ - u32 dx0bdlr3; /* 0x1d8 */ - u32 dx0bdlr4; /* 0x1dc */ - u32 dx0lcdlr0; /* 0x1e0 */ - u32 dx0lcdlr1; /* 0x1e4 */ - u32 dx0lcdlr2; /* 0x1e8 */ - u32 dx0mdlr; /* 0x1ec */ - u32 dx0gtr; /* 0x1f0 */ - u32 dx0gsr2; /* 0x1f4 */ - u8 res4[0x08]; /* 0x1f8 */ - u32 dx1gcr; /* 0x200 */ - u32 dx1gsr0; /* 0x204 */ - u32 dx1gsr1; /* 0x208 */ - u32 dx1bdlr0; /* 0x20c */ - u32 dx1bdlr1; /* 0x210 */ - u32 dx1bdlr2; /* 0x214 */ - u32 dx1bdlr3; /* 0x218 */ - u32 dx1bdlr4; /* 0x21c */ - u32 dx1lcdlr0; /* 0x220 */ - u32 dx1lcdlr1; /* 0x224 */ - u32 dx1lcdlr2; /* 0x228 */ - u32 dx1mdlr; /* 0x22c */ - u32 dx1gtr; /* 0x230 */ - u32 dx1gsr2; /* 0x234 */ -}; - -/* - * DRAM common (sunxi_mctl_com_reg) register constants. - */ -#define MCTL_CR_ROW_MASK (0xf << 4) -#define MCTL_CR_ROW(x) (((x) - 1) << 4) -#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) -#define MCTL_CR_PAGE_SIZE(x) ((x) << 8) - -#endif /* _SUNXI_DRAM_SUN8I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h new file mode 100644 index 0000000000..06adee2723 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h @@ -0,0 +1,266 @@ +/* + * Sun8i platform dram controller register and constant defines + * + * (C) Copyright 2007-2013 + * Allwinner Technology Co., Ltd. + * CPL + * Jerry Wang + * + * (C) Copyright 2014 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_DRAM_SUN8I_H +#define _SUNXI_DRAM_SUN8I_H + +struct dram_para { + u32 clock; + u32 type; + u32 zq; + u32 odt_en; + u32 para1; + u32 para2; + u32 mr0; + u32 mr1; + u32 mr2; + u32 mr3; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr3; + u32 tpr4; + u32 tpr5; + u32 tpr6; + u32 tpr7; + u32 tpr8; + u32 tpr9; + u32 tpr10; + u32 tpr11; + u32 tpr12; + u32 tpr13; +}; + +struct sunxi_mctl_com_reg { + u32 cr; /* 0x00 */ + u32 ccr; /* 0x04 controller configuration register */ + u32 dbgcr; /* 0x08 */ + u8 res0[0x4]; /* 0x0c */ + u32 mcr0_0; /* 0x10 */ + u32 mcr1_0; /* 0x14 */ + u32 mcr0_1; /* 0x18 */ + u32 mcr1_1; /* 0x1c */ + u32 mcr0_2; /* 0x20 */ + u32 mcr1_2; /* 0x24 */ + u32 mcr0_3; /* 0x28 */ + u32 mcr1_3; /* 0x2c */ + u32 mcr0_4; /* 0x30 */ + u32 mcr1_4; /* 0x34 */ + u32 mcr0_5; /* 0x38 */ + u32 mcr1_5; /* 0x3c */ + u32 mcr0_6; /* 0x40 */ + u32 mcr1_6; /* 0x44 */ + u32 mcr0_7; /* 0x48 */ + u32 mcr1_7; /* 0x4c */ + u32 mcr0_8; /* 0x50 */ + u32 mcr1_8; /* 0x54 */ + u32 mcr0_9; /* 0x58 */ + u32 mcr1_9; /* 0x5c */ + u32 mcr0_10; /* 0x60 */ + u32 mcr1_10; /* 0x64 */ + u32 mcr0_11; /* 0x68 */ + u32 mcr1_11; /* 0x6c */ + u32 mcr0_12; /* 0x70 */ + u32 mcr1_12; /* 0x74 */ + u32 mcr0_13; /* 0x78 */ + u32 mcr1_13; /* 0x7c */ + u32 mcr0_14; /* 0x80 */ + u32 mcr1_14; /* 0x84 */ + u32 mcr0_15; /* 0x88 */ + u32 mcr1_15; /* 0x8c */ + u32 bwcr; /* 0x90 */ + u32 maer; /* 0x94 */ + u8 res1[0x4]; /* 0x98 */ + u32 mcgcr; /* 0x9c */ + u32 bwctr; /* 0xa0 */ + u8 res2[0x4]; /* 0xa4 */ + u32 swonr; /* 0xa8 */ + u32 swoffr; /* 0xac */ +}; + +struct sunxi_mctl_ctl_reg { + u32 mstr; /* 0x00 */ + u32 statr; /* 0x04 */ + u8 res0[0x08]; /* 0x08 */ + u32 mrctrl0; /* 0x10 */ + u32 mrctrl1; /* 0x14 */ + u32 mrstatr; /* 0x18 */ + u8 res1[0x04]; /* 0x1c */ + u32 derateen; /* 0x20 */ + u32 deratenint; /* 0x24 */ + u8 res2[0x08]; /* 0x28 */ + u32 pwrctl; /* 0x30 */ + u32 pwrtmg; /* 0x34 */ + u8 res3[0x18]; /* 0x38 */ + u32 rfshctl0; /* 0x50 */ + u32 rfshctl1; /* 0x54 */ + u8 res4[0x8]; /* 0x58 */ + u32 rfshctl3; /* 0x60 */ + u32 rfshtmg; /* 0x64 */ + u8 res6[0x68]; /* 0x68 */ + u32 init0; /* 0xd0 */ + u32 init1; /* 0xd4 */ + u32 init2; /* 0xd8 */ + u32 init3; /* 0xdc */ + u32 init4; /* 0xe0 */ + u32 init5; /* 0xe4 */ + u8 res7[0x0c]; /* 0xe8 */ + u32 rankctl; /* 0xf4 */ + u8 res8[0x08]; /* 0xf8 */ + u32 dramtmg0; /* 0x100 */ + u32 dramtmg1; /* 0x104 */ + u32 dramtmg2; /* 0x108 */ + u32 dramtmg3; /* 0x10c */ + u32 dramtmg4; /* 0x110 */ + u32 dramtmg5; /* 0x114 */ + u32 dramtmg6; /* 0x118 */ + u32 dramtmg7; /* 0x11c */ + u32 dramtmg8; /* 0x120 */ + u8 res9[0x5c]; /* 0x124 */ + u32 zqctl0; /* 0x180 */ + u32 zqctl1; /* 0x184 */ + u32 zqctl2; /* 0x188 */ + u32 zqstat; /* 0x18c */ + u32 pitmg0; /* 0x190 */ + u32 pitmg1; /* 0x194 */ + u32 plpcfg0; /* 0x198 */ + u8 res10[0x04]; /* 0x19c */ + u32 upd0; /* 0x1a0 */ + u32 upd1; /* 0x1a4 */ + u32 upd2; /* 0x1a8 */ + u32 upd3; /* 0x1ac */ + u32 pimisc; /* 0x1b0 */ + u8 res11[0x1c]; /* 0x1b4 */ + u32 trainctl0; /* 0x1d0 */ + u32 trainctl1; /* 0x1d4 */ + u32 trainctl2; /* 0x1d8 */ + u32 trainstat; /* 0x1dc */ + u8 res12[0x60]; /* 0x1e0 */ + u32 odtcfg; /* 0x240 */ + u32 odtmap; /* 0x244 */ + u8 res13[0x08]; /* 0x248 */ + u32 sched; /* 0x250 */ + u8 res14[0x04]; /* 0x254 */ + u32 perfshpr0; /* 0x258 */ + u32 perfshpr1; /* 0x25c */ + u32 perflpr0; /* 0x260 */ + u32 perflpr1; /* 0x264 */ + u32 perfwr0; /* 0x268 */ + u32 perfwr1; /* 0x26c */ +}; + +struct sunxi_mctl_phy_reg { + u8 res0[0x04]; /* 0x00 */ + u32 pir; /* 0x04 */ + u32 pgcr0; /* 0x08 phy general configuration register */ + u32 pgcr1; /* 0x0c phy general configuration register */ + u32 pgsr0; /* 0x10 */ + u32 pgsr1; /* 0x14 */ + u32 dllgcr; /* 0x18 */ + u32 ptr0; /* 0x1c */ + u32 ptr1; /* 0x20 */ + u32 ptr2; /* 0x24 */ + u32 ptr3; /* 0x28 */ + u32 ptr4; /* 0x2c */ + u32 acmdlr; /* 0x30 */ + u32 acbdlr; /* 0x34 */ + u32 aciocr; /* 0x38 */ + u32 dxccr; /* 0x3c DATX8 common configuration register */ + u32 dsgcr; /* 0x40 dram system general config register */ + u32 dcr; /* 0x44 */ + u32 dtpr0; /* 0x48 dram timing parameters register 0 */ + u32 dtpr1; /* 0x4c dram timing parameters register 1 */ + u32 dtpr2; /* 0x50 dram timing parameters register 2 */ + u32 mr0; /* 0x54 mode register 0 */ + u32 mr1; /* 0x58 mode register 1 */ + u32 mr2; /* 0x5c mode register 2 */ + u32 mr3; /* 0x60 mode register 3 */ + u32 odtcr; /* 0x64 */ + u32 dtcr; /* 0x68 */ + u32 dtar0; /* 0x6c data training address register 0 */ + u32 dtar1; /* 0x70 data training address register 1 */ + u32 dtar2; /* 0x74 data training address register 2 */ + u32 dtar3; /* 0x78 data training address register 3 */ + u32 dtdr0; /* 0x7c */ + u32 dtdr1; /* 0x80 */ + u32 dtedr0; /* 0x84 */ + u32 dtedr1; /* 0x88 */ + u32 pgcr2; /* 0x8c */ + u8 res1[0x70]; /* 0x90 */ + u32 bistrr; /* 0x100 */ + u32 bistwcr; /* 0x104 */ + u32 bistmskr0; /* 0x108 */ + u32 bistmskr1; /* 0x10c */ + u32 bistmskr2; /* 0x110 */ + u32 bistlsr; /* 0x114 */ + u32 bistar0; /* 0x118 */ + u32 bistar1; /* 0x11c */ + u32 bistar2; /* 0x120 */ + u32 bistupdr; /* 0x124 */ + u32 bistgsr; /* 0x128 */ + u32 bistwer; /* 0x12c */ + u32 bistber0; /* 0x130 */ + u32 bistber1; /* 0x134 */ + u32 bistber2; /* 0x138 */ + u32 bistber3; /* 0x13c */ + u32 bistwcsr; /* 0x140 */ + u32 bistfwr0; /* 0x144 */ + u32 bistfwr1; /* 0x148 */ + u32 bistfwr2; /* 0x14c */ + u8 res2[0x30]; /* 0x150 */ + u32 zqcr0; /* 0x180 zq control register 0 */ + u32 zqcr1; /* 0x184 zq control register 1 */ + u32 zqsr0; /* 0x188 zq status register 0 */ + u32 zqsr1; /* 0x18c zq status register 1 */ + u32 zqcr2; /* 0x190 zq control register 2 */ + u8 res3[0x2c]; /* 0x194 */ + u32 dx0gcr; /* 0x1c0 */ + u32 dx0gsr0; /* 0x1c4 */ + u32 dx0gsr1; /* 0x1c8 */ + u32 dx0bdlr0; /* 0x1cc */ + u32 dx0bdlr1; /* 0x1d0 */ + u32 dx0bdlr2; /* 0x1d4 */ + u32 dx0bdlr3; /* 0x1d8 */ + u32 dx0bdlr4; /* 0x1dc */ + u32 dx0lcdlr0; /* 0x1e0 */ + u32 dx0lcdlr1; /* 0x1e4 */ + u32 dx0lcdlr2; /* 0x1e8 */ + u32 dx0mdlr; /* 0x1ec */ + u32 dx0gtr; /* 0x1f0 */ + u32 dx0gsr2; /* 0x1f4 */ + u8 res4[0x08]; /* 0x1f8 */ + u32 dx1gcr; /* 0x200 */ + u32 dx1gsr0; /* 0x204 */ + u32 dx1gsr1; /* 0x208 */ + u32 dx1bdlr0; /* 0x20c */ + u32 dx1bdlr1; /* 0x210 */ + u32 dx1bdlr2; /* 0x214 */ + u32 dx1bdlr3; /* 0x218 */ + u32 dx1bdlr4; /* 0x21c */ + u32 dx1lcdlr0; /* 0x220 */ + u32 dx1lcdlr1; /* 0x224 */ + u32 dx1lcdlr2; /* 0x228 */ + u32 dx1mdlr; /* 0x22c */ + u32 dx1gtr; /* 0x230 */ + u32 dx1gsr2; /* 0x234 */ +}; + +/* + * DRAM common (sunxi_mctl_com_reg) register constants. + */ +#define MCTL_CR_ROW_MASK (0xf << 4) +#define MCTL_CR_ROW(x) (((x) - 1) << 4) +#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) +#define MCTL_CR_PAGE_SIZE(x) ((x) << 8) + +#endif /* _SUNXI_DRAM_SUN8I_H */ diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index b716a8ba1e..3d865d140c 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -46,7 +46,7 @@ config MACH_SUN7I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT -config MACH_SUN8I +config MACH_SUN8I_A23 bool "sun8i (Allwinner A23)" select CPU_V7 select SUNXI_GEN_SUN6I @@ -54,6 +54,12 @@ config MACH_SUN8I endchoice +# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33" +config MACH_SUN8I + bool + default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 + + config DRAM_CLK int "sunxi dram clock speed" default 312 if MACH_SUN6I || MACH_SUN8I diff --git a/configs/Ippo_q8h_v1_2_defconfig b/configs/Ippo_q8h_v1_2_defconfig index e003b4ccc6..d9455c8f35 100644 --- a/configs/Ippo_q8h_v1_2_defconfig +++ b/configs/Ippo_q8h_v1_2_defconfig @@ -11,7 +11,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I=y +CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=432 # zq = 0xf74a CONFIG_DRAM_ZQ=63306 diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig index 87d898e983..4cc9a5e1eb 100644 --- a/configs/Ippo_q8h_v5_defconfig +++ b/configs/Ippo_q8h_v5_defconfig @@ -11,7 +11,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_ARM=y CONFIG_ARCH_SUNXI=y -CONFIG_MACH_SUN8I=y +CONFIG_MACH_SUN8I_A23=y CONFIG_DRAM_CLK=480 # zq = 0xf777 CONFIG_DRAM_ZQ=63351