From: Marek Vasut <marex@denx.de>
Date: Mon, 21 Mar 2016 12:38:11 +0000 (+0100)
Subject: arm: socfpga: Handle phy-mode OF property for GMACs
X-Git-Tag: v2016.05-rc1~28^2~4
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=5f79d008408dfe46172f46f8532e5ef6b3616067;p=u-boot

arm: socfpga: Handle phy-mode OF property for GMACs

Thus far, the socfpga init code had hard-coded the configuration
of the ethernet PHY interface to RGMII in the ethernet registers
in sysmgr space, so PHYs connected in another modes did not work.

This patch fixes support for configurations where the ethernet PHYs
are connected over MII/GMII/RMII interfaces by parsing the phy-mode
OF property of the GMACs and configuring the ethernet registers in
sysmgr space accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
Reported-by: Denis Bakhvalov <denis.bakhvalov@nokia.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
---

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ce3ff0acc4..5f988e3ae8 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -77,7 +77,8 @@ void v7_outer_cache_disable(void)
  * DesignWare Ethernet initialization
  */
 #ifdef CONFIG_ETH_DESIGNWARE
-static void dwmac_deassert_reset(const unsigned int of_reset_id)
+static void dwmac_deassert_reset(const unsigned int of_reset_id,
+				 const u32 phymode)
 {
 	u32 physhift, reset;
 
@@ -98,16 +99,41 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id)
 
 	/* configure to PHY interface select choosed */
 	setbits_le32(&sysmgr_regs->emacgrp_ctrl,
-		     SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
+		     phymode << physhift);
 
 	/* Release the EMAC controller from reset */
 	socfpga_per_reset(reset, 0);
 }
 
+static u32 dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
+{
+	if (!phymode)
+		return -EINVAL;
+
+	if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+		return 0;
+	}
+
+	if (!strcmp(phymode, "rgmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
+		return 0;
+	}
+
+	if (!strcmp(phymode, "rmii")) {
+		*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
 static int socfpga_eth_reset(void)
 {
 	const void *fdt = gd->fdt_blob;
 	struct fdtdec_phandle_args args;
+	const char *phy_mode;
+	u32 phy_modereg;
 	int nodes[2];	/* Max. two GMACs */
 	int ret, count;
 	int i, node;
@@ -132,7 +158,14 @@ static int socfpga_eth_reset(void)
 			continue;
 		}
 
-		dwmac_deassert_reset(args.args[0]);
+		phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
+		ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
+		if (ret) {
+			debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
+			continue;
+		}
+
+		dwmac_deassert_reset(args.args[0], phy_modereg);
 	}
 
 	return 0;