From: rtel Date: Wed, 23 Sep 2015 12:16:10 +0000 (+0000) Subject: FreeRTOS source: X-Git-Tag: V8.2.3~11 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=5fd911e4d2fe8d365a5a3ed051538cd57c2550d2;p=freertos FreeRTOS source: + Added Renesas RXv2 port for IAR. Demo apps: + Demo/Rename the CORTEX_R4F_T_GCC_IAR_ARM directory to just Rename the CORTEX_R4F_T_GCC_IAR. + Add IAR project for the RX113. + Add RX231 e2studio projects for the RX231. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2380 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.HardwareDebuglinker b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.HardwareDebuglinker new file mode 100644 index 000000000..b9aca814d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.HardwareDebuglinker @@ -0,0 +1,146 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.Releaselinker b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.Releaselinker new file mode 100644 index 000000000..da6f60055 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.Releaselinker @@ -0,0 +1,89 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.cproject b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.cproject new file mode 100644 index 000000000..b6ac7fa6a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.cproject @@ -0,0 +1,166 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.info b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.info new file mode 100644 index 000000000..88f4c78c5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.info @@ -0,0 +1,7 @@ +TOOL_CHAIN=KPIT GNUARM-NONE-EABI Toolchain +VERSION=v14.02 +TC_INSTALL=C:\Program Files (x86)\KPIT\GNUARM-NONEv14.02-EABI\arm-none-eabi\arm-none-eabi\ +GCC_STRING=4.9-GNUARM-NONE_v14.02 +VERSION_IDE= +E2STUDIO_VERSION=4.0.2.008 +ACTIVE_CONFIGURATION=HardwareDebug diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.project b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.project new file mode 100644 index 000000000..46213b545 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.project @@ -0,0 +1,232 @@ + + + RTOSDemo + + + + + + com.renesas.cdt.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.renesas.cdt.core.kpitcnature + com.renesas.cdt.core.kpitccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1442133034715 + System + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1440591358527 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1440591358537 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1441019347018 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 1441019347028 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1441019347038 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1441019347048 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1441019347058 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1441019347058 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1441019347068 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1441019347078 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1441019347078 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1441019347088 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TimerDemo.c + + + + 1441019347098 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1441019347098 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1441019347108 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1441019347108 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1441019347118 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-death.c + + + + 1440591394340 + src/FreeRTOS_Source/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ARM_CRx_No_GIC + + + + 1440591376868 + src/FreeRTOS_Source/portable/MemMang + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-heap_4.c + + + + + + FREERTOS_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.settings/Dependency_Scan_Preferences.prefs b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.settings/Dependency_Scan_Preferences.prefs new file mode 100644 index 000000000..c52c797ff --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.settings/Dependency_Scan_Preferences.prefs @@ -0,0 +1,4 @@ +Build\ project\ excluding\ the\ dependencies=false +Re-generate\ and\ use\ dependencies\ during\ project\ build=true +Use\ existing\ dependencies\ during\ project\ build=false +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.settings/Project_Generation_Prefrences.prefs b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.settings/Project_Generation_Prefrences.prefs new file mode 100644 index 000000000..b6b9d5c8d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.settings/Project_Generation_Prefrences.prefs @@ -0,0 +1,36 @@ +com.renesas.cdt.core.Assembler.option.includeFileDirectories="${workspace_loc\:/${ProjName}}/src"; +com.renesas.cdt.core.LibraryGenerator.option.ctype=false +com.renesas.cdt.core.LibraryGenerator.option.libraryType=Project-Built +com.renesas.cdt.core.LibraryGenerator.option.math=false +com.renesas.cdt.core.LibraryGenerator.option.selectLibrary=Optimized +com.renesas.cdt.core.LibraryGenerator.option.stdio=true +com.renesas.cdt.core.LibraryGenerator.option.stdlib=true +com.renesas.cdt.core.LibraryGenerator.option.string=true +com.renesas.cdt.core.Linker.option.userDefinedOptions=; +com.renesas.cdt.rz.HardwareDebug.Assembler.option.architecture=armv7-r +com.renesas.cdt.rz.HardwareDebug.Assembler.option.cpuType=cortex-r4f +com.renesas.cdt.rz.HardwareDebug.Compiler.option.architecture=armv7-r +com.renesas.cdt.rz.HardwareDebug.Compiler.option.cpuType=cortex-r4f +com.renesas.cdt.rz.HardwareDebug.Compiler.option.cpuType.585789719=cortex-r4f +com.renesas.cdt.rz.HardwareDebug.Compiler.option.dataEndian=Little-endian +com.renesas.cdt.rz.HardwareDebug.Compiler.option.floatingpointabi=Soft +com.renesas.cdt.rz.HardwareDebug.Compiler.option.instructionset=ARM +com.renesas.cdt.rz.HardwareDebug.Compiler.option.interworking=true +com.renesas.cdt.rz.HardwareDebug.Compiler.option.macroDefines= +com.renesas.cdt.rz.HardwareDebug.Compiler.option.targetfpu=vfp +com.renesas.cdt.rz.HardwareDebug.Linker.option.archiveLibraryFiles=${BuildArtifactFileBaseName};gcc; +com.renesas.cdt.rz.HardwareDebug.Linker.option.archiveSearchDirectories.1574512948="${TCINSTALL}/lib/gcc/arm-none-eabi/${GCC_VERSION}/fpu/interwork";"${TCINSTALL}/arm-none-eabi/lib/fpu/interwork"; +com.renesas.cdt.rz.Release.Assembler.option.architecture=armv7-r +com.renesas.cdt.rz.Release.Assembler.option.cpuType=cortex-r4f +com.renesas.cdt.rz.Release.Compiler.option.architecture=armv7-r +com.renesas.cdt.rz.Release.Compiler.option.cpuType=cortex-r4f +com.renesas.cdt.rz.Release.Compiler.option.cpuType.963183599=cortex-r4f +com.renesas.cdt.rz.Release.Compiler.option.dataEndian=Little-endian +com.renesas.cdt.rz.Release.Compiler.option.floatingpointabi=Soft +com.renesas.cdt.rz.Release.Compiler.option.instructionset=ARM +com.renesas.cdt.rz.Release.Compiler.option.interworking=true +com.renesas.cdt.rz.Release.Compiler.option.macroDefines= +com.renesas.cdt.rz.Release.Compiler.option.targetfpu=vfp +com.renesas.cdt.rz.Release.Linker.option.archiveLibraryFiles=${BuildArtifactFileBaseName};gcc; +com.renesas.cdt.rz.Release.Linker.option.archiveSearchDirectories.966751407="${TCINSTALL}/lib/gcc/arm-none-eabi/${GCC_VERSION}/interwork";"${TCINSTALL}/arm-none-eabi/lib/interwork"; +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.settings/language.settings.xml b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.settings/language.settings.xml new file mode 100644 index 000000000..546c39b1e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/.settings/language.settings.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.jlink b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.jlink new file mode 100644 index 000000000..1ca0b4000 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.jlink @@ -0,0 +1,35 @@ +[BREAKPOINTS] +ForceImpTypeAny = 0 +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 0 +Device="UNSPECIFIED" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..f652b92fd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo HardwareDebug.launch @@ -0,0 +1,87 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..18d232e4a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewd @@ -0,0 +1,2741 @@ + + + + 2 + + Debug + + ARM + + 1 + + C-SPY + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 1 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 1 + + + + + + + + + + + + CMSISDAP_ID + 2 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$TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..d10d23c8d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.ewp @@ -0,0 +1,2095 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 1 + + + + + + + + + + + + + + + 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3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Blinky Demo + + $PROJ_DIR$\src\Blinky_Demo\main_blinky.c + + + + FreeRTOS_Source + + portable + + MemMang + + IAR + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CRx_No_GIC\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CRx_No_GIC\portASM.s + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CRx_No_GIC\portmacro.h + + + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + + + + + $PROJ_DIR$\..\..\Source\event_groups.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\Source\timers.c + + + + Full_Demo + + Common Demo Tasks + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\blocktim.c + + + $PROJ_DIR$\..\Common\Minimal\comtest.c + + + $PROJ_DIR$\..\Common\Minimal\countsem.c + + + $PROJ_DIR$\..\Common\Minimal\death.c + + + $PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c + + + $PROJ_DIR$\..\Common\Minimal\flop.c + + + $PROJ_DIR$\..\Common\Minimal\GenQTest.c + + + $PROJ_DIR$\..\Common\Minimal\IntQueue.c + + + $PROJ_DIR$\..\Common\Minimal\IntSemTest.c + + + $PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c + + + $PROJ_DIR$\..\Common\Minimal\recmutex.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\..\Common\Minimal\TaskNotify.c + + + $PROJ_DIR$\..\Common\Minimal\TimerDemo.c + + + + $PROJ_DIR$\src\Full_Demo\IntQueueTimer.c + + + $PROJ_DIR$\src\Full_Demo\main_full.c + + + $PROJ_DIR$\src\Full_Demo\reg_test_IAR.asm + + + + Renesas_cg_src + + $PROJ_DIR$\src\cg_src\r_cg_cgc_user.c + + + $PROJ_DIR$\src\cg_src\r_cg_cmt_user.c + + + $PROJ_DIR$\src\cg_src\r_cg_icu.c + + + $PROJ_DIR$\src\cg_src\r_cg_icu_user.c + + + $PROJ_DIR$\src\cg_src\r_cg_intprg.c + + + $PROJ_DIR$\src\cg_src\r_cg_port.c + + + $PROJ_DIR$\src\cg_src\r_cg_port_user.c + + + $PROJ_DIR$\src\cg_src\r_cg_rspi.c + + + $PROJ_DIR$\src\cg_src\r_cg_rspi_user.c + + + $PROJ_DIR$\src\cg_src\r_cg_systeminit.c + + + $PROJ_DIR$\src\cg_src\r_cg_tpu.c + + + $PROJ_DIR$\src\cg_src\r_cg_tpu_user.c + + + + System + + $PROJ_DIR$\System\IAR\src\exit.c + + + $PROJ_DIR$\System\IAR\src\loader_init.asm + + + $PROJ_DIR$\System\IAR\src\loader_init2.c + + + $PROJ_DIR$\System\IAR\src\r_atcm_init.c + + + $PROJ_DIR$\System\IAR\src\r_cpg.c + + + $PROJ_DIR$\System\IAR\src\r_ecm.c + + + $PROJ_DIR$\System\IAR\src\r_icu_init.c + + + $PROJ_DIR$\System\IAR\src\r_ram_init.c + + + $PROJ_DIR$\System\IAR\src\r_reset.c + + + $PROJ_DIR$\System\IAR\src\vector.asm + + + + $PROJ_DIR$\src\FreeRTOS_tick_config.c + + + $PROJ_DIR$\src\FreeRTOSConfig.h + + + $PROJ_DIR$\System\IAR\Interrupt_Entry_Stubs.asm + + + $PROJ_DIR$\src\main.c + + + $PROJ_DIR$\src\cg_src\r_cg_cgc.c + + + $PROJ_DIR$\src\cg_src\r_cg_mpc.c + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/GNU_LINKER_ATCM.ld b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/GNU_LINKER_ATCM.ld new file mode 100644 index 000000000..1ec9c36d4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/GNU_LINKER_ATCM.ld @@ -0,0 +1,215 @@ +/**************************************************************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +****************************************************************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : GNU_LINKER_ATCM.ld +* Device(s) : RZ/T1 (R7S910018) +* Tool-Chain : GNUARM-NONEv14.02-EABI +* H/W Platform : RSK+RZT1 CPU Board +* Description : Linker file for projects that require to load and run from RAM (ATCM) +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 +***********************************************************************************************************************/ +OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(start) + +/* Base Address RAM Memory Table 1 Mbyte on-chip RAM */ +MEMORY +{ + /* Internal RAM address range H'2000_0000 to H'2001_FFFF is configured as data retention RAM */ + /* Write access to this address range has to be enabled by writing to registers SYSCR1 and SYSCR2 */ + ATCM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* (512KB) H'00000000 to H'0007FFFF */ + BTCM (rwx) : ORIGIN = 0x00800000, LENGTH = 0x00800000 /* (32KB) H'00800000 to H'00807FFF */ + BUFFER_RAM (rwx) : ORIGIN = 0x20200000, LENGTH = 0x00100000 /* (1024KB) H'08000000 to H'0FFFFFFF */ + DATA_RAM0 (rwx) : ORIGIN = 0x24000000, LENGTH = 0x00080000 /* (512KB) H'22000000 to H'2207FFFF */ + DATA_RAM1 (rwx) : ORIGIN = 0x22000000, LENGTH = 0x00080000 /* (512KB) H'24000000 to H'2407FFFF */ + + SPIBSC (rw) : ORIGIN = 0x30000000, LENGTH = 0x04000000 /* attached to H'30000000 to H'33FFFFFF */ + CS0 (rw) : ORIGIN = 0x40000000, LENGTH = 0x04000000 /* attached to H'40000000 to H'43FFFFFF */ + CS1 (rw) : ORIGIN = 0x44000000, LENGTH = 0x04000000 /* attached to H'44000000 to H'47FFFFFF */ + CS2 (rw) : ORIGIN = 0x48000000, LENGTH = 0x04000000 /* attached to H'40000000 to H'4CFFFFFF */ + CS3 (rw) : ORIGIN = 0x4C000000, LENGTH = 0x04000000 /* attached to H'4C000000 to H'4FFFFFFF */ + CS4 (rw) : ORIGIN = 0x50000000, LENGTH = 0x04000000 /* attached to H'50000000 to H'53FFFFFF */ + CS5 (rw) : ORIGIN = 0x54000000, LENGTH = 0x04000000 /* attached to H'54000000 to H'57FFFFFF */ + + /* Mapped memory type */ + SPI_ROM (rw) : ORIGIN = 0x30000000, LENGTH = 0x04000000 + CS0_ROM (rw) : ORIGIN = 0x40000000, LENGTH = 0x04000000 + CS1_ROM (rw) : ORIGIN = 0x44000000, LENGTH = 0x04000000 + SDRAM0_EXT (rw) : ORIGIN = 0x48000000, LENGTH = 0x04000000 + SDRAM1_EXT (rw) : ORIGIN = 0x4C000000, LENGTH = 0x04000000 +} + +SYS_STACK_SIZE = 0x200; /* Application stack size */ +SVC_STACK_SIZE = 0x200; /* SVC mode stack */ +IRQ_STACK_SIZE = 0x200; /* IRQ mode stack */ +FIQ_STACK_SIZE = 0x200; /* FRQ mode stack */ +UND_STACK_SIZE = 0x200; /* SVC mode stack */ +ABT_STACK_SIZE = 0x200; /* ABT mode stack */ +HEAP_STACK_SIZE = 0x1000; /* Heap stack size */ + +ATCM_BASE = 0x00000000; /* User application located here */ +BTCM_BASE = 0x00800000; /* BTCM base address */ + +USER_EXEC_BASE = 0x00000000; /* Application loads and runs from here */ + +USER_RAM = 0x20000000; /* Application's RAM base */ + +STACK_BASE = 0x00807800; /* Stacks located in BTCM */ + +SDRAM0_BASE = 0x48000000; /* SDRAM1 is attached to CS2 space */ +SDRAM1_BASE = 0x4C000000; /* SDRAM1 is attached to CS3 space */ + +SECTIONS +{ + .reset USER_EXEC_BASE : + { + reset_start = .; + execute = .; + _intvec_start = .; + *start.o (.text); + . = ALIGN(0x4); + _intvec_end = .; + end_reset = .; + } > ATCM + + .text : + { + text_start = .; + *(.text) + *(.text.startup) + text_end = .; + } > ATCM + + .rodata : + { + _rodata_start = .; + *(.rodata) + *(.rodata.*) + . = ALIGN(0x8); + _start_data_ROM = .; + *(.data) + *(.data.*) + _end_data_ROM = .; + *(.got.plt) + *(.got) + . = ALIGN(0x8); + _rodata_end = .; + PROVIDE(end = .); + } > ATCM + + _ram_data_size = (_end_data_ROM - _start_data_ROM); + + .data USER_RAM : + { + _data_start = .; + _start_data_RAM = .; + . += _ram_data_size; + _data_end = .; + } + + .bss _data_end : + { + _bss = .; + PROVIDE(__bss_start__ = .); + *(.bss) + *(.bss.**) + *(COMMON) + . = ALIGN(0x4); + PROVIDE(__bss_end__ = .); + _ebss = .; + _end = .; + PROVIDE(end = .); + } + + .heap : + { + heap_start = .; + . = ALIGN(0x8); + *(.heap_stack) + . += HEAP_STACK_SIZE; + heap_end = .; + } > ATCM + + .sys_stack STACK_BASE : + { + sys_stack_start = .; + . = ALIGN(0x8); + *(.sys_stack) + . += SYS_STACK_SIZE; + sys_stack_end = .; + } > BTCM + + .svc_stack sys_stack_end : + { + svc_stack_start = .; + . = ALIGN(0x8); + *(.svc_stack) + . += SVC_STACK_SIZE; + svc_stack_end = .; + } > BTCM + + .irq_stack svc_stack_end : + { + irq_stack_start = .; + . = ALIGN(0x8); + *(.irq_stack) + . += IRQ_STACK_SIZE; + irq_stack_end = .; + } > BTCM + + .fiq_stack irq_stack_end : + { + fiq_stack_start = .; + . = ALIGN(0x8); + *(.fiq_stack) + . += FIQ_STACK_SIZE; + fiq_stack_end = .; + } > BTCM + + .und_stack fiq_stack_end : + { + und_stack_start = .; + . = ALIGN(0x8); + *(.und_stack) + . += UND_STACK_SIZE; + und_stack_end = .; + } > BTCM + + .abt_stack und_stack_end : + { + abt_stack_start = .; + . = ALIGN(0x8); + *(.abt_stack) + . += ABT_STACK_SIZE; + abt_stack_end = .; + } > BTCM + + /* NOLOAD directs linker NOT to fill VRAMx_SECTION with 0. */ + /* Usage of NOLOAD increases speed of linker and download to target */ + .sdram0_section SDRAM0_BASE (NOLOAD) : {} > SDRAM0_EXT + .sdram1_section SDRAM1_BASE (NOLOAD) : {} > SDRAM1_EXT +} \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/loader_init.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/loader_init.asm new file mode 100644 index 000000000..3d1265b21 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/loader_init.asm @@ -0,0 +1,351 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* System Name : RZ/T1 Init program +* File Name : loader_init.asm +* Version : 0.1 +* Device : R7S910018 +* Abstract : Loader program 1 +* Tool-Chain : GNUARM-NONEv14.02-EABI +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1 +* Description : System low level configuration. +* Limitation : none +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.04.2015 1.00 First Release +***********************************************************************************************************************/ + + .text + .code 32 + + .global reset_handler + .global loader_init1 + .global set_low_vec + .global cache_init + .global mpu_init + .global loader_init2 + .global r_icu_nmi_interrupt + + + reset_handler: + +/*********************************************************************************************************************** +* Function Name : loader_init1 +* Description : Initialize system by loader program +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +loader_init1: + +/* ========================================================================= */ +/* Multi-core startup (future proofing boot code) */ +/* Check core, if not core 0 put to sleep. */ +/* ========================================================================= */ + mrc p15, 0, r0, c0, c0, 5 /* Read MPIDR */ + ands r0, r0, #3 +goToSleep: + wfine + bne goToSleep + + mrs r0, cpsr /* Disalbe FIQ and IRQ */ + orr r0, r0, #0x000000C0 + msr cpsr, r0 + isb + +stack_init: + /* Stack setting */ + cps #17 /* FIQ mode */ + ldr sp, =fiq_stack_end + cps #18 /* IRQ mode */ + ldr sp, =irq_stack_end + cps #23 /* Abort mode */ + ldr sp, =abt_stack_end + cps #27 /* Undef mode */ + ldr sp, =und_stack_end + cps #31 /* System mode */ + ldr sp, =sys_stack_end + cps #19 /* SVC mode */ + ldr sp, =svc_stack_end + +vfp_init: + /* Initialize VFP setting */ + mrc p15, #0, r0, c1, c0, #2 /* Enables cp10 and cp11 accessing */ + orr r0, r0, #0xF00000 + mcr p15, #0, r0, c1, c0, #2 + isb /* Ensuring Context-changing */ + + mov r0, #0x40000000 /* Enables VFP operation */ + vmsr fpexc, r0 + + mrc p15, 0, r0, c1, c0, 0 /* Set SCTLR.VE bit to 1 (Use VIC) */ + orr r0, r0, #0x01000000 + mcr p15, 0, r0, c1, c0, 0 + isb /* Ensuring Context-changing */ + + mrc p15, 0, r0, c1, c0, 1 /* Enalbe ECC */ + orr r0, r0, #0x06000000 + mcr p15, 0, r0, c1, c0, 1 + isb /* Ensuring Context-changing */ + + mrs r0, cpsr /* Re-enalbe FIQ */ + and r0, r0, #0xFFFFFFBF + msr cpsr, r0 + isb + + /* Jump to loader_init2 */ +jump_loader_init2: + ldr r0, =loader_init2 + bx r0 + +/*********************************************************************************************************************** +* Function Name : cache_init +* Description : Initialize I1, D1 cache and MPU settings +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Macro definitions +***********************************************************************************************************************/ + +.equ SCTLR_BR, 0x00020000 +.equ SCTLR_M, 0x00000001 +.equ SCTLR_I_C, 0x00001004 + +.equ DRBAR_REGION_0, 0x04000000 /*Base address = 0400_0000h */ +.equ DRACR_REGION_0, 0x0000030C /*R/W(full), Normal, Non-cache, share */ +.equ DRSR_REGION_0, 0x00000025 /*Size 512KB, MPU enable */ + +.equ DRBAR_REGION_1, 0x10000000 /*Base address = 1000_0000h */ +.equ DRACR_REGION_1, 0x0000030C /*R/W(full), Normal, Non-cache, share */ +.equ DRSR_REGION_1, 0x00000033 /*Size 64MB, MPU enable */ + +.equ DRBAR_REGION_2, 0x20000000 /*Base address = 2000_0000h */ +.equ DRACR_REGION_2, 0x0000030C /*R/W(full), Normal, Non-cache, share */ +.equ DRSR_REGION_2, 0x00000025 /*Size 512KB, MPU enable */ + +.equ DRBAR_REGION_3, 0x22000000 /*Base address = 2200_0000h */ +.equ DRACR_REGION_3, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */ +.equ DRSR_REGION_3, 0x00000033 /*Size 64MB, MPU enable */ + +.equ DRBAR_REGION_4, 0x30000000 /*Base address = 3000_0000h */ +.equ DRACR_REGION_4, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */ +.equ DRSR_REGION_4, 0x00000033 /*Size 64MB, MPU enable */ + +.equ DRBAR_REGION_5, 0x40000000 /*Base address = 4000_0000h */ +.equ DRACR_REGION_5, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */ +.equ DRSR_REGION_5, 0x00000035 /*Size 128MB, MPU enable */ + +.equ DRBAR_REGION_6, 0x48000000 /*Base address = 4800_0000h */ +.equ DRACR_REGION_6, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */ +.equ DRSR_REGION_6, 0x00000035 /*Size 128MB, MPU enable */ + +.equ DRBAR_REGION_7, 0x50000000 /*Base address = 5000_0000h */ +.equ DRACR_REGION_7, 0x00001305 /*R/W(full), XN, Device, share */ +.equ DRSR_REGION_7, 0x00000035 /*Size 128MB, MPU enable */ + +.equ DRBAR_REGION_8, 0x60000000 /*Base address = 6000_0000h */ +.equ DRACR_REGION_8, 0x0000030C /*R/W(full), Normal, Non-cache, share */ +.equ DRSR_REGION_8, 0x00000035 /*Size 128MB, MPU enable */ + +.equ DRBAR_REGION_9, 0x68000000 /*Base address = 6800_0000h */ +.equ DRACR_REGION_9, 0x0000030C /*R/W(full), Normal, Non-cache, share */ +.equ DRSR_REGION_9, 0x00000035 /*Size 128MB, MPU enable */ + +.equ DRBAR_REGION_10, 0x70000000 /*Base address = 7000_0000h */ +.equ DRACR_REGION_10, 0x00001305 /*R/W(full), XN, Device, share */ +.equ DRSR_REGION_10, 0x00000035 /*Size 128MB, MPU enable */ + +.equ DRBAR_REGION_11, 0x80000000 /*Base address = 8000_0000h */ +.equ DRACR_REGION_11, 0x00001305 /*R/W(full), XN, Device, share */ +.equ DRSR_REGION_11, 0x0000003D /*Size 2GB, MPU enable */ + +cache_init: + push {lr} + +cache_invalidate: + /*Invalidate the I1, D1 cache */ + mov r0, #0 + mcr p15, #0, r0, c7, c5, #0 /*Invalidate all Instruction Caches (Write-value is Ignored) */ + isb /*Ensuring Context-changing */ + mcr p15, #0, r0, c15, c5, #0 /*Invalidate all Data Caches (Write-value is Ignored) */ + isb /*Ensuring Context-changing */ + + /*Adopt default memory map as background map. */ + ldr r0, =SCTLR_BR /*Set SCTLR.BR bit to 1 */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, r0 + dsb + mcr p15, 0, r1, c1, c0, 0 + isb /*Ensuring Context-changing */ + + /*Initialize MPU settings (region 0 to 11) */ + /*Define region 0 */ + mov r0, #0 + ldr r1, =DRBAR_REGION_0 + ldr r2, =DRACR_REGION_0 + ldr r3, =DRSR_REGION_0 + bl mpu_init + + /*Define region 1 */ + mov r0, #1 + ldr r1, =DRBAR_REGION_1 + ldr r2, =DRACR_REGION_1 + ldr r3, =DRSR_REGION_1 + bl mpu_init + + /*Define region 2 */ + mov r0, #2 + ldr r1, =DRBAR_REGION_2 + ldr r2, =DRACR_REGION_2 + ldr r3, =DRSR_REGION_2 + bl mpu_init + + /*Define region 3 */ + mov r0, #3 + ldr r1, =DRBAR_REGION_3 + ldr r2, =DRACR_REGION_3 + ldr r3, =DRSR_REGION_3 + bl mpu_init + + /*Define region 4 */ + mov r0, #4 + ldr r1, =DRBAR_REGION_4 + ldr r2, =DRACR_REGION_4 + ldr r3, =DRSR_REGION_4 + bl mpu_init + + /*Define region 5 */ + mov r0, #5 + ldr r1, =DRBAR_REGION_5 + ldr r2, =DRACR_REGION_5 + ldr r3, =DRSR_REGION_5 + bl mpu_init + + /*Define region 6 */ + mov r0, #6 + ldr r1, =DRBAR_REGION_6 + ldr r2, =DRACR_REGION_6 + ldr r3, =DRSR_REGION_6 + bl mpu_init + + /*Define region 7 */ + mov r0, #7 + ldr r1, =DRBAR_REGION_7 + ldr r2, =DRACR_REGION_7 + ldr r3, =DRSR_REGION_7 + bl mpu_init + + /*Define region 8 */ + mov r0, #8 + ldr r1, =DRBAR_REGION_8 + ldr r2, =DRACR_REGION_8 + ldr r3, =DRSR_REGION_8 + bl mpu_init + + /*Define region 9 + mov r0, #9 */ + ldr r1, =DRBAR_REGION_9 + ldr r2, =DRACR_REGION_9 + ldr r3, =DRSR_REGION_9 + bl mpu_init + + /*Define region 10 */ + mov r0, #10 + ldr r1, =DRBAR_REGION_10 + ldr r2, =DRACR_REGION_10 + ldr r3, =DRSR_REGION_10 + bl mpu_init + + /*Define region 11 */ + mov r0, #11 + ldr r1, =DRBAR_REGION_11 + ldr r2, =DRACR_REGION_11 + ldr r3, =DRSR_REGION_11 + bl mpu_init + + /*Enables MPU operation */ + ldr r0, =SCTLR_M /*Set SCTLR.M bit to 1 */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, r0 + dsb + mcr p15, 0, r1, c1, c0, 0 + isb /*Ensuring Context-changing */ + + /*Enables I1,D1 cache operation */ + ldr r0, =SCTLR_I_C /*Set SCTLR.I and C bit to 1 */ + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, r0 + dsb + mcr p15, 0, r1, c1, c0, 0 + isb /*Ensuring Context-changing */ + + pop {pc} + bx lr + +/*********************************************************************************************************************** +* Function Name : mpu_init +* Description : Initialize MPU settings +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +mpu_init: + /*RGNR(MPU Memory Region Number Register) */ + mcr p15, #0, r0, c6, c2, #0 + isb /*Ensuring Context-changing */ + + /*DRBAR(Data Region Base Address Register) */ + mcr p15, #0, r1, c6, c1, #0 + isb /*Ensuring Context-changing */ + + /*DRACR(Data Region Access Control Register) */ + mcr p15, #0, r2, c6, c1, #4 + isb /*Ensuring Context-changing */ + + /*DRSR(Data Region Size and Enable Register) */ + mcr p15, #0, r3, c6, c1, #2 + isb /*Ensuring Context-changing */ + + bx lr + + +/*********************************************************************************************************************** +* Function Name : set_low_vec +* Description : Initialize sysytem by loader program +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +set_low_vec: + mrc p15, 0, r0, c1, c0, 0 /*Set SCTLR.V bit to 1 (low-vector)*/ + and r0, r0, #0xFFFFDFFF + mcr p15, 0, r0, c1, c0, 0 + isb /*Ensuring Context-changing*/ + + bx lr + + .end + +/*End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/start.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/start.asm new file mode 100644 index 000000000..6bbbc9af1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/start.asm @@ -0,0 +1,70 @@ +/************************************************************************************************************************ +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +************************************************************************************************************************/ +/************************************************************************************************************************ +* File Name : start.asm +* Device(s) : RZ/T1 (R7S910018) +* Tool-Chain : GNUARM-NONEv14.02-EABI +* H/W Platform : RSK+T1 CPU Board +* Description : This is the code to be executed on the target + The copyright string signifies the end of the Vector table +* Note boot strap sequence is as follows: +* +* start->reset_handler->main() +* +* start - first code to be executed on the target + start jumps to reset_handler the asm startup routine +* reset_handler jumps to loader_init1() C entry point +* loader_init2() calls main() C User code entry point +************************************************************************************************************************/ +/************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 +************************************************************************************************************************/ + + .text + .code 32 + + .extern FreeRTOS_SVC_Handler + .global start + .func start + +start: + LDR pc, =reset_handler /* Reset Vector */ + LDR pc, =undefined_handler + LDR pc, =FreeRTOS_SVC_Handler + LDR pc, =prefetch_handler + LDR pc, =abort_handler + LDR pc, =reserved_handler + LDR pc, =irq_handler + LDR pc, =fiq_handler +code_start: + .word start /* pointer to the user application start address */ + /* Used by NOR and SPI (System_Boot_Loader_xxxx) */ +code_end: + .word end +code_execute: + .word execute /* execute address of first instruction */ + .string ".BootLoad_ValidProgramTest." /* bootloader validation signature */ + .align 4 + .end diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/vector.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/vector.asm new file mode 100644 index 000000000..3725c0cf0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/asm/vector.asm @@ -0,0 +1,76 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + System Name : RZ/T1 Init program + File Name : vector.asm + Version : 0.1 + Device : R7S910018 + Abstract : vector address (in low vector) + Tool-Chain : GNUARM-NONEv14.02-EABI + OS : not use + H/W Platform : Renesas Starter Kit for RZ/T1 + Description : vector address for RZ/T1 (in low vector) + Limitation : none +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 First Release +***********************************************************************************************************************/ + +/* This program is allocated to section "intvec" */ + + .text + .code 32 + + .global undefined_handler + .global prefetch_handler + .global abort_handler + .global reserved_handler + .global irq_handler + .global fiq_handler + + +undefined_handler: + b undefined_handler + +svc_handler: + b svc_handler + +prefetch_handler: + b prefetch_handler + +abort_handler: + b abort_handler + +reserved_handler: + b reserved_handler + +irq_handler: + b irq_handler + +fiq_handler: + b fiq_handler + + .end + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/ascii.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/ascii.h new file mode 100644 index 000000000..40dc3d8ca --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/ascii.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +************************************************************************************************************************/ +/************************************************************************************************************************ +* File Name : ascii.h +* Device(s) : RZ/T1 (R7S910018) +* Tool-Chain : GNUARM-NONEv14.02-EABI +* H/W Platform : RSK+RZT1 CPU Board +* Description : This Header file contains the Macro Definitions & prototypes +* for the functions used in lcd.c +************************************************************************************************************************/ +/************************************************************************************************************************ +* History : DD.MM.YYYY Version Description +* : 21.04.2015 1.00 +************************************************************************************************************************/ + +/* Multiple inclusion prevention macro */ +#ifndef ASCII_H +#define ASCII_H + +/*********************************************************************************************************************** +Macro Definitions +***********************************************************************************************************************/ +extern const char g_ascii_table[][6]; + +/* ASCII_H */ +#endif + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/compiler_settings.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/compiler_settings.h new file mode 100644 index 000000000..b2e196987 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/compiler_settings.h @@ -0,0 +1,65 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +************************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : compiler_settings.h +* Device(s) : RZ/A1H (R7S910018) +* Tool-Chain : GNUARM-NONEv14.02-EABI +* H/W Platform : RSK+T1 CPU Board +* Description : Any compiler specific settings are stored here. +* : Variants of this file must be created for each compiler +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +/* Compiler specific UART i/O support header */ +#include "../../GCC/inc/gnu_io.h" + +#ifndef COMPILER_SETTINGS_H +#define COMPILER_SETTINGS_H + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Definitions of SDRAM sections from the linker */ +#define BSS_SDRAM0_SECTION __attribute__ ((section (".sdram0_section"))) +#define BSS_SDRAM1_SECTION __attribute__ ((section (".sdram1_section"))) + +/*********************************************************************************************************************** +Variable External definitions and Function External definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Functions Prototypes +***********************************************************************************************************************/ + +/* COMPILER_SETTINGS_H */ +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/gnu_io.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/gnu_io.h new file mode 100644 index 000000000..9a5be86f7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/gnu_io.h @@ -0,0 +1,68 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/****************************************************************************** +* File Name : gnu_io.h +* Device(s) : RZ/A1H (R7S910018) +* Tool-Chain : GNUARM-NONEv14.02-EABI +* H/W Platform : RSK+T1 CPU Board +* Description : GCC support for serial I/O header file +******************************************************************************/ +/****************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 +******************************************************************************/ + +#ifndef GNU_IO_H +#define GNU_IO_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + +extern void put_string(char *pString); +extern void get_string(char *pString); + + +#endif /* GNU_IO_H */ + +/* End of File */ + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/lcd_pmod.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/lcd_pmod.h new file mode 100644 index 000000000..7dc1aadf0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/lcd_pmod.h @@ -0,0 +1,227 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : lcd_pmod.h +* Device(s) : RZ/T1 (R7S910017) +* Tool-Chain : GNUARM-NONEv14.02-EABI +* H/W Platform : RSK+RZT1 CPU Board +* +* Description : This Header file contains the Macro Definitions & prototypes +* for the functions used in lcd.c +* +* This function is created to drive the Okaya LCD display with +* either ST7735 or ST7715 driver device. The commands for both +* the devices are the same. +* +* The display is controlled using the SPI bus. In this example, +* the SCI5 is used. This can be modified to the SCI connected to +* the PMOD interface. The SCI driver file will also be required. +* +* The display memory has an offset with respect to the actual +* pixel. This is not documented but realised from driving the +* display. The offset is set as LEFT MARGIN and TOP MARGIN. +* This offset is catered for internally, so as far as the user +* is concerned, cursor position 0,0 is the top left pixel. +* +* The simplest procedure to run the display is as follows: +* Init_LCD(); Initialise the serial port and set up the display. +* +* Clear the display. +* The font colour is set to white and background colour to black. +* +* DisplaySetFontColour(COL_YELLOW); +* set the font colour to desired colour +* DisplaySetBackColour(COL_BLUE); +* set the background colour to desired value +* DisplayCenter(1,"Renesas"); +* write a title on line 1 of the display. +* +* Note: Line 0 is the top line. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.04.2015 1.00 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +User Includes (Project Level Includes) +***********************************************************************************************************************/ +/* Defines standard variable types used in this file */ +#include +#include "iodefine.h" + +/*********************************************************************************************************************** +Macro Definitions +***********************************************************************************************************************/ +/* Multiple inclusion prevention macro */ +#ifndef LCD_PMOD_H +#define LCD_PMOD_H + + +/*********************************************************************************************************************** +Macro Definitions for Okaya display on PMOD connector +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +* SCREEN +* +* The screen size is 128 x 128 pixels, with coordinate 0,0 at the top left. +* The display controller is ST7735 or ST7715. +* +***********************************************************************************************************************/ +/* 16 lines @ 8 bits = 128. */ +#define SCREEN_HEIGHT (128) +#define SCREEN_WIDTH (128) + +#ifndef USE_PMOD2 +/* DATA/COMMAND select pin */ +#define DATA_CMD_PIN (PORT7.PODR.BIT.B6) +/* Backlight enable pin */ +#define BL_ENABLE_PIN (PORT7.PODR.BIT.B4) +/* Reset pin */ +#define RESET_PIN (PORT6.PODR.BIT.B7) +#else +/* DATA/COMMAND select pin */ +#define DATA_CMD_PIN (PORTM.PODR.BIT.B2) +/* Backlight enable pin */ +#define BL_ENABLE_PIN (PORTM.PODR.BIT.B3) +/* Reset pin */ +#define RESET_PIN (PORT5.PODR.BIT.B1) +#endif + +/* Automatic calculation of parameters */ + + /* including a space */ +#define FONT_WIDTH (6u) +/* including 1 pixel space */ +#define FONT_HEIGHT (8u) +#define MAX_LINES (SCREEN_HEIGHT / FONT_HEIGHT) +#define CHAR_PER_LINE (SCREEN_WIDTH / FONT_WIDTH) + +/* Allow 2 pixel margin on the left and the top */ +#define LEFT_MARGIN (2u) +#define TOP_MARGIN (3u) +#define CR (0x0d) +#define LF (0x0a) +#define BS (0x08) + + +/*********************************************************************************************************************** +* DISPLAY COLOUR DEFINITIONS (16 bits) R5G6B5 format +* +* Only Primary & secondary colours are defined here. Other colours can be +* created using RGB values. +***********************************************************************************************************************/ +#define COL_BLACK (0x0000) +#define COL_RED (0xF800) +#define COL_GREEN (0x07E0) +#define COL_BLUE (0x001F) +#define COL_YELLOW (0xFFE0) +#define COL_CYAN (0x07FF) +#define COL_MAGENTA (0xF81F) +#define COL_WHITE (0xFFFF) + +/*********************************************************************************************************************** + + DISPLAY COMMAND SET ST7735 + +***********************************************************************************************************************/ +#define ST7735_NOP (0x0) +#define ST7735_SWRESET (0x01) +#define ST7735_SLPIN (0x10) +#define ST7735_SLPOUT (0x11) +#define ST7735_PTLON (0x12) +#define ST7735_NORON (0x13) +#define ST7735_INVOFF (0x20) +#define ST7735_INVON (0x21) +#define ST7735_DISPOFF (0x28) +#define ST7735_DISPON (0x29) +#define ST7735_CASET (0x2A) +#define ST7735_RASET (0x2B) +#define ST7735_RAMWR (0x2C) +#define ST7735_COLMOD (0x3A) +#define ST7735_MADCTL (0x36) +#define ST7735_FRMCTR1 (0xB1) +#define ST7735_INVCTR (0xB4) +#define ST7735_DISSET5 (0xB6) +#define ST7735_PWCTR1 (0xC0) +#define ST7735_PWCTR2 (0xC1) +#define ST7735_PWCTR3 (0xC2) +#define ST7735_VMCTR1 (0xC5) +#define ST7735_PWCTR6 (0xFC) +#define ST7735_GMCTRP1 (0xE0) +#define ST7735_GMCTRN1 (0xE1) + +/* delay for delay counter */ +#define DELAY_TIMING (0x08) + +/*********************************************************************************************************************** +* Function Prototypes +***********************************************************************************************************************/ +/* Initialises the debug LCD */ +void lcd_init (void); + +/* Display string at specific line of display */ +void display_lcd (uint8_t const line, uint8_t const column, uint8_t const * string); + +/* Display the string at current cursor position */ +void display_str (uint8_t const * str); + +/* Display the sting at the centre of the specified line */ +void display_center (uint8_t const line_num, uint8_t * const str); + +/* Clears the display */ +void clear_display (uint16_t colour); + +/* Clear a specified line */ +void display_clear_line(uint8_t line_num); + +/* Set the current cursor position */ +void display_set_cursor (uint8_t const x, uint8_t const y); + +/* Delay function */ +void display_delay_us (uint32_t time_us); +void display_delay_ms (uint32_t time_ms); + +/* Set Font colour */ +void display_set_font_colour (uint16_t const col); + +/* Set Background colour */ +void display_set_back_colour (uint16_t const col); + +/* Simple image blit */ +void display_image (uint8_t *image, uint8_t image_width, + uint8_t image_height, uint8_t loc_x, uint8_t loc_y); + +/* Enable display */ +void display_on (void); + +/* Disable display */ +void display_off (void); + + +/* LCD_PMOD_H */ +#endif + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/logo_data.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/logo_data.h new file mode 100644 index 000000000..3971e8950 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/logo_data.h @@ -0,0 +1,44 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/****************************************************************************** +* File Name : logo_data.h +* Device(s) : RZ/A1H (R7S910018) +* Tool-Chain : GNUARM-NONEv14.02-EABI +* H/W Platform : RSK+T1 CPU Board +* Description : Renesas Logo 128*24 pixels +******************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.10.2014 1.00 +***********************************************************************************************************************/ + +/* Multiple inclusion prevention macro */ +#ifndef LOGO_DATA_H +#define LOGO_DATA_H + +/* Declare the image data section */ +extern const uint8_t g_rgb888_logo[]; + +/* LOGO_DATA_H */ +#endif diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_atcm_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_atcm_init.h new file mode 100644 index 000000000..f202d4744 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_atcm_init.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* System Name : RZ/T1 Init program +* File Name : r_atcm.h +* Version : 0.1 +* Device : R7S910018 +* Abstract : API for ATCM function +* Tool-Chain : GNUARM-NONEv14.02-EABI +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : ATCM access wait setting API of RZ/T1 +* Limitation : none +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 First Release +***********************************************************************************************************************/ + +#ifndef _R_ATCM_HEADER_ +#define _R_ATCM_HEADER_ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define ATCM_WAIT_1_OPT (0) +#define ATCM_WAIT_1 (1) +#define ATCM_WAIT_0 (2) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables and functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_ATCM_WaitSet(uint32_t atcm_wait); + + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_bsc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_bsc.h new file mode 100644 index 000000000..998216ca1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_bsc.h @@ -0,0 +1,186 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* System Name : RZ/T1 Init program +* File Name : r_bsc.h +* Version : 0.1 +* Device : R7S910018 +* Abstract : Definitions for BSC functions +* Tool-Chain : GNUARM-NONEv14.02-EABI +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : BSC setting API of RZ/T1 +* Limitation : none +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 First Release +***********************************************************************************************************************/ + +#ifndef _R_BSC_HEADER_ +#define _R_BSC_HEADER_ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define BSC_IDLE_CYCLE_0 (0) +#define BSC_IDLE_CYCLE_1 (1) +#define BSC_IDLE_CYCLE_2 (2) +#define BSC_IDLE_CYCLE_4 (3) +#define BSC_IDLE_CYCLE_6 (4) +#define BSC_IDLE_CYCLE_8 (5) +#define BSC_IDLE_CYCLE_10 (6) +#define BSC_IDLE_CYCLE_12 (7) + +#define BSC_TYPE_NORMAL (0) +#define BSC_TYPE_BURST_ROM_ASYNC (1) +#define BSC_TYPE_MPX_IO (2) +#define BSC_TYPE_SRAM_BYTE (3) +#define BSC_TYPE_SDRAM (4) +#define BSC_TYPE_BURST_ROM_SYNC (7) + +#define BSC_WIDTH_8_BIT (1) +#define BSC_WIDTH_16_BIT (2) +#define BSC_WIDTH_32_BIT (3) + +#define BSC_DELAY_STATE_CYCLE_0_5 (0) +#define BSC_DELAY_STATE_CYCLE_1_5 (1) +#define BSC_DELAY_STATE_CYCLE_2_5 (2) +#define BSC_DELAY_STATE_CYCLE_3_5 (3) + +#define BSC_EXT_WAIT_VALID (0) +#define BSC_EXT_WAIT_IGNORED (1) + +#define BSC_ACCESS_WAIT_0 (0) +#define BSC_ACCESS_WAIT_1 (1) +#define BSC_ACCESS_WAIT_2 (2) +#define BSC_ACCESS_WAIT_3 (3) +#define BSC_ACCESS_WAIT_4 (4) +#define BSC_ACCESS_WAIT_5 (5) +#define BSC_ACCESS_WAIT_6 (6) +#define BSC_ACCESS_WAIT_8 (7) +#define BSC_ACCESS_WAIT_10 (8) +#define BSC_ACCESS_WAIT_12 (9) +#define BSC_ACCESS_WAIT_14 (10) +#define BSC_ACCESS_WAIT_18 (11) +#define BSC_ACCESS_WAIT_24 (12) + +#define BSC_WRITE_ACCESS_WAIT_SAME (0) +#define BSC_WRITE_ACCESS_WAIT_0 (1) +#define BSC_WRITE_ACCESS_WAIT_1 (2) +#define BSC_WRITE_ACCESS_WAIT_2 (3) +#define BSC_WRITE_ACCESS_WAIT_3 (4) +#define BSC_WRITE_ACCESS_WAIT_4 (5) +#define BSC_WRITE_ACCESS_WAIT_5 (6) +#define BSC_WRITE_ACCESS_WAIT_6 (7) + +#define BSC_BYTE_ENABLE_RD_WR (0) +#define BSC_BYTE_ENABLE_WE (1) + +#define BSC_CAS_LATENCY_1 (0) +#define BSC_CAS_LATENCY_2 (1) +#define BSC_CAS_LATENCY_3 (2) +#define BSC_CAS_LATENCY_4 (3) + +#define BSC_WTRC_IDLE_2 (0) +#define BSC_WTRC_IDLE_3 (1) +#define BSC_WTRC_IDLE_5 (2) +#define BSC_WTRC_IDLE_8 (3) + +#define BSC_TRWL_CYCLE_0 (0) +#define BSC_TRWL_CYCLE_1 (1) +#define BSC_TRWL_CYCLE_2 (2) +#define BSC_TRWL_CYCLE_3 (3) + +#define BSC_PRECHARGE_0 (0x00000000) +#define BSC_PRECHARGE_1 (0x00000008) +#define BSC_PRECHARGE_2 (0x00000010) +#define BSC_PRECHARGE_3 (0x00000018) + +#define BSC_WTRCD_WAIT_0 (0) +#define BSC_WTRCD_WAIT_1 (1) +#define BSC_WTRCD_WAIT_2 (2) +#define BSC_WTRCD_WAIT_3 (3) + +#define BSC_WTRP_WAIT_0 (0) +#define BSC_WTRP_WAIT_1 (1) +#define BSC_WTRP_WAIT_2 (2) +#define BSC_WTRP_WAIT_3 (3) + +#define BSC_ROW_11_BIT (0) +#define BSC_ROW_12_BIT (1) +#define BSC_ROW_13_BIT (2) + +#define BSC_COL_8_BIT (0) +#define BSC_COL_9_BIT (1) +#define BSC_COL_10_BIT (2) + +#define BSC_BACTV_AUTO (0) +#define BSC_BACTV_BANK (1) + +#define BSC_PDOWN_INVALID (0) +#define BSC_PDOWN_VALID (1) + +#define BSC_RMODE_AUTO (0) +#define BSC_RMODE_SELF (1) + +#define BSC_RFSH_NONE (0) +#define BSC_RFSH_DONE (1) + +#define BSC_DEEP_SELF (0) +#define BSC_DEEP_DEEP (1) + +#define BSC_PROTECT_KEY (0xA55A0000) + +#define BSC_RFSH_TIME_1 (0) +#define BSC_RFSH_TIME_2 (1) +#define BSC_RFSH_TIME_4 (2) +#define BSC_RFSH_TIME_6 (3) +#define BSC_RFSH_TIME_8 (4) + +#define BSC_CKS_DIV_STOP (0x00000000) +#define BSC_CKS_DIV_4 (0x00000008) +#define BSC_CKS_DIV_16 (0x00000010) +#define BSC_CKS_DIV_64 (0x00000018) +#define BSC_CKS_DIV_256 (0x00000020) +#define BSC_CKS_DIV_1024 (0x00000028) +#define BSC_CKS_DIV_2048 (0x00000030) +#define BSC_CKS_DIV_4096 (0x00000038) + +#define BSC_CMIE_DISABLE (0x00000000) +#define BSC_CMIE_ENABLE (0x00000040) + +/*********************************************************************************************************************** +Exported global variables and functions (to be accessed by other files) +***********************************************************************************************************************/ + + + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_ram_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_ram_init.h new file mode 100644 index 000000000..29e920b3a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_ram_init.h @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* System Name : RZ/T1 Init program +* File Name : r_ram.h +* Version : 0.1 +* Device : R7S910018 +* Abstract : API for internal extended RAM function +* Tool-Chain : GNUARM-NONEv14.02-EABI +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : Internal extended RAM setting API of RZ/T1 +* Limitation : none +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 First Release +***********************************************************************************************************************/ + +#ifndef _R_RAM_HEADER_ +#define _R_RAM_HEADER_ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables and functions (to be accessed by other files) +***********************************************************************************************************************/ +void R_RAM_Init(void); +void R_RAM_ECCEnable(void); +void R_RAM_WriteEnable(void); +void R_RAM_WriteDisable(void); + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_reset.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_reset.h new file mode 100644 index 000000000..78d6c0590 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_reset.h @@ -0,0 +1,62 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* System Name : RZ/T1 Init program +* File Name : r_reset.h +* Version : 0.1 +* Device : R7S910018 +* Abstract : API for reset function +* Tool-Chain : GNUARM-NONEv14.02-EABI +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : Reset function API of RZ/T1 +* Limitation : none +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 First Release +***********************************************************************************************************************/ + +#ifndef _R_RESET_HEADER_ +#define _R_RESET_HEADER_ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define RST_SOURCE_RES (0x00000002) +#define RST_SOURCE_ECM (0x00000004) +#define RST_SOURCE_SWR1 (0x00000008) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/* RESET and Low-Power function registers access control */ +void r_rst_write_enable(void); +void r_rst_write_disable(void); + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_system.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_system.h new file mode 100644 index 000000000..d08bac6a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_system.h @@ -0,0 +1,116 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* System Name : RZ/T1 Init program +* File Name : r_system.h +* Version : 0.1 +* Device : R7S910018 +* Abstract : Definitions for System +* Tool-Chain : GNUARM-NONEv14.02-EABI +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : Define the system settings ans value. +* Limitation : none +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 First Release +***********************************************************************************************************************/ + +#ifndef _R_SYSTEM_HEADER_ +#define _R_SYSTEM_HEADER_ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPCRA0 +#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPCRA1 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPCRA2 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPCRA3 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPCRA4 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPCRA5 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPCRA6 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPCRA7 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPCRA8 +#define MSTP_GPTA SYSTEM.MSTPCRA.BIT.MSTPCRA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPCRA11 + +#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPCRB1 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPCRB2 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPCRB3 +#define MSTP_SCIFA4 SYSTEM.MSTPCRB.BIT.MSTPCRB5 +#define MSTP_SCIFA3 SYSTEM.MSTPCRB.BIT.MSTPCRB6 +#define MSTP_SCIFA2 SYSTEM.MSTPCRB.BIT.MSTPCRB7 +#define MSTP_SCIFA1 SYSTEM.MSTPCRB.BIT.MSTPCRB8 +#define MSTP_SCIFA0 SYSTEM.MSTPCRB.BIT.MSTPCRB9 +#define MSTP_RSPI3 SYSTEM.MSTPCRB.BIT.MSTPCRB10 +#define MSTP_RSPI2 SYSTEM.MSTPCRB.BIT.MSTPCRB11 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPCRB12 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPCRB13 +#define MSTP_ETHERSW SYSTEM.MSTPCRB.BIT.MSTPCRB14 +#define MSTP_ECATC SYSTEM.MSTPCRB.BIT.MSTPCRB15 +#define MSTP_EMDIO SYSTEM.MSTPCRB.BIT.MSTPCRB16 +#define MSTP_ERMII SYSTEM.MSTPCRB.BIT.MSTPCRB17 +#define MSTP_HWRTOS SYSTEM.MSTPCRB.BIT.MSTPCRB18 +#define MSTP_CLKOUT25M SYSTEM.MSTPCRB.BIT.MSTPCRB19 + +#define MSTP_USB SYSTEM.MSTPCRC.BIT.MSTPCRC1 +#define MSTP_DSMIF SYSTEM.MSTPCRC.BIT.MSTPCRC2 +#define MSTP_TEMPS SYSTEM.MSTPCRC.BIT.MSTPCRC3 +#define MSTP_S12ADC1 SYSTEM.MSTPCRC.BIT.MSTPCRC4 +#define MSTP_S12ADC0 SYSTEM.MSTPCRC.BIT.MSTPCRC5 +#define MSTP_ELC SYSTEM.MSTPCRC.BIT.MSTPCRC6 +#define MSTP_BSC SYSTEM.MSTPCRC.BIT.MSTPCRC7 +#define MSTP_CKIO SYSTEM.MSTPCRC.BIT.MSTPCRC8 +#define MSTP_SPIBSC SYSTEM.MSTPCRC.BIT.MSTPCRC9 +#define MSTP_DOC SYSTEM.MSTPCRC.BIT.MSTPCRC10 +#define MSTP_CRC SYSTEM.MSTPCRC.BIT.MSTPCRC11 +#define MSTP_CLMA2 SYSTEM.MSTPCRC.BIT.MSTPCRC12 +#define MSTP_CLMA1 SYSTEM.MSTPCRC.BIT.MSTPCRC13 +#define MSTP_CLMA0 SYSTEM.MSTPCRC.BIT.MSTPCRC14 + +#define MSTP_SSI SYSTEM.MSTPCRD.BIT.MSTPCRD2 + +#define MSTP_DMAC1 SYSTEM.MSTPCRE.BIT.MSTPCRE4 +#define MSTP_DMAC0 SYSTEM.MSTPCRE.BIT.MSTPCRE5 + +#define MSTP_CORESIGHT SYSTEM.MSTPCRF.BIT.MSTPCRF0 + +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables and functions (to be accessed by other files) +***********************************************************************************************************************/ + +/* End _R_SYSTEM_HEADER_ */ +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_typedefs.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_typedefs.h new file mode 100644 index 000000000..f9cc713d8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/r_typedefs.h @@ -0,0 +1,87 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_typedefs.h +* Device(s) : RZ/A1H (R7S910018) +* Tool-Chain : GNUARM-NONEv14.02-EABI +* H/W Platform : RSK+T1 CPU Board +* Description : basic type definition +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.10.2014 1.00 +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include +/* Multiple inclusion prevention macro */ +#ifndef R_TYPEDEFS_H +#define R_TYPEDEFS_H + + +/* in case has defined it. */ +#ifndef NULL +#define NULL (0) +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#if !defined(__bool_true_false_are_defined) && !defined(__cplusplus) + +#define FALSE (0) +#define TRUE (1) + +#endif + +/* These two macros are used to suppress warnings generated by unused variables. + Writing to some registers require a read instruction following the write. + A dummy variable is declared and used to read the register written to. */ +#define UNUSED_PARAM(param) ((void)(param)) +#define UNUSED_VARIABLE(param) ((void)(param)) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef char char_t; +typedef unsigned int bool_t; +typedef int int_t; +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed long int32_t; +typedef signed long long int64_t; +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned long uint32_t; +typedef unsigned long long uint64_t; +typedef float float32_t; +typedef double float64_t; +typedef long double float128_t; + +/* R_TYPEDEFS_H */ +#endif + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/siochar.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/siochar.h new file mode 100644 index 000000000..2f603bf4c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/inc/siochar.h @@ -0,0 +1,57 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : siochar.h +* Device(s) : RZ/A1H (R7S910018) +* Tool-Chain : GNUARM-NONEv14.02-EABI +* H/W Platform : RSK+T1 CPU Board +* Description : Sample Program - Terminal I/O header file +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.10.2014 1.00 +***********************************************************************************************************************/ + +/* Multiple inclusion prevention macro */ +#ifndef SIO_CHAR_H +#define SIO_CHAR_H + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Functions Prototypes +***********************************************************************************************************************/ +int32_t sio_write (int32_t file_no, const char * buffer, uint32_t writing_b); +int32_t sio_read (int32_t file_no, char * buffer, uint32_t reading_b); + +void io_init_scifa2 (void); +char io_get_char (void); +void io_put_char (char buffer); + +/* SIO_CHAR_H */ +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/loader_init2.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/loader_init2.c new file mode 100644 index 000000000..394872d3e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/loader_init2.c @@ -0,0 +1,242 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* System Name : RZ/T1 Init program +* File Name : loader_init2.c +* Version : 0.1 +* Device : R7S910018 +* Abstract : Loader program 2 +* Tool-Chain : GNUARM-NONEv14.02-EABI +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : Initialise the peripheral settings of RZ/T1 +* Limitation : none +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 First Release +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include +#include "iodefine.h" +#include "r_cg_cgc.h" +#include "r_cg_mpc.h" +#include "r_system.h" +#include "r_reset.h" +#include "r_atcm_init.h" +#include "r_typedefs.h" + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private variables and functions +***********************************************************************************************************************/ +static void reset_check (void); +static void cpg_init (void); + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ +extern void main(void); +extern void set_low_vec(void); +extern void cache_init(void); + +/*********************************************************************************************************************** +Exported global variables and functions (to be accessed by other files) +***********************************************************************************************************************/ +void loader_init2 (void); + +/*********************************************************************************************************************** +* Function Name : loader_init2 +* Description : Initialise system by loader program 2 +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void loader_init2 (void) +{ + /* Check the reset source */ + reset_check(); + + /* Set CPU clock and LOCO clock */ + cpg_init(); + + /* Set ATCM access wait to 1-wait with optimisation */ + /* Caution: ATCM_WAIT_0 is permitted if CPUCLK = 150MHz or 300MHz. + ATCM_WAIT_1_OPT is permitted if CPUCLK = 450MHz or 600MHz.*/ + R_ATCM_WaitSet(ATCM_WAIT_1_OPT); + + /* Initialise I1, D1 Cache and MPU setting */ + cache_init(); + + /* Set RZ/T1 to Low-vector (SCTLR.V = 0) */ + set_low_vec(); + + /* Jump to _main() */ + main(); + +} + +/*********************************************************************************************************************** + End of function loader_init2 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name : reset_check +* Description : Check the reset source and execute the each sequence. +* When error source number 35 is generated, set P77 pin to High. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +static void reset_check(void) +{ + volatile uint8_t result=0; + volatile uint32_t dummy=0; + + UNUSED_VARIABLE(result); + UNUSED_VARIABLE(dummy); + + /* Check the reset status flag and execute the each sequence */ + if (RST_SOURCE_ECM == SYSTEM.RSTSR0.LONG) + { + /* Enable writing to the RSTSR0 register */ + r_rst_write_enable(); + + /* Clear reset factor flag */ + SYSTEM.RSTSR0.LONG = 0x00000000; + + /* Disable writing to the RSTSR0 register */ + r_rst_write_disable(); + + /* Please coding the User program */ + + } + + /* Software reset 1 is generated */ + else if (RST_SOURCE_SWR1 == SYSTEM.RSTSR0.LONG) + { + /* Clear reset status flag */ + /* Enable writing to the RSTSR0 register */ + r_rst_write_enable(); + + /* Clear reset factor flag */ + SYSTEM.RSTSR0.LONG = 0x00000000; + + /* Disable writing to the RSTSR0 register */ + r_rst_write_disable(); + + /* Please coding the User program */ + + } + else if (RST_SOURCE_RES == SYSTEM.RSTSR0.LONG) // RES# pin reset is generated + { + /* Clear reset status flag */ + + /* Enable writing to the RSTSR0 register */ + r_rst_write_enable(); + + /* Clear reset factor flag */ + SYSTEM.RSTSR0.LONG = 0x00000000; + + /* Disable writing to the RSTSR0 register */ + r_rst_write_disable(); + + /* Please add user code */ + + } + + /* Any reset is not generated */ + else + { + /* Please add user code */ + } + +} + +/*********************************************************************************************************************** + End of function reset_check +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name : cpg_init +* Description : Set CPU clock and LOCO clock by CPG function +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +static void cpg_init(void) +{ + volatile uint32_t dummy=0; + + UNUSED_VARIABLE(dummy); + + /* Enables writing to the registers related to CPG function */ + R_CPG_WriteEnable(); + + /* Enables LOCO clock operation */ + SYSTEM.LOCOCR.BIT.LCSTP = CPG_LOCO_ENABLE; + + /* Set CPUCLK to 450MHz, and dummy read at three times */ + SYSTEM.PLL1CR.LONG = CPG_CPUCLK_450_MHz; + dummy = SYSTEM.PLL1CR.LONG; + dummy = SYSTEM.PLL1CR.LONG; + dummy = SYSTEM.PLL1CR.LONG; + + /* Enables PLL1 operation */ + SYSTEM.PLL1CR2.LONG = CPG_PLL1_ON; + + /* Disables writing to the registers related to CPG function */ + R_CPG_WriteDisable(); + + /* Wait about 100us for PLL1 (and LOCO) stabilisation */ + R_CPG_PLLWait(); + + /* Enables writing to the registers related to CPG function */ + R_CPG_WriteEnable(); + + /* Selects the PLL1 as clock source */ + SYSTEM.SCKCR2.LONG = CPG_SELECT_PLL1; + + /* Disables writing to the registers related to CPG function */ + R_CPG_WriteDisable(); + +} + +/*********************************************************************************************************************** + End of function cpg_init +***********************************************************************************************************************/ + + +/* End of File */ + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_atcm_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_atcm_init.c new file mode 100644 index 000000000..1c135f308 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_atcm_init.c @@ -0,0 +1,111 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* System Name : RZ/T1 Init program +* File Name : r_atcm_init.c +* Version : 0.1 +* Device : R7S910018 +* Abstract : API for ATCM function +* Tool-Chain : GNUARM-NONEv14.02-EABI +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : ATCM access wait setting API of RZ/T1 +* Limitation : This wait setting could not be executed in ATCM program area. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include +#include "iodefine.h" +#include "r_system.h" +#include "r_atcm_init.h" +#include "r_typedefs.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define ATCM_WRITE_ENABLE (0x0000A508) +#define ATCM_WRITE_DISABLE (0x0000A500) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + + + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +Exported global variables and functions (to be accessed by other files) +***********************************************************************************************************************/ + + + +/*********************************************************************************************************************** +Private variables and functions +***********************************************************************************************************************/ + + + +/*********************************************************************************************************************** +* Function Name : R_ATCM_WaitSet +* Description : Sets ATCM access wait. +* Arguments : atcm_wait +* Wait settings for ATCM access +* Return Value : none +***********************************************************************************************************************/ +void R_ATCM_WaitSet(uint32_t atcm_wait) +{ + volatile uint32_t dummy=0; + + UNUSED_VARIABLE(dummy); + + /* Enables writing to the ATCM register */ + SYSTEM.PRCR.LONG = ATCM_WRITE_ENABLE; + dummy = SYSTEM.PRCR.LONG; + + /* Sets ATCM access wait to atcm_wait value */ + SYSTEM.SYTATCMWAIT.LONG = atcm_wait; + + /* Disables writing to the ATCM register */ + SYSTEM.PRCR.LONG = ATCM_WRITE_DISABLE; + dummy = SYSTEM.PRCR.LONG; + +} + +/*********************************************************************************************************************** + End of function R_ATCM_WaitSet +***********************************************************************************************************************/ + +/* End of File */ + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_ram_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_ram_init.c new file mode 100644 index 000000000..0decedda8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_ram_init.c @@ -0,0 +1,153 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* System Name : RZ/T1 Init program +* File Name : r_ram_init.c +* Version : 0.1 +* Device : R7S910018 +* Abstract : API for internal extended RAM function +* Tool-Chain : GNUARM-NONEv14.02-EABI +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : internal extended RAM setting API of RZ/T1 +* Limitation : none +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include +#include "iodefine.h" +#include "r_system.h" +#include "r_ram_init.h" +#include "r_typedefs.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define RAM_ECC_ENABLE (0x00000001) +#define RAM_ECC_DISABLE (0x00000000) +#define RAM_PROTECT (0x00000000) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + + + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +Exported global variables and functions (to be accessed by other files) +***********************************************************************************************************************/ + + + +/*********************************************************************************************************************** +Private variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name : R_RAM_ECCEnable +* Description : Enable ECC function for internal extended RAM. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_RAM_ECCEnable(void) +{ + /* Enables writing to the protected registers related to RAM function */ + R_RAM_WriteEnable(); + + /* Enable ECC function */ + ECCRAM.RAMEDC.LONG = RAM_ECC_ENABLE; + + /* Disables writing to the protected registers related to RAM function */ + R_RAM_WriteDisable(); + +} + +/*********************************************************************************************************************** + End of function R_RAM_ECCEnable +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +* Function Name : R_RAM_WriteEnable +* Description : Enable writing to the protected registers related to RAM. +* And dummy read the register in order to fix the register value. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_RAM_WriteEnable(void) +{ + volatile uint32_t dummy=0; + + UNUSED_VARIABLE(dummy); + + /* Special sequence for protect release */ + ECCRAM.RAMPCMD.LONG = 0x000000A5; // Write fixed value 0x000000A5 + ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value + ECCRAM.RAMPCMD.LONG = 0x0000FFFE; // Write inverted value of the expected value + ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value again + dummy = ECCRAM.RAMPCMD.LONG; + +} + +/*********************************************************************************************************************** + End of function R_RAM_WriteEnable +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name : R_RAM_WriteDisable +* Description : Disable writing to the protected registers related to RAM. +* And dummy read the register in order to fix the register value. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_RAM_WriteDisable(void) +{ + volatile uint32_t dummy=0; + + UNUSED_VARIABLE(dummy); + + /* Clear RAMPCMD register to zero */ + ECCRAM.RAMPCMD.LONG = RAM_PROTECT; + dummy = ECCRAM.RAMPCMD.LONG; + +} + +/*********************************************************************************************************************** + End of function R_RAM_WriteDisable +***********************************************************************************************************************/ + +/* End of File */ + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_reset.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_reset.c new file mode 100644 index 000000000..60fc61523 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/GCC/src/r_reset.c @@ -0,0 +1,128 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* System Name : RZ/T1 Init program +* File Name : r_reset.c +* Version : 0.1 +* Device : R7S910018 +* Abstract : API for RESET and Low-Power function +* Tool-Chain : GNUARM-NONEv14.02-EABI +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : RESET and Low-Power API of RZ/T1 +* Limitation : none +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.05.2015 1.00 First Release +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include +#include "iodefine.h" +#include "r_system.h" +#include "r_reset.h" +#include "r_typedefs.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define RST_WRITE_ENABLE (0x0000A502) +#define RST_WRITE_DISABLE (0x0000A500) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + + + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +Exported global variables and functions (to be accessed by other files) +***********************************************************************************************************************/ + + + +/*********************************************************************************************************************** +Private variables and functions +***********************************************************************************************************************/ + + +/******************************************************************************* +* Function Name : r_rst_write_enable +* Description : Enables writing to the registers related to RESET and Low- +* Power function. And dummy read the register in order to fix +* the register value. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void r_rst_write_enable(void) +{ + volatile uint32_t dummy=0; + + UNUSED_VARIABLE(dummy); + + /* Enables writing to the Reset and Low-Power register */ + SYSTEM.PRCR.LONG = RST_WRITE_ENABLE; + dummy = SYSTEM.PRCR.LONG; + +} + +/******************************************************************************* + End of function r_rst_write_enable +*******************************************************************************/ + +/******************************************************************************* +* Function Name : r_rst_write_disable +* Description : Disables writing to the registers related to RESET and Low- +* Power function. And dummy read the register in order to fix +* the register value. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void r_rst_write_disable(void) +{ + volatile uint32_t dummy=0; + + UNUSED_VARIABLE(dummy); + + /* Disables writing to the Reset and Low-Power register */ + SYSTEM.PRCR.LONG = RST_WRITE_DISABLE; + dummy = SYSTEM.PRCR.LONG; + +} + +/*********************************************************************************************************************** + End of function r_rst_write_disable +***********************************************************************************************************************/ + +/* End of File */ + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/Interrupt_Entry_Stubs.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/Interrupt_Entry_Stubs.asm new file mode 100644 index 000000000..4668654ac --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/Interrupt_Entry_Stubs.asm @@ -0,0 +1,117 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + SECTION intvec:CODE:ROOT(2) + ARM + + EXTERN pxISRFunction + EXTERN FreeRTOS_Tick_Handler + EXTERN FreeRTOS_IRQ_Handler + EXTERN vCMT_1_Channel_0_ISR + EXTERN vCMT_1_Channel_1_ISR + + PUBLIC FreeRTOS_Tick_Handler_Entry + PUBLIC vCMT_1_Channel_0_ISR_Entry + PUBLIC vCMT_1_Channel_1_ISR_Entry + +FreeRTOS_Tick_Handler_Entry: + /* Save used registers (probably not necessary). */ + PUSH {r0-r1} + /* Save the address of the C portion of this handler in pxISRFunction. */ + LDR r0, =pxISRFunction + LDR R1, =FreeRTOS_Tick_Handler + STR R1, [r0] + /* Restore used registers then branch to the FreeRTOS IRQ handler. */ + POP {r0-r1} + B FreeRTOS_IRQ_Handler +/*-----------------------------------------------------------*/ + +vCMT_1_Channel_0_ISR_Entry: + /* Save used registers (probably not necessary). */ + PUSH {r0-r1} + /* Save the address of the C portion of this handler in pxISRFunction. */ + LDR r0, =pxISRFunction + LDR R1, =vCMT_1_Channel_0_ISR + STR R1, [r0] + /* Restore used registers then branch to the FreeRTOS IRQ handler. */ + POP {r0-r1} + B FreeRTOS_IRQ_Handler +/*-----------------------------------------------------------*/ + +vCMT_1_Channel_1_ISR_Entry: + /* Save used registers (probably not necessary). */ + PUSH {r0-r1} + /* Save the address of the C portion of this handler in pxISRFunction. */ + LDR r0, =pxISRFunction + LDR R1, =vCMT_1_Channel_1_ISR + STR R1, [r0] + /* Restore used registers then branch to the FreeRTOS IRQ handler. */ + POP {r0-r1} + B FreeRTOS_IRQ_Handler + + END diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/RZT1_init_RAM.mac b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/RZT1_init_RAM.mac new file mode 100644 index 000000000..795e779e8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/RZT1_init_RAM.mac @@ -0,0 +1,81 @@ +/* + * + * C-SPY macro information + * + * __jtagCP15ReadReg(CRn, CRm, op1, op2) + * __jtagCP15WriteReg(CRn, CRm, op1, op2, value) + * __readMemory8(address, zone) + * __writeMemory8(value, address, zone) + * __writeMemory32(value, address, zone) + * + * + */ + +__init_TCM() +{ +__var v_reg; + + __message "Initialize ATCM"; + /* + MRC p15, 0, , c1, c0, 1 ; Read ACTLR + MCR p15, 0, , c1, c0, 1 ; Write ACTLR + */ + + /* enable ECC in ACTLR */ + v_reg = __jtagCP15ReadReg(1, 0, 0, 1); + v_reg = v_reg | 0x06000000; // set 26 and 25 bits for enabling ECC + __message "ACTRL: ", v_reg:%x; // output ACTRL value for check + __jtagCP15WriteReg(1, 0, 0, 1, v_reg); + + __fillMemory32(0x0, 0x00000000, "Memory", 0x20000, "Copy"); + __message "ATCM initialization finished"; +} + + +__init_VIC_ProvideHandler() +{ +__var v_reg; + + __message "Initialize VIC provide handler \n"; + /* + MRC p15, 0, , c1, c0, 0 ; Read SCTLR + MCR p15, 0, , c1, c0, 0 ; Write SCTLR + */ + + /* Set VIC to provide handler address */ + v_reg = __jtagCP15ReadReg(1, 0, 0, 0); + v_reg = v_reg | 0x01000000; // set 24 bit for setting VE bit + __jtagCP15WriteReg(1, 0, 0, 0, v_reg); + +} + +execUserPreload() +{ +__var t ; + + __message "Executing execUserPreload() function"; + + __hwReset(0); + __delay(100); + __init_TCM(); + + __message "FINISH Executing execUserPreload() function"; +} + + +execUserReset() +{ +__var t; + __message "Executing execUserReset() function"; + + __init_VIC_ProvideHandler(); + + t = #CPSR; // Clear CPSR.F bit + __message "CPSR ",t:%x; + t = t & 0xFFFFFFBF; + #CPSR = t; + t = #CPSR; + __message "CPSR ",t:%x; + + __message "FINISH Executing execUserReset() function"; +} diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/RZ_T1_init.icf b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/RZ_T1_init.icf new file mode 100644 index 000000000..2e86388b6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/RZ_T1_init.icf @@ -0,0 +1,163 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x40020040; +define symbol __ICFEDIT_region_ROM_end__ = 0x4008FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x00070000; +define symbol __ICFEDIT_region_RAM_end__ = 0x0007FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_svcstack__ = 0x200; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __region_USER_PRG_start__ = 0x00000040; +define symbol __region_USER_PRG_end__ = 0x0006FFFF; + +define symbol __region_D_LDR_DATA_start__ = 0x00800000; +define symbol __region_D_LDR_DATA_end__ = 0x00801FFF; +define symbol __region_D_LDR_PRG_start__ = 0x00802000; +define symbol __region_D_LDR_PRG_end__ = 0x00807FFF; + +define symbol __region_D_LDR_M3PRG_start__ = 0x04000000; +define symbol __region_D_LDR_M3PRG_end__ = 0x0407FFFF; + +define symbol __region_S_LDR_M3PRG_start__ = 0x00050000; +define symbol __region_S_LDR_M3PRG_end__ = 0x0006FFFF; + +define symbol __region_EXT_RAM1_start__ = 0x22000000; +define symbol __region_EXT_RAM1_end__ = 0x2207FFFF; +define symbol __region_EXT_RAM2_start__ = 0x24000000; +define symbol __region_EXT_RAM2_end__ = 0x2407FFFF; +define symbol __region_SPIBSC_start__ = 0x30000000; +define symbol __region_SPIBSC_end__ = 0x33FFFFFF; + +define symbol __region_CS0_start__ = 0x40000000; +define symbol __region_CS0_end__ = 0x43FFFFFF; +define symbol __region_CS1_start__ = 0x44000000; +define symbol __region_CS1_end__ = 0x47FFFFFF; +define symbol __region_CS2_start__ = 0x48000000; +define symbol __region_CS2_end__ = 0x4BFFFFFF; +define symbol __region_CS3_start__ = 0x4C000000; +define symbol __region_CS3_end__ = 0x4FFFFFFF; +define symbol __region_CS4_start__ = 0x50000000; +define symbol __region_CS4_end__ = 0x53FFFFFF; +define symbol __region_CS5_start__ = 0x54000000; +define symbol __region_CS5_end__ = 0x57FFFFFF; + +define region USER_PRG_region = mem:[from __region_USER_PRG_start__ to __region_USER_PRG_end__]; +define region D_LDR_DATA_region = mem:[from __region_D_LDR_DATA_start__ to __region_D_LDR_DATA_end__]; +define region D_LDR_PRG_region = mem:[from __region_D_LDR_PRG_start__ to __region_D_LDR_PRG_end__]; + +define region D_LDR_M3PRG_region = mem:[from __region_D_LDR_M3PRG_start__ to __region_D_LDR_M3PRG_end__]; +define region S_LDR_M3PRG_region = mem:[from __region_S_LDR_M3PRG_start__ to __region_S_LDR_M3PRG_end__]; + +define region EXT_RAM1_region = mem:[from __region_EXT_RAM1_start__ to __region_EXT_RAM1_end__]; +define region EXT_RAM2_region = mem:[from __region_EXT_RAM2_start__ to __region_EXT_RAM2_end__]; +define region SPIBSC_region = mem:[from __region_SPIBSC_start__ to __region_SPIBSC_end__]; +define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__]; +define region CS1_region = mem:[from __region_CS1_start__ to __region_CS1_end__]; +define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__]; +define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__]; +define region CS4_region = mem:[from __region_CS4_start__ to __region_CS4_end__]; +define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +define block LDR_PRG_RBLOCK with fixed order + { ro code object loader_init.o, + ro code object loader_init2.o, + ro code object r_atcm_init.o, + ro code object r_cpg.o, + ro code object r_ram_init.o, + ro code object r_mpc.o, + ro code object r_reset.o, + ro code object data_init.o, + ro code object copy_init3.o }; +define block LDR_DATA_ZBLOCK { section .bss object loader_init.o, + section .bss object loader_init2.o, + section .bss object r_atcm_init.o, + section .bss object r_cpg.o, + section .bss object r_ram_init.o, + section .bss object r_mpc.o, + section .bss object r_reset.o, + section .bss object data_init.o, + section .bss object copy_init3.o }; +define block LDR_DATA_RBLOCK { section .data_init object loader_init.o, + section .data_init object loader_init2.o, + section .data_init object r_atcm_init.o, + section .data_init object r_cpg.o, + section .data_init object r_ram_init.o, + section .data_init object r_mpc.o, + section .data_init object r_reset.o, + section .data_init object data_init.o, + section .data_init object copy_init3.o }; +define block LDR_DATA_WBLOCK { section .data object loader_init.o, + section .data object loader_init2.o, + section .data object r_atcm_init.o, + section .data object r_cpg.o, + section .data object r_ram_init.o, + section .data object r_mpc.o, + section .data object r_reset.o, + section .data object data_init.o, + section .data object copy_init3.o }; +define block VECTOR_RBLOCK { ro code object vector.o }; +define block USER_PRG_RBLOCK { ro code }; +define block USER_DATA_ZBLOCK { section .bss }; +define block USER_DATA_RBLOCK { section .data_init }; +define block USER_DATA_WBLOCK { section .data }; + +define block M3_PRG_RBLOCK { section __M3prg_init }; +define block M3_PRG_WBLOCK { section __M3prg }; + +initialize by copy { readwrite }; + +do not initialize { section .noinit, section .bss }; + +initialize manually { section __M3prg }; + +place at address mem:__ICFEDIT_intvec_start__ { block VECTOR_RBLOCK }; + +place in USER_PRG_region { block USER_PRG_RBLOCK, + block USER_DATA_RBLOCK, + readonly }; +place in RAM_region { readwrite }; +place in RAM_region { block USER_DATA_WBLOCK, + block USER_DATA_ZBLOCK, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; +place in D_LDR_DATA_region { block LDR_DATA_WBLOCK, block LDR_DATA_ZBLOCK }; +place in D_LDR_PRG_region { block LDR_PRG_RBLOCK, + block LDR_DATA_RBLOCK }; + +place in S_LDR_M3PRG_region { block M3_PRG_RBLOCK }; +place in D_LDR_M3PRG_region { block M3_PRG_WBLOCK }; + +place in EXT_RAM1_region {}; +place in EXT_RAM2_region {}; +place in SPIBSC_region {}; +place in CS0_region {}; +place in CS1_region {}; +place in CS2_region {}; +place in CS3_region {}; +place in CS4_region {}; +place in CS5_region {}; diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_atcm_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_atcm_init.h new file mode 100644 index 000000000..977d508fc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_atcm_init.h @@ -0,0 +1,64 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_atcm.h +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for ATCM function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : ATCM access wait setting API of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +#ifndef _R_ATCM_HEADER_ +#define _R_ATCM_HEADER_ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define ATCM_WAIT_1_OPT (0) +#define ATCM_WAIT_1 (1) +#define ATCM_WAIT_0 (2) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void R_ATCM_WaitSet(uint32_t atcm_wait); + + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_bsc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_bsc.h new file mode 100644 index 000000000..926c3aaef --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_bsc.h @@ -0,0 +1,186 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_cpg.h +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for CPG function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : BSC setting API of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +#ifndef _R_BSC_HEADER_ +#define _R_BSC_HEADER_ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define BSC_IDLE_CYCLE_0 (0) +#define BSC_IDLE_CYCLE_1 (1) +#define BSC_IDLE_CYCLE_2 (2) +#define BSC_IDLE_CYCLE_4 (3) +#define BSC_IDLE_CYCLE_6 (4) +#define BSC_IDLE_CYCLE_8 (5) +#define BSC_IDLE_CYCLE_10 (6) +#define BSC_IDLE_CYCLE_12 (7) + +#define BSC_TYPE_NORMAL (0) +#define BSC_TYPE_BURST_ROM_ASYNC (1) +#define BSC_TYPE_MPX_IO (2) +#define BSC_TYPE_SRAM_BYTE (3) +#define BSC_TYPE_SDRAM (4) +#define BSC_TYPE_BURST_ROM_SYNC (7) + +#define BSC_WIDTH_8_BIT (1) +#define BSC_WIDTH_16_BIT (2) +#define BSC_WIDTH_32_BIT (3) + +#define BSC_DELAY_STATE_CYCLE_0_5 (0) +#define BSC_DELAY_STATE_CYCLE_1_5 (1) +#define BSC_DELAY_STATE_CYCLE_2_5 (2) +#define BSC_DELAY_STATE_CYCLE_3_5 (3) + +#define BSC_EXT_WAIT_VALID (0) +#define BSC_EXT_WAIT_IGNORED (1) + +#define BSC_ACCESS_WAIT_0 (0) +#define BSC_ACCESS_WAIT_1 (1) +#define BSC_ACCESS_WAIT_2 (2) +#define BSC_ACCESS_WAIT_3 (3) +#define BSC_ACCESS_WAIT_4 (4) +#define BSC_ACCESS_WAIT_5 (5) +#define BSC_ACCESS_WAIT_6 (6) +#define BSC_ACCESS_WAIT_8 (7) +#define BSC_ACCESS_WAIT_10 (8) +#define BSC_ACCESS_WAIT_12 (9) +#define BSC_ACCESS_WAIT_14 (10) +#define BSC_ACCESS_WAIT_18 (11) +#define BSC_ACCESS_WAIT_24 (12) + +#define BSC_WRITE_ACCESS_WAIT_SAME (0) // Set same settings of WR[3:0]bit +#define BSC_WRITE_ACCESS_WAIT_0 (1) +#define BSC_WRITE_ACCESS_WAIT_1 (2) +#define BSC_WRITE_ACCESS_WAIT_2 (3) +#define BSC_WRITE_ACCESS_WAIT_3 (4) +#define BSC_WRITE_ACCESS_WAIT_4 (5) +#define BSC_WRITE_ACCESS_WAIT_5 (6) +#define BSC_WRITE_ACCESS_WAIT_6 (7) + +#define BSC_BYTE_ENABLE_RD_WR (0) +#define BSC_BYTE_ENABLE_WE (1) + +#define BSC_CAS_LATENCY_1 (0) +#define BSC_CAS_LATENCY_2 (1) +#define BSC_CAS_LATENCY_3 (2) +#define BSC_CAS_LATENCY_4 (3) + +#define BSC_WTRC_IDLE_2 (0) +#define BSC_WTRC_IDLE_3 (1) +#define BSC_WTRC_IDLE_5 (2) +#define BSC_WTRC_IDLE_8 (3) + +#define BSC_TRWL_CYCLE_0 (0) +#define BSC_TRWL_CYCLE_1 (1) +#define BSC_TRWL_CYCLE_2 (2) +#define BSC_TRWL_CYCLE_3 (3) + +#define BSC_PRECHARGE_0 (0x00000000) +#define BSC_PRECHARGE_1 (0x00000008) +#define BSC_PRECHARGE_2 (0x00000010) +#define BSC_PRECHARGE_3 (0x00000018) + +#define BSC_WTRCD_WAIT_0 (0) +#define BSC_WTRCD_WAIT_1 (1) +#define BSC_WTRCD_WAIT_2 (2) +#define BSC_WTRCD_WAIT_3 (3) + +#define BSC_WTRP_WAIT_0 (0) +#define BSC_WTRP_WAIT_1 (1) +#define BSC_WTRP_WAIT_2 (2) +#define BSC_WTRP_WAIT_3 (3) + +#define BSC_ROW_11_BIT (0) +#define BSC_ROW_12_BIT (1) +#define BSC_ROW_13_BIT (2) + +#define BSC_COL_8_BIT (0) +#define BSC_COL_9_BIT (1) +#define BSC_COL_10_BIT (2) + +#define BSC_BACTV_AUTO (0) +#define BSC_BACTV_BANK (1) + +#define BSC_PDOWN_INVALID (0) +#define BSC_PDOWN_VALID (1) + +#define BSC_RMODE_AUTO (0) +#define BSC_RMODE_SELF (1) + +#define BSC_RFSH_NONE (0) +#define BSC_RFSH_DONE (1) + +#define BSC_DEEP_SELF (0) +#define BSC_DEEP_DEEP (1) + +#define BSC_PROTECT_KEY (0xA55A0000) + +#define BSC_RFSH_TIME_1 (0) +#define BSC_RFSH_TIME_2 (1) +#define BSC_RFSH_TIME_4 (2) +#define BSC_RFSH_TIME_6 (3) +#define BSC_RFSH_TIME_8 (4) + +#define BSC_CKS_DIV_STOP (0x00000000) +#define BSC_CKS_DIV_4 (0x00000008) +#define BSC_CKS_DIV_16 (0x00000010) +#define BSC_CKS_DIV_64 (0x00000018) +#define BSC_CKS_DIV_256 (0x00000020) +#define BSC_CKS_DIV_1024 (0x00000028) +#define BSC_CKS_DIV_2048 (0x00000030) +#define BSC_CKS_DIV_4096 (0x00000038) + +#define BSC_CMIE_DISABLE (0x00000000) +#define BSC_CMIE_ENABLE (0x00000040) + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_cpg.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_cpg.h new file mode 100644 index 000000000..5dd55d605 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_cpg.h @@ -0,0 +1,83 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_cpg.h +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for CPG function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : CPG setting API of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +#ifndef _R_CPG_HEADER_ +#define _R_CPG_HEADER_ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define CPG_CPUCLK_150_MHz (0) +#define CPG_CPUCLK_300_MHz (1) +#define CPG_CPUCLK_450_MHz (2) +#define CPG_CPUCLK_600_MHz (3) + +#define CPG_PLL1_OFF (0) +#define CPG_PLL1_ON (1) + +#define CPG_SELECT_PLL0 (0) +#define CPG_SELECT_PLL1 (1) + +#define CPG_CKIO_75_MHz (0) +#define CPG_CKIO_50_MHz (1) +#define CPG_CKIO_37_5_MHz (2) +#define CPG_CKIO_30_MHz (3) +#define CPG_CKIO_25_MHz (4) +#define CPG_CKIO_21_43_MHz (5) +#define CPG_CKIO_18_75_MHz (6) + +#define CPG_LOCO_ENABLE (0x00000000) +#define CPG_LOCO_DISABLE (0x00000001) + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void R_CPG_WriteEnable(void); +void R_CPG_WriteDisable(void); +void R_CPG_PLL_Wait(void); + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_ecm.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_ecm.h new file mode 100644 index 000000000..be645eec2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_ecm.h @@ -0,0 +1,72 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_ecm.h +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for ecm function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : ecm function API of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +#ifndef _R_ECM_HEADER_ +#define _R_ECM_HEADER_ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define ECM_COMMAND_KEY (0x000000A5) + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ +typedef enum +{ + ECM_MASTER, + ECM_CHECKER, + ECM_COMMON, + ECM_TYPE_MAX +} ecm_reg_type_t; + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void R_ECM_Init(void); +void R_ECM_CompareError_Wait(void); +uint8_t R_ECM_Write_Reg8(uint8_t reg_type, volatile unsigned char *reg, uint8_t value); +uint8_t R_ECM_Write_Reg32(uint8_t reg_type, volatile unsigned long *reg, uint32_t value); + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_icu_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_icu_init.h new file mode 100644 index 000000000..be11be733 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_icu_init.h @@ -0,0 +1,389 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_icu_init.h +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for ICU init +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : Initialize interrupt controller unit. +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +#ifndef _R_ICU_INIT_HEADER_ +#define _R_ICU_INIT_HEADER_ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +#define ICU_EXT_PIN_0 (0) +#define ICU_EXT_PIN_1 (1) +#define ICU_EXT_PIN_2 (2) +#define ICU_EXT_PIN_3 (3) +#define ICU_EXT_PIN_4 (4) +#define ICU_EXT_PIN_5 (5) +#define ICU_EXT_PIN_6 (6) +#define ICU_EXT_PIN_7 (7) +#define ICU_EXT_PIN_8 (8) +#define ICU_EXT_PIN_9 (9) +#define ICU_EXT_PIN_10 (10) +#define ICU_EXT_PIN_11 (11) +#define ICU_EXT_PIN_12 (12) +#define ICU_EXT_PIN_13 (13) +#define ICU_EXT_PIN_14 (14) +#define ICU_EXT_PIN_15 (15) + +#define ICU_DETECT_LOW (0x00) +#define ICU_DETECT_FALL (0x04) +#define ICU_DETECT_RISE (0x08) +#define ICU_DETECT_RISE_FALL (0x0C) + +#define ICU_DNF_DIVISION_1 (0) +#define ICU_DNF_DIVISION_8 (1) +#define ICU_DNF_DIVISION_32 (2) +#define ICU_DNF_DIVISION_64 (3) +#define ICU_DNF_NO_USE (4) + +#define ICU_VEC_NUM_1 (1) +#define ICU_VEC_NUM_2 (2) +#define ICU_VEC_NUM_3 (3) +#define ICU_VEC_NUM_4 (4) +#define ICU_VEC_NUM_5 (5) +#define ICU_VEC_NUM_6 (6) +#define ICU_VEC_NUM_7 (7) +#define ICU_VEC_NUM_8 (8) +#define ICU_VEC_NUM_9 (9) +#define ICU_VEC_NUM_10 (10) +#define ICU_VEC_NUM_11 (11) +#define ICU_VEC_NUM_12 (12) +#define ICU_VEC_NUM_13 (13) +#define ICU_VEC_NUM_14 (14) +#define ICU_VEC_NUM_15 (15) +#define ICU_VEC_NUM_16 (16) +#define ICU_VEC_NUM_17 (17) +#define ICU_VEC_NUM_18 (18) +#define ICU_VEC_NUM_19 (19) +#define ICU_VEC_NUM_20 (20) +#define ICU_VEC_NUM_21 (21) +#define ICU_VEC_NUM_22 (22) +#define ICU_VEC_NUM_23 (23) +#define ICU_VEC_NUM_24 (24) +#define ICU_VEC_NUM_25 (25) +#define ICU_VEC_NUM_26 (26) +#define ICU_VEC_NUM_27 (27) +#define ICU_VEC_NUM_28 (28) +#define ICU_VEC_NUM_29 (29) +#define ICU_VEC_NUM_30 (30) +#define ICU_VEC_NUM_31 (31) +#define ICU_VEC_NUM_32 (32) +#define ICU_VEC_NUM_33 (33) +#define ICU_VEC_NUM_34 (34) +#define ICU_VEC_NUM_35 (35) +#define ICU_VEC_NUM_36 (36) +#define ICU_VEC_NUM_37 (37) +#define ICU_VEC_NUM_38 (38) +#define ICU_VEC_NUM_39 (39) +#define ICU_VEC_NUM_40 (40) +#define ICU_VEC_NUM_41 (41) +#define ICU_VEC_NUM_42 (42) +#define ICU_VEC_NUM_43 (43) +#define ICU_VEC_NUM_44 (44) +#define ICU_VEC_NUM_45 (45) +#define ICU_VEC_NUM_46 (46) +#define ICU_VEC_NUM_47 (47) +#define ICU_VEC_NUM_48 (48) +#define ICU_VEC_NUM_49 (49) +#define ICU_VEC_NUM_50 (50) +#define ICU_VEC_NUM_51 (51) +#define ICU_VEC_NUM_52 (52) +#define ICU_VEC_NUM_53 (53) +#define ICU_VEC_NUM_54 (54) +#define ICU_VEC_NUM_55 (55) +#define ICU_VEC_NUM_56 (56) +#define ICU_VEC_NUM_57 (57) +#define ICU_VEC_NUM_58 (58) +#define ICU_VEC_NUM_59 (59) +#define ICU_VEC_NUM_60 (60) +#define ICU_VEC_NUM_61 (61) +#define ICU_VEC_NUM_62 (62) +#define ICU_VEC_NUM_63 (63) +#define ICU_VEC_NUM_64 (64) +#define ICU_VEC_NUM_65 (65) +#define ICU_VEC_NUM_66 (66) +#define ICU_VEC_NUM_67 (67) +#define ICU_VEC_NUM_68 (68) +#define ICU_VEC_NUM_69 (69) +#define ICU_VEC_NUM_70 (70) +#define ICU_VEC_NUM_73 (73) +#define ICU_VEC_NUM_74 (74) +#define ICU_VEC_NUM_75 (75) +#define ICU_VEC_NUM_76 (76) +#define ICU_VEC_NUM_77 (77) +#define ICU_VEC_NUM_78 (78) +#define ICU_VEC_NUM_79 (79) +#define ICU_VEC_NUM_80 (80) +#define ICU_VEC_NUM_81 (81) +#define ICU_VEC_NUM_82 (82) +#define ICU_VEC_NUM_83 (83) +#define ICU_VEC_NUM_84 (84) +#define ICU_VEC_NUM_85 (85) +#define ICU_VEC_NUM_86 (86) +#define ICU_VEC_NUM_87 (87) +#define ICU_VEC_NUM_88 (88) +#define ICU_VEC_NUM_89 (89) +#define ICU_VEC_NUM_90 (90) +#define ICU_VEC_NUM_91 (91) +#define ICU_VEC_NUM_92 (92) +#define ICU_VEC_NUM_93 (93) +#define ICU_VEC_NUM_94 (94) +#define ICU_VEC_NUM_95 (95) +#define ICU_VEC_NUM_96 (96) +#define ICU_VEC_NUM_97 (97) +#define ICU_VEC_NUM_98 (98) +#define ICU_VEC_NUM_99 (99) +#define ICU_VEC_NUM_100 (100) +#define ICU_VEC_NUM_101 (101) +#define ICU_VEC_NUM_102 (102) +#define ICU_VEC_NUM_103 (103) +#define ICU_VEC_NUM_104 (104) +#define ICU_VEC_NUM_105 (105) +#define ICU_VEC_NUM_106 (106) +#define ICU_VEC_NUM_107 (107) +#define ICU_VEC_NUM_108 (108) +#define ICU_VEC_NUM_109 (109) +#define ICU_VEC_NUM_110 (110) +#define ICU_VEC_NUM_111 (111) +#define ICU_VEC_NUM_112 (112) +#define ICU_VEC_NUM_113 (113) +#define ICU_VEC_NUM_114 (114) +#define ICU_VEC_NUM_115 (115) +#define ICU_VEC_NUM_116 (116) +#define ICU_VEC_NUM_117 (117) +#define ICU_VEC_NUM_118 (118) +#define ICU_VEC_NUM_119 (119) +#define ICU_VEC_NUM_120 (120) +#define ICU_VEC_NUM_121 (121) +#define ICU_VEC_NUM_122 (122) +#define ICU_VEC_NUM_123 (123) +#define ICU_VEC_NUM_124 (124) +#define ICU_VEC_NUM_125 (125) +#define ICU_VEC_NUM_126 (126) +#define ICU_VEC_NUM_127 (127) +#define ICU_VEC_NUM_128 (128) +#define ICU_VEC_NUM_145 (145) +#define ICU_VEC_NUM_146 (146) +#define ICU_VEC_NUM_147 (147) +#define ICU_VEC_NUM_148 (148) +#define ICU_VEC_NUM_149 (149) +#define ICU_VEC_NUM_150 (150) +#define ICU_VEC_NUM_151 (151) +#define ICU_VEC_NUM_152 (152) +#define ICU_VEC_NUM_153 (153) +#define ICU_VEC_NUM_154 (154) +#define ICU_VEC_NUM_155 (155) +#define ICU_VEC_NUM_156 (156) +#define ICU_VEC_NUM_157 (157) +#define ICU_VEC_NUM_158 (158) +#define ICU_VEC_NUM_159 (159) +#define ICU_VEC_NUM_160 (160) +#define ICU_VEC_NUM_161 (161) +#define ICU_VEC_NUM_162 (162) +#define ICU_VEC_NUM_163 (163) +#define ICU_VEC_NUM_164 (164) +#define ICU_VEC_NUM_165 (165) +#define ICU_VEC_NUM_166 (166) +#define ICU_VEC_NUM_167 (167) +#define ICU_VEC_NUM_168 (168) +#define ICU_VEC_NUM_169 (169) +#define ICU_VEC_NUM_170 (170) +#define ICU_VEC_NUM_171 (171) +#define ICU_VEC_NUM_172 (172) +#define ICU_VEC_NUM_173 (173) +#define ICU_VEC_NUM_174 (174) +#define ICU_VEC_NUM_175 (175) +#define ICU_VEC_NUM_176 (176) +#define ICU_VEC_NUM_177 (177) +#define ICU_VEC_NUM_178 (178) +#define ICU_VEC_NUM_179 (179) +#define ICU_VEC_NUM_180 (180) +#define ICU_VEC_NUM_181 (181) +#define ICU_VEC_NUM_182 (182) +#define ICU_VEC_NUM_183 (183) +#define ICU_VEC_NUM_184 (184) +#define ICU_VEC_NUM_185 (185) +#define ICU_VEC_NUM_186 (186) +#define ICU_VEC_NUM_187 (187) +#define ICU_VEC_NUM_188 (188) +#define ICU_VEC_NUM_189 (189) +#define ICU_VEC_NUM_190 (190) +#define ICU_VEC_NUM_191 (191) +#define ICU_VEC_NUM_192 (192) +#define ICU_VEC_NUM_193 (193) +#define ICU_VEC_NUM_194 (194) +#define ICU_VEC_NUM_195 (195) +#define ICU_VEC_NUM_196 (196) +#define ICU_VEC_NUM_197 (197) +#define ICU_VEC_NUM_198 (198) +#define ICU_VEC_NUM_199 (199) +#define ICU_VEC_NUM_200 (200) +#define ICU_VEC_NUM_201 (201) +#define ICU_VEC_NUM_202 (202) +#define ICU_VEC_NUM_203 (203) +#define ICU_VEC_NUM_204 (204) +#define ICU_VEC_NUM_205 (205) +#define ICU_VEC_NUM_206 (206) +#define ICU_VEC_NUM_207 (207) +#define ICU_VEC_NUM_208 (208) +#define ICU_VEC_NUM_209 (209) +#define ICU_VEC_NUM_210 (210) +#define ICU_VEC_NUM_211 (211) +#define ICU_VEC_NUM_212 (212) +#define ICU_VEC_NUM_213 (213) +#define ICU_VEC_NUM_214 (214) +#define ICU_VEC_NUM_215 (215) +#define ICU_VEC_NUM_216 (216) +#define ICU_VEC_NUM_217 (217) +#define ICU_VEC_NUM_218 (218) +#define ICU_VEC_NUM_219 (219) +#define ICU_VEC_NUM_220 (220) +#define ICU_VEC_NUM_221 (221) +#define ICU_VEC_NUM_222 (222) +#define ICU_VEC_NUM_223 (223) +#define ICU_VEC_NUM_224 (224) +#define ICU_VEC_NUM_225 (225) +#define ICU_VEC_NUM_226 (226) +#define ICU_VEC_NUM_227 (227) +#define ICU_VEC_NUM_228 (228) +#define ICU_VEC_NUM_229 (229) +#define ICU_VEC_NUM_230 (230) +#define ICU_VEC_NUM_231 (231) +#define ICU_VEC_NUM_232 (232) +#define ICU_VEC_NUM_233 (233) +#define ICU_VEC_NUM_234 (234) +#define ICU_VEC_NUM_235 (235) +#define ICU_VEC_NUM_236 (236) +#define ICU_VEC_NUM_237 (237) +#define ICU_VEC_NUM_238 (238) +#define ICU_VEC_NUM_239 (239) +#define ICU_VEC_NUM_240 (240) +#define ICU_VEC_NUM_241 (241) +#define ICU_VEC_NUM_242 (242) +#define ICU_VEC_NUM_243 (243) +#define ICU_VEC_NUM_246 (246) +#define ICU_VEC_NUM_247 (247) +#define ICU_VEC_NUM_248 (248) +#define ICU_VEC_NUM_249 (249) +#define ICU_VEC_NUM_250 (250) +#define ICU_VEC_NUM_251 (251) +#define ICU_VEC_NUM_252 (252) +#define ICU_VEC_NUM_254 (254) +#define ICU_VEC_NUM_256 (256) +#define ICU_VEC_NUM_257 (257) +#define ICU_VEC_NUM_258 (258) +#define ICU_VEC_NUM_259 (259) +#define ICU_VEC_NUM_260 (260) +#define ICU_VEC_NUM_261 (261) +#define ICU_VEC_NUM_262 (262) +#define ICU_VEC_NUM_263 (263) +#define ICU_VEC_NUM_264 (264) +#define ICU_VEC_NUM_265 (265) +#define ICU_VEC_NUM_266 (266) +#define ICU_VEC_NUM_267 (267) +#define ICU_VEC_NUM_268 (268) +#define ICU_VEC_NUM_269 (269) +#define ICU_VEC_NUM_270 (270) +#define ICU_VEC_NUM_271 (271) +#define ICU_VEC_NUM_272 (272) +#define ICU_VEC_NUM_273 (273) +#define ICU_VEC_NUM_274 (274) +#define ICU_VEC_NUM_275 (275) +#define ICU_VEC_NUM_276 (276) +#define ICU_VEC_NUM_277 (277) +#define ICU_VEC_NUM_278 (278) +#define ICU_VEC_NUM_279 (279) +#define ICU_VEC_NUM_280 (280) +#define ICU_VEC_NUM_281 (281) +#define ICU_VEC_NUM_282 (282) +#define ICU_VEC_NUM_283 (283) +#define ICU_VEC_NUM_284 (284) +#define ICU_VEC_NUM_285 (285) +#define ICU_VEC_NUM_286 (286) +#define ICU_VEC_NUM_287 (287) +#define ICU_VEC_NUM_288 (288) +#define ICU_VEC_NUM_289 (289) +#define ICU_VEC_NUM_290 (290) +#define ICU_VEC_NUM_291 (291) +#define ICU_VEC_NUM_292 (292) +#define ICU_VEC_NUM_293 (293) +#define ICU_VEC_NUM_294 (294) + +#define ICU_TYPE_LEVEL (0) +#define ICU_TYPE_EDGE (1) + +#define ICU_PRIORITY_0 (0) +#define ICU_PRIORITY_1 (1) +#define ICU_PRIORITY_2 (2) +#define ICU_PRIORITY_3 (3) +#define ICU_PRIORITY_4 (4) +#define ICU_PRIORITY_5 (5) +#define ICU_PRIORITY_6 (6) +#define ICU_PRIORITY_7 (7) +#define ICU_PRIORITY_8 (8) +#define ICU_PRIORITY_9 (9) +#define ICU_PRIORITY_10 (10) +#define ICU_PRIORITY_11 (11) +#define ICU_PRIORITY_12 (12) +#define ICU_PRIORITY_13 (13) +#define ICU_PRIORITY_14 (14) +#define ICU_PRIORITY_15 (15) + +#define ICU_IEC_MASK_SET (1) + +#define ICU_PIC_EDGE_CLEAR (1) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void R_ICU_Disable(uint32_t vec_num); +void R_ICU_Enable(uint32_t vec_num); +void R_ICU_ExtPinInit(uint16_t pin_num, uint8_t detect, uint32_t dnf_set); +void R_ICU_Regist(uint32_t vec_num, uint32_t type, uint32_t priority, uint32_t isr_addr); +void R_ICU_Disable(uint32_t vec_num); +void R_ICU_Enable(uint32_t vec_num); + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_mpc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_mpc.h new file mode 100644 index 000000000..cd9d589b8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_mpc.h @@ -0,0 +1,118 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_mpc.h +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for MPC function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : MPC setting API of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +#ifndef _R_MPC_HEADER_ +#define _R_MPC_HEADER_ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define MPC_IRQ_DISABLE (0) +#define MPC_IRQ_ENABLE (1) + +#define MPC_PSEL_PT6_A21 (0x23) +#define MPC_PSEL_PT7_A22 (0x23) +#define MPC_PSEL_PK2_A23 (0x23) +#define MPC_PSEL_PK3_A24 (0x23) +#define MPC_PSEL_P97_A25 (0x23) +#define MPC_PSEL_P36_WE0_DQMLL (0x22) +#define MPC_PSEL_P37_WE1_DQMLU (0x22) +#define MPC_PSEL_PD1_CS1 (0x23) +#define MPC_PSEL_P45_CS2 (0x22) +#define MPC_PSEL_PT4_CS3 (0x23) +#define MPC_PSEL_P90_RAS (0x23) +#define MPC_PSEL_PK0_CAS (0x23) +#define MPC_PSEL_P24_RD_WR (0x22) +#define MPC_PSEL_P46_CKE (0x22) +#define MPC_PSEL_P10_CKIO (0x22) +#define MPC_PSEL_P23_A0 (0x22) +#define MPC_PSEL_PG0_A1 (0x22) +#define MPC_PSEL_PG1_A2 (0x22) +#define MPC_PSEL_PG2_A3 (0x22) +#define MPC_PSEL_PG3_A4 (0x22) +#define MPC_PSEL_PG4_A5 (0x22) +#define MPC_PSEL_PG5_A6 (0x22) +#define MPC_PSEL_PG6_A7 (0x22) +#define MPC_PSEL_PG7_A8 (0x22) +#define MPC_PSEL_PH0_A9 (0x22) +#define MPC_PSEL_PH1_A10 (0x22) +#define MPC_PSEL_PH2_A11 (0x22) +#define MPC_PSEL_PH3_A12 (0x22) +#define MPC_PSEL_PH4_A13 (0x22) +#define MPC_PSEL_PH5_A14 (0x22) +#define MPC_PSEL_PH6_A15 (0x22) +#define MPC_PSEL_PH7_A16 (0x22) +#define MPC_PSEL_P20_A17 (0x22) +#define MPC_PSEL_P25_A18 (0x22) +#define MPC_PSEL_P26_A19 (0x22) +#define MPC_PSEL_P27_A20 (0x22) +#define MPC_PSEL_P00_D0 (0x22) +#define MPC_PSEL_P01_D1 (0x22) +#define MPC_PSEL_P02_D2 (0x22) +#define MPC_PSEL_P03_D3 (0x22) +#define MPC_PSEL_P04_D4 (0x22) +#define MPC_PSEL_P05_D5 (0x22) +#define MPC_PSEL_P06_D6 (0x22) +#define MPC_PSEL_P07_D7 (0x22) +#define MPC_PSEL_PE0_D8 (0x22) +#define MPC_PSEL_PE1_D9 (0x22) +#define MPC_PSEL_PE2_D10 (0x22) +#define MPC_PSEL_PE3_D11 (0x22) +#define MPC_PSEL_PE4_D12 (0x22) +#define MPC_PSEL_PE5_D13 (0x22) +#define MPC_PSEL_PE6_D14 (0x22) +#define MPC_PSEL_PE7_D15 (0x22) +#define MPC_PSEL_P22_RD (0x22) +#define MPC_PSEL_P21_CS0 (0x22) + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void R_MPC_WriteEnable(void); +void R_MPC_WriteDisable(void); + + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_port.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_port.h new file mode 100644 index 000000000..0142e5309 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_port.h @@ -0,0 +1,76 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_port.h +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for PORT function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : PORT setting API of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +#ifndef _R_PORT_HEADER_ +#define _R_PORT_HEADER_ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define PORT_DIRECTION_HIZ (0) +#define PORT_DIRECTION_INPUT (2) +#define PORT_DIRECTION_OUTPUT (3) + +#define PORT_OUTPUT_LOW (0) +#define PORT_OUTPUT_HIGH (1) + +#define PORT_MODE_GENERAL (0) +#define PORT_MODE_PERIPHERAL (1) + +#define PORT_PULL_UPDOWN_DISABLE (0) +#define PORT_PULL_DOWN (1) +#define PORT_PULL_UP (2) + +#define PORT_P10_NORMAL_DRIVE (0) +#define PORT_P10_HIGH_DRIVE (1) + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_ram_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_ram_init.h new file mode 100644 index 000000000..abcf59702 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_ram_init.h @@ -0,0 +1,64 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_ram.h +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for internal extended RAM function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : Internal extended RAM setting API of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +#ifndef _R_RAM_HEADER_ +#define _R_RAM_HEADER_ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void R_RAM_Init(void); +void R_RAM_ECC_Enable(void); +void R_RAM_WriteEnable(void); +void R_RAM_WriteDisable(void); + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_reset.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_reset.h new file mode 100644 index 000000000..06f6e3438 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_reset.h @@ -0,0 +1,64 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_reset.h +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for reset function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : Reset function API of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +#ifndef _R_RESET_HEADER_ +#define _R_RESET_HEADER_ + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define RST_SOURCE_RES (0x00000002) +#define RST_SOURCE_ECM (0x00000004) +#define RST_SOURCE_SWR1 (0x00000008) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ +void r_rst_write_enable(void); +void r_rst_write_disable(void); + +#endif + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_system.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_system.h new file mode 100644 index 000000000..9278ef210 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_system.h @@ -0,0 +1,116 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_system.h +* Version : 0.1 +* Device : R7S9100xx +* Abstract : Definition for System +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : Define the system settings ans value. +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +#ifndef _R_SYSTEM_HEADER_ +#define _R_SYSTEM_HEADER_ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPCRA0 +#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPCRA1 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPCRA2 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPCRA3 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPCRA4 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPCRA5 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPCRA6 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPCRA7 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPCRA8 +#define MSTP_GPTA SYSTEM.MSTPCRA.BIT.MSTPCRA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPCRA11 + +#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPCRB1 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPCRB2 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPCRB3 +#define MSTP_SCIFA4 SYSTEM.MSTPCRB.BIT.MSTPCRB5 +#define MSTP_SCIFA3 SYSTEM.MSTPCRB.BIT.MSTPCRB6 +#define MSTP_SCIFA2 SYSTEM.MSTPCRB.BIT.MSTPCRB7 +#define MSTP_SCIFA1 SYSTEM.MSTPCRB.BIT.MSTPCRB8 +#define MSTP_SCIFA0 SYSTEM.MSTPCRB.BIT.MSTPCRB9 +#define MSTP_RSPI3 SYSTEM.MSTPCRB.BIT.MSTPCRB10 +#define MSTP_RSPI2 SYSTEM.MSTPCRB.BIT.MSTPCRB11 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPCRB12 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPCRB13 +#define MSTP_ETHERSW SYSTEM.MSTPCRB.BIT.MSTPCRB14 +#define MSTP_ECATC SYSTEM.MSTPCRB.BIT.MSTPCRB15 +#define MSTP_EMDIO SYSTEM.MSTPCRB.BIT.MSTPCRB16 +#define MSTP_ERMII SYSTEM.MSTPCRB.BIT.MSTPCRB17 +#define MSTP_HWRTOS SYSTEM.MSTPCRB.BIT.MSTPCRB18 +#define MSTP_CLKOUT25M SYSTEM.MSTPCRB.BIT.MSTPCRB19 + +#define MSTP_USB SYSTEM.MSTPCRC.BIT.MSTPCRC1 +#define MSTP_DSMIF SYSTEM.MSTPCRC.BIT.MSTPCRC2 +#define MSTP_TEMPS SYSTEM.MSTPCRC.BIT.MSTPCRC3 +#define MSTP_S12ADC1 SYSTEM.MSTPCRC.BIT.MSTPCRC4 +#define MSTP_S12ADC0 SYSTEM.MSTPCRC.BIT.MSTPCRC5 +#define MSTP_ELC SYSTEM.MSTPCRC.BIT.MSTPCRC6 +#define MSTP_BSC SYSTEM.MSTPCRC.BIT.MSTPCRC7 +#define MSTP_CKIO SYSTEM.MSTPCRC.BIT.MSTPCRC8 +#define MSTP_SPIBSC SYSTEM.MSTPCRC.BIT.MSTPCRC9 +#define MSTP_DOC SYSTEM.MSTPCRC.BIT.MSTPCRC10 +#define MSTP_CRC SYSTEM.MSTPCRC.BIT.MSTPCRC11 +#define MSTP_CLMA2 SYSTEM.MSTPCRC.BIT.MSTPCRC12 +#define MSTP_CLMA1 SYSTEM.MSTPCRC.BIT.MSTPCRC13 +#define MSTP_CLMA0 SYSTEM.MSTPCRC.BIT.MSTPCRC14 + +#define MSTP_SSI SYSTEM.MSTPCRD.BIT.MSTPCRD2 + +#define MSTP_DMAC1 SYSTEM.MSTPCRE.BIT.MSTPCRE4 +#define MSTP_DMAC0 SYSTEM.MSTPCRE.BIT.MSTPCRE5 + +#define MSTP_CORESIGHT SYSTEM.MSTPCRF.BIT.MSTPCRF0 + +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +#endif // End _R_SYSTEM_HEADER_ + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_typedefs.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_typedefs.h new file mode 100644 index 000000000..a4a339423 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/inc/r_typedefs.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* File Name : r_typedefs.h +* Device(s) : RZ/A1H (R7S910018) +* Tool-Chain : GNUARM-NONEv14.02-EABI +* H/W Platform : RSK+T1 CPU Board +* Description : basic type definition +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* History : DD.MM.YYYY Version Description +* : 21.10.2014 1.00 +***********************************************************************************************************************/ + + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include +/* Multiple inclusion prevention macro */ +#ifndef R_TYPEDEFS_H +#define R_TYPEDEFS_H + + +/* in case has defined it. */ +#ifndef NULL +#define NULL (0) +#endif + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#if !defined(__bool_true_false_are_defined) && !defined(__cplusplus) + +#define FALSE (0) +#define TRUE (1) + +#endif + +/* These two macros are used to suppress warnings generated by unused variables. + Writing to some registers require a read instruction following the write. + A dummy variable is declared and used to read the register written to. */ +#define UNUSED_PARAM(param) ((void)(param)) +#define UNUSED_VARIABLE(param) ((void)(param)) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +typedef char char_t; +typedef unsigned int bool_t; +typedef int int_t; +typedef float float32_t; +typedef double float64_t; +typedef long double float128_t; + +/* R_TYPEDEFS_H */ +#endif + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/RZ_T1_init.icf b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/RZ_T1_init.icf new file mode 100644 index 000000000..2e86388b6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/RZ_T1_init.icf @@ -0,0 +1,163 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x40020040; +define symbol __ICFEDIT_region_ROM_end__ = 0x4008FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x00070000; +define symbol __ICFEDIT_region_RAM_end__ = 0x0007FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_svcstack__ = 0x200; +define symbol __ICFEDIT_size_irqstack__ = 0x100; +define symbol __ICFEDIT_size_fiqstack__ = 0x100; +define symbol __ICFEDIT_size_undstack__ = 0x100; +define symbol __ICFEDIT_size_abtstack__ = 0x100; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __region_USER_PRG_start__ = 0x00000040; +define symbol __region_USER_PRG_end__ = 0x0006FFFF; + +define symbol __region_D_LDR_DATA_start__ = 0x00800000; +define symbol __region_D_LDR_DATA_end__ = 0x00801FFF; +define symbol __region_D_LDR_PRG_start__ = 0x00802000; +define symbol __region_D_LDR_PRG_end__ = 0x00807FFF; + +define symbol __region_D_LDR_M3PRG_start__ = 0x04000000; +define symbol __region_D_LDR_M3PRG_end__ = 0x0407FFFF; + +define symbol __region_S_LDR_M3PRG_start__ = 0x00050000; +define symbol __region_S_LDR_M3PRG_end__ = 0x0006FFFF; + +define symbol __region_EXT_RAM1_start__ = 0x22000000; +define symbol __region_EXT_RAM1_end__ = 0x2207FFFF; +define symbol __region_EXT_RAM2_start__ = 0x24000000; +define symbol __region_EXT_RAM2_end__ = 0x2407FFFF; +define symbol __region_SPIBSC_start__ = 0x30000000; +define symbol __region_SPIBSC_end__ = 0x33FFFFFF; + +define symbol __region_CS0_start__ = 0x40000000; +define symbol __region_CS0_end__ = 0x43FFFFFF; +define symbol __region_CS1_start__ = 0x44000000; +define symbol __region_CS1_end__ = 0x47FFFFFF; +define symbol __region_CS2_start__ = 0x48000000; +define symbol __region_CS2_end__ = 0x4BFFFFFF; +define symbol __region_CS3_start__ = 0x4C000000; +define symbol __region_CS3_end__ = 0x4FFFFFFF; +define symbol __region_CS4_start__ = 0x50000000; +define symbol __region_CS4_end__ = 0x53FFFFFF; +define symbol __region_CS5_start__ = 0x54000000; +define symbol __region_CS5_end__ = 0x57FFFFFF; + +define region USER_PRG_region = mem:[from __region_USER_PRG_start__ to __region_USER_PRG_end__]; +define region D_LDR_DATA_region = mem:[from __region_D_LDR_DATA_start__ to __region_D_LDR_DATA_end__]; +define region D_LDR_PRG_region = mem:[from __region_D_LDR_PRG_start__ to __region_D_LDR_PRG_end__]; + +define region D_LDR_M3PRG_region = mem:[from __region_D_LDR_M3PRG_start__ to __region_D_LDR_M3PRG_end__]; +define region S_LDR_M3PRG_region = mem:[from __region_S_LDR_M3PRG_start__ to __region_S_LDR_M3PRG_end__]; + +define region EXT_RAM1_region = mem:[from __region_EXT_RAM1_start__ to __region_EXT_RAM1_end__]; +define region EXT_RAM2_region = mem:[from __region_EXT_RAM2_start__ to __region_EXT_RAM2_end__]; +define region SPIBSC_region = mem:[from __region_SPIBSC_start__ to __region_SPIBSC_end__]; +define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__]; +define region CS1_region = mem:[from __region_CS1_start__ to __region_CS1_end__]; +define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__]; +define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__]; +define region CS4_region = mem:[from __region_CS4_start__ to __region_CS4_end__]; +define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + + +define block LDR_PRG_RBLOCK with fixed order + { ro code object loader_init.o, + ro code object loader_init2.o, + ro code object r_atcm_init.o, + ro code object r_cpg.o, + ro code object r_ram_init.o, + ro code object r_mpc.o, + ro code object r_reset.o, + ro code object data_init.o, + ro code object copy_init3.o }; +define block LDR_DATA_ZBLOCK { section .bss object loader_init.o, + section .bss object loader_init2.o, + section .bss object r_atcm_init.o, + section .bss object r_cpg.o, + section .bss object r_ram_init.o, + section .bss object r_mpc.o, + section .bss object r_reset.o, + section .bss object data_init.o, + section .bss object copy_init3.o }; +define block LDR_DATA_RBLOCK { section .data_init object loader_init.o, + section .data_init object loader_init2.o, + section .data_init object r_atcm_init.o, + section .data_init object r_cpg.o, + section .data_init object r_ram_init.o, + section .data_init object r_mpc.o, + section .data_init object r_reset.o, + section .data_init object data_init.o, + section .data_init object copy_init3.o }; +define block LDR_DATA_WBLOCK { section .data object loader_init.o, + section .data object loader_init2.o, + section .data object r_atcm_init.o, + section .data object r_cpg.o, + section .data object r_ram_init.o, + section .data object r_mpc.o, + section .data object r_reset.o, + section .data object data_init.o, + section .data object copy_init3.o }; +define block VECTOR_RBLOCK { ro code object vector.o }; +define block USER_PRG_RBLOCK { ro code }; +define block USER_DATA_ZBLOCK { section .bss }; +define block USER_DATA_RBLOCK { section .data_init }; +define block USER_DATA_WBLOCK { section .data }; + +define block M3_PRG_RBLOCK { section __M3prg_init }; +define block M3_PRG_WBLOCK { section __M3prg }; + +initialize by copy { readwrite }; + +do not initialize { section .noinit, section .bss }; + +initialize manually { section __M3prg }; + +place at address mem:__ICFEDIT_intvec_start__ { block VECTOR_RBLOCK }; + +place in USER_PRG_region { block USER_PRG_RBLOCK, + block USER_DATA_RBLOCK, + readonly }; +place in RAM_region { readwrite }; +place in RAM_region { block USER_DATA_WBLOCK, + block USER_DATA_ZBLOCK, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; +place in D_LDR_DATA_region { block LDR_DATA_WBLOCK, block LDR_DATA_ZBLOCK }; +place in D_LDR_PRG_region { block LDR_PRG_RBLOCK, + block LDR_DATA_RBLOCK }; + +place in S_LDR_M3PRG_region { block M3_PRG_RBLOCK }; +place in D_LDR_M3PRG_region { block M3_PRG_WBLOCK }; + +place in EXT_RAM1_region {}; +place in EXT_RAM2_region {}; +place in SPIBSC_region {}; +place in CS0_region {}; +place in CS1_region {}; +place in CS2_region {}; +place in CS3_region {}; +place in CS4_region {}; +place in CS5_region {}; diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/exit.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/exit.c new file mode 100644 index 000000000..19b107e4b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/exit.c @@ -0,0 +1,84 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : exit.c +* Version : 0.1 +* Device : R7S9100xx +* Abstract : exit program +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : exit sequence from main function +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + +/******************************************************************************* +Private variables and functions +*******************************************************************************/ + +/******************************************************************************* +* Outline : exit processing +* Function Name: __exit +* Description : exit sequence from main function. +* Arguments : code +* The return value of main function. +* Return Value : none +*******************************************************************************/ +void __exit(int code) +{ + + while (1) + { + /* Please describe the exit sequence */ + } + +} +/******************************************************************************* + End of function __exit +*******************************************************************************/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/loader_init.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/loader_init.asm new file mode 100644 index 000000000..fe8b0fe71 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/loader_init.asm @@ -0,0 +1,371 @@ +;******************************************************************************* +; DISCLAIMER +; This software is supplied by Renesas Electronics Corporation and is only +; intended for use with Renesas products. No other uses are authorized. This +; software is owned by Renesas Electronics Corporation and is protected under +; all applicable laws, including copyright laws. +; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +; LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +; AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +; TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +; ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +; FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +; ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; Renesas reserves the right, without notice, to make changes to this software +; and to discontinue the availability of this software. By using this software, +; you agree to the additional terms and conditions found by accessing the +; following link: +; http://www.renesas.com/disclaimer +; +; Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +;****************************************************************************** +;******************************************************************************* +; System Name : RZ/T1 Init program +; File Name : loader_init.asm +; Version : 0.1 +; Device : R7S9100xx +; Abstract : Loader program 1 +; Tool-Chain : IAR Embedded Workbench Ver.7.20 +; OS : not use +; H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +; Description : Description interrupt service routine of RZ/T1 +; Limitation : none +;****************************************************************************** +;******************************************************************************* +; History : DD.MM.YYYY Version Description +; : First Release +;****************************************************************************** + + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + + SECTION LDR_DATA_RBLOCK:DATA:ROOT(2) + SECTION LDR_DATA_WBLOCK:DATA:ROOT(2) + + SECTION M3_PRG_RBLOCK:DATA:ROOT(2) + SECTION M3_PRG_WBLOCK:DATA:ROOT(2) + +; This program is allocated to section "d_ldr_prg" + SECTION d_ldr_prg:CODE:ROOT(2) + + ARM + + PUBLIC loader_init1 + PUBLIC set_low_vec + PUBLIC cache_init + PUBLIC mpu_init + IMPORT loader_init2 + + +;*********************************************************************** +; Function Name : loader_init1 +; Description : Initialize sysytem by loader program +; Arguments : none +; Return Value : none +;*********************************************************************** +loader_init1: + +stack_init: + ; Stack setting + cps #17 ; FIQ mode + ldr sp, =SFE(FIQ_STACK) + cps #18 ; IRQ mode + ldr sp, =SFE(IRQ_STACK) + cps #23 ; Abort mode + ldr sp, =SFE(ABT_STACK) + cps #27 ; Undef mode + ldr sp, =SFE(UND_STACK) + cps #31 ; System mode + ldr sp, =SFE(CSTACK) + cps #19 ; SVC mode + ldr sp, =SFE(SVC_STACK) + +vfp_init: + ; Initialize VFP setting + mrc p15, #0, r0, c1, c0, #2 ; Enables cp10 and cp11 accessing + orr r0, r0, #0xF00000 + mcr p15, #0, r0, c1, c0, #2 + isb ; Ensuring Context-changing + + mov r0, #0x40000000 ; Enables VFP operation + vmsr fpexc, r0 + +data_init: + ; Initialize variables has initialized value of loader_init2. + ; Variables has no initialized value already be initialized to zero + ; in boot sequence(Clear ATCM and BTCM). + ldr r0, =SFB(LDR_DATA_RBLOCK) + ldr r1, =SFB(LDR_DATA_WBLOCK) + ldr r2, =SIZEOF(LDR_DATA_WBLOCK) + cmp r2, #0 +#ifdef DUAL_CORE + beq m3_init +#else + beq jump_loader_init2 +#endif + +copy_to_LDR_DATA: + ldrb r3, [r0], #1 + strb r3, [r1], #1 + subs r2, r2, #1 + bne copy_to_LDR_DATA + dsb ; Ensuring data-changing + +#ifdef DUAL_CORE + +m3_init: + ; Initialize image for Cortex-M3 core + ldr r0, =SFB(M3_PRG_RBLOCK) + ldr r1, =SFB(M3_PRG_WBLOCK) + ldr r2, =SIZEOF(M3_PRG_WBLOCK) + cmp r2, #0 + beq jump_loader_init2 + +copy_to_M3_PRG: + ldrb r3, [r0], #1 + strb r3, [r1], #1 + subs r2, r2, #1 + bne copy_to_M3_PRG + dsb ; Ensuring data-changing + +#endif + + ; Jump to loader_init2 +jump_loader_init2: + ldr r0, =loader_init2 + bx r0 + +;*********************************************************************** +; Function Name : cache_init +; Description : Initialize I1, D1 cache and MPU settings +; Arguments : none +; Return Value : none +;*********************************************************************** + +;******************************************************************************* +; Macro definitions +;******************************************************************************* + +SCTLR_BR: dcd 0x00020000 +SCTLR_M: dcd 0x00000001 +SCTLR_I_C: dcd 0x00001004 + +DRBAR_REGION_0: dcd 0x04000000 ; Base address = 0400_0000h +DRACR_REGION_0: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share +DRSR_REGION_0: dcd 0x00000025 ; Size 512KB, MPU enable + +DRBAR_REGION_1: dcd 0x10000000 ; Base address = 1000_0000h +DRACR_REGION_1: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share +DRSR_REGION_1: dcd 0x00000033 ; Size 64MB, MPU enable + +DRBAR_REGION_2: dcd 0x20000000 ; Base address = 2000_0000h +DRACR_REGION_2: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share +DRSR_REGION_2: dcd 0x00000025 ; Size 512KB, MPU enable + +DRBAR_REGION_3: dcd 0x22000000 ; Base address = 2200_0000h +DRACR_REGION_3: dcd 0x00000307 ; R/W(full), Normal, Write-back no allocate, share +DRSR_REGION_3: dcd 0x00000033 ; Size 64MB, MPU enable + +DRBAR_REGION_4: dcd 0x30000000 ; Base address = 3000_0000h +DRACR_REGION_4: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share +DRSR_REGION_4: dcd 0x00000033 ; Size 64MB, MPU enable + +DRBAR_REGION_5: dcd 0x40000000 ; Base address = 4000_0000h +DRACR_REGION_5: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share +DRSR_REGION_5: dcd 0x00000035 ; Size 128MB, MPU enable + +DRBAR_REGION_6: dcd 0x48000000 ; Base address = 4800_0000h +DRACR_REGION_6: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share +DRSR_REGION_6: dcd 0x00000035 ; Size 128MB, MPU enable + +DRBAR_REGION_7: dcd 0x50000000 ; Base address = 5000_0000h +DRACR_REGION_7: dcd 0x00001305 ; R/W(full), XN, Device, share +DRSR_REGION_7: dcd 0x00000035 ; Size 128MB, MPU enable + +DRBAR_REGION_8: dcd 0x60000000 ; Base address = 6000_0000h +DRACR_REGION_8: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share +DRSR_REGION_8: dcd 0x00000035 ; Size 128MB, MPU enable + +DRBAR_REGION_9: dcd 0x68000000 ; Base address = 6800_0000h +DRACR_REGION_9: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share +DRSR_REGION_9: dcd 0x00000035 ; Size 128MB, MPU enable + +DRBAR_REGION_10: dcd 0x70000000 ; Base address = 7000_0000h +DRACR_REGION_10: dcd 0x00001305 ; R/W(full), XN, Device, share +DRSR_REGION_10: dcd 0x00000035 ; Size 128MB, MPU enable + +DRBAR_REGION_11: dcd 0x80000000 ; Base address = 8000_0000h +DRACR_REGION_11: dcd 0x00001305 ; R/W(full), XN, Device, share +DRSR_REGION_11: dcd 0x0000003D ; Size 2GB, MPU enable + +cache_init: + push {lr} + +cache_invalidate: + ; Invalidate the I1, D1 cache + mov r0, #0 + mcr p15, #0, r0, c7, c5, #0 ; Invalidate all Instruction Caches (Write-value is Ignored) + isb ; Ensuring Context-changing + mcr p15, #0, r0, c15, c5, #0 ; Invalidate all Data Caches (Write-value is Ignored) + isb ; Ensuring Context-changing + + ; Adopt default memory map as background map. + ldr r0, SCTLR_BR ; Set SCTLR.BR bit to 1 + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, r0 + dsb + mcr p15, 0, r1, c1, c0, 0 + isb ; Ensuring Context-changing + + ; Initialize MPU settings (region 0 to 11) + ; Define region 0 + mov r0, #0 + ldr r1, DRBAR_REGION_0 + ldr r2, DRACR_REGION_0 + ldr r3, DRSR_REGION_0 + bl mpu_init + + ; Define region 1 + mov r0, #1 + ldr r1, DRBAR_REGION_1 + ldr r2, DRACR_REGION_1 + ldr r3, DRSR_REGION_1 + bl mpu_init + + ; Define region 2 + mov r0, #2 + ldr r1, DRBAR_REGION_2 + ldr r2, DRACR_REGION_2 + ldr r3, DRSR_REGION_2 + bl mpu_init + + ; Define region 3 + mov r0, #3 + ldr r1, DRBAR_REGION_3 + ldr r2, DRACR_REGION_3 + ldr r3, DRSR_REGION_3 + bl mpu_init + + ; Define region 4 + mov r0, #4 + ldr r1, DRBAR_REGION_4 + ldr r2, DRACR_REGION_4 + ldr r3, DRSR_REGION_4 + bl mpu_init + + ; Define region 5 + mov r0, #5 + ldr r1, DRBAR_REGION_5 + ldr r2, DRACR_REGION_5 + ldr r3, DRSR_REGION_5 + bl mpu_init + + ; Define region 6 + mov r0, #6 + ldr r1, DRBAR_REGION_6 + ldr r2, DRACR_REGION_6 + ldr r3, DRSR_REGION_6 + bl mpu_init + + ; Define region 7 + mov r0, #7 + ldr r1, DRBAR_REGION_7 + ldr r2, DRACR_REGION_7 + ldr r3, DRSR_REGION_7 + bl mpu_init + + ; Define region 8 + mov r0, #8 + ldr r1, DRBAR_REGION_8 + ldr r2, DRACR_REGION_8 + ldr r3, DRSR_REGION_8 + bl mpu_init + + ; Define region 9 + mov r0, #9 + ldr r1, DRBAR_REGION_9 + ldr r2, DRACR_REGION_9 + ldr r3, DRSR_REGION_9 + bl mpu_init + + ; Define region 10 + mov r0, #10 + ldr r1, DRBAR_REGION_10 + ldr r2, DRACR_REGION_10 + ldr r3, DRSR_REGION_10 + bl mpu_init + + ; Define region 11 + mov r0, #11 + ldr r1, DRBAR_REGION_11 + ldr r2, DRACR_REGION_11 + ldr r3, DRSR_REGION_11 + bl mpu_init + + ; Enables MPU operation + ldr r0, SCTLR_M ; Set SCTLR.M bit to 1 + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, r0 + dsb + mcr p15, 0, r1, c1, c0, 0 + isb ; Ensuring Context-changing + + ; Enables I1,D1 cache operation + ldr r0, SCTLR_I_C ; Set SCTLR.I and C bit to 1 + mrc p15, 0, r1, c1, c0, 0 + orr r1, r1, r0 + dsb + mcr p15, 0, r1, c1, c0, 0 + isb ; Ensuring Context-changing + + pop {pc} + bx lr + +;*********************************************************************** +; Function Name : mpu_init +; Description : Initialize MPU settings +; Arguments : none +; Return Value : none +;*********************************************************************** +mpu_init: + ; RGNR(MPU Memory Region Number Register) + mcr p15, #0, r0, c6, c2, #0 + isb ; Ensuring Context-changing + + ; DRBAR(Data Region Base Address Register) + mcr p15, #0, r1, c6, c1, #0 + isb ; Ensuring Context-changing + + ; DRACR(Data Region Access Control Register) + mcr p15, #0, r2, c6, c1, #4 + isb ; Ensuring Context-changing + + ; DRSR(Data Region Size and Enable Register) + mcr p15, #0, r3, c6, c1, #2 + isb ; Ensuring Context-changing + + bx lr + + +;*********************************************************************** +; Function Name : set_low_vec +; Description : Initialize sysytem by loader program +; Arguments : none +; Return Value : none +;*********************************************************************** +set_low_vec: + mrc p15, 0, r0, c1, c0, 0 ; Set SCTLR.V bit to 1 (low-vector) + and r0, r0, #0xFFFFDFFF + mcr p15, 0, r0, c1, c0, 0 + isb ; Ensuring Context-changing + + bx lr + + END +; End of File diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/loader_init2.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/loader_init2.c new file mode 100644 index 000000000..6593ad61f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/loader_init2.c @@ -0,0 +1,233 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : loader_init2.c +* Version : 0.1 +* Device : R7S9100xx +* Abstract : Loader program 2 +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : Initialize the peripheral settings of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ +#ifdef __ICCARM__ + +#pragma section="VECTOR_RBLOCK" +#pragma section="VECTOR_WBLOCK" +#pragma section="USER_PRG_RBLOCK" +#pragma section="USER_PRG_WBLOCK" +#pragma section="USER_DATA_RBLOCK" +#pragma section="USER_DATA_WBLOCK" + +#endif // __ICCARM__ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include +#include "r_system.h" +#include "r_reset.h" +#include "r_cpg.h" +#include "r_atcm_init.h" +#include "r_port.h" +#include "r_mpc.h" +#include "r_ecm.h" + + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ +extern int _main(void); +extern void bus_init(void); +extern void set_low_vec(void); +extern void cache_init(void); +extern void __iar_data_init3(void); + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + +/******************************************************************************* +Private variables and functions +*******************************************************************************/ +void loader_init2(void); +void reset_check(void); +void cpg_init(void); + +/******************************************************************************* +* Function Name : loader_init2 +* Description : Initialize sysytem by loader program 2 +* Arguments : none +* Return Value : none +*******************************************************************************/ +void loader_init2(void) +{ + /* Check the reset source */ + reset_check(); + + /* Set CPU clock and LOCO clock */ + cpg_init(); + + /* Set ATCM access wait to 1-wait with optimization */ + /* Caution: ATCM_WAIT_0 is permitted if CPUCLK = 150MHz or 300MHz. + ATCM_WAIT_1_OPT is permitted if CPUCLK = 450MHz or 600MHz.*/ + R_ATCM_WaitSet(ATCM_WAIT_1_OPT); + + /* Copy the variable data */ + __iar_data_init3(); + + /* Initialize I1, D1 Cache and MPU setting */ + cache_init(); + + /* Set RZ/T1 to Low-vector (SCTLR.V = 0) */ + set_low_vec(); + + /* Jump to _main() */ + _main(); + +} + +/******************************************************************************* + End of function loader_init2 +*******************************************************************************/ + +/******************************************************************************* +* Function Name : reset_check +* Description : Check the reset source and execute the each sequence. +* When error source number 35 is generated, set P77 pin to High. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void reset_check(void) +{ + volatile uint8_t result; + volatile uint32_t dummy; + + /* Check the reset status flag and execute the each sequence */ + if (RST_SOURCE_ECM == SYSTEM.RSTSR0.LONG) // ECM reset is generated + { + /* Clear reset status flag */ + r_rst_write_enable(); // Enable writing to the RSTSR0 register + SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag + r_rst_write_disable(); // Disable writing to the RSTSR0 register + + /* Please coding the User program */ + + } + else if (RST_SOURCE_SWR1 == SYSTEM.RSTSR0.LONG) // Software reset 1 is generated + { + /* Clear reset status flag */ + r_rst_write_enable(); // Enable writing to the RSTSR0 register + SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag + r_rst_write_disable(); // Disable writing to the RSTSR0 register + + /* Please coding the User program */ + + } + else if (RST_SOURCE_RES == SYSTEM.RSTSR0.LONG) // RES# pin reset is generated + { + /* Clear reset status flag */ + r_rst_write_enable(); // Enable writing to the RSTSR0 register + SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag + r_rst_write_disable(); // Disable writing to the RSTSR0 register + + /* Please coding the User program */ + + } + else // Any reset is not generated + { + /* Please coding the User program */ + } + +} + +/******************************************************************************* + End of function reset_check +*******************************************************************************/ + +/******************************************************************************* +* Function Name : cpg_init +* Description : Set CPU clock and LOCO clock by CPG function +* Arguments : none +* Return Value : none +*******************************************************************************/ +void cpg_init(void) +{ + volatile uint32_t dummy; + + /* Enables writing to the registers related to CPG function */ + R_CPG_WriteEnable(); + + /* Enables LOCO clock operation */ + SYSTEM.LOCOCR.BIT.LCSTP = CPG_LOCO_ENABLE; + + /* Set CPUCLK to 450MHz, and dummy read at three times */ + SYSTEM.PLL1CR.LONG = CPG_CPUCLK_450_MHz; + dummy = SYSTEM.PLL1CR.LONG; + dummy = SYSTEM.PLL1CR.LONG; + dummy = SYSTEM.PLL1CR.LONG; + + /* Enables PLL1 operation */ + SYSTEM.PLL1CR2.LONG = CPG_PLL1_ON; + + /* Disables writing to the registers related to CPG function */ + R_CPG_WriteDisable(); + + /* Wait about 100us for PLL1 (and LOCO) stabilization */ + R_CPG_PLL_Wait(); + + /* Enables writing to the registers related to CPG function */ + R_CPG_WriteEnable(); + + /* Selects the PLL1 as clock source */ + SYSTEM.SCKCR2.LONG = CPG_SELECT_PLL1; + + /* Disables writing to the registers related to CPG function */ + R_CPG_WriteDisable(); + +} + +/******************************************************************************* + End of function cpg_init +*******************************************************************************/ + + +/* End of File */ + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_atcm_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_atcm_init.c new file mode 100644 index 000000000..e15bf7bf8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_atcm_init.c @@ -0,0 +1,108 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_atcm_init.c +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for ATCM function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : ATCM access wait setting API of RZ/T1 +* Limitation : This wait setting could not be executed in ATCM program area. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include +#include "r_system.h" +#include "r_atcm_init.h" + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define ATCM_WRITE_ENABLE (0x0000A508) +#define ATCM_WRITE_DISABLE (0x0000A500) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + + +/******************************************************************************* +Private variables and functions +*******************************************************************************/ + + + +/******************************************************************************* +* Function Name : R_ATCM_WaitSet +* Description : Sets ATCM access wait. +* Arguments : atcm_wait +* Wait settings for ATCM access +* Return Value : none +*******************************************************************************/ +void R_ATCM_WaitSet(uint32_t atcm_wait) +{ + volatile uint32_t dummy; + + /* Enables writing to the ATCM register */ + SYSTEM.PRCR.LONG = ATCM_WRITE_ENABLE; + dummy = SYSTEM.PRCR.LONG; + + /* Sets ATCM access wait to atcm_wait value */ + SYSTEM.SYTATCMWAIT.LONG = atcm_wait; + + /* Disables writing to the ATCM register */ + SYSTEM.PRCR.LONG = ATCM_WRITE_DISABLE; + dummy = SYSTEM.PRCR.LONG; + +} + +/******************************************************************************* + End of function R_ATCM_WaitSet +*******************************************************************************/ + +/* End of File */ + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_cpg.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_cpg.c new file mode 100644 index 000000000..17775f8bd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_cpg.c @@ -0,0 +1,162 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_cpg.c +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for CPG function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : CPG setting API of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include +#include "r_system.h" +#include "r_cpg.h" +#include "r_reset.h" +#include "r_icu_init.h" + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define CPG_WRITE_ENABLE (0x0000A501) +#define CPG_WRITE_DISABLE (0x0000A500) + +#define CPG_CMT0_CLOCK_PCLKD_32 (1) +#define CPG_CMT0_CMI0_ENABLE (1) +#define CPG_CMT0_CONST_100_us (0xEA) +#define CPG_CMT0_START (1) +#define CPG_CMT0_STOP (0) + +#define CPG_CMT_REG_CLEAR (0x0000) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + +/******************************************************************************* +Private variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name : R_CPG_PLL_Wait +* Description : Wait about 100us for PLL stabilization by using CMT0 +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_CPG_PLL_Wait(void) +{ + + /* Enables writing to the registers related to Reset and Low-Power function */ + r_rst_write_enable(); + + /* Release from the CMT0 module-stop state */ + MSTP(CMT0) = 0; + + /* Disables writing to the registers related to Reset and Low-Power function */ + r_rst_write_disable(); + + /* Set CMT0 to 100us interval operation */ + CMT0.CMCR.BIT.CKS = CPG_CMT0_CLOCK_PCLKD_32; // Count clock = PCLKD/32 + CMT0.CMCR.BIT.CMIE = CPG_CMT0_CMI0_ENABLE; // Enable CMI0 interrupt + CMT0.CMCNT = CPG_CMT_REG_CLEAR; // Clear CMCNT counter + CMT0.CMCOR = CPG_CMT0_CONST_100_us; // Set constant value for 100us + + + /* Set IRQ21(CMI0) for polloing sequence */ + VIC.IEC0.BIT.IEC21 = ICU_IEC_MASK_SET; // Mask IRQ21 interrupt + VIC.PLS0.BIT.PLS21 = ICU_TYPE_EDGE; // Set EDGE type interrupt + VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge + + /* Enable IRQ interrupt (Clear CPSR.I bit to 0) */ + asm("cpsie i"); // Clear CPSR.I bit to 0 + asm("isb"); // Ensuring Context-changing + + /* Start CMT0 count */ + CMT.CMSTR0.BIT.STR0 = CPG_CMT0_START; + + /* Wait for 100us (IRQ21 is generated) */ + while ( !(VIC.RAIS0.BIT.RAI21) ) + { + /* Wait */ + } + + /* Stop CMT0 count */ + CMT.CMSTR0.BIT.STR0 = CPG_CMT0_STOP; + + /* Initialize CMT0 settings and clear interrupt detection edge */ + CMT0.CMCR.WORD = CPG_CMT_REG_CLEAR; + CMT0.CMCNT = CPG_CMT_REG_CLEAR; + CMT0.CMCOR = CPG_CMT_REG_CLEAR; + CMT.CMSTR0.WORD = CPG_CMT_REG_CLEAR; + + VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge + + + /* Disable IRQ interrupt (Set CPSR.I bit to 1) */ + asm("cpsid i"); + asm("isb"); + + /* Enables writing to the registers related to Reset and Low-Power function */ + r_rst_write_enable(); + + /* Set CMT0 to module-stop state */ + MSTP(CMT0) = 1; + + /* Disables writing to the registers related to Reset and Low-Power function */ + r_rst_write_disable(); + + +} + +/******************************************************************************* + End of function R_CPG_PLL_Wait +*******************************************************************************/ + +/* End of File */ + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_ecm.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_ecm.c new file mode 100644 index 000000000..c68b80dfb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_ecm.c @@ -0,0 +1,289 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_ecm.c +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for ECM function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : ECM API of RZ/T1 +* Limitation : LOCO operation is necessary for clearing ERROROUT# pin. +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include +#include "r_system.h" +#include "r_ecm.h" +#include "r_reset.h" +#include "r_icu_init.h" + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define ECM_CMT0_CLOCK_PCLKD_32 (1) +#define ECM_CMT0_CMI0_ENABLE (1) +#define ECM_CMT0_CONST_15_us (0x22) +#define ECM_CMT0_START (1) +#define ECM_CMT0_STOP (0) + +#define ECM_CMT_REG_CLEAR (0x0000) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + + +/******************************************************************************* +Private variables and functions +*******************************************************************************/ +static uint32_t *g_pcmd_reg_adrr[ECM_TYPE_MAX] = +{ + (uint32_t *) &ECMM.ECMMPCMD0.LONG, + (uint32_t *) &ECMC.ECMCPCMD0.LONG, + (uint32_t *) &ECM.ECMPCMD1.LONG +}; + +/******************************************************************************* +* Function Name : R_ECM_Init +* Description : Initialize ECM function. +* - Clear all error source +* - Clear ERROROUT# pin output to in-active (High) level. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_ECM_Init(void) +{ + volatile uint8_t result; + + /* Clear all error source (ECMESSTC0, ECMESSTC1, ECMESSTC2) */ + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC0.LONG), 0xDFFFFFF7); + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC1.LONG), 0x000001FF); + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC2.LONG), 0x70000000); + + /* Mask all error source (ECMEMK0, ECMEMK1, ECMEMK2) for clearing ERROROUT# */ + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK0.LONG), 0xDFFFFFF7); + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK1.LONG), 0x000001FF); + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK2.LONG), 0x30000000); + + /* Mask ECM maskable, non-maskable interrupt and ECM reset of ECM compare match + error (ECMMICFG2, ECMNMICFG2, ECMIRCFG2) */ + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMMICFG2.LONG), 0x00000000); + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMNMICFG2.LONG), 0x00000000); + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMIRCFG2.LONG), 0x00000000); + + /* Clear ERROROUT# pin output to in-active (High) level */ + result = R_ECM_Write_Reg8(ECM_MASTER, &(ECMM.ECMMECLR.BYTE), 0x01); + result = R_ECM_Write_Reg8(ECM_CHECKER, &(ECMC.ECMCECLR.BYTE), 0x01); + + /* Wait 15us for ECM compare error stabilization */ + R_ECM_CompareError_Wait(); + + /* Clear ECM compare error (ECMESSTC2) again */ + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC2.LONG), 0x10000000); + + /* Initialize the all error mask settings (ECMEMK0, ECMEMK1, ECMEMK2) */ + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK0.LONG), 0x00000000); + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK1.LONG), 0x00000000); + result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK2.LONG), 0x00000000); + +} + +/******************************************************************************* + End of function R_ECM_Init +*******************************************************************************/ + +/******************************************************************************* +* Function Name : R_ECM_CompareError_Wait +* Description : Wait about 15 us for ECM compare error stabilizeation by using CMT0 +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_ECM_CompareError_Wait(void) +{ + /* Enables writing to the registers related to Reset and Low-Power function */ + r_rst_write_enable(); + + /* Release from the CMT0 module-stop state */ + MSTP(CMT0) = 0; + + /* Disables writing to the registers related to Reset and Low-Power function */ + r_rst_write_disable(); + + /* Set CMT0 to 100us interval operation */ + CMT0.CMCR.BIT.CKS = ECM_CMT0_CLOCK_PCLKD_32; // Count clock = PCLKD/32 + CMT0.CMCR.BIT.CMIE = ECM_CMT0_CMI0_ENABLE; // Enable CMI0 interrupt + CMT0.CMCNT = ECM_CMT_REG_CLEAR; // Clear CMCNT counter + CMT0.CMCOR = ECM_CMT0_CONST_15_us; // Set constant value for 15us + + + /* Set IRQ21(CMI0) for polloing sequence */ + VIC.IEC0.BIT.IEC21 = ICU_IEC_MASK_SET; // Mask IRQ21 interrupt + VIC.PLS0.BIT.PLS21 = ICU_TYPE_EDGE; // Set EDGE type interrupt + VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge + + /* Enable IRQ interrupt (Clear CPSR.I bit to 0) */ + asm("cpsie i"); // Clear CPSR.I bit to 0 + asm("isb"); // Ensuring Context-changing + + /* Start CMT0 count */ + CMT.CMSTR0.BIT.STR0 = ECM_CMT0_START; + + /* Wait for 15us (IRQ21 is generated) */ + while ( ! (VIC.RAIS0.BIT.RAI21) ) + { + /* Wait */ + } + + /* Stop CMT0 count */ + CMT.CMSTR0.BIT.STR0 = ECM_CMT0_STOP; + + /* Initialize CMT0 settings and clear interrupt detection edge */ + CMT0.CMCR.WORD = ECM_CMT_REG_CLEAR; + CMT0.CMCNT = ECM_CMT_REG_CLEAR; + CMT0.CMCOR = ECM_CMT_REG_CLEAR; + CMT.CMSTR0.WORD = ECM_CMT_REG_CLEAR; + + VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge + + + /* Disable IRQ interrupt (Set CPSR.I bit to 1) */ + asm("cpsid i"); + asm("isb"); + + /* Enables writing to the registers related to Reset and Low-Power function */ + r_rst_write_enable(); + + /* Set CMT0 to module-stop state */ + MSTP(CMT0) = 1; + + /* Disables writing to the registers related to Reset and Low-Power function */ + r_rst_write_disable(); + +} + +/******************************************************************************* + End of function R_ECM_CompareError_Wait +*******************************************************************************/ + + +/******************************************************************************* +* Function Name : R_ECM_Write_Reg8 +* Description : Writing the special sequence for 8-bit ECM protected register +* Arguments : reg_type +* The type of ECM register (ECM_MASETR, ECM_CHECKER, ECM_COMMON) +* *reg +* The address of ECM protected register +* value +* The 8-bit value of writing to protected register +* Return Value : none +*******************************************************************************/ +uint8_t R_ECM_Write_Reg8( uint8_t reg_type, volatile unsigned char *reg, uint8_t value) +{ + uint8_t result; + volatile uint8_t dummy_8; + volatile uint32_t dummy_32; + + /* Special write sequence */ + *g_pcmd_reg_adrr[reg_type] = ECM_COMMAND_KEY; // Write fixed value + dummy_32 = *g_pcmd_reg_adrr[reg_type]; + + *reg = value; // Write expected value + *reg = ~value; // Write inversed value of the expected value + *reg = value; // Write expected value + dummy_8 = *reg; + + /* Check the ECMPS register whether special sequence is success or failure + result = 0 : Special sequence is success. + = 1 : Special sequence is failure. */ + result = ECM.ECMPS.BYTE; + + return result; + +} +/******************************************************************************* + End of function R_ECM_Write_Reg8 +*******************************************************************************/ + +/******************************************************************************* +* Function Name : R_ECM_Write_Reg32 +* Description : Writing the special sequence for 32-bit ECM protected register +* Arguments : reg_type +* The type of ECM register (ECM_MASETR, ECM_CHECKER, ECM_COMMON) +* *reg +* The address of ECM protected register +* value +* The 32-bit value of writing to protected register +* Return Value : none +*******************************************************************************/ +uint8_t R_ECM_Write_Reg32( uint8_t reg_type, volatile unsigned long *reg, uint32_t value) +{ + uint8_t result; + volatile uint32_t dummy_32; + + /* Special write sequence */ + *g_pcmd_reg_adrr[reg_type] = ECM_COMMAND_KEY; // Write fixed value + dummy_32 = *g_pcmd_reg_adrr[reg_type]; + + *reg = value; // Write expected value + *reg = ~value; // Write inversed value of the expected value + *reg = value; // Write expected value + dummy_32 = *reg; + + /* Check the ECMPS register whether special sequence is success or failure + result = 0 : Special sequence is success. + = 1 : Special sequence is failure. */ + result = ECM.ECMPS.BYTE; + + return result; + +} +/******************************************************************************* + End of function R_ECM_Write_Reg32 +*******************************************************************************/ + +/* End of File */ + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_icu_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_icu_init.c new file mode 100644 index 000000000..daf7ce037 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_icu_init.c @@ -0,0 +1,329 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_icu_init.c +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for ICU init +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : Initialize the peripheral settings of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include +#include "r_icu_init.h" +#include "r_system.h" +#include "r_mpc.h" +#include "r_ecm.h" + +/******************************************************************************* +Macro definitions +*******************************************************************************/ + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + +/******************************************************************************* +Private variables and functions +*******************************************************************************/ +#ifdef __ICCARM__ +#pragma type_attribute=__irq __arm +#endif // __ICCARM__ +void R_IRQ9_isr(void); + + + +/******************************************************************************* +* Function Name: R_ICU_Disable +* Description : Disable IRQ interrupt +* Arguments : vec_num + Vector interrupt number (1 to 294). +* Return Value : none +*******************************************************************************/ +void R_ICU_Disable(uint32_t vec_num) +{ + /* Define IECn register address pointer */ + volatile uint32_t *p_iec_base; + + /* Variable to specify register suffix */ + uint32_t reg_num; // IECn (n = reg_num) + uint32_t bit_num; // IECn.IECm (m = bit_num) + + /* Calcurate register address and register suffix number */ + if ( 255 >= vec_num ) // Vector number : 1 to 255 + { + /* Set each pointer base address as IEC0 */ + /* Casting the pointer to a (uint32_t *) is valid because this pointer + will reference 32 bit I/O register address */ + p_iec_base = (uint32_t*)&(VIC.IEC0.LONG); + + /* Calcurate register suffix number */ + reg_num = vec_num / 32; // IECn (n = reg_num) + bit_num = vec_num % 32; // IECn.IECm (m = bit_num) + } + else // Vector number : 256 to 294 + { + /* Set each pointer address as IEC8 */ + /* Casting the pointer to a (uint32_t *) is valid because this pointer + will reference 32 bit I/O register address */ + p_iec_base = (uint32_t*)&(VIC.IEC8.LONG); + + /* Calcurate register suffix number. And subtract 8 from reg_num + because IEC8 is base address in this case */ + reg_num = (vec_num / 32) - 8; // IECn (n = 8 + reg_num) + bit_num = (vec_num % 32); // IECn.IECm (m = bit_num) + } + + /* Set interrupt enable clear register (disable interrupt) */ + p_iec_base += reg_num; // Specify IECn register address + *p_iec_base |= ( 1 << bit_num ); // Set IECn.IECm bit + +} +/******************************************************************************* + End of function R_ICU_Disable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_ICU_Enable +* Description : Enable IRQ interrupt +* Arguments : vec_num + Vector interrupt number (1 to 294). +* Return Value : none +*******************************************************************************/ +void R_ICU_Enable(uint32_t vec_num) +{ + /* Define IENn register address pointer */ + volatile uint32_t *p_ien_base; + + /* Variable to specify register suffix */ + uint32_t reg_num; // IENn (n = reg_num) + uint32_t bit_num; // IENn.IENm (m = bit_num) + + + /* Calcurate register address and register suffix number */ + if ( 255 >= vec_num ) // Vector number : 1 to 255 + { + /* Set each pointer base address as IEN0 */ + /* Casting the pointer to a (uint32_t *) is valid because this pointer + will reference 32 bit I/O register address */ + p_ien_base = (uint32_t*)&(VIC.IEN0.LONG); + + /* Calcurate register suffix number */ + reg_num = vec_num / 32; // IENn (n = reg_num) + bit_num = vec_num % 32; // IENn.IENm (m = bit_num) + } + else // Vector number : 256 to 294 + { + /* Set each pointer address as IEN8 */ + /* Casting the pointer to a (uint32_t *) is valid because this pointer + will reference 32 bit I/O register address */ + p_ien_base = (uint32_t*)&(VIC.IEN8.LONG); + + /* Calcurate register suffix number. And subtract 8 from reg_num + because IEN8 is base address in this case */ + reg_num = (vec_num / 32) - 8; // IENn (n = 8 + reg_num) + bit_num = (vec_num % 32); // IENn.IENm (m = bit_num) + } + + /* Set interrupt enable register (enable interrupt) */ + p_ien_base += reg_num; // Specify IENn register address + *p_ien_base |= ( 1 << bit_num ); // Set IENn.IENm bit + +} +/******************************************************************************* + End of function R_ICU_Enable +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_ICU_ExtPinInit +* Description : Initialize external interrupt pin setting. +* Arguments : pin_num + External interrupt pin number (0 to 15). + detect + Interrupt pin detection sense (Low, Fall, Rise, RIse&Fall). + dnf_set + Setting of degital noise filter +* Return Value : none +*******************************************************************************/ +void R_ICU_ExtPinInit(uint16_t pin_num, uint8_t detect, uint32_t dnf_set) +{ + /* Define IRQCRn register address pointer */ + /* Casting the pointer to a (void *) is valid because this pointer will + reference 32 bit I/O register address */ + volatile uint32_t *p_irqcr_base = (void *)(&(ICU.IRQCR0.LONG)); + + /* Disable digital noise filter (Clear IRQFLTEn bit (n = pin_num))*/ + ICU.IRQFLTE.LONG &= (0x0000FFFF & ~( 1 << pin_num )); + + /* Set IRQ detection sense */ + p_irqcr_base += pin_num; // Specify IRQCRn register address + *p_irqcr_base = detect; // Set IRQCRn.IRQMD[1:0] + + /* Set digital noise filter and enable */ + if ( ICU_DNF_NO_USE != dnf_set ) + { + /* Set digital noise filter */ + ICU.IRQFLTC.LONG &= ~( 3 << ( pin_num * 2 ) ); // Clear FCLKSELn[1:0] + ICU.IRQFLTC.LONG |= (dnf_set << ( pin_num * 2)); // Set FCLKSELn[1:0] to dnf_set value + + /* Enable digital noise filter */ + ICU.IRQFLTE.LONG |= ( 1 << pin_num ); + } + +} +/******************************************************************************* + End of function R_ICU_ExtPinInit +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: R_ICU_Regist +* Description : Registration interrupt controller setting. +* Arguments : vec_num + Vector interrupt number (1 to 294). + type + IRQ detection type(Level or Edge). + priority + IRQ priority level ( Vector number 1 to 255 : 0 to 15, + Vector number 256 to 294 : 16 to 31) + isr_addr + Interrupt service routine address +* Return Value : none +*******************************************************************************/ +void R_ICU_Regist(uint32_t vec_num, uint32_t type, uint32_t priority, uint32_t isr_addr) +{ + /* Define PLSn, PRLn, VADn and PICn registers address pointer */ + volatile uint32_t *p_pls_base; + volatile uint32_t *p_prl_base; + volatile uint32_t *p_vad_base; + volatile uint32_t *p_pic_base; + + /* Variable to specify register suffix */ + uint32_t reg_num; // PLSn, PICn (n = reg_num) + uint32_t bit_num; // PLSn.PLSm, PICn.PICm (m = bit_num) + + + /* Calcurate register address and register suffix number */ + if ( 255 >= vec_num ) // Vector number : 1 to 255 + { + /* Set each pointer base address as PLS0, PRL1, VAD1 and PIC0 */ + /* Casting the pointer to a (uint32_t *) is valid because this pointer + will reference 32 bit I/O register address */ + p_pls_base = (uint32_t*)&(VIC.PLS0.LONG); + p_prl_base = (uint32_t*)&(VIC.PRL1.LONG); + p_vad_base = (uint32_t*)&(VIC.VAD1.LONG); + p_pic_base = (uint32_t*)&(VIC.PIC0.LONG); + + /* Calcurate register suffix number */ + reg_num = vec_num / 32; // PLSn, PICn (n = reg_num) + bit_num = vec_num % 32; // PLSn.PLSm, PICn.PICm (m = bit_num) + } + else // Vector number : 256 to 294 + { + /* Set each pointer address as PLS8, PRL256, VAD256 and PIC8 */ + /* Casting the pointer to a (uint32_t *) is valid because this pointer + will reference 32 bit I/O register address */ + p_pls_base = (uint32_t*)&(VIC.PLS8.LONG); + p_prl_base = (uint32_t*)&(VIC.PRL256.LONG); + p_vad_base = (uint32_t*)&(VIC.VAD256.LONG); + p_pic_base = (uint32_t*)&(VIC.PIC8.LONG); + + /* Calcurate register suffix number. And subtract 8 from reg_num + because PLS8 and PIC8 are base address in this case */ + reg_num = (vec_num / 32) - 8; // PLSn, PICn (n = 8 + reg_num) + bit_num = (vec_num % 32); // PLSn.PLSm, PICn.PICm (m = bit_num) + vec_num -= 255; // Offset (PRLn and VADn base is changed (eg. VAD1 to VAD256) + } + + /* Set interrupt detection type (Level or Edge) by PLSn */ + p_pls_base += reg_num; // Specify PLSn register address + *p_pls_base &= ~( 1 << bit_num ); // Clear PLSn.PLSm bit + *p_pls_base |= ( type << bit_num ); // Set PLSn.PLSm bit to type value + + /* Set interrupt priority level (0 to 15) or (16 to 31) */ + p_prl_base += ( vec_num - 1 ); // Specify PRLn register address + *p_prl_base = priority; // Set PRLn to priority value + + /* Set interrupt service routine address */ + p_vad_base += ( vec_num - 1 ); // Specify VADn register address + *p_vad_base = isr_addr; // Set VADn to isr_addr value + + /* Clear interrupt edge detection (edge type only)*/ + if ( ICU_TYPE_EDGE == type ) + { + p_pic_base += reg_num; // Specify PICn register address + *p_pic_base |= ( 1 << bit_num ); // Set PICn.PICm bit to 1 + } + +} + +/******************************************************************************* + End of function R_ICU_Regist +*******************************************************************************/ + +/******************************************************************************* +* Function Name: R_IRQ9_isr +* Description : Interrupt service routine of IRQ9 (IRQ5 pin interrupt). +* Toggle the P56 output level (LED1) +* Arguments : none +* Return Value : none +*******************************************************************************/ +#ifdef __ICCARM__ +#pragma type_attribute=__irq __arm +#endif // __ICCARM__ +void R_IRQ9_isr(void) +{ + /* Clear interrupt edge detection */ + VIC.PIC0.BIT.PIC9 = ICU_PIC_EDGE_CLEAR; + + /* Toggle the P56 output level(LED1) */ + PORT5.PODR.BIT.B6 ^= 1; + + /* End interrupt sequence (dummy writing to HVA0 register) */ + VIC.HVA0.LONG = 0x00000000; + +} + +/******************************************************************************* + End of function R_IRQ9_isr +*******************************************************************************/ + + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_ram_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_ram_init.c new file mode 100644 index 000000000..e6f395ce5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_ram_init.c @@ -0,0 +1,148 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_ram_init.c +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for internal extended RAM function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : internal extended RAM setting API of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include +#include "r_system.h" +#include "r_ram_init.h" + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define RAM_ECC_ENABLE (0x00000001) +#define RAM_ECC_DISABLE (0x00000000) +#define RAM_PROTECT (0x00000000) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + + +/******************************************************************************* +Private variables and functions +*******************************************************************************/ + +/******************************************************************************* +* Function Name : R_RAM_ECC_Enable +* Description : Enable ECC function for internal extended RAM. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_RAM_ECC_Enable(void) +{ + /* Enables writing to the protected registers related to RAM function */ + R_RAM_WriteEnable(); + + /* Enable ECC function */ + ECCRAM.RAMEDC.LONG = RAM_ECC_ENABLE; + + /* Disables writing to the protected registers related to RAM function */ + R_RAM_WriteDisable(); + +} + +/******************************************************************************* + End of function R_RAM_ECC_Enable +*******************************************************************************/ + + +/******************************************************************************* +* Function Name : R_RAM_WriteEnable +* Description : Enable writing to the protected registers related to RAM. +* And dummy read the register in order to fix the register value. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_RAM_WriteEnable(void) +{ + volatile uint32_t dummy; + + /* Special sequence for protect release */ + ECCRAM.RAMPCMD.LONG = 0x000000A5; // Write fixed value 0x000000A5 + ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value + ECCRAM.RAMPCMD.LONG = 0x0000FFFE; // Write inversed value of the expected value + ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value again + dummy = ECCRAM.RAMPCMD.LONG; + +} + +/******************************************************************************* + End of function R_RAM_WriteEnable +*******************************************************************************/ + +/******************************************************************************* +* Function Name : R_RAM_WriteDisable +* Description : Disable writing to the protected registers related to RAM. +* And dummy read the register in order to fix the register value. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void R_RAM_WriteDisable(void) +{ + volatile uint32_t dummy; + + /* Clear RAMPCMD register to zero */ + ECCRAM.RAMPCMD.LONG = RAM_PROTECT; + dummy = ECCRAM.RAMPCMD.LONG; + +} + +/******************************************************************************* + End of function R_RAM_WriteDisable +*******************************************************************************/ + +/* End of File */ + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_reset.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_reset.c new file mode 100644 index 000000000..615f75f64 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/r_reset.c @@ -0,0 +1,123 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* System Name : RZ/T1 Init program +* File Name : r_reset.c +* Version : 0.1 +* Device : R7S9100xx +* Abstract : API for RESET and Low-Power function +* Tool-Chain : IAR Embedded Workbench Ver.7.20 +* OS : not use +* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +* Description : RESET and Low-Power API of RZ/T1 +* Limitation : none +*******************************************************************************/ +/******************************************************************************* +* History : DD.MM.YYYY Version Description +* : First Release +*******************************************************************************/ + +/******************************************************************************* +Includes , "Project Includes" +*******************************************************************************/ +#include +#include +#include "r_system.h" +#include "r_reset.h" + +/******************************************************************************* +Macro definitions +*******************************************************************************/ +#define RST_WRITE_ENABLE (0x0000A502) +#define RST_WRITE_DISABLE (0x0000A500) + +/******************************************************************************* +Typedef definitions +*******************************************************************************/ + + + +/******************************************************************************* +Imported global variables and functions (from other files) +*******************************************************************************/ + + +/******************************************************************************* +Exported global variables and functions (to be accessed by other files) +*******************************************************************************/ + + + +/******************************************************************************* +Private variables and functions +*******************************************************************************/ + + +/******************************************************************************* +* Function Name : r_rst_write_enable +* Description : Enables writing to the registers related to RESET and Low- +* Power function. And dummy read the register in order to fix +* the register value. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void r_rst_write_enable(void) +{ + volatile uint32_t dummy; + + /* Enables writing to the Reset and Low-Power register */ + SYSTEM.PRCR.LONG = RST_WRITE_ENABLE; + dummy = SYSTEM.PRCR.LONG; + +} + +/******************************************************************************* + End of function r_rst_write_enable +*******************************************************************************/ + +/******************************************************************************* +* Function Name : r_rst_write_disable +* Description : Disables writing to the registers related to RESET and Low- +* Power function. And dummy read the register in order to fix +* the register value. +* Arguments : none +* Return Value : none +*******************************************************************************/ +void r_rst_write_disable(void) +{ + volatile uint32_t dummy; + + /* Disables writing to the Reset and Low-Power register */ + SYSTEM.PRCR.LONG = RST_WRITE_DISABLE; + dummy = SYSTEM.PRCR.LONG; + +} + +/******************************************************************************* + End of function r_rst_write_disable +*******************************************************************************/ + +/* End of File */ + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/vector.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/vector.asm new file mode 100644 index 000000000..1e29b24ce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/System/IAR/src/vector.asm @@ -0,0 +1,73 @@ +;******************************************************************************* +; DISCLAIMER +; This software is supplied by Renesas Electronics Corporation and is only +; intended for use with Renesas products. No other uses are authorized. This +; software is owned by Renesas Electronics Corporation and is protected under +; all applicable laws, including copyright laws. +; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +; LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +; AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +; TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +; ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +; FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +; ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; Renesas reserves the right, without notice, to make changes to this software +; and to discontinue the availability of this software. By using this software, +; you agree to the additional terms and conditions found by accessing the +; following link: +; http://www.renesas.com/disclaimer +; +; Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. +;****************************************************************************** +;******************************************************************************* +; System Name : RZ/T1 Init program +; File Name : vector.asm +; Version : 0.1 +; Device : R7S9100xx +; Abstract : vector address (in low vector) +; Tool-Chain : IAR Embedded Workbench Ver.7.20 +; OS : not use +; H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) +; Description : vector address for RZ/T1 (in low vector) +; Limitation : none +;****************************************************************************** +;******************************************************************************* +; History : DD.MM.YYYY Version Description +; : First Release +;****************************************************************************** + +/* This program is allocated to section "intvec" */ + SECTION intvec:CODE:ROOT(2) + + EXTERN FreeRTOS_SVC_Handler + + ARM + +reset_handler: + b reset_handler + +undefined_handler: + b undefined_handler + +svc_handler: + b FreeRTOS_SVC_Handler + +prefetch_handler: + b prefetch_handler + +abort_handler: + b abort_handler + +reserved_handler: + b reserved_handler + +irq_handler: + b irq_handler + +fiq_handler: + b fiq_handler + + END +; End of File diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/makefile.init b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/makefile.init new file mode 100644 index 000000000..9f2d24f6f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/makefile.init @@ -0,0 +1,5 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +PATH := $(PATH):C:\PROGRA~2\KPIT\GNUARM~1.02-\ARM-NO~1\ARM-NO~1\bin;C:\PROGRA~2\KPIT\GNUARM~1.02-\ARM-NO~1\ARM-NO~1\libexec\gcc\arm-none-eabi\4.9-GNUARM-NONE_v14.02 \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.cspy.bat new file mode 100644 index 000000000..82e077d1c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%1" == "" goto debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.driver.xcl b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.driver.xcl new file mode 100644 index 000000000..4ac5dda39 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.driver.xcl @@ -0,0 +1,43 @@ + -B + +"--endian=little" + +"--cpu=Cortex-R4F" + +"--fpu=VFPv3" + +"-p" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\CONFIG\debugger\Renesas\R7S910018_R4F.ddf" + +"--drv_verify_download" + +"--semihosting=none" + +"--device=R7S910018_R4F" + +"--multicore_nr_of_cores=1" + +"--jet_standard_reset=7,0,0" + +"--reset_style=\"0,-,0,Disabled__no_reset_\"" + +"--reset_style=\"1,-,0,Software\"" + +"--reset_style=\"2,-,0,Hardware\"" + +"--reset_style=\"7,ResetAndStopAtUser,1,Reset_and_halt_after_bootloader\"" + +"--drv_restore_breakpoints=_main" + +"--drv_catch_exceptions=0x01a" + +"--jet_board_cfg=C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\Renesas\RZT1.ProbeConfig" + +"--drv_trace_size=8388608" + +"--board_file=C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\config\flashloader\" + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.general.xcl b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.general.xcl new file mode 100644 index 000000000..12fbca4ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.Debug.general.xcl @@ -0,0 +1,15 @@ +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\bin\armproc.dll" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\bin\armJET.dll" + +"C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\Debug\Exe\c.out" + +--plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\bin\armbat.dll" + +--device_macro "C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\config\debugger\Renesas\Trace_RZT1.dmac" + +--macro "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_R4F_RZ_T_GCC_IAR\System\IAR\RZT1_init_RAM.mac" + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.crun b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.crun new file mode 100644 index 000000000..5bb5acca4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.crun @@ -0,0 +1,16 @@ + + + + 1 + + + * + * + * + 0 + 1 + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..01a951688 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,277 @@ + + + + + + + 20 + 1622 + + + 20 + 1216 + 324 + 81 + + + + 194 + 27 + 27 + 27 + + + + + Disassembly + _I0 + + + 500 + 20 + + + + 2 + 0 + 0 + + + 1 + 1 + + + + 3 + 0 + 0 + + + + Breakpoint + _I0 + + + 500 + 35 + + + + + 2 + 0 + 0 + + + + + + + + + TabID-31370-17793 + Debug Log + Debug-Log + + + + TabID-30847-17802 + Build + Build + + + + 0 + + + + + TabID-9350-17796 + Workspace + Workspace + + + RTOSDemo + RTOSDemo/FreeRTOS_Source + RTOSDemo/Full_Demo + + + + + 0 + + + + + + TextEditor + $WS_DIR$\src\main.c + 0 + 0 + 0 + 0 + 0 + 128 + 6721 + 6721 + + 0 + + TextEditor + $WS_DIR$\src\Full_Demo\IntQueueTimer.c + 0 + 0 + 0 + 0 + 0 + 81 + 4886 + 4912 + + + TextEditor + $WS_DIR$\System\IAR\Interrupt_Entry_Stubs.asm + 0 + 0 + 0 + 0 + 0 + 66 + 4185 + 4185 + + + TextEditor + $WS_DIR$\..\..\Source\portable\IAR\ARM_CRx_No_GIC\port.c + 0 + 0 + 0 + 0 + 0 + 245 + 11320 + 11320 + + + TextEditor + $WS_DIR$\src\Full_Demo\reg_test_IAR.asm + 0 + 0 + 0 + 0 + 0 + 123 + 5555 + 5555 + + + TextEditor + $WS_DIR$\..\Common\Minimal\TimerDemo.c + 0 + 0 + 0 + 0 + 0 + 242 + 12612 + 12612 + + + TextEditor + $WS_DIR$\..\..\Source\tasks.c + 0 + 0 + 0 + 0 + 0 + 202 + 11920 + 11930 + + + 0 + + + 1000000 + 1000000 + + + 1 + + + + + + + iaridepm.enu1 + + + debuggergui.enu1 + + + + + + + armjet.enu1 + + + + + + + + + + -2 + -2 + 718 + 268 + -2 + -2 + 200 + 200 + 119048 + 203252 + 160714 + 731707 + + + + + + + + + + + + + + + + -2 + -2 + 198 + 1682 + -2 + -2 + 1684 + 200 + 1002381 + 203252 + 119048 + 203252 + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dni b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..d7aa2b822 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.dni @@ -0,0 +1,112 @@ +[InterruptLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +SumSortOrder=0 +[DataLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Interrupts] +Enabled=1 +[MemConfig] +Base=1 +Manual=0 +Ddf=1 +TypeViol=0 +Stop=1 +[Trace1] +Enabled=0 +ShowSource=1 +[Simulator] +Freq=10000000 +MultiCoreRunAll=1 +[PlDriver] +MemConfigValue=C:\DevTools\IAR Systems\Embedded Workbench 7.2\arm\CONFIG\debugger\Renesas\R7S910018_R4F.ddf +FirstRun=0 +[Jet] +DisableInterrupts=0 +MultiCoreRunAll=0 +JetConnSerialNo=73866 +JetConnFoundProbes= +OnlineReset=Software +PrevWtdReset=Reset and halt after bootloader +[ArmDriver] +EnableCache=1 +[DebugChecksum] +Checksum=479945930 +[Exceptions] +StopOnUncaught=_ 0 +StopOnThrow=_ 0 +[CallStack] +ShowArgs=0 +[Disassembly] +MixedMode=1 +[SWOManager] +SamplingDivider=8192 +OverrideClock=0 +CpuClock=7274605 +SwoClock=7340141 +DataLogMode=0 +ItmPortsEnabled=63 +ItmTermIOPorts=1 +ItmLogPorts=0 +ItmLogFile=$PROJ_DIR$\ITM.log +PowerForcePC=1 +PowerConnectPC=1 +[Trace2] +Enabled=0 +ShowSource=0 +[SWOTraceWindow] +ForcedPcSampling=0 +ForcedInterruptLogs=0 +ForcedItmLogs=0 +EventCPI=0 +EventEXC=0 +EventFOLD=0 +EventLSU=0 +EventSLEEP=0 +[PowerLog] +Title_0=ITrgPwr +Symbol_0=0 4 1 +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +LiveEnabled=0 +LiveFile=PowerLogLive.log +[CallStackLog] +Enabled=0 +[CallStackStripe] +ShowTiming=1 +[PowerProbe] +Frequency=10000 +Probe0=ITrgPwr +ProbeSetup0=2 1 1 2 0 0 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints2] +Count=0 +[Aliases] +Count=0 +SuppressDialog=0 diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..ce2aca9bc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,89 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 222272727 + + + + + 201622 + + + + + + 20121632481 + + + 497 + 82 + 746 + 331 + + + + + + + + + TabID-31096-4084 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Full_DemoRTOSDemo/Full_Demo/Common Demo Tasks + + + + 0 + + + TabID-12820-6268 + Debug Log + Debug-Log + + + + TabID-23359-8322 + Build + Build + + + + TabID-12571-20119 + Find in Files + Find-in-Files + + + + + 1 + + + + + + TextEditor$WS_DIR$\src\main.c00000128672167210TextEditor$WS_DIR$\src\Full_Demo\IntQueueTimer.c000008148864912TextEditor$WS_DIR$\System\IAR\Interrupt_Entry_Stubs.asm000006641854185TextEditor$WS_DIR$\..\..\Source\portable\IAR\ARM_CRx_No_GIC\port.c000002451132011320TextEditor$WS_DIR$\src\Full_Demo\reg_test_IAR.asm0000012355555555TextEditor$WS_DIR$\..\Common\Minimal\TimerDemo.c000002421261212612TextEditor$WS_DIR$\..\..\Source\tasks.c0000020211920119300100000010000001 + + + + + + + iaridepm.enu1-2-2619312-2-2200200119048203252186905631098-2-23211682-2-216843231002381328252119048203252 + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wspos b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wspos new file mode 100644 index 000000000..ecdc2c482 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/settings/RTOSDemo.wspos @@ -0,0 +1,2 @@ +[MainWindow] +WindowPlacement=_ 519 0 1619 872 3 diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..83d88be71 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,234 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas includes. */ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + LED2 = !LED2; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOSConfig.h new file mode 100644 index 000000000..49e1c887f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOSConfig.h @@ -0,0 +1,187 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configCPU_CLOCK_HZ 450000000 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 38 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xEventGroupSetBitFromISR 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Cortex-R specific setting: FPU has 16 (rather than 32) d registers. */ +#define configFPU_D32 0 + +/* Cortex-R specific setting: The address of the register within the interrupt +controller from which the address of the current interrupt's handling function +can be obtained. */ +#define configINTERRUPT_VECTOR_ADDRESS + +/* Cortex-R specific setting: The address of End of Interrupt register within +the interrupt controller. */ +#define configEOI_ADDRESS 0xA0010200UL /* VIC HVA0 register */ + +/* Cortex-R specific setting: configCLEAR_TICK_INTERRUPT() is a macro that is +called by the RTOS kernel's tick handler to clear the source of the tick +interrupt. */ +#define configCLEAR_TICK_INTERRUPT() VIC.PIC9.LONG = 0x00001000UL; + +/* Prevent C code being included in assembly files when the IAR compiler is +used. */ +#ifndef __IASMARM__ + + /* Renesas hardware definitions. */ + #include "iodefine.h" + + /* Application specific definition. See _TBD_ for usage instructions. */ + typedef void (*ISRFunction_t)( void ); + + /* Normal assert() semantics without relying on the provision of an assert.h + header file. */ + #define configASSERT( x ) if( ( x ) == 0 ) { portDISABLE_INTERRUPTS(); for( ;; ); } + + + + /****** Hardware specific settings. *******************************************/ + + /* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. FreeRTOS_Tick_Handler() must + * be installed as the peripheral's interrupt handler. + */ + void vConfigureTickInterrupt( void ); + #define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt() + +#endif /* __IASMARM__ */ + +/* To allow the debugger to find the end of the interrupt stack frame. */ +#define configTASK_RETURN_ADDRESS NULL + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOS_tick_config.c new file mode 100644 index 000000000..449274271 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/FreeRTOS_tick_config.c @@ -0,0 +1,213 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" + +/* Renesas includes. */ +#include "r_cg_macrodriver.h" +#include "r_cg_cmt.h" +#include "r_reset.h" + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the FreeRTOS tick interrupt. This sets the pxISRFunction + * variable to point to the RTOS tick handler, then branches to the FreeRTOS + * IRQ handler. + */ +#ifdef __GNUC__ + static void FreeRTOS_Tick_Handler_Entry( void ) __attribute__((naked)); +#endif /* __GNUC__ */ +#ifdef __ICCARM__ + /* IAR requires the entry point to be in an assembly file. The function is + implemented in $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm. */ + extern void FreeRTOS_Tick_Handler_Entry( void ); +#endif /* __ICCARM__ */ + +/* + * The FreeRTOS IRQ handler, which is implemented in the RTOS port layer. + */ +extern void FreeRTOS_IRQ_Handler( void ); + +/* + * The function called by the FreeRTOS_IRQ_Handler() to call the actual + * peripheral handler. + */ +void vApplicationIRQHandler( void ); + +/*-----------------------------------------------------------*/ + +/* + * Variable used to hold the address of the interrupt handler the FreeRTOS IRQ + * handler will branch to. + */ +ISRFunction_t pxISRFunction = NULL; + +/*-----------------------------------------------------------*/ + +/* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. + */ +void vConfigureTickInterrupt( void ) +{ +uint32_t ulCompareMatchValue; +const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL; + + /* Disable CMI5 interrupt. */ + VIC.IEC9.LONG = 0x00001000UL; + + /* Cancel CMT stop state in LPC. */ + r_rst_write_enable(); + MSTP( CMT2 ) = 0U; + r_rst_write_disable(); + + /* Interrupt on compare match. */ + CMT5.CMCR.BIT.CMIE = 1; + + /* Calculate the compare match value. */ + ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider; + ulCompareMatchValue /= ulCMTClockDivider; + ulCompareMatchValue /= configTICK_RATE_HZ; + ulCompareMatchValue -= 1UL; + + /* Set the compare match value. */ + CMT5.CMCOR = ( unsigned short ) ulCompareMatchValue; + + /* Divide the PCLK by 8. */ + CMT5.CMCR.BIT.CKS = 0; + + CMT5.CMCNT = 0; + + /* Set CMI5 edge detection type. */ + VIC.PLS9.LONG |= 0x00001000UL; + + /* Set CMI5 priority level to the lowest possible. */ + VIC.PRL300.LONG = _CMT_PRIORITY_LEVEL31; + + /* Set CMI5 interrupt address */ + VIC.VAD300.LONG = ( uint32_t ) FreeRTOS_Tick_Handler_Entry; + + /* Enable CMI5 interrupt in ICU. */ + VIC.IEN9.LONG |= 0x00001000UL; + + /* Start CMT5 count. */ + CMT.CMSTR2.BIT.STR5 = 1U; +} +/*-----------------------------------------------------------*/ + +/* + * The function called by the FreeRTOS IRQ handler, after it has managed + * interrupt entry. This function creates a local copy of pxISRFunction before + * re-enabling interrupts and actually calling the handler pointed to by + * pxISRFunction. + */ +void vApplicationIRQHandler( void ) +{ +ISRFunction_t pxISRToCall = pxISRFunction; + + portENABLE_INTERRUPTS(); + + /* Call the installed ISR. */ + pxISRToCall(); +} +/*-----------------------------------------------------------*/ + +/* + * The RZ/T vectors directly to a peripheral specific interrupt handler, rather + * than using the Cortex-R IRQ vector. Therefore each interrupt handler + * installed by the application must follow the example below, which saves a + * pointer to a standard C function in the pxISRFunction variable, before + * branching to the FreeRTOS IRQ handler. The FreeRTOS IRQ handler then manages + * interrupt entry (including interrupt nesting), before calling the C function + * saved in the pxISRFunction variable. NOTE: This entry point is a naked + * function - do not add C code to this function. + */ +#ifdef __GNUC__ + /* The IAR equivalent is implemented in + $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */ + static void FreeRTOS_Tick_Handler_Entry( void ) + { + __asm volatile ( \ + "PUSH {r0-r1} \t\n" \ + "LDR r0, =pxISRFunction \t\n" \ + "LDR R1, =FreeRTOS_Tick_Handler \t\n" \ + "STR R1, [r0] \t\n" \ + "POP {r0-r1} \t\n" \ + "B FreeRTOS_IRQ_Handler " + ); + } +#endif /* __GNUC__ */ +/*-----------------------------------------------------------*/ + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..5aee68feb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.c @@ -0,0 +1,242 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file contains the non-portable and therefore RZ/T specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Renesas includes. */ +#include "r_cg_macrodriver.h" +#include "r_cg_cmt.h" +#include "r_reset.h" + +#define tmrCMT_1_CHANNEL_0_HZ ( 4000UL ) +#define tmrCMT_1_CHANNEL_1_HZ ( 2011UL ) + +/* + * Handlers for the two timers used. See the documentation page + * for this port on TBD for more information on writing + * interrupt handlers. + */ +void vCMT_1_Channel_0_ISR( void ); +void vCMT_1_Channel_1_ISR( void ); + +/* + * Entry point for the handlers. These set the pxISRFunction variable to point + * to the C handler for each timer, then branch to the FreeRTOS IRQ handler. + */ +#ifdef __GNUC__ + static void vCMT_1_Channel_0_ISR_Entry( void ) __attribute__((naked)); + static void vCMT_1_Channel_1_ISR_Entry( void ) __attribute__((naked)); +#endif /* __GNUC__ */ +#ifdef __ICCARM__ + /* IAR requires the entry point to be in an assembly file. The functions + are implemented in $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm. */ + extern void vCMT_1_Channel_0_ISR_Entry( void ); + extern void vCMT_1_Channel_1_ISR_Entry( void ); +#endif /* __ICCARM__ */ +/*-----------------------------------------------------------*/ + +void vInitialiseTimerForIntQueueTest( void ) +{ +uint32_t ulCompareMatchValue; +const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL; + + /* Disable CMI2 and CMI3 interrupts. */ + VIC.IEC0.LONG = ( 1UL << 23UL ) | ( 1UL << 24UL ); + + /* Cancel CMT stop state in LPC. */ + r_rst_write_enable(); + MSTP( CMT1 ) = 0U; + r_rst_write_disable(); + + /* Interrupt on compare match. */ + CMT2.CMCR.BIT.CMIE = 1; + CMT3.CMCR.BIT.CMIE = 1; + + /* Calculate the compare match value. */ + ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider; + ulCompareMatchValue /= ulCMTClockDivider; + ulCompareMatchValue /= tmrCMT_1_CHANNEL_0_HZ; + ulCompareMatchValue -= 1UL; + CMT2.CMCOR = ( unsigned short ) ulCompareMatchValue; + + ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider; + ulCompareMatchValue /= ulCMTClockDivider; + ulCompareMatchValue /= tmrCMT_1_CHANNEL_1_HZ; + ulCompareMatchValue -= 1UL; + CMT3.CMCOR = ( unsigned short ) ulCompareMatchValue; + + /* Divide the PCLK by 8. */ + CMT2.CMCR.BIT.CKS = 0; + CMT3.CMCR.BIT.CKS = 0; + + /* Clear count to 0. */ + CMT2.CMCNT = 0; + CMT3.CMCNT = 0; + + /* Set CMI2 and CMI3 edge detection type. */ + VIC.PLS0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL ); + + /* Set CMI2 and CMI3 priority levels so they nest. */ + VIC.PRL23.LONG = _CMT_PRIORITY_LEVEL2; + VIC.PRL24.LONG = _CMT_PRIORITY_LEVEL9; + + /* Set CMI2 and CMI3 interrupt address. */ + VIC.VAD23.LONG = ( uint32_t ) vCMT_1_Channel_0_ISR_Entry; + VIC.VAD24.LONG = ( uint32_t ) vCMT_1_Channel_1_ISR_Entry; + + /* Enable CMI2 and CMI3 interrupts in ICU. */ + VIC.IEN0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL ); + + /* Start CMT1 channel 0 and 1 count. */ + CMT.CMSTR1.BIT.STR2 = 1U; + CMT.CMSTR1.BIT.STR3 = 1U; +} +/*-----------------------------------------------------------*/ + +void vCMT_1_Channel_0_ISR( void ) +{ + /* Clear the interrupt. */ + VIC.PIC0.LONG = ( 1UL << 23UL ); + + /* Call the handler that is part of the common code - this is where the + non-portable code ends and the actual test is performed. */ + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +void vCMT_1_Channel_1_ISR( void ) +{ + /* Clear the interrupt. */ + VIC.PIC0.LONG = ( 1UL << 24UL ); + + /* Call the handler that is part of the common code - this is where the + non-portable code ends and the actual test is performed. */ + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +/* + * The RZ/T vectors directly to a peripheral specific interrupt handler, rather + * than using the Cortex-R IRQ vector. Therefore each interrupt handler + * installed by the application must follow the examples below, which save a + * pointer to a standard C function in the pxISRFunction variable, before + * branching to the FreeRTOS IRQ handler. The FreeRTOS IRQ handler then manages + * interrupt entry (including interrupt nesting), before calling the C function + * saved in the pxISRFunction variable. NOTE: The entry points are naked + * functions - do not add C code to these functions. + */ +#ifdef __GNUC__ + /* The IAR equivalent is implemented in + $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */ + static void vCMT_1_Channel_0_ISR_Entry( void ) + { + __asm volatile ( \ + "PUSH {r0-r1} \t\n" \ + "LDR r0, =pxISRFunction \t\n" \ + "LDR r1, =vCMT_1_Channel_0_ISR \t\n" \ + "STR r1, [r0] \t\n" \ + "POP {r0-r1} \t\n" \ + "B FreeRTOS_IRQ_Handler " + ); + } +#endif /* __GNUC__ */ +/*-----------------------------------------------------------*/ + +#ifdef __GNUC__ + /* The IAR equivalent is implemented in + $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */ + static void vCMT_1_Channel_1_ISR_Entry( void ) + { + __asm volatile ( \ + "PUSH {r0-r1} \t\n" \ + "LDR r0, =pxISRFunction \t\n" \ + "LDR r1, =vCMT_1_Channel_1_ISR \t\n" \ + "STR r1, [r0] \t\n" \ + "POP {r0-r1} \t\n" \ + "B FreeRTOS_IRQ_Handler " + ); + } +#endif /* __GNUC__ */ + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..fcf9f8c1f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/main_full.c new file mode 100644 index 000000000..f80371559 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/main_full.c @@ -0,0 +1,513 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Renesas includes. */ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the FPU registers, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly file, but the + * entry points are kept in the C file for the convenience of checking the task + * parameter. + */ +static void prvRegTestTaskEntry1( void *pvParameters ); +extern void vRegTest1Implementation( void ); +static void prvRegTestTaskEntry2( void *pvParameters ); +extern void vRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/* String for display in the web server. It is set to an error message if the +check task detects an error. */ +const char *pcStatusMessage = "All tasks running without error"; +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + LED2 = !LED2; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + pcStatusMessage = "Error found in at least one task."; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry1( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* The reg test task also tests the floating point registers. Tasks + that use the floating point unit must call vPortTaskUsesFPU() before + any floating point instructions are executed. */ + vPortTaskUsesFPU(); + + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check timer will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry2( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* The reg test task also tests the floating point registers. Tasks + that use the floating point unit must call vPortTaskUsesFPU() before + any floating point instructions are executed. */ + vPortTaskUsesFPU(); + + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check timer will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} + + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/reg_test_GCC.S b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/reg_test_GCC.S new file mode 100644 index 000000000..8de8a6e8e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/reg_test_GCC.S @@ -0,0 +1,464 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2014 Real Time Engineers Ltd. + + FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT + http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + + >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + details. You should have received a copy of the GNU General Public License + and the FreeRTOS license exception along with FreeRTOS; if not itcan be + viewed here: http://www.freertos.org/a00114.html and also obtained by + writing to Real Time Engineers Ltd., contact details for whom are available + on the FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, and our new + fully thread aware and reentrant UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems, who sell the code with commercial support, + indemnification and middleware, under the OpenRTOS brand. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. +*/ + + .global vRegTest1Implementation + .global vRegTest2Implementation + .extern ulRegTest1LoopCounter + .extern ulRegTest2LoopCounter + + .text + .arm + + /* This function is explained in the comments at the top of main-full.c. */ +.type vRegTest1Implementation, %function +vRegTest1Implementation: + + /* Fill each general purpose register with a known value. */ + mov r0, #0xFF + mov r1, #0x11 + mov r2, #0x22 + mov r3, #0x33 + mov r4, #0x44 + mov r5, #0x55 + mov r6, #0x66 + mov r7, #0x77 + mov r8, #0x88 + mov r9, #0x99 + mov r10, #0xAA + mov r11, #0xBB + mov r12, #0xCC + mov r14, #0xEE + + + /* Fill each FPU register with a known value. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + + /* Loop, checking each itteration that each register still contains the + expected value. */ +reg1_loop: + /* Yield to increase test coverage */ + svc 0 + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d1 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d2 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d3 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + vmov r0, r1, d4 + cmp r0, #0x88 + bne reg1_error_loopf + cmp r1, #0x99 + bne reg1_error_loopf + vmov r0, r1, d5 + cmp r0, #0xAA + bne reg1_error_loopf + cmp r1, #0xBB + bne reg1_error_loopf + vmov r0, r1, d6 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d7 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d8 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d9 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + vmov r0, r1, d10 + cmp r0, #0x88 + bne reg1_error_loopf + cmp r1, #0x99 + bne reg1_error_loopf + vmov r0, r1, d11 + cmp r0, #0xAA + bne reg1_error_loopf + cmp r1, #0xBB + bne reg1_error_loopf + vmov r0, r1, d12 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d13 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d14 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d15 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg1_loopf_pass + +reg1_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg1_error_loopf + +reg1_loopf_pass: + + /* Test each general purpose register to check that it still contains the + expected known value, jumping to reg1_error_loop if any register contains + an unexpected value. */ + cmp r0, #0xFF + bne reg1_error_loop + cmp r1, #0x11 + bne reg1_error_loop + cmp r2, #0x22 + bne reg1_error_loop + cmp r3, #0x33 + bne reg1_error_loop + cmp r4, #0x44 + bne reg1_error_loop + cmp r5, #0x55 + bne reg1_error_loop + cmp r6, #0x66 + bne reg1_error_loop + cmp r7, #0x77 + bne reg1_error_loop + cmp r8, #0x88 + bne reg1_error_loop + cmp r9, #0x99 + bne reg1_error_loop + cmp r10, #0xAA + bne reg1_error_loop + cmp r11, #0xBB + bne reg1_error_loop + cmp r12, #0xCC + bne reg1_error_loop + cmp r14, #0xEE + bne reg1_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + nop + +/*-----------------------------------------------------------*/ + +.type vRegTest2Implementation, %function +vRegTest2Implementation: + + /* Put a known value in each register. */ + mov r0, #0xFF000000 + mov r1, #0x11000000 + mov r2, #0x22000000 + mov r3, #0x33000000 + mov r4, #0x44000000 + mov r5, #0x55000000 + mov r6, #0x66000000 + mov r7, #0x77000000 + mov r8, #0x88000000 + mov r9, #0x99000000 + mov r10, #0xAA000000 + mov r11, #0xBB000000 + mov r12, #0xCC000000 + mov r14, #0xEE000000 + + /* Likewise the floating point registers */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + + /* Loop, checking each itteration that each register still contains the + expected value. */ +reg2_loop: + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d1 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d2 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d3 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + vmov r0, r1, d4 + cmp r0, #0x88000000 + bne reg2_error_loopf + cmp r1, #0x99000000 + bne reg2_error_loopf + vmov r0, r1, d5 + cmp r0, #0xAA000000 + bne reg2_error_loopf + cmp r1, #0xBB000000 + bne reg2_error_loopf + vmov r0, r1, d6 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d7 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d8 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d9 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + vmov r0, r1, d10 + cmp r0, #0x88000000 + bne reg2_error_loopf + cmp r1, #0x99000000 + bne reg2_error_loopf + vmov r0, r1, d11 + cmp r0, #0xAA000000 + bne reg2_error_loopf + cmp r1, #0xBB000000 + bne reg2_error_loopf + vmov r0, r1, d12 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d13 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d14 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d15 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg2_loopf_pass + +reg2_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg2_error_loopf + +reg2_loopf_pass: + + cmp r0, #0xFF000000 + bne reg2_error_loop + cmp r1, #0x11000000 + bne reg2_error_loop + cmp r2, #0x22000000 + bne reg2_error_loop + cmp r3, #0x33000000 + bne reg2_error_loop + cmp r4, #0x44000000 + bne reg2_error_loop + cmp r5, #0x55000000 + bne reg2_error_loop + cmp r6, #0x66000000 + bne reg2_error_loop + cmp r7, #0x77000000 + bne reg2_error_loop + cmp r8, #0x88000000 + bne reg2_error_loop + cmp r9, #0x99000000 + bne reg2_error_loop + cmp r10, #0xAA000000 + bne reg2_error_loop + cmp r11, #0xBB000000 + bne reg2_error_loop + cmp r12, #0xCC000000 + bne reg2_error_loop + cmp r14, #0xEE000000 + bne reg2_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg2_error_loop + nop + + + .end + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/reg_test_IAR.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/reg_test_IAR.asm new file mode 100644 index 000000000..653edaaf4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/Full_Demo/reg_test_IAR.asm @@ -0,0 +1,462 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2014 Real Time Engineers Ltd. + + FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT + http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + + >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + details. You should have received a copy of the GNU General Public License + and the FreeRTOS license exception along with FreeRTOS; if not itcan be + viewed here: http://www.freertos.org/a00114.html and also obtained by + writing to Real Time Engineers Ltd., contact details for whom are available + on the FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, and our new + fully thread aware and reentrant UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems, who sell the code with commercial support, + indemnification and middleware, under the OpenRTOS brand. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. +*/ + + PUBLIC vRegTest1Implementation + PUBLIC vRegTest2Implementation + EXTERN ulRegTest1LoopCounter + EXTERN ulRegTest2LoopCounter + + SECTION intvec:CODE:ROOT(2) + ARM + + /* This function is explained in the comments at the top of main-full.c. */ +vRegTest1Implementation: + + /* Fill each general purpose register with a known value. */ + mov r0, #0xFF + mov r1, #0x11 + mov r2, #0x22 + mov r3, #0x33 + mov r4, #0x44 + mov r5, #0x55 + mov r6, #0x66 + mov r7, #0x77 + mov r8, #0x88 + mov r9, #0x99 + mov r10, #0xAA + mov r11, #0xBB + mov r12, #0xCC + mov r14, #0xEE + + + /* Fill each FPU register with a known value. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + + /* Loop, checking each itteration that each register still contains the + expected value. */ +reg1_loop: + /* Yield to increase test coverage */ + svc 0 + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d1 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d2 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d3 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + vmov r0, r1, d4 + cmp r0, #0x88 + bne reg1_error_loopf + cmp r1, #0x99 + bne reg1_error_loopf + vmov r0, r1, d5 + cmp r0, #0xAA + bne reg1_error_loopf + cmp r1, #0xBB + bne reg1_error_loopf + vmov r0, r1, d6 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d7 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d8 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d9 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + vmov r0, r1, d10 + cmp r0, #0x88 + bne reg1_error_loopf + cmp r1, #0x99 + bne reg1_error_loopf + vmov r0, r1, d11 + cmp r0, #0xAA + bne reg1_error_loopf + cmp r1, #0xBB + bne reg1_error_loopf + vmov r0, r1, d12 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d13 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d14 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d15 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg1_loopf_pass + +reg1_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg1_error_loopf + +reg1_loopf_pass: + + /* Test each general purpose register to check that it still contains the + expected known value, jumping to reg1_error_loop if any register contains + an unexpected value. */ + cmp r0, #0xFF + bne reg1_error_loop + cmp r1, #0x11 + bne reg1_error_loop + cmp r2, #0x22 + bne reg1_error_loop + cmp r3, #0x33 + bne reg1_error_loop + cmp r4, #0x44 + bne reg1_error_loop + cmp r5, #0x55 + bne reg1_error_loop + cmp r6, #0x66 + bne reg1_error_loop + cmp r7, #0x77 + bne reg1_error_loop + cmp r8, #0x88 + bne reg1_error_loop + cmp r9, #0x99 + bne reg1_error_loop + cmp r10, #0xAA + bne reg1_error_loop + cmp r11, #0xBB + bne reg1_error_loop + cmp r12, #0xCC + bne reg1_error_loop + cmp r14, #0xEE + bne reg1_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + nop + +/*-----------------------------------------------------------*/ + +vRegTest2Implementation: + + /* Put a known value in each register. */ + mov r0, #0xFF000000 + mov r1, #0x11000000 + mov r2, #0x22000000 + mov r3, #0x33000000 + mov r4, #0x44000000 + mov r5, #0x55000000 + mov r6, #0x66000000 + mov r7, #0x77000000 + mov r8, #0x88000000 + mov r9, #0x99000000 + mov r10, #0xAA000000 + mov r11, #0xBB000000 + mov r12, #0xCC000000 + mov r14, #0xEE000000 + + /* Likewise the floating point registers */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + + /* Loop, checking each itteration that each register still contains the + expected value. */ +reg2_loop: + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d1 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d2 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d3 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + vmov r0, r1, d4 + cmp r0, #0x88000000 + bne reg2_error_loopf + cmp r1, #0x99000000 + bne reg2_error_loopf + vmov r0, r1, d5 + cmp r0, #0xAA000000 + bne reg2_error_loopf + cmp r1, #0xBB000000 + bne reg2_error_loopf + vmov r0, r1, d6 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d7 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d8 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d9 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + vmov r0, r1, d10 + cmp r0, #0x88000000 + bne reg2_error_loopf + cmp r1, #0x99000000 + bne reg2_error_loopf + vmov r0, r1, d11 + cmp r0, #0xAA000000 + bne reg2_error_loopf + cmp r1, #0xBB000000 + bne reg2_error_loopf + vmov r0, r1, d12 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d13 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d14 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d15 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg2_loopf_pass + +reg2_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg2_error_loopf + +reg2_loopf_pass: + + cmp r0, #0xFF000000 + bne reg2_error_loop + cmp r1, #0x11000000 + bne reg2_error_loop + cmp r2, #0x22000000 + bne reg2_error_loop + cmp r3, #0x33000000 + bne reg2_error_loop + cmp r4, #0x44000000 + bne reg2_error_loop + cmp r5, #0x55000000 + bne reg2_error_loop + cmp r6, #0x66000000 + bne reg2_error_loop + cmp r7, #0x77000000 + bne reg2_error_loop + cmp r8, #0x88000000 + bne reg2_error_loop + cmp r9, #0x99000000 + bne reg2_error_loop + cmp r10, #0xAA000000 + bne reg2_error_loop + cmp r11, #0xBB000000 + bne reg2_error_loop + cmp r12, #0xCC000000 + bne reg2_error_loop + cmp r14, #0xEE000000 + bne reg2_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg2_error_loop + nop + + + END + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/iodefine.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/iodefine.h new file mode 100644 index 000000000..366367f10 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/iodefine.h @@ -0,0 +1,45398 @@ +/********************************************************************************/ +/* */ +/* Device : RZ/T1 */ +/* File Name : iodefine.h */ +/* Abstract : Definition of I/O Register. */ +/* History : V0.8 (2015-02-23) [Hardware Manual Revision : 0.8] */ +/* Note : This is a typical example. */ +/* */ +/* Copyright(c) 2015 Renesas Electronics Corp. ,All Rights Reserved. */ +/* */ +/********************************************************************************/ +#ifndef __RZT1___IODEFINE_HEADER__ +#define __RZT1___IODEFINE_HEADER__ +struct st_bsc +{ + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS0BCR; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS1BCR; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS2BCR; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS3BCR; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS4BCR; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long BSZ:2; + unsigned long :1; + unsigned long TYPE:3; + unsigned long :1; + unsigned long IWRRS:3; + unsigned long IWRRD:3; + unsigned long IWRWS:3; + unsigned long IWRWD:3; + unsigned long IWW:3; + unsigned long :1; + } BIT; + } CS5BCR; + char wk0[12]; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long HW:2; + unsigned long :4; + unsigned long WM:1; + unsigned long WR:4; + unsigned long SW:2; + unsigned long :7; + unsigned long BAS:1; + unsigned long :11; + } BIT; + } CS0WCR_0; + union + { + unsigned long LONG; + struct + { + unsigned long :6; + unsigned long WM:1; + unsigned long W:4; + unsigned long :5; + unsigned long BW:2; + unsigned long :2; + unsigned long BST:2; + unsigned long :10; + } BIT; + } CS0WCR_1; + union + { + unsigned long LONG; + struct + { + unsigned long :6; + unsigned long WM:1; + unsigned long W:4; + unsigned long :5; + unsigned long BW:2; + unsigned long :14; + } BIT; + } CS0WCR_2; + } CS0WCR; + union + { + unsigned long LONG; + struct + { + unsigned long HW:2; + unsigned long :4; + unsigned long WM:1; + unsigned long WR:4; + unsigned long SW:2; + unsigned long :3; + unsigned long WW:3; + unsigned long :1; + unsigned long BAS:1; + unsigned long :11; + } BIT; + } CS1WCR; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long :6; + unsigned long WM:1; + unsigned long WR:4; + unsigned long :9; + unsigned long BAS:1; + unsigned long :11; + } BIT; + } CS2WCR_0; + union + { + unsigned long LONG; + struct + { + unsigned long :7; + unsigned long A2CL:2; + unsigned long :23; + } BIT; + } CS2WCR_1; + } CS2WCR; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long :6; + unsigned long WM:1; + unsigned long WR:4; + unsigned long :9; + unsigned long BAS:1; + unsigned long :11; + } BIT; + } CS3WCR_0; + union + { + unsigned long LONG; + struct + { + unsigned long WTRC:2; + unsigned long :1; + unsigned long TRWL:2; + unsigned long :2; + unsigned long A3CL:2; + unsigned long :1; + unsigned long WTRCD:2; + unsigned long :1; + unsigned long WTRP:2; + unsigned long :17; + } BIT; + } CS3WCR_1; + } CS3WCR; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long HW:2; + unsigned long :4; + unsigned long WM:1; + unsigned long WR:4; + unsigned long SW:2; + unsigned long :3; + unsigned long WW:3; + unsigned long :1; + unsigned long BAS:1; + unsigned long :11; + } BIT; + } CS4WCR_0; + union + { + unsigned long LONG; + struct + { + unsigned long HW:2; + unsigned long :4; + unsigned long WM:1; + unsigned long W:4; + unsigned long SW:2; + unsigned long :3; + unsigned long BW:2; + unsigned long :2; + unsigned long BST:2; + unsigned long :10; + } BIT; + } CS4WCR_1; + } CS4WCR; + union + { + unsigned long LONG; + struct + { + unsigned long HW:2; + unsigned long :4; + unsigned long WM:1; + unsigned long WR:4; + unsigned long SW:2; + unsigned long :3; + unsigned long WW:3; + unsigned long :1; + unsigned long MPXWBAS:1; + unsigned long SZSEL:1; + unsigned long :10; + } BIT; + } CS5WCR; + char wk1[12]; + union + { + unsigned long LONG; + struct + { + unsigned long A3COL:2; + unsigned long :1; + unsigned long A3ROW:2; + unsigned long :3; + unsigned long BACTV:1; + unsigned long PDOWN:1; + unsigned long RMODE:1; + unsigned long RFSH:1; + unsigned long :1; + unsigned long DEEP:1; + unsigned long :2; + unsigned long A2COL:2; + unsigned long :1; + unsigned long A2ROW:2; + unsigned long :11; + } BIT; + } SDCR; + union + { + unsigned long LONG; + } RTCSR; + unsigned long RTCNT; + unsigned long RTCOR; + char wk2[4]; + unsigned long TOSCOR0; + unsigned long TOSCOR1; + unsigned long TOSCOR2; + unsigned long TOSCOR3; + unsigned long TOSCOR4; + unsigned long TOSCOR5; + char wk3[8]; + union + { + unsigned long LONG; + struct + { + unsigned long CS0TOSTF:1; + unsigned long CS1TOSTF:1; + unsigned long CS2TOSTF:1; + unsigned long CS3TOSTF:1; + unsigned long CS4TOSTF:1; + unsigned long CS5TOSTF:1; + unsigned long :26; + } BIT; + } TOSTR; + union + { + unsigned long LONG; + struct + { + unsigned long CS0TOEN:1; + unsigned long CS1TOEN:1; + unsigned long CS2TOEN:1; + unsigned long CS3TOEN:1; + unsigned long CS4TOEN:1; + unsigned long CS5TOEN:1; + unsigned long :26; + } BIT; + } TOENR; + char wk4[2948]; + union + { + unsigned long LONG; + } CKIOSET; + char wk5[236]; + union + { + unsigned char BYTE; + } CKIOKEY; +}; + +struct st_clma0 +{ + union + { + unsigned char BYTE; + } CLMA0CTL0; + char wk0[7]; + union + { + unsigned short WORD; + struct + { + unsigned short CLMAnCMPL:12; + unsigned short :4; + } BIT; + } CLMA0CMPL; + char wk1[2]; + union + { + unsigned short WORD; + struct + { + unsigned short CLMAnCMPH:12; + unsigned short :4; + } BIT; + } CLMA0CMPH; + char wk2[2]; + union + { + unsigned char BYTE; + } CLMA0PCMD; + char wk3[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char CLMAnPRERR:1; + unsigned char :7; + } BIT; + } CLMA0PS; +}; + +struct st_clma1 +{ + union + { + unsigned char BYTE; + } CLMA1CTL0; + char wk0[7]; + union + { + unsigned short WORD; + struct + { + unsigned short CLMAnCMPL:12; + unsigned short :4; + } BIT; + } CLMA1CMPL; + char wk1[2]; + union + { + unsigned short WORD; + struct + { + unsigned short CLMAnCMPH:12; + unsigned short :4; + } BIT; + } CLMA1CMPH; + char wk2[2]; + union + { + unsigned char BYTE; + } CLMA1PCMD; + char wk3[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char CLMAnPRERR:1; + unsigned char :7; + } BIT; + } CLMA1PS; +}; + +struct st_clma2 +{ + union + { + unsigned char BYTE; + } CLMA2CTL0; + char wk0[7]; + union + { + unsigned short WORD; + struct + { + unsigned short CLMAnCMPL:12; + unsigned short :4; + } BIT; + } CLMA2CMPL; + char wk1[2]; + union + { + unsigned short WORD; + struct + { + unsigned short CLMAnCMPH:12; + unsigned short :4; + } BIT; + } CLMA2CMPH; + char wk2[2]; + union + { + unsigned char BYTE; + } CLMA2PCMD; + char wk3[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char CLMAnPRERR:1; + unsigned char :7; + } BIT; + } CLMA2PS; +}; + +struct st_cmt +{ + union + { + unsigned short WORD; + struct + { + unsigned short STR0:1; + unsigned short STR1:1; + unsigned short :14; + } BIT; + } CMSTR0; + char wk0[30]; + union + { + unsigned short WORD; + struct + { + unsigned short STR2:1; + unsigned short STR3:1; + unsigned short :14; + } BIT; + } CMSTR1; + char wk1[30]; + union + { + unsigned short WORD; + struct + { + unsigned short STR4:1; + unsigned short STR5:1; + unsigned short :14; + } BIT; + } CMSTR2; +}; + +struct st_cmt0 +{ + union + { + unsigned short WORD; + struct + { + unsigned short CKS:2; + unsigned short :4; + unsigned short CMIE:1; + unsigned short :9; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_cmtw +{ + union + { + unsigned long LONG; + struct + { + unsigned long NF0EN:1; + unsigned long NF1EN:1; + unsigned long NFCS0:2; + unsigned long :28; + } BIT; + } NFCR0; + union + { + unsigned long LONG; + struct + { + unsigned long NF2EN:1; + unsigned long NF3EN:1; + unsigned long NFCS1:2; + unsigned long :28; + } BIT; + } NFCR1; + char wk0[8]; + union + { + unsigned long LONG; + struct + { + unsigned long DMERSL:3; + unsigned long :29; + } BIT; + } ECDMESLR; +}; + +struct st_cmtw0 +{ + union + { + unsigned short WORD; + struct + { + unsigned short STR:1; + unsigned short :15; + } BIT; + } CMWSTR; + char wk0[2]; + union + { + unsigned short WORD; + struct + { + unsigned short CKS:2; + unsigned short :1; + unsigned short CMWIE:1; + unsigned short IC0IE:1; + unsigned short IC1IE:1; + unsigned short OC0IE:1; + unsigned short OC1IE:1; + unsigned short :1; + unsigned short CMS:1; + unsigned short :3; + unsigned short CCLR:3; + } BIT; + } CMWCR; + char wk1[2]; + union + { + unsigned short WORD; + struct + { + unsigned short IC0:2; + unsigned short IC1:2; + unsigned short IC0E:1; + unsigned short IC1E:1; + unsigned short :2; + unsigned short OC0:2; + unsigned short OC1:2; + unsigned short OC0E:1; + unsigned short OC1E:1; + unsigned short :1; + unsigned short CMWE:1; + } BIT; + } CMWIOR; + char wk2[6]; + unsigned long CMWCNT; + unsigned long CMWCOR; + unsigned long CMWICR0; + unsigned long CMWICR1; + unsigned long CMWOCR0; + unsigned long CMWOCR1; +}; + +struct st_crc +{ + union + { + unsigned long LONG; + struct + { + unsigned long DCRA0CIN:32; + } BIT; + } CRCDIR; + union + { + unsigned long LONG; + struct + { + unsigned long DCRA0COUT:32; + } BIT; + } CRCDOR; + char wk0[24]; + union + { + unsigned char BYTE; + struct + { + unsigned char DCRA0POL:2; + unsigned char :2; + unsigned char DCRA0ISZ:2; + unsigned char :2; + } BIT; + } CRCCR; +}; + +struct st_dma0 +{ + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_0_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_0_W; + } N0SA_0; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_0; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_0; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_0_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_0_W; + } N1SA_0; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_0; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_0; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_0; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_0; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_0; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_0; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_0; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_1_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_1_W; + } N0SA_1; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_1; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_1; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_1_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_1_W; + } N1SA_1; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_1; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_1; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_1; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_1; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_1; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_1; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_1; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_2_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_2_W; + } N0SA_2; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_2; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_2; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_2_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_2_W; + } N1SA_2; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_2; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_2; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_2; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_2; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_2; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_2; + char wk2[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_2; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_3_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_3_W; + } N0SA_3; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_3; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_3; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_3_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_3_W; + } N1SA_3; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_3; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_3; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_3; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_3; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_3; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_3; + char wk3[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_3; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_4_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_4_W; + } N0SA_4; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_4; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_4; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_4_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_4_W; + } N1SA_4; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_4; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_4; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_4; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_4; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_4; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_4; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_4; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_5_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_5_W; + } N0SA_5; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_5; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_5; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_5_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_5_W; + } N1SA_5; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_5; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_5; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_5; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_5; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_5; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_5; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_5; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_6_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_6_W; + } N0SA_6; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_6; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_6; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_6_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_6_W; + } N1SA_6; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_6; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_6; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_6; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_6; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_6; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_6; + char wk6[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_6; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_7_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_7_W; + } N0SA_7; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_7; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_7; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_7_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_7_W; + } N1SA_7; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_7; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_7; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_7; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_7; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_7; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_7; + char wk7[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_7; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_0; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_0; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_0; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_0; + char wk8[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_1; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_1; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_1; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_1; + char wk9[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_2; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_2; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_2; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_2; + char wk10[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_3; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_3; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_3; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_3; + char wk11[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_4; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_4; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_4; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_4; + char wk12[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_5; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_5; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_5; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_5; + char wk13[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_6; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_6; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_6; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_6; + char wk14[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_7; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_7; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_7; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_7; + char wk15[16]; + union + { + unsigned long LONG; + struct + { + unsigned long PR:1; + unsigned long :31; + } BIT; + } DMAC0_DCTRL_A; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long DITVL:8; + unsigned long :16; + } BIT; + } DMAC0_DSCITVL_A; + char wk16[8]; + union + { + unsigned long LONG; + struct + { + unsigned long EN08:1; + unsigned long EN19:1; + unsigned long EN210:1; + unsigned long EN311:1; + unsigned long EN412:1; + unsigned long EN513:1; + unsigned long EN614:1; + unsigned long EN715:1; + unsigned long :24; + } BIT; + } DMAC0_DST_EN_A; + union + { + unsigned long LONG; + struct + { + unsigned long ER08:1; + unsigned long ER19:1; + unsigned long ER210:1; + unsigned long ER311:1; + unsigned long ER412:1; + unsigned long ER513:1; + unsigned long ER614:1; + unsigned long ER715:1; + unsigned long :24; + } BIT; + } DMAC0_DST_ER_A; + union + { + unsigned long LONG; + struct + { + unsigned long END08:1; + unsigned long END19:1; + unsigned long END210:1; + unsigned long END311:1; + unsigned long END412:1; + unsigned long END513:1; + unsigned long END614:1; + unsigned long END715:1; + unsigned long :24; + } BIT; + } DMAC0_DST_END_A; + char wk17[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SUS08:1; + unsigned long SUS19:1; + unsigned long SUS210:1; + unsigned long SUS311:1; + unsigned long SUS412:1; + unsigned long SUS513:1; + unsigned long SUS614:1; + unsigned long SUS715:1; + unsigned long :24; + } BIT; + } DMAC0_DST_SUS_A; + char wk18[220]; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_8_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_8_W; + } N0SA_8; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_8; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_8; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_8_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_8_W; + } N1SA_8; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_8; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_8; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_8; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_8; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_8; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_8; + char wk19[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_8; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_9_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_9_W; + } N0SA_9; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_9; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_9; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_9_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_9_W; + } N1SA_9; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_9; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_9; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_9; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_9; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_9; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_9; + char wk20[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_9; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_10_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_10_W; + } N0SA_10; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_10; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_10; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_10_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_10_W; + } N1SA_10; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_10; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_10; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_10; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_10; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_10; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_10; + char wk21[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_10; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_11_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_11_W; + } N0SA_11; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_11; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_11; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_11_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_11_W; + } N1SA_11; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_11; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_11; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_11; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_11; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_11; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_11; + char wk22[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_11; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_12_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_12_W; + } N0SA_12; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_12; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_12; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_12_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_12_W; + } N1SA_12; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_12; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_12; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_12; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_12; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_12; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_12; + char wk23[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_12; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_13_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_13_W; + } N0SA_13; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_13; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_13; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_13_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_13_W; + } N1SA_13; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_13; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_13; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_13; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_13; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_13; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_13; + char wk24[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_13; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_14_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_14_W; + } N0SA_14; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_14; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_14; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_14_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_14_W; + } N1SA_14; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_14; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_14; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_14; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_14; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_14; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_14; + char wk25[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_14; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N0SA_15_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N0SA_15_W; + } N0SA_15; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N0DA_15; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N0TB_15; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC0_N1SA_15_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC0_N1SA_15_W; + } N1SA_15; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC0_N1DA_15; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC0_N1TB_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC0_CRSA_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC0_CRDA_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC0_CRTB_15; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC0_CHSTAT_15; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC0_CHCTRL_15; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC0_CHCFG_15; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC0_CHITVL_15; + char wk26[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC0_NXLA_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC0_CRLA_15; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_8; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_8; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_8; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_8; + char wk27[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_9; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_9; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_9; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_9; + char wk28[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_10; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_10; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_10; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_10; + char wk29[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_11; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_11; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_11; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_11; + char wk30[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_12; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_12; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_12; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_12; + char wk31[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_13; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_13; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_13; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_13; + char wk32[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_14; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_14; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_14; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_14; + char wk33[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC0_SCNT_15; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC0_SSKP_15; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC0_DCNT_15; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC0_DSKP_15; + char wk34[16]; + union + { + unsigned long LONG; + struct + { + unsigned long PR:1; + unsigned long :31; + } BIT; + } DMAC0_DCTRL_B; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long DITVL:8; + unsigned long :16; + } BIT; + } DMAC0_DSCITVL_B; + char wk35[8]; + union + { + unsigned long LONG; + struct + { + unsigned long EN08:1; + unsigned long EN19:1; + unsigned long EN210:1; + unsigned long EN311:1; + unsigned long EN412:1; + unsigned long EN513:1; + unsigned long EN614:1; + unsigned long EN715:1; + unsigned long :24; + } BIT; + } DMAC0_DST_EN_B; + union + { + unsigned long LONG; + struct + { + unsigned long ER08:1; + unsigned long ER19:1; + unsigned long ER210:1; + unsigned long ER311:1; + unsigned long ER412:1; + unsigned long ER513:1; + unsigned long ER614:1; + unsigned long ER715:1; + unsigned long :24; + } BIT; + } DMAC0_DST_ER_B; + union + { + unsigned long LONG; + struct + { + unsigned long END08:1; + unsigned long END19:1; + unsigned long END210:1; + unsigned long END311:1; + unsigned long END412:1; + unsigned long END513:1; + unsigned long END614:1; + unsigned long END715:1; + unsigned long :24; + } BIT; + } DMAC0_DST_END_B; + char wk36[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SUS08:1; + unsigned long SUS19:1; + unsigned long SUS210:1; + unsigned long SUS311:1; + unsigned long SUS412:1; + unsigned long SUS513:1; + unsigned long SUS614:1; + unsigned long SUS715:1; + unsigned long :24; + } BIT; + } DMAC0_DST_SUS_B; + char wk37[202972]; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL0; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL1; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL2; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL3; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL4; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL5; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL6; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL7; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL8; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL9; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL10; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL11; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL12; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL13; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL14; + union + { + unsigned long LONG; + struct + { + unsigned long IFC0:8; + unsigned long :24; + } BIT; + } DMA0SEL15; +}; + +struct st_dma1 +{ + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_0_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_0_W; + } N0SA_0; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_0; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_0; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_0_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_0_W; + } N1SA_0; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_0; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_0; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_0; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_0; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_0; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_0; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_0; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_0; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_1_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_1_W; + } N0SA_1; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_1; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_1; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_1_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_1_W; + } N1SA_1; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_1; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_1; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_1; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_1; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_1; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_1; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_1; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_1; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_2_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_2_W; + } N0SA_2; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_2; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_2; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_2_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_2_W; + } N1SA_2; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_2; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_2; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_2; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_2; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_2; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_2; + char wk2[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_2; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_2; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_3_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_3_W; + } N0SA_3; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_3; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_3; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_3_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_3_W; + } N1SA_3; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_3; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_3; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_3; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_3; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_3; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_3; + char wk3[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_3; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_3; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_4_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_4_W; + } N0SA_4; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_4; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_4; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_4_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_4_W; + } N1SA_4; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_4; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_4; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_4; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_4; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_4; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_4; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_4; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_4; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_5_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_5_W; + } N0SA_5; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_5; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_5; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_5_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_5_W; + } N1SA_5; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_5; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_5; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_5; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_5; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_5; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_5; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_5; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_5; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_6_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_6_W; + } N0SA_6; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_6; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_6; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_6_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_6_W; + } N1SA_6; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_6; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_6; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_6; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_6; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_6; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_6; + char wk6[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_6; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_6; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_7_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_7_W; + } N0SA_7; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_7; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_7; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_7_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_7_W; + } N1SA_7; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_7; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_7; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_7; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_7; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_7; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_7; + char wk7[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_7; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_7; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_0; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_0; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_0; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_0; + char wk8[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_1; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_1; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_1; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_1; + char wk9[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_2; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_2; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_2; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_2; + char wk10[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_3; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_3; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_3; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_3; + char wk11[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_4; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_4; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_4; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_4; + char wk12[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_5; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_5; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_5; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_5; + char wk13[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_6; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_6; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_6; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_6; + char wk14[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_7; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_7; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_7; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_7; + char wk15[16]; + union + { + unsigned long LONG; + struct + { + unsigned long PR:1; + unsigned long :31; + } BIT; + } DMAC1_DCTRL_A; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long DITVL:8; + unsigned long :16; + } BIT; + } DMAC1_DSCITVL_A; + char wk16[8]; + union + { + unsigned long LONG; + struct + { + unsigned long EN08:1; + unsigned long EN19:1; + unsigned long EN210:1; + unsigned long EN311:1; + unsigned long EN412:1; + unsigned long EN513:1; + unsigned long EN614:1; + unsigned long EN715:1; + unsigned long :24; + } BIT; + } DMAC1_DST_EN_A; + union + { + unsigned long LONG; + struct + { + unsigned long ER08:1; + unsigned long ER19:1; + unsigned long ER210:1; + unsigned long ER311:1; + unsigned long ER412:1; + unsigned long ER513:1; + unsigned long ER614:1; + unsigned long ER715:1; + unsigned long :24; + } BIT; + } DMAC1_DST_ER_A; + union + { + unsigned long LONG; + struct + { + unsigned long END08:1; + unsigned long END19:1; + unsigned long END210:1; + unsigned long END311:1; + unsigned long END412:1; + unsigned long END513:1; + unsigned long END614:1; + unsigned long END715:1; + unsigned long :24; + } BIT; + } DMAC1_DST_END_A; + char wk17[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SUS08:1; + unsigned long SUS19:1; + unsigned long SUS210:1; + unsigned long SUS311:1; + unsigned long SUS412:1; + unsigned long SUS513:1; + unsigned long SUS614:1; + unsigned long SUS715:1; + unsigned long :24; + } BIT; + } DMAC1_DST_SUS_A; + char wk18[220]; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_8_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_8_W; + } N0SA_8; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_8; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_8; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_8_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_8_W; + } N1SA_8; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_8; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_8; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_8; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_8; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_8; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_8; + char wk19[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_8; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_8; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_9_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_9_W; + } N0SA_9; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_9; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_9; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_9_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_9_W; + } N1SA_9; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_9; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_9; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_9; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_9; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_9; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_9; + char wk20[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_9; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_9; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_10_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_10_W; + } N0SA_10; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_10; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_10; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_10_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_10_W; + } N1SA_10; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_10; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_10; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_10; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_10; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_10; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_10; + char wk21[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_10; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_10; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_11_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_11_W; + } N0SA_11; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_11; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_11; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_11_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_11_W; + } N1SA_11; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_11; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_11; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_11; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_11; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_11; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_11; + char wk22[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_11; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_11; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_12_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_12_W; + } N0SA_12; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_12; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_12; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_12_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_12_W; + } N1SA_12; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_12; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_12; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_12; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_12; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_12; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_12; + char wk23[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_12; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_12; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_13_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_13_W; + } N0SA_13; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_13; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_13; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_13_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_13_W; + } N1SA_13; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_13; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_13; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_13; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_13; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_13; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_13; + char wk24[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_13; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_13; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_14_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_14_W; + } N0SA_14; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_14; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_14; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_14_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_14_W; + } N1SA_14; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_14; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_14; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_14; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_14; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_14; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_14; + char wk25[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_14; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_14; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N0SA_15_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N0SA_15_W; + } N0SA_15; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N0DA_15; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N0TB_15; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SA:32; + } BIT; + } DMAC1_N1SA_15_N; + union + { + unsigned long LONG; + struct + { + unsigned long WD:32; + } BIT; + } DMAC1_N1SA_15_W; + } N1SA_15; + union + { + unsigned long LONG; + struct + { + unsigned long DA:32; + } BIT; + } DMAC1_N1DA_15; + union + { + unsigned long LONG; + struct + { + unsigned long TB:32; + } BIT; + } DMAC1_N1TB_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRSA:32; + } BIT; + } DMAC1_CRSA_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRDA:32; + } BIT; + } DMAC1_CRDA_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRTB:32; + } BIT; + } DMAC1_CRTB_15; + union + { + unsigned long LONG; + struct + { + unsigned long EN:1; + unsigned long RQST:1; + unsigned long TACT:1; + unsigned long SUS:1; + unsigned long ER:1; + unsigned long END:1; + unsigned long :1; + unsigned long SR:1; + unsigned long DL:1; + unsigned long DW:1; + unsigned long DER:1; + unsigned long MODE:1; + unsigned long :4; + unsigned long INTM:1; + unsigned long DMARQM:1; + unsigned long SWPRQ:1; + unsigned long :5; + unsigned long DNUM:8; + } BIT; + } DMAC1_CHSTAT_15; + union + { + unsigned long LONG; + struct + { + unsigned long SETEN:1; + unsigned long CLREN:1; + unsigned long :1; + unsigned long SWRST:1; + unsigned long CLRRQ:1; + unsigned long CLREND:1; + unsigned long :1; + unsigned long CLRDE:1; + unsigned long SETSUS:1; + unsigned long CLRSUS:1; + unsigned long :2; + unsigned long SETREN:1; + unsigned long :1; + unsigned long SETSSWPRQ:1; + unsigned long :1; + unsigned long SETINTM:1; + unsigned long CLRINTM:1; + unsigned long SETDMARQM:1; + unsigned long CLRDMARQM:1; + unsigned long :12; + } BIT; + } DMAC1_CHCTRL_15; + union + { + unsigned long LONG; + struct + { + unsigned long SEL:3; + unsigned long REQD:1; + unsigned long LOEN:1; + unsigned long HIEN:1; + unsigned long LVL:1; + unsigned long :1; + unsigned long AM:3; + unsigned long DRRP:1; + unsigned long SDS:4; + unsigned long DDS:4; + unsigned long SAD:1; + unsigned long DAD:1; + unsigned long TM:1; + unsigned long WONLY:1; + unsigned long DEM:1; + unsigned long :1; + unsigned long DIM:1; + unsigned long SBE:1; + unsigned long RSEL:1; + unsigned long RSW:1; + unsigned long REN:1; + unsigned long DMS:1; + } BIT; + } DMAC1_CHCFG_15; + union + { + unsigned long LONG; + struct + { + unsigned long ITVL:16; + unsigned long :16; + } BIT; + } DMAC1_CHITVL_15; + char wk26[4]; + union + { + unsigned long LONG; + struct + { + unsigned long NXLA:32; + } BIT; + } DMAC1_NXLA_15; + union + { + unsigned long LONG; + struct + { + unsigned long CRLA:32; + } BIT; + } DMAC1_CRLA_15; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_8; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_8; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_8; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_8; + char wk27[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_9; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_9; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_9; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_9; + char wk28[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_10; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_10; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_10; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_10; + char wk29[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_11; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_11; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_11; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_11; + char wk30[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_12; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_12; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_12; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_12; + char wk31[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_13; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_13; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_13; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_13; + char wk32[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_14; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_14; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_14; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_14; + char wk33[16]; + union + { + unsigned long LONG; + struct + { + unsigned long SCNT:32; + } BIT; + } DMAC1_SCNT_15; + union + { + unsigned long LONG; + struct + { + unsigned long SSKP:32; + } BIT; + } DMAC1_SSKP_15; + union + { + unsigned long LONG; + struct + { + unsigned long DCNT:32; + } BIT; + } DMAC1_DCNT_15; + union + { + unsigned long LONG; + struct + { + unsigned long DSKP:32; + } BIT; + } DMAC1_DSKP_15; + char wk34[16]; + union + { + unsigned long LONG; + struct + { + unsigned long PR:1; + unsigned long :31; + } BIT; + } DMAC1_DCTRL_B; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long DITVL:8; + unsigned long :16; + } BIT; + } DMAC1_DSCITVL_B; + char wk35[8]; + union + { + unsigned long LONG; + struct + { + unsigned long EN08:1; + unsigned long EN19:1; + unsigned long EN210:1; + unsigned long EN311:1; + unsigned long EN412:1; + unsigned long EN513:1; + unsigned long EN614:1; + unsigned long EN715:1; + unsigned long :24; + } BIT; + } DMAC1_DST_EN_B; + union + { + unsigned long LONG; + struct + { + unsigned long ER08:1; + unsigned long ER19:1; + unsigned long ER210:1; + unsigned long ER311:1; + unsigned long ER412:1; + unsigned long ER513:1; + unsigned long ER614:1; + unsigned long ER715:1; + unsigned long :24; + } BIT; + } DMAC1_DST_ER_B; + union + { + unsigned long LONG; + struct + { + unsigned long END08:1; + unsigned long END19:1; + unsigned long END210:1; + unsigned long END311:1; + unsigned long END412:1; + unsigned long END513:1; + unsigned long END614:1; + unsigned long END715:1; + unsigned long :24; + } BIT; + } DMAC1_DST_END_B; + char wk36[4]; + union + { + unsigned long LONG; + struct + { + unsigned long SUS08:1; + unsigned long SUS19:1; + unsigned long SUS210:1; + unsigned long SUS311:1; + unsigned long SUS412:1; + unsigned long SUS513:1; + unsigned long SUS614:1; + unsigned long SUS715:1; + unsigned long :24; + } BIT; + } DMAC1_DST_SUS_B; + char wk37[198940]; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL0; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL1; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL2; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL3; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL4; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL5; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL6; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL7; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL8; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL9; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL10; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL11; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL12; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL13; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL14; + union + { + unsigned long LONG; + struct + { + unsigned long IFC1:8; + unsigned long :24; + } BIT; + } DMA1SEL15; +}; + +struct st_dmac +{ + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long DPRTY:2; + unsigned long :13; + unsigned long AL0:1; + unsigned long AL1:1; + unsigned long AL2:1; + unsigned long :1; + unsigned long TL0:1; + unsigned long TL1:1; + unsigned long TL2:1; + unsigned long :1; + } BIT; + } CMNCR; + char wk0[598140]; + union + { + unsigned long LONG; + struct + { + unsigned long DMREQ0:1; + unsigned long DMREQ1:1; + unsigned long :30; + } BIT; + } DMASTG; +}; + +struct st_doc +{ + union + { + unsigned char BYTE; + struct + { + unsigned char OMS:2; + unsigned char DCSEL:1; + unsigned char :1; + unsigned char DOPCIE:1; + unsigned char DOPCF:1; + unsigned char DOPCFCL:1; + unsigned char :1; + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +}; + +struct st_dsmif +{ + union + { + unsigned long LONG; + struct + { + unsigned long ENABLE:1; + unsigned long :7; + unsigned long SINC1SEL:2; + unsigned long :2; + unsigned long WORD1GEN:3; + unsigned long :1; + unsigned long BITSHIFT1:4; + unsigned long SINC2SEL:2; + unsigned long :2; + unsigned long WORD2GEN:3; + unsigned long :1; + unsigned long BITSHIFT2:4; + } BIT; + } UVWCTL; + union + { + unsigned long LONG; + struct + { + unsigned long ERUI:1; + unsigned long ERVI:1; + unsigned long ERWI:1; + unsigned long :1; + unsigned long ERUSC:1; + unsigned long ERVSC:1; + unsigned long ERWSC:1; + unsigned long :1; + unsigned long ERUVWIGND:1; + unsigned long :23; + } BIT; + } UVWSTA; + union + { + unsigned long LONG; + struct + { + unsigned long CMPUVWIUNDER:16; + unsigned long :16; + } BIT; + } UVWIUNCMP; + union + { + unsigned long LONG; + struct + { + unsigned long CMPUVWIOVER:16; + unsigned long :16; + } BIT; + } UVWIOVCMP; + union + { + unsigned long LONG; + struct + { + unsigned long CMPUVWSCUNDER:13; + unsigned long :19; + } BIT; + } UVWSCUNCMP; + union + { + unsigned long LONG; + struct + { + unsigned long CMPUVWSCOVER:13; + unsigned long :19; + } BIT; + } UVWSCOVCMP; + union + { + unsigned long LONG; + struct + { + unsigned long CMPUVWIGNDUNDER:18; + unsigned long :14; + } BIT; + } UVWIGUNCMP; + union + { + unsigned long LONG; + struct + { + unsigned long CMPUVWIGNDOVER:18; + unsigned long :14; + } BIT; + } UVWIGOVCMP; + union + { + unsigned long LONG; + struct + { + unsigned long U1DATA:16; + unsigned long :16; + } BIT; + } U1DATA; + union + { + unsigned long LONG; + struct + { + unsigned long U1CDATA:16; + unsigned long :16; + } BIT; + } U1CDATA; + union + { + unsigned long LONG; + struct + { + unsigned long U1VDATA:16; + unsigned long :16; + } BIT; + } U1VDATA; + union + { + unsigned long LONG; + struct + { + unsigned long U2DATA:16; + unsigned long :16; + } BIT; + } U2DATA; + union + { + unsigned long LONG; + struct + { + unsigned long V1DATA:16; + unsigned long :16; + } BIT; + } V1DATA; + union + { + unsigned long LONG; + struct + { + unsigned long V1CDATA:16; + unsigned long :16; + } BIT; + } V1CDATA; + union + { + unsigned long LONG; + struct + { + unsigned long V1VDATA:16; + unsigned long :16; + } BIT; + } V1VDATA; + union + { + unsigned long LONG; + struct + { + unsigned long V2DATA:16; + unsigned long :16; + } BIT; + } V2DATA; + union + { + unsigned long LONG; + struct + { + unsigned long W1DATA:16; + unsigned long :16; + } BIT; + } W1DATA; + union + { + unsigned long LONG; + struct + { + unsigned long W1CDATA:16; + unsigned long :16; + } BIT; + } W1CDATA; + union + { + unsigned long LONG; + struct + { + unsigned long W1VDATA:16; + unsigned long :16; + } BIT; + } W1VDATA; + union + { + unsigned long LONG; + struct + { + unsigned long W2DATA:16; + unsigned long :16; + } BIT; + } W2DATA; + char wk0[48]; + union + { + unsigned long LONG; + struct + { + unsigned long ENABLE:1; + unsigned long :7; + unsigned long SINC1SEL:2; + unsigned long :2; + unsigned long WORD1GEN:3; + unsigned long :1; + unsigned long BITSHIFT1:4; + unsigned long SINC2SEL:2; + unsigned long :2; + unsigned long WORD2GEN:3; + unsigned long :1; + unsigned long BITSHIFT2:4; + } BIT; + } XYZCTL; + union + { + unsigned long LONG; + struct + { + unsigned long ERXI:1; + unsigned long :3; + unsigned long ERXSC:1; + unsigned long :27; + } BIT; + } XYZSTA; + union + { + unsigned long LONG; + struct + { + unsigned long CMPXIUNDER:16; + unsigned long :16; + } BIT; + } XYZIUNCMP; + union + { + unsigned long LONG; + struct + { + unsigned long CMPXIOVER:16; + unsigned long :16; + } BIT; + } XYZIOVCMP; + union + { + unsigned long LONG; + struct + { + unsigned long CMPXSCUNDER:13; + unsigned long :19; + } BIT; + } XYZSCUNCMP; + union + { + unsigned long LONG; + struct + { + unsigned long CMPXSCOVER:13; + unsigned long :19; + } BIT; + } XYZSCOVCMP; + char wk1[8]; + union + { + unsigned long LONG; + struct + { + unsigned long X1DATA:16; + unsigned long :16; + } BIT; + } X1DATA; + union + { + unsigned long LONG; + struct + { + unsigned long X1CDATA:16; + unsigned long :16; + } BIT; + } X1CDATA; + union + { + unsigned long LONG; + struct + { + unsigned long X1VDATA:16; + unsigned long :16; + } BIT; + } X1VDATA; + char wk2[16]; + union + { + unsigned long LONG; + struct + { + unsigned long X2DATA:16; + unsigned long :16; + } BIT; + } X2DATA; +}; + +struct st_ecatc +{ + union + { + unsigned long LONG; + struct + { + unsigned long OADD0:1; + unsigned long OADD1:1; + unsigned long OADD2:1; + unsigned long OADD3:1; + unsigned long OADD4:1; + unsigned long :27; + } BIT; + } CATOFFADD; + union + { + unsigned long LONG; + struct + { + unsigned long I2CSIZE:1; + unsigned long :31; + } BIT; + } CATEMMD; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TXSFT00:1; + unsigned long TXSFT01:1; + unsigned long TXSFT10:1; + unsigned long TXSFT11:1; + unsigned long :28; + } BIT; + } CATTXCSFT; + char wk1[69360]; + union + { + unsigned char BYTE; + struct + { + unsigned char TYPE:8; + } BIT; + } TYPE; + union + { + unsigned char BYTE; + struct + { + unsigned char REV:8; + } BIT; + } REVISION; + union + { + unsigned short WORD; + struct + { + unsigned short BUILD:16; + } BIT; + } BUILD; + union + { + unsigned char BYTE; + struct + { + unsigned char NUMFMMU:8; + } BIT; + } FMMU_NUM; + union + { + unsigned char BYTE; + struct + { + unsigned char NUMSYNC:8; + } BIT; + } SYNC_MANAGER; + union + { + unsigned char BYTE; + struct + { + unsigned char RAMSIZE:8; + } BIT; + } RAM_SIZE; + union + { + unsigned char BYTE; + struct + { + unsigned char P0:2; + unsigned char P1:2; + unsigned char P2:2; + unsigned char P3:2; + } BIT; + } PORT_DESC; + union + { + unsigned short WORD; + struct + { + unsigned short FMMU:1; + unsigned short :1; + unsigned short DC:1; + unsigned short DCWID:1; + unsigned short :2; + unsigned short LINKDECMII:1; + unsigned short FCS:1; + unsigned short DCSYNC:1; + unsigned short LRW:1; + unsigned short RWSUPP:1; + unsigned short FSCONFIG:1; + unsigned short :4; + } BIT; + } FEATURE; + char wk2[6]; + union + { + unsigned short WORD; + struct + { + unsigned short NODADDR:16; + } BIT; + } STATION_ADR; + union + { + unsigned short WORD; + struct + { + unsigned short NODALIADDR:16; + } BIT; + } STATION_ALIAS; + char wk3[12]; + union + { + unsigned char BYTE; + struct + { + unsigned char ENABLE:1; + unsigned char :7; + } BIT; + } WR_REG_ENABLE; + union + { + unsigned char BYTE; + struct + { + unsigned char PROTECT:1; + unsigned char :7; + } BIT; + } WR_REG_PROTECT; + char wk4[14]; + union + { + unsigned char BYTE; + struct + { + unsigned char ENABLE:1; + unsigned char :7; + } BIT; + } ESC_WR_ENABLE; + union + { + unsigned char BYTE; + struct + { + unsigned char PROTECT:1; + unsigned char :7; + } BIT; + } ESC_WR_PROTECT; + char wk5[14]; + union + { + union + { + unsigned char BYTE; + } ESC_RESET_ECAT_W; + union + { + unsigned char BYTE; + } ESC_RESET_ECAT_R; + } RESET_ECAT; + union + { + union + { + unsigned char BYTE; + } ESC_RESET_PDI_W; + union + { + unsigned char BYTE; + } ESC_RESET_PDI_R; + } RESET_PDI; + char wk6[190]; + union + { + unsigned long LONG; + struct + { + unsigned long FWDRULE:1; + unsigned long TEMPUSE:1; + unsigned long :6; + unsigned long LP0:2; + unsigned long LP1:2; + unsigned long LP2:2; + unsigned long LP3:2; + unsigned long RXFIFO:3; + unsigned long :5; + unsigned long STAALIAS:1; + unsigned long :7; + } BIT; + } ESC_DL_CONTROL; + char wk7[4]; + union + { + unsigned short WORD; + struct + { + unsigned short RWOFFSET:16; + } BIT; + } PHYSICAL_RW_OFFSET; + char wk8[6]; + union + { + unsigned short WORD; + struct + { + unsigned short PDIOPE:1; + unsigned short PDIWDST:1; + unsigned short ENHLINKD:1; + unsigned short :1; + unsigned short PHYP0:1; + unsigned short PHYP1:1; + unsigned short PHYP2:1; + unsigned short PHYP3:1; + unsigned short LP0:1; + unsigned short COMP0:1; + unsigned short LP1:1; + unsigned short COMP1:1; + unsigned short LP2:1; + unsigned short COMP2:1; + unsigned short LP3:1; + unsigned short COMP3:1; + } BIT; + } ESC_DL_STATUS; + char wk9[14]; + union + { + unsigned short WORD; + struct + { + unsigned short INISTATE:4; + unsigned short ERRINDACK:1; + unsigned short :11; + } BIT; + } AL_CONTROL; + char wk10[14]; + union + { + unsigned short WORD; + struct + { + unsigned short ACTSTATE:4; + unsigned short ERR:1; + unsigned short :11; + } BIT; + } AL_STATUS; + char wk11[2]; + union + { + unsigned short WORD; + struct + { + unsigned short STATUSCODE:16; + } BIT; + } AL_STATUS_CODE; + char wk12[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char LEDCODE:4; + unsigned char OVERRIDEEN:1; + unsigned char :3; + } BIT; + } RUN_LED_OVERRIDE; + union + { + unsigned char BYTE; + struct + { + unsigned char LEDCODE:4; + unsigned char OVERRIDEEN:1; + unsigned char :3; + } BIT; + } ERR_LED_OVERRIDE; + char wk13[6]; + union + { + unsigned char BYTE; + struct + { + unsigned char PDI:8; + } BIT; + } PDI_CONTROL; + union + { + unsigned char BYTE; + struct + { + unsigned char DEVEMU:1; + unsigned char ENLALLP:1; + unsigned char DCSYNC:1; + unsigned char DCLATCH:1; + unsigned char ENLP0:1; + unsigned char ENLP1:1; + unsigned char ENLP2:1; + unsigned char ENLP3:1; + } BIT; + } ESC_CONFIG; + char wk14[14]; + union + { + unsigned char BYTE; + struct + { + unsigned char ONCHIPBUSCLK:5; + unsigned char ONCHIPBUS:3; + } BIT; + } PDI_CONFIG; + union + { + unsigned char BYTE; + struct + { + unsigned char SYNC0OUT:2; + unsigned char SYNCLAT0:1; + unsigned char SYNC0MAP:1; + unsigned char :1; + unsigned char SYNC1OUT:1; + unsigned char SYNCLAT1:1; + unsigned char SYNC1MAP:1; + } BIT; + } SYNC_LATCH_CONFIG; + union + { + unsigned short WORD; + struct + { + unsigned short DATABUSWID:1; + unsigned short :15; + } BIT; + } EXT_PDI_CONFIG; + char wk15[172]; + union + { + unsigned short WORD; + struct + { + unsigned short ECATEVMASK:16; + } BIT; + } ECAT_EVENT_MASK; + char wk16[2]; + union + { + unsigned long LONG; + struct + { + unsigned long ALEVMASK:32; + } BIT; + } AL_EVENT_MASK; + char wk17[8]; + union + { + unsigned short WORD; + struct + { + unsigned short DCLATCH:1; + unsigned short :1; + unsigned short DLSTA:1; + unsigned short ALSTA:1; + unsigned short SMSTA0:1; + unsigned short SMSTA1:1; + unsigned short SMSTA2:1; + unsigned short SMSTA3:1; + unsigned short SMSTA4:1; + unsigned short SMSTA5:1; + unsigned short SMSTA6:1; + unsigned short SMSTA7:1; + unsigned short :4; + } BIT; + } ECAT_EVENT_REQ; + char wk18[14]; + union + { + unsigned long LONG; + struct + { + unsigned long ALCTRL:1; + unsigned long DCLATCH:1; + unsigned long DCSYNC0STA:1; + unsigned long DCSYNC1STA:1; + unsigned long SYNCACT:1; + unsigned long :1; + unsigned long WDPD:1; + unsigned long :1; + unsigned long SMINT0:1; + unsigned long SMINT1:1; + unsigned long SMINT2:1; + unsigned long SMINT3:1; + unsigned long SMINT4:1; + unsigned long SMINT5:1; + unsigned long SMINT6:1; + unsigned long SMINT7:1; + unsigned long :16; + } BIT; + } AL_EVENT_REQ; + char wk19[220]; + union + { + unsigned short WORD; + struct + { + unsigned short RXERRCNT:16; + } BIT; + } RX_ERR_COUNT0; + union + { + unsigned short WORD; + struct + { + unsigned short RXERRCNT:16; + } BIT; + } RX_ERR_COUNT1; + char wk20[4]; + union + { + unsigned char BYTE; + struct + { + unsigned char FWDERRCNT:8; + } BIT; + } FWD_RX_ERR_COUNT0; + union + { + unsigned char BYTE; + struct + { + unsigned char FWDERRCNT:8; + } BIT; + } FWD_RX_ERR_COUNT1; + char wk21[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char EPUERRCNT:8; + } BIT; + } ECAT_PROC_ERR_COUNT; + union + { + unsigned char BYTE; + struct + { + unsigned char PDIERRCNT:8; + } BIT; + } PDI_ERR_COUNT; + char wk22[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char LOSTLINKCNT:8; + } BIT; + } LOST_LINK_COUNT0; + union + { + unsigned char BYTE; + struct + { + unsigned char LOSTLINKCNT:8; + } BIT; + } LOST_LINK_COUNT1; + char wk23[238]; + union + { + unsigned short WORD; + struct + { + unsigned short WDDIV:16; + } BIT; + } WD_DIVIDE; + char wk24[14]; + union + { + unsigned short WORD; + struct + { + unsigned short WDTIMPDI:16; + } BIT; + } WDT_PDI; + char wk25[14]; + union + { + unsigned short WORD; + struct + { + unsigned short WDTIMPD:16; + } BIT; + } WDT_DATA; + char wk26[30]; + union + { + unsigned short WORD; + struct + { + unsigned short WDSTAPD:1; + unsigned short :15; + } BIT; + } WDS_DATA; + union + { + unsigned char BYTE; + struct + { + unsigned char WDCNTPD:8; + } BIT; + } WDC_DATA; + union + { + unsigned char BYTE; + struct + { + unsigned char WDCNTPDI:8; + } BIT; + } WDC_PDI; + char wk27[188]; + union + { + unsigned char BYTE; + struct + { + unsigned char CTRLPDI:1; + unsigned char FORCEECAT:1; + unsigned char :6; + } BIT; + } EEP_CONF; + union + { + unsigned char BYTE; + struct + { + unsigned char PDIACCESS:1; + unsigned char :7; + } BIT; + } EEP_STATE; + union + { + unsigned short WORD; + struct + { + unsigned short ECATWREN:1; + unsigned short :5; + unsigned short READBYTE:1; + unsigned short PROMSIZE:1; + unsigned short COMMAND:3; + unsigned short CKSUMERR:1; + unsigned short LOADSTA:1; + unsigned short ACKCMDERR:1; + unsigned short WRENERR:1; + unsigned short BUSY:1; + } BIT; + } EEP_CONT_STAT; + union + { + unsigned long LONG; + struct + { + unsigned long ADDRESS:32; + } BIT; + } EEP_ADR; + union + { + unsigned long LONG; + struct + { + unsigned long LODATA:16; + unsigned long HIDATA:16; + } BIT; + } EEP_DATA; + char wk28[4]; + union + { + unsigned short WORD; + struct + { + unsigned short WREN:1; + unsigned short PDICTRL:1; + unsigned short MILINK:1; + unsigned short PHYOFFSET:5; + unsigned short COMMAND:2; + unsigned short :3; + unsigned short READERR:1; + unsigned short CMDERR:1; + unsigned short BUSY:1; + } BIT; + } MII_CONT_STAT; + union + { + unsigned char BYTE; + struct + { + unsigned char PHYADDR:5; + unsigned char :3; + } BIT; + } PHY_ADR; + union + { + unsigned char BYTE; + struct + { + unsigned char PHYREGADDR:5; + unsigned char :3; + } BIT; + } PHY_REG_ADR; + union + { + unsigned short WORD; + struct + { + unsigned short PHYREGDATA:16; + } BIT; + } PHY_DATA; + union + { + unsigned char BYTE; + struct + { + unsigned char ACSMII:1; + unsigned char :7; + } BIT; + } MII_ECAT_ACS_STAT; + union + { + unsigned char BYTE; + struct + { + unsigned char ACSMII:1; + unsigned char FORPDI:1; + unsigned char :6; + } BIT; + } MII_PDI_ACS_STAT; + union + { + unsigned char BYTE; + struct + { + unsigned char PHYLINKSTA:1; + unsigned char LINKSTA:1; + unsigned char LINKSTAERR:1; + unsigned char READERR:1; + unsigned char LINKPARTERR:1; + unsigned char PHYCONFIG:1; + unsigned char :2; + } BIT; + } PHY_STATUS0; + union + { + unsigned char BYTE; + struct + { + unsigned char PHYLINKSTA:1; + unsigned char LINKSTA:1; + unsigned char LINKSTAERR:1; + unsigned char READERR:1; + unsigned char LINKPARTERR:1; + unsigned char PHYCONFIG:1; + unsigned char :2; + } BIT; + } PHY_STATUS1; + char wk29[230]; + struct + { + union + { + unsigned long LONG; + struct + { + unsigned long LSTAADR:32; + } BIT; + } L_START_ADR; + union + { + unsigned short WORD; + struct + { + unsigned short FMMULEN:16; + } BIT; + } LEN; + union + { + unsigned char BYTE; + struct + { + unsigned char LSTABIT:3; + unsigned char :5; + } BIT; + } L_START_BIT; + union + { + unsigned char BYTE; + struct + { + unsigned char LSTABIT:3; + unsigned char :5; + } BIT; + } L_STOP_BIT; + union + { + unsigned short WORD; + struct + { + unsigned short PHYSTAADR:16; + } BIT; + } P_START_ADR; + union + { + unsigned char BYTE; + struct + { + unsigned char PHYSTABIT:3; + unsigned char :5; + } BIT; + } P_START_BIT; + union + { + unsigned char BYTE; + struct + { + unsigned char READ:1; + unsigned char WRITE:1; + unsigned char :6; + } BIT; + } TYPE; + union + { + unsigned char BYTE; + struct + { + unsigned char ACTIVATE:1; + unsigned char :7; + } BIT; + } ACT; + char fmmu_wk[3]; + } FMMU[8]; + char wk37[0x180]; + struct + { + union + { + unsigned short WORD; + struct + { + unsigned short SMSTAADDR:16; + } BIT; + } P_START_ADR; + union + { + unsigned short WORD; + struct + { + unsigned short SMLEN:16; + } BIT; + } LEN; + union + { + unsigned char BYTE; + struct + { + unsigned char OPEMODE:2; + unsigned char DIR:2; + unsigned char IRQECAT:1; + unsigned char IRQPDI:1; + unsigned char WDTRGEN:1; + unsigned char :1; + } BIT; + } CONTROL; + union + { + unsigned char BYTE; + struct + { + unsigned char INTWR:1; + unsigned char INTRD:1; + unsigned char :1; + unsigned char MAILBOX:1; + unsigned char BUFFERED:2; + unsigned char RDBUF:1; + unsigned char WRBUF:1; + } BIT; + } STATUS; + union + { + unsigned char BYTE; + struct + { + unsigned char SMEN:1; + unsigned char REPEATREQ:1; + unsigned char :4; + unsigned char LATCHECAT:1; + unsigned char LATCHPDI:1; + } BIT; + } ACT; + union + { + unsigned char BYTE; + struct + { + unsigned char DEACTIVE:1; + unsigned char REPEATACK:1; + unsigned char :6; + } BIT; + } PDI_CONT; + } SM[8]; + char wk38[192]; + union + { + unsigned long LONG; + struct + { + unsigned long RCVTIME0:32; + } BIT; + } DC_RCV_TIME_PORT0; + union + { + unsigned long LONG; + struct + { + unsigned long RCVTIME1:32; + } BIT; + } DC_RCV_TIME_PORT1; + char wk39[8]; + union + { + unsigned long long LONGLONG; + } DC_SYS_TIME; + union + { + unsigned long long LONGLONG; + } DC_RCV_TIME_UNIT; + union + { + unsigned long long LONGLONG; + } DC_SYS_TIME_OFFSET; + union + { + unsigned long LONG; + struct + { + unsigned long SYSTIMDLY:32; + } BIT; + } DC_SYS_TIME_DELAY; + union + { + unsigned long LONG; + struct + { + unsigned long LOCALCOPY:1; + unsigned long DIFF:31; + } BIT; + } DC_SYS_TIME_DIFF; + union + { + unsigned short WORD; + struct + { + unsigned short :1; + unsigned short SPDCNTSTRT:15; + } BIT; + } DC_SPEED_COUNT_START; + union + { + unsigned short WORD; + struct + { + unsigned short SPDCNTDIFF:16; + } BIT; + } DC_SPEED_COUNT_DIFF; + union + { + unsigned char BYTE; + struct + { + unsigned char :4; + unsigned char SYSTIMDEP:4; + } BIT; + } DC_SYS_TIME_DIFF_FIL_DEPTH; + union + { + unsigned char BYTE; + struct + { + unsigned char :4; + unsigned char CLKPERDEP:4; + } BIT; + } DC_SPEED_COUNT_FIL_DEPTH; + char wk40[74]; + union + { + unsigned char BYTE; + struct + { + unsigned char :2; + unsigned char LATCH1:1; + unsigned char LATCH0:1; + unsigned char :3; + unsigned char SYNCOUT:1; + } BIT; + } DC_CYC_CONT; + union + { + unsigned char BYTE; + struct + { + unsigned char DBGPULSE:1; + unsigned char NEARFUTURE:1; + unsigned char STARTTIME:1; + unsigned char EXTSTARTTIME:1; + unsigned char AUTOACT:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + unsigned char SYNCACT:1; + } BIT; + } DC_ACT; + union + { + unsigned short WORD; + struct + { + unsigned short PULSELEN:16; + } BIT; + } DC_PULSE_LEN; + union + { + unsigned char BYTE; + struct + { + unsigned char :5; + unsigned char STARTTIME:1; + unsigned char SYNC1ACT:1; + unsigned char SYNC0ACT:1; + } BIT; + } DC_ACT_STAT; + char wk41[9]; + union + { + unsigned char BYTE; + struct + { + unsigned char :7; + unsigned char SYNC0STA:1; + } BIT; + } DC_SYNC0_STAT; + union + { + unsigned char BYTE; + struct + { + unsigned char :7; + unsigned char SYNC1STA:1; + } BIT; + } DC_SYNC1_STAT; + union + { + unsigned long long LONGLONG; + } DC_CYC_START_TIME; + union + { + unsigned long long LONGLONG; + } DC_NEXT_SYNC1_PULSE; + union + { + unsigned long LONG; + struct + { + unsigned long SYNC0CYC:32; + } BIT; + } DC_SYNC0_CYC_TIME; + union + { + unsigned long LONG; + struct + { + unsigned long SYNC1CYC:32; + } BIT; + } DC_SYNC1_CYC_TIME; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char NEGEDGE:1; + unsigned char POSEDGE:1; + } BIT; + } DC_LATCH0_CONT; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char NEGEDGE:1; + unsigned char POSEDGE:1; + } BIT; + } DC_LATCH1_CONT; + char wk42[4]; + union + { + unsigned char BYTE; + struct + { + unsigned char :5; + unsigned char PINSTATE:1; + unsigned char EVENTNEG:1; + unsigned char EVENTPOS:1; + } BIT; + } DC_LATCH0_STAT; + union + { + unsigned char BYTE; + struct + { + unsigned char :5; + unsigned char PINSTATE:1; + unsigned char EVENTNEG:1; + unsigned char EVENTPOS:1; + } BIT; + } DC_LATCH1_STAT; + union + { + unsigned long long LONGLONG; + } DC_LATCH0_TIME_POS; + union + { + unsigned long long LONGLONG; + } DC_LATCH0_TIME_NEG; + union + { + unsigned long long LONGLONG; + } DC_LATCH1_TIME_POS; + union + { + unsigned long long LONGLONG; + } DC_LATCH1_TIME_NEG; + char wk43[32]; + union + { + unsigned long LONG; + struct + { + unsigned long ECATCHANGE:32; + } BIT; + } DC_ECAT_CNG_EV_TIME; + char wk44[4]; + union + { + unsigned long LONG; + struct + { + unsigned long PDISTART:32; + } BIT; + } DC_PDI_START_EV_TIME; + union + { + unsigned long LONG; + struct + { + unsigned long PDICHANGE:32; + } BIT; + } DC_PDI_CNG_EV_TIME; + char wk45[1024]; + union + { + unsigned long long LONGLONG; + } PRODUCT_ID; + union + { + unsigned long long LONGLONG; + } VENDOR_ID; +}; + +struct st_eccram +{ + union + { + unsigned long LONG; + } RAMPCMD; + char wk0[252]; + union + { + unsigned long LONG; + struct + { + unsigned long :31; + unsigned long ECC_ENABLE:1; + } BIT; + } RAMEDC; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long DBE_DIST15:1; + unsigned long DBE_DIST14:1; + unsigned long DBE_DIST13:1; + unsigned long DBE_DIST12:1; + unsigned long DBE_DIST11:1; + unsigned long DBE_DIST10:1; + unsigned long DBE_DIST9:1; + unsigned long DBE_DIST8:1; + unsigned long DBE_DIST7:1; + unsigned long DBE_DIST6:1; + unsigned long DBE_DIST5:1; + unsigned long DBE_DIST4:1; + unsigned long DBE_DIST3:1; + unsigned long DBE_DIST2:1; + unsigned long DBE_DIST1:1; + unsigned long DBE_DIST0:1; + } BIT; + } RAMEEC; + union + { + unsigned long LONG; + struct + { + unsigned long :16; + unsigned long DBE_RAM15:1; + unsigned long DBE_RAM14:1; + unsigned long DBE_RAM13:1; + unsigned long DBE_RAM12:1; + unsigned long DBE_RAM11:1; + unsigned long DBE_RAM10:1; + unsigned long DBE_RAM9:1; + unsigned long DBE_RAM8:1; + unsigned long DBE_RAM7:1; + unsigned long DBE_RAM6:1; + unsigned long DBE_RAM5:1; + unsigned long DBE_RAM4:1; + unsigned long DBE_RAM3:1; + unsigned long DBE_RAM2:1; + unsigned long DBE_RAM1:1; + unsigned long DBE_RAM0:1; + } BIT; + } RAMDBEST; + union + { + unsigned long LONG; + struct + { + unsigned long :12; + unsigned long BANK:2; + unsigned long ADDRESS:16; + unsigned long :1; + unsigned long LOCK:1; + } BIT; + } RAMDBEAD; + union + { + unsigned long LONG; + struct + { + unsigned long :28; + unsigned long ERRCOUNT:4; + } BIT; + } RAMDBECNT; +}; + +struct st_ecm +{ + union + { + unsigned char BYTE; + } ECMEPCFG; + char wk0[3]; + union + { + unsigned long LONG; + } ECMMICFG0; + union + { + unsigned long LONG; + } ECMMICFG1; + union + { + unsigned long LONG; + } ECMMICFG2; + union + { + unsigned long LONG; + } ECMNMICFG0; + union + { + unsigned long LONG; + } ECMNMICFG1; + union + { + unsigned long LONG; + } ECMNMICFG2; + union + { + unsigned long LONG; + } ECMIRCFG0; + union + { + unsigned long LONG; + } ECMIRCFG1; + union + { + unsigned long LONG; + } ECMIRCFG2; + union + { + unsigned long LONG; + } ECMEMK0; + union + { + unsigned long LONG; + } ECMEMK1; + union + { + unsigned long LONG; + } ECMEMK2; + union + { + unsigned long LONG; + } ECMESSTC0; + union + { + unsigned long LONG; + } ECMESSTC1; + union + { + unsigned long LONG; + } ECMESSTC2; + union + { + unsigned long LONG; + } ECMPCMD1; + union + { + unsigned char BYTE; + struct + { + unsigned char ECMPRERR:1; + unsigned char :7; + } BIT; + } ECMPS; + char wk1[3]; + union + { + unsigned long LONG; + } ECMPE0; + union + { + unsigned long LONG; + } ECMPE1; + union + { + unsigned long LONG; + } ECMPE2; + union + { + unsigned char BYTE; + } ECMDTMCTL; + char wk2[3]; + union + { + unsigned short WORD; + struct + { + unsigned short ECMTDMR:16; + } BIT; + } ECMDTMR; + char wk3[2]; + union + { + unsigned long LONG; + } ECMDTMCMP; + union + { + unsigned long LONG; + } ECMDTMCFG0; + union + { + unsigned long LONG; + } ECMDTMCFG1; + union + { + unsigned long LONG; + } ECMDTMCFG2; + union + { + unsigned long LONG; + } ECMDTMCFG3; + union + { + unsigned long LONG; + } ECMDTMCFG4; + union + { + unsigned long LONG; + } ECMDTMCFG5; + union + { + unsigned long LONG; + } ECMEOCCFG; +}; + +struct st_ecmc +{ + union + { + unsigned char BYTE; + } ECMCESET; + char wk0[3]; + union + { + unsigned char BYTE; + } ECMCECLR; + char wk1[3]; + union + { + unsigned long LONG; + struct + { + unsigned long ECMCSSE000:1; + unsigned long ECMCSSE001:1; + unsigned long ECMCSSE002:1; + unsigned long :1; + unsigned long ECMCSSE004:1; + unsigned long ECMCSSE005:1; + unsigned long ECMCSSE006:1; + unsigned long ECMCSSE007:1; + unsigned long ECMCSSE008:1; + unsigned long ECMCSSE009:1; + unsigned long ECMCSSE010:1; + unsigned long ECMCSSE011:1; + unsigned long ECMCSSE012:1; + unsigned long ECMCSSE013:1; + unsigned long ECMCSSE014:1; + unsigned long ECMCSSE015:1; + unsigned long ECMCSSE016:1; + unsigned long ECMCSSE017:1; + unsigned long ECMCSSE018:1; + unsigned long ECMCSSE019:1; + unsigned long ECMCSSE020:1; + unsigned long ECMCSSE021:1; + unsigned long ECMCSSE022:1; + unsigned long ECMCSSE023:1; + unsigned long ECMCSSE024:1; + unsigned long ECMCSSE025:1; + unsigned long ECMCSSE026:1; + unsigned long ECMCSSE027:1; + unsigned long ECMCSSE028:1; + unsigned long :1; + unsigned long ECMCSSE030:1; + unsigned long ECMCSSE031:1; + } BIT; + } ECMCESSTR0; + union + { + unsigned long LONG; + struct + { + unsigned long ECMCSSE100:1; + unsigned long ECMCSSE101:1; + unsigned long ECMCSSE202:1; + unsigned long :1; + unsigned long ECMCSSE104:1; + unsigned long ECMCSSE105:1; + unsigned long ECMCSSE106:1; + unsigned long ECMCSSE107:1; + unsigned long ECMCSSE108:1; + unsigned long :23; + } BIT; + } ECMCESSTR1; + union + { + unsigned long LONG; + struct + { + unsigned long :28; + unsigned long ECMCSSE228:1; + unsigned long ECMCSSE229:1; + unsigned long ECMCSSE230:1; + unsigned long ECMCSSE231:1; + } BIT; + } ECMCESSTR2; + union + { + unsigned long LONG; + struct + { + unsigned long ECMC0REG:8; + unsigned long :24; + } BIT; + } ECMCPCMD0; +}; + +struct st_ecmm +{ + union + { + unsigned char BYTE; + } ECMMESET; + char wk0[3]; + union + { + unsigned char BYTE; + } ECMMECLR; + char wk1[3]; + union + { + unsigned long LONG; + struct + { + unsigned long ECMMSSE000:1; + unsigned long ECMMSSE001:1; + unsigned long ECMMSSE002:1; + unsigned long :1; + unsigned long ECMMSSE004:1; + unsigned long ECMMSSE005:1; + unsigned long ECMMSSE006:1; + unsigned long ECMMSSE007:1; + unsigned long ECMMSSE008:1; + unsigned long ECMMSSE009:1; + unsigned long ECMMSSE010:1; + unsigned long ECMMSSE011:1; + unsigned long ECMMSSE012:1; + unsigned long ECMMSSE013:1; + unsigned long ECMMSSE014:1; + unsigned long ECMMSSE015:1; + unsigned long ECMMSSE016:1; + unsigned long ECMMSSE017:1; + unsigned long ECMMSSE018:1; + unsigned long ECMMSSE019:1; + unsigned long ECMMSSE020:1; + unsigned long ECMMSSE021:1; + unsigned long ECMMSSE022:1; + unsigned long ECMMSSE023:1; + unsigned long ECMMSSE024:1; + unsigned long ECMMSSE025:1; + unsigned long ECMMSSE026:1; + unsigned long ECMMSSE027:1; + unsigned long ECMMSSE028:1; + unsigned long :1; + unsigned long ECMMSSE030:1; + unsigned long ECMMSSE031:1; + } BIT; + } ECMMESSTR0; + union + { + unsigned long LONG; + struct + { + unsigned long ECMMSSE100:1; + unsigned long ECMMSSE101:1; + unsigned long ECMMSSE102:1; + unsigned long :1; + unsigned long ECMMSSE104:1; + unsigned long ECMMSSE105:1; + unsigned long ECMMSSE106:1; + unsigned long ECMMSSE107:1; + unsigned long ECMMSSE108:1; + unsigned long :23; + } BIT; + } ECMMESSTR1; + union + { + unsigned long LONG; + struct + { + unsigned long :28; + unsigned long ECMMSSE228:1; + unsigned long ECMMSSE229:1; + unsigned long ECMMSSE230:1; + unsigned long ECMMSSE231:1; + } BIT; + } ECMMESSTR2; + union + { + unsigned long LONG; + struct + { + unsigned long ECMM0REG:8; + unsigned long :24; + } BIT; + } ECMMPCMD0; +}; + +struct st_elc +{ + union + { + unsigned char BYTE; + struct + { + unsigned char :7; + unsigned char ELCON:1; + } BIT; + } ELCR; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR0; + char wk0[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR3; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR4; + char wk1[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR7; + char wk2[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR10; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR11; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR12; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR13; + char wk3[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR15; + char wk4[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR18; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR19; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR20; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR21; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR22; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR23; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR24; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR25; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR26; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR27; + char wk5[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char MTU0MD:2; + unsigned char :4; + unsigned char MTU3MD:2; + } BIT; + } ELOPA; + union + { + unsigned char BYTE; + struct + { + unsigned char MTU4MD:2; + unsigned char :6; + } BIT; + } ELOPB; + union + { + unsigned char BYTE; + struct + { + unsigned char :2; + unsigned char CMT1MD:2; + unsigned char :4; + } BIT; + } ELOPC; + union + { + unsigned char BYTE; + struct + { + unsigned char DSU0MD:2; + unsigned char DSU1MD:2; + unsigned char DSX0MD:2; + unsigned char DSX1MD:2; + } BIT; + } ELOPD; + union + { + unsigned char BYTE; + struct + { + unsigned char PGRn0:1; + unsigned char PGRn1:1; + unsigned char PGRn2:1; + unsigned char PGRn3:1; + unsigned char PGRn4:1; + unsigned char PGRn5:1; + unsigned char PGRn6:1; + unsigned char PGRn7:1; + } BIT; + } PGR1; + union + { + unsigned char BYTE; + struct + { + unsigned char PGRn0:1; + unsigned char PGRn1:1; + unsigned char PGRn2:1; + unsigned char PGRn3:1; + unsigned char PGRn4:1; + unsigned char PGRn5:1; + unsigned char PGRn6:1; + unsigned char PGRn7:1; + } BIT; + } PGR2; + union + { + unsigned char BYTE; + struct + { + unsigned char PGCIn:2; + unsigned char PGCOVEn:1; + unsigned char :1; + unsigned char PGCOn:3; + unsigned char :1; + } BIT; + } PGC1; + union + { + unsigned char BYTE; + struct + { + unsigned char PGCIn:2; + unsigned char PGCOVEn:1; + unsigned char :1; + unsigned char PGCOn:3; + unsigned char :1; + } BIT; + } PGC2; + union + { + unsigned char BYTE; + struct + { + unsigned char PDBFn0:1; + unsigned char PDBFn1:1; + unsigned char PDBFn2:1; + unsigned char PDBFn3:1; + unsigned char PDBFn4:1; + unsigned char PDBFn5:1; + unsigned char PDBFn6:1; + unsigned char PDBFn7:1; + } BIT; + } PDBF1; + union + { + unsigned char BYTE; + struct + { + unsigned char PDBFn0:1; + unsigned char PDBFn1:1; + unsigned char PDBFn2:1; + unsigned char PDBFn3:1; + unsigned char PDBFn4:1; + unsigned char PDBFn5:1; + unsigned char PDBFn6:1; + unsigned char PDBFn7:1; + } BIT; + } PDBF2; + union + { + unsigned char BYTE; + struct + { + unsigned char PSBn:3; + unsigned char PSPn:2; + unsigned char PSMn:2; + unsigned char :1; + } BIT; + } PEL0; + union + { + unsigned char BYTE; + struct + { + unsigned char PSBn:3; + unsigned char PSPn:2; + unsigned char PSMn:2; + unsigned char :1; + } BIT; + } PEL1; + union + { + unsigned char BYTE; + struct + { + unsigned char PSBn:3; + unsigned char PSPn:2; + unsigned char PSMn:2; + unsigned char :1; + } BIT; + } PEL2; + union + { + unsigned char BYTE; + struct + { + unsigned char PSBn:3; + unsigned char PSPn:2; + unsigned char PSMn:2; + unsigned char :1; + } BIT; + } PEL3; + union + { + unsigned char BYTE; + struct + { + unsigned char SEG:1; + unsigned char :5; + unsigned char WE:1; + unsigned char WI:1; + } BIT; + } ELSEGR; + char wk6[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR33; + char wk7[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR35; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR36; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR37; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR38; + char wk8[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR41; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR42; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR43; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR44; + union + { + unsigned char BYTE; + struct + { + unsigned char ELS:8; + } BIT; + } ELSR45; + char wk9[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPU0MD:2; + unsigned char TPU1MD:2; + unsigned char TPU2MD:2; + unsigned char TPU3MD:2; + } BIT; + } ELOPF; + char wk10[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char CMTW0MD:2; + unsigned char :6; + } BIT; + } ELOPH; + union + { + unsigned char BYTE; + struct + { + unsigned char GPT0MD:3; + unsigned char :1; + unsigned char GPT1MD:3; + unsigned char :1; + } BIT; + } ELOPI; + union + { + unsigned char BYTE; + struct + { + unsigned char GPT2MD:3; + unsigned char :1; + unsigned char GPT3MD:3; + unsigned char :1; + } BIT; + } ELOPJ; +}; + +struct st_etherc +{ + union + { + unsigned long LONG; + } ETSPCMD; + union + { + unsigned long LONG; + struct + { + unsigned long MAC:3; + unsigned long :29; + } BIT; + } MACSEL; + union + { + unsigned long LONG; + struct + { + unsigned long MODE:5; + unsigned long :3; + unsigned long FULLD:1; + unsigned long :1; + unsigned long RMII_CRS_MODE:1; + unsigned long :21; + } BIT; + } MII_CTRL0; + union + { + unsigned long LONG; + struct + { + unsigned long MODE:5; + unsigned long :3; + unsigned long FULLD:1; + unsigned long :1; + unsigned long RMII_CRS_MODE:1; + unsigned long :21; + } BIT; + } MII_CTRL1; + union + { + unsigned long LONG; + struct + { + unsigned long MODE:5; + unsigned long :3; + unsigned long FULLD:1; + unsigned long :1; + unsigned long RMII_CRS_MODE:1; + unsigned long :21; + } BIT; + } MII_CTRL2; + char wk0[260]; + union + { + unsigned long LONG; + struct + { + unsigned long CATRST:1; + unsigned long SWRST:1; + unsigned long PHYRST:1; + unsigned long PHYRST2:1; + unsigned long MIICRST:1; + unsigned long :27; + } BIT; + } ETHSFTRST; + char wk1[196324]; + union + { + unsigned long LONG; + struct + { + unsigned long SYSC:16; + unsigned long :16; + } BIT; + } SYSC; + union + { + unsigned long LONG; + struct + { + unsigned long R4B:32; + } BIT; + } R4; + union + { + unsigned long LONG; + struct + { + unsigned long R5B:32; + } BIT; + } R5; + union + { + unsigned long LONG; + struct + { + unsigned long R6B:32; + } BIT; + } R6; + union + { + unsigned long LONG; + struct + { + unsigned long R7B:32; + } BIT; + } R7; + char wk2[12]; + union + { + unsigned long LONG; + struct + { + unsigned long R0B:32; + } BIT; + } R0; + union + { + unsigned long LONG; + struct + { + unsigned long R1B:32; + } BIT; + } R1; + char wk3[4068]; + union + { + unsigned long LONG; + struct + { + unsigned long TXID:32; + } BIT; + } GMAC_TXID; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOUFLOW:1; + unsigned long RETRYN:4; + unsigned long LCOLLIS:1; + unsigned long UNDERFW:1; + unsigned long OVERFW:1; + unsigned long CSERR:1; + unsigned long MCOLLIS:1; + unsigned long SCOLLIS:1; + unsigned long TFAIL:1; + unsigned long TABT:1; + unsigned long TCMP:1; + unsigned long :18; + } BIT; + } GMAC_TXRESULT; + char wk4[12]; + union + { + unsigned long LONG; + struct + { + unsigned long :30; + unsigned long DUPMODE:1; + unsigned long ETHMODE:1; + } BIT; + } GMAC_MODE; + union + { + unsigned long LONG; + struct + { + unsigned long :9; + unsigned long RRTTH:3; + unsigned long RFULLTH:2; + unsigned long REMPTH:2; + unsigned long :12; + unsigned long RAMASKEN:1; + unsigned long SFRXFIFO:1; + unsigned long MFILLTEREN:1; + unsigned long AFILLTEREN:1; + } BIT; + } GMAC_RXMODE; + union + { + unsigned long LONG; + struct + { + unsigned long :6; + unsigned long TRBMODE:2; + unsigned long :1; + unsigned long TFULLTH:2; + unsigned long TEMPTH:3; + unsigned long FSTTH:2; + unsigned long :10; + unsigned long SFOP:1; + unsigned long RTRANSLC:1; + unsigned long SPTXEN:1; + unsigned long SF:1; + unsigned long LPTXEN:1; + unsigned long RTRANSDEN:1; + } BIT; + } GMAC_TXMODE; + char wk5[4]; + union + { + unsigned long LONG; + struct + { + unsigned long :13; + unsigned long RXRST:1; + unsigned long :1; + unsigned long TXRST:1; + unsigned long :15; + unsigned long ALLRST:1; + } BIT; + } GMAC_RESET; + char wk6[76]; + union + { + unsigned long LONG; + struct + { + unsigned long PPDATA1:32; + } BIT; + } GMAC_PAUSE1; + union + { + unsigned long LONG; + struct + { + unsigned long PPDATA2:32; + } BIT; + } GMAC_PAUSE2; + union + { + unsigned long LONG; + struct + { + unsigned long PPDATA3:32; + } BIT; + } GMAC_PAUSE3; + union + { + unsigned long LONG; + struct + { + unsigned long PPDATA4:32; + } BIT; + } GMAC_PAUSE4; + union + { + unsigned long LONG; + struct + { + unsigned long PPDATA5:32; + } BIT; + } GMAC_PAUSE5; + char wk7[4]; + union + { + unsigned long LONG; + struct + { + unsigned long :31; + unsigned long PPRXEN:1; + } BIT; + } GMAC_FLWCTL; + union + { + unsigned long LONG; + struct + { + unsigned long :31; + unsigned long PPR:1; + } BIT; + } GMAC_PAUSPKT; + union + { + unsigned long LONG; + struct + { + unsigned long DATA:16; + unsigned long REGADDR:5; + unsigned long PHYADDR:5; + unsigned long RWDV:1; + unsigned long :5; + } BIT; + } GMAC_MIIM; + char wk8[92]; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR0A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR0B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR1A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR1B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR2A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR2B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR3A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR3B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR4A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR4B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR5A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR5B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR6A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR6B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR7A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR7B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR8A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR8B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR9A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR9B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR10A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR10B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR11A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR11B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR12A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR12B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR13A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR13B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR14A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR14B; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR1B:8; + unsigned long MADDR2B:8; + unsigned long MADDR3B:8; + unsigned long MADDR4B:8; + } BIT; + } GMAC_ADR15A; + union + { + unsigned long LONG; + struct + { + unsigned long MADDR5B:8; + unsigned long MADDR6B:8; + unsigned long BITMSK:8; + unsigned long :8; + } BIT; + } GMAC_ADR15B; + char wk9[128]; + union + { + unsigned long LONG; + struct + { + unsigned long :17; + unsigned long RSW:12; + unsigned long RRT:1; + unsigned long REMP:1; + unsigned long RFULL:1; + } BIT; + } GMAC_RXFIFO; + union + { + unsigned long LONG; + struct + { + unsigned long :24; + unsigned long TRBFR:3; + unsigned long TSTATUS:3; + unsigned long TEMP:1; + unsigned long TFULL:1; + } BIT; + } GMAC_TXFIFO; + union + { + unsigned long LONG; + struct + { + unsigned long RTCPIPEN:1; + unsigned long TTCPIPEN:1; + unsigned long RTCPIPACC:1; + unsigned long :29; + } BIT; + } GMAC_ACC; + char wk10[20]; + union + { + unsigned long LONG; + struct + { + unsigned long RMACEN:1; + unsigned long :31; + } BIT; + } GMAC_RXMAC_ENA; + union + { + unsigned long LONG; + struct + { + unsigned long :31; + unsigned long LPMEN:1; + } BIT; + } GMAC_LPI_MODE; + union + { + unsigned long LONG; + struct + { + unsigned long LPWTIME:16; + unsigned long LPRDEF:16; + } BIT; + } GMAC_LPI_TIMING; + char wk11[3796]; + union + { + unsigned long LONG; + struct + { + unsigned long ADDR:16; + unsigned long WORD:12; + unsigned long VALID:1; + unsigned long :2; + unsigned long NOEMP:1; + } BIT; + } BUFID; + char wk12[4092]; + union + { + unsigned long LONG; + } SPCMD; + char wk13[12]; + union + { + unsigned long LONG; + struct + { + unsigned long EMACRST:1; + unsigned long :31; + } BIT; + } EMACRST; +}; + +struct st_ethersw +{ + union + { + unsigned long LONG; + struct + { + unsigned long SWLINK0:1; + unsigned long SWLINK1:1; + unsigned long CATLINK0:1; + unsigned long CATLINK1:1; + unsigned long :28; + } BIT; + } ETHPHYLNK; + char wk0[248]; + union + { + unsigned long LONG; + struct + { + unsigned long SWTAGTYP:16; + unsigned long :15; + unsigned long SWTAGEN:1; + } BIT; + } ETHSWMTC; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long P0HDMODE:1; + unsigned long :1; + unsigned long P1HDMODE:1; + unsigned long :28; + } BIT; + } ETHSWMD; + char wk1[232]; + union + { + unsigned long LONG; + struct + { + unsigned long OUTEN:1; + unsigned long :31; + } BIT; + } SWTMEN; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTSEC:32; + } BIT; + } SWTMSTSEC; + union + { + unsigned long LONG; + struct + { + unsigned long TMSTNS:32; + } BIT; + } SWTMSTNS; + union + { + unsigned long LONG; + struct + { + unsigned long TMPSEC:32; + } BIT; + } SWTMPSEC; + union + { + unsigned long LONG; + struct + { + unsigned long TMPNS:32; + } BIT; + } SWTMPNS; + union + { + unsigned long LONG; + struct + { + unsigned long TMWTH:16; + unsigned long :16; + } BIT; + } SWTMWTH; + char wk2[20]; + union + { + unsigned long LONG; + struct + { + unsigned long TMLATSEC:32; + } BIT; + } SWTMLATSEC; + union + { + unsigned long LONG; + struct + { + unsigned long TMLATNS:32; + } BIT; + } SWTMLATNS; + char wk3[3540]; + union + { + unsigned long LONG; + struct + { + unsigned long P0ENA:1; + unsigned long P1ENA:1; + unsigned long P2ENA:1; + unsigned long :29; + } BIT; + } PORT_ENA; + union + { + unsigned long LONG; + struct + { + unsigned long P0UCASTDM:1; + unsigned long P1UCASTDM:1; + unsigned long P2UCASTDM:1; + unsigned long :29; + } BIT; + } UCAST_DEFAULT_MASK; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long P0BCASTDM:1; + unsigned long P1BCASTDM:1; + unsigned long P2BCASTDM:1; + unsigned long :29; + } BIT; + } BCAST_DEFAULT_MASK; + union + { + unsigned long LONG; + struct + { + unsigned long P0MCASTDM:1; + unsigned long P1MCASTDM:1; + unsigned long P2MCASTDM:1; + unsigned long :29; + } BIT; + } MCAST_DEFAULT_MASK; + union + { + unsigned long LONG; + struct + { + unsigned long P0BLOCKEN:1; + unsigned long P1BLOCKEN:1; + unsigned long P2BLOCKEN:1; + unsigned long :13; + unsigned long P0LEARNDIS:1; + unsigned long P1LEARNDIS:1; + unsigned long P2LEARNDIS:1; + unsigned long :13; + } BIT; + } INPUT_LERAN_BLOCK; + union + { + unsigned long LONG; + struct + { + unsigned long PORT:2; + unsigned long :3; + unsigned long MSGTRANS:1; + unsigned long ENABLE:1; + unsigned long DISCARD:1; + unsigned long :5; + unsigned long PRIORITY:3; + unsigned long P0PORTMASK:1; + unsigned long P1PORTMASK:1; + unsigned long :14; + } BIT; + } MGMT_CONFIG; + union + { + unsigned long LONG; + struct + { + unsigned long :31; + unsigned long STATSRESET:1; + } BIT; + } MODE_CONFIG; + char wk5[12]; + union + { + unsigned long LONG; + struct + { + unsigned long VLANTAGID:16; + unsigned long :16; + } BIT; + } VLAN_TAG_ID; + char wk6[72]; + union + { + unsigned long LONG; + struct + { + unsigned long BUSYINIT:1; + unsigned long NOCELL:1; + unsigned long MEMFULL:1; + unsigned long MEMFULL_LT:1; + unsigned long :2; + unsigned long DEQUEGRANT:1; + unsigned long :9; + unsigned long CELLAVILABLE:16; + } BIT; + } OQMGR_STATUS; + union + { + unsigned long LONG; + struct + { + unsigned long MINCELLS:5; + unsigned long :27; + } BIT; + } QMGR_MINCELLS; + union + { + unsigned long LONG; + struct + { + unsigned long STMINCELLS:5; + unsigned long :27; + } BIT; + } QMGR_ST_MINCELLS; + union + { + unsigned long LONG; + struct + { + unsigned long P0CGS:1; + unsigned long P1CGS:1; + unsigned long P2CGS:1; + unsigned long :29; + } BIT; + } QMGR_CGS_STAT; + union + { + unsigned long LONG; + struct + { + unsigned long P0TXFIFOST:1; + unsigned long P1TXFIFOST:1; + unsigned long P2TXFIFOST:1; + unsigned long :13; + unsigned long P0RXFIFOAV:1; + unsigned long P1RXFIFOAV:1; + unsigned long P2RXFIFOAV:1; + unsigned long :13; + } BIT; + } QMGR_IFACE_STAT; + union + { + unsigned long LONG; + struct + { + unsigned long QUEUE0:5; + unsigned long :3; + unsigned long QUEUE1:5; + unsigned long :3; + unsigned long QUEUE2:5; + unsigned long :3; + unsigned long QUEUE3:5; + unsigned long :3; + } BIT; + } QMGR_WEIGHTS; + char wk7[104]; + union + { + unsigned long LONG; + struct + { + unsigned long PRIORITY0:3; + unsigned long PRIORITY1:3; + unsigned long PRIORITY2:3; + unsigned long PRIORITY3:3; + unsigned long PRIORITY4:3; + unsigned long PRIORITY5:3; + unsigned long PRIORITY6:3; + unsigned long PRIORITY7:3; + unsigned long :8; + } BIT; + } VLAN_PRIORITY[3]; + char wk8[52]; + union + { + unsigned long LONG; + struct + { + unsigned long ADDRESS:8; + unsigned long IPV6SELECT:1; + unsigned long PRIORITY:2; + unsigned long :20; + unsigned long READ:1; + } BIT; + } IP_PRIORITY0; + union + { + unsigned long LONG; + struct + { + unsigned long ADDRESS:8; + unsigned long IPV6SELECT:1; + unsigned long PRIORITY:2; + unsigned long :20; + unsigned long READ:1; + } BIT; + } IP_PRIORITY1; + union + { + unsigned long LONG; + struct + { + unsigned long ADDRESS:8; + unsigned long IPV6SELECT:1; + unsigned long PRIORITY:2; + unsigned long :20; + unsigned long READ:1; + } BIT; + } IP_PRIORITY2; + char wk9[52]; + union + { + unsigned long LONG; + struct + { + unsigned long VLANEN:1; + unsigned long IPEN:1; + unsigned long :2; + unsigned long DEFAULTPRI:3; + unsigned long :25; + } BIT; + } PRIORITY_CFG[3]; + char wk10[52]; + union + { + unsigned long LONG; + struct + { + unsigned long HUBEN:1; + unsigned long DIR0TO1EN:1; + unsigned long DIR1TO0EN:1; + unsigned long BROCAFILEN:1; + unsigned long HUBIPG:4; + unsigned long :24; + } BIT; + } HUB_CONTROL; + union + { + unsigned long LONG; + struct + { + unsigned long NUM1TO0:32; + } BIT; + } HUB_STATS; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD1n:8; + unsigned long MACADD2n:8; + unsigned long MACADD3n:8; + unsigned long MACADD4n:8; + } BIT; + } HUB_FLT_MAC0lo; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD5n:8; + unsigned long MACADD6n:8; + unsigned long MASKCOMP:8; + unsigned long FORCEFOW:1; + unsigned long :7; + } BIT; + } HUB_FLT_MAC0hi; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD1n:8; + unsigned long MACADD2n:8; + unsigned long MACADD3n:8; + unsigned long MACADD4n:8; + } BIT; + } HUB_FLT_MAC1lo; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD5n:8; + unsigned long MACADD6n:8; + unsigned long MASKCOMP:8; + unsigned long FORCEFOW:1; + unsigned long :7; + } BIT; + } HUB_FLT_MAC1hi; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD1n:8; + unsigned long MACADD2n:8; + unsigned long MACADD3n:8; + unsigned long MACADD4n:8; + } BIT; + } HUB_FLT_MAC2lo; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD5n:8; + unsigned long MACADD6n:8; + unsigned long MASKCOMP:8; + unsigned long FORCEFOW:1; + unsigned long :7; + } BIT; + } HUB_FLT_MAC2hi; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD1n:8; + unsigned long MACADD2n:8; + unsigned long MACADD3n:8; + unsigned long MACADD4n:8; + } BIT; + } HUB_FLT_MAC3lo; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD5n:8; + unsigned long MACADD6n:8; + unsigned long MASKCOMP:8; + unsigned long FORCEFOW:1; + unsigned long :7; + } BIT; + } HUB_FLT_MAC3hi; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD1n:8; + unsigned long MACADD2n:8; + unsigned long MACADD3n:8; + unsigned long MACADD4n:8; + } BIT; + } HUB_FLT_MAC4lo; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD5n:8; + unsigned long MACADD6n:8; + unsigned long MASKCOMP:8; + unsigned long FORCEFOW:1; + unsigned long :7; + } BIT; + } HUB_FLT_MAC4hi; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD1n:8; + unsigned long MACADD2n:8; + unsigned long MACADD3n:8; + unsigned long MACADD4n:8; + } BIT; + } HUB_FLT_MAC5lo; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD5n:8; + unsigned long MACADD6n:8; + unsigned long MASKCOMP:8; + unsigned long FORCEFOW:1; + unsigned long :7; + } BIT; + } HUB_FLT_MAC5hi; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD1n:8; + unsigned long MACADD2n:8; + unsigned long MACADD3n:8; + unsigned long MACADD4n:8; + } BIT; + } HUB_FLT_MAC6lo; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD5n:8; + unsigned long MACADD6n:8; + unsigned long MASKCOMP:8; + unsigned long FORCEFOW:1; + unsigned long :7; + } BIT; + } HUB_FLT_MAC6hi; + char wk11[256]; + unsigned long TOTAL_BYT_FRM; + unsigned long TOTAL_BYT_DISC; + unsigned long TOTAL_FRM; + unsigned long TOTAL_DISC; + unsigned long ODISC0; + unsigned long IDISC_BLOCKED0; + unsigned long ODISC1; + unsigned long IDISC_BLOCKED1; + unsigned long ODISC2; + unsigned long IDISC_BLOCKED2; + char wk12[472]; + union + { + unsigned long LONG; + struct + { + unsigned long SRCADD1:8; + unsigned long SRCADD2:8; + unsigned long SRCADD3:8; + unsigned long SRCADD4:8; + } BIT; + } LRN_REC_A; + union + { + unsigned long LONG; + struct + { + unsigned long SRCADD5:8; + unsigned long SRCADD6:8; + unsigned long HASH:8; + unsigned long PORT:4; + unsigned long :4; + } BIT; + } LRN_REC_B; + union + { + unsigned long LONG; + struct + { + unsigned long LERNAVAL:1; + unsigned long :31; + } BIT; + } LRN_STATUS; + char wk13[0x4000-0x050C]; + char ADR_TABLE[0x8000-0x4000]; + struct + { + char mac_wk01[8]; + union + { + unsigned long LONG; + struct + { + unsigned long TXENA:1; + unsigned long RXENA:1; + unsigned long :11; + unsigned long SWRESET:1; + unsigned long :9; + unsigned long CNTRLREMEN:1; + unsigned long NOLGTHCHK:1; + unsigned long :1; + unsigned long RXERRDISC:1; + unsigned long :4; + unsigned long CNTRESET:1; + } BIT; + } COMMAND_CONFIG; + char mac_wk02[8]; + union + { + unsigned long LONG; + struct + { + unsigned long FRMLEN:14; + unsigned long :18; + } BIT; + } FRM_LENGTH; + char mac_wk03[4]; + unsigned long RX_SECTION_EMPTY; + unsigned long RX_SECTION_FULL; + unsigned long TX_SECTION_EMPTY; + unsigned long TX_SECTION_FULL; + unsigned long RX_ALMOST_EMPTY; + unsigned long RX_ALMOST_FULL; + unsigned long TX_ALMOST_EMPTY; + unsigned long TX_ALMOST_FULL; + char mac_wk04[28]; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long SPEEDP0:1; + unsigned long :1; + unsigned long HDPP0:1; + unsigned long :1; + unsigned long SPEEDP1:1; + unsigned long :1; + unsigned long HDPP1:1; + unsigned long :17; + } BIT; + } MAC_STATUS; + union + { + unsigned long LONG; + struct + { + unsigned long TXIPGLEN:5; + unsigned long :27; + } BIT; + } TX_IPG_LENGTH; + char mac_wk05[160]; + unsigned long etherStatsOctets; + unsigned long OctetsOK; + unsigned long aAlignmentErrors; + unsigned long aPAUSEMACCtrlFrames; + unsigned long FramesOK; + unsigned long CRCErrors; + unsigned long VLANOK; + unsigned long ifInErrors; + unsigned long ifInUcastPkts; + unsigned long ifInMulticastPkts; + unsigned long ifInBroadcastPkts; + unsigned long etherStatsDropEvents; + unsigned long etherStatsPkts; + unsigned long etherStatsUndersizePkts; + unsigned long etherStatsPkts64Octets; + unsigned long etherStatsPkts65to127Octets; + unsigned long etherStatsPkts128to255Octets; + unsigned long etherStatsPkts256to511Octets; + unsigned long etherStatsPkts512to1023Octets; + unsigned long etherStatsPkts1024to1518Octets; + unsigned long etherStatsPkts1519toMax; + unsigned long etherStatsOversizePkts; + unsigned long etherStatsJabbers; + unsigned long etherStatsFragments; + unsigned long aMACControlFramesReceived; + unsigned long aFrameTooLong; + char mac_wk06[4]; + unsigned long StackedVLANOK; + char mac_wk07[16]; + unsigned long TXetherStatsOctets; + unsigned long TxOctetsOK; + char mac_wk08[4]; + unsigned long TXaPAUSEMACCtrlFrames; + unsigned long TxFramesOK; + unsigned long TxCRCErrors; + unsigned long TxVLANOK; + unsigned long ifOutErrors; + unsigned long ifUcastPkts; + unsigned long ifMulticastPkts; + unsigned long ifBroadcastPkts; + unsigned long TXetherStatsDropEvents; + unsigned long TXetherStatsPkts; + unsigned long TXetherStatsUndersizePkts; + unsigned long TXetherStatsPkts64Octets; + unsigned long TXetherStatsPkts65to127Octets; + unsigned long TXetherStatsPkts128to255Octets; + unsigned long TXetherStatsPkts256to511Octets; + unsigned long TXetherStatsPkts512to1023Octets; + unsigned long TXetherStatsPkts1024to1518Octets; + unsigned long TXetherStatsPkts1519toMax; + unsigned long TXetherStatsOversizePkts; + unsigned long TXetherStatsJabbers; + unsigned long TXetherStatsFragments; + unsigned long aMACControlFrames; + unsigned long TXaFrameTooLong; + char mac_wk09[4]; + unsigned long aMultipleCollisions; + unsigned long aSingleCollisions; + unsigned long aLateCollisions; + unsigned long aExcessCollisions; + char mac_wk10[0xA000-0x81FC]; + } MAC[2]; + char wk32[4]; + union + { + unsigned long LONG; + struct + { + unsigned long IRQENA:1; + unsigned long IRQEVTOFF:1; + unsigned long IRQEVTPERD:1; + unsigned long IRQTIMOVER:1; + unsigned long IRQTEST:1; + unsigned long :7; + unsigned long IRQTXENAP0:1; + unsigned long IRQTXENAP1:1; + unsigned long :18; + } BIT; + } TSM_CONFIG; + union + { + unsigned long LONG; + struct + { + unsigned long IRQENA:1; + unsigned long IRQEVTOFF:1; + unsigned long IRQEVTPERD:1; + unsigned long IRQTIMOVER:1; + unsigned long IRQTEST:1; + unsigned long :7; + unsigned long IRQTXP0:1; + unsigned long IRQTXP1:1; + unsigned long :18; + } BIT; + } TSM_IRQ_STAT_ACK; + char wk33[20]; + union + { + unsigned long LONG; + struct + { + unsigned long TSVALID:1; + unsigned long TSOVR:1; + unsigned long TSKEEP:1; + unsigned long :29; + } BIT; + } PORT0_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long TSREG:32; + } BIT; + } PORT0_TIME; + union + { + unsigned long LONG; + struct + { + unsigned long TSVALID:1; + unsigned long TSOVR:1; + unsigned long TSKEEP:1; + unsigned long :29; + } BIT; + } PORT1_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long TSREG:32; + } BIT; + } PORT1_TIME; + char wk34[240]; + union + { + unsigned long LONG; + struct + { + unsigned long TMENA:1; + unsigned long :1; + unsigned long EVTOFFENA:1; + unsigned long :1; + unsigned long EVTPERIENA:1; + unsigned long EVTPERIRST:1; + unsigned long :3; + unsigned long RST:1; + unsigned long :1; + unsigned long CAPTR:1; + unsigned long PLUS1:1; + unsigned long :19; + } BIT; + } ATIME_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long TMR:32; + } BIT; + } ATIME; + union + { + unsigned long LONG; + struct + { + unsigned long OFFSET:32; + } BIT; + } ATIME_OFFSET; + union + { + unsigned long LONG; + struct + { + unsigned long TIMPEREVET:32; + } BIT; + } ATIME_EVT_PERIOD; + union + { + unsigned long LONG; + struct + { + unsigned long DRIFCORVAL:31; + unsigned long :1; + } BIT; + } ATIME_CORR; + union + { + unsigned long LONG; + struct + { + unsigned long CLKPERD:7; + unsigned long :1; + unsigned long CORRINC:7; + unsigned long :1; + unsigned long OFFSCORRINC:7; + unsigned long :9; + } BIT; + } ATIME_INC; + union + { + unsigned long LONG; + struct + { + unsigned long SECTIM:32; + } BIT; + } ATIME_SEC; + union + { + unsigned long LONG; + struct + { + unsigned long OFFCOR:32; + } BIT; + } ATIME_CORR_OFFS; + char wk35[7872]; + union + { + unsigned long LONG; + struct + { + unsigned long DLRENA:1; + unsigned long :3; + unsigned long BECTIMOUT:1; + unsigned long :3; + unsigned long CYCMCLK:8; + unsigned long :16; + } BIT; + } DLR_CONTROL; + union + { + unsigned long LONG; + struct + { + unsigned long BEAREV0:1; + unsigned long BEAREV1:1; + unsigned long :6; + unsigned long CURRSTA:8; + unsigned long LINSTAP0:1; + unsigned long LINSTAP1:1; + unsigned long :6; + unsigned long NETTOPGY:8; + } BIT; + } DLR_STATUS; + union + { + unsigned long LONG; + struct + { + unsigned long ETHTYPDLR:16; + unsigned long :16; + } BIT; + } DLR_ETH_TYP; + union + { + unsigned long LONG; + struct + { + unsigned long IRQCHNGENA:1; + unsigned long IRQFLUENA:1; + unsigned long IRQSTOPP0:1; + unsigned long IRQSTOPP1:1; + unsigned long IRQBECTOUT0:1; + unsigned long IRQBECTOUT1:1; + unsigned long IRQSUPENA:1; + unsigned long IRQLINKENA0:1; + unsigned long IRQLINKENA1:1; + unsigned long IRQSUPIGENA:1; + unsigned long IRQIPADDREN:1; + unsigned long IRQINVTMREN:1; + unsigned long IRQBECENA0:1; + unsigned long IRQBECENA1:1; + unsigned long IRQFRMDSP0:1; + unsigned long IRQFRMDSP1:1; + unsigned long :14; + unsigned long ATOMICOR:1; + unsigned long ATOMICAND:1; + } BIT; + } DLR_IRQ_CTRL; + union + { + unsigned long LONG; + struct + { + unsigned long STACHANGE:1; + unsigned long FLUEVENT:1; + unsigned long STOPNBCHK0:1; + unsigned long STOPNBCHK1:1; + unsigned long BECTMRP0:1; + unsigned long BECTMRP1:1; + unsigned long SUPRCHAG:1; + unsigned long LINKSTAP0:1; + unsigned long LINKSTAP1:1; + unsigned long SUPIGNBEC:1; + unsigned long IPCHANEVET:1; + unsigned long INVTMR:1; + unsigned long BECFRAP0:1; + unsigned long BECFRAP1:1; + unsigned long FRMDISP0:1; + unsigned long FRMDISP1:1; + unsigned long :16; + } BIT; + } DLR_IRQ_STAT_ACK; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD1:8; + unsigned long MACADD2:8; + unsigned long MACADD3:8; + unsigned long MACADD4:8; + } BIT; + } LOC_MAClo; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD5:8; + unsigned long MACADD6:8; + unsigned long :16; + } BIT; + } LOC_MAChi; + char wk36[4]; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD1:8; + unsigned long MACADD2:8; + unsigned long MACADD3:8; + unsigned long MACADD4:8; + } BIT; + } SUPR_MAClo; + union + { + unsigned long LONG; + struct + { + unsigned long MACADD5:8; + unsigned long MACADD6:8; + unsigned long SUPRPRE:8; + unsigned long :8; + } BIT; + } SUPR_MAChi; + union + { + unsigned long LONG; + struct + { + unsigned long RINGSTATE:8; + unsigned long VLANVALID:1; + unsigned long :7; + unsigned long VLANCI:16; + } BIT; + } STATE_VLAN; + union + { + unsigned long LONG; + struct + { + unsigned long BECTMOUT:32; + } BIT; + } BEC_TMOUT; + union + { + unsigned long LONG; + struct + { + unsigned long BECINTVAL:32; + } BIT; + } BEC_INTRVL; + union + { + unsigned long LONG; + struct + { + unsigned long SPVIP:32; + } BIT; + } SUPR_IPADR; + union + { + unsigned long LONG; + struct + { + unsigned long DLRRINGTPY:8; + unsigned long DLRRINGVER:8; + unsigned long SOURP:8; + unsigned long :8; + } BIT; + } ETH_STYP_VER; + union + { + unsigned long LONG; + struct + { + unsigned long INVBECTMOUT:32; + } BIT; + } INV_TMOUT; + unsigned long SEQ_ID; + char wk37[28]; + unsigned long RX_STAT0; + unsigned long RX_ERR_STAT0; + unsigned long TX_STAT0; + char wk38[4]; + unsigned long RX_STAT1; + unsigned long RX_ERR_STAT1; + unsigned long TX_STAT1; +}; + +struct st_gpt +{ + union + { + unsigned short WORD; + struct + { + unsigned short CST0:1; + unsigned short CST1:1; + unsigned short CST2:1; + unsigned short CST3:1; + unsigned short :12; + } BIT; + } GTSTR; + union + { + unsigned short WORD; + struct + { + unsigned short NFA0EN:1; + unsigned short NFB0EN:1; + unsigned short NFA1EN:1; + unsigned short NFB1EN:1; + unsigned short NFA2EN:1; + unsigned short NFB2EN:1; + unsigned short NFA3EN:1; + unsigned short NFB3EN:1; + unsigned short NFCS0:2; + unsigned short NFCS1:2; + unsigned short NFCS2:2; + unsigned short NFCS3:2; + } BIT; + } NFCR; + union + { + unsigned short WORD; + struct + { + unsigned short CSHW0:2; + unsigned short CSHW1:2; + unsigned short CSHW2:2; + unsigned short CSHW3:2; + unsigned short CPHW0:2; + unsigned short CPHW1:2; + unsigned short CPHW2:2; + unsigned short CPHW3:2; + } BIT; + } GTHSCR; + union + { + unsigned short WORD; + struct + { + unsigned short CCHW0:2; + unsigned short CCHW1:2; + unsigned short CCHW2:2; + unsigned short CCHW3:2; + unsigned short CCSW0:1; + unsigned short CCSW1:1; + unsigned short CCSW2:1; + unsigned short CCSW3:1; + unsigned short :4; + } BIT; + } GTHCCR; + union + { + unsigned short WORD; + struct + { + unsigned short CSHSL0:4; + unsigned short CSHSL1:4; + unsigned short CSHSL2:4; + unsigned short CSHSL3:4; + } BIT; + } GTHSSR; + union + { + unsigned short WORD; + struct + { + unsigned short CSHPL0:4; + unsigned short CSHPL1:4; + unsigned short CSHPL2:4; + unsigned short CSHPL3:4; + } BIT; + } GTHPSR; + union + { + unsigned short WORD; + struct + { + unsigned short WP0:1; + unsigned short WP1:1; + unsigned short WP2:1; + unsigned short WP3:1; + unsigned short :12; + } BIT; + } GTWP; + union + { + unsigned short WORD; + struct + { + unsigned short SYNC0:2; + unsigned short :2; + unsigned short SYNC1:2; + unsigned short :2; + unsigned short SYNC2:2; + unsigned short :2; + unsigned short SYNC3:2; + unsigned short :2; + } BIT; + } GTSYNC; + union + { + unsigned short WORD; + struct + { + unsigned short ETIPEN:1; + unsigned short ETINEN:1; + unsigned short :11; + unsigned short GTENFCS:2; + unsigned short GTETRGEN:1; + } BIT; + } GTETINT; + char wk0[2]; + union + { + unsigned short WORD; + struct + { + unsigned short BD00:1; + unsigned short BD01:1; + unsigned short BD02:1; + unsigned short BD03:1; + unsigned short BD10:1; + unsigned short BD11:1; + unsigned short BD12:1; + unsigned short BD13:1; + unsigned short BD20:1; + unsigned short BD21:1; + unsigned short BD22:1; + unsigned short BD23:1; + unsigned short BD30:1; + unsigned short BD31:1; + unsigned short BD32:1; + unsigned short BD33:1; + } BIT; + } GTBDR; + char wk1[2]; + union + { + unsigned short WORD; + struct + { + unsigned short SWP0:1; + unsigned short SWP1:1; + unsigned short SWP2:1; + unsigned short SWP3:1; + unsigned short :12; + } BIT; + } GTSWP; +}; + +struct st_gpt0 +{ + union + { + unsigned short WORD; + struct + { + unsigned short GTIOA:6; + unsigned short OADFLT:1; + unsigned short OAHLD:1; + unsigned short GTIOB:6; + unsigned short OBDFLT:1; + unsigned short OBHLD:1; + } BIT; + } GTIOR; + union + { + unsigned short WORD; + struct + { + unsigned short GTINTA:1; + unsigned short GTINTB:1; + unsigned short GTINTC:1; + unsigned short GTINTD:1; + unsigned short GTINTE:1; + unsigned short GTINTF:1; + unsigned short GTINTPR:2; + unsigned short :3; + unsigned short EINT:1; + unsigned short ADTRAUEN:1; + unsigned short ADTRADEN:1; + unsigned short ADTRBUEN:1; + unsigned short ADTRBDEN:1; + } BIT; + } GTINTAD; + union + { + unsigned short WORD; + struct + { + unsigned short MD:3; + unsigned short :5; + unsigned short TPCS:2; + unsigned short :2; + unsigned short CCLR:2; + unsigned short :2; + } BIT; + } GTCR; + union + { + unsigned short WORD; + struct + { + unsigned short CCRA:2; + unsigned short CCRB:2; + unsigned short PR:2; + unsigned short CCRSWT:1; + unsigned short :1; + unsigned short ADTTA:2; + unsigned short ADTDA:1; + unsigned short :1; + unsigned short ADTTB:2; + unsigned short ADTDB:1; + unsigned short :1; + } BIT; + } GTBER; + union + { + unsigned short WORD; + struct + { + unsigned short UD:1; + unsigned short UDF:1; + unsigned short :14; + } BIT; + } GTUDC; + union + { + unsigned short WORD; + struct + { + unsigned short ITLA:1; + unsigned short ITLB:1; + unsigned short ITLC:1; + unsigned short ITLD:1; + unsigned short ITLE:1; + unsigned short ITLF:1; + unsigned short IVTC:2; + unsigned short IVTT:3; + unsigned short :1; + unsigned short ADTAL:1; + unsigned short :1; + unsigned short ADTBL:1; + unsigned short :1; + } BIT; + } GTITC; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short ITCNT:3; + unsigned short DTEF:1; + unsigned short :3; + unsigned short TUCF:1; + } BIT; + } GTST; + unsigned short GTCNT; + unsigned short GTCCRA; + unsigned short GTCCRB; + unsigned short GTCCRC; + unsigned short GTCCRD; + unsigned short GTCCRE; + unsigned short GTCCRF; + unsigned short GTPR; + unsigned short GTPBR; + unsigned short GTPDBR; + char wk0[2]; + unsigned short GTADTRA; + unsigned short GTADTBRA; + unsigned short GTADTDBRA; + char wk1[2]; + unsigned short GTADTRB; + unsigned short GTADTBRB; + unsigned short GTADTDBRB; + char wk2[2]; + union + { + unsigned short WORD; + struct + { + unsigned short NEA:1; + unsigned short NEB:1; + unsigned short NVA:1; + unsigned short NVB:1; + unsigned short NFS:4; + unsigned short NFV:1; + unsigned short :3; + unsigned short SWN:1; + unsigned short :1; + unsigned short OAE:1; + unsigned short OBE:1; + } BIT; + } GTONCR; + union + { + unsigned short WORD; + struct + { + unsigned short TDE:1; + unsigned short :3; + unsigned short TDBUE:1; + unsigned short TDBDE:1; + unsigned short :2; + unsigned short TDFER:1; + unsigned short :7; + } BIT; + } GTDTCR; + unsigned short GTDVU; + unsigned short GTDVD; + unsigned short GTDBU; + unsigned short GTDBD; + union + { + unsigned short WORD; + struct + { + unsigned short SOS:2; + unsigned short :14; + } BIT; + } GTSOS; + union + { + unsigned short WORD; + struct + { + unsigned short SOTR:1; + unsigned short :15; + } BIT; + } GTSOTR; +}; + +struct st_icu +{ + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR0; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR1; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR2; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR3; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR4; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR5; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR6; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR7; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR8; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR9; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR10; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR11; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR12; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR13; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR14; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long IRQMD:2; + unsigned long :28; + } BIT; + } IRQCR15; + union + { + unsigned long LONG; + struct + { + unsigned long FLTEN0:1; + unsigned long FLTEN1:1; + unsigned long FLTEN2:1; + unsigned long FLTEN3:1; + unsigned long FLTEN4:1; + unsigned long FLTEN5:1; + unsigned long FLTEN6:1; + unsigned long FLTEN7:1; + unsigned long FLTEN8:1; + unsigned long FLTEN9:1; + unsigned long FLTEN10:1; + unsigned long FLTEN11:1; + unsigned long FLTEN12:1; + unsigned long FLTEN13:1; + unsigned long FLTEN14:1; + unsigned long FLTEN15:1; + unsigned long :16; + } BIT; + } IRQFLTE; + union + { + unsigned long LONG; + struct + { + unsigned long FCLKSEL0:2; + unsigned long FCLKSEL1:2; + unsigned long FCLKSEL2:2; + unsigned long FCLKSEL3:2; + unsigned long FCLKSEL4:2; + unsigned long FCLKSEL5:2; + unsigned long FCLKSEL6:2; + unsigned long FCLKSEL7:2; + unsigned long FCLKSEL8:2; + unsigned long FCLKSEL9:2; + unsigned long FCLKSEL10:2; + unsigned long FCLKSEL11:2; + unsigned long FCLKSEL12:2; + unsigned long FCLKSEL13:2; + unsigned long FCLKSEL14:2; + unsigned long FCLKSEL15:2; + } BIT; + } IRQFLTC; + union + { + unsigned long LONG; + struct + { + unsigned long NMIST:1; + unsigned long ECMST:1; + unsigned long :30; + } BIT; + } NMISR; + union + { + unsigned long LONG; + struct + { + unsigned long NMICLR:1; + unsigned long ECMCLR:1; + unsigned long :30; + } BIT; + } NMICLR; + union + { + unsigned long LONG; + struct + { + unsigned long :3; + unsigned long NMIMD:1; + unsigned long :28; + } BIT; + } NMICR; + union + { + unsigned long LONG; + struct + { + unsigned long NFLTEN:1; + unsigned long :31; + } BIT; + } NMIFLTE; + union + { + unsigned long LONG; + struct + { + unsigned long NFCLKSEL:2; + unsigned long :30; + } BIT; + } NMIFLTC; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long EPHYMD:2; + unsigned long :28; + } BIT; + } EPHYCR0; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long EPHYMD:2; + unsigned long :28; + } BIT; + } EPHYCR1; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long EPHYMD:2; + unsigned long :28; + } BIT; + } EPHYCR2; + union + { + unsigned long LONG; + struct + { + unsigned long EFLTEN0:1; + unsigned long EFLTEN1:1; + unsigned long EFLTEN2:1; + unsigned long :29; + } BIT; + } EPHYFLTE; + union + { + unsigned long LONG; + struct + { + unsigned long EFCLKSEL0:2; + unsigned long EFCLKSEL1:2; + unsigned long EFCLKSEL2:2; + unsigned long :26; + } BIT; + } EPHYFLTC; + union + { + unsigned long LONG; + struct + { + unsigned long DFLTEN0:1; + unsigned long DFLTEN1:1; + unsigned long DFLTEN2:1; + unsigned long :29; + } BIT; + } DREQFLTE; + union + { + unsigned long LONG; + struct + { + unsigned long DFCLKSEL0:2; + unsigned long DFCLKSEL1:2; + unsigned long DFCLKSEL2:2; + unsigned long :26; + } BIT; + } DREQFLTC; + char wk0[24]; + union + { + unsigned long LONG; + struct + { + unsigned long CM3INT:1; + unsigned long :15; + unsigned long CR4INT:1; + unsigned long :15; + } BIT; + } CPUINT; +}; + +struct st_iwdt +{ + union + { + unsigned char BYTE; + struct + { + unsigned char REFRESH:8; + } BIT; + } IWDTRR; + char wk0[1]; + union + { + unsigned short WORD; + struct + { + unsigned short TOPS:2; + unsigned short :2; + unsigned short CKS:4; + unsigned short RPES:2; + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + } BIT; + } IWDTCR; + union + { + unsigned short WORD; + struct + { + unsigned short CNTVAL:14; + unsigned short UNDFF:1; + unsigned short REFEF:1; + } BIT; + } IWDTSR; + union + { + unsigned char BYTE; + struct + { + unsigned char :7; + unsigned char RSTIRQS:1; + } BIT; + } IWDTRCR; +}; + +struct st_mpc +{ + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } P00PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } P01PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } P02PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } P03PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } P04PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } P05PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } P06PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } P07PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P10PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P11PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P12PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P13PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P14PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P15PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P16PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P17PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P20PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P21PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P22PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P23PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P24PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P25PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P26PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P27PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P30PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P31PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P32PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P33PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P34PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P35PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P36PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P37PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P40PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P41PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P42PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P43PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P44PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P45PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P46PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P47PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P50PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P51PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P52PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P53PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P54PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P55PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P56PFS; + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P60PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P61PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P62PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P63PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P64PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P65PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P66PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P67PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P70PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P71PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P72PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P73PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P74PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P75PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P76PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } P77PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P80PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P81PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P82PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P83PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P84PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P85PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P86PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P87PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P90PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P91PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P92PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P93PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P94PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P95PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P96PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char ASEL:1; + } BIT; + } P97PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PA7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PB7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PC7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :1; + unsigned char ASEL:1; + } BIT; + } PD0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :1; + unsigned char ASEL:1; + } BIT; + } PD1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :1; + unsigned char ASEL:1; + } BIT; + } PD2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :1; + unsigned char ASEL:1; + } BIT; + } PD3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :1; + unsigned char ASEL:1; + } BIT; + } PD4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :1; + unsigned char ASEL:1; + } BIT; + } PD5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :1; + unsigned char ASEL:1; + } BIT; + } PD6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :1; + unsigned char ASEL:1; + } BIT; + } PD7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PE7PFS; + char wk1[5]; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PF5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PF6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PF7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PG0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PG1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PG2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PG3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PG4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PG5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PG6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PG7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PH7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PJ7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PK0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PK1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PK2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PK3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PK4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PK5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PK6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PK7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PL7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PM0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PM1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PM2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PM3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PM4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PM5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PM6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PM7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PN0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PN1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PN2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PN3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PN4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PN5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PN6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PN7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PP0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PP1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PP2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PP3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PP4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PP5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PP6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char :2; + } BIT; + } PP7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PR0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PR1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PR2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PR3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PR4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PR5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PR6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PR7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PS0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PS1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PS2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PS3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PS4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PS5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PS6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PS7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PT0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PT1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PT2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PT3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PT4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PT5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PT6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PT7PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PU0PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PU1PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PU2PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PU3PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PU4PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PU5PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PU6PFS; + union + { + unsigned char BYTE; + struct + { + unsigned char PSEL:6; + unsigned char ISEL:1; + unsigned char :1; + } BIT; + } PU7PFS; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char PFSWE:1; + unsigned char B0WI:1; + } BIT; + } PWPR; +}; + +struct st_mtu +{ + union + { + unsigned char BYTE; + struct + { + unsigned char OE3B:1; + unsigned char OE4A:1; + unsigned char OE4B:1; + unsigned char OE3D:1; + unsigned char OE4C:1; + unsigned char OE4D:1; + unsigned char :2; + } BIT; + } TOERA; + char wk0[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char UF:1; + unsigned char VF:1; + unsigned char WF:1; + unsigned char FB:1; + unsigned char P:1; + unsigned char N:1; + unsigned char BDC:1; + unsigned char :1; + } BIT; + } TGCRA; + union + { + unsigned char BYTE; + struct + { + unsigned char OLSP:1; + unsigned char OLSN:1; + unsigned char TOCS:1; + unsigned char TOCL:1; + unsigned char :2; + unsigned char PSYE:1; + unsigned char :1; + } BIT; + } TOCR1A; + union + { + unsigned char BYTE; + struct + { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3P:1; + unsigned char OLS3N:1; + unsigned char BF:2; + } BIT; + } TOCR2A; + char wk1[4]; + unsigned short TCDRA; + unsigned short TDDRA; + char wk2[8]; + unsigned short TCNTSA; + unsigned short TCBRA; + char wk3[12]; + union + { + unsigned char BYTE; + struct + { + unsigned char T4VCOR:3; + unsigned char T4VEN:1; + unsigned char T3ACOR:3; + unsigned char T3AEN:1; + } BIT; + } TITCR1A; + union + { + unsigned char BYTE; + struct + { + unsigned char T4VCNT:3; + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + } BIT; + } TITCNT1A; + union + { + unsigned char BYTE; + struct + { + unsigned char BTE:2; + unsigned char :6; + } BIT; + } TBTERA; + char wk4[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TDER:1; + unsigned char :7; + } BIT; + } TDERA; + char wk5[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3P:1; + unsigned char OLS3N:1; + unsigned char :2; + } BIT; + } TOLBRA; + char wk6[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char TITM:1; + unsigned char :7; + } BIT; + } TITMRA; + union + { + unsigned char BYTE; + struct + { + unsigned char TRG4COR:3; + unsigned char :5; + } BIT; + } TITCR2A; + union + { + unsigned char BYTE; + struct + { + unsigned char TRG4CNT:3; + unsigned char :5; + } BIT; + } TITCNT2A; + char wk7[35]; + union + { + unsigned char BYTE; + struct + { + unsigned char WRE:1; + unsigned char SCC:1; + unsigned char :5; + unsigned char CCE:1; + } BIT; + } TWCRA; + char wk8[15]; + union + { + unsigned char BYTE; + struct + { + unsigned char DRS:1; + unsigned char :7; + } BIT; + } TMDR2A; + char wk9[15]; + union + { + unsigned char BYTE; + struct + { + unsigned char CST0:1; + unsigned char CST1:1; + unsigned char CST2:1; + unsigned char CST8:1; + unsigned char :2; + unsigned char CST3:1; + unsigned char CST4:1; + } BIT; + } TSTRA; + union + { + unsigned char BYTE; + struct + { + unsigned char SYNC0:1; + unsigned char SYNC1:1; + unsigned char SYNC2:1; + unsigned char :3; + unsigned char SYNC3:1; + unsigned char SYNC4:1; + } BIT; + } TSYRA; + union + { + unsigned char BYTE; + struct + { + unsigned char SCH7:1; + unsigned char SCH6:1; + unsigned char :1; + unsigned char SCH4:1; + unsigned char SCH3:1; + unsigned char SCH2:1; + unsigned char SCH1:1; + unsigned char SCH0:1; + } BIT; + } TCSYSTR; + char wk10[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char RWE:1; + unsigned char :7; + } BIT; + } TRWERA; + char wk11[1925]; + union + { + unsigned char BYTE; + struct + { + unsigned char OE6B:1; + unsigned char OE7A:1; + unsigned char OE7B:1; + unsigned char OE6D:1; + unsigned char OE7C:1; + unsigned char OE7D:1; + unsigned char :2; + } BIT; + } TOERB; + char wk12[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char OLSP:1; + unsigned char OLSN:1; + unsigned char TOCS:1; + unsigned char TOCL:1; + unsigned char :2; + unsigned char PSYE:1; + unsigned char :1; + } BIT; + } TOCR1B; + union + { + unsigned char BYTE; + struct + { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3P:1; + unsigned char OLS3N:1; + unsigned char BF:2; + } BIT; + } TOCR2B; + char wk13[4]; + unsigned short TCDRB; + unsigned short TDDRB; + char wk14[8]; + unsigned short TCNTSB; + unsigned short TCBRB; + char wk15[12]; + union + { + unsigned char BYTE; + struct + { + unsigned char T7VCOR:3; + unsigned char T7VEN:1; + unsigned char T6ACOR:3; + unsigned char T6AEN:1; + } BIT; + } TITCR1B; + union + { + unsigned char BYTE; + struct + { + unsigned char T7VCNT:3; + unsigned char :1; + unsigned char T6ACNT:3; + unsigned char :1; + } BIT; + } TITCNT1B; + union + { + unsigned char BYTE; + struct + { + unsigned char BTE:2; + unsigned char :6; + } BIT; + } TBTERB; + char wk16[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TDER:1; + unsigned char :7; + } BIT; + } TDERB; + char wk17[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char OLS1P:1; + unsigned char OLS1N:1; + unsigned char OLS2P:1; + unsigned char OLS2N:1; + unsigned char OLS3P:1; + unsigned char OLS3N:1; + unsigned char :2; + } BIT; + } TOLBRB; + char wk18[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char TITM:1; + unsigned char :7; + } BIT; + } TITMRB; + union + { + unsigned char BYTE; + struct + { + unsigned char TRG7COR:3; + unsigned char :5; + } BIT; + } TITCR2B; + union + { + unsigned char BYTE; + struct + { + unsigned char TRG7CNT:3; + unsigned char :5; + } BIT; + } TITCNT2B; + char wk19[35]; + union + { + unsigned char BYTE; + struct + { + unsigned char WRE:1; + unsigned char SCC:1; + unsigned char :5; + unsigned char CCE:1; + } BIT; + } TWCRB; + char wk20[15]; + union + { + unsigned char BYTE; + struct + { + unsigned char DRS:1; + unsigned char :7; + } BIT; + } TMDR2B; + char wk21[15]; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char CST6:1; + unsigned char CST7:1; + } BIT; + } TSTRB; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char SYNC6:1; + unsigned char SYNC7:1; + } BIT; + } TSYRB; + char wk22[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char RWE:1; + unsigned char :7; + } BIT; + } TRWERB; +}; + +struct st_mtu0 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR0; + char wk0[8]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCSC:2; + unsigned char :2; + } BIT; + } NFCRC; + char wk1[102]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char BFE:1; + unsigned char :1; + } BIT; + } TMDR1; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk2[1]; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk3[16]; + unsigned short TGRE; + unsigned short TGRF; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEE:1; + unsigned char TGIEF:1; + unsigned char :5; + unsigned char TTGE2:1; + } BIT; + } TIER2; + char wk4[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char TTSE:1; + unsigned char :5; + } BIT; + } TBTM; + char wk5[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; +}; + +struct st_mtu1 +{ + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR1; + char wk1[238]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char :4; + } BIT; + } TMDR1; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + char wk2[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char :2; + unsigned char TCFV:1; + unsigned char TCFU:1; + unsigned char :1; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union + { + unsigned char BYTE; + struct + { + unsigned char I1AE:1; + unsigned char I1BE:1; + unsigned char I2AE:1; + unsigned char I2BE:1; + unsigned char :4; + } BIT; + } TICCR; + union + { + unsigned char BYTE; + struct + { + unsigned char LWA:1; + unsigned char PHCKSEL:1; + unsigned char :6; + } BIT; + } TMDR3; + char wk4[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char PCB:2; + unsigned char :3; + } BIT; + } TCR2; + char wk5[11]; + unsigned long TCNTLW; + unsigned long TGRALW; + unsigned long TGRBLW; +}; + +struct st_mtu2 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR2; + char wk0[365]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char :4; + } BIT; + } TMDR1; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char :2; + unsigned char TCFV:1; + unsigned char TCFU:1; + unsigned char :1; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char PCB:2; + unsigned char :3; + } BIT; + } TCR2; +}; + +struct st_mtu3 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR1; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + char wk2[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char TGFC:1; + unsigned char TGFD:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TCFD:1; + } BIT; + } TSR; + char wk7[11]; + union + { + unsigned char BYTE; + struct + { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char :6; + } BIT; + } TBTM; + char wk8[19]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; + char wk9[37]; + unsigned short TGRE; + char wk10[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR3; +}; + +struct st_mtu4 +{ + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR1; + char wk2[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + char wk3[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :1; + unsigned char TTGE2:1; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char TGFC:1; + unsigned char TGFD:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TCFD:1; + } BIT; + } TSR; + char wk8[11]; + union + { + unsigned char BYTE; + struct + { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char :6; + } BIT; + } TBTM; + char wk9[6]; + union + { + unsigned short WORD; + struct + { + unsigned short ITB4VE:1; + unsigned short ITB3AE:1; + unsigned short ITA4VE:1; + unsigned short ITA3AE:1; + unsigned short DT4BE:1; + unsigned short UT4BE:1; + unsigned short DT4AE:1; + unsigned short UT4AE:1; + unsigned short :6; + unsigned short BF:2; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR4; +}; + +struct st_mtu5 +{ + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFUEN:1; + unsigned char NFVEN:1; + unsigned char NFWEN:1; + unsigned char :1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR5; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:2; + unsigned char :6; + } BIT; + } TCRU; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char CKEG:2; + unsigned char :3; + } BIT; + } TCR2U; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORU; + char wk2[9]; + unsigned short TCNTV; + unsigned short TGRV; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:2; + unsigned char :6; + } BIT; + } TCRV; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char CKEG:2; + unsigned char :3; + } BIT; + } TCR2V; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORV; + char wk3[9]; + unsigned short TCNTW; + unsigned short TGRW; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:2; + unsigned char :6; + } BIT; + } TCRW; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char CKEG:2; + unsigned char :3; + } BIT; + } TCR2W; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:5; + unsigned char :3; + } BIT; + } TIORW; + char wk4[11]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIE5W:1; + unsigned char TGIE5V:1; + unsigned char TGIE5U:1; + unsigned char :5; + } BIT; + } TIER; + char wk5[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char CSTW5:1; + unsigned char CSTV5:1; + unsigned char CSTU5:1; + unsigned char :5; + } BIT; + } TSTR; + char wk6[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char CMPCLR5W:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5U:1; + unsigned char :5; + } BIT; + } TCNTCMPCLR; +}; + +struct st_mtu6 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR1; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + char wk2[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char TGFC:1; + unsigned char TGFD:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TCFD:1; + } BIT; + } TSR; + char wk7[11]; + union + { + unsigned char BYTE; + struct + { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char :6; + } BIT; + } TBTM; + char wk8[19]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; + char wk9[3]; + union + { + unsigned char BYTE; + struct + { + unsigned char CE2B:1; + unsigned char CE2A:1; + unsigned char CE1B:1; + unsigned char CE1A:1; + unsigned char CE0D:1; + unsigned char CE0C:1; + unsigned char CE0B:1; + unsigned char CE0A:1; + } BIT; + } TSYCR; + char wk10[33]; + unsigned short TGRE; + char wk11[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR6; +}; + +struct st_mtu7 +{ + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR1; + char wk2[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + char wk3[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :1; + unsigned char TTGE2:1; + unsigned char TTGE:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char TGFC:1; + unsigned char TGFD:1; + unsigned char TCFV:1; + unsigned char :2; + unsigned char TCFD:1; + } BIT; + } TSR; + char wk8[11]; + union + { + unsigned char BYTE; + struct + { + unsigned char TTSA:1; + unsigned char TTSB:1; + unsigned char :6; + } BIT; + } TBTM; + char wk9[6]; + union + { + unsigned short WORD; + struct + { + unsigned short ITB7VE:1; + unsigned short ITB6AE:1; + unsigned short ITA7VE:1; + unsigned short ITA6AE:1; + unsigned short DT7BE:1; + unsigned short UT7BE:1; + unsigned short DT7AE:1; + unsigned short UT7AE:1; + unsigned short :6; + unsigned short BF:2; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; + char wk12[38]; + unsigned short TGRE; + unsigned short TGRF; + char wk13[28]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR7; +}; + +struct st_mtu8 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR8; + char wk0[871]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char :2; + } BIT; + } TMDR1; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char :3; + } BIT; + } TIER; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC2:3; + unsigned char :5; + } BIT; + } TCR2; + char wk2[1]; + unsigned long TCNT; + unsigned long TGRA; + unsigned long TGRB; + unsigned long TGRC; + unsigned long TGRD; +}; + +struct st_poe +{ + union + { + unsigned short WORD; + struct + { + unsigned short POE0M:2; + unsigned short :6; + unsigned short PIE1:1; + unsigned short :3; + unsigned short POE0F:1; + unsigned short :3; + } BIT; + } ICSR1; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short OIE1:1; + unsigned short OCE1:1; + unsigned short :5; + unsigned short OSF1:1; + } BIT; + } OCSR1; + union + { + unsigned short WORD; + struct + { + unsigned short POE4M:2; + unsigned short :6; + unsigned short PIE2:1; + unsigned short :3; + unsigned short POE4F:1; + unsigned short :3; + } BIT; + } ICSR2; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short OIE2:1; + unsigned short OCE2:1; + unsigned short :5; + unsigned short OSF2:1; + } BIT; + } OCSR2; + union + { + unsigned short WORD; + struct + { + unsigned short POE8M:2; + unsigned short :6; + unsigned short PIE3:1; + unsigned short POE8E:1; + unsigned short :2; + unsigned short POE8F:1; + unsigned short :3; + } BIT; + } ICSR3; + union + { + unsigned char BYTE; + struct + { + unsigned char MTUCH34HIZ:1; + unsigned char MTUCH67HIZ:1; + unsigned char MTUCH0HIZ:1; + unsigned char :1; + unsigned char GPT3HIZ:1; + unsigned char :3; + } BIT; + } SPOER; + union + { + unsigned char BYTE; + struct + { + unsigned char MTU0AZE:1; + unsigned char MTU0BZE:1; + unsigned char MTU0CZE:1; + unsigned char MTU0DZE:1; + unsigned char :4; + } BIT; + } POECR1; + union + { + unsigned short WORD; + struct + { + unsigned short MTU7BDZE:1; + unsigned short MTU7ACZE:1; + unsigned short MTU6BDZE:1; + unsigned short :5; + unsigned short MTU4BDZE:1; + unsigned short MTU4ACZE:1; + unsigned short MTU3BDZE:1; + unsigned short :5; + } BIT; + } POECR2; + union + { + unsigned short WORD; + struct + { + unsigned short :9; + unsigned short GPT3ABZE:1; + unsigned short :6; + } BIT; + } POECR3; + union + { + unsigned short WORD; + struct + { + unsigned short :2; + unsigned short IC2ADDMT34ZE:1; + unsigned short IC3ADDMT34ZE:1; + unsigned short IC4ADDMT34ZE:1; + unsigned short IC5ADDMT34ZE:1; + unsigned short :3; + unsigned short IC1ADDMT67ZE:1; + unsigned short :1; + unsigned short IC3ADDMT67ZE:1; + unsigned short IC4ADDMT67ZE:1; + unsigned short IC5ADDMT67ZE:1; + unsigned short :2; + } BIT; + } POECR4; + union + { + unsigned short WORD; + struct + { + unsigned short :1; + unsigned short IC1ADDMT0ZE:1; + unsigned short IC2ADDMT0ZE:1; + unsigned short :1; + unsigned short IC4ADDMT0ZE:1; + unsigned short IC5ADDMT0ZE:1; + unsigned short :10; + } BIT; + } POECR5; + union + { + unsigned short WORD; + struct + { + unsigned short :9; + unsigned short IC1ADDGPT3ZE:1; + unsigned short IC2ADDGPT3ZE:1; + unsigned short IC3ADDGPT3ZE:1; + unsigned short IC4ADDGPT3ZE:1; + unsigned short :3; + } BIT; + } POECR6; + union + { + unsigned short WORD; + struct + { + unsigned short POE10M:2; + unsigned short :6; + unsigned short PIE4:1; + unsigned short POE10E:1; + unsigned short :2; + unsigned short POE10F:1; + unsigned short :3; + } BIT; + } ICSR4; + union + { + unsigned short WORD; + struct + { + unsigned short POE10M:2; + unsigned short :6; + unsigned short PIE5:1; + unsigned short POE10E:1; + unsigned short :2; + unsigned short POE10F:1; + unsigned short :3; + } BIT; + } ICSR5; + union + { + unsigned short WORD; + struct + { + unsigned short OLSG0A:1; + unsigned short OLSG0B:1; + unsigned short OLSG1A:1; + unsigned short OLSG1B:1; + unsigned short OLSG2A:1; + unsigned short OLSG2B:1; + unsigned short :1; + unsigned short OLSEN:1; + unsigned short :8; + } BIT; + } ALR1; + union + { + unsigned short WORD; + struct + { + unsigned short :9; + unsigned short OSTSTE:1; + unsigned short :2; + unsigned short OSTSTF:1; + unsigned short :3; + } BIT; + } ICSR6; + char wk0[5]; + union + { + unsigned char BYTE; + struct + { + unsigned char G3ASEL:4; + unsigned char G3BSEL:4; + } BIT; + } G3SELR; + union + { + unsigned char BYTE; + struct + { + unsigned char M0ASEL:4; + unsigned char M0BSEL:4; + } BIT; + } M0SELR1; + union + { + unsigned char BYTE; + struct + { + unsigned char M0CSEL:4; + unsigned char M0DSEL:4; + } BIT; + } M0SELR2; + union + { + unsigned char BYTE; + struct + { + unsigned char M3BSEL:4; + unsigned char M3DSEL:4; + } BIT; + } M3SELR; + union + { + unsigned char BYTE; + struct + { + unsigned char M4ASEL:4; + unsigned char M4CSEL:4; + } BIT; + } M4SELR1; + union + { + unsigned char BYTE; + struct + { + unsigned char M4BSEL:4; + unsigned char M4DSEL:4; + } BIT; + } M4SELR2; +}; + +struct st_port0 +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[62]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[127]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_port1 +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[61]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[128]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; + char wk4[62]; + union + { + unsigned short WORD; + struct + { + unsigned char H; + unsigned char L; + } BYTE; + struct + { + unsigned char B0:1; + unsigned char :8; + unsigned char :7; + } BIT; + } DSCR; +}; + +struct st_port2 +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[60]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[129]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_port3 +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[59]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[130]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_port4 +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[58]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[131]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_port5 +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[57]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[132]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_port6 +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[56]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[133]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_port7 +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[55]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[134]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_port8 +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[54]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[135]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_port9 +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[53]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[136]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_porta +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[52]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[137]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portb +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[51]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[138]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portc +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[50]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; +}; + +struct st_portd +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[49]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[140]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_porte +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[48]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[141]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portf +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[47]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[142]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portg +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[46]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[143]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_porth +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[45]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[144]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portj +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[44]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[145]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portk +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[43]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[146]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portl +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[42]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[147]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portm +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[41]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[148]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portn +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[40]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[149]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portp +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[39]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[150]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portr +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[38]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[151]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_ports +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[37]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[152]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portt +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[36]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[153]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_portu +{ + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PDR; + char wk0[35]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PODR; + char wk1[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PIDR; + char wk2[31]; + union + { + unsigned char BYTE; + struct + { + unsigned char B0:1; + unsigned char B1:1; + unsigned char B2:1; + unsigned char B3:1; + unsigned char B4:1; + unsigned char B5:1; + unsigned char B6:1; + unsigned char B7:1; + } BIT; + } PMR; + char wk3[154]; + union + { + unsigned short WORD; + struct + { + unsigned short B0:2; + unsigned short B1:2; + unsigned short B2:2; + unsigned short B3:2; + unsigned short B4:2; + unsigned short B5:2; + unsigned short B6:2; + unsigned short B7:2; + } BIT; + } PCR; +}; + +struct st_ppg0 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char G0CMS:2; + unsigned char G1CMS:2; + unsigned char G2CMS:2; + unsigned char G3CMS:2; + } BIT; + } PCR; + union + { + unsigned char BYTE; + struct + { + unsigned char G0NOV:1; + unsigned char G1NOV:1; + unsigned char G2NOV:1; + unsigned char G3NOV:1; + unsigned char G0INV:1; + unsigned char G1INV:1; + unsigned char G2INV:1; + unsigned char G3INV:1; + } BIT; + } PMR; + union + { + unsigned char BYTE; + struct + { + unsigned char NDER8:1; + unsigned char NDER9:1; + unsigned char NDER10:1; + unsigned char NDER11:1; + unsigned char NDER12:1; + unsigned char NDER13:1; + unsigned char NDER14:1; + unsigned char NDER15:1; + } BIT; + } NDERH; + union + { + unsigned char BYTE; + struct + { + unsigned char NDER0:1; + unsigned char NDER1:1; + unsigned char NDER2:1; + unsigned char NDER3:1; + unsigned char NDER4:1; + unsigned char NDER5:1; + unsigned char NDER6:1; + unsigned char NDER7:1; + } BIT; + } NDERL; + union + { + unsigned char BYTE; + struct + { + unsigned char POD8:1; + unsigned char POD9:1; + unsigned char POD10:1; + unsigned char POD11:1; + unsigned char POD12:1; + unsigned char POD13:1; + unsigned char POD14:1; + unsigned char POD15:1; + } BIT; + } PODRH; + union + { + unsigned char BYTE; + struct + { + unsigned char POD0:1; + unsigned char POD1:1; + unsigned char POD2:1; + unsigned char POD3:1; + unsigned char POD4:1; + unsigned char POD5:1; + unsigned char POD6:1; + unsigned char POD7:1; + } BIT; + } PODRL; + union + { + unsigned char BYTE; + struct + { + unsigned char NDR8:1; + unsigned char NDR9:1; + unsigned char NDR10:1; + unsigned char NDR11:1; + unsigned char NDR12:1; + unsigned char NDR13:1; + unsigned char NDR14:1; + unsigned char NDR15:1; + } BIT; + } NDRH; + union + { + unsigned char BYTE; + struct + { + unsigned char NDR0:1; + unsigned char NDR1:1; + unsigned char NDR2:1; + unsigned char NDR3:1; + unsigned char NDR4:1; + unsigned char NDR5:1; + unsigned char NDR6:1; + unsigned char NDR7:1; + } BIT; + } NDRL; + union + { + unsigned char BYTE; + struct + { + unsigned char NDR8:1; + unsigned char NDR9:1; + unsigned char NDR10:1; + unsigned char NDR11:1; + unsigned char NDR12:1; + unsigned char NDR13:1; + unsigned char NDR14:1; + unsigned char NDR15:1; + } BIT; + } NDRH2; + union + { + unsigned char BYTE; + struct + { + unsigned char NDR0:1; + unsigned char NDR1:1; + unsigned char NDR2:1; + unsigned char NDR3:1; + unsigned char NDR4:1; + unsigned char NDR5:1; + unsigned char NDR6:1; + unsigned char NDR7:1; + } BIT; + } NDRL2; +}; + +struct st_ppg1 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char G0CMS:2; + unsigned char G1CMS:2; + unsigned char G2CMS:2; + unsigned char G3CMS:2; + } BIT; + } PCR; + union + { + unsigned char BYTE; + struct + { + unsigned char G0NOV:1; + unsigned char G1NOV:1; + unsigned char G2NOV:1; + unsigned char G3NOV:1; + unsigned char G0INV:1; + unsigned char G1INV:1; + unsigned char G2INV:1; + unsigned char G3INV:1; + } BIT; + } PMR; + union + { + unsigned char BYTE; + struct + { + unsigned char NDER8:1; + unsigned char NDER9:1; + unsigned char NDER10:1; + unsigned char NDER11:1; + unsigned char NDER12:1; + unsigned char NDER13:1; + unsigned char NDER14:1; + unsigned char NDER15:1; + } BIT; + } NDERH; + union + { + unsigned char BYTE; + struct + { + unsigned char NDER0:1; + unsigned char NDER1:1; + unsigned char NDER2:1; + unsigned char NDER3:1; + unsigned char NDER4:1; + unsigned char NDER5:1; + unsigned char NDER6:1; + unsigned char NDER7:1; + } BIT; + } NDERL; + union + { + unsigned char BYTE; + struct + { + unsigned char POD8:1; + unsigned char POD9:1; + unsigned char POD10:1; + unsigned char POD11:1; + unsigned char POD12:1; + unsigned char POD13:1; + unsigned char POD14:1; + unsigned char POD15:1; + } BIT; + } PODRH; + union + { + unsigned char BYTE; + struct + { + unsigned char POD0:1; + unsigned char POD1:1; + unsigned char POD2:1; + unsigned char POD3:1; + unsigned char POD4:1; + unsigned char POD5:1; + unsigned char POD6:1; + unsigned char POD7:1; + } BIT; + } PODRL; + union + { + unsigned char BYTE; + struct + { + unsigned char NDR8:1; + unsigned char NDR9:1; + unsigned char NDR10:1; + unsigned char NDR11:1; + unsigned char NDR12:1; + unsigned char NDR13:1; + unsigned char NDR14:1; + unsigned char NDR15:1; + } BIT; + } NDRH; + union + { + unsigned char BYTE; + struct + { + unsigned char NDR0:1; + unsigned char NDR1:1; + unsigned char NDR2:1; + unsigned char NDR3:1; + unsigned char NDR4:1; + unsigned char NDR5:1; + unsigned char NDR6:1; + unsigned char NDR7:1; + } BIT; + } NDRL; + union + { + unsigned char BYTE; + struct + { + unsigned char NDR8:1; + unsigned char NDR9:1; + unsigned char NDR10:1; + unsigned char NDR11:1; + unsigned char NDR12:1; + unsigned char NDR13:1; + unsigned char NDR14:1; + unsigned char NDR15:1; + } BIT; + } NDRH2; + union + { + unsigned char BYTE; + struct + { + unsigned char NDR0:1; + unsigned char NDR1:1; + unsigned char NDR2:1; + unsigned char NDR3:1; + unsigned char NDR4:1; + unsigned char NDR5:1; + unsigned char NDR6:1; + unsigned char NDR7:1; + } BIT; + } NDRL2; + union + { + unsigned char BYTE; + struct + { + unsigned char PTRSL:1; + unsigned char :7; + } BIT; + } PTRSLR; +}; + +struct st_riic +{ + union + { + unsigned char BYTE; + struct + { + unsigned char SDAI:1; + unsigned char SCLI:1; + unsigned char SDAO:1; + unsigned char SCLO:1; + unsigned char SOWP:1; + unsigned char CLO:1; + unsigned char IICRST:1; + unsigned char ICE:1; + } BIT; + } ICCR1; + union + { + unsigned char BYTE; + struct + { + unsigned char :1; + unsigned char ST:1; + unsigned char RS:1; + unsigned char SP:1; + unsigned char :1; + unsigned char TRS:1; + unsigned char MST:1; + unsigned char BBSY:1; + } BIT; + } ICCR2; + union + { + unsigned char BYTE; + struct + { + unsigned char BC:3; + unsigned char BCWP:1; + unsigned char CKS:3; + unsigned char MTWP:1; + } BIT; + } ICMR1; + union + { + unsigned char BYTE; + struct + { + unsigned char TMOS:1; + unsigned char TMOL:1; + unsigned char TMOH:1; + unsigned char :1; + unsigned char SDDL:3; + unsigned char DLCS:1; + } BIT; + } ICMR2; + union + { + unsigned char BYTE; + struct + { + unsigned char NF:2; + unsigned char ACKBR:1; + unsigned char ACKBT:1; + unsigned char ACKWP:1; + unsigned char RDRFS:1; + unsigned char WAIT:1; + unsigned char :1; + } BIT; + } ICMR3; + union + { + unsigned char BYTE; + struct + { + unsigned char TMOE:1; + unsigned char MALE:1; + unsigned char NALE:1; + unsigned char SALE:1; + unsigned char NACKE:1; + unsigned char NFE:1; + unsigned char SCLE:1; + unsigned char :1; + } BIT; + } ICFER; + union + { + unsigned char BYTE; + struct + { + unsigned char SAR0E:1; + unsigned char SAR1E:1; + unsigned char SAR2E:1; + unsigned char GCAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :2; + } BIT; + } ICSER; + union + { + unsigned char BYTE; + struct + { + unsigned char TMOIE:1; + unsigned char ALIE:1; + unsigned char STIE:1; + unsigned char SPIE:1; + unsigned char NAKIE:1; + unsigned char RIE:1; + unsigned char TEIE:1; + unsigned char TIE:1; + } BIT; + } ICIER; + union + { + unsigned char BYTE; + struct + { + unsigned char AAS0:1; + unsigned char AAS1:1; + unsigned char AAS2:1; + unsigned char GCA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :2; + } BIT; + } ICSR1; + union + { + unsigned char BYTE; + struct + { + unsigned char TMOF:1; + unsigned char AL:1; + unsigned char START:1; + unsigned char STOP:1; + unsigned char NACKF:1; + unsigned char RDRF:1; + unsigned char TEND:1; + unsigned char TDRE:1; + } BIT; + } ICSR2; + union + { + unsigned char BYTE; + struct + { + unsigned char SVA0:1; + unsigned char SVA:7; + } BIT; + } ICSARL0; + union + { + unsigned char BYTE; + struct + { + unsigned char FS:1; + unsigned char SVA:2; + unsigned char :5; + } BIT; + } ICSARU0; + union + { + unsigned char BYTE; + struct + { + unsigned char SVA0:1; + unsigned char SVA:7; + } BIT; + } ICSARL1; + union + { + unsigned char BYTE; + struct + { + unsigned char FS:1; + unsigned char SVA:2; + unsigned char :5; + } BIT; + } ICSARU1; + union + { + unsigned char BYTE; + struct + { + unsigned char SVA0:1; + unsigned char SVA:7; + } BIT; + } ICSARL2; + union + { + unsigned char BYTE; + struct + { + unsigned char FS:1; + unsigned char SVA:2; + unsigned char :5; + } BIT; + } ICSARU2; + union + { + unsigned char BYTE; + struct + { + unsigned char BRL:5; + unsigned char :3; + } BIT; + } ICBRL; + union + { + unsigned char BYTE; + struct + { + unsigned char BRH:5; + unsigned char :3; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rscan +{ + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long BRP:10; + unsigned long :6; + unsigned long TSEG1:4; + unsigned long TSEG2:3; + unsigned long :1; + unsigned long SJW:2; + unsigned long :6; + } BIT; + } RSCAN0C0CFG; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CHMDC:2; + unsigned char CSLPR:1; + unsigned char RTBO:1; + unsigned char :4; + unsigned char BEIE:1; + unsigned char EWIE:1; + unsigned char EPIE:1; + unsigned char BOEIE:1; + unsigned char BORIE:1; + unsigned char OLIE:1; + unsigned char BLIE:1; + unsigned char ALIE:1; + unsigned char TAIE:1; + unsigned char :4; + unsigned char BOM:2; + unsigned char ERRD:1; + unsigned char CTME:1; + unsigned char CTMS:2; + unsigned char :5; + } BIT; + } RSCAN0C0CTR; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CRSTSTS:1; + unsigned char CHLTSTS:1; + unsigned char CSLPSTS:1; + unsigned char EPSTS:1; + unsigned char BOSTS:1; + unsigned char TRMSTS:1; + unsigned char RECSTS:1; + unsigned char COMSTS:1; + unsigned char :8; + unsigned char REC:8; + unsigned char TEC:8; + } BIT; + } RSCAN0C0STS; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long BEF:1; + unsigned long EWF:1; + unsigned long EPF:1; + unsigned long BOEF:1; + unsigned long BORF:1; + unsigned long OVLF:1; + unsigned long BLF:1; + unsigned long ALF:1; + unsigned long SERR:1; + unsigned long FERR:1; + unsigned long AERR:1; + unsigned long CERR:1; + unsigned long B1ERR:1; + unsigned long B0ERR:1; + unsigned long ADERR:1; + unsigned long :1; + unsigned long CRCREG:15; + unsigned long :1; + } BIT; + } RSCAN0C0ERFL; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long BRP:10; + unsigned long :6; + unsigned long TSEG1:4; + unsigned long TSEG2:3; + unsigned long :1; + unsigned long SJW:2; + unsigned long :6; + } BIT; + } RSCAN0C1CFG; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CHMDC:2; + unsigned char CSLPR:1; + unsigned char RTBO:1; + unsigned char :4; + unsigned char BEIE:1; + unsigned char EWIE:1; + unsigned char EPIE:1; + unsigned char BOEIE:1; + unsigned char BORIE:1; + unsigned char OLIE:1; + unsigned char BLIE:1; + unsigned char ALIE:1; + unsigned char TAIE:1; + unsigned char :4; + unsigned char BOM:2; + unsigned char ERRD:1; + unsigned char CTME:1; + unsigned char CTMS:2; + unsigned char :5; + } BIT; + } RSCAN0C1CTR; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CRSTSTS:1; + unsigned char CHLTSTS:1; + unsigned char CSLPSTS:1; + unsigned char EPSTS:1; + unsigned char BOSTS:1; + unsigned char TRMSTS:1; + unsigned char RECSTS:1; + unsigned char COMSTS:1; + unsigned char :8; + unsigned char REC:8; + unsigned char TEC:8; + } BIT; + } RSCAN0C1STS; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long BEF:1; + unsigned long EWF:1; + unsigned long EPF:1; + unsigned long BOEF:1; + unsigned long BORF:1; + unsigned long OVLF:1; + unsigned long BLF:1; + unsigned long ALF:1; + unsigned long SERR:1; + unsigned long FERR:1; + unsigned long AERR:1; + unsigned long CERR:1; + unsigned long B1ERR:1; + unsigned long B0ERR:1; + unsigned long ADERR:1; + unsigned long :1; + unsigned long CRCREG:15; + unsigned long :1; + } BIT; + } RSCAN0C1ERFL; + char wk0[100]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TPRI:1; + unsigned long DCE:1; + unsigned long DRE:1; + unsigned long MME:1; + unsigned long DCS:1; + unsigned long :3; + unsigned long TSP:4; + unsigned long TSSS:1; + unsigned long TSBTCS:3; + unsigned long ITRCP:16; + } BIT; + } RSCAN0GCFG; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char GMDC:2; + unsigned char GSLPR:1; + unsigned char :5; + unsigned char DEIE:1; + unsigned char MEIE:1; + unsigned char THLEIE:1; + unsigned char :5; + unsigned char TSRST:1; + unsigned char :7; + unsigned char :8; + } BIT; + } RSCAN0GCTR; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char GRSTSTS:1; + unsigned char GHLTSTS:1; + unsigned char GSLPSTS:1; + unsigned char GRAMINIT:1; + unsigned char :4; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GSTS; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char DEF:1; + unsigned char MES:1; + unsigned char THLES:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GERFL; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned long TS:16; + unsigned long :16; + } BIT; + } RSCAN0GTSC; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char AFLPN:5; + unsigned char :3; + unsigned char AFLDAE:1; + unsigned char :7; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GAFLECTR; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char RNC1:8; + unsigned char RNC0:8; + } BIT; + } RSCAN0GAFLCFG0; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char NRXMB:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RMNB; + union + { + unsigned long LONG; + struct + { + unsigned short RMNSq_l; + unsigned short RMNSq_h; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + } RSCAN0RMND0; + char wk2[12]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFE:1; + unsigned char RFIE:1; + unsigned char :6; + unsigned char RFDC:3; + unsigned char :1; + unsigned char RFIM:1; + unsigned char RFIGCV:3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFCC7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFEMP:1; + unsigned char RFFLL:1; + unsigned char RFMLT:1; + unsigned char RFIF:1; + unsigned char :4; + unsigned char RFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFSTS7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFPCTR7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFE:1; + unsigned char CFRXIE:1; + unsigned char CFTXIE:1; + unsigned char :5; + unsigned char CFDC:3; + unsigned char :1; + unsigned char CFIM:1; + unsigned char CFIGCV:3; + unsigned char CFM:2; + unsigned char CFITSS:1; + unsigned char CFITR:1; + unsigned char CFTML:4; + unsigned char CFITT:8; + } BIT; + } RSCAN0CFCC5; + char wk3[72]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFEMP:1; + unsigned char CFFLL:1; + unsigned char CFMLT:1; + unsigned char CFRXIF:1; + unsigned char CFTXIF:1; + unsigned char :3; + unsigned char CFMC:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFSTS5; + char wk4[72]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CFPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFPCTR5; + char wk5[72]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RF0EMP:1; + unsigned char RF1EMP:1; + unsigned char RF2EMP:1; + unsigned char RF3EMP:1; + unsigned char RF4EMP:1; + unsigned char RF5EMP:1; + unsigned char RF6EMP:1; + unsigned char RF7EMP:1; + unsigned char CF0EMP:1; + unsigned char CF1EMP:1; + unsigned char CF2EMP:1; + unsigned char CF3EMP:1; + unsigned char CF4EMP:1; + unsigned char CF5EMP:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0FESTS; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RF0FLL:1; + unsigned char RF1FLL:1; + unsigned char RF2FLL:1; + unsigned char RF3FLL:1; + unsigned char RF4FLL:1; + unsigned char RF5FLL:1; + unsigned char RF6FLL:1; + unsigned char RF7FLL:1; + unsigned char CF0FLL:1; + unsigned char CF1FLL:1; + unsigned char CF2FLL:1; + unsigned char CF3FLL:1; + unsigned char CF4FLL:1; + unsigned char CF5FLL:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0FFSTS; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RF0MLT:1; + unsigned char RF1MLT:1; + unsigned char RF2MLT:1; + unsigned char RF3MLT:1; + unsigned char RF4MLT:1; + unsigned char RF5MLT:1; + unsigned char RF6MLT:1; + unsigned char RF7MLT:1; + unsigned char CF0MLT:1; + unsigned char CF1MLT:1; + unsigned char CF2MLT:1; + unsigned char CF3MLT:1; + unsigned char CF4MLT:1; + unsigned char CF5MLT:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0FMSTS; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char RF0IF:1; + unsigned char RF1IF:1; + unsigned char RF2IF:1; + unsigned char RF3IF:1; + unsigned char RF4IF:1; + unsigned char RF5IF:1; + unsigned char RF6IF:1; + unsigned char RF7IF:1; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0RFISTS; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CF0RXIF:1; + unsigned char CF1RXIF:1; + unsigned char CF2RXIF:1; + unsigned char CF3RXIF:1; + unsigned char CF4RXIF:1; + unsigned char CF5RXIF:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFRISTS; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char CF0TXIF:1; + unsigned char CF1TXIF:1; + unsigned char CF2TXIF:1; + unsigned char CF3TXIF:1; + unsigned char CF4TXIF:1; + unsigned char CF5TXIF:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0CFTISTS; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC0; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC1; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC2; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC3; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC4; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC5; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC6; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC7; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC8; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC9; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC10; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC11; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC12; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC13; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC14; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC15; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC16; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC17; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC18; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC19; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC20; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC21; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC22; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC23; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC24; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC25; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC26; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC27; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC28; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC29; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC30; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTR:1; + unsigned char TMTAR:1; + unsigned char TMOM:1; + unsigned char :5; + } BIT; + } RSCAN0TMC31; + char wk6[96]; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS0; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS1; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS2; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS3; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS4; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS5; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS6; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS7; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS8; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS9; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS10; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS11; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS12; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS13; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS14; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS15; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS16; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS17; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS18; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS19; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS20; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS21; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS22; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS23; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS24; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS25; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS26; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS27; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS28; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS29; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS30; + union + { + unsigned char BYTE; + struct + { + unsigned char TMTSTS:1; + unsigned char TMTRF:2; + unsigned char TMTRM:1; + unsigned char TMTARM:1; + unsigned char :3; + } BIT; + } RSCAN0TMSTS31; + char wk7[96]; + union + { + unsigned long LONG; + struct + { + unsigned short TMTRSTSp_l; + unsigned short TMTRSTSp_h; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + } RSCAN0TMTRSTS0; + char wk8[12]; + union + { + unsigned long LONG; + struct + { + unsigned short TMTARSTSp_l; + unsigned short TMTARSTSp_h; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + } RSCAN0TMTARSTS0; + char wk9[12]; + union + { + unsigned long LONG; + struct + { + unsigned short TMTCSTSp_l; + unsigned short TMTCSTSp_h; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + } RSCAN0TMTCSTS0; + char wk10[12]; + union + { + unsigned long LONG; + struct + { + unsigned short TMTASTSp_l; + unsigned short TMTASTSp_h; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + } RSCAN0TMTASTS0; + char wk11[12]; + union + { + unsigned long LONG; + struct + { + unsigned short TMIEp_l; + unsigned short TMIEp_h; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + } RSCAN0TMIEC0; + char wk12[12]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char TXQE:1; + unsigned char :7; + unsigned char TXQDC:4; + unsigned char TXQIE:1; + unsigned char TXQIM:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQCC0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char TXQE:1; + unsigned char :7; + unsigned char TXQDC:4; + unsigned char TXQIE:1; + unsigned char TXQIM:1; + unsigned char :2; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQCC1; + char wk13[24]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char TXQEMP:1; + unsigned char TXQFLL:1; + unsigned char TXQIF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char TXQEMP:1; + unsigned char TXQFLL:1; + unsigned char TXQIF:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQSTS1; + char wk14[24]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char TXQPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char TXQPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0TXQPCTR1; + char wk15[24]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char THLE:1; + unsigned char :7; + unsigned char THLIE:1; + unsigned char THLIM:1; + unsigned char THLDTE:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLCC0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char THLE:1; + unsigned char :7; + unsigned char THLIE:1; + unsigned char THLIM:1; + unsigned char THLDTE:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLCC1; + char wk16[24]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char THLEMP:1; + unsigned char THLFLL:1; + unsigned char THLELT:1; + unsigned char THLIF:1; + unsigned char :4; + unsigned char THLMC:5; + unsigned char :3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLSTS0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char THLEMP:1; + unsigned char THLFLL:1; + unsigned char THLELT:1; + unsigned char THLIF:1; + unsigned char :4; + unsigned char THLMC:5; + unsigned char :3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLSTS1; + char wk17[24]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char THLPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLPCTR0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char THLPC:8; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLPCTR1; + char wk18[24]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char TSIF0:1; + unsigned char TAIF0:1; + unsigned char TQIF0:1; + unsigned char CFTIF0:1; + unsigned char THIF0:1; + unsigned char :3; + unsigned char TSIF1:1; + unsigned char TAIF1:1; + unsigned char TQIF1:1; + unsigned char CFTIF1:1; + unsigned char THIF1:1; + unsigned char :3; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GTINTSTS0; + char wk19[4]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char C0ICBCE:1; + unsigned char C1ICBCE:1; + unsigned char :6; + unsigned char :8; + unsigned char RTMPS:7; + unsigned char :1; + unsigned char :8; + } BIT; + } RSCAN0GTSTCFG; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char ICBCTME:1; + unsigned char :1; + unsigned char RTME:1; + unsigned char :5; + unsigned char :8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0GTSTCTR; + char wk20[12]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + } RSCAN0GLOCKK; + char wk21[128]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP00; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP01; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP02; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP03; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP04; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP05; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP15; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP06; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP16; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP07; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP17; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID8; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM8; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP08; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP18; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID9; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM9; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP09; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP19; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP010; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP110; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP011; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP111; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP012; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP112; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP013; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP113; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP014; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP114; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLID:29; + unsigned long GAFLLB:1; + unsigned long GAFLRTR:1; + unsigned long GAFLIDE:1; + } BIT; + } RSCAN0GAFLID15; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLIDM:29; + unsigned long :1; + unsigned long GAFLRTRM:1; + unsigned long GAFLIDEM:1; + } BIT; + } RSCAN0GAFLM15; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long :8; + unsigned long GAFLRMDP:7; + unsigned long GAFLRMV:1; + unsigned long GAFLPTR:12; + unsigned long GAFLDLC:4; + } BIT; + } RSCAN0GAFLP015; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long GAFLFDPr:8; + unsigned long GAFLFDP:18; + unsigned long :6; + } BIT; + } RSCAN0GAFLP115; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF00; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF01; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF02; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF03; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF04; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF05; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF15; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF06; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF16; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF07; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF17; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID8; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR8; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF08; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF18; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID9; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR9; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF09; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF19; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF010; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF110; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF011; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF111; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF012; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF112; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF013; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF113; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF014; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF114; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID15; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR15; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF015; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF115; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID16; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR16; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF016; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF116; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID17; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR17; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF017; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF117; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID18; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR18; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF018; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF118; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID19; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR19; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF019; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF119; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID20; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR20; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF020; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF120; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID21; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR21; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF021; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF121; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID22; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR22; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF022; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF122; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID23; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR23; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF023; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF123; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID24; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR24; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF024; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF124; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID25; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR25; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF025; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF125; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID26; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR26; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF026; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF126; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID27; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR27; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF027; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF127; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID28; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR28; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF028; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF128; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID29; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR29; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF029; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF129; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID30; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR30; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF030; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF130; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMID:29; + unsigned long :1; + unsigned long RMRTR:1; + unsigned long RMIDE:1; + } BIT; + } RSCAN0RMID31; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RMTS:16; + unsigned long RMPTR:12; + unsigned long RMDLC:4; + } BIT; + } RSCAN0RMPTR31; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB0; + unsigned char RMDB1; + unsigned char RMDB2; + unsigned char RMDB3; + } BYTE; + } RSCAN0RMDF031; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RMDB4; + unsigned char RMDB5; + unsigned char RMDB6; + unsigned char RMDB7; + } BYTE; + } RSCAN0RMDF131; + char wk22[1536]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF00; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF01; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF02; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF03; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF04; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF05; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF15; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF06; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF16; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFID:29; + unsigned long :1; + unsigned long RFRTR:1; + unsigned long RFIDE:1; + } BIT; + } RSCAN0RFID7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RFTS:16; + unsigned long RFPTR:12; + unsigned long RFDLC:4; + } BIT; + } RSCAN0RFPTR7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB0; + unsigned char RFDB1; + unsigned char RFDB2; + unsigned char RFDB3; + } BYTE; + } RSCAN0RFDF07; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char RFDB4; + unsigned char RFDB5; + unsigned char RFDB6; + unsigned char RFDB7; + } BYTE; + } RSCAN0RFDF17; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF00; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF01; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF02; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF03; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF04; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFID:29; + unsigned long THLEN:1; + unsigned long CFRTR:1; + unsigned long CFIDE:1; + } BIT; + } RSCAN0CFID5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long CFTS:16; + unsigned long CFPTR:12; + unsigned long CFDLC:4; + } BIT; + } RSCAN0CFPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB0; + unsigned char CFDB1; + unsigned char CFDB2; + unsigned char CFDB3; + } BYTE; + } RSCAN0CFDF05; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char CFDB4; + unsigned char CFDB5; + unsigned char CFDB6; + unsigned char CFDB7; + } BYTE; + } RSCAN0CFDF15; + char wk23[288]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF00; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF01; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF02; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF03; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF04; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF05; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF15; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF06; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF16; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF07; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF17; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID8; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR8; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF08; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF18; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID9; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR9; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF09; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF19; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF010; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF110; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF011; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF111; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF012; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF112; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF013; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF113; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF014; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF114; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID15; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR15; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF015; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF115; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID16; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR16; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF016; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF116; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID17; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR17; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF017; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF117; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID18; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR18; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF018; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF118; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID19; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR19; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF019; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF119; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID20; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR20; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF020; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF120; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID21; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR21; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF021; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF121; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID22; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR22; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF022; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF122; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID23; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR23; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF023; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF123; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID24; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR24; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF024; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF124; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID25; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR25; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF025; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF125; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID26; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR26; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF026; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF126; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID27; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR27; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF027; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF127; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID28; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR28; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF028; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF128; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID29; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR29; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF029; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF129; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID30; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR30; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF030; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF130; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long TMID:29; + unsigned long THLEN:1; + unsigned long TMRTR:1; + unsigned long TMIDE:1; + } BIT; + } RSCAN0TMID31; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char :8; + unsigned char :8; + unsigned char TMPTR:8; + unsigned char :4; + unsigned char TMDLC:4; + } BIT; + } RSCAN0TMPTR31; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB0; + unsigned char TMDB1; + unsigned char TMDB2; + unsigned char TMDB3; + } BYTE; + } RSCAN0TMDF031; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char TMDB4; + unsigned char TMDB5; + unsigned char TMDB6; + unsigned char TMDB7; + } BYTE; + } RSCAN0TMDF131; + char wk24[1536]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char BT:3; + unsigned char BN:4; + unsigned char :1; + unsigned char TID:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLACC0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char BT:3; + unsigned char BN:4; + unsigned char :1; + unsigned char TID:8; + unsigned char :8; + unsigned char :8; + } BIT; + } RSCAN0THLACC1; + char wk25[248]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC7; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC8; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC9; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC10; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC11; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC12; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC13; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC14; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC15; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC16; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC17; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC18; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC19; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC20; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC21; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC22; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC23; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC24; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC25; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC26; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC27; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC28; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC29; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC30; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC31; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC32; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC33; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC34; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC35; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC36; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC37; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC38; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC39; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC40; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC41; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC42; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC43; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC44; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC45; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC46; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC47; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC48; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC49; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC50; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC51; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC52; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC53; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC54; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC55; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC56; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC57; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC58; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC59; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC60; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC61; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC62; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDTA:32; + } BIT; + } RSCAN0RPGACC63; + char wk26[5632]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned char ECEMF:1; + unsigned char ECER1F:1; + unsigned char ECER2F:1; + unsigned char EC1EDIC:1; + unsigned char EC2EDIC:1; + unsigned char EC1ECP:1; + unsigned char ECERVF:1; + unsigned char ECTHM:1; + unsigned char :1; + unsigned char ECER1C:1; + unsigned char ECER2C:1; + unsigned char ECOVFF:1; + unsigned char :2; + unsigned char EMCA0:1; + unsigned char EMCA1:1; + unsigned char ECSEDF0:1; + unsigned char ECDEDF0:1; + unsigned char ECSEDF1:1; + unsigned char ECDEDF1:1; + unsigned char ECSEDF2:1; + unsigned char ECDEDF2:1; + unsigned char ECSEDF3:1; + unsigned char ECDEDF3:1; + unsigned char ECSEDF4:1; + unsigned char ECDEDF4:1; + unsigned char ECSEDF5:1; + unsigned char ECDEDF5:1; + unsigned char ECSEDF6:1; + unsigned char ECDEDF6:1; + unsigned char ECSEDF7:1; + unsigned char ECDEDF7:1; + } BIT; + } ECCRCANCTL; + char wk27[12]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long ECEADz:11; + unsigned long :21; + } BIT; + } ECCRCANEAD0; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long ECEADz:11; + unsigned long :21; + } BIT; + } ECCRCANEAD1; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long ECEADz:11; + unsigned long :21; + } BIT; + } ECCRCANEAD2; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long ECEADz:11; + unsigned long :21; + } BIT; + } ECCRCANEAD3; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long ECEADz:11; + unsigned long :21; + } BIT; + } ECCRCANEAD4; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long ECEADz:11; + unsigned long :21; + } BIT; + } ECCRCANEAD5; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long ECEADz:11; + unsigned long :21; + } BIT; + } ECCRCANEAD6; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long ECEADz:11; + unsigned long :21; + } BIT; + } ECCRCANEAD7; +}; + +struct st_rspi +{ + union + { + unsigned char BYTE; + struct + { + unsigned char SPMS:1; + unsigned char TXMD:1; + unsigned char MODFEN:1; + unsigned char MSTR:1; + unsigned char SPEIE:1; + unsigned char SPTIE:1; + unsigned char SPE:1; + unsigned char SPRIE:1; + } BIT; + } SPCR; + union + { + unsigned char BYTE; + struct + { + unsigned char SSL0P:1; + unsigned char SSL1P:1; + unsigned char SSL2P:1; + unsigned char SSL3P:1; + unsigned char :4; + } BIT; + } SSLP; + union + { + unsigned char BYTE; + struct + { + unsigned char SPLP:1; + unsigned char SPLP2:1; + unsigned char SPOM:1; + unsigned char :1; + unsigned char MOIFV:1; + unsigned char MOIFE:1; + unsigned char :2; + } BIT; + } SPPCR; + union + { + unsigned char BYTE; + struct + { + unsigned char OVRF:1; + unsigned char IDLNF:1; + unsigned char MODF:1; + unsigned char PERF:1; + unsigned char :4; + } BIT; + } SPSR; + union + { + unsigned long LONG; + struct + { + unsigned short L; + unsigned short H; + } WORD; + } SPDR; + union + { + unsigned char BYTE; + struct + { + unsigned char SPSLN:3; + unsigned char :5; + } BIT; + } SPSCR; + union + { + unsigned char BYTE; + struct + { + unsigned char SPCP:3; + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + } BIT; + } SPSSR; + unsigned char SPBR; + union + { + unsigned char BYTE; + struct + { + unsigned char SPFC:2; + unsigned char :2; + unsigned char SPRDTD:1; + unsigned char SPLW:1; + unsigned char :2; + } BIT; + } SPDCR; + union + { + unsigned char BYTE; + struct + { + unsigned char SCKDL:3; + unsigned char :5; + } BIT; + } SPCKD; + union + { + unsigned char BYTE; + struct + { + unsigned char SLNDL:3; + unsigned char :5; + } BIT; + } SSLND; + union + { + unsigned char BYTE; + struct + { + unsigned char SPNDL:3; + unsigned char :5; + } BIT; + } SPND; + union + { + unsigned char BYTE; + struct + { + unsigned char SPPE:1; + unsigned char SPOE:1; + unsigned char SPIIE:1; + unsigned char PTE:1; + unsigned char SCKASE:1; + unsigned char :3; + } BIT; + } SPCR2; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLy:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD0; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLy:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD1; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLy:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD2; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLy:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD3; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLy:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD4; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLy:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD5; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLy:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD6; + union + { + unsigned short WORD; + struct + { + unsigned short CPHA:1; + unsigned short CPOL:1; + unsigned short BRDV:2; + unsigned short SSLy:3; + unsigned short SSLKP:1; + unsigned short SPB:4; + unsigned short LSBF:1; + unsigned short SPNDEN:1; + unsigned short SLNDEN:1; + unsigned short SCKDEN:1; + } BIT; + } SPCMD7; +}; + +struct st_s12adc0 +{ + union + { + unsigned short WORD; + struct + { + unsigned short DBLANS:5; + unsigned short :1; + unsigned short GBADIE:1; + unsigned short DBLE:1; + unsigned short EXTRG:1; + unsigned short TRGE:1; + unsigned short :2; + unsigned short ADIE:1; + unsigned short ADCS:2; + unsigned short ADST:1; + } BIT; + } ADCSR; + char wk0[2]; + union + { + unsigned short WORD; + struct + { + unsigned short ANSA:16; + } BIT; + } ADANSA; + char wk1[2]; + union + { + unsigned short WORD; + struct + { + unsigned short ADS:16; + } BIT; + } ADADS; + char wk2[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char ADC:2; + unsigned char :5; + unsigned char AVEE:1; + } BIT; + } ADADC; + char wk3[1]; + union + { + unsigned short WORD; + struct + { + unsigned short :1; + unsigned short ADPRC:2; + unsigned short :2; + unsigned short ACE:1; + unsigned short :2; + unsigned short DIAGVAL:2; + unsigned short DIAGLD:1; + unsigned short DIAGM:1; + unsigned short :3; + unsigned short ADRFMT:1; + } BIT; + } ADCER; + union + { + unsigned short WORD; + struct + { + unsigned short TRSB:6; + unsigned short :2; + unsigned short TRSA:6; + unsigned short :2; + } BIT; + } ADSTRGR; + union + { + unsigned short WORD; + struct + { + unsigned short TSSAD:1; + unsigned short :7; + unsigned short TSSA:1; + unsigned short :1; + unsigned short TSSB:1; + unsigned short :5; + } BIT; + } ADEXICR; + union + { + unsigned short WORD; + struct + { + unsigned short ANSB:16; + } BIT; + } ADANSB; + char wk4[2]; + unsigned short ADDBLDR; + unsigned short ADTSDR; + char wk5[2]; + unsigned short ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk6[48]; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR0; + char wk7[5]; + union + { + unsigned short WORD; + struct + { + unsigned short SSTSH:8; + unsigned short SHANS:4; + unsigned short :4; + } BIT; + } ADSHCR; + char wk8[8]; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTRT; + char wk9[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR1; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR2; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR3; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR4; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR5; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR6; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR7; + union + { + unsigned char BYTE; + struct + { + unsigned char ADNDIS:5; + unsigned char :3; + } BIT; + } ADDISCR; + char wk10[5]; + union + { + unsigned short WORD; + struct + { + unsigned short PGS:1; + unsigned short GBRSCN:1; + unsigned short :13; + unsigned short GBRP:1; + } BIT; + } ADGSPCR; + char wk11[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk12[8]; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char WCMPE:1; + unsigned char CMPIE:1; + } BIT; + } ADCMPCR; + char wk13[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char CMPSTS:1; + unsigned char :7; + } BIT; + } ADCMPANSER; + union + { + unsigned char BYTE; + struct + { + unsigned char CMPLTS:1; + unsigned char :7; + } BIT; + } ADCMPLER; + union + { + unsigned short WORD; + struct + { + unsigned short CMPS:16; + } BIT; + } ADCMPANSR; + char wk14[2]; + union + { + unsigned short WORD; + struct + { + unsigned short CMPL:16; + } BIT; + } ADCMPLR; + char wk15[2]; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union + { + unsigned short WORD; + struct + { + unsigned short CMPF:16; + } BIT; + } ADCMPSR; + char wk16[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char CMPFTS:1; + unsigned char :7; + } BIT; + } ADCMPSER; + char wk17[35]; + union + { + unsigned char BYTE; + struct + { + unsigned char TDLV:2; + unsigned char :5; + unsigned char TDE:1; + } BIT; + } ADTDCR; + char wk18[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char :2; + unsigned char OWEIE:1; + unsigned char :5; + } BIT; + } ADERCR; + union + { + unsigned char BYTE; + struct + { + unsigned char :2; + unsigned char OWEC:1; + unsigned char :5; + } BIT; + } ADERCLR; + char wk19[6]; + union + { + unsigned short WORD; + struct + { + unsigned short OWE:16; + } BIT; + } ADOWER; + char wk20[2]; + union + { + unsigned short WORD; + struct + { + unsigned short DBOWE:1; + unsigned short DAOWE:1; + unsigned short DOWE:1; + unsigned short DIAGOWE:1; + unsigned short TSOWE:1; + unsigned short :11; + } BIT; + } ADOWEER; +}; + +struct st_s12adc1 +{ + union + { + unsigned short WORD; + struct + { + unsigned short DBLANS:5; + unsigned short :1; + unsigned short GBADIE:1; + unsigned short DBLE:1; + unsigned short EXTRG:1; + unsigned short TRGE:1; + unsigned short :2; + unsigned short ADIE:1; + unsigned short ADCS:2; + unsigned short ADST:1; + } BIT; + } ADCSR; + char wk0[2]; + union + { + unsigned short WORD; + struct + { + unsigned short ANSA:16; + } BIT; + } ADANSA; + char wk1[2]; + union + { + unsigned short WORD; + struct + { + unsigned short ADS:16; + } BIT; + } ADADS; + char wk2[2]; + union + { + unsigned char BYTE; + struct + { + unsigned char ADC:2; + unsigned char :5; + unsigned char AVEE:1; + } BIT; + } ADADC; + char wk3[1]; + union + { + unsigned short WORD; + struct + { + unsigned short :1; + unsigned short ADPRC:2; + unsigned short :2; + unsigned short ACE:1; + unsigned short :2; + unsigned short DIAGVAL:2; + unsigned short DIAGLD:1; + unsigned short DIAGM:1; + unsigned short :3; + unsigned short ADRFMT:1; + } BIT; + } ADCER; + union + { + unsigned short WORD; + struct + { + unsigned short TRSB:6; + unsigned short :2; + unsigned short TRSA:6; + unsigned short :2; + } BIT; + } ADSTRGR; + union + { + unsigned short WORD; + struct + { + unsigned short :13; + unsigned short EXSEL:2; + unsigned short EXOEN:1; + } BIT; + } ADEXICR; + union + { + unsigned short WORD; + struct + { + unsigned short ANSB:16; + } BIT; + } ADANSB; + char wk4[2]; + unsigned short ADDBLDR; + char wk5[4]; + unsigned short ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + unsigned short ADDR8; + unsigned short ADDR9; + unsigned short ADDR10; + unsigned short ADDR11; + unsigned short ADDR12; + unsigned short ADDR13; + unsigned short ADDR14; + unsigned short ADDR15; + char wk6[32]; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR0; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTRL; + char wk7[17]; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR1; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR2; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR3; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR4; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR5; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR6; + union + { + unsigned char BYTE; + struct + { + unsigned char SST:8; + } BIT; + } ADSSTR7; + union + { + unsigned char BYTE; + struct + { + unsigned char ADNDIS:5; + unsigned char :3; + } BIT; + } ADDISCR; + char wk8[5]; + union + { + unsigned short WORD; + struct + { + unsigned short PGS:1; + unsigned short GBRSCN:1; + unsigned short :13; + unsigned short GBRP:1; + } BIT; + } ADGSPCR; + char wk9[2]; + unsigned short ADDBLDRA; + unsigned short ADDBLDRB; + char wk10[8]; + union + { + unsigned char BYTE; + struct + { + unsigned char :6; + unsigned char WCMPE:1; + unsigned char CMPIE:1; + } BIT; + } ADCMPCR; + char wk11[3]; + union + { + unsigned short WORD; + struct + { + unsigned short CMPS:16; + } BIT; + } ADCMPANSR; + char wk12[2]; + union + { + unsigned short WORD; + struct + { + unsigned short CMPL:16; + } BIT; + } ADCMPLR; + char wk13[2]; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union + { + unsigned short WORD; + struct + { + unsigned short CMPF:16; + } BIT; + } ADCMPSR; + char wk14[38]; + union + { + unsigned char BYTE; + struct + { + unsigned char TDLV:2; + unsigned char :5; + unsigned char TDE:1; + } BIT; + } ADTDCR; + char wk15[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char :2; + unsigned char OWEIE:1; + unsigned char :5; + } BIT; + } ADERCR; + union + { + unsigned char BYTE; + struct + { + unsigned char :2; + unsigned char OWEC:1; + unsigned char :5; + } BIT; + } ADERCLR; + char wk16[6]; + union + { + unsigned short WORD; + struct + { + unsigned short OWE:16; + } BIT; + } ADOWER; + char wk17[2]; + union + { + unsigned short WORD; + struct + { + unsigned short DBOWE:1; + unsigned short DAOWE:1; + unsigned short DOWE:1; + unsigned short DIAGOWE:1; + unsigned short TSOWE:1; + unsigned short :11; + } BIT; + } ADOWEER; +}; + +struct st_scifa +{ + union + { + unsigned short WORD; + struct + { + unsigned short CKS:2; + unsigned short :1; + unsigned short STOP:1; + unsigned short PM:1; + unsigned short PE:1; + unsigned short CHR:1; + unsigned short CM:1; + unsigned short :8; + } BIT; + } SMR; + union + { + unsigned char BRR; + unsigned char MDDR; + } BRR_MDDR; + char wk0[1]; + union + { + unsigned short WORD; + struct + { + unsigned short CKE:2; + unsigned short TEIE:1; + unsigned short REIE:1; + unsigned short RE:1; + unsigned short TE:1; + unsigned short RIE:1; + unsigned short TIE:1; + unsigned short :8; + } BIT; + } SCR; + unsigned char FTDR; + char wk1[1]; + union + { + unsigned short WORD; + struct + { + unsigned short DR:1; + unsigned short RDF:1; + unsigned short PER:1; + unsigned short FER:1; + unsigned short BRK:1; + unsigned short TDFE:1; + unsigned short TEND:1; + unsigned short ER:1; + unsigned short :8; + } BIT; + } FSR; + unsigned char FRDR; + char wk2[1]; + union + { + unsigned short WORD; + struct + { + unsigned short LOOP:1; + unsigned short RFRST:1; + unsigned short TFRST:1; + unsigned short MCE:1; + unsigned short TTRG:2; + unsigned short RTRG:2; + unsigned short RSTRG:3; + unsigned short :5; + } BIT; + } FCR; + union + { + unsigned short WORD; + struct + { + unsigned short R:5; + unsigned short :3; + unsigned short T:5; + unsigned short :3; + } BIT; + } FDR; + union + { + unsigned short WORD; + struct + { + unsigned short SPB2DT:1; + unsigned short SPB2IO:1; + unsigned short SCKDT:1; + unsigned short SCKIO:1; + unsigned short CTS2DT:1; + unsigned short CTS2IO:1; + unsigned short RTS2DT:1; + unsigned short RTS2IO:1; + unsigned short :8; + } BIT; + } SPTR; + union + { + unsigned short WORD; + struct + { + unsigned short ORER:1; + unsigned short :1; + unsigned short FER:4; + unsigned short :2; + unsigned short PER:4; + unsigned short :4; + } BIT; + } LSR; + union + { + unsigned char BYTE; + struct + { + unsigned char ABCS0:1; + unsigned char :1; + unsigned char NFEN:1; + unsigned char DIR:1; + unsigned char MDDRS:1; + unsigned char BRME:1; + unsigned char :1; + unsigned char BGDM:1; + } BIT; + } SEMR; + char wk3[1]; + union + { + unsigned short WORD; + struct + { + unsigned short TFTC:5; + unsigned short :2; + unsigned short TTRGS:1; + unsigned short RFTC:5; + unsigned short :2; + unsigned short RTRGS:1; + } BIT; + } FTCR; +}; + +struct st_spibsc +{ + union + { + unsigned long LONG; + struct + { + unsigned long BSZ:2; + unsigned long :1; + unsigned long CPOL:1; + unsigned long SSLP:1; + unsigned long CPHAR:1; + unsigned long CPHAT:1; + unsigned long :1; + unsigned long IO0FV:2; + unsigned long :2; + unsigned long IO2FV:2; + unsigned long IO3FV:2; + unsigned long MOIIO0:2; + unsigned long MOIIO1:2; + unsigned long MOIIO2:2; + unsigned long MOIIO3:2; + unsigned long SFDE:1; + unsigned long :6; + unsigned long MD:1; + } BIT; + } CMNCR; + union + { + unsigned long LONG; + struct + { + unsigned long SCKDL:3; + unsigned long :5; + unsigned long SLNDL:3; + unsigned long :5; + unsigned long SPNDL:3; + unsigned long :13; + } BIT; + } SSLDR; + union + { + unsigned long LONG; + struct + { + unsigned long BRDV:2; + unsigned long :6; + unsigned long SPBR:8; + unsigned long :16; + } BIT; + } SPBCR; + union + { + unsigned long LONG; + struct + { + unsigned long SSLE:1; + unsigned long :7; + unsigned long RBE:1; + unsigned long RCF:1; + unsigned long :6; + unsigned long RBURST:4; + unsigned long :4; + unsigned long SSLN:1; + unsigned long :7; + } BIT; + } DRCR; + union + { + unsigned long LONG; + struct + { + unsigned long OCMD:8; + unsigned long :8; + unsigned long CMD:8; + unsigned long :8; + } BIT; + } DRCMR; + union + { + unsigned long LONG; + struct + { + unsigned long EAC:3; + unsigned long :13; + unsigned long EAV:8; + unsigned long :8; + } BIT; + } DREAR; + union + { + unsigned long LONG; + struct + { + unsigned long OPD0:8; + unsigned long OPD1:8; + unsigned long OPD2:8; + unsigned long OPD3:8; + } BIT; + } DROPR; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long OPDE:4; + unsigned long ADE:4; + unsigned long OCDE:1; + unsigned long :1; + unsigned long CDE:1; + unsigned long DME:1; + unsigned long DRDB:2; + unsigned long :2; + unsigned long OPDB:2; + unsigned long :2; + unsigned long ADB:2; + unsigned long :2; + unsigned long OCDB:2; + unsigned long CDB:2; + } BIT; + } DRENR; + union + { + unsigned long LONG; + struct + { + unsigned long SPIE:1; + unsigned long SPIWE:1; + unsigned long SPIRE:1; + unsigned long :5; + unsigned long SSLKP:1; + unsigned long :23; + } BIT; + } SMCR; + union + { + unsigned long LONG; + struct + { + unsigned long OCMD:8; + unsigned long :8; + unsigned long CMD:8; + unsigned long :8; + } BIT; + } SMCMR; + union + { + unsigned long LONG; + struct + { + unsigned long ADR:24; + unsigned long ADRE:8; + } BIT; + } SMADR; + union + { + unsigned long LONG; + struct + { + unsigned long OPD0:8; + unsigned long OPD1:8; + unsigned long OPD2:8; + unsigned long OPD3:8; + } BIT; + } SMOPR; + union + { + unsigned long LONG; + struct + { + unsigned long SPIDE:4; + unsigned long OPDE:4; + unsigned long ADE:4; + unsigned long OCDE:1; + unsigned long :1; + unsigned long CDE:1; + unsigned long DME:1; + unsigned long SPIDB:2; + unsigned long :2; + unsigned long OPDB:2; + unsigned long :2; + unsigned long ADB:2; + unsigned long :2; + unsigned long OCDB:2; + unsigned long CDB:2; + } BIT; + } SMENR; + char wk0[4]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long RDATA0:32; + } BIT; + } SMRDR0; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long WDATA0:32; + } BIT; + } SMWDR0; + char wk2[4]; + union + { + unsigned long LONG; + struct + { + unsigned long TEND:1; + unsigned long SSLF:1; + unsigned long :30; + } BIT; + } CMNSR; + char wk3[12]; + union + { + unsigned long LONG; + struct + { + unsigned long DMCYC:3; + unsigned long :13; + unsigned long DMDB:2; + unsigned long :14; + } BIT; + } DRDMCR; + char wk4[4]; + union + { + unsigned long LONG; + struct + { + unsigned long DMCYC:3; + unsigned long :13; + unsigned long DMDB:2; + unsigned long :14; + } BIT; + } SMDMCR; +}; + +struct st_ssi +{ + union + { + unsigned long LONG; + struct + { + unsigned long REN:1; + unsigned long TEN:1; + unsigned long :1; + unsigned long MUEN:1; + unsigned long CKDV:4; + unsigned long DEL:1; + unsigned long PDTA:1; + unsigned long SDTA:1; + unsigned long SPDP:1; + unsigned long SWSP:1; + unsigned long SCKP:1; + unsigned long SWSD:1; + unsigned long SCKD:1; + unsigned long SWL:3; + unsigned long DWL:3; + unsigned long CHNL:2; + unsigned long :1; + unsigned long IIEN:1; + unsigned long ROIEN:1; + unsigned long RUIEN:1; + unsigned long TOIEN:1; + unsigned long TUIEN:1; + unsigned long CKS:1; + unsigned long :1; + } BIT; + } SSICR; + union + { + unsigned long LONG; + struct + { + unsigned long IDST:1; + unsigned long RSWNO:1; + unsigned long :2; + unsigned long TSWNO:1; + unsigned long :20; + unsigned long IIRQ:1; + unsigned long ROIRQ:1; + unsigned long RUIRQ:1; + unsigned long TOIRQ:1; + unsigned long TUIRQ:1; + unsigned long :2; + } BIT; + } SSISR; + char wk0[8]; + union + { + unsigned long LONG; + struct + { + unsigned long RFRST:1; + unsigned long TFRST:1; + unsigned long RIE:1; + unsigned long TIE:1; + unsigned long RTRG:2; + unsigned long TTRG:2; + unsigned long :23; + unsigned long AUCKE:1; + } BIT; + } SSIFCR; + union + { + unsigned long LONG; + struct + { + unsigned long RDF:1; + unsigned long :7; + unsigned long RDC:4; + unsigned long :4; + unsigned long TDE:1; + unsigned long :7; + unsigned long TDC:4; + unsigned long :4; + } BIT; + } SSIFSR; + unsigned long SSIFTDR; + unsigned long SSIFRDR; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long CONT:1; + unsigned long :23; + } BIT; + } SSITDMR; +}; + +struct st_system +{ + union + { + unsigned long LONG; + struct + { + unsigned long PCKG:2; + unsigned long PCKF:2; + unsigned long PCKE:2; + unsigned long :2; + unsigned long CKIO:3; + unsigned long :1; + unsigned long ETCKE:1; + unsigned long :1; + unsigned long ETCKD:2; + unsigned long SERICK:1; + unsigned long :3; + unsigned long TCLK:1; + unsigned long :11; + } BIT; + } SCKCR; + union + { + unsigned long LONG; + struct + { + unsigned long CKSEL0:1; + unsigned long :31; + } BIT; + } SCKCR2; + union + { + unsigned long LONG; + struct + { + unsigned long DSSEL0:1; + unsigned long DSCK0:3; + unsigned long DSINV0:1; + unsigned long DSCHSEL:1; + unsigned long :10; + unsigned long DSSEL1:1; + unsigned long DSCK1:3; + unsigned long DSINV1:1; + unsigned long :11; + } BIT; + } DSCR; + char wk0[8]; + union + { + unsigned long LONG; + struct + { + unsigned long CPUCKSEL:2; + unsigned long :30; + } BIT; + } PLL1CR; + union + { + unsigned long LONG; + struct + { + unsigned long PLL1EN:1; + unsigned long :31; + } BIT; + } PLL1CR2; + char wk1[4]; + union + { + unsigned long LONG; + struct + { + unsigned long LCSTP:1; + unsigned long :31; + } BIT; + } LOCOCR; + char wk2[8]; + union + { + unsigned long LONG; + struct + { + unsigned long OSTDIE:1; + unsigned long :6; + unsigned long OSTDE:1; + unsigned long :24; + } BIT; + } OSTDCR; + char wk3[432]; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long TRF:1; + unsigned long ECMRF:1; + unsigned long SWR1F:1; + unsigned long :28; + } BIT; + } RSTSR0; + char wk4[12]; + union + { + unsigned long LONG; + } SWRR1; + char wk5[12]; + union + { + unsigned long LONG; + } SWRR2; + char wk6[36]; + union + { + unsigned long LONG; + struct + { + unsigned long MRUSBF:1; + unsigned long MRUSBH:1; + unsigned long :30; + } BIT; + } MRCTLC; + char wk7[180]; + union + { + unsigned long LONG; + struct + { + unsigned long MSTPCRA0:1; + unsigned long MSTPCRA1:1; + unsigned long MSTPCRA2:1; + unsigned long MSTPCRA3:1; + unsigned long MSTPCRA4:1; + unsigned long MSTPCRA5:1; + unsigned long MSTPCRA6:1; + unsigned long MSTPCRA7:1; + unsigned long MSTPCRA8:1; + unsigned long MSTPCRA9:1; + unsigned long :1; + unsigned long MSTPCRA11:1; + unsigned long :20; + } BIT; + } MSTPCRA; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long MSTPCRB1:1; + unsigned long MSTPCRB2:1; + unsigned long MSTPCRB3:1; + unsigned long :1; + unsigned long MSTPCRB5:1; + unsigned long MSTPCRB6:1; + unsigned long MSTPCRB7:1; + unsigned long MSTPCRB8:1; + unsigned long MSTPCRB9:1; + unsigned long MSTPCRB10:1; + unsigned long MSTPCRB11:1; + unsigned long MSTPCRB12:1; + unsigned long MSTPCRB13:1; + unsigned long MSTPCRB14:1; + unsigned long MSTPCRB15:1; + unsigned long MSTPCRB16:1; + unsigned long MSTPCRB17:1; + unsigned long MSTPCRB18:1; + unsigned long MSTPCRB19:1; + unsigned long :12; + } BIT; + } MSTPCRB; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long MSTPCRC1:1; + unsigned long MSTPCRC2:1; + unsigned long MSTPCRC3:1; + unsigned long MSTPCRC4:1; + unsigned long MSTPCRC5:1; + unsigned long MSTPCRC6:1; + unsigned long MSTPCRC7:1; + unsigned long MSTPCRC8:1; + unsigned long MSTPCRC9:1; + unsigned long MSTPCRC10:1; + unsigned long MSTPCRC11:1; + unsigned long MSTPCRC12:1; + unsigned long MSTPCRC13:1; + unsigned long MSTPCRC14:1; + unsigned long :17; + } BIT; + } MSTPCRC; + union + { + unsigned long LONG; + struct + { + unsigned long :2; + unsigned long MSTPCRD2:1; + unsigned long :29; + } BIT; + } MSTPCRD; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long MSTPCRE4:1; + unsigned long MSTPCRE5:1; + unsigned long :26; + } BIT; + } MSTPCRE; + union + { + unsigned long LONG; + struct + { + unsigned long MSTPCRF0:1; + unsigned long :31; + } BIT; + } MSTPCRF; + char wk8[1256]; + union + { + unsigned long LONG; + struct + { + unsigned long ATCMWAIT:2; + unsigned long :30; + } BIT; + } SYTATCMWAIT; + char wk9[284]; + union + { + unsigned long LONG; + struct + { + unsigned long SEMFEN:1; + unsigned long :31; + } BIT; + } SYTSEMFEN; + char wk10[12]; + union + { + unsigned long LONG; + struct + { + unsigned long SEMF0:1; + unsigned long :31; + } BIT; + } SYTSEMF0; + union + { + unsigned long LONG; + struct + { + unsigned long SEMF1:1; + unsigned long :31; + } BIT; + } SYTSEMF1; + union + { + unsigned long LONG; + struct + { + unsigned long SEMF2:1; + unsigned long :31; + } BIT; + } SYTSEMF2; + union + { + unsigned long LONG; + struct + { + unsigned long SEMF3:1; + unsigned long :31; + } BIT; + } SYTSEMF3; + union + { + unsigned long LONG; + struct + { + unsigned long SEMF4:1; + unsigned long :31; + } BIT; + } SYTSEMF4; + union + { + unsigned long LONG; + struct + { + unsigned long SEMF5:1; + unsigned long :31; + } BIT; + } SYTSEMF5; + union + { + unsigned long LONG; + struct + { + unsigned long SEMF6:1; + unsigned long :31; + } BIT; + } SYTSEMF6; + union + { + unsigned long LONG; + struct + { + unsigned long SEMF7:1; + unsigned long :31; + } BIT; + } SYTSEMF7; + char wk11[176]; + union + { + unsigned long LONG; + struct + { + unsigned long SWVSEL:2; + unsigned long :30; + } BIT; + } DBGIFCNT; + char wk12[92]; + union + { + unsigned long LONG; + struct + { + unsigned long MD0:1; + unsigned long MD1:1; + unsigned long MD2:1; + unsigned long :29; + } BIT; + } MDMONR; + char wk13[28]; + union + { + unsigned long LONG; + struct + { + unsigned long MSKC:1; + unsigned long MSKM:1; + unsigned long :30; + } BIT; + } ECMMCNT; + char wk14[124]; + union + { + unsigned long LONG; + } PRCR; +}; + +struct st_tpu0 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR; + char wk0[7]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char ICSELB:1; + unsigned char ICSELD:1; + } BIT; + } TMDR; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char TGFC:1; + unsigned char TGFD:1; + unsigned char TCFV:1; + unsigned char TCFU:1; + unsigned char :1; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu1 +{ + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR; + char wk1[22]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char ICSELB:1; + unsigned char ICSELD:1; + } BIT; + } TMDR; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + char wk2[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char TGFC:1; + unsigned char TGFD:1; + unsigned char TCFV:1; + unsigned char TCFU:1; + unsigned char :1; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu2 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR; + char wk0[37]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char ICSELB:1; + unsigned char ICSELD:1; + } BIT; + } TMDR; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char TGFC:1; + unsigned char TGFD:1; + unsigned char TCFV:1; + unsigned char TCFU:1; + unsigned char :1; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu3 +{ + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR; + char wk1[52]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char ICSELB:1; + unsigned char ICSELD:1; + } BIT; + } TMDR; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIORH; + union + { + unsigned char BYTE; + struct + { + unsigned char IOC:4; + unsigned char IOD:4; + } BIT; + } TIORL; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char TGFC:1; + unsigned char TGFD:1; + unsigned char TCFV:1; + unsigned char TCFU:1; + unsigned char :1; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu4 +{ + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR; + char wk0[67]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char ICSELB:1; + unsigned char ICSELD:1; + } BIT; + } TMDR; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + char wk1[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char TGFC:1; + unsigned char TGFD:1; + unsigned char TCFV:1; + unsigned char TCFU:1; + unsigned char :1; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu5 +{ + char wk0[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char NFAEN:1; + unsigned char NFBEN:1; + unsigned char NFCEN:1; + unsigned char NFDEN:1; + unsigned char NFCS:2; + unsigned char :2; + } BIT; + } NFCR; + char wk1[82]; + union + { + unsigned char BYTE; + struct + { + unsigned char TPSC:3; + unsigned char CKEG:2; + unsigned char CCLR:3; + } BIT; + } TCR; + union + { + unsigned char BYTE; + struct + { + unsigned char MD:4; + unsigned char BFA:1; + unsigned char BFB:1; + unsigned char ICSELB:1; + unsigned char ICSELD:1; + } BIT; + } TMDR; + union + { + unsigned char BYTE; + struct + { + unsigned char IOA:4; + unsigned char IOB:4; + } BIT; + } TIOR; + char wk2[1]; + union + { + unsigned char BYTE; + struct + { + unsigned char TGIEA:1; + unsigned char TGIEB:1; + unsigned char TGIEC:1; + unsigned char TGIED:1; + unsigned char TCIEV:1; + unsigned char TCIEU:1; + unsigned char :1; + unsigned char TTGE:1; + } BIT; + } TIER; + union + { + unsigned char BYTE; + struct + { + unsigned char TGFA:1; + unsigned char TGFB:1; + unsigned char TGFC:1; + unsigned char TGFD:1; + unsigned char TCFV:1; + unsigned char TCFU:1; + unsigned char :1; + unsigned char TCFD:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpua +{ + union + { + unsigned char BYTE; + struct + { + unsigned char CST0:1; + unsigned char CST1:1; + unsigned char CST2:1; + unsigned char CST3:1; + unsigned char CST4:1; + unsigned char CST5:1; + unsigned char :2; + } BIT; + } TSTRA; + union + { + unsigned char BYTE; + struct + { + unsigned char SYNC0:1; + unsigned char SYNC1:1; + unsigned char SYNC2:1; + unsigned char SYNC3:1; + unsigned char SYNC4:1; + unsigned char SYNC5:1; + unsigned char :2; + } BIT; + } TSYRA; + char wk0[126]; + union + { + unsigned char BYTE; + struct + { + unsigned char CST0:1; + unsigned char CST1:1; + unsigned char CST2:1; + unsigned char CST3:1; + unsigned char CST4:1; + unsigned char CST5:1; + unsigned char :2; + } BIT; + } TSTRB; + union + { + unsigned char BYTE; + struct + { + unsigned char SYNC0:1; + unsigned char SYNC1:1; + unsigned char SYNC2:1; + unsigned char SYNC3:1; + unsigned char SYNC4:1; + unsigned char SYNC5:1; + unsigned char :2; + } BIT; + } TSYRB; +}; + +struct st_tpusl +{ + union + { + unsigned long LONG; + struct + { + unsigned long TPU0EN:1; + unsigned long :1; + unsigned long FBSL0:3; + unsigned long :3; + unsigned long TPU1EN:1; + unsigned long :1; + unsigned long FBSL1:3; + unsigned long :19; + } BIT; + } PWMFBSLR; +}; + +struct st_tsn +{ + union + { + unsigned char BYTE; + struct + { + unsigned char :4; + unsigned char TSOE:1; + unsigned char :2; + unsigned char TSEN:1; + } BIT; + } TSCR; +}; + +struct st_usbf +{ + union + { + unsigned short WORD; + struct + { + unsigned short USBE:1; + unsigned short :3; + unsigned short DPRPU:1; + unsigned short DRPD:1; + unsigned short :1; + unsigned short HSE:1; + unsigned short :8; + } BIT; + } SYSCFG0; + union + { + unsigned short WORD; + struct + { + unsigned short BWAIT:6; + unsigned short :10; + } BIT; + } SYSCFG1; + union + { + unsigned short WORD; + struct + { + unsigned short LNST:2; + unsigned short :14; + } BIT; + } SYSSTS0; + char wk0[2]; + union + { + unsigned short WORD; + struct + { + unsigned short RHST:3; + unsigned short :5; + unsigned short WKUP:1; + unsigned short :7; + } BIT; + } DVSTCTR0; + char wk1[2]; + union + { + unsigned short WORD; + struct + { + unsigned short UTST:4; + unsigned short :12; + } BIT; + } TESTMODE; + char wk2[2]; + union + { + unsigned short WORD; + struct + { + unsigned short :4; + unsigned short TENDE:1; + unsigned short :7; + unsigned short DFACC:2; + unsigned short :2; + } BIT; + } D0FBCFG; + union + { + unsigned short WORD; + struct + { + unsigned short :4; + unsigned short TENDE:1; + unsigned short :7; + unsigned short DFACC:2; + unsigned short :2; + } BIT; + } D1FBCFG; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } CFIFO; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D0FIFO; + union + { + unsigned long LONG; + struct + { + unsigned short H; + unsigned short L; + } WORD; + struct + { + unsigned char HH; + unsigned char HL; + unsigned char LH; + unsigned char LL; + } BYTE; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D1FIFO; + union + { + unsigned short WORD; + struct + { + unsigned short CURPIPE:4; + unsigned short :1; + unsigned short ISEL:1; + unsigned short :2; + unsigned short BIGEND:1; + unsigned short :1; + unsigned short MBW:2; + unsigned short :2; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } CFIFOSEL; + union + { + unsigned short WORD; + struct + { + unsigned short DTLN:12; + unsigned short :1; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } CFIFOCTR; + char wk3[4]; + union + { + unsigned short WORD; + struct + { + unsigned short CURPIPE:4; + unsigned short :4; + unsigned short BIGEND:1; + unsigned short :1; + unsigned short MBW:2; + unsigned short DREQE:1; + unsigned short DCLRM:1; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } D0FIFOSEL; + union + { + unsigned short WORD; + struct + { + unsigned short DTLN:12; + unsigned short :1; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } D0FIFOCTR; + union + { + unsigned short WORD; + struct + { + unsigned short CURPIPE:4; + unsigned short :4; + unsigned short BIGEND:1; + unsigned short :1; + unsigned short MBW:2; + unsigned short DREQE:1; + unsigned short DCLRM:1; + unsigned short REW:1; + unsigned short RCNT:1; + } BIT; + } D1FIFOSEL; + union + { + unsigned short WORD; + struct + { + unsigned short DTLN:12; + unsigned short :1; + unsigned short FRDY:1; + unsigned short BCLR:1; + unsigned short BVAL:1; + } BIT; + } D1FIFOCTR; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short BRDYE:1; + unsigned short NRDYE:1; + unsigned short BEMPE:1; + unsigned short CTRE:1; + unsigned short DVSE:1; + unsigned short SOFE:1; + unsigned short RSME:1; + unsigned short VBSE:1; + } BIT; + } INTENB0; + char wk4[4]; + union + { + unsigned short WORD; + struct + { + unsigned short PIPEBRDYE:10; + unsigned short :6; + } BIT; + } BRDYENB; + union + { + unsigned short WORD; + struct + { + unsigned short PIPENRDYE:10; + unsigned short :6; + } BIT; + } NRDYENB; + union + { + unsigned short WORD; + struct + { + unsigned short PIPEBEMPE:10; + unsigned short :6; + } BIT; + } BEMPENB; + union + { + unsigned short WORD; + struct + { + unsigned short :4; + unsigned short EDGESTS:1; + unsigned short INTL:1; + unsigned short BRDYM:1; + unsigned short :9; + } BIT; + } SOFCFG; + char wk5[2]; + union + { + unsigned short WORD; + struct + { + unsigned short CTSQ:3; + unsigned short VALID:1; + unsigned short DVSQ:3; + unsigned short VBSTS:1; + unsigned short BRDY:1; + unsigned short NRDY:1; + unsigned short BEMP:1; + unsigned short CTRT:1; + unsigned short DVST:1; + unsigned short SOFR:1; + unsigned short RESM:1; + unsigned short VBINT:1; + } BIT; + } INTSTS0; + char wk6[4]; + union + { + unsigned short WORD; + struct + { + unsigned short PIPEBRDY:10; + unsigned short :6; + } BIT; + } BRDYSTS; + union + { + unsigned short WORD; + struct + { + unsigned short PIPENRDY:10; + unsigned short :6; + } BIT; + } NRDYSTS; + union + { + unsigned short WORD; + struct + { + unsigned short PIPEBEMP:10; + unsigned short :6; + } BIT; + } BEMPSTS; + union + { + unsigned short WORD; + struct + { + unsigned short FRNM:11; + unsigned short :3; + unsigned short CRCE:1; + unsigned short OVRN:1; + } BIT; + } FRMNUM; + union + { + unsigned short WORD; + struct + { + unsigned short UFRNM:3; + unsigned short :13; + } BIT; + } UFRMNUM; + union + { + unsigned short WORD; + struct + { + unsigned short USBADDR:7; + unsigned short :9; + } BIT; + } USBADDR; + char wk7[2]; + union + { + unsigned short WORD; + struct + { + unsigned short bmRequestType:8; + unsigned short bRequest:8; + } BIT; + } USBREQ; + union + { + unsigned short WORD; + struct + { + unsigned short wValue:16; + } BIT; + } USBVAL; + union + { + unsigned short WORD; + struct + { + unsigned short wIndex:16; + } BIT; + } USBINDX; + union + { + unsigned short WORD; + struct + { + unsigned short wLength:16; + } BIT; + } USBLENG; + unsigned short DCPCFG; + union + { + unsigned short WORD; + struct + { + unsigned short MXPS:7; + unsigned short :9; + } BIT; + } DCPMAXP; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short CCPL:1; + unsigned short :2; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short :6; + unsigned short BSTS:1; + } BIT; + } DCPCTR; + char wk8[2]; + union + { + unsigned short WORD; + struct + { + unsigned short PIPESEL:4; + unsigned short :12; + } BIT; + } PIPESEL; + char wk9[2]; + union + { + unsigned short WORD; + struct + { + unsigned short EPNUM:4; + unsigned short DIR:1; + unsigned short :2; + unsigned short SHTNAK:1; + unsigned short CNTMD:1; + unsigned short DBLB:1; + unsigned short BFRE:1; + unsigned short :3; + unsigned short TYPE:2; + } BIT; + } PIPECFG; + union + { + unsigned short WORD; + struct + { + unsigned short BUFNMB:8; + unsigned short :2; + unsigned short BUFSIZE:5; + unsigned short :1; + } BIT; + } PIPEBUF; + union + { + unsigned short WORD; + struct + { + unsigned short MXPS:11; + unsigned short :5; + } BIT; + } PIPEMAXP; + union + { + unsigned short WORD; + struct + { + unsigned short IITV:3; + unsigned short :9; + unsigned short IFIS:1; + unsigned short :3; + } BIT; + } PIPEPERI; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE1CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE2CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE3CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE4CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short ATREPM:1; + unsigned short :3; + unsigned short INBUFM:1; + unsigned short BSTS:1; + } BIT; + } PIPE5CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE6CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE7CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE8CTR; + union + { + unsigned short WORD; + struct + { + unsigned short PID:2; + unsigned short :3; + unsigned short PBUSY:1; + unsigned short SQMON:1; + unsigned short SQSET:1; + unsigned short SQCLR:1; + unsigned short ACLRM:1; + unsigned short :5; + unsigned short BSTS:1; + } BIT; + } PIPE9CTR; + char wk10[14]; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE1TRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPE1TRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE2TRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPE2TRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE3TRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPE3TRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE4TRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPE4TRN; + union + { + unsigned short WORD; + struct + { + unsigned short :8; + unsigned short TRCLR:1; + unsigned short TRENB:1; + unsigned short :6; + } BIT; + } PIPE5TRE; + union + { + unsigned short WORD; + struct + { + unsigned short TRNCNT:16; + } BIT; + } PIPE5TRN; + char wk11[92]; + unsigned short LPCTRL; + union + { + unsigned short WORD; + struct + { + unsigned short :14; + unsigned short SUSPM:1; + unsigned short :1; + } BIT; + } LPSTS; + unsigned short PHYFUNCTR; + char wk12[90]; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D0FIFOB0; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D0FIFOB1; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D0FIFOB2; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D0FIFOB3; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D0FIFOB4; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D0FIFOB5; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D0FIFOB6; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D0FIFOB7; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D1FIFOB0; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D1FIFOB1; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D1FIFOB2; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D1FIFOB3; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D1FIFOB4; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D1FIFOB5; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D1FIFOB6; + union + { + unsigned long LONG; + struct + { + unsigned long FIFOPORT:32; + } BIT; + } D1FIFOB7; + union + { + unsigned short WORD; + struct + { + unsigned short P1PORTSEL:2; + unsigned short PHYPD:1; + unsigned short PHYRESET:1; + unsigned short PHYVBUSIN:1; + unsigned short :11; + } BIT; + } PHYSET1; +}; + +struct st_usbh +{ + union + { + unsigned long LONG; + struct + { + unsigned long Revision:8; + unsigned long :24; + } BIT; + } HcRevision; + union + { + unsigned long LONG; + struct + { + unsigned long CBSR:2; + unsigned long PLE:1; + unsigned long IE:1; + unsigned long CLE:1; + unsigned long BLE:1; + unsigned long HCFS:2; + unsigned long :1; + unsigned long RWC:1; + unsigned long RWE:1; + unsigned long :21; + } BIT; + } HcControl; + union + { + unsigned long LONG; + struct + { + unsigned long HCR:1; + unsigned long CLF:1; + unsigned long BLF:1; + unsigned long OCR:1; + unsigned long :12; + unsigned long SOC:2; + unsigned long :14; + } BIT; + } HcCommandStatus; + union + { + unsigned long LONG; + struct + { + unsigned long SO:1; + unsigned long WDH:1; + unsigned long SF:1; + unsigned long RD:1; + unsigned long UE:1; + unsigned long FNO:1; + unsigned long RHSC:1; + unsigned long :25; + } BIT; + } HcIntStatus; + union + { + unsigned long LONG; + struct + { + unsigned long SOE:1; + unsigned long WDHE:1; + unsigned long SFE:1; + unsigned long RDE:1; + unsigned long UEE:1; + unsigned long FNOE:1; + unsigned long RHSCE:1; + unsigned long :24; + unsigned long MIE:1; + } BIT; + } HcIntEnable; + union + { + unsigned long LONG; + struct + { + unsigned long SOD:1; + unsigned long WDHD:1; + unsigned long SFD:1; + unsigned long RDD:1; + unsigned long UED:1; + unsigned long FNOD:1; + unsigned long RHSCD:1; + unsigned long :24; + unsigned long MID:1; + } BIT; + } HcIntDisable; + union + { + unsigned long LONG; + struct + { + unsigned long :8; + unsigned long HcHCCA:24; + } BIT; + } HcHCCA; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long PeriodicCurrentED:28; + } BIT; + } HcPeriodCurED; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long ControlHeadED:28; + } BIT; + } HcContHeadED; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long ControlCurrentED:28; + } BIT; + } HcContCurrentED; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long BulkHeadED:28; + } BIT; + } HcBulkHeadED; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long BulkCurrentED:28; + } BIT; + } HcBulkCurrentED; + union + { + unsigned long LONG; + struct + { + unsigned long :4; + unsigned long DoneHead:28; + } BIT; + } HcDoneHead; + union + { + unsigned long LONG; + struct + { + unsigned long FI:14; + unsigned long :2; + unsigned long FSMPS:15; + unsigned long FIT:1; + } BIT; + } HcFmInterval; + union + { + unsigned long LONG; + struct + { + unsigned long FR:14; + unsigned long :17; + unsigned long FRT:1; + } BIT; + } HcFmRemaining; + union + { + unsigned long LONG; + struct + { + unsigned long FrameNumber:16; + unsigned long :16; + } BIT; + } HcFmNumber; + union + { + unsigned long LONG; + struct + { + unsigned long PeriodicStart:14; + unsigned long :18; + } BIT; + } HcPeriodicStart; + union + { + unsigned long LONG; + struct + { + unsigned long HcLSThreshold:12; + unsigned long :20; + } BIT; + } HcLSThreshold; + union + { + unsigned long LONG; + struct + { + unsigned long NDP:8; + unsigned long PSM:1; + unsigned long NPS:1; + unsigned long DT:1; + unsigned long OCPM:1; + unsigned long NOCP:1; + unsigned long :11; + unsigned long POTPGT:8; + } BIT; + } HcRhDescriptorA; + union + { + unsigned long LONG; + struct + { + unsigned long DR:16; + unsigned long PPCM:16; + } BIT; + } HcRhDescriptorB; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long CGP:1; + unsigned long OCI:1; + unsigned long :13; + unsigned long SRWE:1; + unsigned long SGP:1; + unsigned long OCIC:1; + unsigned long :13; + unsigned long CRWE:1; + } BIT; + } HcRhStatus_A; + union + { + unsigned long LONG; + struct + { + unsigned long LPS:1; + unsigned long OCI:1; + unsigned long :13; + unsigned long DRWE:1; + unsigned long LPSC:1; + unsigned long OCIC:1; + unsigned long :13; + unsigned long CRWE:1; + } BIT; + } HcRhStatus_B; + } HcRhStatus; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long CPE:1; + unsigned long SPE:1; + unsigned long SPS:1; + unsigned long CSS:1; + unsigned long SPR:1; + unsigned long :3; + unsigned long SPP:1; + unsigned long CPP:1; + unsigned long :6; + unsigned long CSC:1; + unsigned long PESC:1; + unsigned long PSSC:1; + unsigned long OCIC:1; + unsigned long PRSC:1; + unsigned long :11; + } BIT; + } HcRhPortStatus1_A; + union + { + unsigned long LONG; + struct + { + unsigned long CCS:1; + unsigned long PES:1; + unsigned long PSS:1; + unsigned long POCI:1; + unsigned long PRS:1; + unsigned long :3; + unsigned long PPS:1; + unsigned long LSDA:1; + unsigned long :6; + unsigned long CSC:1; + unsigned long PESC:1; + unsigned long PSSC:1; + unsigned long OCIC:1; + unsigned long PRSC:1; + unsigned long :11; + } BIT; + } HcRhPortStatus1_B; + } HcRhPortStatus1; + char wk0[4008]; + union + { + unsigned long LONG; + struct + { + unsigned long CapabilityRegistersLength:8; + unsigned long :8; + unsigned long InterfaceVersionNumber:16; + } BIT; + } CAPL_VERSION; + union + { + unsigned long LONG; + struct + { + unsigned long N_PORTS:4; + unsigned long PPC:1; + unsigned long :2; + unsigned long PortRoutingRules:1; + unsigned long N_PCC:4; + unsigned long N_CC:4; + unsigned long P_INDICATOR:1; + unsigned long :3; + unsigned long DebugPortNumber:4; + unsigned long :8; + } BIT; + } HCSPARAMS; + union + { + unsigned long LONG; + struct + { + unsigned long AC64:1; + unsigned long PFLF:1; + unsigned long ASPC:1; + unsigned long :1; + unsigned long IST:4; + unsigned long EECP:8; + unsigned long :16; + } BIT; + } HCCPARAMS; + union + { + unsigned long LONG; + struct + { + unsigned long CompanionPortRoute:32; + } BIT; + } HCSP_PORTROUTE; + char wk1[16]; + union + { + unsigned long LONG; + struct + { + unsigned long RS:1; + unsigned long HCRESET:1; + unsigned long FrameListSize:2; + unsigned long PeriodicScheduleEnable:1; + unsigned long ASPME:1; + unsigned long InterruptonAsyncAdvanceDoorbell:1; + unsigned long LightHostControllerReset:1; + unsigned long ASPMC:2; + unsigned long :1; + unsigned long AsynchronousScheduleParkModeEnable:1; + unsigned long :4; + unsigned long InterruptThresholdControl:8; + unsigned long :8; + } BIT; + } USBCMD; + union + { + unsigned long LONG; + struct + { + unsigned long USBINT:1; + unsigned long USBERRINT:1; + unsigned long PortChangeDetect:1; + unsigned long FrameListRollover:1; + unsigned long HostSystemError:1; + unsigned long InterruptonAsyncAdvance:1; + unsigned long :6; + unsigned long HCHalted:1; + unsigned long Reclamation:1; + unsigned long PeriodicScheduleStatus:1; + unsigned long AsynchronousScheduleStatus:1; + unsigned long :16; + } BIT; + } USBSTS; + union + { + unsigned long LONG; + struct + { + unsigned long USBInterruptEnable:1; + unsigned long USBErrorInterruptEnable:1; + unsigned long PortChangeInterruptEnable:1; + unsigned long FrameListRolloverEnable:1; + unsigned long HostSystemErrorEnable:1; + unsigned long InterruptonAsyncAdvanceEnable:1; + unsigned long :26; + } BIT; + } USBINTR; + union + { + unsigned long LONG; + struct + { + unsigned long FrameIndex:14; + unsigned long :18; + } BIT; + } FRINDEX; + union + { + unsigned long LONG; + struct + { + unsigned long CTRLDSSEGMENT:32; + } BIT; + } CTRLDSSEGMENT; + union + { + unsigned long LONG; + struct + { + unsigned long :12; + unsigned long BaseAddressLow:20; + } BIT; + } PERIODICLIST; + union + { + unsigned long LONG; + struct + { + unsigned long :5; + unsigned long LPL:27; + } BIT; + } ASYNCLISTADDR; + char wk2[36]; + union + { + unsigned long LONG; + struct + { + unsigned long CF:1; + unsigned long :31; + } BIT; + } CONFIGFLAG; + union + { + unsigned long LONG; + struct + { + unsigned long CurrentConnectStatus:1; + unsigned long ConnectStatusChange:1; + unsigned long PortEnabledDisabled:1; + unsigned long PortEnableDisableChange:1; + unsigned long OvercurrentActive:1; + unsigned long OvercurrentChange:1; + unsigned long ForcePortResume:1; + unsigned long Suspend:1; + unsigned long PortReset:1; + unsigned long :1; + unsigned long LineStatus:2; + unsigned long PP:1; + unsigned long PortOwner:1; + unsigned long PortIndicatorControl:2; + unsigned long PortTestControl:4; + unsigned long WKCNNT_E:1; + unsigned long WKDSCNNT_E:1; + unsigned long WKOC_E:1; + unsigned long :9; + } BIT; + } PORTSC1; + char wk3[61336]; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long VendorID:16; + unsigned long DeviceID:16; + } BIT; + } VID_DID_O; + union + { + unsigned long LONG; + struct + { + unsigned long VENDOR_ID:16; + unsigned long DEVICE_ID:16; + } BIT; + } VID_DID_A; + } VID_DID; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long IOSpace:1; + unsigned long MemorySpace:1; + unsigned long BusMaster:1; + unsigned long SpecialCycle:1; + unsigned long MemoryWriteandInvalidateEnable:1; + unsigned long VGAPaletteSnoop:1; + unsigned long ParityErrorResponse:1; + unsigned long WaitCycleControl:1; + unsigned long SERREnable:1; + unsigned long FastBacktoBackEnable:1; + unsigned long :10; + unsigned long CapabilitiesList:1; + unsigned long :2; + unsigned long FastBacktoBackCapable:1; + unsigned long DataParityErrorDetected:1; + unsigned long DevselTiming:2; + unsigned long SignaledTargetAbort:1; + unsigned long ReceivedTargetAbort:1; + unsigned long ReceivedMasterAbort:1; + unsigned long SignaledSystemError:1; + unsigned long DetectedParityError:1; + } BIT; + } CMND_STS_O; + union + { + unsigned long LONG; + struct + { + unsigned long IOEN:1; + unsigned long MEMEN:1; + unsigned long MASTEREN:1; + unsigned long SPECIALC:1; + unsigned long MWINVEN:1; + unsigned long VGAPSNP:1; + unsigned long PERREN:1; + unsigned long STEPCTR:1; + unsigned long SERREN:1; + unsigned long FBTBEN:1; + unsigned long :10; + unsigned long CAPLIST:1; + unsigned long CAP66M:1; + unsigned long :1; + unsigned long FBTBCAP:1; + unsigned long MDPERR:1; + unsigned long DEVTIM:2; + unsigned long SIGTABORT:1; + unsigned long RETABORT:1; + unsigned long REMABORT:1; + unsigned long SIGSERR:1; + unsigned long DETPERR:1; + } BIT; + } CMND_STS_A; + } CMND_STS; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long RevisionID:8; + unsigned long ProgrammingIF:8; + unsigned long SubClass:8; + unsigned long BaseClass:8; + } BIT; + } REVID_CC_O; + union + { + unsigned long LONG; + struct + { + unsigned long REVISION_ID:8; + unsigned long CLASS_CODE:24; + } BIT; + } REVID_CC_A; + } REVID_CC; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long CacheLineSize:8; + unsigned long LatencyTimer:8; + unsigned long HeaderType:8; + unsigned long BIST:8; + } BIT; + } CLS_LT_HT_BIST_O; + union + { + unsigned long LONG; + struct + { + unsigned long CACHE_LINE_SIZE:8; + unsigned long LATENCY_TIMER:8; + unsigned long HEADER_TYPE:8; + unsigned long BIST:8; + } BIT; + } CLS_LT_HT_BIST_A; + } CLS_LT_HT_BIST; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long MemorySpaceIndicator:1; + unsigned long Type:2; + unsigned long Prefetchable:1; + unsigned long OHCIBaseAddress:28; + } BIT; + } BASEAD_O; + union + { + unsigned long LONG; + struct + { + unsigned long MEM:1; + unsigned long TYPE:2; + unsigned long PREFETCH:1; + unsigned long :6; + unsigned long PCICOM_BASEADR:22; + } BIT; + } BASEAD_A; + } BASEAD; + union + { + unsigned long LONG; + struct + { + unsigned long MEM:1; + unsigned long TYPE:2; + unsigned long PREFETCH:1; + unsigned long :24; + unsigned long PCI_WIN1_BASEADR:4; + } BIT; + } WIN1_BASEAD; + char wk4[20]; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long SubsystemVendorID:16; + unsigned long SubsystemID:16; + } BIT; + } SSVID_SSID_O; + union + { + unsigned long LONG; + struct + { + unsigned long SUBSYS_VENDOR_ID:16; + unsigned long SUBSYS_ID:16; + } BIT; + } SSVID_SSID_A; + } SSVID_SSID; + union + { + unsigned long LONG; + struct + { + unsigned long ROMDecodeEnable:1; + unsigned long :9; + unsigned long ExpansionROMBaseAddress:22; + } BIT; + } EROM_BASEAD; + union + { + unsigned long LONG; + struct + { + unsigned long CapabilityPointer:8; + unsigned long :24; + } BIT; + } CAPPTR; + char wk5[4]; + union + { + union + { + unsigned long LONG; + struct + { + unsigned long InterruptLine:8; + unsigned long InterruptPin:8; + unsigned long MINGnt:8; + unsigned long MaxLatency:8; + } BIT; + } INTR_LINE_PIN_O; + union + { + unsigned long LONG; + struct + { + unsigned long INT_LINE:8; + unsigned long INT_PIN:8; + unsigned long MIN_GNT:8; + unsigned long MAX_LAT:8; + } BIT; + } INTR_LINE_PIN_A; + } INTR_LINE_PIN; + union + { + unsigned long LONG; + struct + { + unsigned long CapabilityIdentifier:8; + unsigned long NextItemPointer:8; + unsigned long Version:3; + unsigned long PMECLK:1; + unsigned long :1; + unsigned long DSI:1; + unsigned long AUXCurrent:3; + unsigned long D1Support:1; + unsigned long D2Support:1; + unsigned long PMESupport:5; + } BIT; + } CAPID_NIP_PMCAP; + union + { + unsigned long LONG; + struct + { + unsigned long PowerState:2; + unsigned long :6; + unsigned long PMEEnable:1; + unsigned long DataSelect:4; + unsigned long DataScale:2; + unsigned long PMEStatus:1; + unsigned long :6; + unsigned long B2_B3:1; + unsigned long BPCCEnable:1; + unsigned long Data:8; + } BIT; + } PMC_STS_PMCSR; + char wk6[152]; + union + { + unsigned long LONG; + struct + { + unsigned long Port_no:2; + unsigned long :5; + unsigned long ID_Write_Enable:1; + unsigned long :5; + unsigned long HyperSpeedtransferControl1:1; + unsigned long :5; + unsigned long HyperSpeedtransferControl2:5; + unsigned long potpgt:8; + } BIT; + } EXT1; + union + { + unsigned long LONG; + struct + { + unsigned long EHCI_mask:1; + unsigned long HyperSpeedtransferControl3:1; + unsigned long :14; + unsigned long RUNRAMConnectCheck:1; + unsigned long RAMConnectCheckENDFlag:1; + unsigned long RAMConnectCheckResult:1; + unsigned long :13; + } BIT; + } EXT2; + char wk7[24]; + union + { + unsigned long LONG; + struct + { + unsigned long VendorID:16; + unsigned long DeviceID:16; + } BIT; + } VID_DID_E; + union + { + unsigned long LONG; + struct + { + unsigned long IOSpace:1; + unsigned long MemorySpace:1; + unsigned long BusMaster:1; + unsigned long SpecialCycle:1; + unsigned long MemoryWriteandInvalidateEnable:1; + unsigned long VGAPaletteSnoop:1; + unsigned long ParityErrorResponse:1; + unsigned long WaitCycleControl:1; + unsigned long SERREnable:1; + unsigned long FastBacktoBackEnable:1; + unsigned long :10; + unsigned long CapabilitiesList:1; + unsigned long Capable66MHz:1; + unsigned long :1; + unsigned long FastBacktoBackCapable:1; + unsigned long DataParityErrorDetected:1; + unsigned long DevselTiming:2; + unsigned long SignaledTargetAbort:1; + unsigned long ReceivedTargetAbort:1; + unsigned long ReceivedMasterAbort:1; + unsigned long SignaledSystemError:1; + unsigned long DetectedParityError:1; + } BIT; + } CMND_STS_E; + union + { + unsigned long LONG; + struct + { + unsigned long RevisionID:8; + unsigned long ProgrammingIF:8; + unsigned long SubClass:8; + unsigned long BaseClass:8; + } BIT; + } REVID_CC_E; + union + { + unsigned long LONG; + struct + { + unsigned long CacheLineSize:8; + unsigned long LatencyTimer:8; + unsigned long HeaderType:8; + unsigned long BIST:8; + } BIT; + } CLS_LT_HT_BIST_E; + union + { + unsigned long LONG; + struct + { + unsigned long MemorySpaceIndicator:1; + unsigned long Type:2; + unsigned long Prefetchable:1; + unsigned long EHCIBaseAddress:28; + } BIT; + } BASEAD_E; + char wk8[24]; + union + { + unsigned long LONG; + struct + { + unsigned long SubsystemVendorID:16; + unsigned long SubsystemID:16; + } BIT; + } SSVID_SSID_E; + union + { + unsigned long LONG; + struct + { + unsigned long ROMDecodeEnable:1; + unsigned long :9; + unsigned long ExpansionROMBaseAddress:22; + } BIT; + } EROM_BASEAD_E; + union + { + unsigned long LONG; + struct + { + unsigned long CapabilityPointer:8; + unsigned long :24; + } BIT; + } CAPPTR_E; + char wk9[4]; + union + { + unsigned long LONG; + struct + { + unsigned long InterruptLine:8; + unsigned long InterruptPin:8; + unsigned long MinGnt:8; + unsigned long MaxLatency:8; + } BIT; + } INTR_LINE_PIN_E; + union + { + unsigned long LONG; + struct + { + unsigned long CapabilityIdentifier:8; + unsigned long NextItemPointer:8; + unsigned long Version:3; + unsigned long PMECLK:1; + unsigned long :1; + unsigned long DSI:1; + unsigned long AUXCurrent:3; + unsigned long D1Support:1; + unsigned long D2Support:1; + unsigned long PMESupport:5; + } BIT; + } CAPID_NIP_PMCAP_E; + union + { + unsigned long LONG; + struct + { + unsigned long PowerState:2; + unsigned long :6; + unsigned long PMEEnable:1; + unsigned long DataSelect:4; + unsigned long DataScale:2; + unsigned long PMEStatus:1; + unsigned long :6; + unsigned long B2_B3:1; + unsigned long BPCCEnable:1; + unsigned long Data:8; + } BIT; + } PMC_STS_PMCSR_E; + char wk10[24]; + union + { + unsigned long LONG; + struct + { + unsigned long SBRN:8; + unsigned long FLADJ:8; + unsigned long PORTWAKECAP:16; + } BIT; + } SBRN_FLADJ_PW; + char wk11[124]; + unsigned long EXT1_E; + unsigned long EXT2_E; + char wk12[1560]; + union + { + unsigned long LONG; + struct + { + unsigned long PREFETCH:2; + unsigned long :26; + unsigned long AHB_BASEADR:4; + } BIT; + } PCIAHB_WIN1_CTR; + char wk13[12]; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long PCICMD:3; + unsigned long :7; + unsigned long PCIWIN1_BASEADR:21; + } BIT; + } AHBPCI_WIN1_CTR; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long PCICMD:3; + unsigned long :1; + unsigned long BURST_EN:1; + unsigned long :10; + unsigned long PCIWIN2_BASEADR:16; + } BIT; + } AHBPCI_WIN2_CTR; + char wk14[8]; + union + { + unsigned long LONG; + struct + { + unsigned long SIGTABORT_INTEN:1; + unsigned long RETABORT_INTEN:1; + unsigned long REMABORT_INTEN:1; + unsigned long PERR_INTEN:1; + unsigned long SIGSERR_INTEN:1; + unsigned long RESERR_INTEN:1; + unsigned long :6; + unsigned long PCIAHB_WIN1_INTEN:1; + unsigned long PCIAHB_WIN2_INTEN:1; + unsigned long :2; + unsigned long USBH_INTAEN:1; + unsigned long USBH_INTBEN:1; + unsigned long :1; + unsigned long USBH_PMEEN:1; + unsigned long :12; + } BIT; + } PCI_INT_ENABLE; + union + { + unsigned long LONG; + struct + { + unsigned long SIGTABORT_INT:1; + unsigned long RETABORT_INT:1; + unsigned long REMABORT_INT:1; + unsigned long PERR_INT:1; + unsigned long SIGSERR_INT:1; + unsigned long RESERR_INT:1; + unsigned long :6; + unsigned long PCIAHB_WIN1_INT:1; + unsigned long PCIAHB_WIN2_INT:1; + unsigned long :2; + unsigned long USBH_INTA:1; + unsigned long USBH_INTB:1; + unsigned long :1; + unsigned long USBH_PME:1; + unsigned long :12; + } BIT; + } PCI_INT_STATUS; + char wk15[8]; + union + { + unsigned long LONG; + struct + { + unsigned long MMODE_HTRANS:1; + unsigned long MMODE_BYTE_BURST:1; + unsigned long MMODE_WR_INCR:1; + unsigned long :4; + unsigned long MMODE_HBUSREQ:1; + unsigned long :9; + unsigned long SMODE_READY_CTR:1; + unsigned long :14; + } BIT; + } AHB_BUS_CTR; + union + { + unsigned long LONG; + struct + { + unsigned long USBH_RST:1; + unsigned long PCICLK_MASK:1; + unsigned long :7; + unsigned long PCI_AHB_WIN2_EN:1; + unsigned long PCI_AHB_WIN1_SIZE:2; + unsigned long :20; + } BIT; + } USBCTR; + char wk16[8]; + union + { + unsigned long LONG; + struct + { + unsigned long PCIREQ0:1; + unsigned long PCIREQ1:1; + unsigned long :10; + unsigned long PCIBP_MODE:1; + unsigned long :19; + } BIT; + } PCI_ARBITER_CTR; + char wk17[4]; + union + { + unsigned long LONG; + struct + { + unsigned long MinorRevisionID:16; + unsigned long MajorRevisionID:16; + } BIT; + } PCI_UNIT_REV; +}; + +struct st_vic +{ + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long IRQ1:1; + unsigned long IRQ2:1; + unsigned long IRQ3:1; + unsigned long IRQ4:1; + unsigned long IRQ5:1; + unsigned long IRQ6:1; + unsigned long IRQ7:1; + unsigned long IRQ8:1; + unsigned long IRQ9:1; + unsigned long IRQ10:1; + unsigned long IRQ11:1; + unsigned long IRQ12:1; + unsigned long IRQ13:1; + unsigned long IRQ14:1; + unsigned long IRQ15:1; + unsigned long IRQ16:1; + unsigned long IRQ17:1; + unsigned long IRQ18:1; + unsigned long IRQ19:1; + unsigned long IRQ20:1; + unsigned long IRQ21:1; + unsigned long IRQ22:1; + unsigned long IRQ23:1; + unsigned long IRQ24:1; + unsigned long IRQ25:1; + unsigned long IRQ26:1; + unsigned long IRQ27:1; + unsigned long IRQ28:1; + unsigned long IRQ29:1; + unsigned long IRQ30:1; + unsigned long IRQ31:1; + } BIT; + } IRQS0; + union + { + unsigned long LONG; + struct + { + unsigned long IRQ32:1; + unsigned long IRQ33:1; + unsigned long IRQ34:1; + unsigned long IRQ35:1; + unsigned long IRQ36:1; + unsigned long IRQ37:1; + unsigned long IRQ38:1; + unsigned long IRQ39:1; + unsigned long IRQ40:1; + unsigned long IRQ41:1; + unsigned long IRQ42:1; + unsigned long IRQ43:1; + unsigned long IRQ44:1; + unsigned long IRQ45:1; + unsigned long IRQ46:1; + unsigned long IRQ47:1; + unsigned long IRQ48:1; + unsigned long IRQ49:1; + unsigned long IRQ50:1; + unsigned long IRQ51:1; + unsigned long IRQ52:1; + unsigned long IRQ53:1; + unsigned long IRQ54:1; + unsigned long IRQ55:1; + unsigned long IRQ56:1; + unsigned long IRQ57:1; + unsigned long IRQ58:1; + unsigned long IRQ59:1; + unsigned long IRQ60:1; + unsigned long IRQ61:1; + unsigned long IRQ62:1; + unsigned long IRQ63:1; + } BIT; + } IRQS1; + union + { + unsigned long LONG; + struct + { + unsigned long IRQ64:1; + unsigned long IRQ65:1; + unsigned long IRQ66:1; + unsigned long IRQ67:1; + unsigned long IRQ68:1; + unsigned long IRQ69:1; + unsigned long IRQ70:1; + unsigned long IRQ71:1; + unsigned long IRQ72:1; + unsigned long IRQ73:1; + unsigned long IRQ74:1; + unsigned long IRQ75:1; + unsigned long IRQ76:1; + unsigned long IRQ77:1; + unsigned long IRQ78:1; + unsigned long IRQ79:1; + unsigned long IRQ80:1; + unsigned long IRQ81:1; + unsigned long IRQ82:1; + unsigned long IRQ83:1; + unsigned long IRQ84:1; + unsigned long IRQ85:1; + unsigned long IRQ86:1; + unsigned long IRQ87:1; + unsigned long IRQ88:1; + unsigned long IRQ89:1; + unsigned long IRQ90:1; + unsigned long IRQ91:1; + unsigned long IRQ92:1; + unsigned long IRQ93:1; + unsigned long IRQ94:1; + unsigned long IRQ95:1; + } BIT; + } IRQS2; + union + { + unsigned long LONG; + struct + { + unsigned long IRQ96:1; + unsigned long IRQ97:1; + unsigned long IRQ98:1; + unsigned long IRQ99:1; + unsigned long IRQ100:1; + unsigned long IRQ101:1; + unsigned long IRQ102:1; + unsigned long IRQ103:1; + unsigned long IRQ104:1; + unsigned long IRQ105:1; + unsigned long IRQ106:1; + unsigned long IRQ107:1; + unsigned long IRQ108:1; + unsigned long IRQ109:1; + unsigned long IRQ110:1; + unsigned long IRQ111:1; + unsigned long IRQ112:1; + unsigned long IRQ113:1; + unsigned long IRQ114:1; + unsigned long IRQ115:1; + unsigned long IRQ116:1; + unsigned long IRQ117:1; + unsigned long IRQ118:1; + unsigned long IRQ119:1; + unsigned long IRQ120:1; + unsigned long IRQ121:1; + unsigned long IRQ122:1; + unsigned long IRQ123:1; + unsigned long IRQ124:1; + unsigned long IRQ125:1; + unsigned long IRQ126:1; + unsigned long IRQ127:1; + } BIT; + } IRQS3; + union + { + unsigned long LONG; + struct + { + unsigned long IRQ128:1; + unsigned long IRQ129:1; + unsigned long IRQ130:1; + unsigned long IRQ131:1; + unsigned long IRQ132:1; + unsigned long IRQ133:1; + unsigned long IRQ134:1; + unsigned long IRQ135:1; + unsigned long IRQ136:1; + unsigned long IRQ137:1; + unsigned long IRQ138:1; + unsigned long IRQ139:1; + unsigned long IRQ140:1; + unsigned long IRQ141:1; + unsigned long IRQ142:1; + unsigned long IRQ143:1; + unsigned long IRQ144:1; + unsigned long IRQ145:1; + unsigned long IRQ146:1; + unsigned long IRQ147:1; + unsigned long IRQ148:1; + unsigned long IRQ149:1; + unsigned long IRQ150:1; + unsigned long IRQ151:1; + unsigned long IRQ152:1; + unsigned long IRQ153:1; + unsigned long IRQ154:1; + unsigned long IRQ155:1; + unsigned long IRQ156:1; + unsigned long IRQ157:1; + unsigned long IRQ158:1; + unsigned long IRQ159:1; + } BIT; + } IRQS4; + union + { + unsigned long LONG; + struct + { + unsigned long IRQ160:1; + unsigned long IRQ161:1; + unsigned long IRQ162:1; + unsigned long IRQ163:1; + unsigned long IRQ164:1; + unsigned long IRQ165:1; + unsigned long IRQ166:1; + unsigned long IRQ167:1; + unsigned long IRQ168:1; + unsigned long IRQ169:1; + unsigned long IRQ170:1; + unsigned long IRQ171:1; + unsigned long IRQ172:1; + unsigned long IRQ173:1; + unsigned long IRQ174:1; + unsigned long IRQ175:1; + unsigned long IRQ176:1; + unsigned long IRQ177:1; + unsigned long IRQ178:1; + unsigned long IRQ179:1; + unsigned long IRQ180:1; + unsigned long IRQ181:1; + unsigned long IRQ182:1; + unsigned long IRQ183:1; + unsigned long IRQ184:1; + unsigned long IRQ185:1; + unsigned long IRQ186:1; + unsigned long IRQ187:1; + unsigned long IRQ188:1; + unsigned long IRQ189:1; + unsigned long IRQ190:1; + unsigned long IRQ191:1; + } BIT; + } IRQS5; + union + { + unsigned long LONG; + struct + { + unsigned long IRQ192:1; + unsigned long IRQ193:1; + unsigned long IRQ194:1; + unsigned long IRQ195:1; + unsigned long IRQ196:1; + unsigned long IRQ197:1; + unsigned long IRQ198:1; + unsigned long IRQ199:1; + unsigned long IRQ200:1; + unsigned long IRQ201:1; + unsigned long IRQ202:1; + unsigned long IRQ203:1; + unsigned long IRQ204:1; + unsigned long IRQ205:1; + unsigned long IRQ206:1; + unsigned long IRQ207:1; + unsigned long IRQ208:1; + unsigned long IRQ209:1; + unsigned long IRQ210:1; + unsigned long IRQ211:1; + unsigned long IRQ212:1; + unsigned long IRQ213:1; + unsigned long IRQ214:1; + unsigned long IRQ215:1; + unsigned long IRQ216:1; + unsigned long IRQ217:1; + unsigned long IRQ218:1; + unsigned long IRQ219:1; + unsigned long IRQ220:1; + unsigned long IRQ221:1; + unsigned long IRQ222:1; + unsigned long IRQ223:1; + } BIT; + } IRQS6; + union + { + unsigned long LONG; + struct + { + unsigned long IRQ224:1; + unsigned long IRQ225:1; + unsigned long IRQ226:1; + unsigned long IRQ227:1; + unsigned long IRQ228:1; + unsigned long IRQ229:1; + unsigned long IRQ230:1; + unsigned long IRQ231:1; + unsigned long IRQ232:1; + unsigned long IRQ233:1; + unsigned long IRQ234:1; + unsigned long IRQ235:1; + unsigned long IRQ236:1; + unsigned long IRQ237:1; + unsigned long IRQ238:1; + unsigned long IRQ239:1; + unsigned long IRQ240:1; + unsigned long IRQ241:1; + unsigned long IRQ242:1; + unsigned long IRQ243:1; + unsigned long IRQ244:1; + unsigned long IRQ245:1; + unsigned long IRQ246:1; + unsigned long IRQ247:1; + unsigned long IRQ248:1; + unsigned long IRQ249:1; + unsigned long IRQ250:1; + unsigned long IRQ251:1; + unsigned long IRQ252:1; + unsigned long IRQ253:1; + unsigned long IRQ254:1; + unsigned long IRQ255:1; + } BIT; + } IRQS7; + char wk0[32]; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long RAI1:1; + unsigned long RAI2:1; + unsigned long RAI3:1; + unsigned long RAI4:1; + unsigned long RAI5:1; + unsigned long RAI6:1; + unsigned long RAI7:1; + unsigned long RAI8:1; + unsigned long RAI9:1; + unsigned long RAI10:1; + unsigned long RAI11:1; + unsigned long RAI12:1; + unsigned long RAI13:1; + unsigned long RAI14:1; + unsigned long RAI15:1; + unsigned long RAI16:1; + unsigned long RAI17:1; + unsigned long RAI18:1; + unsigned long RAI19:1; + unsigned long RAI20:1; + unsigned long RAI21:1; + unsigned long RAI22:1; + unsigned long RAI23:1; + unsigned long RAI24:1; + unsigned long RAI25:1; + unsigned long RAI26:1; + unsigned long RAI27:1; + unsigned long RAI28:1; + unsigned long RAI29:1; + unsigned long RAI30:1; + unsigned long RAI31:1; + } BIT; + } RAIS0; + union + { + unsigned long LONG; + struct + { + unsigned long RAI32:1; + unsigned long RAI33:1; + unsigned long RAI34:1; + unsigned long RAI35:1; + unsigned long RAI36:1; + unsigned long RAI37:1; + unsigned long RAI38:1; + unsigned long RAI39:1; + unsigned long RAI40:1; + unsigned long RAI41:1; + unsigned long RAI42:1; + unsigned long RAI43:1; + unsigned long RAI44:1; + unsigned long RAI45:1; + unsigned long RAI46:1; + unsigned long RAI47:1; + unsigned long RAI48:1; + unsigned long RAI49:1; + unsigned long RAI50:1; + unsigned long RAI51:1; + unsigned long RAI52:1; + unsigned long RAI53:1; + unsigned long RAI54:1; + unsigned long RAI55:1; + unsigned long RAI56:1; + unsigned long RAI57:1; + unsigned long RAI58:1; + unsigned long RAI59:1; + unsigned long RAI60:1; + unsigned long RAI61:1; + unsigned long RAI62:1; + unsigned long RAI63:1; + } BIT; + } RAIS1; + union + { + unsigned long LONG; + struct + { + unsigned long RAI64:1; + unsigned long RAI65:1; + unsigned long RAI66:1; + unsigned long RAI67:1; + unsigned long RAI68:1; + unsigned long RAI69:1; + unsigned long RAI70:1; + unsigned long RAI71:1; + unsigned long RAI72:1; + unsigned long RAI73:1; + unsigned long RAI74:1; + unsigned long RAI75:1; + unsigned long RAI76:1; + unsigned long RAI77:1; + unsigned long RAI78:1; + unsigned long RAI79:1; + unsigned long RAI80:1; + unsigned long RAI81:1; + unsigned long RAI82:1; + unsigned long RAI83:1; + unsigned long RAI84:1; + unsigned long RAI85:1; + unsigned long RAI86:1; + unsigned long RAI87:1; + unsigned long RAI88:1; + unsigned long RAI89:1; + unsigned long RAI90:1; + unsigned long RAI91:1; + unsigned long RAI92:1; + unsigned long RAI93:1; + unsigned long RAI94:1; + unsigned long RAI95:1; + } BIT; + } RAIS2; + union + { + unsigned long LONG; + struct + { + unsigned long RAI96:1; + unsigned long RAI97:1; + unsigned long RAI98:1; + unsigned long RAI99:1; + unsigned long RAI100:1; + unsigned long RAI101:1; + unsigned long RAI102:1; + unsigned long RAI103:1; + unsigned long RAI104:1; + unsigned long RAI105:1; + unsigned long RAI106:1; + unsigned long RAI107:1; + unsigned long RAI108:1; + unsigned long RAI109:1; + unsigned long RAI110:1; + unsigned long RAI111:1; + unsigned long RAI112:1; + unsigned long RAI113:1; + unsigned long RAI114:1; + unsigned long RAI115:1; + unsigned long RAI116:1; + unsigned long RAI117:1; + unsigned long RAI118:1; + unsigned long RAI119:1; + unsigned long RAI120:1; + unsigned long RAI121:1; + unsigned long RAI122:1; + unsigned long RAI123:1; + unsigned long RAI124:1; + unsigned long RAI125:1; + unsigned long RAI126:1; + unsigned long RAI127:1; + } BIT; + } RAIS3; + union + { + unsigned long LONG; + struct + { + unsigned long RAI128:1; + unsigned long RAI129:1; + unsigned long RAI130:1; + unsigned long RAI131:1; + unsigned long RAI132:1; + unsigned long RAI133:1; + unsigned long RAI134:1; + unsigned long RAI135:1; + unsigned long RAI136:1; + unsigned long RAI137:1; + unsigned long RAI138:1; + unsigned long RAI139:1; + unsigned long RAI140:1; + unsigned long RAI141:1; + unsigned long RAI142:1; + unsigned long RAI143:1; + unsigned long RAI144:1; + unsigned long RAI145:1; + unsigned long RAI146:1; + unsigned long RAI147:1; + unsigned long RAI148:1; + unsigned long RAI149:1; + unsigned long RAI150:1; + unsigned long RAI151:1; + unsigned long RAI152:1; + unsigned long RAI153:1; + unsigned long RAI154:1; + unsigned long RAI155:1; + unsigned long RAI156:1; + unsigned long RAI157:1; + unsigned long RAI158:1; + unsigned long RAI159:1; + } BIT; + } RAIS4; + union + { + unsigned long LONG; + struct + { + unsigned long RAI160:1; + unsigned long RAI161:1; + unsigned long RAI162:1; + unsigned long RAI163:1; + unsigned long RAI164:1; + unsigned long RAI165:1; + unsigned long RAI166:1; + unsigned long RAI167:1; + unsigned long RAI168:1; + unsigned long RAI169:1; + unsigned long RAI170:1; + unsigned long RAI171:1; + unsigned long RAI172:1; + unsigned long RAI173:1; + unsigned long RAI174:1; + unsigned long RAI175:1; + unsigned long RAI176:1; + unsigned long RAI177:1; + unsigned long RAI178:1; + unsigned long RAI179:1; + unsigned long RAI180:1; + unsigned long RAI181:1; + unsigned long RAI182:1; + unsigned long RAI183:1; + unsigned long RAI184:1; + unsigned long RAI185:1; + unsigned long RAI186:1; + unsigned long RAI187:1; + unsigned long RAI188:1; + unsigned long RAI189:1; + unsigned long RAI190:1; + unsigned long RAI191:1; + } BIT; + } RAIS5; + union + { + unsigned long LONG; + struct + { + unsigned long RAI192:1; + unsigned long RAI193:1; + unsigned long RAI194:1; + unsigned long RAI195:1; + unsigned long RAI196:1; + unsigned long RAI197:1; + unsigned long RAI198:1; + unsigned long RAI199:1; + unsigned long RAI200:1; + unsigned long RAI201:1; + unsigned long RAI202:1; + unsigned long RAI203:1; + unsigned long RAI204:1; + unsigned long RAI205:1; + unsigned long RAI206:1; + unsigned long RAI207:1; + unsigned long RAI208:1; + unsigned long RAI209:1; + unsigned long RAI210:1; + unsigned long RAI211:1; + unsigned long RAI212:1; + unsigned long RAI213:1; + unsigned long RAI214:1; + unsigned long RAI215:1; + unsigned long RAI216:1; + unsigned long RAI217:1; + unsigned long RAI218:1; + unsigned long RAI219:1; + unsigned long RAI220:1; + unsigned long RAI221:1; + unsigned long RAI222:1; + unsigned long RAI223:1; + } BIT; + } RAIS6; + union + { + unsigned long LONG; + struct + { + unsigned long RAI224:1; + unsigned long RAI225:1; + unsigned long RAI226:1; + unsigned long RAI227:1; + unsigned long RAI228:1; + unsigned long RAI229:1; + unsigned long RAI230:1; + unsigned long RAI231:1; + unsigned long RAI232:1; + unsigned long RAI233:1; + unsigned long RAI234:1; + unsigned long RAI235:1; + unsigned long RAI236:1; + unsigned long RAI237:1; + unsigned long RAI238:1; + unsigned long RAI239:1; + unsigned long RAI240:1; + unsigned long RAI241:1; + unsigned long RAI242:1; + unsigned long RAI243:1; + unsigned long RAI244:1; + unsigned long RAI245:1; + unsigned long RAI246:1; + unsigned long RAI247:1; + unsigned long RAI248:1; + unsigned long RAI249:1; + unsigned long RAI250:1; + unsigned long RAI251:1; + unsigned long RAI252:1; + unsigned long RAI253:1; + unsigned long RAI254:1; + unsigned long RAI255:1; + } BIT; + } RAIS7; + char wk1[32]; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long IEN1:1; + unsigned long IEN2:1; + unsigned long IEN3:1; + unsigned long IEN4:1; + unsigned long IEN5:1; + unsigned long IEN6:1; + unsigned long IEN7:1; + unsigned long IEN8:1; + unsigned long IEN9:1; + unsigned long IEN10:1; + unsigned long IEN11:1; + unsigned long IEN12:1; + unsigned long IEN13:1; + unsigned long IEN14:1; + unsigned long IEN15:1; + unsigned long IEN16:1; + unsigned long IEN17:1; + unsigned long IEN18:1; + unsigned long IEN19:1; + unsigned long IEN20:1; + unsigned long IEN21:1; + unsigned long IEN22:1; + unsigned long IEN23:1; + unsigned long IEN24:1; + unsigned long IEN25:1; + unsigned long IEN26:1; + unsigned long IEN27:1; + unsigned long IEN28:1; + unsigned long IEN29:1; + unsigned long IEN30:1; + unsigned long IEN31:1; + } BIT; + } IEN0; + union + { + unsigned long LONG; + struct + { + unsigned long IEN32:1; + unsigned long IEN33:1; + unsigned long IEN34:1; + unsigned long IEN35:1; + unsigned long IEN36:1; + unsigned long IEN37:1; + unsigned long IEN38:1; + unsigned long IEN39:1; + unsigned long IEN40:1; + unsigned long IEN41:1; + unsigned long IEN42:1; + unsigned long IEN43:1; + unsigned long IEN44:1; + unsigned long IEN45:1; + unsigned long IEN46:1; + unsigned long IEN47:1; + unsigned long IEN48:1; + unsigned long IEN49:1; + unsigned long IEN50:1; + unsigned long IEN51:1; + unsigned long IEN52:1; + unsigned long IEN53:1; + unsigned long IEN54:1; + unsigned long IEN55:1; + unsigned long IEN56:1; + unsigned long IEN57:1; + unsigned long IEN58:1; + unsigned long IEN59:1; + unsigned long IEN60:1; + unsigned long IEN61:1; + unsigned long IEN62:1; + unsigned long IEN63:1; + } BIT; + } IEN1; + union + { + unsigned long LONG; + struct + { + unsigned long IEN64:1; + unsigned long IEN65:1; + unsigned long IEN66:1; + unsigned long IEN67:1; + unsigned long IEN68:1; + unsigned long IEN69:1; + unsigned long IEN70:1; + unsigned long IEN71:1; + unsigned long IEN72:1; + unsigned long IEN73:1; + unsigned long IEN74:1; + unsigned long IEN75:1; + unsigned long IEN76:1; + unsigned long IEN77:1; + unsigned long IEN78:1; + unsigned long IEN79:1; + unsigned long IEN80:1; + unsigned long IEN81:1; + unsigned long IEN82:1; + unsigned long IEN83:1; + unsigned long IEN84:1; + unsigned long IEN85:1; + unsigned long IEN86:1; + unsigned long IEN87:1; + unsigned long IEN88:1; + unsigned long IEN89:1; + unsigned long IEN90:1; + unsigned long IEN91:1; + unsigned long IEN92:1; + unsigned long IEN93:1; + unsigned long IEN94:1; + unsigned long IEN95:1; + } BIT; + } IEN2; + union + { + unsigned long LONG; + struct + { + unsigned long IEN96:1; + unsigned long IEN97:1; + unsigned long IEN98:1; + unsigned long IEN99:1; + unsigned long IEN100:1; + unsigned long IEN101:1; + unsigned long IEN102:1; + unsigned long IEN103:1; + unsigned long IEN104:1; + unsigned long IEN105:1; + unsigned long IEN106:1; + unsigned long IEN107:1; + unsigned long IEN108:1; + unsigned long IEN109:1; + unsigned long IEN110:1; + unsigned long IEN111:1; + unsigned long IEN112:1; + unsigned long IEN113:1; + unsigned long IEN114:1; + unsigned long IEN115:1; + unsigned long IEN116:1; + unsigned long IEN117:1; + unsigned long IEN118:1; + unsigned long IEN119:1; + unsigned long IEN120:1; + unsigned long IEN121:1; + unsigned long IEN122:1; + unsigned long IEN123:1; + unsigned long IEN124:1; + unsigned long IEN125:1; + unsigned long IEN126:1; + unsigned long IEN127:1; + } BIT; + } IEN3; + union + { + unsigned long LONG; + struct + { + unsigned long IEN128:1; + unsigned long IEN129:1; + unsigned long IEN130:1; + unsigned long IEN131:1; + unsigned long IEN132:1; + unsigned long IEN133:1; + unsigned long IEN134:1; + unsigned long IEN135:1; + unsigned long IEN136:1; + unsigned long IEN137:1; + unsigned long IEN138:1; + unsigned long IEN139:1; + unsigned long IEN140:1; + unsigned long IEN141:1; + unsigned long IEN142:1; + unsigned long IEN143:1; + unsigned long IEN144:1; + unsigned long IEN145:1; + unsigned long IEN146:1; + unsigned long IEN147:1; + unsigned long IEN148:1; + unsigned long IEN149:1; + unsigned long IEN150:1; + unsigned long IEN151:1; + unsigned long IEN152:1; + unsigned long IEN153:1; + unsigned long IEN154:1; + unsigned long IEN155:1; + unsigned long IEN156:1; + unsigned long IEN157:1; + unsigned long IEN158:1; + unsigned long IEN159:1; + } BIT; + } IEN4; + union + { + unsigned long LONG; + struct + { + unsigned long IEN160:1; + unsigned long IEN161:1; + unsigned long IEN162:1; + unsigned long IEN163:1; + unsigned long IEN164:1; + unsigned long IEN165:1; + unsigned long IEN166:1; + unsigned long IEN167:1; + unsigned long IEN168:1; + unsigned long IEN169:1; + unsigned long IEN170:1; + unsigned long IEN171:1; + unsigned long IEN172:1; + unsigned long IEN173:1; + unsigned long IEN174:1; + unsigned long IEN175:1; + unsigned long IEN176:1; + unsigned long IEN177:1; + unsigned long IEN178:1; + unsigned long IEN179:1; + unsigned long IEN180:1; + unsigned long IEN181:1; + unsigned long IEN182:1; + unsigned long IEN183:1; + unsigned long IEN184:1; + unsigned long IEN185:1; + unsigned long IEN186:1; + unsigned long IEN187:1; + unsigned long IEN188:1; + unsigned long IEN189:1; + unsigned long IEN190:1; + unsigned long IEN191:1; + } BIT; + } IEN5; + union + { + unsigned long LONG; + struct + { + unsigned long IEN192:1; + unsigned long IEN193:1; + unsigned long IEN194:1; + unsigned long IEN195:1; + unsigned long IEN196:1; + unsigned long IEN197:1; + unsigned long IEN198:1; + unsigned long IEN199:1; + unsigned long IEN200:1; + unsigned long IEN201:1; + unsigned long IEN202:1; + unsigned long IEN203:1; + unsigned long IEN204:1; + unsigned long IEN205:1; + unsigned long IEN206:1; + unsigned long IEN207:1; + unsigned long IEN208:1; + unsigned long IEN209:1; + unsigned long IEN210:1; + unsigned long IEN211:1; + unsigned long IEN212:1; + unsigned long IEN213:1; + unsigned long IEN214:1; + unsigned long IEN215:1; + unsigned long IEN216:1; + unsigned long IEN217:1; + unsigned long IEN218:1; + unsigned long IEN219:1; + unsigned long IEN220:1; + unsigned long IEN221:1; + unsigned long IEN222:1; + unsigned long IEN223:1; + } BIT; + } IEN6; + union + { + unsigned long LONG; + struct + { + unsigned long IEN224:1; + unsigned long IEN225:1; + unsigned long IEN226:1; + unsigned long IEN227:1; + unsigned long IEN228:1; + unsigned long IEN229:1; + unsigned long IEN230:1; + unsigned long IEN231:1; + unsigned long IEN232:1; + unsigned long IEN233:1; + unsigned long IEN234:1; + unsigned long IEN235:1; + unsigned long IEN236:1; + unsigned long IEN237:1; + unsigned long IEN238:1; + unsigned long IEN239:1; + unsigned long IEN240:1; + unsigned long IEN241:1; + unsigned long IEN242:1; + unsigned long IEN243:1; + unsigned long IEN244:1; + unsigned long IEN245:1; + unsigned long IEN246:1; + unsigned long IEN247:1; + unsigned long IEN248:1; + unsigned long IEN249:1; + unsigned long IEN250:1; + unsigned long IEN251:1; + unsigned long IEN252:1; + unsigned long IEN253:1; + unsigned long IEN254:1; + unsigned long IEN255:1; + } BIT; + } IEN7; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long IEC1:1; + unsigned long IEC2:1; + unsigned long IEC3:1; + unsigned long IEC4:1; + unsigned long IEC5:1; + unsigned long IEC6:1; + unsigned long IEC7:1; + unsigned long IEC8:1; + unsigned long IEC9:1; + unsigned long IEC10:1; + unsigned long IEC11:1; + unsigned long IEC12:1; + unsigned long IEC13:1; + unsigned long IEC14:1; + unsigned long IEC15:1; + unsigned long IEC16:1; + unsigned long IEC17:1; + unsigned long IEC18:1; + unsigned long IEC19:1; + unsigned long IEC20:1; + unsigned long IEC21:1; + unsigned long IEC22:1; + unsigned long IEC23:1; + unsigned long IEC24:1; + unsigned long IEC25:1; + unsigned long IEC26:1; + unsigned long IEC27:1; + unsigned long IEC28:1; + unsigned long IEC29:1; + unsigned long IEC30:1; + unsigned long IEC31:1; + } BIT; + } IEC0; + union + { + unsigned long LONG; + struct + { + unsigned long IEC32:1; + unsigned long IEC33:1; + unsigned long IEC34:1; + unsigned long IEC35:1; + unsigned long IEC36:1; + unsigned long IEC37:1; + unsigned long IEC38:1; + unsigned long IEC39:1; + unsigned long IEC40:1; + unsigned long IEC41:1; + unsigned long IEC42:1; + unsigned long IEC43:1; + unsigned long IEC44:1; + unsigned long IEC45:1; + unsigned long IEC46:1; + unsigned long IEC47:1; + unsigned long IEC48:1; + unsigned long IEC49:1; + unsigned long IEC50:1; + unsigned long IEC51:1; + unsigned long IEC52:1; + unsigned long IEC53:1; + unsigned long IEC54:1; + unsigned long IEC55:1; + unsigned long IEC56:1; + unsigned long IEC57:1; + unsigned long IEC58:1; + unsigned long IEC59:1; + unsigned long IEC60:1; + unsigned long IEC61:1; + unsigned long IEC62:1; + unsigned long IEC63:1; + } BIT; + } IEC1; + union + { + unsigned long LONG; + struct + { + unsigned long IEC64:1; + unsigned long IEC65:1; + unsigned long IEC66:1; + unsigned long IEC67:1; + unsigned long IEC68:1; + unsigned long IEC69:1; + unsigned long IEC70:1; + unsigned long IEC71:1; + unsigned long IEC72:1; + unsigned long IEC73:1; + unsigned long IEC74:1; + unsigned long IEC75:1; + unsigned long IEC76:1; + unsigned long IEC77:1; + unsigned long IEC78:1; + unsigned long IEC79:1; + unsigned long IEC80:1; + unsigned long IEC81:1; + unsigned long IEC82:1; + unsigned long IEC83:1; + unsigned long IEC84:1; + unsigned long IEC85:1; + unsigned long IEC86:1; + unsigned long IEC87:1; + unsigned long IEC88:1; + unsigned long IEC89:1; + unsigned long IEC90:1; + unsigned long IEC91:1; + unsigned long IEC92:1; + unsigned long IEC93:1; + unsigned long IEC94:1; + unsigned long IEC95:1; + } BIT; + } IEC2; + union + { + unsigned long LONG; + struct + { + unsigned long IEC96:1; + unsigned long IEC97:1; + unsigned long IEC98:1; + unsigned long IEC99:1; + unsigned long IEC100:1; + unsigned long IEC101:1; + unsigned long IEC102:1; + unsigned long IEC103:1; + unsigned long IEC104:1; + unsigned long IEC105:1; + unsigned long IEC106:1; + unsigned long IEC107:1; + unsigned long IEC108:1; + unsigned long IEC109:1; + unsigned long IEC110:1; + unsigned long IEC111:1; + unsigned long IEC112:1; + unsigned long IEC113:1; + unsigned long IEC114:1; + unsigned long IEC115:1; + unsigned long IEC116:1; + unsigned long IEC117:1; + unsigned long IEC118:1; + unsigned long IEC119:1; + unsigned long IEC120:1; + unsigned long IEC121:1; + unsigned long IEC122:1; + unsigned long IEC123:1; + unsigned long IEC124:1; + unsigned long IEC125:1; + unsigned long IEC126:1; + unsigned long IEC127:1; + } BIT; + } IEC3; + union + { + unsigned long LONG; + struct + { + unsigned long IEC128:1; + unsigned long IEC129:1; + unsigned long IEC130:1; + unsigned long IEC131:1; + unsigned long IEC132:1; + unsigned long IEC133:1; + unsigned long IEC134:1; + unsigned long IEC135:1; + unsigned long IEC136:1; + unsigned long IEC137:1; + unsigned long IEC138:1; + unsigned long IEC139:1; + unsigned long IEC140:1; + unsigned long IEC141:1; + unsigned long IEC142:1; + unsigned long IEC143:1; + unsigned long IEC144:1; + unsigned long IEC145:1; + unsigned long IEC146:1; + unsigned long IEC147:1; + unsigned long IEC148:1; + unsigned long IEC149:1; + unsigned long IEC150:1; + unsigned long IEC151:1; + unsigned long IEC152:1; + unsigned long IEC153:1; + unsigned long IEC154:1; + unsigned long IEC155:1; + unsigned long IEC156:1; + unsigned long IEC157:1; + unsigned long IEC158:1; + unsigned long IEC159:1; + } BIT; + } IEC4; + union + { + unsigned long LONG; + struct + { + unsigned long IEC160:1; + unsigned long IEC161:1; + unsigned long IEC162:1; + unsigned long IEC163:1; + unsigned long IEC164:1; + unsigned long IEC165:1; + unsigned long IEC166:1; + unsigned long IEC167:1; + unsigned long IEC168:1; + unsigned long IEC169:1; + unsigned long IEC170:1; + unsigned long IEC171:1; + unsigned long IEC172:1; + unsigned long IEC173:1; + unsigned long IEC174:1; + unsigned long IEC175:1; + unsigned long IEC176:1; + unsigned long IEC177:1; + unsigned long IEC178:1; + unsigned long IEC179:1; + unsigned long IEC180:1; + unsigned long IEC181:1; + unsigned long IEC182:1; + unsigned long IEC183:1; + unsigned long IEC184:1; + unsigned long IEC185:1; + unsigned long IEC186:1; + unsigned long IEC187:1; + unsigned long IEC188:1; + unsigned long IEC189:1; + unsigned long IEC190:1; + unsigned long IEC191:1; + } BIT; + } IEC5; + union + { + unsigned long LONG; + struct + { + unsigned long IEC192:1; + unsigned long IEC193:1; + unsigned long IEC194:1; + unsigned long IEC195:1; + unsigned long IEC196:1; + unsigned long IEC197:1; + unsigned long IEC198:1; + unsigned long IEC199:1; + unsigned long IEC200:1; + unsigned long IEC201:1; + unsigned long IEC202:1; + unsigned long IEC203:1; + unsigned long IEC204:1; + unsigned long IEC205:1; + unsigned long IEC206:1; + unsigned long IEC207:1; + unsigned long IEC208:1; + unsigned long IEC209:1; + unsigned long IEC210:1; + unsigned long IEC211:1; + unsigned long IEC212:1; + unsigned long IEC213:1; + unsigned long IEC214:1; + unsigned long IEC215:1; + unsigned long IEC216:1; + unsigned long IEC217:1; + unsigned long IEC218:1; + unsigned long IEC219:1; + unsigned long IEC220:1; + unsigned long IEC221:1; + unsigned long IEC222:1; + unsigned long IEC223:1; + } BIT; + } IEC6; + union + { + unsigned long LONG; + struct + { + unsigned long IEC224:1; + unsigned long IEC225:1; + unsigned long IEC226:1; + unsigned long IEC227:1; + unsigned long IEC228:1; + unsigned long IEC229:1; + unsigned long IEC230:1; + unsigned long IEC231:1; + unsigned long IEC232:1; + unsigned long IEC233:1; + unsigned long IEC234:1; + unsigned long IEC235:1; + unsigned long IEC236:1; + unsigned long IEC237:1; + unsigned long IEC238:1; + unsigned long IEC239:1; + unsigned long IEC240:1; + unsigned long IEC241:1; + unsigned long IEC242:1; + unsigned long IEC243:1; + unsigned long IEC244:1; + unsigned long IEC245:1; + unsigned long IEC246:1; + unsigned long IEC247:1; + unsigned long IEC248:1; + unsigned long IEC249:1; + unsigned long IEC250:1; + unsigned long IEC251:1; + unsigned long IEC252:1; + unsigned long IEC253:1; + unsigned long IEC254:1; + unsigned long IEC255:1; + } BIT; + } IEC7; + char wk2[64]; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long PLS1:1; + unsigned long PLS2:1; + unsigned long PLS3:1; + unsigned long PLS4:1; + unsigned long PLS5:1; + unsigned long PLS6:1; + unsigned long PLS7:1; + unsigned long PLS8:1; + unsigned long PLS9:1; + unsigned long PLS10:1; + unsigned long PLS11:1; + unsigned long PLS12:1; + unsigned long PLS13:1; + unsigned long PLS14:1; + unsigned long PLS15:1; + unsigned long PLS16:1; + unsigned long PLS17:1; + unsigned long PLS18:1; + unsigned long PLS19:1; + unsigned long PLS20:1; + unsigned long PLS21:1; + unsigned long PLS22:1; + unsigned long PLS23:1; + unsigned long PLS24:1; + unsigned long PLS25:1; + unsigned long PLS26:1; + unsigned long PLS27:1; + unsigned long PLS28:1; + unsigned long PLS29:1; + unsigned long PLS30:1; + unsigned long PLS31:1; + } BIT; + } PLS0; + union + { + unsigned long LONG; + struct + { + unsigned long PLS32:1; + unsigned long PLS33:1; + unsigned long PLS34:1; + unsigned long PLS35:1; + unsigned long PLS36:1; + unsigned long PLS37:1; + unsigned long PLS38:1; + unsigned long PLS39:1; + unsigned long PLS40:1; + unsigned long PLS41:1; + unsigned long PLS42:1; + unsigned long PLS43:1; + unsigned long PLS44:1; + unsigned long PLS45:1; + unsigned long PLS46:1; + unsigned long PLS47:1; + unsigned long PLS48:1; + unsigned long PLS49:1; + unsigned long PLS50:1; + unsigned long PLS51:1; + unsigned long PLS52:1; + unsigned long PLS53:1; + unsigned long PLS54:1; + unsigned long PLS55:1; + unsigned long PLS56:1; + unsigned long PLS57:1; + unsigned long PLS58:1; + unsigned long PLS59:1; + unsigned long PLS60:1; + unsigned long PLS61:1; + unsigned long PLS62:1; + unsigned long PLS63:1; + } BIT; + } PLS1; + union + { + unsigned long LONG; + struct + { + unsigned long PLS64:1; + unsigned long PLS65:1; + unsigned long PLS66:1; + unsigned long PLS67:1; + unsigned long PLS68:1; + unsigned long PLS69:1; + unsigned long PLS70:1; + unsigned long PLS71:1; + unsigned long PLS72:1; + unsigned long PLS73:1; + unsigned long PLS74:1; + unsigned long PLS75:1; + unsigned long PLS76:1; + unsigned long PLS77:1; + unsigned long PLS78:1; + unsigned long PLS79:1; + unsigned long PLS80:1; + unsigned long PLS81:1; + unsigned long PLS82:1; + unsigned long PLS83:1; + unsigned long PLS84:1; + unsigned long PLS85:1; + unsigned long PLS86:1; + unsigned long PLS87:1; + unsigned long PLS88:1; + unsigned long PLS89:1; + unsigned long PLS90:1; + unsigned long PLS91:1; + unsigned long PLS92:1; + unsigned long PLS93:1; + unsigned long PLS94:1; + unsigned long PLS95:1; + } BIT; + } PLS2; + union + { + unsigned long LONG; + struct + { + unsigned long PLS96:1; + unsigned long PLS97:1; + unsigned long PLS98:1; + unsigned long PLS99:1; + unsigned long PLS100:1; + unsigned long PLS101:1; + unsigned long PLS102:1; + unsigned long PLS103:1; + unsigned long PLS104:1; + unsigned long PLS105:1; + unsigned long PLS106:1; + unsigned long PLS107:1; + unsigned long PLS108:1; + unsigned long PLS109:1; + unsigned long PLS110:1; + unsigned long PLS111:1; + unsigned long PLS112:1; + unsigned long PLS113:1; + unsigned long PLS114:1; + unsigned long PLS115:1; + unsigned long PLS116:1; + unsigned long PLS117:1; + unsigned long PLS118:1; + unsigned long PLS119:1; + unsigned long PLS120:1; + unsigned long PLS121:1; + unsigned long PLS122:1; + unsigned long PLS123:1; + unsigned long PLS124:1; + unsigned long PLS125:1; + unsigned long PLS126:1; + unsigned long PLS127:1; + } BIT; + } PLS3; + union + { + unsigned long LONG; + struct + { + unsigned long PLS128:1; + unsigned long PLS129:1; + unsigned long PLS130:1; + unsigned long PLS131:1; + unsigned long PLS132:1; + unsigned long PLS133:1; + unsigned long PLS134:1; + unsigned long PLS135:1; + unsigned long PLS136:1; + unsigned long PLS137:1; + unsigned long PLS138:1; + unsigned long PLS139:1; + unsigned long PLS140:1; + unsigned long PLS141:1; + unsigned long PLS142:1; + unsigned long PLS143:1; + unsigned long PLS144:1; + unsigned long PLS145:1; + unsigned long PLS146:1; + unsigned long PLS147:1; + unsigned long PLS148:1; + unsigned long PLS149:1; + unsigned long PLS150:1; + unsigned long PLS151:1; + unsigned long PLS152:1; + unsigned long PLS153:1; + unsigned long PLS154:1; + unsigned long PLS155:1; + unsigned long PLS156:1; + unsigned long PLS157:1; + unsigned long PLS158:1; + unsigned long PLS159:1; + } BIT; + } PLS4; + union + { + unsigned long LONG; + struct + { + unsigned long PLS160:1; + unsigned long PLS161:1; + unsigned long PLS162:1; + unsigned long PLS163:1; + unsigned long PLS164:1; + unsigned long PLS165:1; + unsigned long PLS166:1; + unsigned long PLS167:1; + unsigned long PLS168:1; + unsigned long PLS169:1; + unsigned long PLS170:1; + unsigned long PLS171:1; + unsigned long PLS172:1; + unsigned long PLS173:1; + unsigned long PLS174:1; + unsigned long PLS175:1; + unsigned long PLS176:1; + unsigned long PLS177:1; + unsigned long PLS178:1; + unsigned long PLS179:1; + unsigned long PLS180:1; + unsigned long PLS181:1; + unsigned long PLS182:1; + unsigned long PLS183:1; + unsigned long PLS184:1; + unsigned long PLS185:1; + unsigned long PLS186:1; + unsigned long PLS187:1; + unsigned long PLS188:1; + unsigned long PLS189:1; + unsigned long PLS190:1; + unsigned long PLS191:1; + } BIT; + } PLS5; + union + { + unsigned long LONG; + struct + { + unsigned long PLS192:1; + unsigned long PLS193:1; + unsigned long PLS194:1; + unsigned long PLS195:1; + unsigned long PLS196:1; + unsigned long PLS197:1; + unsigned long PLS198:1; + unsigned long PLS199:1; + unsigned long PLS200:1; + unsigned long PLS201:1; + unsigned long PLS202:1; + unsigned long PLS203:1; + unsigned long PLS204:1; + unsigned long PLS205:1; + unsigned long PLS206:1; + unsigned long PLS207:1; + unsigned long PLS208:1; + unsigned long PLS209:1; + unsigned long PLS210:1; + unsigned long PLS211:1; + unsigned long PLS212:1; + unsigned long PLS213:1; + unsigned long PLS214:1; + unsigned long PLS215:1; + unsigned long PLS216:1; + unsigned long PLS217:1; + unsigned long PLS218:1; + unsigned long PLS219:1; + unsigned long PLS220:1; + unsigned long PLS221:1; + unsigned long PLS222:1; + unsigned long PLS223:1; + } BIT; + } PLS6; + union + { + unsigned long LONG; + struct + { + unsigned long PLS224:1; + unsigned long PLS225:1; + unsigned long PLS226:1; + unsigned long PLS227:1; + unsigned long PLS228:1; + unsigned long PLS229:1; + unsigned long PLS230:1; + unsigned long PLS231:1; + unsigned long PLS232:1; + unsigned long PLS233:1; + unsigned long PLS234:1; + unsigned long PLS235:1; + unsigned long PLS236:1; + unsigned long PLS237:1; + unsigned long PLS238:1; + unsigned long PLS239:1; + unsigned long PLS240:1; + unsigned long PLS241:1; + unsigned long PLS242:1; + unsigned long PLS243:1; + unsigned long PLS244:1; + unsigned long PLS245:1; + unsigned long PLS246:1; + unsigned long PLS247:1; + unsigned long PLS248:1; + unsigned long PLS249:1; + unsigned long PLS250:1; + unsigned long PLS251:1; + unsigned long PLS252:1; + unsigned long PLS253:1; + unsigned long PLS254:1; + unsigned long PLS255:1; + } BIT; + } PLS7; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long PIC1:1; + unsigned long PIC2:1; + unsigned long PIC3:1; + unsigned long PIC4:1; + unsigned long PIC5:1; + unsigned long PIC6:1; + unsigned long PIC7:1; + unsigned long PIC8:1; + unsigned long PIC9:1; + unsigned long PIC10:1; + unsigned long PIC11:1; + unsigned long PIC12:1; + unsigned long PIC13:1; + unsigned long PIC14:1; + unsigned long PIC15:1; + unsigned long PIC16:1; + unsigned long PIC17:1; + unsigned long PIC18:1; + unsigned long PIC19:1; + unsigned long PIC20:1; + unsigned long PIC21:1; + unsigned long PIC22:1; + unsigned long PIC23:1; + unsigned long PIC24:1; + unsigned long PIC25:1; + unsigned long PIC26:1; + unsigned long PIC27:1; + unsigned long PIC28:1; + unsigned long PIC29:1; + unsigned long PIC30:1; + unsigned long PIC31:1; + } BIT; + } PIC0; + union + { + unsigned long LONG; + struct + { + unsigned long PIC32:1; + unsigned long PIC33:1; + unsigned long PIC34:1; + unsigned long PIC35:1; + unsigned long PIC36:1; + unsigned long PIC37:1; + unsigned long PIC38:1; + unsigned long PIC39:1; + unsigned long PIC40:1; + unsigned long PIC41:1; + unsigned long PIC42:1; + unsigned long PIC43:1; + unsigned long PIC44:1; + unsigned long PIC45:1; + unsigned long PIC46:1; + unsigned long PIC47:1; + unsigned long PIC48:1; + unsigned long PIC49:1; + unsigned long PIC50:1; + unsigned long PIC51:1; + unsigned long PIC52:1; + unsigned long PIC53:1; + unsigned long PIC54:1; + unsigned long PIC55:1; + unsigned long PIC56:1; + unsigned long PIC57:1; + unsigned long PIC58:1; + unsigned long PIC59:1; + unsigned long PIC60:1; + unsigned long PIC61:1; + unsigned long PIC62:1; + unsigned long PIC63:1; + } BIT; + } PIC1; + union + { + unsigned long LONG; + struct + { + unsigned long PIC64:1; + unsigned long PIC65:1; + unsigned long PIC66:1; + unsigned long PIC67:1; + unsigned long PIC68:1; + unsigned long PIC69:1; + unsigned long PIC70:1; + unsigned long PIC71:1; + unsigned long PIC72:1; + unsigned long PIC73:1; + unsigned long PIC74:1; + unsigned long PIC75:1; + unsigned long PIC76:1; + unsigned long PIC77:1; + unsigned long PIC78:1; + unsigned long PIC79:1; + unsigned long PIC80:1; + unsigned long PIC81:1; + unsigned long PIC82:1; + unsigned long PIC83:1; + unsigned long PIC84:1; + unsigned long PIC85:1; + unsigned long PIC86:1; + unsigned long PIC87:1; + unsigned long PIC88:1; + unsigned long PIC89:1; + unsigned long PIC90:1; + unsigned long PIC91:1; + unsigned long PIC92:1; + unsigned long PIC93:1; + unsigned long PIC94:1; + unsigned long PIC95:1; + } BIT; + } PIC2; + union + { + unsigned long LONG; + struct + { + unsigned long PIC96:1; + unsigned long PIC97:1; + unsigned long PIC98:1; + unsigned long PIC99:1; + unsigned long PIC100:1; + unsigned long PIC101:1; + unsigned long PIC102:1; + unsigned long PIC103:1; + unsigned long PIC104:1; + unsigned long PIC105:1; + unsigned long PIC106:1; + unsigned long PIC107:1; + unsigned long PIC108:1; + unsigned long PIC109:1; + unsigned long PIC110:1; + unsigned long PIC111:1; + unsigned long PIC112:1; + unsigned long PIC113:1; + unsigned long PIC114:1; + unsigned long PIC115:1; + unsigned long PIC116:1; + unsigned long PIC117:1; + unsigned long PIC118:1; + unsigned long PIC119:1; + unsigned long PIC120:1; + unsigned long PIC121:1; + unsigned long PIC122:1; + unsigned long PIC123:1; + unsigned long PIC124:1; + unsigned long PIC125:1; + unsigned long PIC126:1; + unsigned long PIC127:1; + } BIT; + } PIC3; + union + { + unsigned long LONG; + struct + { + unsigned long PIC128:1; + unsigned long PIC129:1; + unsigned long PIC130:1; + unsigned long PIC131:1; + unsigned long PIC132:1; + unsigned long PIC133:1; + unsigned long PIC134:1; + unsigned long PIC135:1; + unsigned long PIC136:1; + unsigned long PIC137:1; + unsigned long PIC138:1; + unsigned long PIC139:1; + unsigned long PIC140:1; + unsigned long PIC141:1; + unsigned long PIC142:1; + unsigned long PIC143:1; + unsigned long PIC144:1; + unsigned long PIC145:1; + unsigned long PIC146:1; + unsigned long PIC147:1; + unsigned long PIC148:1; + unsigned long PIC149:1; + unsigned long PIC150:1; + unsigned long PIC151:1; + unsigned long PIC152:1; + unsigned long PIC153:1; + unsigned long PIC154:1; + unsigned long PIC155:1; + unsigned long PIC156:1; + unsigned long PIC157:1; + unsigned long PIC158:1; + unsigned long PIC159:1; + } BIT; + } PIC4; + union + { + unsigned long LONG; + struct + { + unsigned long PIC160:1; + unsigned long PIC161:1; + unsigned long PIC162:1; + unsigned long PIC163:1; + unsigned long PIC164:1; + unsigned long PIC165:1; + unsigned long PIC166:1; + unsigned long PIC167:1; + unsigned long PIC168:1; + unsigned long PIC169:1; + unsigned long PIC170:1; + unsigned long PIC171:1; + unsigned long PIC172:1; + unsigned long PIC173:1; + unsigned long PIC174:1; + unsigned long PIC175:1; + unsigned long PIC176:1; + unsigned long PIC177:1; + unsigned long PIC178:1; + unsigned long PIC179:1; + unsigned long PIC180:1; + unsigned long PIC181:1; + unsigned long PIC182:1; + unsigned long PIC183:1; + unsigned long PIC184:1; + unsigned long PIC185:1; + unsigned long PIC186:1; + unsigned long PIC187:1; + unsigned long PIC188:1; + unsigned long PIC189:1; + unsigned long PIC190:1; + unsigned long PIC191:1; + } BIT; + } PIC5; + union + { + unsigned long LONG; + struct + { + unsigned long PIC192:1; + unsigned long PIC193:1; + unsigned long PIC194:1; + unsigned long PIC195:1; + unsigned long PIC196:1; + unsigned long PIC197:1; + unsigned long PIC198:1; + unsigned long PIC199:1; + unsigned long PIC200:1; + unsigned long PIC201:1; + unsigned long PIC202:1; + unsigned long PIC203:1; + unsigned long PIC204:1; + unsigned long PIC205:1; + unsigned long PIC206:1; + unsigned long PIC207:1; + unsigned long PIC208:1; + unsigned long PIC209:1; + unsigned long PIC210:1; + unsigned long PIC211:1; + unsigned long PIC212:1; + unsigned long PIC213:1; + unsigned long PIC214:1; + unsigned long PIC215:1; + unsigned long PIC216:1; + unsigned long PIC217:1; + unsigned long PIC218:1; + unsigned long PIC219:1; + unsigned long PIC220:1; + unsigned long PIC221:1; + unsigned long PIC222:1; + unsigned long PIC223:1; + } BIT; + } PIC6; + union + { + unsigned long LONG; + struct + { + unsigned long PIC224:1; + unsigned long PIC225:1; + unsigned long PIC226:1; + unsigned long PIC227:1; + unsigned long PIC228:1; + unsigned long PIC229:1; + unsigned long PIC230:1; + unsigned long PIC231:1; + unsigned long PIC232:1; + unsigned long PIC233:1; + unsigned long PIC234:1; + unsigned long PIC235:1; + unsigned long PIC236:1; + unsigned long PIC237:1; + unsigned long PIC238:1; + unsigned long PIC239:1; + unsigned long PIC240:1; + unsigned long PIC241:1; + unsigned long PIC242:1; + unsigned long PIC243:1; + unsigned long PIC244:1; + unsigned long PIC245:1; + unsigned long PIC246:1; + unsigned long PIC247:1; + unsigned long PIC248:1; + unsigned long PIC249:1; + unsigned long PIC250:1; + unsigned long PIC251:1; + unsigned long PIC252:1; + unsigned long PIC253:1; + unsigned long PIC254:1; + unsigned long PIC255:1; + } BIT; + } PIC7; + char wk3[128]; + union + { + unsigned long LONG; + struct + { + unsigned long PRLM0:1; + unsigned long PRLM1:1; + unsigned long PRLM2:1; + unsigned long PRLM3:1; + unsigned long PRLM4:1; + unsigned long PRLM5:1; + unsigned long PRLM6:1; + unsigned long PRLM7:1; + unsigned long PRLM8:1; + unsigned long PRLM9:1; + unsigned long PRLM10:1; + unsigned long PRLM11:1; + unsigned long PRLM12:1; + unsigned long PRLM13:1; + unsigned long PRLM14:1; + unsigned long PRLM15:1; + unsigned long :16; + } BIT; + } PRLM0; + union + { + unsigned long LONG; + struct + { + unsigned long PRLC0:1; + unsigned long PRLC1:1; + unsigned long PRLC2:1; + unsigned long PRLC3:1; + unsigned long PRLC4:1; + unsigned long PRLC5:1; + unsigned long PRLC6:1; + unsigned long PRLC7:1; + unsigned long PRLC8:1; + unsigned long PRLC9:1; + unsigned long PRLC10:1; + unsigned long PRLC11:1; + unsigned long PRLC12:1; + unsigned long PRLC13:1; + unsigned long PRLC14:1; + unsigned long PRLC15:1; + unsigned long :16; + } BIT; + } PRLC0; + union + { + unsigned long LONG; + struct + { + unsigned long UE:1; + unsigned long :31; + } BIT; + } UEN0; + char wk4[52]; + union + { + unsigned long LONG; + } HVA0; + char wk5[12]; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long ISS1:1; + unsigned long ISS2:1; + unsigned long ISS3:1; + unsigned long ISS4:1; + unsigned long ISS5:1; + unsigned long ISS6:1; + unsigned long ISS7:1; + unsigned long ISS8:1; + unsigned long ISS9:1; + unsigned long ISS10:1; + unsigned long ISS11:1; + unsigned long ISS12:1; + unsigned long ISS13:1; + unsigned long ISS14:1; + unsigned long ISS15:1; + unsigned long ISS16:1; + unsigned long ISS17:1; + unsigned long ISS18:1; + unsigned long ISS19:1; + unsigned long ISS20:1; + unsigned long ISS21:1; + unsigned long ISS22:1; + unsigned long ISS23:1; + unsigned long ISS24:1; + unsigned long ISS25:1; + unsigned long ISS26:1; + unsigned long ISS27:1; + unsigned long ISS28:1; + unsigned long ISS29:1; + unsigned long ISS30:1; + unsigned long ISS31:1; + } BIT; + } ISS0; + union + { + unsigned long LONG; + struct + { + unsigned long ISS32:1; + unsigned long ISS33:1; + unsigned long ISS34:1; + unsigned long ISS35:1; + unsigned long ISS36:1; + unsigned long ISS37:1; + unsigned long ISS38:1; + unsigned long ISS39:1; + unsigned long ISS40:1; + unsigned long ISS41:1; + unsigned long ISS42:1; + unsigned long ISS43:1; + unsigned long ISS44:1; + unsigned long ISS45:1; + unsigned long ISS46:1; + unsigned long ISS47:1; + unsigned long ISS48:1; + unsigned long ISS49:1; + unsigned long ISS50:1; + unsigned long ISS51:1; + unsigned long ISS52:1; + unsigned long ISS53:1; + unsigned long ISS54:1; + unsigned long ISS55:1; + unsigned long ISS56:1; + unsigned long ISS57:1; + unsigned long ISS58:1; + unsigned long ISS59:1; + unsigned long ISS60:1; + unsigned long ISS61:1; + unsigned long ISS62:1; + unsigned long ISS63:1; + } BIT; + } ISS1; + union + { + unsigned long LONG; + struct + { + unsigned long ISS64:1; + unsigned long ISS65:1; + unsigned long ISS66:1; + unsigned long ISS67:1; + unsigned long ISS68:1; + unsigned long ISS69:1; + unsigned long ISS70:1; + unsigned long ISS71:1; + unsigned long ISS72:1; + unsigned long ISS73:1; + unsigned long ISS74:1; + unsigned long ISS75:1; + unsigned long ISS76:1; + unsigned long ISS77:1; + unsigned long ISS78:1; + unsigned long ISS79:1; + unsigned long ISS80:1; + unsigned long ISS81:1; + unsigned long ISS82:1; + unsigned long ISS83:1; + unsigned long ISS84:1; + unsigned long ISS85:1; + unsigned long ISS86:1; + unsigned long ISS87:1; + unsigned long ISS88:1; + unsigned long ISS89:1; + unsigned long ISS90:1; + unsigned long ISS91:1; + unsigned long ISS92:1; + unsigned long ISS93:1; + unsigned long ISS94:1; + unsigned long ISS95:1; + } BIT; + } ISS2; + union + { + unsigned long LONG; + struct + { + unsigned long ISS96:1; + unsigned long ISS97:1; + unsigned long ISS98:1; + unsigned long ISS99:1; + unsigned long ISS100:1; + unsigned long ISS101:1; + unsigned long ISS102:1; + unsigned long ISS103:1; + unsigned long ISS104:1; + unsigned long ISS105:1; + unsigned long ISS106:1; + unsigned long ISS107:1; + unsigned long ISS108:1; + unsigned long ISS109:1; + unsigned long ISS110:1; + unsigned long ISS111:1; + unsigned long ISS112:1; + unsigned long ISS113:1; + unsigned long ISS114:1; + unsigned long ISS115:1; + unsigned long ISS116:1; + unsigned long ISS117:1; + unsigned long ISS118:1; + unsigned long ISS119:1; + unsigned long ISS120:1; + unsigned long ISS121:1; + unsigned long ISS122:1; + unsigned long ISS123:1; + unsigned long ISS124:1; + unsigned long ISS125:1; + unsigned long ISS126:1; + unsigned long ISS127:1; + } BIT; + } ISS3; + union + { + unsigned long LONG; + struct + { + unsigned long ISS128:1; + unsigned long ISS129:1; + unsigned long ISS130:1; + unsigned long ISS131:1; + unsigned long ISS132:1; + unsigned long ISS133:1; + unsigned long ISS134:1; + unsigned long ISS135:1; + unsigned long ISS136:1; + unsigned long ISS137:1; + unsigned long ISS138:1; + unsigned long ISS139:1; + unsigned long ISS140:1; + unsigned long ISS141:1; + unsigned long ISS142:1; + unsigned long ISS143:1; + unsigned long ISS144:1; + unsigned long ISS145:1; + unsigned long ISS146:1; + unsigned long ISS147:1; + unsigned long ISS148:1; + unsigned long ISS149:1; + unsigned long ISS150:1; + unsigned long ISS151:1; + unsigned long ISS152:1; + unsigned long ISS153:1; + unsigned long ISS154:1; + unsigned long ISS155:1; + unsigned long ISS156:1; + unsigned long ISS157:1; + unsigned long ISS158:1; + unsigned long ISS159:1; + } BIT; + } ISS4; + union + { + unsigned long LONG; + struct + { + unsigned long ISS160:1; + unsigned long ISS161:1; + unsigned long ISS162:1; + unsigned long ISS163:1; + unsigned long ISS164:1; + unsigned long ISS165:1; + unsigned long ISS166:1; + unsigned long ISS167:1; + unsigned long ISS168:1; + unsigned long ISS169:1; + unsigned long ISS170:1; + unsigned long ISS171:1; + unsigned long ISS172:1; + unsigned long ISS173:1; + unsigned long ISS174:1; + unsigned long ISS175:1; + unsigned long ISS176:1; + unsigned long ISS177:1; + unsigned long ISS178:1; + unsigned long ISS179:1; + unsigned long ISS180:1; + unsigned long ISS181:1; + unsigned long ISS182:1; + unsigned long ISS183:1; + unsigned long ISS184:1; + unsigned long ISS185:1; + unsigned long ISS186:1; + unsigned long ISS187:1; + unsigned long ISS188:1; + unsigned long ISS189:1; + unsigned long ISS190:1; + unsigned long ISS191:1; + } BIT; + } ISS5; + union + { + unsigned long LONG; + struct + { + unsigned long ISS192:1; + unsigned long ISS193:1; + unsigned long ISS194:1; + unsigned long ISS195:1; + unsigned long ISS196:1; + unsigned long ISS197:1; + unsigned long ISS198:1; + unsigned long ISS199:1; + unsigned long ISS200:1; + unsigned long ISS201:1; + unsigned long ISS202:1; + unsigned long ISS203:1; + unsigned long ISS204:1; + unsigned long ISS205:1; + unsigned long ISS206:1; + unsigned long ISS207:1; + unsigned long ISS208:1; + unsigned long ISS209:1; + unsigned long ISS210:1; + unsigned long ISS211:1; + unsigned long ISS212:1; + unsigned long ISS213:1; + unsigned long ISS214:1; + unsigned long ISS215:1; + unsigned long ISS216:1; + unsigned long ISS217:1; + unsigned long ISS218:1; + unsigned long ISS219:1; + unsigned long ISS220:1; + unsigned long ISS221:1; + unsigned long ISS222:1; + unsigned long ISS223:1; + } BIT; + } ISS6; + union + { + unsigned long LONG; + struct + { + unsigned long ISS224:1; + unsigned long ISS225:1; + unsigned long ISS226:1; + unsigned long ISS227:1; + unsigned long ISS228:1; + unsigned long ISS229:1; + unsigned long ISS230:1; + unsigned long ISS231:1; + unsigned long ISS232:1; + unsigned long ISS233:1; + unsigned long ISS234:1; + unsigned long ISS235:1; + unsigned long ISS236:1; + unsigned long ISS237:1; + unsigned long ISS238:1; + unsigned long ISS239:1; + unsigned long ISS240:1; + unsigned long ISS241:1; + unsigned long ISS242:1; + unsigned long ISS243:1; + unsigned long ISS244:1; + unsigned long ISS245:1; + unsigned long ISS246:1; + unsigned long ISS247:1; + unsigned long ISS248:1; + unsigned long ISS249:1; + unsigned long ISS250:1; + unsigned long ISS251:1; + unsigned long ISS252:1; + unsigned long ISS253:1; + unsigned long ISS254:1; + unsigned long ISS255:1; + } BIT; + } ISS7; + union + { + unsigned long LONG; + struct + { + unsigned long :1; + unsigned long ISC1:1; + unsigned long ISC2:1; + unsigned long ISC3:1; + unsigned long ISC4:1; + unsigned long ISC5:1; + unsigned long ISC6:1; + unsigned long ISC7:1; + unsigned long ISC8:1; + unsigned long ISC9:1; + unsigned long ISC10:1; + unsigned long ISC11:1; + unsigned long ISC12:1; + unsigned long ISC13:1; + unsigned long ISC14:1; + unsigned long ISC15:1; + unsigned long ISC16:1; + unsigned long ISC17:1; + unsigned long ISC18:1; + unsigned long ISC19:1; + unsigned long ISC20:1; + unsigned long ISC21:1; + unsigned long ISC22:1; + unsigned long ISC23:1; + unsigned long ISC24:1; + unsigned long ISC25:1; + unsigned long ISC26:1; + unsigned long ISC27:1; + unsigned long ISC28:1; + unsigned long ISC29:1; + unsigned long ISC30:1; + unsigned long ISC31:1; + } BIT; + } ISC0; + union + { + unsigned long LONG; + struct + { + unsigned long ISC32:1; + unsigned long ISC33:1; + unsigned long ISC34:1; + unsigned long ISC35:1; + unsigned long ISC36:1; + unsigned long ISC37:1; + unsigned long ISC38:1; + unsigned long ISC39:1; + unsigned long ISC40:1; + unsigned long ISC41:1; + unsigned long ISC42:1; + unsigned long ISC43:1; + unsigned long ISC44:1; + unsigned long ISC45:1; + unsigned long ISC46:1; + unsigned long ISC47:1; + unsigned long ISC48:1; + unsigned long ISC49:1; + unsigned long ISC50:1; + unsigned long ISC51:1; + unsigned long ISC52:1; + unsigned long ISC53:1; + unsigned long ISC54:1; + unsigned long ISC55:1; + unsigned long ISC56:1; + unsigned long ISC57:1; + unsigned long ISC58:1; + unsigned long ISC59:1; + unsigned long ISC60:1; + unsigned long ISC61:1; + unsigned long ISC62:1; + unsigned long ISC63:1; + } BIT; + } ISC1; + union + { + unsigned long LONG; + struct + { + unsigned long ISC64:1; + unsigned long ISC65:1; + unsigned long ISC66:1; + unsigned long ISC67:1; + unsigned long ISC68:1; + unsigned long ISC69:1; + unsigned long ISC70:1; + unsigned long ISC71:1; + unsigned long ISC72:1; + unsigned long ISC73:1; + unsigned long ISC74:1; + unsigned long ISC75:1; + unsigned long ISC76:1; + unsigned long ISC77:1; + unsigned long ISC78:1; + unsigned long ISC79:1; + unsigned long ISC80:1; + unsigned long ISC81:1; + unsigned long ISC82:1; + unsigned long ISC83:1; + unsigned long ISC84:1; + unsigned long ISC85:1; + unsigned long ISC86:1; + unsigned long ISC87:1; + unsigned long ISC88:1; + unsigned long ISC89:1; + unsigned long ISC90:1; + unsigned long ISC91:1; + unsigned long ISC92:1; + unsigned long ISC93:1; + unsigned long ISC94:1; + unsigned long ISC95:1; + } BIT; + } ISC2; + union + { + unsigned long LONG; + struct + { + unsigned long ISC96:1; + unsigned long ISC97:1; + unsigned long ISC98:1; + unsigned long ISC99:1; + unsigned long ISC100:1; + unsigned long ISC101:1; + unsigned long ISC102:1; + unsigned long ISC103:1; + unsigned long ISC104:1; + unsigned long ISC105:1; + unsigned long ISC106:1; + unsigned long ISC107:1; + unsigned long ISC108:1; + unsigned long ISC109:1; + unsigned long ISC110:1; + unsigned long ISC111:1; + unsigned long ISC112:1; + unsigned long ISC113:1; + unsigned long ISC114:1; + unsigned long ISC115:1; + unsigned long ISC116:1; + unsigned long ISC117:1; + unsigned long ISC118:1; + unsigned long ISC119:1; + unsigned long ISC120:1; + unsigned long ISC121:1; + unsigned long ISC122:1; + unsigned long ISC123:1; + unsigned long ISC124:1; + unsigned long ISC125:1; + unsigned long ISC126:1; + unsigned long ISC127:1; + } BIT; + } ISC3; + union + { + unsigned long LONG; + struct + { + unsigned long ISC128:1; + unsigned long ISC129:1; + unsigned long ISC130:1; + unsigned long ISC131:1; + unsigned long ISC132:1; + unsigned long ISC133:1; + unsigned long ISC134:1; + unsigned long ISC135:1; + unsigned long ISC136:1; + unsigned long ISC137:1; + unsigned long ISC138:1; + unsigned long ISC139:1; + unsigned long ISC140:1; + unsigned long ISC141:1; + unsigned long ISC142:1; + unsigned long ISC143:1; + unsigned long ISC144:1; + unsigned long ISC145:1; + unsigned long ISC146:1; + unsigned long ISC147:1; + unsigned long ISC148:1; + unsigned long ISC149:1; + unsigned long ISC150:1; + unsigned long ISC151:1; + unsigned long ISC152:1; + unsigned long ISC153:1; + unsigned long ISC154:1; + unsigned long ISC155:1; + unsigned long ISC156:1; + unsigned long ISC157:1; + unsigned long ISC158:1; + unsigned long ISC159:1; + } BIT; + } ISC4; + union + { + unsigned long LONG; + struct + { + unsigned long ISC160:1; + unsigned long ISC161:1; + unsigned long ISC162:1; + unsigned long ISC163:1; + unsigned long ISC164:1; + unsigned long ISC165:1; + unsigned long ISC166:1; + unsigned long ISC167:1; + unsigned long ISC168:1; + unsigned long ISC169:1; + unsigned long ISC170:1; + unsigned long ISC171:1; + unsigned long ISC172:1; + unsigned long ISC173:1; + unsigned long ISC174:1; + unsigned long ISC175:1; + unsigned long ISC176:1; + unsigned long ISC177:1; + unsigned long ISC178:1; + unsigned long ISC179:1; + unsigned long ISC180:1; + unsigned long ISC181:1; + unsigned long ISC182:1; + unsigned long ISC183:1; + unsigned long ISC184:1; + unsigned long ISC185:1; + unsigned long ISC186:1; + unsigned long ISC187:1; + unsigned long ISC188:1; + unsigned long ISC189:1; + unsigned long ISC190:1; + unsigned long ISC191:1; + } BIT; + } ISC5; + union + { + unsigned long LONG; + struct + { + unsigned long ISC192:1; + unsigned long ISC193:1; + unsigned long ISC194:1; + unsigned long ISC195:1; + unsigned long ISC196:1; + unsigned long ISC197:1; + unsigned long ISC198:1; + unsigned long ISC199:1; + unsigned long ISC200:1; + unsigned long ISC201:1; + unsigned long ISC202:1; + unsigned long ISC203:1; + unsigned long ISC204:1; + unsigned long ISC205:1; + unsigned long ISC206:1; + unsigned long ISC207:1; + unsigned long ISC208:1; + unsigned long ISC209:1; + unsigned long ISC210:1; + unsigned long ISC211:1; + unsigned long ISC212:1; + unsigned long ISC213:1; + unsigned long ISC214:1; + unsigned long ISC215:1; + unsigned long ISC216:1; + unsigned long ISC217:1; + unsigned long ISC218:1; + unsigned long ISC219:1; + unsigned long ISC220:1; + unsigned long ISC221:1; + unsigned long ISC222:1; + unsigned long ISC223:1; + } BIT; + } ISC6; + union + { + unsigned long LONG; + struct + { + unsigned long ISC224:1; + unsigned long ISC225:1; + unsigned long ISC226:1; + unsigned long ISC227:1; + unsigned long ISC228:1; + unsigned long ISC229:1; + unsigned long ISC230:1; + unsigned long ISC231:1; + unsigned long ISC232:1; + unsigned long ISC233:1; + unsigned long ISC234:1; + unsigned long ISC235:1; + unsigned long ISC236:1; + unsigned long ISC237:1; + unsigned long ISC238:1; + unsigned long ISC239:1; + unsigned long ISC240:1; + unsigned long ISC241:1; + unsigned long ISC242:1; + unsigned long ISC243:1; + unsigned long ISC244:1; + unsigned long ISC245:1; + unsigned long ISC246:1; + unsigned long ISC247:1; + unsigned long ISC248:1; + unsigned long ISC249:1; + unsigned long ISC250:1; + unsigned long ISC251:1; + unsigned long ISC252:1; + unsigned long ISC253:1; + unsigned long ISC254:1; + unsigned long ISC255:1; + } BIT; + } ISC7; + char wk6[436]; + union + { + unsigned long LONG; + struct + { + unsigned long VAD1:32; + } BIT; + } VAD1; + union + { + unsigned long LONG; + struct + { + unsigned long VAD2:32; + } BIT; + } VAD2; + union + { + unsigned long LONG; + struct + { + unsigned long VAD3:32; + } BIT; + } VAD3; + union + { + unsigned long LONG; + struct + { + unsigned long VAD4:32; + } BIT; + } VAD4; + union + { + unsigned long LONG; + struct + { + unsigned long VAD5:32; + } BIT; + } VAD5; + union + { + unsigned long LONG; + struct + { + unsigned long VAD6:32; + } BIT; + } VAD6; + union + { + unsigned long LONG; + struct + { + unsigned long VAD7:32; + } BIT; + } VAD7; + union + { + unsigned long LONG; + struct + { + unsigned long VAD8:32; + } BIT; + } VAD8; + union + { + unsigned long LONG; + struct + { + unsigned long VAD9:32; + } BIT; + } VAD9; + union + { + unsigned long LONG; + struct + { + unsigned long VAD10:32; + } BIT; + } VAD10; + union + { + unsigned long LONG; + struct + { + unsigned long VAD11:32; + } BIT; + } VAD11; + union + { + unsigned long LONG; + struct + { + unsigned long VAD12:32; + } BIT; + } VAD12; + union + { + unsigned long LONG; + struct + { + unsigned long VAD13:32; + } BIT; + } VAD13; + union + { + unsigned long LONG; + struct + { + unsigned long VAD14:32; + } BIT; + } VAD14; + union + { + unsigned long LONG; + struct + { + unsigned long VAD15:32; + } BIT; + } VAD15; + union + { + unsigned long LONG; + struct + { + unsigned long VAD16:32; + } BIT; + } VAD16; + union + { + unsigned long LONG; + struct + { + unsigned long VAD17:32; + } BIT; + } VAD17; + union + { + unsigned long LONG; + struct + { + unsigned long VAD18:32; + } BIT; + } VAD18; + union + { + unsigned long LONG; + struct + { + unsigned long VAD19:32; + } BIT; + } VAD19; + union + { + unsigned long LONG; + struct + { + unsigned long VAD20:32; + } BIT; + } VAD20; + union + { + unsigned long LONG; + struct + { + unsigned long VAD21:32; + } BIT; + } VAD21; + union + { + unsigned long LONG; + struct + { + unsigned long VAD22:32; + } BIT; + } VAD22; + union + { + unsigned long LONG; + struct + { + unsigned long VAD23:32; + } BIT; + } VAD23; + union + { + unsigned long LONG; + struct + { + unsigned long VAD24:32; + } BIT; + } VAD24; + union + { + unsigned long LONG; + struct + { + unsigned long VAD25:32; + } BIT; + } VAD25; + union + { + unsigned long LONG; + struct + { + unsigned long VAD26:32; + } BIT; + } VAD26; + union + { + unsigned long LONG; + struct + { + unsigned long VAD27:32; + } BIT; + } VAD27; + union + { + unsigned long LONG; + struct + { + unsigned long VAD28:32; + } BIT; + } VAD28; + union + { + unsigned long LONG; + struct + { + unsigned long VAD29:32; + } BIT; + } VAD29; + union + { + unsigned long LONG; + struct + { + unsigned long VAD30:32; + } BIT; + } VAD30; + union + { + unsigned long LONG; + struct + { + unsigned long VAD31:32; + } BIT; + } VAD31; + union + { + unsigned long LONG; + struct + { + unsigned long VAD32:32; + } BIT; + } VAD32; + union + { + unsigned long LONG; + struct + { + unsigned long VAD33:32; + } BIT; + } VAD33; + union + { + unsigned long LONG; + struct + { + unsigned long VAD34:32; + } BIT; + } VAD34; + union + { + unsigned long LONG; + struct + { + unsigned long VAD35:32; + } BIT; + } VAD35; + union + { + unsigned long LONG; + struct + { + unsigned long VAD36:32; + } BIT; + } VAD36; + union + { + unsigned long LONG; + struct + { + unsigned long VAD37:32; + } BIT; + } VAD37; + union + { + unsigned long LONG; + struct + { + unsigned long VAD38:32; + } BIT; + } VAD38; + union + { + unsigned long LONG; + struct + { + unsigned long VAD39:32; + } BIT; + } VAD39; + union + { + unsigned long LONG; + struct + { + unsigned long VAD40:32; + } BIT; + } VAD40; + union + { + unsigned long LONG; + struct + { + unsigned long VAD41:32; + } BIT; + } VAD41; + union + { + unsigned long LONG; + struct + { + unsigned long VAD42:32; + } BIT; + } VAD42; + union + { + unsigned long LONG; + struct + { + unsigned long VAD43:32; + } BIT; + } VAD43; + union + { + unsigned long LONG; + struct + { + unsigned long VAD44:32; + } BIT; + } VAD44; + union + { + unsigned long LONG; + struct + { + unsigned long VAD45:32; + } BIT; + } VAD45; + union + { + unsigned long LONG; + struct + { + unsigned long VAD46:32; + } BIT; + } VAD46; + union + { + unsigned long LONG; + struct + { + unsigned long VAD47:32; + } BIT; + } VAD47; + union + { + unsigned long LONG; + struct + { + unsigned long VAD48:32; + } BIT; + } VAD48; + union + { + unsigned long LONG; + struct + { + unsigned long VAD49:32; + } BIT; + } VAD49; + union + { + unsigned long LONG; + struct + { + unsigned long VAD50:32; + } BIT; + } VAD50; + union + { + unsigned long LONG; + struct + { + unsigned long VAD51:32; + } BIT; + } VAD51; + union + { + unsigned long LONG; + struct + { + unsigned long VAD52:32; + } BIT; + } VAD52; + union + { + unsigned long LONG; + struct + { + unsigned long VAD53:32; + } BIT; + } VAD53; + union + { + unsigned long LONG; + struct + { + unsigned long VAD54:32; + } BIT; + } VAD54; + union + { + unsigned long LONG; + struct + { + unsigned long VAD55:32; + } BIT; + } VAD55; + union + { + unsigned long LONG; + struct + { + unsigned long VAD56:32; + } BIT; + } VAD56; + union + { + unsigned long LONG; + struct + { + unsigned long VAD57:32; + } BIT; + } VAD57; + union + { + unsigned long LONG; + struct + { + unsigned long VAD58:32; + } BIT; + } VAD58; + union + { + unsigned long LONG; + struct + { + unsigned long VAD59:32; + } BIT; + } VAD59; + union + { + unsigned long LONG; + struct + { + unsigned long VAD60:32; + } BIT; + } VAD60; + union + { + unsigned long LONG; + struct + { + unsigned long VAD61:32; + } BIT; + } VAD61; + union + { + unsigned long LONG; + struct + { + unsigned long VAD62:32; + } BIT; + } VAD62; + union + { + unsigned long LONG; + struct + { + unsigned long VAD63:32; + } BIT; + } VAD63; + union + { + unsigned long LONG; + struct + { + unsigned long VAD64:32; + } BIT; + } VAD64; + union + { + unsigned long LONG; + struct + { + unsigned long VAD65:32; + } BIT; + } VAD65; + union + { + unsigned long LONG; + struct + { + unsigned long VAD66:32; + } BIT; + } VAD66; + union + { + unsigned long LONG; + struct + { + unsigned long VAD67:32; + } BIT; + } VAD67; + union + { + unsigned long LONG; + struct + { + unsigned long VAD68:32; + } BIT; + } VAD68; + union + { + unsigned long LONG; + struct + { + unsigned long VAD69:32; + } BIT; + } VAD69; + union + { + unsigned long LONG; + struct + { + unsigned long VAD70:32; + } BIT; + } VAD70; + union + { + unsigned long LONG; + struct + { + unsigned long VAD71:32; + } BIT; + } VAD71; + union + { + unsigned long LONG; + struct + { + unsigned long VAD72:32; + } BIT; + } VAD72; + union + { + unsigned long LONG; + struct + { + unsigned long VAD73:32; + } BIT; + } VAD73; + union + { + unsigned long LONG; + struct + { + unsigned long VAD74:32; + } BIT; + } VAD74; + union + { + unsigned long LONG; + struct + { + unsigned long VAD75:32; + } BIT; + } VAD75; + union + { + unsigned long LONG; + struct + { + unsigned long VAD76:32; + } BIT; + } VAD76; + union + { + unsigned long LONG; + struct + { + unsigned long VAD77:32; + } BIT; + } VAD77; + union + { + unsigned long LONG; + struct + { + unsigned long VAD78:32; + } BIT; + } VAD78; + union + { + unsigned long LONG; + struct + { + unsigned long VAD79:32; + } BIT; + } VAD79; + union + { + unsigned long LONG; + struct + { + unsigned long VAD80:32; + } BIT; + } VAD80; + union + { + unsigned long LONG; + struct + { + unsigned long VAD81:32; + } BIT; + } VAD81; + union + { + unsigned long LONG; + struct + { + unsigned long VAD82:32; + } BIT; + } VAD82; + union + { + unsigned long LONG; + struct + { + unsigned long VAD83:32; + } BIT; + } VAD83; + union + { + unsigned long LONG; + struct + { + unsigned long VAD84:32; + } BIT; + } VAD84; + union + { + unsigned long LONG; + struct + { + unsigned long VAD85:32; + } BIT; + } VAD85; + union + { + unsigned long LONG; + struct + { + unsigned long VAD86:32; + } BIT; + } VAD86; + union + { + unsigned long LONG; + struct + { + unsigned long VAD87:32; + } BIT; + } VAD87; + union + { + unsigned long LONG; + struct + { + unsigned long VAD88:32; + } BIT; + } VAD88; + union + { + unsigned long LONG; + struct + { + unsigned long VAD89:32; + } BIT; + } VAD89; + union + { + unsigned long LONG; + struct + { + unsigned long VAD90:32; + } BIT; + } VAD90; + union + { + unsigned long LONG; + struct + { + unsigned long VAD91:32; + } BIT; + } VAD91; + union + { + unsigned long LONG; + struct + { + unsigned long VAD92:32; + } BIT; + } VAD92; + union + { + unsigned long LONG; + struct + { + unsigned long VAD93:32; + } BIT; + } VAD93; + union + { + unsigned long LONG; + struct + { + unsigned long VAD94:32; + } BIT; + } VAD94; + union + { + unsigned long LONG; + struct + { + unsigned long VAD95:32; + } BIT; + } VAD95; + union + { + unsigned long LONG; + struct + { + unsigned long VAD96:32; + } BIT; + } VAD96; + union + { + unsigned long LONG; + struct + { + unsigned long VAD97:32; + } BIT; + } VAD97; + union + { + unsigned long LONG; + struct + { + unsigned long VAD98:32; + } BIT; + } VAD98; + union + { + unsigned long LONG; + struct + { + unsigned long VAD99:32; + } BIT; + } VAD99; + union + { + unsigned long LONG; + struct + { + unsigned long VAD100:32; + } BIT; + } VAD100; + union + { + unsigned long LONG; + struct + { + unsigned long VAD101:32; + } BIT; + } VAD101; + union + { + unsigned long LONG; + struct + { + unsigned long VAD102:32; + } BIT; + } VAD102; + union + { + unsigned long LONG; + struct + { + unsigned long VAD103:32; + } BIT; + } VAD103; + union + { + unsigned long LONG; + struct + { + unsigned long VAD104:32; + } BIT; + } VAD104; + union + { + unsigned long LONG; + struct + { + unsigned long VAD105:32; + } BIT; + } VAD105; + union + { + unsigned long LONG; + struct + { + unsigned long VAD106:32; + } BIT; + } VAD106; + union + { + unsigned long LONG; + struct + { + unsigned long VAD107:32; + } BIT; + } VAD107; + union + { + unsigned long LONG; + struct + { + unsigned long VAD108:32; + } BIT; + } VAD108; + union + { + unsigned long LONG; + struct + { + unsigned long VAD109:32; + } BIT; + } VAD109; + union + { + unsigned long LONG; + struct + { + unsigned long VAD110:32; + } BIT; + } VAD110; + union + { + unsigned long LONG; + struct + { + unsigned long VAD111:32; + } BIT; + } VAD111; + union + { + unsigned long LONG; + struct + { + unsigned long VAD112:32; + } BIT; + } VAD112; + union + { + unsigned long LONG; + struct + { + unsigned long VAD113:32; + } BIT; + } VAD113; + union + { + unsigned long LONG; + struct + { + unsigned long VAD114:32; + } BIT; + } VAD114; + union + { + unsigned long LONG; + struct + { + unsigned long VAD115:32; + } BIT; + } VAD115; + union + { + unsigned long LONG; + struct + { + unsigned long VAD116:32; + } BIT; + } VAD116; + union + { + unsigned long LONG; + struct + { + unsigned long VAD117:32; + } BIT; + } VAD117; + union + { + unsigned long LONG; + struct + { + unsigned long VAD118:32; + } BIT; + } VAD118; + union + { + unsigned long LONG; + struct + { + unsigned long VAD119:32; + } BIT; + } VAD119; + union + { + unsigned long LONG; + struct + { + unsigned long VAD120:32; + } BIT; + } VAD120; + union + { + unsigned long LONG; + struct + { + unsigned long VAD121:32; + } BIT; + } VAD121; + union + { + unsigned long LONG; + struct + { + unsigned long VAD122:32; + } BIT; + } VAD122; + union + { + unsigned long LONG; + struct + { + unsigned long VAD123:32; + } BIT; + } VAD123; + union + { + unsigned long LONG; + struct + { + unsigned long VAD124:32; + } BIT; + } VAD124; + union + { + unsigned long LONG; + struct + { + unsigned long VAD125:32; + } BIT; + } VAD125; + union + { + unsigned long LONG; + struct + { + unsigned long VAD126:32; + } BIT; + } VAD126; + union + { + unsigned long LONG; + struct + { + unsigned long VAD127:32; + } BIT; + } VAD127; + union + { + unsigned long LONG; + struct + { + unsigned long VAD128:32; + } BIT; + } VAD128; + union + { + unsigned long LONG; + struct + { + unsigned long VAD129:32; + } BIT; + } VAD129; + union + { + unsigned long LONG; + struct + { + unsigned long VAD130:32; + } BIT; + } VAD130; + union + { + unsigned long LONG; + struct + { + unsigned long VAD131:32; + } BIT; + } VAD131; + union + { + unsigned long LONG; + struct + { + unsigned long VAD132:32; + } BIT; + } VAD132; + union + { + unsigned long LONG; + struct + { + unsigned long VAD133:32; + } BIT; + } VAD133; + union + { + unsigned long LONG; + struct + { + unsigned long VAD134:32; + } BIT; + } VAD134; + union + { + unsigned long LONG; + struct + { + unsigned long VAD135:32; + } BIT; + } VAD135; + union + { + unsigned long LONG; + struct + { + unsigned long VAD136:32; + } BIT; + } VAD136; + union + { + unsigned long LONG; + struct + { + unsigned long VAD137:32; + } BIT; + } VAD137; + union + { + unsigned long LONG; + struct + { + unsigned long VAD138:32; + } BIT; + } VAD138; + union + { + unsigned long LONG; + struct + { + unsigned long VAD139:32; + } BIT; + } VAD139; + union + { + unsigned long LONG; + struct + { + unsigned long VAD140:32; + } BIT; + } VAD140; + union + { + unsigned long LONG; + struct + { + unsigned long VAD141:32; + } BIT; + } VAD141; + union + { + unsigned long LONG; + struct + { + unsigned long VAD142:32; + } BIT; + } VAD142; + union + { + unsigned long LONG; + struct + { + unsigned long VAD143:32; + } BIT; + } VAD143; + union + { + unsigned long LONG; + struct + { + unsigned long VAD144:32; + } BIT; + } VAD144; + union + { + unsigned long LONG; + struct + { + unsigned long VAD145:32; + } BIT; + } VAD145; + union + { + unsigned long LONG; + struct + { + unsigned long VAD146:32; + } BIT; + } VAD146; + union + { + unsigned long LONG; + struct + { + unsigned long VAD147:32; + } BIT; + } VAD147; + union + { + unsigned long LONG; + struct + { + unsigned long VAD148:32; + } BIT; + } VAD148; + union + { + unsigned long LONG; + struct + { + unsigned long VAD149:32; + } BIT; + } VAD149; + union + { + unsigned long LONG; + struct + { + unsigned long VAD150:32; + } BIT; + } VAD150; + union + { + unsigned long LONG; + struct + { + unsigned long VAD151:32; + } BIT; + } VAD151; + union + { + unsigned long LONG; + struct + { + unsigned long VAD152:32; + } BIT; + } VAD152; + union + { + unsigned long LONG; + struct + { + unsigned long VAD153:32; + } BIT; + } VAD153; + union + { + unsigned long LONG; + struct + { + unsigned long VAD154:32; + } BIT; + } VAD154; + union + { + unsigned long LONG; + struct + { + unsigned long VAD155:32; + } BIT; + } VAD155; + union + { + unsigned long LONG; + struct + { + unsigned long VAD156:32; + } BIT; + } VAD156; + union + { + unsigned long LONG; + struct + { + unsigned long VAD157:32; + } BIT; + } VAD157; + union + { + unsigned long LONG; + struct + { + unsigned long VAD158:32; + } BIT; + } VAD158; + union + { + unsigned long LONG; + struct + { + unsigned long VAD159:32; + } BIT; + } VAD159; + union + { + unsigned long LONG; + struct + { + unsigned long VAD160:32; + } BIT; + } VAD160; + union + { + unsigned long LONG; + struct + { + unsigned long VAD161:32; + } BIT; + } VAD161; + union + { + unsigned long LONG; + struct + { + unsigned long VAD162:32; + } BIT; + } VAD162; + union + { + unsigned long LONG; + struct + { + unsigned long VAD163:32; + } BIT; + } VAD163; + union + { + unsigned long LONG; + struct + { + unsigned long VAD164:32; + } BIT; + } VAD164; + union + { + unsigned long LONG; + struct + { + unsigned long VAD165:32; + } BIT; + } VAD165; + union + { + unsigned long LONG; + struct + { + unsigned long VAD166:32; + } BIT; + } VAD166; + union + { + unsigned long LONG; + struct + { + unsigned long VAD167:32; + } BIT; + } VAD167; + union + { + unsigned long LONG; + struct + { + unsigned long VAD168:32; + } BIT; + } VAD168; + union + { + unsigned long LONG; + struct + { + unsigned long VAD169:32; + } BIT; + } VAD169; + union + { + unsigned long LONG; + struct + { + unsigned long VAD170:32; + } BIT; + } VAD170; + union + { + unsigned long LONG; + struct + { + unsigned long VAD171:32; + } BIT; + } VAD171; + union + { + unsigned long LONG; + struct + { + unsigned long VAD172:32; + } BIT; + } VAD172; + union + { + unsigned long LONG; + struct + { + unsigned long VAD173:32; + } BIT; + } VAD173; + union + { + unsigned long LONG; + struct + { + unsigned long VAD174:32; + } BIT; + } VAD174; + union + { + unsigned long LONG; + struct + { + unsigned long VAD175:32; + } BIT; + } VAD175; + union + { + unsigned long LONG; + struct + { + unsigned long VAD176:32; + } BIT; + } VAD176; + union + { + unsigned long LONG; + struct + { + unsigned long VAD177:32; + } BIT; + } VAD177; + union + { + unsigned long LONG; + struct + { + unsigned long VAD178:32; + } BIT; + } VAD178; + union + { + unsigned long LONG; + struct + { + unsigned long VAD179:32; + } BIT; + } VAD179; + union + { + unsigned long LONG; + struct + { + unsigned long VAD180:32; + } BIT; + } VAD180; + union + { + unsigned long LONG; + struct + { + unsigned long VAD181:32; + } BIT; + } VAD181; + union + { + unsigned long LONG; + struct + { + unsigned long VAD182:32; + } BIT; + } VAD182; + union + { + unsigned long LONG; + struct + { + unsigned long VAD183:32; + } BIT; + } VAD183; + union + { + unsigned long LONG; + struct + { + unsigned long VAD184:32; + } BIT; + } VAD184; + union + { + unsigned long LONG; + struct + { + unsigned long VAD185:32; + } BIT; + } VAD185; + union + { + unsigned long LONG; + struct + { + unsigned long VAD186:32; + } BIT; + } VAD186; + union + { + unsigned long LONG; + struct + { + unsigned long VAD187:32; + } BIT; + } VAD187; + union + { + unsigned long LONG; + struct + { + unsigned long VAD188:32; + } BIT; + } VAD188; + union + { + unsigned long LONG; + struct + { + unsigned long VAD189:32; + } BIT; + } VAD189; + union + { + unsigned long LONG; + struct + { + unsigned long VAD190:32; + } BIT; + } VAD190; + union + { + unsigned long LONG; + struct + { + unsigned long VAD191:32; + } BIT; + } VAD191; + union + { + unsigned long LONG; + struct + { + unsigned long VAD192:32; + } BIT; + } VAD192; + union + { + unsigned long LONG; + struct + { + unsigned long VAD193:32; + } BIT; + } VAD193; + union + { + unsigned long LONG; + struct + { + unsigned long VAD194:32; + } BIT; + } VAD194; + union + { + unsigned long LONG; + struct + { + unsigned long VAD195:32; + } BIT; + } VAD195; + union + { + unsigned long LONG; + struct + { + unsigned long VAD196:32; + } BIT; + } VAD196; + union + { + unsigned long LONG; + struct + { + unsigned long VAD197:32; + } BIT; + } VAD197; + union + { + unsigned long LONG; + struct + { + unsigned long VAD198:32; + } BIT; + } VAD198; + union + { + unsigned long LONG; + struct + { + unsigned long VAD199:32; + } BIT; + } VAD199; + union + { + unsigned long LONG; + struct + { + unsigned long VAD200:32; + } BIT; + } VAD200; + union + { + unsigned long LONG; + struct + { + unsigned long VAD201:32; + } BIT; + } VAD201; + union + { + unsigned long LONG; + struct + { + unsigned long VAD202:32; + } BIT; + } VAD202; + union + { + unsigned long LONG; + struct + { + unsigned long VAD203:32; + } BIT; + } VAD203; + union + { + unsigned long LONG; + struct + { + unsigned long VAD204:32; + } BIT; + } VAD204; + union + { + unsigned long LONG; + struct + { + unsigned long VAD205:32; + } BIT; + } VAD205; + union + { + unsigned long LONG; + struct + { + unsigned long VAD206:32; + } BIT; + } VAD206; + union + { + unsigned long LONG; + struct + { + unsigned long VAD207:32; + } BIT; + } VAD207; + union + { + unsigned long LONG; + struct + { + unsigned long VAD208:32; + } BIT; + } VAD208; + union + { + unsigned long LONG; + struct + { + unsigned long VAD209:32; + } BIT; + } VAD209; + union + { + unsigned long LONG; + struct + { + unsigned long VAD210:32; + } BIT; + } VAD210; + union + { + unsigned long LONG; + struct + { + unsigned long VAD211:32; + } BIT; + } VAD211; + union + { + unsigned long LONG; + struct + { + unsigned long VAD212:32; + } BIT; + } VAD212; + union + { + unsigned long LONG; + struct + { + unsigned long VAD213:32; + } BIT; + } VAD213; + union + { + unsigned long LONG; + struct + { + unsigned long VAD214:32; + } BIT; + } VAD214; + union + { + unsigned long LONG; + struct + { + unsigned long VAD215:32; + } BIT; + } VAD215; + union + { + unsigned long LONG; + struct + { + unsigned long VAD216:32; + } BIT; + } VAD216; + union + { + unsigned long LONG; + struct + { + unsigned long VAD217:32; + } BIT; + } VAD217; + union + { + unsigned long LONG; + struct + { + unsigned long VAD218:32; + } BIT; + } VAD218; + union + { + unsigned long LONG; + struct + { + unsigned long VAD219:32; + } BIT; + } VAD219; + union + { + unsigned long LONG; + struct + { + unsigned long VAD220:32; + } BIT; + } VAD220; + union + { + unsigned long LONG; + struct + { + unsigned long VAD221:32; + } BIT; + } VAD221; + union + { + unsigned long LONG; + struct + { + unsigned long VAD222:32; + } BIT; + } VAD222; + union + { + unsigned long LONG; + struct + { + unsigned long VAD223:32; + } BIT; + } VAD223; + union + { + unsigned long LONG; + struct + { + unsigned long VAD224:32; + } BIT; + } VAD224; + union + { + unsigned long LONG; + struct + { + unsigned long VAD225:32; + } BIT; + } VAD225; + union + { + unsigned long LONG; + struct + { + unsigned long VAD226:32; + } BIT; + } VAD226; + union + { + unsigned long LONG; + struct + { + unsigned long VAD227:32; + } BIT; + } VAD227; + union + { + unsigned long LONG; + struct + { + unsigned long VAD228:32; + } BIT; + } VAD228; + union + { + unsigned long LONG; + struct + { + unsigned long VAD229:32; + } BIT; + } VAD229; + union + { + unsigned long LONG; + struct + { + unsigned long VAD230:32; + } BIT; + } VAD230; + union + { + unsigned long LONG; + struct + { + unsigned long VAD231:32; + } BIT; + } VAD231; + union + { + unsigned long LONG; + struct + { + unsigned long VAD232:32; + } BIT; + } VAD232; + union + { + unsigned long LONG; + struct + { + unsigned long VAD233:32; + } BIT; + } VAD233; + union + { + unsigned long LONG; + struct + { + unsigned long VAD234:32; + } BIT; + } VAD234; + union + { + unsigned long LONG; + struct + { + unsigned long VAD235:32; + } BIT; + } VAD235; + union + { + unsigned long LONG; + struct + { + unsigned long VAD236:32; + } BIT; + } VAD236; + union + { + unsigned long LONG; + struct + { + unsigned long VAD237:32; + } BIT; + } VAD237; + union + { + unsigned long LONG; + struct + { + unsigned long VAD238:32; + } BIT; + } VAD238; + union + { + unsigned long LONG; + struct + { + unsigned long VAD239:32; + } BIT; + } VAD239; + union + { + unsigned long LONG; + struct + { + unsigned long VAD240:32; + } BIT; + } VAD240; + union + { + unsigned long LONG; + struct + { + unsigned long VAD241:32; + } BIT; + } VAD241; + union + { + unsigned long LONG; + struct + { + unsigned long VAD242:32; + } BIT; + } VAD242; + union + { + unsigned long LONG; + struct + { + unsigned long VAD243:32; + } BIT; + } VAD243; + union + { + unsigned long LONG; + struct + { + unsigned long VAD244:32; + } BIT; + } VAD244; + union + { + unsigned long LONG; + struct + { + unsigned long VAD245:32; + } BIT; + } VAD245; + union + { + unsigned long LONG; + struct + { + unsigned long VAD246:32; + } BIT; + } VAD246; + union + { + unsigned long LONG; + struct + { + unsigned long VAD247:32; + } BIT; + } VAD247; + union + { + unsigned long LONG; + struct + { + unsigned long VAD248:32; + } BIT; + } VAD248; + union + { + unsigned long LONG; + struct + { + unsigned long VAD249:32; + } BIT; + } VAD249; + union + { + unsigned long LONG; + struct + { + unsigned long VAD250:32; + } BIT; + } VAD250; + union + { + unsigned long LONG; + struct + { + unsigned long VAD251:32; + } BIT; + } VAD251; + union + { + unsigned long LONG; + struct + { + unsigned long VAD252:32; + } BIT; + } VAD252; + union + { + unsigned long LONG; + struct + { + unsigned long VAD253:32; + } BIT; + } VAD253; + union + { + unsigned long LONG; + struct + { + unsigned long VAD254:32; + } BIT; + } VAD254; + union + { + unsigned long LONG; + struct + { + unsigned long VAD255:32; + } BIT; + } VAD255; + char wk7[4]; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL1; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL2; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL3; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL4; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL5; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL6; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL7; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL8; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL9; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL10; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL11; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL12; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL13; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL14; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL15; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL16; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL17; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL18; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL19; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL20; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL21; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL22; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL23; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL24; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL25; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL26; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL27; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL28; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL29; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL30; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL31; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL32; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL33; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL34; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL35; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL36; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL37; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL38; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL39; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL40; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL41; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL42; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL43; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL44; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL45; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL46; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL47; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL48; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL49; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL50; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL51; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL52; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL53; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL54; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL55; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL56; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL57; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL58; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL59; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL60; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL61; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL62; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL63; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL64; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL65; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL66; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL67; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL68; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL69; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL70; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL71; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL72; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL73; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL74; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL75; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL76; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL77; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL78; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL79; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL80; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL81; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL82; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL83; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL84; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL85; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL86; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL87; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL88; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL89; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL90; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL91; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL92; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL93; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL94; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL95; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL96; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL97; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL98; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL99; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL100; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL101; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL102; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL103; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL104; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL105; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL106; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL107; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL108; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL109; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL110; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL111; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL112; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL113; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL114; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL115; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL116; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL117; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL118; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL119; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL120; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL121; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL122; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL123; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL124; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL125; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL126; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL127; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL128; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL129; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL130; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL131; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL132; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL133; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL134; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL135; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL136; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL137; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL138; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL139; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL140; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL141; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL142; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL143; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL144; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL145; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL146; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL147; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL148; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL149; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL150; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL151; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL152; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL153; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL154; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL155; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL156; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL157; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL158; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL159; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL160; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL161; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL162; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL163; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL164; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL165; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL166; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL167; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL168; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL169; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL170; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL171; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL172; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL173; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL174; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL175; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL176; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL177; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL178; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL179; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL180; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL181; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL182; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL183; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL184; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL185; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL186; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL187; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL188; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL189; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL190; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL191; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL192; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL193; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL194; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL195; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL196; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL197; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL198; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL199; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL200; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL201; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL202; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL203; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL204; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL205; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL206; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL207; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL208; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL209; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL210; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL211; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL212; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL213; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL214; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL215; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL216; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL217; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL218; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL219; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL220; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL221; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL222; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL223; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL224; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL225; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL226; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL227; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL228; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL229; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL230; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL231; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL232; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL233; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL234; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL235; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL236; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL237; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL238; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL239; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL240; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL241; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL242; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL243; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL244; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL245; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL246; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL247; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL248; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL249; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL250; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL251; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL252; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL253; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL254; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL255; + char wk8[1024]; + union + { + unsigned long LONG; + struct + { + unsigned long IRQ256:1; + unsigned long IRQ257:1; + unsigned long IRQ258:1; + unsigned long IRQ259:1; + unsigned long IRQ260:1; + unsigned long IRQ261:1; + unsigned long IRQ262:1; + unsigned long IRQ263:1; + unsigned long IRQ264:1; + unsigned long IRQ265:1; + unsigned long IRQ266:1; + unsigned long IRQ267:1; + unsigned long IRQ268:1; + unsigned long IRQ269:1; + unsigned long IRQ270:1; + unsigned long IRQ271:1; + unsigned long IRQ272:1; + unsigned long IRQ273:1; + unsigned long IRQ274:1; + unsigned long IRQ275:1; + unsigned long IRQ276:1; + unsigned long IRQ277:1; + unsigned long IRQ278:1; + unsigned long IRQ279:1; + unsigned long IRQ280:1; + unsigned long IRQ281:1; + unsigned long IRQ282:1; + unsigned long IRQ283:1; + unsigned long IRQ284:1; + unsigned long IRQ285:1; + unsigned long IRQ286:1; + unsigned long IRQ287:1; + } BIT; + } IRQS8; + union + { + unsigned long LONG; + struct + { + unsigned long IRQ288:1; + unsigned long IRQ289:1; + unsigned long IRQ290:1; + unsigned long IRQ291:1; + unsigned long IRQ292:1; + unsigned long IRQ293:1; + unsigned long IRQ294:1; + unsigned long IRQ295:1; + unsigned long IRQ296:1; + unsigned long IRQ297:1; + unsigned long IRQ298:1; + unsigned long IRQ299:1; + unsigned long IRQ300:1; + unsigned long :19; + } BIT; + } IRQS9; + char wk9[56]; + union + { + unsigned long LONG; + struct + { + unsigned long RAI256:1; + unsigned long RAI257:1; + unsigned long RAI258:1; + unsigned long RAI259:1; + unsigned long RAI260:1; + unsigned long RAI261:1; + unsigned long RAI262:1; + unsigned long RAI263:1; + unsigned long RAI264:1; + unsigned long RAI265:1; + unsigned long RAI266:1; + unsigned long RAI267:1; + unsigned long RAI268:1; + unsigned long RAI269:1; + unsigned long RAI270:1; + unsigned long RAI271:1; + unsigned long RAI272:1; + unsigned long RAI273:1; + unsigned long RAI274:1; + unsigned long RAI275:1; + unsigned long RAI276:1; + unsigned long RAI277:1; + unsigned long RAI278:1; + unsigned long RAI279:1; + unsigned long RAI280:1; + unsigned long RAI281:1; + unsigned long RAI282:1; + unsigned long RAI283:1; + unsigned long RAI284:1; + unsigned long RAI285:1; + unsigned long RAI286:1; + unsigned long RAI287:1; + } BIT; + } RAIS8; + union + { + unsigned long LONG; + struct + { + unsigned long RAI288:1; + unsigned long RAI289:1; + unsigned long RAI290:1; + unsigned long RAI291:1; + unsigned long RAI292:1; + unsigned long RAI293:1; + unsigned long RAI294:1; + unsigned long RAI295:1; + unsigned long RAI296:1; + unsigned long RAI297:1; + unsigned long RAI298:1; + unsigned long RAI299:1; + unsigned long RAI300:1; + unsigned long :19; + } BIT; + } RAIS9; + char wk10[56]; + union + { + unsigned long LONG; + struct + { + unsigned long IEN256:1; + unsigned long IEN257:1; + unsigned long IEN258:1; + unsigned long IEN259:1; + unsigned long IEN260:1; + unsigned long IEN261:1; + unsigned long IEN262:1; + unsigned long IEN263:1; + unsigned long IEN264:1; + unsigned long IEN265:1; + unsigned long IEN266:1; + unsigned long IEN267:1; + unsigned long IEN268:1; + unsigned long IEN269:1; + unsigned long IEN270:1; + unsigned long IEN271:1; + unsigned long IEN272:1; + unsigned long IEN273:1; + unsigned long IEN274:1; + unsigned long IEN275:1; + unsigned long IEN276:1; + unsigned long IEN277:1; + unsigned long IEN278:1; + unsigned long IEN279:1; + unsigned long IEN280:1; + unsigned long IEN281:1; + unsigned long IEN282:1; + unsigned long IEN283:1; + unsigned long IEN284:1; + unsigned long IEN285:1; + unsigned long IEN286:1; + unsigned long IEN287:1; + } BIT; + } IEN8; + union + { + unsigned long LONG; + struct + { + unsigned long IEN288:1; + unsigned long IEN289:1; + unsigned long IEN290:1; + unsigned long IEN291:1; + unsigned long IEN292:1; + unsigned long IEN293:1; + unsigned long IEN294:1; + unsigned long IEN295:1; + unsigned long IEN296:1; + unsigned long IEN297:1; + unsigned long IEN298:1; + unsigned long IEN299:1; + unsigned long IEN300:1; + unsigned long :19; + } BIT; + } IEN9; + char wk11[24]; + union + { + unsigned long LONG; + struct + { + unsigned long IEC256:1; + unsigned long IEC257:1; + unsigned long IEC258:1; + unsigned long IEC259:1; + unsigned long IEC260:1; + unsigned long IEC261:1; + unsigned long IEC262:1; + unsigned long IEC263:1; + unsigned long IEC264:1; + unsigned long IEC265:1; + unsigned long IEC266:1; + unsigned long IEC267:1; + unsigned long IEC268:1; + unsigned long IEC269:1; + unsigned long IEC270:1; + unsigned long IEC271:1; + unsigned long IEC272:1; + unsigned long IEC273:1; + unsigned long IEC274:1; + unsigned long IEC275:1; + unsigned long IEC276:1; + unsigned long IEC277:1; + unsigned long IEC278:1; + unsigned long IEC279:1; + unsigned long IEC280:1; + unsigned long IEC281:1; + unsigned long IEC282:1; + unsigned long IEC283:1; + unsigned long IEC284:1; + unsigned long IEC285:1; + unsigned long IEC286:1; + unsigned long IEC287:1; + } BIT; + } IEC8; + union + { + unsigned long LONG; + struct + { + unsigned long IEC288:1; + unsigned long IEC289:1; + unsigned long IEC290:1; + unsigned long IEC291:1; + unsigned long IEC292:1; + unsigned long IEC293:1; + unsigned long IEC294:1; + unsigned long IEC295:1; + unsigned long IEC296:1; + unsigned long IEC297:1; + unsigned long IEC298:1; + unsigned long IEC299:1; + unsigned long IEC300:1; + unsigned long :19; + } BIT; + } IEC9; + char wk12[88]; + union + { + unsigned long LONG; + struct + { + unsigned long PLS256:1; + unsigned long PLS257:1; + unsigned long PLS258:1; + unsigned long PLS259:1; + unsigned long PLS260:1; + unsigned long PLS261:1; + unsigned long PLS262:1; + unsigned long PLS263:1; + unsigned long PLS264:1; + unsigned long PLS265:1; + unsigned long PLS266:1; + unsigned long PLS267:1; + unsigned long PLS268:1; + unsigned long PLS269:1; + unsigned long PLS270:1; + unsigned long PLS271:1; + unsigned long PLS272:1; + unsigned long PLS273:1; + unsigned long PLS274:1; + unsigned long PLS275:1; + unsigned long PLS276:1; + unsigned long PLS277:1; + unsigned long PLS278:1; + unsigned long PLS279:1; + unsigned long PLS280:1; + unsigned long PLS281:1; + unsigned long PLS282:1; + unsigned long PLS283:1; + unsigned long PLS284:1; + unsigned long PLS285:1; + unsigned long PLS286:1; + unsigned long PLS287:1; + } BIT; + } PLS8; + union + { + unsigned long LONG; + struct + { + unsigned long PLS288:1; + unsigned long PLS289:1; + unsigned long PLS290:1; + unsigned long PLS291:1; + unsigned long PLS292:1; + unsigned long PLS293:1; + unsigned long PLS294:1; + unsigned long PLS295:1; + unsigned long PLS296:1; + unsigned long PLS297:1; + unsigned long PLS298:1; + unsigned long PLS299:1; + unsigned long PLS300:1; + unsigned long :19; + } BIT; + } PLS9; + char wk13[24]; + union + { + unsigned long LONG; + struct + { + unsigned long PIC256:1; + unsigned long PIC257:1; + unsigned long PIC258:1; + unsigned long PIC259:1; + unsigned long PIC260:1; + unsigned long PIC261:1; + unsigned long PIC262:1; + unsigned long PIC263:1; + unsigned long PIC264:1; + unsigned long PIC265:1; + unsigned long PIC266:1; + unsigned long PIC267:1; + unsigned long PIC268:1; + unsigned long PIC269:1; + unsigned long PIC270:1; + unsigned long PIC271:1; + unsigned long PIC272:1; + unsigned long PIC273:1; + unsigned long PIC274:1; + unsigned long PIC275:1; + unsigned long PIC276:1; + unsigned long PIC277:1; + unsigned long PIC278:1; + unsigned long PIC279:1; + unsigned long PIC280:1; + unsigned long PIC281:1; + unsigned long PIC282:1; + unsigned long PIC283:1; + unsigned long PIC284:1; + unsigned long PIC285:1; + unsigned long PIC286:1; + unsigned long PIC287:1; + } BIT; + } PIC8; + union + { + unsigned long LONG; + struct + { + unsigned long PIC288:1; + unsigned long PIC289:1; + unsigned long PIC290:1; + unsigned long PIC291:1; + unsigned long PIC292:1; + unsigned long PIC293:1; + unsigned long PIC294:1; + unsigned long PIC295:1; + unsigned long PIC296:1; + unsigned long PIC297:1; + unsigned long PIC298:1; + unsigned long PIC299:1; + unsigned long PIC300:1; + unsigned long :19; + } BIT; + } PIC9; + char wk14[152]; + union + { + unsigned long LONG; + struct + { + unsigned long PRLM0:1; + unsigned long PRLM1:1; + unsigned long PRLM2:1; + unsigned long PRLM3:1; + unsigned long PRLM4:1; + unsigned long PRLM5:1; + unsigned long PRLM6:1; + unsigned long PRLM7:1; + unsigned long PRLM8:1; + unsigned long PRLM9:1; + unsigned long PRLM10:1; + unsigned long PRLM11:1; + unsigned long PRLM12:1; + unsigned long PRLM13:1; + unsigned long PRLM14:1; + unsigned long PRLM15:1; + unsigned long :16; + } BIT; + } PRLM1; + union + { + unsigned long LONG; + struct + { + unsigned long PRLC0:1; + unsigned long PRLC1:1; + unsigned long PRLC2:1; + unsigned long PRLC3:1; + unsigned long PRLC4:1; + unsigned long PRLC5:1; + unsigned long PRLC6:1; + unsigned long PRLC7:1; + unsigned long PRLC8:1; + unsigned long PRLC9:1; + unsigned long PRLC10:1; + unsigned long PRLC11:1; + unsigned long PRLC12:1; + unsigned long PRLC13:1; + unsigned long PRLC14:1; + unsigned long PRLC15:1; + unsigned long :16; + } BIT; + } PRLC1; + union + { + unsigned long LONG; + struct + { + unsigned long UE:1; + unsigned long :31; + } BIT; + } UEN1; + char wk15[68]; + union + { + unsigned long LONG; + struct + { + unsigned long ISS256:1; + unsigned long ISS257:1; + unsigned long ISS258:1; + unsigned long ISS259:1; + unsigned long ISS260:1; + unsigned long ISS261:1; + unsigned long ISS262:1; + unsigned long ISS263:1; + unsigned long ISS264:1; + unsigned long ISS265:1; + unsigned long ISS266:1; + unsigned long ISS267:1; + unsigned long ISS268:1; + unsigned long ISS269:1; + unsigned long ISS270:1; + unsigned long ISS271:1; + unsigned long ISS272:1; + unsigned long ISS273:1; + unsigned long ISS274:1; + unsigned long ISS275:1; + unsigned long ISS276:1; + unsigned long ISS277:1; + unsigned long ISS278:1; + unsigned long SS279:1; + unsigned long ISS280:1; + unsigned long ISS281:1; + unsigned long ISS282:1; + unsigned long ISS283:1; + unsigned long ISS284:1; + unsigned long ISS285:1; + unsigned long ISS286:1; + unsigned long ISS287:1; + } BIT; + } ISS8; + union + { + unsigned long LONG; + struct + { + unsigned long ISS288:1; + unsigned long ISS289:1; + unsigned long ISS290:1; + unsigned long ISS291:1; + unsigned long ISS292:1; + unsigned long ISS293:1; + unsigned long ISS294:1; + unsigned long ISS295:1; + unsigned long ISS296:1; + unsigned long ISS297:1; + unsigned long ISS298:1; + unsigned long ISS299:1; + unsigned long ISS300:1; + unsigned long :19; + } BIT; + } ISS9; + char wk16[24]; + union + { + unsigned long LONG; + struct + { + unsigned long ISC256:1; + unsigned long ISC257:1; + unsigned long ISC258:1; + unsigned long ISC259:1; + unsigned long ISC260:1; + unsigned long ISC261:1; + unsigned long ISC262:1; + unsigned long ISC263:1; + unsigned long ISC264:1; + unsigned long ISC265:1; + unsigned long ISC266:1; + unsigned long ISC267:1; + unsigned long ISC268:1; + unsigned long ISC269:1; + unsigned long ISC270:1; + unsigned long ISC271:1; + unsigned long ISC272:1; + unsigned long ISC273:1; + unsigned long ISC274:1; + unsigned long ISC275:1; + unsigned long ISC276:1; + unsigned long ISC277:1; + unsigned long ISC278:1; + unsigned long ISC279:1; + unsigned long ISC280:1; + unsigned long ISC281:1; + unsigned long ISC282:1; + unsigned long ISC283:1; + unsigned long ISC284:1; + unsigned long ISC285:1; + unsigned long ISC286:1; + unsigned long ISC287:1; + } BIT; + } ISC8; + union + { + unsigned long LONG; + struct + { + unsigned long ISC288:1; + unsigned long ISC289:1; + unsigned long ISC290:1; + unsigned long ISC291:1; + unsigned long ISC292:1; + unsigned long ISC293:1; + unsigned long ISC294:1; + unsigned long ISC295:1; + unsigned long ISC296:1; + unsigned long ISC297:1; + unsigned long ISC298:1; + unsigned long ISC299:1; + unsigned long ISC300:1; + unsigned long :19; + } BIT; + } ISC9; + char wk17[456]; + union + { + unsigned long LONG; + struct + { + unsigned long VAD256:32; + } BIT; + } VAD256; + union + { + unsigned long LONG; + struct + { + unsigned long VAD257:32; + } BIT; + } VAD257; + union + { + unsigned long LONG; + struct + { + unsigned long VAD258:32; + } BIT; + } VAD258; + union + { + unsigned long LONG; + struct + { + unsigned long VAD259:32; + } BIT; + } VAD259; + union + { + unsigned long LONG; + struct + { + unsigned long VAD260:32; + } BIT; + } VAD260; + union + { + unsigned long LONG; + struct + { + unsigned long VAD261:32; + } BIT; + } VAD261; + union + { + unsigned long LONG; + struct + { + unsigned long VAD262:32; + } BIT; + } VAD262; + union + { + unsigned long LONG; + struct + { + unsigned long VAD263:32; + } BIT; + } VAD263; + union + { + unsigned long LONG; + struct + { + unsigned long VAD264:32; + } BIT; + } VAD264; + union + { + unsigned long LONG; + struct + { + unsigned long VAD265:32; + } BIT; + } VAD265; + union + { + unsigned long LONG; + struct + { + unsigned long VAD266:32; + } BIT; + } VAD266; + union + { + unsigned long LONG; + struct + { + unsigned long VAD267:32; + } BIT; + } VAD267; + union + { + unsigned long LONG; + struct + { + unsigned long VAD268:32; + } BIT; + } VAD268; + union + { + unsigned long LONG; + struct + { + unsigned long VAD269:32; + } BIT; + } VAD269; + union + { + unsigned long LONG; + struct + { + unsigned long VAD270:32; + } BIT; + } VAD270; + union + { + unsigned long LONG; + struct + { + unsigned long VAD271:32; + } BIT; + } VAD271; + union + { + unsigned long LONG; + struct + { + unsigned long VAD272:32; + } BIT; + } VAD272; + union + { + unsigned long LONG; + struct + { + unsigned long VAD273:32; + } BIT; + } VAD273; + union + { + unsigned long LONG; + struct + { + unsigned long VAD274:32; + } BIT; + } VAD274; + union + { + unsigned long LONG; + struct + { + unsigned long VAD275:32; + } BIT; + } VAD275; + union + { + unsigned long LONG; + struct + { + unsigned long VAD276:32; + } BIT; + } VAD276; + union + { + unsigned long LONG; + struct + { + unsigned long VAD277:32; + } BIT; + } VAD277; + union + { + unsigned long LONG; + struct + { + unsigned long VAD278:32; + } BIT; + } VAD278; + union + { + unsigned long LONG; + struct + { + unsigned long VAD279:32; + } BIT; + } VAD279; + union + { + unsigned long LONG; + struct + { + unsigned long VAD280:32; + } BIT; + } VAD280; + union + { + unsigned long LONG; + struct + { + unsigned long VAD281:32; + } BIT; + } VAD281; + union + { + unsigned long LONG; + struct + { + unsigned long VAD282:32; + } BIT; + } VAD282; + union + { + unsigned long LONG; + struct + { + unsigned long VAD283:32; + } BIT; + } VAD283; + union + { + unsigned long LONG; + struct + { + unsigned long VAD284:32; + } BIT; + } VAD284; + union + { + unsigned long LONG; + struct + { + unsigned long VAD285:32; + } BIT; + } VAD285; + union + { + unsigned long LONG; + struct + { + unsigned long VAD286:32; + } BIT; + } VAD286; + union + { + unsigned long LONG; + struct + { + unsigned long VAD287:32; + } BIT; + } VAD287; + union + { + unsigned long LONG; + struct + { + unsigned long VAD288:32; + } BIT; + } VAD288; + union + { + unsigned long LONG; + struct + { + unsigned long VAD289:32; + } BIT; + } VAD289; + union + { + unsigned long LONG; + struct + { + unsigned long VAD290:32; + } BIT; + } VAD290; + union + { + unsigned long LONG; + struct + { + unsigned long VAD291:32; + } BIT; + } VAD291; + union + { + unsigned long LONG; + struct + { + unsigned long VAD292:32; + } BIT; + } VAD292; + union + { + unsigned long LONG; + struct + { + unsigned long VAD293:32; + } BIT; + } VAD293; + union + { + unsigned long LONG; + struct + { + unsigned long VAD294:32; + } BIT; + } VAD294; + union + { + unsigned long LONG; + struct + { + unsigned long VAD295:32; + } BIT; + } VAD295; + union + { + unsigned long LONG; + struct + { + unsigned long VAD296:32; + } BIT; + } VAD296; + union + { + unsigned long LONG; + struct + { + unsigned long VAD297:32; + } BIT; + } VAD297; + union + { + unsigned long LONG; + struct + { + unsigned long VAD298:32; + } BIT; + } VAD298; + union + { + unsigned long LONG; + struct + { + unsigned long VAD299:32; + } BIT; + } VAD299; + union + { + unsigned long LONG; + struct + { + unsigned long VAD300:32; + } BIT; + } VAD300; + char wk18[844]; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL256; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL257; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL258; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL259; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL260; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL261; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL262; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL263; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL264; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL265; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL266; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL267; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL268; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL269; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL270; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL271; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL272; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL273; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL274; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL275; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL276; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL277; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL278; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL279; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL280; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL281; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL282; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL283; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL284; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL285; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL286; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL287; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL288; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL289; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL290; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL291; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL292; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL293; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL294; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL295; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL296; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL297; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL298; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL299; + union + { + unsigned long LONG; + struct + { + unsigned long PRL:4; + unsigned long :28; + } BIT; + } PRL300; +}; + +struct st_wdt +{ + union + { + unsigned char BYTE; + struct + { + unsigned char REFRESH:8; + } BIT; + } WDTRR; + char wk0[1]; + union + { + unsigned short WORD; + struct + { + unsigned short TOPS:2; + unsigned short :2; + unsigned short CKS:4; + unsigned short RPES:2; + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + } BIT; + } WDTCR; + union + { + unsigned short WORD; + struct + { + unsigned short CNTVAL:14; + unsigned short UNDFF:1; + unsigned short REFEF:1; + } BIT; + } WDTSR; + union + { + unsigned char BYTE; + struct + { + unsigned char :7; + unsigned char RSTIRQS:1; + } BIT; + } WDTRCR; +}; + +//------------------------------------- +// Peripheral I/O region +//------------------------------------- +#ifdef _RZT1_REGISTER_CORTEX_M3_ +#define PERI_BASE (0x40000000UL) +#else +#define PERI_BASE (0xA0000000UL) +#endif + +#define BSC (*(volatile struct st_bsc *)(PERI_BASE + 0x00002004)) +#define CLMA0 (*(volatile struct st_clma0 *)(PERI_BASE + 0x00090000)) +#define CLMA1 (*(volatile struct st_clma1 *)(PERI_BASE + 0x00090020)) +#define CLMA2 (*(volatile struct st_clma2 *)(PERI_BASE + 0x00090040)) +#define CMT (*(volatile struct st_cmt *)(PERI_BASE + 0x00080000)) +#define CMT0 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080002)) +#define CMT1 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080008)) +#define CMT2 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080022)) +#define CMT3 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080028)) +#define CMT4 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080042)) +#define CMT5 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080048)) +#define CMTW (*(volatile struct st_cmtw *)(PERI_BASE + 0x00080400)) +#define CMTW0 (*(volatile struct st_cmtw0 *)(PERI_BASE + 0x00080300)) +#define CMTW1 (*(volatile struct st_cmtw0 *)(PERI_BASE + 0x00080380)) +#define CRC (*(volatile struct st_crc *)(PERI_BASE + 0x0007C000)) +#define DMA0 (*(volatile struct st_dma0 *)(PERI_BASE + 0x00062000)) +#define DMA1 (*(volatile struct st_dma1 *)(PERI_BASE + 0x00063000)) +#define DMAC (*(volatile struct st_dmac *)(PERI_BASE + 0x00002000)) +#define DOC (*(volatile struct st_doc *)(PERI_BASE + 0x00081200)) +#define DSMIF (*(volatile struct st_dsmif *)(PERI_BASE + 0x00072000)) +#define ECATC (*(volatile struct st_ecatc *)(PERI_BASE + 0x000BF100)) +#define ECCRAM (*(volatile struct st_eccram *)(PERI_BASE + 0x000F3000)) +#define ECM (*(volatile struct st_ecm *)(PERI_BASE + 0x0007D080)) +#define ECMC (*(volatile struct st_ecmc *)(PERI_BASE + 0x0007D040)) +#define ECMM (*(volatile struct st_ecmm *)(PERI_BASE + 0x0007D000)) +#define ELC (*(volatile struct st_elc *)(PERI_BASE + 0x00080B00)) +#define ETHERC (*(volatile struct st_etherc *)(PERI_BASE + 0x000BF000)) +#define ETHERSW (*(volatile struct st_ethersw *)(PERI_BASE + 0x000BF014)) +#define GPT (*(volatile struct st_gpt *)(PERI_BASE + 0x0006C000)) +#define GPT0 (*(volatile struct st_gpt0 *)(PERI_BASE + 0x0006C100)) +#define GPT1 (*(volatile struct st_gpt0 *)(PERI_BASE + 0x0006C180)) +#define GPT2 (*(volatile struct st_gpt0 *)(PERI_BASE + 0x0006C200)) +#define GPT3 (*(volatile struct st_gpt0 *)(PERI_BASE + 0x0006C280)) +#define ICU (*(volatile struct st_icu *)(PERI_BASE + 0x00094200)) +#define IWDT (*(volatile struct st_iwdt *)(PERI_BASE + 0x00080700)) +#define MPC (*(volatile struct st_mpc *)(PERI_BASE + 0x00000200)) +#define MTU (*(volatile struct st_mtu *)(PERI_BASE + 0x0006A00A)) +#define MTU0 (*(volatile struct st_mtu0 *)(PERI_BASE + 0x0006A090)) +#define MTU1 (*(volatile struct st_mtu1 *)(PERI_BASE + 0x0006A090)) +#define MTU2 (*(volatile struct st_mtu2 *)(PERI_BASE + 0x0006A092)) +#define MTU3 (*(volatile struct st_mtu3 *)(PERI_BASE + 0x0006A000)) +#define MTU4 (*(volatile struct st_mtu4 *)(PERI_BASE + 0x0006A000)) +#define MTU5 (*(volatile struct st_mtu5 *)(PERI_BASE + 0x0006A894)) +#define MTU6 (*(volatile struct st_mtu6 *)(PERI_BASE + 0x0006A800)) +#define MTU7 (*(volatile struct st_mtu7 *)(PERI_BASE + 0x0006A800)) +#define MTU8 (*(volatile struct st_mtu8 *)(PERI_BASE + 0x0006A098)) +#define POE3 (*(volatile struct st_poe *)(PERI_BASE + 0x00080800)) +#define PORT0 (*(volatile struct st_port0 *)(PERI_BASE + 0x00000000)) +#define PORT1 (*(volatile struct st_port1 *)(PERI_BASE + 0x00000002)) +#define PORT2 (*(volatile struct st_port2 *)(PERI_BASE + 0x00000004)) +#define PORT3 (*(volatile struct st_port3 *)(PERI_BASE + 0x00000006)) +#define PORT4 (*(volatile struct st_port4 *)(PERI_BASE + 0x00000008)) +#define PORT5 (*(volatile struct st_port5 *)(PERI_BASE + 0x0000000A)) +#define PORT6 (*(volatile struct st_port6 *)(PERI_BASE + 0x0000000C)) +#define PORT7 (*(volatile struct st_port7 *)(PERI_BASE + 0x0000000E)) +#define PORT8 (*(volatile struct st_port8 *)(PERI_BASE + 0x00000010)) +#define PORT9 (*(volatile struct st_port9 *)(PERI_BASE + 0x00000012)) +#define PORTA (*(volatile struct st_porta *)(PERI_BASE + 0x00000014)) +#define PORTB (*(volatile struct st_portb *)(PERI_BASE + 0x00000016)) +#define PORTC (*(volatile struct st_portc *)(PERI_BASE + 0x00000018)) +#define PORTD (*(volatile struct st_portd *)(PERI_BASE + 0x0000001A)) +#define PORTE (*(volatile struct st_porte *)(PERI_BASE + 0x0000001C)) +#define PORTF (*(volatile struct st_portf *)(PERI_BASE + 0x0000001E)) +#define PORTG (*(volatile struct st_portg *)(PERI_BASE + 0x00000020)) +#define PORTH (*(volatile struct st_porth *)(PERI_BASE + 0x00000022)) +#define PORTJ (*(volatile struct st_portj *)(PERI_BASE + 0x00000024)) +#define PORTK (*(volatile struct st_portk *)(PERI_BASE + 0x00000026)) +#define PORTL (*(volatile struct st_portl *)(PERI_BASE + 0x00000028)) +#define PORTM (*(volatile struct st_portm *)(PERI_BASE + 0x0000002A)) +#define PORTN (*(volatile struct st_portn *)(PERI_BASE + 0x0000002C)) +#define PORTP (*(volatile struct st_portp *)(PERI_BASE + 0x0000002E)) +#define PORTR (*(volatile struct st_portr *)(PERI_BASE + 0x00000030)) +#define PORTS (*(volatile struct st_ports *)(PERI_BASE + 0x00000032)) +#define PORTT (*(volatile struct st_portt *)(PERI_BASE + 0x00000034)) +#define PORTU (*(volatile struct st_portu *)(PERI_BASE + 0x00000036)) +#define PPG0 (*(volatile struct st_ppg0 *)(PERI_BASE + 0x00080506)) +#define PPG1 (*(volatile struct st_ppg1 *)(PERI_BASE + 0x00080516)) +#define RIIC0 (*(volatile struct st_riic *)(PERI_BASE + 0x00080900)) +#define RIIC1 (*(volatile struct st_riic *)(PERI_BASE + 0x00080940)) +#define RSCAN (*(volatile struct st_rscan *)(PERI_BASE + 0x00078000)) +#define RSPI0 (*(volatile struct st_rspi *)(PERI_BASE + 0x00068000)) +#define RSPI1 (*(volatile struct st_rspi *)(PERI_BASE + 0x00068400)) +#define RSPI2 (*(volatile struct st_rspi *)(PERI_BASE + 0x00068800)) +#define RSPI3 (*(volatile struct st_rspi *)(PERI_BASE + 0x00068C00)) +#define S12ADC0 (*(volatile struct st_s12adc0 *)(PERI_BASE + 0x0008C000)) +#define S12ADC1 (*(volatile struct st_s12adc1 *)(PERI_BASE + 0x0008C400)) +#define SCIFA0 (*(volatile struct st_scifa *)(PERI_BASE + 0x00065000)) +#define SCIFA1 (*(volatile struct st_scifa *)(PERI_BASE + 0x00065400)) +#define SCIFA2 (*(volatile struct st_scifa *)(PERI_BASE + 0x00065800)) +#define SCIFA3 (*(volatile struct st_scifa *)(PERI_BASE + 0x00065C00)) +#define SCIFA4 (*(volatile struct st_scifa *)(PERI_BASE + 0x00066000)) +#define SPIBSC (*(volatile struct st_spibsc *)(PERI_BASE + 0x00005000)) +#define SSI (*(volatile struct st_ssi *)(PERI_BASE + 0x00081000)) +#define SYSTEM (*(volatile struct st_system *)(PERI_BASE + 0x000B0020)) +#define TPU0 (*(volatile struct st_tpu0 *)(PERI_BASE + 0x00080108)) +#define TPU1 (*(volatile struct st_tpu1 *)(PERI_BASE + 0x00080108)) +#define TPU2 (*(volatile struct st_tpu2 *)(PERI_BASE + 0x0008010A)) +#define TPU3 (*(volatile struct st_tpu3 *)(PERI_BASE + 0x0008010A)) +#define TPU4 (*(volatile struct st_tpu4 *)(PERI_BASE + 0x0008010C)) +#define TPU5 (*(volatile struct st_tpu5 *)(PERI_BASE + 0x0008010C)) +#define TPU6 (*(volatile struct st_tpu0 *)(PERI_BASE + 0x00080188)) +#define TPU7 (*(volatile struct st_tpu1 *)(PERI_BASE + 0x00080188)) +#define TPU8 (*(volatile struct st_tpu2 *)(PERI_BASE + 0x0008018A)) +#define TPU9 (*(volatile struct st_tpu3 *)(PERI_BASE + 0x0008018A)) +#define TPU10 (*(volatile struct st_tpu4 *)(PERI_BASE + 0x0008018C)) +#define TPU11 (*(volatile struct st_tpu5 *)(PERI_BASE + 0x0008018C)) +#define TPUA (*(volatile struct st_tpua *)(PERI_BASE + 0x00080100)) +#define TPUSL (*(volatile struct st_tpusl *)(PERI_BASE + 0x00080200)) +#define TSN (*(volatile struct st_tsn *)(PERI_BASE + 0x00080A00)) +#define USBf (*(volatile struct st_usbf *)(PERI_BASE + 0x00060000)) +#define USBh (*(volatile struct st_usbh *)(PERI_BASE + 0x00040000)) +#define VIC (*(volatile struct st_vic *)(PERI_BASE + 0x00010000)) +#define WDT0 (*(volatile struct st_wdt *)(PERI_BASE + 0x00080600)) +#define WDT1 (*(volatile struct st_wdt *)(PERI_BASE + 0x00080620)) + +#endif diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc.c new file mode 100644 index 000000000..d88bae003 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc.c @@ -0,0 +1,212 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for CGC module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +#include "r_reset.h" +#include "r_system.h" +#include "r_typedefs.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ + +#define CPG_WRITE_ENABLE (0x0000A501) +#define CPG_WRITE_DISABLE (0x0000A500) + +#define CPG_CMT0_CLOCK_PCLKD_32 (1) +#define CPG_CMT0_CMI0_ENABLE (1) +#define CPG_CMT0_CONST_100_US (0xEA) +#define CPG_CMT0_START (1) +#define CPG_CMT0_STOP (0) + +#define CPG_CMT_REG_CLEAR (0x0000) + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Create(void) +{ + uint16_t w_count; + + /* LOCO circuit disable */ + SYSTEM.LOCOCR.BIT.LCSTP = 1U; + + /* Systen clock control register setting */ + SYSTEM.SCKCR.LONG = _CGC_CKIO_0 | _CGC_TCLK_0 | _CGC_PCLKE_0 | _CGC_PCLKF_0 | _CGC_PCLKG_0 | _CGC_SERICLK_0 | + _CGC_ETCKE_0 | _CGC_ETCKD_0; + + /* Set the CPU frequency for PLL1 */ + SYSTEM.PLL1CR.BIT.CPUCKSEL = _CGC_PLL1_CPUCKSEL_600; + + /* PLL1 circuit enable */ + SYSTEM.PLL1CR2.BIT.PLL1EN = 1U; + + /* Wait 100us for PLL1 stabilization */ + for (w_count = 0U; w_count < _CGC_PLL_WAIT_CYCLE; w_count++) + { + nop(); + } + + /* Set system clock register 2 to PLL1 */ + SYSTEM.SCKCR2.BIT.CKSEL0 = 1U; + + /* Delta-sigma interface operation setting, DSCLK0 and DSCLK1 both in master mode */ + SYSTEM.DSCR.LONG = _CGC_DSSEL0_MASTER | _CGC_DSCLK0_0 | _CGC_DSSEL1_MASTER | _CGC_DSCLK1_0; +} + +/* Start user code for adding. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name : R_CPG_WriteEnable +* Description : Enables writing to the registers related to CPG function. +* And dummy read the register in order to fix the register value. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_CPG_WriteEnable(void) +{ + volatile uint32_t dummy = 0; + + UNUSED_VARIABLE(dummy); + + /* Enables writing to the CPG register */ + SYSTEM.PRCR.LONG = CPG_WRITE_ENABLE; + dummy = SYSTEM.PRCR.LONG; + +} + +/*********************************************************************************************************************** + End of function R_CPG_WriteEnable +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name : R_CPG_WriteDisable +* Description : Disables writing to the registers related to CPG function. +* And dummy read the register in order to fix the register value. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_CPG_WriteDisable(void) +{ + volatile uint32_t dummy = 0; + + UNUSED_VARIABLE(dummy); + + /* Disables writing to the CPG register */ + SYSTEM.PRCR.LONG = CPG_WRITE_DISABLE; + dummy = SYSTEM.PRCR.LONG; + +} + +/*********************************************************************************************************************** + End of function R_CPG_WriteDisable +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name : R_CPG_PLLWait +* Description : Wait about 100us for PLL stabilisation by using CMT0 +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_CPG_PLLWait(void) +{ + + /* Enables writing to the registers related to Reset and Low-Power function */ + r_rst_write_enable(); + + /* Release from the CMT0 module-stop state */ + MSTP(CMT0) = 0; + + /* Disables writing to the registers related to Reset and Low-Power function */ + r_rst_write_disable(); + + /* Set CMT0 to 100us interval operation */ + CMT0.CMCR.BIT.CKS = CPG_CMT0_CLOCK_PCLKD_32; + CMT0.CMCR.BIT.CMIE = CPG_CMT0_CMI0_ENABLE; + CMT0.CMCNT = CPG_CMT_REG_CLEAR; + CMT0.CMCOR = CPG_CMT0_CONST_100_US; + + /* Set IRQ21(CMI0) for polling sequence */ + VIC.IEC0.BIT.IEC21 = 1U; + VIC.PLS0.BIT.PLS21 = 1U; + VIC.PIC0.BIT.PIC21 = 1U; + + /* Start CMT0 count */ + CMT.CMSTR0.BIT.STR0 = CPG_CMT0_START; + + /* Wait for 100us (IRQ21 is generated) */ + while ( !(VIC.RAIS0.BIT.RAI21) ) + { + /* Wait */ + } + + /* Stop CMT0 count */ + CMT.CMSTR0.BIT.STR0 = CPG_CMT0_STOP; + + /* Initialise CMT0 settings and clear interrupt detection edge */ + CMT0.CMCR.WORD = CPG_CMT_REG_CLEAR; + CMT0.CMCNT = CPG_CMT_REG_CLEAR; + CMT0.CMCOR = CPG_CMT_REG_CLEAR; + CMT.CMSTR0.WORD = CPG_CMT_REG_CLEAR; + + VIC.PIC0.BIT.PIC21 = 1U; + + /* Enables writing to the registers related to Reset and Low-Power function */ + r_rst_write_enable(); + + /* Set CMT0 to module-stop state */ + MSTP(CMT0) = 1; + + /* Disables writing to the registers related to Reset and Low-Power function */ + r_rst_write_disable(); +} + +/*********************************************************************************************************************** + End of function R_CPG_PLLWait +***********************************************************************************************************************/ + +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc.h new file mode 100644 index 000000000..b70f13a67 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc.h @@ -0,0 +1,203 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.h +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for CGC module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ +#ifndef CGC_H +#define CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + System Clock Control Register (SCKCR) +*/ +/* Peripheral Module Clock G (PCLKG) */ +#define _CGC_PCLKG_0 (0x00000000UL) /* 60 MHz */ +#define _CGC_PCLKG_1 (0x00000001UL) /* 30 MHz */ +#define _CGC_PCLKG_2 (0x00000002UL) /* 15 MHz */ +#define _CGC_PCLKG_3 (0x00000003UL) /* 7.5 MHz */ +/* Peripheral Module Clock F (PCLKF) */ +#define _CGC_PCLKF_0 (0x00000000UL) /* 60 MHz */ +#define _CGC_PCLKF_1 (0x00000004UL) /* 30 MHz */ +#define _CGC_PCLKF_2 (0x00000008UL) /* 15 MHz */ +#define _CGC_PCLKF_3 (0x0000000CUL) /* 7.5 MHz */ +/* Peripheral Module Clock E (PCLKE) */ +#define _CGC_PCLKE_0 (0x00000000UL) /* 75 MHz */ +#define _CGC_PCLKE_1 (0x00000010UL) /* 37.5 MHz */ +#define _CGC_PCLKE_2 (0x00000020UL) /* 18.75 MHz */ +/* External Bus Clock (CKIO) */ +#define _CGC_CKIO_0 (0x00000000UL) /* 75 MHz */ +#define _CGC_CKIO_1 (0x00000100UL) /* 50 MHz */ +#define _CGC_CKIO_2 (0x00000200UL) /* 37.5 MHz */ +#define _CGC_CKIO_3 (0x00000300UL) /* 30 MHz */ +#define _CGC_CKIO_4 (0x00000400UL) /* 25 MHz */ +#define _CGC_CKIO_5 (0x00000500UL) /* 21.43 MHz */ +#define _CGC_CKIO_6 (0x00000600UL) /* 18.75 MHz */ +/* Ether Clock E (ETCLKE) */ +#define _CGC_ETCKE_0 (0x00000000UL) /* 25 MHz */ +#define _CGC_ETCKE_1 (0x00001000UL) /* 50 MHz */ +#define _CGC_ETCKE_2 (0x00003000UL) /* 25 MHz */ +/* Ether Clock D (ETCLKD) */ +#define _CGC_ETCKD_0 (0x00000000UL) /* 12.5 MHz */ +#define _CGC_ETCKD_1 (0x00004000UL) /* 6.25 MHz */ +#define _CGC_ETCKD_2 (0x00008000UL) /* 3.125 MHz */ +#define _CGC_ETCKD_3 (0x0000C000UL) /* 1.563 MHz */ +/* High-Speed Serial Clock (SERICLK) */ +#define _CGC_SERICLK_0 (0x00000000UL) /* 150 MHz */ +#define _CGC_SERICLK_1 (0x00010000UL) /* 120 MHz */ +/* USB Clock (USBMCLK) */ +#define _CGC_UCK_0 (0x00000000UL) /* 50 MHz */ +#define _CGC_UCK_1 (0x00020000UL) /* 24 MHz */ +/* Trace Interface Clock (TCLK) */ +#define _CGC_TCLK_0 (0x00000000UL) /* 150 MHz */ +#define _CGC_TCLK_1 (0x00100000UL) /* 75 MHz */ + +/* + System Clock Control Register 2 (SCKCR2) +*/ +#define _CGC_SKSEL0_PLL0 (0x00000000UL) /* PLL0 */ +#define _CGC_SKSEL0_PLL1 (0x00000001UL) /* PLL1 */ + +/* + Delta-Sigma Interface Clock Control Register (DSCR) +*/ +#define _CGC_DSSEL0_SLAVE (0x00000000UL) /* Supplied from outside the LSI (slave operation) */ +#define _CGC_DSSEL0_MASTER (0x00000001UL) /* Supplied from CGC (master operation) */ +#define _CGC_DSCLK0_0 (0x00000000UL) /* 25 MHz */ +#define _CGC_DSCLK0_1 (0x00000002UL) /* 18.75 MHz */ +#define _CGC_DSCLK0_2 (0x00000004UL) /* 12.5 MHz */ +#define _CGC_DSCLK0_3 (0x00000006UL) /* 9.375 MHz */ +#define _CGC_DSCLK0_4 (0x00000008UL) /* 6.25 MHz */ +#define _CGC_DSCLK0_POL_NORMAL (0x00000000UL) /* Polarity not inverted (master and slave operation) */ +#define _CGC_DSCLK0_POL_INVERT (0x00000010UL) /* Polarity inverted (master and slave operation) */ +#define _CGC_DSCLK0_SLAVE_MCLK0_2 (0x00000000UL) /* Clock input to MCLK0,MCLK1,MCLK2 pins are used */ +#define _CGC_DSCLK0_SLAVE_MCLK0 (0x00000020UL) /* Clock input to MCLK0 pin is used */ +#define _CGC_DSSEL1_SLAVE (0x00000000UL) /* Supplied from outside the LSI (slave operation) */ +#define _CGC_DSSEL1_MASTER (0x00010000UL) /* Supplied from CGC (master operation) */ +#define _CGC_DSCLK1_0 (0x00000000UL) /* 25 MHz */ +#define _CGC_DSCLK1_1 (0x00020000UL) /* 18.75 MHz */ +#define _CGC_DSCLK1_2 (0x00040000UL) /* 12.5 MHz */ +#define _CGC_DSCLK1_3 (0x00060000UL) /* 9.375 MHz */ +#define _CGC_DSCLK1_4 (0x00080000UL) /* 6.25 MHz */ +#define _CGC_DSCLK1_POL_NORMAL (0x00000000UL) /* Polarity not inverted (master and slave operation) */ +#define _CGC_DSCLK1_POL_INVERT (0x00100000UL) /* Polarity inverted (master and slave operation) */ + +/* + PLL1 Control Register (PLL1CR) +*/ +#define _CGC_PLL1_CPUCKSEL_150 (0x00U) /* 150 MHz */ +#define _CGC_PLL1_CPUCKSEL_300 (0x01U) /* 300 MHz */ +#define _CGC_PLL1_CPUCKSEL_450 (0x02U) /* 450 MHz */ +#define _CGC_PLL1_CPUCKSEL_600 (0x03U) /* 600 MHz */ + +/* + PLL1 Control Register 2 (PLL1CR2) +*/ +#define _CGC_PLL1_DISABLE (0x00000000UL) /* PLL1 stops */ +#define _CGC_PLL1_ENABLE (0x00000001UL) /* PLL1 runs */ + +/* + Low-Speed On-Chip Oscillator Control Register (LOCOCR) +*/ +#define _CGC_LOCO_RUN (0x00000000UL) /* LOCO Run */ +#define _CGC_LOCO_STOP (0x00000001UL) /* LOCO Stop */ + +/* + Oscillation Stop Detection Control Register (OSTDCR) +*/ +/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */ +#define _CGC_OSC_STOP_DET_INT_DISABLE (0x00000000UL) /* Stop detection interrupt is disabled */ +#define _CGC_OSC_STOP_DET_INT_ENABLE (0x00000001UL) /* Stop detection interrupt is enabled */ +/* Oscillation Stop Detection Function Enable (OSTDE) */ +#define _CGC_OSC_STOP_DET_DISABLE (0x00000000UL) /* Oscillation stop detection function is disabled */ +#define _CGC_OSC_STOP_DET_ENABLE (0x00000080UL) /* Oscillation stop detection function is enabled */ + +/* + ECM Non-maskable Interrupt Configuration Register 0 (ECMNMICFG0) +*/ +#define _ECM_NMI_OSC_STOP_DISABLE (0x00000000UL) /* Stop detection NMI interrupt is disabled */ +#define _ECM_NMI_OSC_STOP_ENABLE (0x00080000UL) /* Stop detection NMI interrupt is enabled */ + +/* + ECM Maskable Interrupt Configuration Register 0 (ECMMICFG0) +*/ +#define _ECM_MI_OSC_STOP_DISABLE (0x00000000UL) /* Stop detection Maskable interrupt is disabled */ +#define _ECM_MI_OSC_STOP_ENABLE (0x00080000UL) /* Stop detection Maskable interrupt is enabled */ + +/* + Debugging Interface Control Register (DBGIFCNT) +*/ +#define _SWV_SEL_NOOUTPUT (0x00000000UL) /* SWV output is not output */ +#define _SWV_SEL_TDO (0x00000001UL) /* SWV output is output from the TDO pin */ +#define _SWV_SEL_TRACEDATA0 (0x00000002UL) /* SWV output is output from the TRACEDATA0 pin */ +#define _SWV_SEL_TRACECTL (0x00000003UL) /* SWV output is output from the TRACECTL pin */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _CGC_PLL_WAIT_CYCLE (0x1D4CU) /* Wait 100us when switch clock source in PLL0 and PLL1 */ +#define _CGC_LOCO_WAIT_CYCLE (0x0BB8U) /* Wait 40us for LOCO oscillation stabilization */ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); + +/* Start user code for function. Do not edit comment generated here */ + +void R_CPG_PLLWait(void); +void R_CPG_WriteEnable(void); +void R_CPG_WriteDisable(void); + +#define CPG_CPUCLK_150_MHz (0) +#define CPG_CPUCLK_300_MHz (1) +#define CPG_CPUCLK_450_MHz (2) +#define CPG_CPUCLK_600_MHz (3) + +#define CPG_PLL1_OFF (0) +#define CPG_PLL1_ON (1) + +#define CPG_SELECT_PLL0 (0) +#define CPG_SELECT_PLL1 (1) + +#define CPG_CKIO_75_MHz (0) +#define CPG_CKIO_50_MHz (1) +#define CPG_CKIO_37_5_MHz (2) +#define CPG_CKIO_30_MHz (3) +#define CPG_CKIO_25_MHz (4) +#define CPG_CKIO_21_43_MHz (5) +#define CPG_CKIO_18_75_MHz (6) + +#define CPG_LOCO_ENABLE (0x00000000) +#define CPG_LOCO_DISABLE (0x00000001) + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc_user.c new file mode 100644 index 000000000..debe5a292 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cgc_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc_user.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for CGC module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cmt.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cmt.h new file mode 100644 index 000000000..c2e456863 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cmt.h @@ -0,0 +1,112 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cmt.h +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for CMT module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ +#ifndef CMT_H +#define CMT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Compare Match Timer Control Register (CMCR) +*/ +/* Clock Select (CKS[1:0]) */ +#define _CMT_CMCR_CKS_PCLK8 (0x0000U) /* PCLK/8 */ +#define _CMT_CMCR_CKS_PCLK32 (0x0001U) /* PCLK/32 */ +#define _CMT_CMCR_CKS_PCLK128 (0x0002U) /* PCLK/128 */ +#define _CMT_CMCR_CKS_PCLK512 (0x0003U) /* PCLK/512 */ +/* Compare Match Interrupt Enable (CMIE) */ +#define _CMT_CMCR_CMIE_DISABLE (0x0000U) /* Compare match interrupt (CMIn) disabled */ +#define _CMT_CMCR_CMIE_ENABLE (0x0040U) /* Compare match interrupt (CMIn) enabled */ + +/* + Interrupt Priority Level Store Register n (PRLn) +*/ +/* Interrupt Priority Level Store (PRL[3:0]) */ +#define _CMT_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */ +#define _CMT_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */ +#define _CMT_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */ +#define _CMT_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */ +#define _CMT_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */ +#define _CMT_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */ +#define _CMT_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */ +#define _CMT_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */ +#define _CMT_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */ +#define _CMT_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */ +#define _CMT_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */ +#define _CMT_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */ +#define _CMT_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */ +#define _CMT_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */ +#define _CMT_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */ +#define _CMT_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */ +#define _CMT_PRIORITY_LEVEL16 (0x00000000UL) /* Level 16 */ +#define _CMT_PRIORITY_LEVEL17 (0x00000001UL) /* Level 17 */ +#define _CMT_PRIORITY_LEVEL18 (0x00000002UL) /* Level 18 */ +#define _CMT_PRIORITY_LEVEL19 (0x00000003UL) /* Level 19 */ +#define _CMT_PRIORITY_LEVEL20 (0x00000004UL) /* Level 20 */ +#define _CMT_PRIORITY_LEVEL21 (0x00000005UL) /* Level 21 */ +#define _CMT_PRIORITY_LEVEL22 (0x00000006UL) /* Level 22 */ +#define _CMT_PRIORITY_LEVEL23 (0x00000007UL) /* Level 23 */ +#define _CMT_PRIORITY_LEVEL24 (0x00000008UL) /* Level 24 */ +#define _CMT_PRIORITY_LEVEL25 (0x00000009UL) /* Level 25 */ +#define _CMT_PRIORITY_LEVEL26 (0x0000000AUL) /* Level 26 */ +#define _CMT_PRIORITY_LEVEL27 (0x0000000BUL) /* Level 27 */ +#define _CMT_PRIORITY_LEVEL28 (0x0000000CUL) /* Level 28 */ +#define _CMT_PRIORITY_LEVEL29 (0x0000000DUL) /* Level 29 */ +#define _CMT_PRIORITY_LEVEL30 (0x0000000EUL) /* Level 30 */ +#define _CMT_PRIORITY_LEVEL31 (0x0000000FUL) /* Level 31 (lowest) */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* Compare Match Timer Constant Register (CMCOR) */ +#define _CMT4_CMCOR_VALUE (0x0008U) +/* Compare Match Timer Constant Register (CMCOR) */ +#define _CMT5_CMCOR_VALUE (0x249EU) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CMT4_Create(void); +void R_CMT4_Start(void); +void R_CMT4_Stop(void); +void R_CMT5_Create(void); +void R_CMT5_Start(void); +void R_CMT5_Stop(void); + +/* Start user code for function. Do not edit comment generated here */ + +/* Counters used to generate user's delay period */ +extern volatile uint32_t g_time_ms_count; +extern volatile uint32_t g_time_us_count; + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cmt_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cmt_user.c new file mode 100644 index 000000000..ae2d886af --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_cmt_user.c @@ -0,0 +1,99 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cmt_user.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for CMT module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cmt.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ + +/* Counters used to generate user's delay period */ +volatile uint32_t g_time_ms_count; +volatile uint32_t g_time_us_count; + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_cmt_cmi4_interrupt +* Description : This function is CMI4 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_cmt_cmi4_interrupt(void) +{ + /* Clear the interrupt source CMI4 */ + VIC.PIC9.LONG = 0x00000800UL; + + /* Start user code. Do not edit comment generated here */ + + /* Decrement the count value */ + g_time_us_count--; + + /* End user code. Do not edit comment generated here */ + + /* Dummy write */ + VIC.HVA0.LONG = 0x00000000UL; +} +/*********************************************************************************************************************** +* Function Name: r_cmt_cmi5_interrupt +* Description : This function is CMI5 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_cmt_cmi5_interrupt(void) +{ + /* Clear the interrupt source CMI5 */ + VIC.PIC9.LONG = 0x00001000UL; + + /* Start user code. Do not edit comment generated here */ + + /* Decrement the count value */ + g_time_ms_count--; + + /* End user code. Do not edit comment generated here */ + + /* Dummy write */ + VIC.HVA0.LONG = 0x00000000UL; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu.c new file mode 100644 index 000000000..b8cd5b323 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu.c @@ -0,0 +1,102 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_icu.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for ICU module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_icu.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_ICU_Create +* Description : This function initializes ICU module. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_Create(void) +{ + + /* Disable IRQ12 interrupt */ + VIC.IEC0.LONG = 0x00010000UL; + + /* Set IRQ12 edge detection type */ + VIC.PLS0.LONG |= 0x00010000UL; + ICU.IRQCR12.BIT.IRQMD = (uint8_t)_ICU_IRQ_EDGE_FALLING; + + /* Enable IRQ12 digital filter */ + ICU.IRQFLTE.BIT.FLTEN12 = 1U; + + /* Set IRQ12 digital filter clock */ + ICU.IRQFLTC.BIT.FCLKSEL12 = _ICU_IRQ12_FILTER_PCLKB_64; + + /* Set IRQ12 Priority */ + VIC.PRL16.LONG = _ICU_PRIORITY_LEVEL3; + + /* Set IRQ12 interupt address */ + VIC.VAD16.LONG = (uint32_t)r_icu_irq12_interrupt; +} +/*********************************************************************************************************************** +* Function Name: R_ICU_IRQ12_Start +* Description : This function enables IRQ12 interrupt. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_IRQ12_Start(void) +{ + /* Enable IRQ12 interrupt */ + VIC.IEN0.LONG |= 0x00010000UL; +} +/*********************************************************************************************************************** +* Function Name: R_ICU_IRQ12_Stop +* Description : This function disables IRQ12 interrupt. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_ICU_IRQ12_Stop(void) +{ + /* Disable IRQ12 interrupt */ + VIC.IEC0.LONG = 0x00010000UL; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu.h new file mode 100644 index 000000000..acd76789a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu.h @@ -0,0 +1,326 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_icu.h +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for ICU module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ +#ifndef ICU_H +#define ICU_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/* + DMAC Software Activation Register (DMASTG) +*/ +/* DMA Unit 0 Software Activation (DMREQ0) */ +#define _DMA_UNIT0_SOFTWARE_ACTIVATION_DISABLE (0x00U) /* DMA transfer is not requested for DMA Unit 0*/ +#define _DMA_UNIT0_SOFTWARE_ACTIVATION_ENABLE (0x01U) /* DMA transfer is requested for DMA Unit 0 */ +/* DMA Unit 1 Software Activation (DMREQ1) */ +#define _DMA_UNIT1_SOFTWARE_ACTIVATION_DISABLE (0x00U) /* DMA transfer is not requested for DMA Unit 1*/ +#define _DMA_UNIT1_SOFTWARE_ACTIVATION_ENABLE (0x02U) /* DMA transfer is requested for DMA Unit 1*/ + +/* + IRQ Control Register i (IRQCRi) (i = 0 to 15) +*/ +/* IRQ Detection Sense Select (IRQMD[1:0]) */ +#define _ICU_IRQ_EDGE_LOW_LEVEL (0x00U) /* Low level */ +#define _ICU_IRQ_EDGE_FALLING (0x01U) /* Falling edge */ +#define _ICU_IRQ_EDGE_RISING (0x02U) /* Rising edge */ +#define _ICU_IRQ_EDGE_BOTH (0x03U) /* Rising and falling edge */ + +/* + IRQ Pin Digital Noise Filter Enable Register 0 (IRQFLTE) +*/ +/* IRQn Digital Noise Filter Enable (FLTEN0n) */ +#define _ICU_IRQn_FILTER_DISABLE (0x00000000UL) /* IRQn digital noise filter is disabled */ +#define _ICU_IRQ0_FILTER_ENABLE (0x00000001UL) /* IRQ0 digital noise filter is enabled */ +#define _ICU_IRQ1_FILTER_ENABLE (0x00000002UL) /* IRQ1 digital noise filter is enabled */ +#define _ICU_IRQ2_FILTER_ENABLE (0x00000004UL) /* IRQ2 digital noise filter is enabled */ +#define _ICU_IRQ3_FILTER_ENABLE (0x00000008UL) /* IRQ3 digital noise filter is enabled */ +#define _ICU_IRQ4_FILTER_ENABLE (0x00000010UL) /* IRQ4 digital noise filter is enabled */ +#define _ICU_IRQ5_FILTER_ENABLE (0x00000020UL) /* IRQ5 digital noise filter is enabled */ +#define _ICU_IRQ6_FILTER_ENABLE (0x00000040UL) /* IRQ6 digital noise filter is enabled */ +#define _ICU_IRQ7_FILTER_ENABLE (0x00000080UL) /* IRQ7 digital noise filter is enabled */ +#define _ICU_IRQ8_FILTER_ENABLE (0x00000100UL) /* IRQ8 digital noise filter is enabled */ +#define _ICU_IRQ9_FILTER_ENABLE (0x00000200UL) /* IRQ9 digital noise filter is enabled */ +#define _ICU_IRQ10_FILTER_ENABLE (0x00000400UL) /* IRQ10 digital noise filter is enabled */ +#define _ICU_IRQ11_FILTER_ENABLE (0x00000800UL) /* IRQ11 digital noise filter is enabled */ +#define _ICU_IRQ12_FILTER_ENABLE (0x00001000UL) /* IRQ12 digital noise filter is enabled */ +#define _ICU_IRQ13_FILTER_ENABLE (0x00002000UL) /* IRQ13 digital noise filter is enabled */ +#define _ICU_IRQ14_FILTER_ENABLE (0x00004000UL) /* IRQ14 digital noise filter is enabled */ +#define _ICU_IRQ15_FILTER_ENABLE (0x00008000UL) /* IRQ15 digital noise filter is enabled */ + +/* + IRQ Pin Digital Filter Setting Register (IRQFLTC) +*/ +/* IRQn Digital Filter Sampling Clock (FCLKSELn[1:0]) */ +#define _ICU_IRQ0_FILTER_PCLKB (0x00U) /* IRQ0 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ0_FILTER_PCLKB_8 (0x01U) /* IRQ0 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ0_FILTER_PCLKB_32 (0x02U) /* IRQ0 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ0_FILTER_PCLKB_64 (0x03U) /* IRQ0 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ1_FILTER_PCLKB (0x00U) /* IRQ1 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ1_FILTER_PCLKB_8 (0x01U) /* IRQ1 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ1_FILTER_PCLKB_32 (0x02U) /* IRQ1 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ1_FILTER_PCLKB_64 (0x03U) /* IRQ1 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ2_FILTER_PCLKB (0x00U) /* IRQ2 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ2_FILTER_PCLKB_8 (0x01U) /* IRQ2 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ2_FILTER_PCLKB_32 (0x02U) /* IRQ2 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ2_FILTER_PCLKB_64 (0x03U) /* IRQ2 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ3_FILTER_PCLKB (0x00U) /* IRQ3 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ3_FILTER_PCLKB_8 (0x01U) /* IRQ3 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ3_FILTER_PCLKB_32 (0x02U) /* IRQ3 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ3_FILTER_PCLKB_64 (0x03U) /* IRQ3 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ4_FILTER_PCLKB (0x00U) /* IRQ4 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ4_FILTER_PCLKB_8 (0x01U) /* IRQ4 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ4_FILTER_PCLKB_32 (0x02U) /* IRQ4 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ4_FILTER_PCLKB_64 (0x03U) /* IRQ4 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ5_FILTER_PCLKB (0x00U) /* IRQ5 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ5_FILTER_PCLKB_8 (0x01U) /* IRQ5 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ5_FILTER_PCLKB_32 (0x02U) /* IRQ5 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ5_FILTER_PCLKB_64 (0x03U) /* IRQ5 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ6_FILTER_PCLKB (0x00U) /* IRQ6 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ6_FILTER_PCLKB_8 (0x01U) /* IRQ6 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ6_FILTER_PCLKB_32 (0x02U) /* IRQ6 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ6_FILTER_PCLKB_64 (0x03U) /* IRQ6 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ7_FILTER_PCLKB (0x00U) /* IRQ7 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ7_FILTER_PCLKB_8 (0x01U) /* IRQ7 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ7_FILTER_PCLKB_32 (0x02U) /* IRQ7 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ7_FILTER_PCLKB_64 (0x03U) /* IRQ7 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ8_FILTER_PCLKB (0x00U) /* IRQ8 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ8_FILTER_PCLKB_8 (0x01U) /* IRQ8 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ8_FILTER_PCLKB_32 (0x02U) /* IRQ8 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ8_FILTER_PCLKB_64 (0x03U) /* IRQ8 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ9_FILTER_PCLKB (0x00U) /* IRQ9 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ9_FILTER_PCLKB_8 (0x01U) /* IRQ9 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ9_FILTER_PCLKB_32 (0x02U) /* IRQ9 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ9_FILTER_PCLKB_64 (0x03U) /* IRQ9 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ10_FILTER_PCLKB (0x00U) /* IRQ10 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ10_FILTER_PCLKB_8 (0x01U) /* IRQ10 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ10_FILTER_PCLKB_32 (0x02U) /* IRQ10 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ10_FILTER_PCLKB_64 (0x03U) /* IRQ10 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ11_FILTER_PCLKB (0x00U) /* IRQ11 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ11_FILTER_PCLKB_8 (0x01U) /* IRQ11 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ11_FILTER_PCLKB_32 (0x02U) /* IRQ11 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ11_FILTER_PCLKB_64 (0x03U) /* IRQ11 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ12_FILTER_PCLKB (0x00U) /* IRQ12 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ12_FILTER_PCLKB_8 (0x01U) /* IRQ12 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ12_FILTER_PCLKB_32 (0x02U) /* IRQ12 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ12_FILTER_PCLKB_64 (0x03U) /* IRQ12 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ13_FILTER_PCLKB (0x00U) /* IRQ13 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ13_FILTER_PCLKB_8 (0x01U) /* IRQ13 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ13_FILTER_PCLKB_32 (0x02U) /* IRQ13 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ13_FILTER_PCLKB_64 (0x03U) /* IRQ13 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ14_FILTER_PCLKB (0x00U) /* IRQ14 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ14_FILTER_PCLKB_8 (0x01U) /* IRQ14 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ14_FILTER_PCLKB_32 (0x02U) /* IRQ14 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ14_FILTER_PCLKB_64 (0x03U) /* IRQ14 sample clock run at every PCLKB/64 cycle */ +#define _ICU_IRQ15_FILTER_PCLKB (0x00U) /* IRQ15 sample clock run at every PCLKB cycle */ +#define _ICU_IRQ15_FILTER_PCLKB_8 (0x01U) /* IRQ15 sample clock run at every PCLKB/8 cycle */ +#define _ICU_IRQ15_FILTER_PCLKB_32 (0x02U) /* IRQ15 sample clock run at every PCLKB/32 cycle */ +#define _ICU_IRQ15_FILTER_PCLKB_64 (0x03U) /* IRQ15 sample clock run at every PCLKB/64 cycle */ + +/* + Interrupt Source Priority Register n (IPRn) +*/ +/* Interrupt Priority Level Select (IPR[3:0]) */ +#define _ICU_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (interrupt disabled) */ +#define _ICU_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */ +#define _ICU_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */ +#define _ICU_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */ +#define _ICU_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */ +#define _ICU_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */ +#define _ICU_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */ +#define _ICU_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */ +#define _ICU_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */ +#define _ICU_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */ +#define _ICU_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */ +#define _ICU_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */ +#define _ICU_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */ +#define _ICU_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */ +#define _ICU_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */ +#define _ICU_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 (highest) */ + +/* + NMI Pin Interrupt Control Register (NMICR) +*/ +/* NMI Detection Sense Selection (NMIMD) */ +#define _ICU_NMI_DETECTION_SENSE_FALLING (0x00U) /* Falling edge */ +#define _ICU_NMI_DETECTION_SENSE_RISING (0x08U) /* Rising edge */ + +/* + DMA Noise Filter Setting Register (DMAINT) +*/ +/* DMA Digital Noise Filter Sampling Clock (DREQFLTC[1:0]) */ +#define _ICU_DMAINT0_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */ +#define _ICU_DMAINT0_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */ +#define _ICU_DMAINT0_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */ +#define _ICU_DMAINT0_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */ +#define _ICU_DMAINT1_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */ +#define _ICU_DMAINT1_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */ +#define _ICU_DMAINT1_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */ +#define _ICU_DMAINT1_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */ +#define _ICU_DMAINT2_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */ +#define _ICU_DMAINT2_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */ +#define _ICU_DMAINT2_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */ +#define _ICU_DMAINT2_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */ + +/* + NMI Pin Digital Noise Filter Setting Register (NMIFLTC) +*/ +/* NMI Digital Noise Filter Sampling Clock (NFCLKSEL[1:0]) */ +#define _ICU_NMI_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */ +#define _ICU_NMI_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */ +#define _ICU_NMI_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */ +#define _ICU_NMI_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */ + +/* + EtherPHY Control Register i (EPHYCRi) (i = 0 to 2) +*/ +/* EtherPHYn interrupt Detection Setting (EPHYMD[1:0]) */ +#define _ICU_ETHERPHY0_EDGE_LOW_LEVEL (0x00U) /* Low level */ +#define _ICU_ETHERPHY0_EDGE_FALLING (0x01U) /* Falling edge */ +#define _ICU_ETHERPHY0_EDGE_RISING (0x02U) /* Rising edge */ +#define _ICU_ETHERPHY0_EDGE_BOTH (0x03U) /* Rising and falling edge */ +#define _ICU_ETHERPHY1_EDGE_LOW_LEVEL (0x00U) /* Low level */ +#define _ICU_ETHERPHY1_EDGE_FALLING (0x01U) /* Falling edge */ +#define _ICU_ETHERPHY1_EDGE_RISING (0x02U) /* Rising edge */ +#define _ICU_ETHERPHY1_EDGE_BOTH (0x03U) /* Rising and falling edge */ +#define _ICU_ETHERPHY2_EDGE_LOW_LEVEL (0x00U) /* Low level */ +#define _ICU_ETHERPHY2_EDGE_FALLING (0x01U) /* Falling edge */ +#define _ICU_ETHERPHY2_EDGE_RISING (0x02U) /* Rising edge */ +#define _ICU_ETHERPHY2_EDGE_BOTH (0x03U) /* Rising and falling edge */ + +/* + EtherPHY Interrupt Request Pin Digital Noise Filter Enable Register 0 (EPHYFLTE) +*/ +/* EtherPHYn Interrupt Digital Noise Filter Enable (EFLTENn) */ +#define _ICU_ETHERPHYn_FILTER_DISABLE (0x00U) /* ETHER PHY0 digital noise filter is disabled */ +#define _ICU_ETHERPHY0_FILTER_ENABLE (0x01U) /* ETHER PHY0 digital noise filter is enabled */ +#define _ICU_ETHERPHY1_FILTER_ENABLE (0x01U) /* ETHER PHY1 digital noise filter is enabled */ +#define _ICU_ETHERPHY2_FILTER_ENABLE (0x01U) /* ETHER PHY2 digital noise filter is enabled */ + +/* + EtherPHY Interrupt Request Pin Digital Filter Setting Register (EPHYFLTC) +*/ +/* EtherPHYn Interrupts Digital Noise Filter Sampling Clock (EFCLKSELn[1:0]) */ +#define _ICU_ETHPHYI0_FILTER_PCLKB (0x00U) /* ETHER PHY0 sample clock is run at every PCLKB cycle */ +#define _ICU_ETHPHYI0_FILTER_PCLKB_8 (0x01U) /* ETHER PHY0 sample clock is run at every PCLKB/8 cycle */ +#define _ICU_ETHPHYI0_FILTER_PCLKB_32 (0x02U) /* ETHER PHY0 sample clock is run at every PCLKB/32 cycle */ +#define _ICU_ETHPHYI0_FILTER_PCLKB_64 (0x03U) /* ETHER PHY0 sample clock is run at every PCLKB/64 cycle */ +#define _ICU_ETHPHYI1_FILTER_PCLKB (0x00U) /* ETHER PHY1 sample clock is run at every PCLKB cycle */ +#define _ICU_ETHPHYI1_FILTER_PCLKB_8 (0x01U) /* ETHER PHY1 sample clock is run at every PCLKB/8 cycle */ +#define _ICU_ETHPHYI1_FILTER_PCLKB_32 (0x02U) /* ETHER PHY1 sample clock is run at every PCLKB/32 cycle */ +#define _ICU_ETHPHYI1_FILTER_PCLKB_64 (0x03U) /* ETHER PHY1 sample clock is run at every PCLKB/64 cycle */ +#define _ICU_ETHPHYI2_FILTER_PCLKB (0x00U) /* ETHER PHY2 sample clock is run at every PCLKB cycle */ +#define _ICU_ETHPHYI2_FILTER_PCLKB_8 (0x01U) /* ETHER PHY2 sample clock is run at every PCLKB/8 cycle */ +#define _ICU_ETHPHYI2_FILTER_PCLKB_32 (0x02U) /* ETHER PHY2 sample clock is run at every PCLKB/32 cycle */ +#define _ICU_ETHPHYI2_FILTER_PCLKB_64 (0x03U) /* ETHER PHY2 sample clock is run at every PCLKB/64 cycle */ + +/* + External DMA Request Pin Digital Noise Enable Register (DREQFLTE) +*/ +/* DREQn Digital Noise Filter Enable (DFLTENn) */ +#define _ICU_DREQn_FILTER_DISABLE (0x00U) /* Digital noise filter is disabled */ +#define _ICU_DREQ0_FILTER_ENABLE (0x01U) /* DREQ0 Digital noise filter is enabled */ +#define _ICU_DREQ1_FILTER_ENABLE (0x01U) /* DREQ1 Digital noise filter is enabled */ +#define _ICU_DREQ2_FILTER_ENABLE (0x01U) /* DREQ2 Digital noise filter is enabled */ + +/* + External DMA Request Pin Digital Noise Setting Register (DREQFLTC) +*/ +/* DREQn Digital Noise Filter Sampling Clock (DFCLKSELn[1:0]) */ +#define _ICU_DREQ0_FILTER_PCLKB (0x00U) /* DREQ0 sample clock is run at every PCLKB cycle */ +#define _ICU_DREQ0_FILTER_PCLKB_8 (0x01U) /* DREQ0 sample clock is run at every PCLKB/8 cycle */ +#define _ICU_DREQ0_FILTER_PCLKB_32 (0x02U) /* DREQ0 sample clock is run at every PCLKB/32 cycle */ +#define _ICU_DREQ0_FILTER_PCLKB_64 (0x03U) /* DREQ0 sample clock is run at every PCLKB/64 cycle */ +#define _ICU_DREQ1_FILTER_PCLKB (0x00U) /* DREQ1 sample clock is run at every PCLKB cycle */ +#define _ICU_DREQ1_FILTER_PCLKB_8 (0x01U) /* DREQ1 sample clock is run at every PCLKB/8 cycle */ +#define _ICU_DREQ1_FILTER_PCLKB_32 (0x02U) /* DREQ1 sample clock is run at every PCLKB/32 cycle */ +#define _ICU_DREQ1_FILTER_PCLKB_64 (0x03U) /* DREQ1 sample clock is run at every PCLKB/64 cycle */ +#define _ICU_DREQ2_FILTER_PCLKB (0x00U) /* DREQ2 sample clock is run at every PCLKB cycle */ +#define _ICU_DREQ2_FILTER_PCLKB_8 (0x01U) /* DREQ2 sample clock is run at every PCLKB/8 cycle */ +#define _ICU_DREQ2_FILTER_PCLKB_32 (0x02U) /* DREQ2 sample clock is run at every PCLKB/32 cycle */ +#define _ICU_DREQ2_FILTER_PCLKB_64 (0x03U) /* DREQ2 sample clock is run at every PCLKB/64 cycle */ + +/* + User Mode Enable Register 0 (UEN0) +*/ +/* Interrupt control register access selection (UE) */ +#define _ICU_UEN0_CTRL_REG_ACCESS_DISABLE (0x00000000UL) /* Disables access in user mode. */ +#define _ICU_UEN0_CTRL_REG_ACCESS_ENABLE (0x00000001UL) /* Enables access in user mode. */ + +/* + User Mode Enable Register 1 (UEN1) +*/ +/* Interrupt control register access selection (UE) */ +#define _ICU_UEN1_CTRL_REG_ACCESS_DISABLE (0x00000000UL) /* Disables access in user mode. */ +#define _ICU_UEN1_CTRL_REG_ACCESS_ENABLE (0x00000001UL) /* Enables access in user mode. */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_ICU_Create(void); +void R_ICU_IRQ12_Start(void); +void R_ICU_IRQ12_Stop(void); + +/* Start user code for function. Do not edit comment generated here */ + +#define SW1_PRESS_FLG (0x01) +#define SW2_PRESS_FLG (0x02) +#define SW3_PRESS_FLG (0x04) + +#define SW1_HELD_FLG (0x10) +#define SW2_HELD_FLG (0x20) +#define SW3_HELD_FLG (0x40) + +#define SW1_SET_FLG_MASK (0xEE) +#define SW2_SET_FLG_MASK (0xDD) +#define SW3_SET_FLG_MASK (0xBB) + +#define SW_ALL_OFF (0xF8) + +#define SW1_INPUT_STATE (PORT3.PIDR.BIT.B5) +#define SW2_INPUT_STATE (PORTN.PIDR.BIT.B5) +#define SW3_INPUT_STATE (PORT4.PIDR.BIT.B4) + +#define SW1_OUTPUT_PIN (PORT3.PODR.BIT.B5) +#define SW2_OUTPUT_PIN (PORTN.PODR.BIT.B5) +#define SW3_OUTPUT_PIN (PORT4.PODR.BIT.B4) + +/* Stores switch states detected via interrupts */ +extern volatile uint8_t g_switch_press_flg; + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu_user.c new file mode 100644 index 000000000..8dac89a7c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_icu_user.c @@ -0,0 +1,76 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_icu_user.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for ICU module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_icu.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ + +/* Stores switch states detected via interrupts */ +volatile uint8_t g_switch_press_flg = 0u; + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_icu_irq12_interrupt +* Description : This function handles the irqn pin interrupt. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#ifdef __ICCARM__ + __irq __arm +#endif /* __ICCARM__ */ +void r_icu_irq12_interrupt(void) +{ + VIC.PIC0.LONG = 0x00010000UL; + /* Start user code. Do not edit comment generated here */ + + /* Set global switch flag to indicate SW3 is pressed */ + g_switch_press_flg |= SW3_PRESS_FLG; + + /* End user code. Do not edit comment generated here */ + VIC.HVA0.LONG = 0x00000000UL; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_interrupthandlers.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_interrupthandlers.h new file mode 100644 index 000000000..2f0f9357c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_interrupthandlers.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_interrupthandlers.h +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file declares interrupt handlers. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ +#ifndef INTERRUPT_HANDLERS_H +#define INTERRUPT_HANDLERS_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* FIQ exception handler */ +#ifdef __ICCARM__ + __irq __arm void r_fiq_handler(void); + + /* ICU IRQ12 */ + __irq __arm void r_icu_irq12_interrupt(void); + + /* RSPI1 SPTI1 */ + __irq __arm void r_rspi1_transmit_interrupt(void); + + /* RSPI1 SPEI1 */ + __irq __arm void r_rspi1_error_interrupt(void); + + /* RSPI1 SPII1 */ + __irq __arm void r_rspi1_idle_interrupt(void); +#endif /* __ICCARM__ */ + +#ifdef __GNUC__ + void r_fiq_handler(void) __attribute__((interrupt ("FIQ"))); + + /* ICU IRQ12 */ + void r_icu_irq12_interrupt(void) __attribute__((interrupt ("IRQ"))); + + /* RSPI1 SPTI1 */ + void r_rspi1_transmit_interrupt(void) __attribute__((interrupt ("IRQ"))); + + /* RSPI1 SPEI1 */ + void r_rspi1_error_interrupt(void) __attribute__((interrupt ("IRQ"))); + + /* RSPI1 SPII1 */ + void r_rspi1_idle_interrupt(void) __attribute__((interrupt ("IRQ"))); +#endif /* __GNUC__ */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_intprg.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_intprg.c new file mode 100644 index 000000000..256ffaae7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_intprg.c @@ -0,0 +1,87 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_intprg.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : Set the non-maskable interrupt. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/*********************************************************************************************************************** +* Function Name: r_set_exception_handler +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_set_exception_handler(void) +{ + uint32_t *pointer; + + /* FIQ exception handler address */ + pointer = (uint32_t *)0x1c; + + /* Branch to next address instruction */ + *pointer ++ = 0xeaffffff; + + /* LDR PC,[PC, #-0x04], load r_fiq_handler address to PC */ + *pointer ++ = 0xe51ff004; + + /* DC32 r_fiq_handler, define the r_fiq_handler address */ + *pointer = (uint32_t)r_fiq_handler; + + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_fiq_handler +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#ifdef __ICCARM__ + __irq __arm +#endif /* __ICCARM__ */ +void r_fiq_handler(void) +{ + while(1); + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_macrodriver.h new file mode 100644 index 000000000..79afd916a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_macrodriver.h @@ -0,0 +1,149 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements general head file. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ +#ifndef MODULEID_H +#define MODULEID_H +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include +#include "iodefine.h" +#include "r_cg_interrupthandlers.h" +#include "r_cg_mpc.h" + + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ +#define DI() asm("cpsid i") /* Disable IRQ interrupt (Set CPSR.I bit to 1) */ +#define EI() asm("cpsie i") /* Enable IRQ interrupt (Clear CPSR.I bit to 0) */ +#define nop() asm("nop") + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + +/* MSTP macro definition */ +#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPCRA0 +#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPCRA1 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPCRA2 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPCRA3 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPCRA4 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPCRA5 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPCRA6 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPCRA7 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPCRA8 +#define MSTP_GPTA SYSTEM.MSTPCRA.BIT.MSTPCRA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPCRA11 + +#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPCRB1 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPCRB2 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPCRB3 +#define MSTP_SCIFA4 SYSTEM.MSTPCRB.BIT.MSTPCRB5 +#define MSTP_SCIFA3 SYSTEM.MSTPCRB.BIT.MSTPCRB6 +#define MSTP_SCIFA2 SYSTEM.MSTPCRB.BIT.MSTPCRB7 +#define MSTP_SCIFA1 SYSTEM.MSTPCRB.BIT.MSTPCRB8 +#define MSTP_SCIFA0 SYSTEM.MSTPCRB.BIT.MSTPCRB9 +#define MSTP_RSPI3 SYSTEM.MSTPCRB.BIT.MSTPCRB10 +#define MSTP_RSPI2 SYSTEM.MSTPCRB.BIT.MSTPCRB11 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPCRB12 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPCRB13 +#define MSTP_ETHERSW SYSTEM.MSTPCRB.BIT.MSTPCRB14 +#define MSTP_ECATC SYSTEM.MSTPCRB.BIT.MSTPCRB15 +#define MSTP_EMDIO SYSTEM.MSTPCRB.BIT.MSTPCRB16 +#define MSTP_ERMII SYSTEM.MSTPCRB.BIT.MSTPCRB17 +#define MSTP_HWRTOS SYSTEM.MSTPCRB.BIT.MSTPCRB18 +#define MSTP_CLKOUT25M SYSTEM.MSTPCRB.BIT.MSTPCRB19 + +#define MSTP_USB SYSTEM.MSTPCRC.BIT.MSTPCRC1 +#define MSTP_DSMIF SYSTEM.MSTPCRC.BIT.MSTPCRC2 +#define MSTP_TEMPS SYSTEM.MSTPCRC.BIT.MSTPCRC3 +#define MSTP_S12ADC1 SYSTEM.MSTPCRC.BIT.MSTPCRC4 +#define MSTP_S12ADC0 SYSTEM.MSTPCRC.BIT.MSTPCRC5 +#define MSTP_ELC SYSTEM.MSTPCRC.BIT.MSTPCRC6 +#define MSTP_BSC SYSTEM.MSTPCRC.BIT.MSTPCRC7 +#define MSTP_CKIO SYSTEM.MSTPCRC.BIT.MSTPCRC8 +#define MSTP_SPIBSC SYSTEM.MSTPCRC.BIT.MSTPCRC9 +#define MSTP_DOC SYSTEM.MSTPCRC.BIT.MSTPCRC10 +#define MSTP_CRC SYSTEM.MSTPCRC.BIT.MSTPCRC11 +#define MSTP_CLMA2 SYSTEM.MSTPCRC.BIT.MSTPCRC12 +#define MSTP_CLMA1 SYSTEM.MSTPCRC.BIT.MSTPCRC13 +#define MSTP_CLMA0 SYSTEM.MSTPCRC.BIT.MSTPCRC14 + +#define MSTP_SSI SYSTEM.MSTPCRD.BIT.MSTPCRD2 + +#define MSTP_DMAC1 SYSTEM.MSTPCRE.BIT.MSTPCRE4 +#define MSTP_DMAC0 SYSTEM.MSTPCRE.BIT.MSTPCRE5 + +#define MSTP_CORESIGHT SYSTEM.MSTPCRF.BIT.MSTPCRF0 + +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + #ifndef __ICCARM__ + typedef signed char int8_t; + typedef unsigned char uint8_t; + typedef signed short int16_t; + typedef unsigned short uint16_t; + typedef signed long int32_t; + typedef unsigned long uint32_t; + #endif /* __ICCARM__ */ + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_mpc.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_mpc.c new file mode 100644 index 000000000..56a770f87 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_mpc.c @@ -0,0 +1,155 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_mpc.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : Setting of port and mpc registers. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +#include "r_typedefs.h" +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_mpc.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name: R_MPC_Create +* Description : This function initializes the Port I/O. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_MPC_Create(void) +{ + /* Set RSPCK1 pin */ + MPC.PN3PFS.BYTE |= 0x0EU; + PORTN.PMR.BYTE |= 0x08U; + /* Set MOSI1 pin */ + MPC.PN2PFS.BYTE |= 0x0EU; + PORTN.PMR.BYTE |= 0x04U; + /* Set MISO1 pin */ + MPC.PN1PFS.BYTE |= 0x0EU; + PORTN.PMR.BYTE |= 0x02U; + /* Set SSL10 pin */ + MPC.PN0PFS.BYTE |= 0x0EU; + PORTN.PMR.BYTE |= 0x01U; + /* Set SSL11 pin */ + MPC.PN4PFS.BYTE |= 0x0EU; + PORTN.PMR.BYTE |= 0x10U; + /* Set TXD2 pin */ + MPC.P91PFS.BYTE |= 0x0BU; + PORT9.PMR.BYTE |= 0x02U; + /* Set RXD2 pin */ + MPC.P92PFS.BYTE |= 0x0BU; + PORT9.PMR.BYTE |= 0x04U; + /* Set IRQ12 pin */ + MPC.P44PFS.BYTE |= 0x40U; + PORT4.PMR.BYTE &= 0xEFU; + PORT4.PDR.WORD &= 0xFEFFU; + PORT4.PDR.WORD |= 0x0200U; + /* Set TIOCB9 pin */ + MPC.PL0PFS.BYTE |= 0x03U; + PORTL.PMR.BYTE |= 0x01U; + /* Set TIOCC9 pin */ + MPC.PU4PFS.BYTE |= 0x03U; + PORTU.PMR.BYTE |= 0x10U; + /* Set TIOCD9 pin */ + MPC.PN5PFS.BYTE |= 0x03U; + PORTN.PMR.BYTE |= 0x20U; + + R_MPC_Create_UserInit(); +} +/*********************************************************************************************************************** +* Function Name: R_MPC_Create_UserInit +* Description : This function adds user code after initializing modules pin setting. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_MPC_Create_UserInit(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name : R_MPC_WriteEnable +* Description : Enables writing to the PmnPFS register (m = 0-9, A-U, n = 0-7). + And dummy read the register in order to fix the register value. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_MPC_WriteEnable(void) +{ + volatile uint8_t dummy=0; + + UNUSED_VARIABLE(dummy); + + /* Enables writing to the PmnPFS register */ + MPC.PWPR.BYTE = MPC_PFSWE_WRITE_ENABLE; + dummy = MPC.PWPR.BYTE; + MPC.PWPR.BYTE = MPC_PFS_WRITE_ENABLE; + dummy = MPC.PWPR.BYTE; + +} + +/*********************************************************************************************************************** + End of function R_MPC_WriteEnable +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* Function Name : R_MPC_WriteDisable +* Description : Disables writing to the PmnPFS register (m = 0-9, A-U, n = 0-7). + And dummy read the register in order to fix the register value. +* Arguments : none +* Return Value : none +***********************************************************************************************************************/ +void R_MPC_WriteDisable(void) +{ + volatile uint8_t dummy=0; + + UNUSED_PARAM(dummy); + + /* Disables writing to the PmnPFS register */ + MPC.PWPR.BYTE = MPC_PFS_WRITE_DISABLE; + dummy = MPC.PWPR.BYTE; + +} + +/*********************************************************************************************************************** + End of function R_MPC_WriteDisable +***********************************************************************************************************************/ + +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_mpc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_mpc.h new file mode 100644 index 000000000..1ebdf96ba --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_mpc.h @@ -0,0 +1,49 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_mpc.h +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : Header file of mpc file. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ +#ifndef _MPC_H +#define _MPC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_MPC_Create(void); +void R_MPC_Create_UserInit(void); + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port.c new file mode 100644 index 000000000..4c5032379 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port.c @@ -0,0 +1,69 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for Port module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_PORT_Create +* Description : This function initializes the Port I/O. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_PORT_Create(void) +{ + PORT5.PODR.BYTE = _Pm1_OUTPUT_1; + PORT6.PODR.BYTE = _Pm7_OUTPUT_1; + PORT5.PDR.WORD = _Pm1_MODE_OUTPUT | _Pm6_MODE_OUTPUT; + PORT6.PDR.WORD = _Pm7_MODE_OUTPUT; + PORT7.PDR.WORD = _Pm4_MODE_OUTPUT | _Pm6_MODE_OUTPUT | _Pm7_MODE_OUTPUT; + PORTA.PDR.WORD = _Pm0_MODE_OUTPUT; + PORTF.PDR.WORD = _Pm7_MODE_OUTPUT; + PORTM.PDR.WORD = _Pm2_MODE_OUTPUT | _Pm3_MODE_OUTPUT; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port.h new file mode 100644 index 000000000..f92e679da --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port.h @@ -0,0 +1,135 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port.h +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for Port module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ +#ifndef PORT_H +#define PORT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Port Direction Register (PDR) +*/ +/* Pmn Direction Control (B0 - B15) */ +#define _Pm0_MODE_NOT_USED (0x0000U) /* Pm0 not used (Hi-z input protection) */ +#define _Pm0_MODE_INPUT (0x0002U) /* Pm0 as input */ +#define _Pm0_MODE_OUTPUT (0x0003U) /* Pm0 as output */ +#define _Pm1_MODE_NOT_USED (0x0000U) /* Pm1 not used (Hi-z input protection) */ +#define _Pm1_MODE_INPUT (0x0008U) /* Pm1 as input */ +#define _Pm1_MODE_OUTPUT (0x000CU) /* Pm1 as output */ +#define _Pm2_MODE_NOT_USED (0x0000U) /* Pm2 not used (Hi-z input protection) */ +#define _Pm2_MODE_INPUT (0x0020U) /* Pm2 as input */ +#define _Pm2_MODE_OUTPUT (0x0030U) /* Pm2 as output */ +#define _Pm3_MODE_NOT_USED (0x0000U) /* Pm3 not used (Hi-z input protection) */ +#define _Pm3_MODE_INPUT (0x0080U) /* Pm3 as input */ +#define _Pm3_MODE_OUTPUT (0x00C0U) /* Pm3 as output */ +#define _Pm4_MODE_NOT_USED (0x0000U) /* Pm4 not used (Hi-z input protection) */ +#define _Pm4_MODE_INPUT (0x0200U) /* Pm4 as input */ +#define _Pm4_MODE_OUTPUT (0x0300U) /* Pm4 as output */ +#define _Pm5_MODE_NOT_USED (0x0000U) /* Pm5 not used (Hi-z input protection) */ +#define _Pm5_MODE_INPUT (0x0800U) /* Pm5 as input */ +#define _Pm5_MODE_OUTPUT (0x0C00U) /* Pm5 as output */ +#define _Pm6_MODE_NOT_USED (0x0000U) /* Pm6 not used (Hi-z input protection) */ +#define _Pm6_MODE_INPUT (0x2000U) /* Pm6 as input */ +#define _Pm6_MODE_OUTPUT (0x3000U) /* Pm6 as output */ +#define _Pm7_MODE_NOT_USED (0x0000U) /* Pm7 not used (Hi-z input protection) */ +#define _Pm7_MODE_INPUT (0x8000U) /* Pm7 as input */ +#define _Pm7_MODE_OUTPUT (0xC000U) /* Pm7 as output */ + +/* + Port Output Data Register (PODR) +*/ +/* Pmn Output Data Store (B0 - B7) */ +#define _Pm0_OUTPUT_0 (0x00U) /* Output low at B0 */ +#define _Pm0_OUTPUT_1 (0x01U) /* Output high at B0 */ +#define _Pm1_OUTPUT_0 (0x00U) /* Output low at B1 */ +#define _Pm1_OUTPUT_1 (0x02U) /* Output high at B1 */ +#define _Pm2_OUTPUT_0 (0x00U) /* Output low at B2 */ +#define _Pm2_OUTPUT_1 (0x04U) /* Output high at B2 */ +#define _Pm3_OUTPUT_0 (0x00U) /* Output low at B3 */ +#define _Pm3_OUTPUT_1 (0x08U) /* Output high at B3 */ +#define _Pm4_OUTPUT_0 (0x00U) /* Output low at B4 */ +#define _Pm4_OUTPUT_1 (0x10U) /* Output high at B4 */ +#define _Pm5_OUTPUT_0 (0x00U) /* Output low at B5 */ +#define _Pm5_OUTPUT_1 (0x20U) /* Output high at B5 */ +#define _Pm6_OUTPUT_0 (0x00U) /* Output low at B6 */ +#define _Pm6_OUTPUT_1 (0x40U) /* Output high at B6 */ +#define _Pm7_OUTPUT_0 (0x00U) /* Output low at B7 */ +#define _Pm7_OUTPUT_1 (0x80U) /* Output high at B7 */ + +/* + Pull-Up/Pull-Down Control Register (PCR) +*/ +/* Pmn Input Pull-Up Resistor Control (B0 - B15) */ +#define _Pm0_PULLUPDOWN_DISABLE (0x0000U) /* Pm0 pull-up resistor and pull-down resistor not connected */ +#define _Pm0_PULLUPDOWN_PULLDOWN_ON (0x0001U) /* Pm0 pull-down resistor connected */ +#define _Pm0_PULLUPDOWN_PULLUP_ON (0x0002U) /* Pm0 pull-up resistor connected */ +#define _Pm1_PULLUPDOWN_DISABLE (0x0000U) /* Pm1 pull-up resistor and pull-down resistor not connected */ +#define _Pm1_PULLUPDOWN_PULLDOWN_ON (0x0004U) /* Pm1 pull-down resistor connected */ +#define _Pm1_PULLUPDOWN_PULLUP_ON (0x0008U) /* Pm1 pull-up resistor connected */ +#define _Pm2_PULLUPDOWN_DISABLE (0x0000U) /* Pm2 pull-up resistor and pull-down resistor not connected */ +#define _Pm2_PULLUPDOWN_PULLDOWN_ON (0x0010U) /* Pm2 pull-down resistor connected */ +#define _Pm2_PULLUPDOWN_PULLUP_ON (0x0020U) /* Pm2 pull-up resistor connected */ +#define _Pm3_PULLUPDOWN_DISABLE (0x0000U) /* Pm3 pull-up resistor and pull-down resistor not connected */ +#define _Pm3_PULLUPDOWN_PULLDOWN_ON (0x0040U) /* Pm3 pull-down resistor connected */ +#define _Pm3_PULLUPDOWN_PULLUP_ON (0x0080U) /* Pm3 pull-up resistor connected */ +#define _Pm4_PULLUPDOWN_DISABLE (0x0000U) /* Pm4 pull-up resistor and pull-down resistor not connected */ +#define _Pm4_PULLUPDOWN_PULLDOWN_ON (0x0100U) /* Pm4 pull-down resistor connected */ +#define _Pm4_PULLUPDOWN_PULLUP_ON (0x0200U) /* Pm4 pull-up resistor connected */ +#define _Pm5_PULLUPDOWN_DISABLE (0x0000U) /* Pm5 pull-up resistor and pull-down resistor not connected */ +#define _Pm5_PULLUPDOWN_PULLDOWN_ON (0x0400U) /* Pm5 pull-down resistor connected */ +#define _Pm5_PULLUPDOWN_PULLUP_ON (0x0800U) /* Pm5 pull-up resistor connected */ +#define _Pm6_PULLUPDOWN_DISABLE (0x0000U) /* Pm6 pull-up resistor and pull-down resistor not connected */ +#define _Pm6_PULLUPDOWN_PULLDOWN_ON (0x1000U) /* Pm6 pull-down resistor connected */ +#define _Pm6_PULLUPDOWN_PULLUP_ON (0x2000U) /* Pm6 pull-up resistor connected */ +#define _Pm7_PULLUPDOWN_DISABLE (0x0000U) /* Pm7 pull-up resistor and pull-down resistor not connected */ +#define _Pm7_PULLUPDOWN_PULLDOWN_ON (0x4000U) /* Pm7 pull-down resistor connected */ +#define _Pm7_PULLUPDOWN_PULLUP_ON (0x8000U) /* Pm7 pull-up resistor connected */ + +/* + Drive Capacity Control Register (DSCR) +*/ +/* P10 Drive Capacity Control (B0) */ +#define _Pm0_HIDRV_OFF (0x0000U) /* P10 Normal drive output */ +#define _Pm0_HIDRV_ON (0x0001U) /* P10 High-drive output */ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_PORT_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port_user.c new file mode 100644 index 000000000..db2c2b166 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_port_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_port_user.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for Port module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_port.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi.c new file mode 100644 index 000000000..2e9325ae0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi.c @@ -0,0 +1,196 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_rspi.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for RSPI module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_rspi.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +const uint32_t * gp_rspi1_tx_address; /* RSPI1 transmit buffer address */ +uint16_t g_rspi1_tx_count; /* RSPI1 transmit data number */ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + + +/*********************************************************************************************************************** +* Function Name: R_RSPI1_Create +* Description : This function initializes the RSPI1 module. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_RSPI1_Create(void) +{ + /* Disable RSPI interrupts */ + VIC.IEC2.LONG = 0x00200000UL; /* Disable SPTI1 interrupt */ + VIC.IEC2.LONG = 0x00400000UL; /* Disable SPEI1 interrupt */ + VIC.IEC2.LONG = 0x00800000UL; /* Disable SPII1 interrupt */ + + /* Set interrupt detection type */ + VIC.PLS2.LONG |= 0x00200000UL; /* Set SPTI1 edge detection interrupt */ + + /* Cancel RSPI module stop state */ + MSTP(RSPI1) = 0U; + + /* Disable RSPI function */ + RSPI1.SPCR.BIT.SPE = 0U; + + /* Set control registers */ + RSPI1.SPPCR.BYTE = _RSPI_MOSI_LEVEL_HIGH | _RSPI_MOSI_FIXING_MOIFV_BIT | _RSPI_OUTPUT_PIN_CMOS | _RSPI_LOOPBACK_DISABLED | _RSPI_LOOPBACK2_DISABLED; + RSPI1.SPBR = _RSPI1_DIVISOR; + RSPI1.SPDCR.BYTE = _RSPI_ACCESS_LONGWORD | _RSPI_FRAMES_1; + RSPI1.SPSCR.BYTE = _RSPI_SEQUENCE_LENGTH_1; + RSPI1.SSLP.BYTE = _RSPI_SSL0_POLARITY_LOW | _RSPI_SSL1_POLARITY_LOW; + RSPI1.SPCKD.BYTE = _RSPI_RSPCK_DELAY_1; + RSPI1.SSLND.BYTE = _RSPI_SSL_NEGATION_DELAY_1; + RSPI1.SPND.BYTE = _RSPI_NEXT_ACCESS_DELAY_1; + RSPI1.SPCR2.BYTE = _RSPI_PARITY_DISABLE; + RSPI1.SPCMD0.WORD = _RSPI_RSPCK_SAMPLING_EVEN | _RSPI_RSPCK_POLARITY_HIGH | _RSPI_BASE_BITRATE_1 | + _RSPI_SIGNAL_ASSERT_SSL0 | _RSPI_SSL_KEEP_DISABLE | _RSPI_DATA_LENGTH_BITS_8 | + _RSPI_MSB_FIRST | _RSPI_NEXT_ACCESS_DELAY_DISABLE | _RSPI_NEGATION_DELAY_DISABLE | + _RSPI_RSPCK_DELAY_DISABLE; + + /* Set SPTI1 priority level */ + VIC.PRL85.LONG = _RSPI_PRIORITY_LEVEL6; + + /* Set SPEI1 priority level */ + VIC.PRL86.LONG = _RSPI_PRIORITY_LEVEL5; + + /* Set SPII1 priority level */ + VIC.PRL87.LONG = _RSPI_PRIORITY_LEVEL7; + + /* Set SPTI1 interrupt address */ + VIC.VAD85.LONG = (uint32_t)r_rspi1_transmit_interrupt; + + /* Set SPEI1 interrupt address */ + VIC.VAD86.LONG = (uint32_t)r_rspi1_error_interrupt; + + /* Set SPII1 interrupt address */ + VIC.VAD87.LONG = (uint32_t)r_rspi1_idle_interrupt; + + RSPI1.SPCR.BYTE = _RSPI_MODE_SPI | _RSPI_TRANSMIT_ONLY | _RSPI_MASTER_MODE; +} + +/*********************************************************************************************************************** +* Function Name: R_RSPI1_Start +* Description : This function starts the RSPI1 module operation. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_RSPI1_Start(void) +{ + volatile uint8_t dummy; + + /* Enable RSPI interrupts */ + VIC.IEN2.LONG |= 0x00200000UL; /* Enable SPTI1 interrupt */ + VIC.IEN2.LONG |= 0x00400000UL; /* Enable SPEI1 interrupt */ + VIC.IEN2.LONG |= 0x00800000UL; /* Enable SPII1 interrupt */ + + /* Clear error sources */ + dummy = RSPI1.SPSR.BYTE; + ( void ) dummy; + RSPI1.SPSR.BYTE = 0x00U; + + /* Disable idle interrupt */ + RSPI1.SPCR2.BIT.SPIIE = 0U; +} + +/*********************************************************************************************************************** +* Function Name: R_RSPI1_Stop +* Description : This function stops the RSPI1 module operation. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_RSPI1_Stop(void) +{ + /* Disable RSPI interrupts */ + VIC.IEC2.LONG = 0x00200000UL; /* Disable SPTI1 interrupt */ + VIC.IEC2.LONG = 0x00400000UL; /* Disable SPEI1 interrupt */ + VIC.IEC2.LONG = 0x00800000UL; /* Disable SPII1 interrupt */ + + /* Disable RSPI function */ + RSPI1.SPCR.BIT.SPE = 0U; +} +/*********************************************************************************************************************** +* Function Name: R_RSPI1_Send +* Description : This function sends RSPI1 data. +* Arguments : tx_buf - +* transfer buffer pointer (not used when data is handled by DMAC) +* tx_num - +* buffer size +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_RSPI1_Send(const uint32_t * tx_buf, uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + if (tx_num < 1U) + { + status = MD_ARGERROR; + } + else + { + gp_rspi1_tx_address = tx_buf; + g_rspi1_tx_count = tx_num; + + /* Enable transmit interrupt */ + RSPI1.SPCR.BIT.SPTIE = 1U; + + /* Enable error interrupt */ + RSPI1.SPCR.BIT.SPEIE = 1U; + + /* Enable idle interrupt */ + RSPI1.SPCR2.BIT.SPIIE = 1U; + + /* Enable RSPI function */ + RSPI1.SPCR.BIT.SPE = 1U; + } + + return (status); +} + + + + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi.h new file mode 100644 index 000000000..e5c4b24a1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi.h @@ -0,0 +1,274 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_rspi.h +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for RSPI module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ +#ifndef RSPI_H +#define RSPI_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + RSPI Control Register (SPCR) +*/ +/* RSPI Mode Select (SPMS) */ +#define _RSPI_MODE_SPI (0x00U) /* SPI operation (four-wire method) */ +#define _RSPI_MODE_CLOCK_SYNCHRONOUS (0x01U) /* Clock synchronous operation (three-wire method) */ +/* Communications Operating Mode Select (TXMD) */ +#define _RSPI_FULL_DUPLEX_SYNCHRONOUS (0x00U) /* Full-duplex synchronous serial communications */ +#define _RSPI_TRANSMIT_ONLY (0x02U) /* Serial communications with transmit only operations */ +/* Mode Fault Error Detection Enable (MODFEN) */ +#define _RSPI_MODE_FAULT_DETECT_DISABLED (0x00U) /* Disables the detection of mode fault error */ +#define _RSPI_MODE_FAULT_DETECT_ENABLED (0x04U) /* Enables the detection of mode fault error */ +/* RSPI Master/Slave Mode Select (MSTR) */ +#define _RSPI_SLAVE_MODE (0x00U) /* Slave mode */ +#define _RSPI_MASTER_MODE (0x08U) /* Master mode */ +/* RSPI Error Interrupt Enable (SPEIE) */ +#define _RSPI_ERROR_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI error interrupt */ +#define _RSPI_ERROR_INTERRUPT_ENABLED (0x10U) /* Enables the generation of RSPI error interrupt */ +/* RSPI Transmit Interrupt Enable (SPTIE) */ +#define _RSPI_TRANSMIT_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI transmit interrupt */ +#define _RSPI_TRANSMIT_INTERRUPT_ENABLED (0x20U) /* Enables the generation of RSPI transmit interrupt */ +/* RSPI Function Enable (SPE) */ +#define _RSPI_FUNCTION_DISABLED (0x00U) /* Disables the RSPI function */ +#define _RSPI_FUNCTION_ENABLED (0x40U) /* Enables the RSPI function */ +/* RSPI Receive Interrupt Enable (SPRIE) */ +#define _RSPI_RECEIVE_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI receive interrupt */ +#define _RSPI_RECEIVE_INTERRUPT_ENABLED (0x80U) /* Enables the generation of RSPI receive interrupt */ + +/* + RSPI Slave Select Polarity Register (SSLP) +*/ +/* SSL0 Signal Polarity Setting (SSL0P) */ +#define _RSPI_SSL0_POLARITY_LOW (0x00U) /* SSL0 signal is active low */ +#define _RSPI_SSL0_POLARITY_HIGH (0x01U) /* SSL0 signal is active high */ +/* SSL1 Signal Polarity Setting (SSL1P) */ +#define _RSPI_SSL1_POLARITY_LOW (0x00U) /* SSL1 signal is active low */ +#define _RSPI_SSL1_POLARITY_HIGH (0x02U) /* SSL1 signal is active high */ +/* SSL2 Signal Polarity Setting (SSL2P) */ +#define _RSPI_SSL2_POLARITY_LOW (0x00U) /* SSL2 signal is active low */ +#define _RSPI_SSL2_POLARITY_HIGH (0x04U) /* SSL2 signal is active high */ +/* SSL3 Signal Polarity Setting (SSL3P) */ +#define _RSPI_SSL3_POLARITY_LOW (0x00U) /* SSL3 signal is active low */ +#define _RSPI_SSL3_POLARITY_HIGH (0x08U) /* SSL3 signal is active high */ + +/* + RSPI Pin Control Register (SPPCR) +*/ +/* RSPI Loopback (SPLP) */ +#define _RSPI_LOOPBACK_DISABLED (0x00U) /* Normal mode */ +#define _RSPI_LOOPBACK_ENABLED (0x01U) /* Loopback mode (reversed transmit data = receive data) */ +/* RSPI Loopback 2 (SPLP2) */ +#define _RSPI_LOOPBACK2_DISABLED (0x00U) /* Normal mode */ +#define _RSPI_LOOPBACK2_ENABLED (0x02U) /* Loopback mode (transmit data = receive data) */ +/* Output pin mode (SPOM) */ +#define _RSPI_OUTPUT_PIN_CMOS (0x00U) /* CMOS output */ +#define _RSPI_OUTPUT_PIN_OPEN_DRAIN (0x04U) /* Open-drain output */ +/* MOSI Idle Fixed Value (MOIFV) */ +#define _RSPI_MOSI_LEVEL_LOW (0x00U) /* Level output on MOSIA during idling corresponds to low */ +#define _RSPI_MOSI_LEVEL_HIGH (0x10U) /* Level output on MOSIA during idling corresponds to high */ +/* MOSI Idle Value Fixing Enable (MOIFE) */ +#define _RSPI_MOSI_FIXING_PREV_TRANSFER (0x00U) /* MOSI output value equals final data from previous transfer */ +#define _RSPI_MOSI_FIXING_MOIFV_BIT (0x20U) /* MOSI output value equals the value set in the MOIFV bit */ + +/* + RSPI Sequence Control Register (SPSCR) +*/ +/* RSPI Sequence Length Specification (SPSLN[2:0]) */ +#define _RSPI_SEQUENCE_LENGTH_1 (0x00U) /* 0 -> 0... */ +#define _RSPI_SEQUENCE_LENGTH_2 (0x01U) /* 0 -> 1 -> 0... */ +#define _RSPI_SEQUENCE_LENGTH_3 (0x02U) /* 0 -> 1 -> 2 -> 0... */ +#define _RSPI_SEQUENCE_LENGTH_4 (0x03U) /* 0 -> 1 -> 2 -> 3 -> 0... */ +#define _RSPI_SEQUENCE_LENGTH_5 (0x04U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 0... */ +#define _RSPI_SEQUENCE_LENGTH_6 (0x05U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 0... */ +#define _RSPI_SEQUENCE_LENGTH_7 (0x06U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 0... */ +#define _RSPI_SEQUENCE_LENGTH_8 (0x07U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 7 -> 0... */ + +/* + RSPI Data Control Register (SPDCR) +*/ +/* Number of Frames Specification (SPFC[1:0]) */ +#define _RSPI_FRAMES_1 (0x00U) /* 1 frame */ +#define _RSPI_FRAMES_2 (0x01U) /* 2 frames */ +#define _RSPI_FRAMES_3 (0x02U) /* 3 frames */ +#define _RSPI_FRAMES_4 (0x03U) /* 4 frames */ +/* RSPI Receive/Transmit Data Selection (SPRDTD) */ +#define _RSPI_READ_SPDR_RX_BUFFER (0x00U) /* read SPDR values from receive buffer */ +#define _RSPI_READ_SPDR_TX_BUFFER (0x10U) /* read SPDR values from transmit buffer (transmit buffer empty) */ +/* RSPI Longword Access/Word Access Specification (SPLW) */ +#define _RSPI_ACCESS_WORD (0x00U) /* SPDR is accessed in words */ +#define _RSPI_ACCESS_LONGWORD (0x20U) /* SPDR is accessed in longwords */ + +/* + RSPI Clock Delay Register (SPCKD) +*/ +/* RSPCK Delay Setting (SCKDL[2:0]) */ +#define _RSPI_RSPCK_DELAY_1 (0x00U) /* 1 RSPCK */ +#define _RSPI_RSPCK_DELAY_2 (0x01U) /* 2 RSPCK */ +#define _RSPI_RSPCK_DELAY_3 (0x02U) /* 3 RSPCK */ +#define _RSPI_RSPCK_DELAY_4 (0x03U) /* 4 RSPCK */ +#define _RSPI_RSPCK_DELAY_5 (0x04U) /* 5 RSPCK */ +#define _RSPI_RSPCK_DELAY_6 (0x05U) /* 6 RSPCK */ +#define _RSPI_RSPCK_DELAY_7 (0x06U) /* 7 RSPCK */ +#define _RSPI_RSPCK_DELAY_8 (0x07U) /* 8 RSPCK */ + +/* + RSPI Slave Select Negation Delay Register (SSLND) +*/ +/* SSL Negation Delay Setting (SLNDL[2:0]) */ +#define _RSPI_SSL_NEGATION_DELAY_1 (0x00U) /* 1 RSPCK */ +#define _RSPI_SSL_NEGATION_DELAY_2 (0x01U) /* 2 RSPCK */ +#define _RSPI_SSL_NEGATION_DELAY_3 (0x02U) /* 3 RSPCK */ +#define _RSPI_SSL_NEGATION_DELAY_4 (0x03U) /* 4 RSPCK */ +#define _RSPI_SSL_NEGATION_DELAY_5 (0x04U) /* 5 RSPCK */ +#define _RSPI_SSL_NEGATION_DELAY_6 (0x05U) /* 6 RSPCK */ +#define _RSPI_SSL_NEGATION_DELAY_7 (0x06U) /* 7 RSPCK */ +#define _RSPI_SSL_NEGATION_DELAY_8 (0x07U) /* 8 RSPCK */ + +/* + RSPI Next-Access Delay Register (SPND) +*/ +/* RSPI Next-Access Delay Setting (SPNDL[2:0]) */ +#define _RSPI_NEXT_ACCESS_DELAY_1 (0x00U) /* 1 RSPCK + 2 SERICLK */ +#define _RSPI_NEXT_ACCESS_DELAY_2 (0x01U) /* 2 RSPCK + 2 SERICLK */ +#define _RSPI_NEXT_ACCESS_DELAY_3 (0x02U) /* 3 RSPCK + 2 SERICLK */ +#define _RSPI_NEXT_ACCESS_DELAY_4 (0x03U) /* 4 RSPCK + 2 SERICLK */ +#define _RSPI_NEXT_ACCESS_DELAY_5 (0x04U) /* 5 RSPCK + 2 SERICLK */ +#define _RSPI_NEXT_ACCESS_DELAY_6 (0x05U) /* 6 RSPCK + 2 SERICLK */ +#define _RSPI_NEXT_ACCESS_DELAY_7 (0x06U) /* 7 RSPCK + 2 SERICLK */ +#define _RSPI_NEXT_ACCESS_DELAY_8 (0x07U) /* 8 RSPCK + 2 SERICLK */ + +/* + RSPI Control Register 2 (SPCR2) +*/ +/* Parity Enable (SPPE) */ +#define _RSPI_PARITY_DISABLE (0x00U) /* Does not add parity bit to transmit data */ +#define _RSPI_PARITY_ENABLE (0x01U) /* Adds the parity bit to transmit data */ +/* Parity Mode (SPOE) */ +#define _RSPI_PARITY_EVEN (0x00U) /* Selects even parity for use in transmission and reception */ +#define _RSPI_PARITY_ODD (0x02U) /* Selects odd parity for use in transmission and reception */ +/* RSPI Idle Interrupt Enable (SPIIE) */ +#define _RSPI_IDLE_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI idle interrupt */ +#define _RSPI_IDLE_INTERRUPT_ENABLED (0x04U) /* Enables the generation of RSPI idle interrupt */ +/* Parity Self-Testing (PTE) */ +#define _RSPI_SELF_TEST_DISABLED (0x00U) /* Disables the self-diagnosis function of the parity circuit */ +#define _RSPI_SELF_TEST_ENABLED (0x08U) /* Enables the self-diagnosis function of the parity circuit */ +/* RSPCK Auto-Stop Function Enable (SCKASE) */ +#define _RSPI_AUTO_STOP_DISABLED (0x00U) /* Disables the RSPCK auto-stop function */ +#define _RSPI_AUTO_STOP_ENABLED (0x10U) /* Enables the RSPCK auto-stop function */ + +/* + RSPI Command Registers 0 to 7 (SPCMD0 to SPCMD7) +*/ +/* RSPCK Phase Setting (CPHA) */ +#define _RSPI_RSPCK_SAMPLING_ODD (0x0000U) /* Data sampling on odd edge, data variation on even edge */ +#define _RSPI_RSPCK_SAMPLING_EVEN (0x0001U) /* Data variation on odd edge, data sampling on even edge */ +/* RSPCK Polarity Setting (CPOL) */ +#define _RSPI_RSPCK_POLARITY_LOW (0x0000U) /* RSPCK is low when idle */ +#define _RSPI_RSPCK_POLARITY_HIGH (0x0002U) /* RSPCK is high when idle */ +/* Bit Rate Division Setting (BRDV[1:0]) */ +#define _RSPI_BASE_BITRATE_1 (0x0000U) /* These bits select the base bit rate */ +#define _RSPI_BASE_BITRATE_2 (0x0004U) /* These bits select the base bit rate divided by 2 */ +#define _RSPI_BASE_BITRATE_4 (0x0008U) /* These bits select the base bit rate divided by 4 */ +#define _RSPI_BASE_BITRATE_8 (0x000CU) /* These bits select the base bit rate divided by 8 */ +/* SSL Signal Assertion Setting (SSLA[2:0]) */ +#define _RSPI_SIGNAL_ASSERT_SSL0 (0x0000U) /* SSL0 */ +#define _RSPI_SIGNAL_ASSERT_SSL1 (0x0010U) /* SSL1 */ +#define _RSPI_SIGNAL_ASSERT_SSL2 (0x0020U) /* SSL2 */ +#define _RSPI_SIGNAL_ASSERT_SSL3 (0x0030U) /* SSL3 */ +/* SSL Signal Level Keeping (SSLKP) */ +#define _RSPI_SSL_KEEP_DISABLE (0x0000U) /* Negates all SSL signals upon completion of transfer */ +#define _RSPI_SSL_KEEP_ENABLE (0x0080U) /* Keep SSL level from end of transfer till next access */ +/* RSPI Data Length Setting (SPB[3:0]) */ +#define _RSPI_DATA_LENGTH_BITS_8 (0x0400U) /* 8 bits */ +#define _RSPI_DATA_LENGTH_BITS_9 (0x0800U) /* 9 bits */ +#define _RSPI_DATA_LENGTH_BITS_10 (0x0900U) /* 10 bits */ +#define _RSPI_DATA_LENGTH_BITS_11 (0x0A00U) /* 11 bits */ +#define _RSPI_DATA_LENGTH_BITS_12 (0x0B00U) /* 12 bits */ +#define _RSPI_DATA_LENGTH_BITS_13 (0x0C00U) /* 13 bits */ +#define _RSPI_DATA_LENGTH_BITS_14 (0x0D00U) /* 14 bits */ +#define _RSPI_DATA_LENGTH_BITS_15 (0x0E00U) /* 15 bits */ +#define _RSPI_DATA_LENGTH_BITS_16 (0x0F00U) /* 16 bits */ +#define _RSPI_DATA_LENGTH_BITS_20 (0x0000U) /* 20 bits */ +#define _RSPI_DATA_LENGTH_BITS_24 (0x0100U) /* 24 bits */ +#define _RSPI_DATA_LENGTH_BITS_32 (0x0200U) /* 32 bits */ +/* RSPI LSB First (LSBF) */ +#define _RSPI_MSB_FIRST (0x0000U) /* MSB first */ +#define _RSPI_LSB_FIRST (0x1000U) /* LSB first */ +/* RSPI Next-Access Delay Enable (SPNDEN) */ +#define _RSPI_NEXT_ACCESS_DELAY_DISABLE (0x0000U) /* Next-access delay of 1 RSPCK + 2 SERICLK */ +#define _RSPI_NEXT_ACCESS_DELAY_ENABLE (0x2000U) /* Next-access delay equal to setting of SPND register */ +/* SSL Negation Delay Setting Enable (SLNDEN) */ +#define _RSPI_NEGATION_DELAY_DISABLE (0x0000U) /* SSL negation delay of 1 RSPCK */ +#define _RSPI_NEGATION_DELAY_ENABLE (0x4000U) /* SSL negation delay equal to setting of SSLND register */ +/* RSPCK Delay Setting Enable (SCKDEN) */ +#define _RSPI_RSPCK_DELAY_DISABLE (0x0000U) /* RSPCK delay of 1 RSPCK */ +#define _RSPI_RSPCK_DELAY_ENABLE (0x8000U) /* RSPCK delay equal to setting of the SPCKD register */ + +/* + Interrupt Priority Level Store Register n (PRLn) +*/ +/* Interrupt Priority Level Store (PRL[3:0]) */ +#define _RSPI_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */ +#define _RSPI_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */ +#define _RSPI_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */ +#define _RSPI_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */ +#define _RSPI_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */ +#define _RSPI_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */ +#define _RSPI_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */ +#define _RSPI_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */ +#define _RSPI_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */ +#define _RSPI_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */ +#define _RSPI_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */ +#define _RSPI_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */ +#define _RSPI_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */ +#define _RSPI_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */ +#define _RSPI_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */ +#define _RSPI_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#define _RSPI1_DIVISOR (0x4AU) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_RSPI1_Create(void); +void R_RSPI1_Start(void); +void R_RSPI1_Stop(void); +MD_STATUS R_RSPI1_Send(const uint32_t * tx_buf, uint16_t tx_num); +void r_rspi1_callback_transmitend(void); +void r_rspi1_callback_error(uint8_t err_type); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi_user.c new file mode 100644 index 000000000..9f8c97390 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_rspi_user.c @@ -0,0 +1,197 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_rspi_user.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for RSPI module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_rspi.h" +/* Start user code for include. Do not edit comment generated here */ +#include "r_typedefs.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +extern const uint32_t * gp_rspi1_tx_address; /* RSPI1 transmit buffer address */ +extern uint16_t g_rspi1_tx_count; /* RSPI1 transmit data number */ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_rspi1_transmit_interrupt +* Description : This function is SPTI1 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#ifdef __ICCARM__ + __irq __arm +#endif /* __ICCARM__ */ +void r_rspi1_transmit_interrupt(void) +{ + uint16_t frame_cnt; + + /* Clear the interrupt source */ + VIC.PIC2.LONG = 0x00200000UL; + + for (frame_cnt = 0U; frame_cnt < (_RSPI_FRAMES_1 + 1U); frame_cnt++) + { + if (g_rspi1_tx_count > 0U) + { + /* Write data for transmission */ + RSPI1.SPDR.LONG = (*(uint32_t*)gp_rspi1_tx_address); + gp_rspi1_tx_address++; + g_rspi1_tx_count--; + } + else + { + /* Disable transmit interrupt */ + RSPI1.SPCR.BIT.SPTIE = 0U; + + /* Enable idle interrupt */ + RSPI1.SPCR2.BIT.SPIIE = 1U; + break; + } + } + + /* Dummy write */ + VIC.HVA0.LONG = 0x00000000UL; +} +/*********************************************************************************************************************** +* Function Name: r_rspi1_error_interrupt +* Description : This function is SPEI1 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#ifdef __ICCARM__ + __irq __arm +#endif /* __ICCARM__ */ +void r_rspi1_error_interrupt(void) +{ + uint8_t err_type; + + /* Disable RSPI function */ + RSPI1.SPCR.BIT.SPE = 0U; + + /* Disable transmit interrupt */ + RSPI1.SPCR.BIT.SPTIE = 0U; + + /* Disable error interrupt */ + RSPI1.SPCR.BIT.SPEIE = 0U; + + /* Disable idle interrupt */ + RSPI1.SPCR2.BIT.SPIIE = 0U; + + /* Clear error sources */ + err_type = RSPI1.SPSR.BYTE; + RSPI1.SPSR.BYTE = 0xA0U; + + if (err_type != 0U) + { + r_rspi1_callback_error(err_type); + } + /* Wait the interrupt signal is disabled */ + while (0U != (VIC.IRQS2.LONG & 0x00400000UL)) + { + VIC.IEC2.LONG = 0x00400000UL; + } + + VIC.IEN2.LONG |= 0x00400000UL; + + /* Dummy write */ + VIC.HVA0.LONG = 0x00000000UL; +} +/*********************************************************************************************************************** +* Function Name: r_rspi1_idle_interrupt +* Description : This function is SPII1 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#ifdef __ICCARM__ + __irq __arm +#endif /* __ICCARM__ */ +void r_rspi1_idle_interrupt(void) +{ + /* Disable RSPI function */ + RSPI1.SPCR.BIT.SPE = 0U; + + /* Disable idle interrupt */ + RSPI1.SPCR2.BIT.SPIIE = 0U; + + r_rspi1_callback_transmitend(); + + /* Wait the interrupt signal is disabled */ + while (0U != (VIC.IRQS2.LONG & 0x00800000UL)) + { + VIC.IEC2.LONG = 0x00800000UL; + } + + VIC.IEN2.LONG |= 0x00800000UL; + + /* Dummy write */ + VIC.HVA0.LONG = 0x00000000UL; +} +/*********************************************************************************************************************** +* Function Name: r_rspi1_callback_transmitend +* Description : This function is a callback function when RSPI1 finishes transmission. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_rspi1_callback_transmitend(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + + +/*********************************************************************************************************************** +* Function Name: r_rspi1_callback_error +* Description : This function is a callback function when RSPI1 error occurs. +* Arguments : err_type - +* error type value +* Return Value : None +***********************************************************************************************************************/ +void r_rspi1_callback_error(uint8_t err_type) +{ + /* Start user code. Do not edit comment generated here */ + + /* Used to suppress the warning message generated for unused variables */ + UNUSED_VARIABLE(err_type); + + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_systeminit.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_systeminit.c new file mode 100644 index 000000000..996abb8bb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_systeminit.c @@ -0,0 +1,95 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_systeminit.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements system initializing function. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +#include "r_cg_icu.h" +#include "r_cg_port.h" +#include "r_cg_tpu.h" +#include "r_cg_rspi.h" +#include "r_cg_mpc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ + +void R_Systeminit(void); + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every macro. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_Systeminit(void) +{ + DI(); + + /* Enable writing to registers related to operating modes, LPC, CGC and ATCM */ + SYSTEM.PRCR.LONG = 0x0000A50BU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + r_set_exception_handler(); + + /* Set peripheral settings */ + R_CGC_Create(); + R_ICU_Create(); + R_PORT_Create(); + R_TPU_Create(); + R_RSPI1_Create(); + R_MPC_Create(); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.LONG = 0x0000A500U; + EI(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu.c new file mode 100644 index 000000000..77af3eafb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu.c @@ -0,0 +1,98 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_tpu.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for TPU module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_tpu.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_TPU_Create +* Description : This function initializes the TPU Unit0 module. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TPU_Create(void) +{ + /* Cancel TPU stop state in LPC */ + MSTP(TPU1) = 0U; + + /* Stop all channels */ + TPUA.TSTRB.BYTE = 0x00U; + + /* Channel 9 is used as normal mode */ + TPU9.TCR.BYTE = _TPU_PCLKD_4096 | _TPU_CKEG_IT_R | _TPU_CKCL_DIS; + TPU9.TIER.BYTE |= _TPU_TGIEA_DISABLE | _TPU_TGIEB_DISABLE | _TPU_TGIEC_DISABLE | _TPU_TGIED_DISABLE | + _TPU_TCIEV_DISABLE | _TPU_TTGE_DISABLE; + TPU9.TIORH.BYTE = _TPU_IOB_IR | _TPU_IOA_DISABLE; + TPU9.TIORL.BYTE = _TPU_IOD_IR | _TPU_IOC_IR; + TPU9.TGRA = _TPU9_TCNTA_VALUE; + TPU9.TMDR.BYTE = _TPU_NORMAL | _TPU_BFA_NORMAL | _TPU_BFB_NORMAL | _TPU_ICSELB_BPIN | _TPU_ICSELD_DPIN; + + /* Internal PWM feedback function status */ + TPUSL.PWMFBSLR.LONG = _TPU_TPU0EN_DISABLE | _TPU_TPU1EN_DISABLE; +} +/*********************************************************************************************************************** +* Function Name: R_TPU9_Start +* Description : This function starts TPU channel 9 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TPU9_Start(void) +{ + TPUA.TSTRB.BIT.CST3 = 1U; +} +/*********************************************************************************************************************** +* Function Name: R_TPU9_Stop +* Description : This function stops TPU channel 9 counter. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_TPU9_Stop(void) +{ + TPUA.TSTRB.BIT.CST3 = 0U; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu.h new file mode 100644 index 000000000..46b9ae450 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu.h @@ -0,0 +1,328 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_tpu.h +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for TPU module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ +#ifndef TPU_H +#define TPU_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + Timer Control Register (TCR) +*/ +/* Time Prescaler Select (TPSC[2:0]) */ +#define _TPU_PCLKD_1 (0x00U) /* Internal clock: counts on PCLKD/1 */ +#define _TPU_PCLKD_4 (0x01U) /* Internal clock: counts on PCLKD/4 */ +#define _TPU_PCLKD_16 (0x02U) /* Internal clock: counts on PCLKD/16 */ +#define _TPU_PCLKD_64 (0x03U) /* Internal clock: counts on PCLKD/64 */ +#define _TPU_PCLKD_256 (0x06U) /* Internal clock: counts on PCLKD/256 */ +#define _TPU2_PCLKD_1024 (0x07U) /* TPU2 Internal clock: counts on PCLKD/1024 */ +#define _TPU3_PCLKD_1024 (0x05U) /* TPU3 Internal clock: counts on PCLKD/1024 */ +#define _TPU4_PCLKD_1024 (0x06U) /* TPU4 Internal clock: counts on PCLKD/1024 */ +#define _TPU8_PCLKD_1024 (0x07U) /* TPU8 Internal clock: counts on PCLKD/1024 */ +#define _TPU9_PCLKD_1024 (0x05U) /* TPU9 Internal clock: counts on PCLKD/1024 */ +#define _TPU10_PCLKD_1024 (0x06U) /* TPU10 Internal clock: counts on PCLKD/1024 */ +#define _TPU_PCLKD_4096 (0x07U) /* Internal clock: counts on PCLKD/4096 */ +#define _TPU_TCLKA (0x04U) /* External clock: counts on TCLKA pin input */ +#define _TPU_TCLKB (0x05U) /* External clock: counts on TCLKB pin input */ +#define _TPU_TCLKC_06 (0x06U) /* External clock: counts on TCLKC pin input */ +#define _TPU_TCLKC_05 (0x05U) /* External clock: counts on TCLKC pin input */ +#define _TPU_TCLKD (0x07U) /* External clock: counts on TCLKD pin input */ +#define _TPU_TCLKE (0x04U) /* External clock: counts on TCLKE pin input */ +#define _TPU_TCLKF (0x05U) /* External clock: counts on TCLKF pin input */ +#define _TPU_TCLKG_06 (0x06U) /* External clock: counts on TCLKG pin input */ +#define _TPU_TCLKG_05 (0x05U) /* External clock: counts on TCLKG pin input */ +#define _TPU_TCLKH (0x07U) /* External clock: counts on TCLKH pin input */ +#define _TPU2_COUNT (0x07U) /* TPU1: Counts on TPU2.TCNT counter overflow/underflow */ +#define _TPU5_COUNT (0x07U) /* TPU4: Counts on TPU5.TCNT counter overflow/underflow */ +#define _TPU8_COUNT (0x07U) /* TPU7: Counts on TPU8.TCNT counter overflow/underflow */ +#define _TPU11_COUNT (0x07U) /* TPU10: Counts on TPU11.TCNT counter overflow/underflow */ +/* Clock Edge Select (CKEG[1:0]) */ +#define _TPU_CKEG_IT_F (0x00U) /* Internal Clock: Count at falling edge */ +#define _TPU_CKEG_EX_R (0x00U) /* External Clock: Count at rising edge */ +#define _TPU_CKEG_IT_R (0x08U) /* Internal Clock: Count at rising edge */ +#define _TPU_CKEG_EX_F (0x08U) /* External Clock: Count at falling edge */ +#define _TPU_CKEG_BOTH (0x10U) /* Count at both edge */ +/* Counter Clear Select (CCLR[2:0]) */ +#define _TPU_CKCL_DIS (0x00U) /* TCNT clearing disabled */ +#define _TPU_CKCL_A (0x20U) /* TCNT cleared by TGRA compare match/input capture */ +#define _TPU_CKCL_B (0x40U) /* TCNT cleared by TGRB compare match/input capture */ +#define _TPU_CKCL_SYN (0x60U) /* TCNT cleared by counter clearing in another synchronous channel */ +#define _TPU_CKCL_C (0xA0U) /* TCNT cleared by TGRC compare match/input capture */ +#define _TPU_CKCL_D (0xC0U) /* TCNT cleared by TGRD compare match/input capture */ + +/* + Timer Mode Register (TMDR) +*/ +/* Mode Select (MD[3:0]) */ +#define _TPU_NORMAL (0x00U) /* Normal mode */ +#define _TPU_PWM1 (0x02U) /* PWM mode 1 */ +#define _TPU_PWM2 (0x03U) /* PWM mode 2 */ +#define _TPU_COT1 (0x04U) /* Phase counting mode 1 */ +#define _TPU_COT2 (0x05U) /* Phase counting mode 2 */ +#define _TPU_COT3 (0x06U) /* Phase counting mode 3 */ +#define _TPU_COT4 (0x07U) /* Phase counting mode 4 */ +/* Buffer Operation A (BFA) */ +#define _TPU_BFA_NORMAL (0x00U) /* TPUm.TGRA operates normally (m = 0, 3, 6, 9) */ +#define _TPU_BFA_BUFFER (0x10U) /* TPUm.TGRA and TPUm.TGRC used together for buffer operation */ +/* Buffer Operation B (BFB) */ +#define _TPU_BFB_NORMAL (0x00U) /* TPUm.TGRB operates normally (m = 0, 3, 6, 9) */ +#define _TPU_BFB_BUFFER (0x20U) /* TPUm.TGRB and TPUm.TGRD used together for buffer operation */ +/* TGRB Input Capture Input Select (ICSELB) */ +#define _TPU_ICSELB_BPIN (0x00U) /* Input capture input source is TIOCBn pin */ +#define _TPU_ICSELB_APIN (0x40U) /* Input capture input source is TIOCAn pin (n = 0 to 11) */ +/* TGRD Input Capture Input Select (ICSELD) */ +#define _TPU_ICSELD_DPIN (0x00U) /* Input capture input source is TIOCDn pin */ +#define _TPU_ICSELD_CPIN (0x80U) /* Input capture input source is TIOCCn pin (n = 0, 3, 6, 9) */ + +/* + Timer I/O Control Register (TIOR) +*/ +/* I/O Control A (IOA[3:0]) for TPU0.TIORH, TPU1.TIOR, TPU2.TIOR, TPU3.TIORH, TPU4.TIORH, TPU5.TIOR + TPU6.TIORH, TPU7.TIOR, TPU8.TIOR, TPU9.TIORH, TPU10.TIOR, TPU11.TIOR*/ +#define _TPU_IOA_DISABLE (0x00U) /* Output prohibited */ +#define _TPU_IOA_LL (0x01U) /* Initial output is low. Low output at compare match */ +#define _TPU_IOA_LH (0x02U) /* Initial output is low. High output at compare match */ +#define _TPU_IOA_LT (0x03U) /* Initial output is low. Toggle output at compare match */ +#define _TPU_IOA_HL (0x05U) /* Initial output is high. Low output at compare match */ +#define _TPU_IOA_HH (0x06U) /* Initial output is high. High output at compare match */ +#define _TPU_IOA_HT (0x07U) /* Initial output is high. Toggle output at compare match */ +#define _TPU_IOA_IR (0x08U) /* Input capture at rising edge. */ +#define _TPU_IOA_IF (0x09U) /* Input capture at falling edge */ +#define _TPU_IOA_IB (0x0AU) /* Input capture at both edges */ +#define _TPU_IOA_EX (0x0CU) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count + or TPU7.TCNT or TPU10.TCNT up-count/down-count */ +#define _TPU_IOA_TGRA (0x0DU) /* Input capture at TPU0.TGRA or TPU3.TGRA compare match/input capture + or TPU6.TGRA or TPU9.TGRA compare match/input capture */ +/* I/O Control B (IOB[3:0]) for TPU0.TIORH, TPU1.TIOR, TPU2.TIOR, TPU3.TIORH, TPU4.TIORH, TPU5.TIOR + TPU6.TIORH, TPU7.TIOR, TPU8.TIOR, TPU9.TIORH, TPU10.TIOR, TPU11.TIOR*/ +#define _TPU_IOB_DISABLE (0x00U) /* Output prohibited */ +#define _TPU_IOB_LL (0x10U) /* Initial output is low. Low output at compare match */ +#define _TPU_IOB_LH (0x20U) /* Initial output is low. High output at compare match */ +#define _TPU_IOB_LT (0x30U) /* Initial output is low. Toggle output at compare match */ +#define _TPU_IOB_HL (0x50U) /* Initial output is high. Low output at compare match */ +#define _TPU_IOB_HH (0x60U) /* Initial output is high. High output at compare match */ +#define _TPU_IOB_HT (0x70U) /* Initial output is high. Toggle output at compare match */ +#define _TPU_IOB_IR (0x80U) /* Input capture at rising edge */ +#define _TPU_IOB_IF (0x90U) /* Input capture at falling edge */ +#define _TPU_IOB_IB (0xA0U) /* Input capture at both edges. */ +#define _TPU_IOB_EX (0xC0U) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count + or TPU7.TCNT or TPU10.TCNT up-count/down-count*/ +#define _TPU_IOB_TGRC (0xD0U) /* Input capture at TPU0.TGRC or TPU3.TGRC compare match/input capture + or TPU6.TGRC or TPU9.TGRC compare match/input capture*/ +/* I/O Control C (IOC[3:0]) for TPU0.TIORL, TPU3.TIORL, TPU6.TIORL, TPU9.TIORL */ +#define _TPU_IOC_DISABLE (0x00U) /* Output prohibited */ +#define _TPU_IOC_LL (0x01U) /* Initial output is low. Low output at compare match */ +#define _TPU_IOC_LH (0x02U) /* Initial output is low. High output at compare match */ +#define _TPU_IOC_LT (0x03U) /* Initial output is low. Toggle output at compare match */ +#define _TPU_IOC_HL (0x05U) /* Initial output is high. Low output at compare match. */ +#define _TPU_IOC_HH (0x06U) /* Initial output is high. High output at compare match. */ +#define _TPU_IOC_HT (0x07U) /* Initial output is high. Toggle output at compare match. */ +#define _TPU_IOC_IR (0x08U) /* Input capture at rising edge. */ +#define _TPU_IOC_IF (0x09U) /* Input capture at falling edge. */ +#define _TPU_IOC_IB (0x0AU) /* Input capture at both edges. */ +#define _TPU_IOC_EX (0x0CU) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count + or TPU7.TCNT or TPU10.TCNT up-count/down-count. */ +/* I/O Control D (IOD[3:0]) for TPU0.TIORL, TPU3.TIORL, TPU6.TIORL, TPU9.TIOR */ +#define _TPU_IOD_DISABLE (0x00U) /* Output prohibited */ +#define _TPU_IOD_LL (0x10U) /* Initial output is low. Low output at compare match */ +#define _TPU_IOD_LH (0x20U) /* Initial output is low. High output at compare match */ +#define _TPU_IOD_LT (0x30U) /* Initial output is low. Toggle output at compare match */ +#define _TPU_IOD_HL (0x50U) /* Initial output is high. Low output at compare match. */ +#define _TPU_IOD_HH (0x60U) /* Initial output is high. High output at compare match. */ +#define _TPU_IOD_HT (0x70U) /* Initial output is high. Toggle output at compare match. */ +#define _TPU_IOD_IR (0x80U) /* Input capture at rising edge. */ +#define _TPU_IOD_IF (0x90U) /* Input capture at falling edge. */ +#define _TPU_IOD_IB (0xA0U) /* Input capture at both edges. */ +#define _TPU_IOD_EX (0xC0U) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count + or TPU7.TCNT or TPU10.TCNT up-count/down-count. */ + +/* + Timer Start Registers (TSTRA) +*/ +/* Counter Start 0 (CST0) */ +#define _TPU_CST0_OFF (0x00U) /* TPU0.TCNT performs count stop */ +#define _TPU_CST0_ON (0x01U) /* TPU0.TCNT performs count operation */ +/* Counter Start 1 (CST1) */ +#define _TPU_CST1_OFF (0x00U) /* TPU1.TCNT performs count stop */ +#define _TPU_CST1_ON (0x02U) /* TPU1.TCNT performs count operation */ +/* Counter Start 2 (CST2) */ +#define _TPU_CST2_OFF (0x00U) /* TPU3.TCNT performs count stop */ +#define _TPU_CST2_ON (0x04U) /* TPU3.TCNT performs count operation */ +/* Counter Start 3 (CST3) */ +#define _TPU_CST3_OFF (0x00U) /* TPU3.TCNT performs count stop */ +#define _TPU_CST3_ON (0x08U) /* TPU3.TCNT performs count operation */ +/* Counter Start 4 (CST4) */ +#define _TPU_CST4_OFF (0x00U) /* TPU4.TCNT performs count stop */ +#define _TPU_CST4_ON (0x10U) /* TPU4.TCNT performs count operation */ +/* Counter Start 5 (CST5) */ +#define _TPU_CST5_OFF (0x00U) /* TPU5.TCNT performs count stop */ +#define _TPU_CST5_ON (0x20U) /* TPU5.TCNT performs count operation */ + +/* + Timer Start Registers (TSTRB) +*/ +/* Counter Start 6 (CST0) */ +#define _TPU_CST6_OFF (0x00U) /* TPU6.TCNT performs count stop */ +#define _TPU_CST6_ON (0x01U) /* TPU6.TCNT performs count operation */ +/* Counter Start 7 (CST1) */ +#define _TPU_CST7_OFF (0x00U) /* TPU7.TCNT performs count stop */ +#define _TPU_CST7_ON (0x02U) /* TPU7.TCNT performs count operation */ +/* Counter Start 8 (CST2) */ +#define _TPU_CST8_OFF (0x00U) /* TPU8.TCNT performs count stop */ +#define _TPU_CST8_ON (0x04U) /* TPU8.TCNT performs count operation */ +/* Counter Start 9 (CST3) */ +#define _TPU_CST9_OFF (0x00U) /* TPU9.TCNT performs count stop */ +#define _TPU_CST9_ON (0x08U) /* TPU9.TCNT performs count operation */ +/* Counter Start 10 (CST4) */ +#define _TPU_CST10_OFF (0x00U) /* TPU10.TCNT performs count stop */ +#define _TPU_CST10_ON (0x10U) /* TPU10.TCNT performs count operation */ +/* Counter Start 11 (CST5) */ +#define _TPU_CST11_OFF (0x00U) /* TPU11.TCNT performs count stop */ +#define _TPU_CST11_ON (0x20U) /* TPU11.TCNT performs count operation */ + +/* + Noise Filter Control Register (NFCR) +*/ +/* Noise Filter A Enable Bit (NFAEN) */ +#define _TPU_NFAEN_DISABLE (0x00U) /* The noise filter for the TIOCAm pin is disabled */ +#define _TPU_NFAEN_ENABLE (0x01U) /* The noise filter for the TIOCAm pin is enabled */ +/* Noise Filter B Enable Bit (NFBEN) */ +#define _TPU_NFBEN_DISABLE (0x00U) /* The noise filter for the TIOCBm pin is disabled */ +#define _TPU_NFBEN_ENABLE (0x02U) /* The noise filter for the TIOCBm pin is enabled */ +/* Noise Filter C Enable Bit (NFCEN) */ +#define _TPU_NFCEN_DISABLE (0x00U) /* The noise filter for the TIOCCm pin is disabled */ +#define _TPU_NFCEN_ENABLE (0x04U) /* The noise filter for the TIOCCm pin is enabled */ +/* Noise Filter D Enable Bit (NFDEN) */ +#define _TPU_NFDEN_DISABLE (0x00U) /* The noise filter for the TIOCDm pin is disabled */ +#define _TPU_NFDEN_ENABLE (0x08U) /* The noise filter for the TIOCDm pin is enabled */ +/* Noise Filter Clock Select (NFCS[1:0]) */ +#define _TPU_NFCS_PCLKD_1 (0x00U) /* PCLKD/1 */ +#define _TPU_NFCS_PCLKD_8 (0x10U) /* PCLKD/8 */ +#define _TPU_NFCS_PCLKD_32 (0x20U) /* PCLKD/32 */ +#define _TPU_NFCS_EXCLK (0x30U) /* The clock source for counting is the external clock */ + +/* + PWM Feedback Select Register (PWMFBSLR) +*/ +/* TPU (Unit 0) Internal PWM Feedback Enable (TPU0EN)*/ +#define _TPU_TPU0EN_DISABLE (0x00000000UL) /* Internal PWM feedback input function unit 0 is disabled */ +#define _TPU_TPU0EN_ENABLE (0x00000001UL) /* Internal PWM feedback input function unit 0 is enabled */ +/* Internal PWM Feedback Input Source Select 0 (FBSL0[2:0]) */ +#define _TPU0_PWM_SIG_MTU34 (0x00000010UL) /* PWM output signals of MTU3 and MTU4 */ +#define _TPU0_PWM_SIG_MTU67 (0x00000014UL) /* PWM output signals of MTU6 and MTU7 */ +#define _TPU0_PWM_SIG_GPT02 (0x00000018UL) /* PWM output signals of GPT0 to GPT2 */ +/* TPU (Unit 1) Internal PWM Feedback Enable (TPU1EN)*/ +#define _TPU_TPU1EN_DISABLE (0x00000000UL) /* Internal PWM feedback input function unit 1 is disabled */ +#define _TPU_TPU1EN_ENABLE (0x00000100UL) /* Internal PWM feedback input function unit 1 is enabled */ +/* Internal PWM Feedback Input Source Select 1 (FBSL1[2:0]) */ +#define _TPU1_PWM_SIG_MTU34 (0x00001000UL) /* PWM output signals of MTU3 and MTU4 */ +#define _TPU1_PWM_SIG_MTU67 (0x00001400UL) /* PWM output signals of MTU6 and MTU7 */ +#define _TPU1_PWM_SIG_GPT02 (0x00001800UL) /* PWM output signals of GPT0 to GPT2 */ +/* + Timer Interrupt Enable Register (TIER) +*/ +/* TGR Interrupt Enable A (TGIEA) */ +#define _TPU_TGIEA_DISABLE (0x00U) /* Interrupt requests TGIA disabled */ +#define _TPU_TGIEA_ENABLE (0x01U) /* Interrupt requests TGIA enabled */ +/* TGR Interrupt Enable B (TGIEB) */ +#define _TPU_TGIEB_DISABLE (0x00U) /* Interrupt requests TGIB disabled */ +#define _TPU_TGIEB_ENABLE (0x02U) /* Interrupt requests TGIB enabled */ +/* TGR Interrupt Enable C (TGIEC) */ +#define _TPU_TGIEC_DISABLE (0x00U) /* Interrupt requests TGIC disabled */ +#define _TPU_TGIEC_ENABLE (0x04U) /* Interrupt requests TGIC enabled */ +/* TGR Interrupt Enable D (TGIED) */ +#define _TPU_TGIED_DISABLE (0x00U) /* Interrupt requests TGID disabled */ +#define _TPU_TGIED_ENABLE (0x08U) /* Interrupt requests TGID enabled */ +/* Overflow Interrupt Enable (TCIEV) */ +#define _TPU_TCIEV_DISABLE (0x00U) /* Interrupt requests TCIV disabled */ +#define _TPU_TCIEV_ENABLE (0x10U) /* Interrupt requests TCIV enabled */ +/* Underflow Interrupt Enable (TCIEU) */ +#define _TPU_TCIEU_DISABLE (0x00U) /* Interrupt requests TCIU disabled */ +#define _TPU_TCIEU_ENABLE (0x20U) /* Interrupt requests TCIU enabled */ +/* A/D Converter Start Request Enable (TTGE) */ +#define _TPU_TTGE_DISABLE (0x00U) /* A/D converter start request generation disabled */ +#define _TPU_TTGE_ENABLE (0x80U) /* A/D converter start request generation enabled */ + +/* + Interrupt Source Priority Register n (PRLn) +*/ +/* Interrupt Priority Level Select (PRL[3:0]) */ +#define _TPU_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */ +#define _TPU_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */ +#define _TPU_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */ +#define _TPU_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */ +#define _TPU_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */ +#define _TPU_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */ +#define _TPU_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */ +#define _TPU_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */ +#define _TPU_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */ +#define _TPU_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */ +#define _TPU_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */ +#define _TPU_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */ +#define _TPU_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */ +#define _TPU_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */ +#define _TPU_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */ +#define _TPU_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */ +#define _TPU_PRIORITY_LEVEL16 (0x00000000UL) /* Level 16 */ +#define _TPU_PRIORITY_LEVEL17 (0x00000001UL) /* Level 17 */ +#define _TPU_PRIORITY_LEVEL18 (0x00000002UL) /* Level 18 */ +#define _TPU_PRIORITY_LEVEL19 (0x00000003UL) /* Level 19 */ +#define _TPU_PRIORITY_LEVEL20 (0x00000004UL) /* Level 20 */ +#define _TPU_PRIORITY_LEVEL21 (0x00000005UL) /* Level 21 */ +#define _TPU_PRIORITY_LEVEL22 (0x00000006UL) /* Level 22 */ +#define _TPU_PRIORITY_LEVEL23 (0x00000007UL) /* Level 23 */ +#define _TPU_PRIORITY_LEVEL24 (0x00000008UL) /* Level 24 */ +#define _TPU_PRIORITY_LEVEL25 (0x00000009UL) /* Level 25 */ +#define _TPU_PRIORITY_LEVEL26 (0x0000000AUL) /* Level 26 */ +#define _TPU_PRIORITY_LEVEL27 (0x0000000BUL) /* Level 27 */ +#define _TPU_PRIORITY_LEVEL28 (0x0000000CUL) /* Level 28 */ +#define _TPU_PRIORITY_LEVEL29 (0x0000000DUL) /* Level 29 */ +#define _TPU_PRIORITY_LEVEL30 (0x0000000EUL) /* Level 30 */ +#define _TPU_PRIORITY_LEVEL31 (0x0000000FUL) /* Level 31 (lowest) */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +/* TGRA value channel 9 */ +#define _TPU9_TCNTA_VALUE (0x0726U) + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_TPU_Create(void); +void R_TPU9_Start(void); +void R_TPU9_Stop(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu_user.c new file mode 100644 index 000000000..8d1fc9a89 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_tpu_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_tpu_user.c +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file implements device driver for TPU module. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_tpu.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_userdefine.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_userdefine.h new file mode 100644 index 000000000..2db8e0c19 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/cg_src/r_cg_userdefine.h @@ -0,0 +1,72 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] +* Device(s) : R7S910018CBG +* Tool-Chain : GCCARM +* Description : This file includes user definition. +* Creation Date: 22/04/2015 +***********************************************************************************************************************/ +#ifndef _USER_DEF_H +#define _USER_DEF_H + +/*********************************************************************************************************************** +User definitions +***********************************************************************************************************************/ + +/* Start user code for function. Do not edit comment generated here */ + +#define MPC_PFSWE_WRITE_ENABLE (0x00) +#define MPC_PFS_WRITE_ENABLE (0x40) +#define MPC_PFS_WRITE_DISABLE (0x80) + +#define MPC_IRQ_DISABLE (0) +#define MPC_IRQ_ENABLE (1) + +/* Define LED states */ +#define LED_ON (1U) +#define LED_OFF (0U) + +/* Define user LEDs mode register pins */ +#define LED0_MODE (PORTF.PMR.BIT.B7) +#define LED1_MODE (PORT5.PMR.BIT.B6) +#define LED2_MODE (PORT7.PMR.BIT.B7) +#define LED3_MODE (PORTA.PMR.BIT.B0) + +/* Define user LEDs direction's pins */ +#define LED0_DIR (PORTF.PDR.BIT.B7) +#define LED1_DIR (PORT5.PDR.BIT.B6) +#define LED2_DIR (PORT7.PDR.BIT.B7) +#define LED3_DIR (PORTA.PDR.BIT.B0) + +/* Define user LEDs */ +#define LED0 (PORTF.PODR.BIT.B7) +#define LED1 (PORT5.PODR.BIT.B6) +#define LED2 (PORT7.PODR.BIT.B7) +#define LED3 (PORTA.PODR.BIT.B0) + +void R_MPC_WriteEnable (void); +void R_MPC_WriteDisable (void); + +extern void r_set_exception_handler(void); + +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/main.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/main.c new file mode 100644 index 000000000..730e617a5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR/src/main.c @@ -0,0 +1,253 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup, standard FreeRTOS hook functions, and the ISR hander called + * by the RTOS after interrupt entry (including nesting) has been taken care of. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Standard includes. */ +#include "string.h" + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Renesas includes. */ +#include "r_cg_macrodriver.h" +#include "r_cg_icu.h" +#include "r_cg_rspi.h" +#include "r_system.h" +#include "r_reset.h" +#include "r_cg_userdefine.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ + +/* + * The GCC start up code does not include a routine to clear the BSS segment to + * 0 (as would be normal before calling main()), so the BSS is cleared manually + * using the following function. + */ +static void prvClearBSS( void ); + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/* Prototype for the IRQ handler called by the generic Cortex-A5 RTOS port +layer. */ +void vApplicationIRQHandler( void ); + +/* Library initialisation. */ +extern void R_Systeminit( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* The start up code does not include a routine to clear the BSS segment to + 0 (as would be normal before calling main()), so the BSS is cleared manually + using the following function. */ + prvClearBSS(); + + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + R_Systeminit(); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +static void prvClearBSS( void ) +{ +#ifdef __GNUC__ + /* The GCC start up files seem to be missing code to clear the BSS, so it + is done manually here. */ + extern uint32_t __bss_start__[]; + extern uint32_t __bss_end__[]; + size_t xSize; + + /* Zero out bss. */ + xSize = ( ( size_t ) __bss_end__ ) - ( ( size_t ) __bss_start__ ); + memset( ( void * ) __bss_start__, 0x00, xSize ); +#endif /* __GNUC__ */ +} + + + diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.HardwareDebuglinker b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.HardwareDebuglinker deleted file mode 100644 index b9aca814d..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.HardwareDebuglinker +++ /dev/null @@ -1,146 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.Releaselinker b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.Releaselinker deleted file mode 100644 index da6f60055..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.Releaselinker +++ /dev/null @@ -1,89 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject deleted file mode 100644 index b6ac7fa6a..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject +++ /dev/null @@ -1,166 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.info b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.info deleted file mode 100644 index 88f4c78c5..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.info +++ /dev/null @@ -1,7 +0,0 @@ -TOOL_CHAIN=KPIT GNUARM-NONE-EABI Toolchain -VERSION=v14.02 -TC_INSTALL=C:\Program Files (x86)\KPIT\GNUARM-NONEv14.02-EABI\arm-none-eabi\arm-none-eabi\ -GCC_STRING=4.9-GNUARM-NONE_v14.02 -VERSION_IDE= -E2STUDIO_VERSION=4.0.2.008 -ACTIVE_CONFIGURATION=HardwareDebug diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.project b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.project deleted file mode 100644 index 46213b545..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.project +++ /dev/null @@ -1,232 +0,0 @@ - - - RTOSDemo - - - - - - com.renesas.cdt.core.genmakebuilder - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - 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5 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-flop.c - - - - 1441019347088 - src/Full_Demo/Standard_Demo_Tasks - 5 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-TimerDemo.c - - - - 1441019347098 - src/Full_Demo/Standard_Demo_Tasks - 5 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-QueueOverwrite.c - - - - 1441019347098 - src/Full_Demo/Standard_Demo_Tasks - 5 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-EventGroupsDemo.c - - - - 1441019347108 - src/Full_Demo/Standard_Demo_Tasks - 5 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-TaskNotify.c - - - - 1441019347108 - src/Full_Demo/Standard_Demo_Tasks - 5 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-IntSemTest.c - - - - 1441019347118 - src/Full_Demo/Standard_Demo_Tasks - 5 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-death.c - - - - 1440591394340 - src/FreeRTOS_Source/portable/GCC - 9 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-ARM_CRx_No_GIC - - - - 1440591376868 - src/FreeRTOS_Source/portable/MemMang - 5 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-false-false-heap_4.c - - - - - - FREERTOS_ROOT - $%7BPARENT-3-PROJECT_LOC%7D - - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.settings/Dependency_Scan_Preferences.prefs b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.settings/Dependency_Scan_Preferences.prefs deleted file mode 100644 index c52c797ff..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.settings/Dependency_Scan_Preferences.prefs +++ /dev/null @@ -1,4 +0,0 @@ -Build\ project\ excluding\ the\ dependencies=false -Re-generate\ and\ use\ dependencies\ during\ project\ build=true -Use\ existing\ dependencies\ during\ project\ build=false -eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.settings/Project_Generation_Prefrences.prefs b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.settings/Project_Generation_Prefrences.prefs deleted file mode 100644 index b6b9d5c8d..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.settings/Project_Generation_Prefrences.prefs +++ /dev/null @@ -1,36 +0,0 @@ -com.renesas.cdt.core.Assembler.option.includeFileDirectories="${workspace_loc\:/${ProjName}}/src"; -com.renesas.cdt.core.LibraryGenerator.option.ctype=false -com.renesas.cdt.core.LibraryGenerator.option.libraryType=Project-Built -com.renesas.cdt.core.LibraryGenerator.option.math=false -com.renesas.cdt.core.LibraryGenerator.option.selectLibrary=Optimized -com.renesas.cdt.core.LibraryGenerator.option.stdio=true -com.renesas.cdt.core.LibraryGenerator.option.stdlib=true -com.renesas.cdt.core.LibraryGenerator.option.string=true -com.renesas.cdt.core.Linker.option.userDefinedOptions=; -com.renesas.cdt.rz.HardwareDebug.Assembler.option.architecture=armv7-r -com.renesas.cdt.rz.HardwareDebug.Assembler.option.cpuType=cortex-r4f -com.renesas.cdt.rz.HardwareDebug.Compiler.option.architecture=armv7-r -com.renesas.cdt.rz.HardwareDebug.Compiler.option.cpuType=cortex-r4f -com.renesas.cdt.rz.HardwareDebug.Compiler.option.cpuType.585789719=cortex-r4f -com.renesas.cdt.rz.HardwareDebug.Compiler.option.dataEndian=Little-endian -com.renesas.cdt.rz.HardwareDebug.Compiler.option.floatingpointabi=Soft -com.renesas.cdt.rz.HardwareDebug.Compiler.option.instructionset=ARM -com.renesas.cdt.rz.HardwareDebug.Compiler.option.interworking=true -com.renesas.cdt.rz.HardwareDebug.Compiler.option.macroDefines= -com.renesas.cdt.rz.HardwareDebug.Compiler.option.targetfpu=vfp -com.renesas.cdt.rz.HardwareDebug.Linker.option.archiveLibraryFiles=${BuildArtifactFileBaseName};gcc; -com.renesas.cdt.rz.HardwareDebug.Linker.option.archiveSearchDirectories.1574512948="${TCINSTALL}/lib/gcc/arm-none-eabi/${GCC_VERSION}/fpu/interwork";"${TCINSTALL}/arm-none-eabi/lib/fpu/interwork"; -com.renesas.cdt.rz.Release.Assembler.option.architecture=armv7-r -com.renesas.cdt.rz.Release.Assembler.option.cpuType=cortex-r4f -com.renesas.cdt.rz.Release.Compiler.option.architecture=armv7-r -com.renesas.cdt.rz.Release.Compiler.option.cpuType=cortex-r4f -com.renesas.cdt.rz.Release.Compiler.option.cpuType.963183599=cortex-r4f -com.renesas.cdt.rz.Release.Compiler.option.dataEndian=Little-endian -com.renesas.cdt.rz.Release.Compiler.option.floatingpointabi=Soft -com.renesas.cdt.rz.Release.Compiler.option.instructionset=ARM -com.renesas.cdt.rz.Release.Compiler.option.interworking=true -com.renesas.cdt.rz.Release.Compiler.option.macroDefines= -com.renesas.cdt.rz.Release.Compiler.option.targetfpu=vfp -com.renesas.cdt.rz.Release.Linker.option.archiveLibraryFiles=${BuildArtifactFileBaseName};gcc; -com.renesas.cdt.rz.Release.Linker.option.archiveSearchDirectories.966751407="${TCINSTALL}/lib/gcc/arm-none-eabi/${GCC_VERSION}/interwork";"${TCINSTALL}/arm-none-eabi/lib/interwork"; -eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.settings/language.settings.xml b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.settings/language.settings.xml deleted file mode 100644 index 546c39b1e..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.settings/language.settings.xml +++ /dev/null @@ -1,13 +0,0 @@ - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/RTOSDemo HardwareDebug.jlink b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/RTOSDemo HardwareDebug.jlink deleted file mode 100644 index 1ca0b4000..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/RTOSDemo HardwareDebug.jlink +++ /dev/null @@ -1,35 +0,0 @@ -[BREAKPOINTS] -ForceImpTypeAny = 0 -ShowInfoWin = 1 -EnableFlashBP = 2 -BPDuringExecution = 0 -[CFI] -CFISize = 0x00 -CFIAddr = 0x00 -[CPU] -OverrideMemMap = 0 -AllowSimulation = 1 -ScriptFile="" -[FLASH] -CacheExcludeSize = 0x00 -CacheExcludeAddr = 0x00 -MinNumBytesFlashDL = 0 -SkipProgOnCRCMatch = 1 -VerifyDownload = 1 -AllowCaching = 1 -EnableFlashDL = 2 -Override = 0 -Device="UNSPECIFIED" -[GENERAL] -WorkRAMSize = 0x00 -WorkRAMAddr = 0x00 -RAMUsageLimit = 0x00 -[SWO] -SWOLogFile="" -[MEM] -RdOverrideOrMask = 0x00 -RdOverrideAndMask = 0xFFFFFFFF -RdOverrideAddr = 0xFFFFFFFF -WrOverrideOrMask = 0x00 -WrOverrideAndMask = 0xFFFFFFFF -WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/GNU_LINKER_ATCM.ld b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/GNU_LINKER_ATCM.ld deleted file mode 100644 index 1ec9c36d4..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/GNU_LINKER_ATCM.ld +++ /dev/null @@ -1,215 +0,0 @@ -/**************************************************************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -****************************************************************************************************************************************************************/ -/*********************************************************************************************************************** -* File Name : GNU_LINKER_ATCM.ld -* Device(s) : RZ/T1 (R7S910018) -* Tool-Chain : GNUARM-NONEv14.02-EABI -* H/W Platform : RSK+RZT1 CPU Board -* Description : Linker file for projects that require to load and run from RAM (ATCM) -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 -***********************************************************************************************************************/ -OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(start) - -/* Base Address RAM Memory Table 1 Mbyte on-chip RAM */ -MEMORY -{ - /* Internal RAM address range H'2000_0000 to H'2001_FFFF is configured as data retention RAM */ - /* Write access to this address range has to be enabled by writing to registers SYSCR1 and SYSCR2 */ - ATCM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* (512KB) H'00000000 to H'0007FFFF */ - BTCM (rwx) : ORIGIN = 0x00800000, LENGTH = 0x00800000 /* (32KB) H'00800000 to H'00807FFF */ - BUFFER_RAM (rwx) : ORIGIN = 0x20200000, LENGTH = 0x00100000 /* (1024KB) H'08000000 to H'0FFFFFFF */ - DATA_RAM0 (rwx) : ORIGIN = 0x24000000, LENGTH = 0x00080000 /* (512KB) H'22000000 to H'2207FFFF */ - DATA_RAM1 (rwx) : ORIGIN = 0x22000000, LENGTH = 0x00080000 /* (512KB) H'24000000 to H'2407FFFF */ - - SPIBSC (rw) : ORIGIN = 0x30000000, LENGTH = 0x04000000 /* attached to H'30000000 to H'33FFFFFF */ - CS0 (rw) : ORIGIN = 0x40000000, LENGTH = 0x04000000 /* attached to H'40000000 to H'43FFFFFF */ - CS1 (rw) : ORIGIN = 0x44000000, LENGTH = 0x04000000 /* attached to H'44000000 to H'47FFFFFF */ - CS2 (rw) : ORIGIN = 0x48000000, LENGTH = 0x04000000 /* attached to H'40000000 to H'4CFFFFFF */ - CS3 (rw) : ORIGIN = 0x4C000000, LENGTH = 0x04000000 /* attached to H'4C000000 to H'4FFFFFFF */ - CS4 (rw) : ORIGIN = 0x50000000, LENGTH = 0x04000000 /* attached to H'50000000 to H'53FFFFFF */ - CS5 (rw) : ORIGIN = 0x54000000, LENGTH = 0x04000000 /* attached to H'54000000 to H'57FFFFFF */ - - /* Mapped memory type */ - SPI_ROM (rw) : ORIGIN = 0x30000000, LENGTH = 0x04000000 - CS0_ROM (rw) : ORIGIN = 0x40000000, LENGTH = 0x04000000 - CS1_ROM (rw) : ORIGIN = 0x44000000, LENGTH = 0x04000000 - SDRAM0_EXT (rw) : ORIGIN = 0x48000000, LENGTH = 0x04000000 - SDRAM1_EXT (rw) : ORIGIN = 0x4C000000, LENGTH = 0x04000000 -} - -SYS_STACK_SIZE = 0x200; /* Application stack size */ -SVC_STACK_SIZE = 0x200; /* SVC mode stack */ -IRQ_STACK_SIZE = 0x200; /* IRQ mode stack */ -FIQ_STACK_SIZE = 0x200; /* FRQ mode stack */ -UND_STACK_SIZE = 0x200; /* SVC mode stack */ -ABT_STACK_SIZE = 0x200; /* ABT mode stack */ -HEAP_STACK_SIZE = 0x1000; /* Heap stack size */ - -ATCM_BASE = 0x00000000; /* User application located here */ -BTCM_BASE = 0x00800000; /* BTCM base address */ - -USER_EXEC_BASE = 0x00000000; /* Application loads and runs from here */ - -USER_RAM = 0x20000000; /* Application's RAM base */ - -STACK_BASE = 0x00807800; /* Stacks located in BTCM */ - -SDRAM0_BASE = 0x48000000; /* SDRAM1 is attached to CS2 space */ -SDRAM1_BASE = 0x4C000000; /* SDRAM1 is attached to CS3 space */ - -SECTIONS -{ - .reset USER_EXEC_BASE : - { - reset_start = .; - execute = .; - _intvec_start = .; - *start.o (.text); - . = ALIGN(0x4); - _intvec_end = .; - end_reset = .; - } > ATCM - - .text : - { - text_start = .; - *(.text) - *(.text.startup) - text_end = .; - } > ATCM - - .rodata : - { - _rodata_start = .; - *(.rodata) - *(.rodata.*) - . = ALIGN(0x8); - _start_data_ROM = .; - *(.data) - *(.data.*) - _end_data_ROM = .; - *(.got.plt) - *(.got) - . = ALIGN(0x8); - _rodata_end = .; - PROVIDE(end = .); - } > ATCM - - _ram_data_size = (_end_data_ROM - _start_data_ROM); - - .data USER_RAM : - { - _data_start = .; - _start_data_RAM = .; - . += _ram_data_size; - _data_end = .; - } - - .bss _data_end : - { - _bss = .; - PROVIDE(__bss_start__ = .); - *(.bss) - *(.bss.**) - *(COMMON) - . = ALIGN(0x4); - PROVIDE(__bss_end__ = .); - _ebss = .; - _end = .; - PROVIDE(end = .); - } - - .heap : - { - heap_start = .; - . = ALIGN(0x8); - *(.heap_stack) - . += HEAP_STACK_SIZE; - heap_end = .; - } > ATCM - - .sys_stack STACK_BASE : - { - sys_stack_start = .; - . = ALIGN(0x8); - *(.sys_stack) - . += SYS_STACK_SIZE; - sys_stack_end = .; - } > BTCM - - .svc_stack sys_stack_end : - { - svc_stack_start = .; - . = ALIGN(0x8); - *(.svc_stack) - . += SVC_STACK_SIZE; - svc_stack_end = .; - } > BTCM - - .irq_stack svc_stack_end : - { - irq_stack_start = .; - . = ALIGN(0x8); - *(.irq_stack) - . += IRQ_STACK_SIZE; - irq_stack_end = .; - } > BTCM - - .fiq_stack irq_stack_end : - { - fiq_stack_start = .; - . = ALIGN(0x8); - *(.fiq_stack) - . += FIQ_STACK_SIZE; - fiq_stack_end = .; - } > BTCM - - .und_stack fiq_stack_end : - { - und_stack_start = .; - . = ALIGN(0x8); - *(.und_stack) - . += UND_STACK_SIZE; - und_stack_end = .; - } > BTCM - - .abt_stack und_stack_end : - { - abt_stack_start = .; - . = ALIGN(0x8); - *(.abt_stack) - . += ABT_STACK_SIZE; - abt_stack_end = .; - } > BTCM - - /* NOLOAD directs linker NOT to fill VRAMx_SECTION with 0. */ - /* Usage of NOLOAD increases speed of linker and download to target */ - .sdram0_section SDRAM0_BASE (NOLOAD) : {} > SDRAM0_EXT - .sdram1_section SDRAM1_BASE (NOLOAD) : {} > SDRAM1_EXT -} \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/loader_init.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/loader_init.asm deleted file mode 100644 index 3d1265b21..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/loader_init.asm +++ /dev/null @@ -1,351 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* System Name : RZ/T1 Init program -* File Name : loader_init.asm -* Version : 0.1 -* Device : R7S910018 -* Abstract : Loader program 1 -* Tool-Chain : GNUARM-NONEv14.02-EABI -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1 -* Description : System low level configuration. -* Limitation : none -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.04.2015 1.00 First Release -***********************************************************************************************************************/ - - .text - .code 32 - - .global reset_handler - .global loader_init1 - .global set_low_vec - .global cache_init - .global mpu_init - .global loader_init2 - .global r_icu_nmi_interrupt - - - reset_handler: - -/*********************************************************************************************************************** -* Function Name : loader_init1 -* Description : Initialize system by loader program -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -loader_init1: - -/* ========================================================================= */ -/* Multi-core startup (future proofing boot code) */ -/* Check core, if not core 0 put to sleep. */ -/* ========================================================================= */ - mrc p15, 0, r0, c0, c0, 5 /* Read MPIDR */ - ands r0, r0, #3 -goToSleep: - wfine - bne goToSleep - - mrs r0, cpsr /* Disalbe FIQ and IRQ */ - orr r0, r0, #0x000000C0 - msr cpsr, r0 - isb - -stack_init: - /* Stack setting */ - cps #17 /* FIQ mode */ - ldr sp, =fiq_stack_end - cps #18 /* IRQ mode */ - ldr sp, =irq_stack_end - cps #23 /* Abort mode */ - ldr sp, =abt_stack_end - cps #27 /* Undef mode */ - ldr sp, =und_stack_end - cps #31 /* System mode */ - ldr sp, =sys_stack_end - cps #19 /* SVC mode */ - ldr sp, =svc_stack_end - -vfp_init: - /* Initialize VFP setting */ - mrc p15, #0, r0, c1, c0, #2 /* Enables cp10 and cp11 accessing */ - orr r0, r0, #0xF00000 - mcr p15, #0, r0, c1, c0, #2 - isb /* Ensuring Context-changing */ - - mov r0, #0x40000000 /* Enables VFP operation */ - vmsr fpexc, r0 - - mrc p15, 0, r0, c1, c0, 0 /* Set SCTLR.VE bit to 1 (Use VIC) */ - orr r0, r0, #0x01000000 - mcr p15, 0, r0, c1, c0, 0 - isb /* Ensuring Context-changing */ - - mrc p15, 0, r0, c1, c0, 1 /* Enalbe ECC */ - orr r0, r0, #0x06000000 - mcr p15, 0, r0, c1, c0, 1 - isb /* Ensuring Context-changing */ - - mrs r0, cpsr /* Re-enalbe FIQ */ - and r0, r0, #0xFFFFFFBF - msr cpsr, r0 - isb - - /* Jump to loader_init2 */ -jump_loader_init2: - ldr r0, =loader_init2 - bx r0 - -/*********************************************************************************************************************** -* Function Name : cache_init -* Description : Initialize I1, D1 cache and MPU settings -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* Macro definitions -***********************************************************************************************************************/ - -.equ SCTLR_BR, 0x00020000 -.equ SCTLR_M, 0x00000001 -.equ SCTLR_I_C, 0x00001004 - -.equ DRBAR_REGION_0, 0x04000000 /*Base address = 0400_0000h */ -.equ DRACR_REGION_0, 0x0000030C /*R/W(full), Normal, Non-cache, share */ -.equ DRSR_REGION_0, 0x00000025 /*Size 512KB, MPU enable */ - -.equ DRBAR_REGION_1, 0x10000000 /*Base address = 1000_0000h */ -.equ DRACR_REGION_1, 0x0000030C /*R/W(full), Normal, Non-cache, share */ -.equ DRSR_REGION_1, 0x00000033 /*Size 64MB, MPU enable */ - -.equ DRBAR_REGION_2, 0x20000000 /*Base address = 2000_0000h */ -.equ DRACR_REGION_2, 0x0000030C /*R/W(full), Normal, Non-cache, share */ -.equ DRSR_REGION_2, 0x00000025 /*Size 512KB, MPU enable */ - -.equ DRBAR_REGION_3, 0x22000000 /*Base address = 2200_0000h */ -.equ DRACR_REGION_3, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */ -.equ DRSR_REGION_3, 0x00000033 /*Size 64MB, MPU enable */ - -.equ DRBAR_REGION_4, 0x30000000 /*Base address = 3000_0000h */ -.equ DRACR_REGION_4, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */ -.equ DRSR_REGION_4, 0x00000033 /*Size 64MB, MPU enable */ - -.equ DRBAR_REGION_5, 0x40000000 /*Base address = 4000_0000h */ -.equ DRACR_REGION_5, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */ -.equ DRSR_REGION_5, 0x00000035 /*Size 128MB, MPU enable */ - -.equ DRBAR_REGION_6, 0x48000000 /*Base address = 4800_0000h */ -.equ DRACR_REGION_6, 0x00000307 /*R/W(full), Normal, Write-back no allocate, share */ -.equ DRSR_REGION_6, 0x00000035 /*Size 128MB, MPU enable */ - -.equ DRBAR_REGION_7, 0x50000000 /*Base address = 5000_0000h */ -.equ DRACR_REGION_7, 0x00001305 /*R/W(full), XN, Device, share */ -.equ DRSR_REGION_7, 0x00000035 /*Size 128MB, MPU enable */ - -.equ DRBAR_REGION_8, 0x60000000 /*Base address = 6000_0000h */ -.equ DRACR_REGION_8, 0x0000030C /*R/W(full), Normal, Non-cache, share */ -.equ DRSR_REGION_8, 0x00000035 /*Size 128MB, MPU enable */ - -.equ DRBAR_REGION_9, 0x68000000 /*Base address = 6800_0000h */ -.equ DRACR_REGION_9, 0x0000030C /*R/W(full), Normal, Non-cache, share */ -.equ DRSR_REGION_9, 0x00000035 /*Size 128MB, MPU enable */ - -.equ DRBAR_REGION_10, 0x70000000 /*Base address = 7000_0000h */ -.equ DRACR_REGION_10, 0x00001305 /*R/W(full), XN, Device, share */ -.equ DRSR_REGION_10, 0x00000035 /*Size 128MB, MPU enable */ - -.equ DRBAR_REGION_11, 0x80000000 /*Base address = 8000_0000h */ -.equ DRACR_REGION_11, 0x00001305 /*R/W(full), XN, Device, share */ -.equ DRSR_REGION_11, 0x0000003D /*Size 2GB, MPU enable */ - -cache_init: - push {lr} - -cache_invalidate: - /*Invalidate the I1, D1 cache */ - mov r0, #0 - mcr p15, #0, r0, c7, c5, #0 /*Invalidate all Instruction Caches (Write-value is Ignored) */ - isb /*Ensuring Context-changing */ - mcr p15, #0, r0, c15, c5, #0 /*Invalidate all Data Caches (Write-value is Ignored) */ - isb /*Ensuring Context-changing */ - - /*Adopt default memory map as background map. */ - ldr r0, =SCTLR_BR /*Set SCTLR.BR bit to 1 */ - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, r0 - dsb - mcr p15, 0, r1, c1, c0, 0 - isb /*Ensuring Context-changing */ - - /*Initialize MPU settings (region 0 to 11) */ - /*Define region 0 */ - mov r0, #0 - ldr r1, =DRBAR_REGION_0 - ldr r2, =DRACR_REGION_0 - ldr r3, =DRSR_REGION_0 - bl mpu_init - - /*Define region 1 */ - mov r0, #1 - ldr r1, =DRBAR_REGION_1 - ldr r2, =DRACR_REGION_1 - ldr r3, =DRSR_REGION_1 - bl mpu_init - - /*Define region 2 */ - mov r0, #2 - ldr r1, =DRBAR_REGION_2 - ldr r2, =DRACR_REGION_2 - ldr r3, =DRSR_REGION_2 - bl mpu_init - - /*Define region 3 */ - mov r0, #3 - ldr r1, =DRBAR_REGION_3 - ldr r2, =DRACR_REGION_3 - ldr r3, =DRSR_REGION_3 - bl mpu_init - - /*Define region 4 */ - mov r0, #4 - ldr r1, =DRBAR_REGION_4 - ldr r2, =DRACR_REGION_4 - ldr r3, =DRSR_REGION_4 - bl mpu_init - - /*Define region 5 */ - mov r0, #5 - ldr r1, =DRBAR_REGION_5 - ldr r2, =DRACR_REGION_5 - ldr r3, =DRSR_REGION_5 - bl mpu_init - - /*Define region 6 */ - mov r0, #6 - ldr r1, =DRBAR_REGION_6 - ldr r2, =DRACR_REGION_6 - ldr r3, =DRSR_REGION_6 - bl mpu_init - - /*Define region 7 */ - mov r0, #7 - ldr r1, =DRBAR_REGION_7 - ldr r2, =DRACR_REGION_7 - ldr r3, =DRSR_REGION_7 - bl mpu_init - - /*Define region 8 */ - mov r0, #8 - ldr r1, =DRBAR_REGION_8 - ldr r2, =DRACR_REGION_8 - ldr r3, =DRSR_REGION_8 - bl mpu_init - - /*Define region 9 - mov r0, #9 */ - ldr r1, =DRBAR_REGION_9 - ldr r2, =DRACR_REGION_9 - ldr r3, =DRSR_REGION_9 - bl mpu_init - - /*Define region 10 */ - mov r0, #10 - ldr r1, =DRBAR_REGION_10 - ldr r2, =DRACR_REGION_10 - ldr r3, =DRSR_REGION_10 - bl mpu_init - - /*Define region 11 */ - mov r0, #11 - ldr r1, =DRBAR_REGION_11 - ldr r2, =DRACR_REGION_11 - ldr r3, =DRSR_REGION_11 - bl mpu_init - - /*Enables MPU operation */ - ldr r0, =SCTLR_M /*Set SCTLR.M bit to 1 */ - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, r0 - dsb - mcr p15, 0, r1, c1, c0, 0 - isb /*Ensuring Context-changing */ - - /*Enables I1,D1 cache operation */ - ldr r0, =SCTLR_I_C /*Set SCTLR.I and C bit to 1 */ - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, r0 - dsb - mcr p15, 0, r1, c1, c0, 0 - isb /*Ensuring Context-changing */ - - pop {pc} - bx lr - -/*********************************************************************************************************************** -* Function Name : mpu_init -* Description : Initialize MPU settings -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -mpu_init: - /*RGNR(MPU Memory Region Number Register) */ - mcr p15, #0, r0, c6, c2, #0 - isb /*Ensuring Context-changing */ - - /*DRBAR(Data Region Base Address Register) */ - mcr p15, #0, r1, c6, c1, #0 - isb /*Ensuring Context-changing */ - - /*DRACR(Data Region Access Control Register) */ - mcr p15, #0, r2, c6, c1, #4 - isb /*Ensuring Context-changing */ - - /*DRSR(Data Region Size and Enable Register) */ - mcr p15, #0, r3, c6, c1, #2 - isb /*Ensuring Context-changing */ - - bx lr - - -/*********************************************************************************************************************** -* Function Name : set_low_vec -* Description : Initialize sysytem by loader program -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -set_low_vec: - mrc p15, 0, r0, c1, c0, 0 /*Set SCTLR.V bit to 1 (low-vector)*/ - and r0, r0, #0xFFFFDFFF - mcr p15, 0, r0, c1, c0, 0 - isb /*Ensuring Context-changing*/ - - bx lr - - .end - -/*End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/start.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/start.asm deleted file mode 100644 index 6bbbc9af1..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/start.asm +++ /dev/null @@ -1,70 +0,0 @@ -/************************************************************************************************************************ -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -************************************************************************************************************************/ -/************************************************************************************************************************ -* File Name : start.asm -* Device(s) : RZ/T1 (R7S910018) -* Tool-Chain : GNUARM-NONEv14.02-EABI -* H/W Platform : RSK+T1 CPU Board -* Description : This is the code to be executed on the target - The copyright string signifies the end of the Vector table -* Note boot strap sequence is as follows: -* -* start->reset_handler->main() -* -* start - first code to be executed on the target - start jumps to reset_handler the asm startup routine -* reset_handler jumps to loader_init1() C entry point -* loader_init2() calls main() C User code entry point -************************************************************************************************************************/ -/************************************************************************************************************************ -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 -************************************************************************************************************************/ - - .text - .code 32 - - .extern FreeRTOS_SVC_Handler - .global start - .func start - -start: - LDR pc, =reset_handler /* Reset Vector */ - LDR pc, =undefined_handler - LDR pc, =FreeRTOS_SVC_Handler - LDR pc, =prefetch_handler - LDR pc, =abort_handler - LDR pc, =reserved_handler - LDR pc, =irq_handler - LDR pc, =fiq_handler -code_start: - .word start /* pointer to the user application start address */ - /* Used by NOR and SPI (System_Boot_Loader_xxxx) */ -code_end: - .word end -code_execute: - .word execute /* execute address of first instruction */ - .string ".BootLoad_ValidProgramTest." /* bootloader validation signature */ - .align 4 - .end diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/vector.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/vector.asm deleted file mode 100644 index 3725c0cf0..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/asm/vector.asm +++ /dev/null @@ -1,76 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** - System Name : RZ/T1 Init program - File Name : vector.asm - Version : 0.1 - Device : R7S910018 - Abstract : vector address (in low vector) - Tool-Chain : GNUARM-NONEv14.02-EABI - OS : not use - H/W Platform : Renesas Starter Kit for RZ/T1 - Description : vector address for RZ/T1 (in low vector) - Limitation : none -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 First Release -***********************************************************************************************************************/ - -/* This program is allocated to section "intvec" */ - - .text - .code 32 - - .global undefined_handler - .global prefetch_handler - .global abort_handler - .global reserved_handler - .global irq_handler - .global fiq_handler - - -undefined_handler: - b undefined_handler - -svc_handler: - b svc_handler - -prefetch_handler: - b prefetch_handler - -abort_handler: - b abort_handler - -reserved_handler: - b reserved_handler - -irq_handler: - b irq_handler - -fiq_handler: - b fiq_handler - - .end - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/ascii.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/ascii.h deleted file mode 100644 index 40dc3d8ca..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/ascii.h +++ /dev/null @@ -1,49 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -************************************************************************************************************************/ -/************************************************************************************************************************ -* File Name : ascii.h -* Device(s) : RZ/T1 (R7S910018) -* Tool-Chain : GNUARM-NONEv14.02-EABI -* H/W Platform : RSK+RZT1 CPU Board -* Description : This Header file contains the Macro Definitions & prototypes -* for the functions used in lcd.c -************************************************************************************************************************/ -/************************************************************************************************************************ -* History : DD.MM.YYYY Version Description -* : 21.04.2015 1.00 -************************************************************************************************************************/ - -/* Multiple inclusion prevention macro */ -#ifndef ASCII_H -#define ASCII_H - -/*********************************************************************************************************************** -Macro Definitions -***********************************************************************************************************************/ -extern const char g_ascii_table[][6]; - -/* ASCII_H */ -#endif - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/compiler_settings.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/compiler_settings.h deleted file mode 100644 index b2e196987..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/compiler_settings.h +++ /dev/null @@ -1,65 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -************************************************************************************************************************/ -/*********************************************************************************************************************** -* File Name : compiler_settings.h -* Device(s) : RZ/A1H (R7S910018) -* Tool-Chain : GNUARM-NONEv14.02-EABI -* H/W Platform : RSK+T1 CPU Board -* Description : Any compiler specific settings are stored here. -* : Variants of this file must be created for each compiler -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 -***********************************************************************************************************************/ - - -/*********************************************************************************************************************** -Includes , "Project Includes" -***********************************************************************************************************************/ -/* Compiler specific UART i/O support header */ -#include "../../GCC/inc/gnu_io.h" - -#ifndef COMPILER_SETTINGS_H -#define COMPILER_SETTINGS_H - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -/* Definitions of SDRAM sections from the linker */ -#define BSS_SDRAM0_SECTION __attribute__ ((section (".sdram0_section"))) -#define BSS_SDRAM1_SECTION __attribute__ ((section (".sdram1_section"))) - -/*********************************************************************************************************************** -Variable External definitions and Function External definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Functions Prototypes -***********************************************************************************************************************/ - -/* COMPILER_SETTINGS_H */ -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/gnu_io.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/gnu_io.h deleted file mode 100644 index 9a5be86f7..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/gnu_io.h +++ /dev/null @@ -1,68 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/****************************************************************************** -* File Name : gnu_io.h -* Device(s) : RZ/A1H (R7S910018) -* Tool-Chain : GNUARM-NONEv14.02-EABI -* H/W Platform : RSK+T1 CPU Board -* Description : GCC support for serial I/O header file -******************************************************************************/ -/****************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 -******************************************************************************/ - -#ifndef GNU_IO_H -#define GNU_IO_H - -/****************************************************************************** -Includes , "Project Includes" -******************************************************************************/ - -/****************************************************************************** -Typedef definitions -******************************************************************************/ - -/****************************************************************************** -Macro definitions -******************************************************************************/ - -/****************************************************************************** -Variable Externs -******************************************************************************/ - -/****************************************************************************** -Functions Prototypes -******************************************************************************/ - -extern void put_string(char *pString); -extern void get_string(char *pString); - - -#endif /* GNU_IO_H */ - -/* End of File */ - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/lcd_pmod.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/lcd_pmod.h deleted file mode 100644 index 7dc1aadf0..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/lcd_pmod.h +++ /dev/null @@ -1,227 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* File Name : lcd_pmod.h -* Device(s) : RZ/T1 (R7S910017) -* Tool-Chain : GNUARM-NONEv14.02-EABI -* H/W Platform : RSK+RZT1 CPU Board -* -* Description : This Header file contains the Macro Definitions & prototypes -* for the functions used in lcd.c -* -* This function is created to drive the Okaya LCD display with -* either ST7735 or ST7715 driver device. The commands for both -* the devices are the same. -* -* The display is controlled using the SPI bus. In this example, -* the SCI5 is used. This can be modified to the SCI connected to -* the PMOD interface. The SCI driver file will also be required. -* -* The display memory has an offset with respect to the actual -* pixel. This is not documented but realised from driving the -* display. The offset is set as LEFT MARGIN and TOP MARGIN. -* This offset is catered for internally, so as far as the user -* is concerned, cursor position 0,0 is the top left pixel. -* -* The simplest procedure to run the display is as follows: -* Init_LCD(); Initialise the serial port and set up the display. -* -* Clear the display. -* The font colour is set to white and background colour to black. -* -* DisplaySetFontColour(COL_YELLOW); -* set the font colour to desired colour -* DisplaySetBackColour(COL_BLUE); -* set the background colour to desired value -* DisplayCenter(1,"Renesas"); -* write a title on line 1 of the display. -* -* Note: Line 0 is the top line. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.04.2015 1.00 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -User Includes (Project Level Includes) -***********************************************************************************************************************/ -/* Defines standard variable types used in this file */ -#include -#include "iodefine.h" - -/*********************************************************************************************************************** -Macro Definitions -***********************************************************************************************************************/ -/* Multiple inclusion prevention macro */ -#ifndef LCD_PMOD_H -#define LCD_PMOD_H - - -/*********************************************************************************************************************** -Macro Definitions for Okaya display on PMOD connector -***********************************************************************************************************************/ - - -/*********************************************************************************************************************** -* SCREEN -* -* The screen size is 128 x 128 pixels, with coordinate 0,0 at the top left. -* The display controller is ST7735 or ST7715. -* -***********************************************************************************************************************/ -/* 16 lines @ 8 bits = 128. */ -#define SCREEN_HEIGHT (128) -#define SCREEN_WIDTH (128) - -#ifndef USE_PMOD2 -/* DATA/COMMAND select pin */ -#define DATA_CMD_PIN (PORT7.PODR.BIT.B6) -/* Backlight enable pin */ -#define BL_ENABLE_PIN (PORT7.PODR.BIT.B4) -/* Reset pin */ -#define RESET_PIN (PORT6.PODR.BIT.B7) -#else -/* DATA/COMMAND select pin */ -#define DATA_CMD_PIN (PORTM.PODR.BIT.B2) -/* Backlight enable pin */ -#define BL_ENABLE_PIN (PORTM.PODR.BIT.B3) -/* Reset pin */ -#define RESET_PIN (PORT5.PODR.BIT.B1) -#endif - -/* Automatic calculation of parameters */ - - /* including a space */ -#define FONT_WIDTH (6u) -/* including 1 pixel space */ -#define FONT_HEIGHT (8u) -#define MAX_LINES (SCREEN_HEIGHT / FONT_HEIGHT) -#define CHAR_PER_LINE (SCREEN_WIDTH / FONT_WIDTH) - -/* Allow 2 pixel margin on the left and the top */ -#define LEFT_MARGIN (2u) -#define TOP_MARGIN (3u) -#define CR (0x0d) -#define LF (0x0a) -#define BS (0x08) - - -/*********************************************************************************************************************** -* DISPLAY COLOUR DEFINITIONS (16 bits) R5G6B5 format -* -* Only Primary & secondary colours are defined here. Other colours can be -* created using RGB values. -***********************************************************************************************************************/ -#define COL_BLACK (0x0000) -#define COL_RED (0xF800) -#define COL_GREEN (0x07E0) -#define COL_BLUE (0x001F) -#define COL_YELLOW (0xFFE0) -#define COL_CYAN (0x07FF) -#define COL_MAGENTA (0xF81F) -#define COL_WHITE (0xFFFF) - -/*********************************************************************************************************************** - - DISPLAY COMMAND SET ST7735 - -***********************************************************************************************************************/ -#define ST7735_NOP (0x0) -#define ST7735_SWRESET (0x01) -#define ST7735_SLPIN (0x10) -#define ST7735_SLPOUT (0x11) -#define ST7735_PTLON (0x12) -#define ST7735_NORON (0x13) -#define ST7735_INVOFF (0x20) -#define ST7735_INVON (0x21) -#define ST7735_DISPOFF (0x28) -#define ST7735_DISPON (0x29) -#define ST7735_CASET (0x2A) -#define ST7735_RASET (0x2B) -#define ST7735_RAMWR (0x2C) -#define ST7735_COLMOD (0x3A) -#define ST7735_MADCTL (0x36) -#define ST7735_FRMCTR1 (0xB1) -#define ST7735_INVCTR (0xB4) -#define ST7735_DISSET5 (0xB6) -#define ST7735_PWCTR1 (0xC0) -#define ST7735_PWCTR2 (0xC1) -#define ST7735_PWCTR3 (0xC2) -#define ST7735_VMCTR1 (0xC5) -#define ST7735_PWCTR6 (0xFC) -#define ST7735_GMCTRP1 (0xE0) -#define ST7735_GMCTRN1 (0xE1) - -/* delay for delay counter */ -#define DELAY_TIMING (0x08) - -/*********************************************************************************************************************** -* Function Prototypes -***********************************************************************************************************************/ -/* Initialises the debug LCD */ -void lcd_init (void); - -/* Display string at specific line of display */ -void display_lcd (uint8_t const line, uint8_t const column, uint8_t const * string); - -/* Display the string at current cursor position */ -void display_str (uint8_t const * str); - -/* Display the sting at the centre of the specified line */ -void display_center (uint8_t const line_num, uint8_t * const str); - -/* Clears the display */ -void clear_display (uint16_t colour); - -/* Clear a specified line */ -void display_clear_line(uint8_t line_num); - -/* Set the current cursor position */ -void display_set_cursor (uint8_t const x, uint8_t const y); - -/* Delay function */ -void display_delay_us (uint32_t time_us); -void display_delay_ms (uint32_t time_ms); - -/* Set Font colour */ -void display_set_font_colour (uint16_t const col); - -/* Set Background colour */ -void display_set_back_colour (uint16_t const col); - -/* Simple image blit */ -void display_image (uint8_t *image, uint8_t image_width, - uint8_t image_height, uint8_t loc_x, uint8_t loc_y); - -/* Enable display */ -void display_on (void); - -/* Disable display */ -void display_off (void); - - -/* LCD_PMOD_H */ -#endif - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/logo_data.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/logo_data.h deleted file mode 100644 index 3971e8950..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/logo_data.h +++ /dev/null @@ -1,44 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/****************************************************************************** -* File Name : logo_data.h -* Device(s) : RZ/A1H (R7S910018) -* Tool-Chain : GNUARM-NONEv14.02-EABI -* H/W Platform : RSK+T1 CPU Board -* Description : Renesas Logo 128*24 pixels -******************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.10.2014 1.00 -***********************************************************************************************************************/ - -/* Multiple inclusion prevention macro */ -#ifndef LOGO_DATA_H -#define LOGO_DATA_H - -/* Declare the image data section */ -extern const uint8_t g_rgb888_logo[]; - -/* LOGO_DATA_H */ -#endif diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_atcm_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_atcm_init.h deleted file mode 100644 index f202d4744..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_atcm_init.h +++ /dev/null @@ -1,64 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* System Name : RZ/T1 Init program -* File Name : r_atcm.h -* Version : 0.1 -* Device : R7S910018 -* Abstract : API for ATCM function -* Tool-Chain : GNUARM-NONEv14.02-EABI -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : ATCM access wait setting API of RZ/T1 -* Limitation : none -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 First Release -***********************************************************************************************************************/ - -#ifndef _R_ATCM_HEADER_ -#define _R_ATCM_HEADER_ - - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -#define ATCM_WAIT_1_OPT (0) -#define ATCM_WAIT_1 (1) -#define ATCM_WAIT_0 (2) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Exported global variables and functions (to be accessed by other files) -***********************************************************************************************************************/ -void R_ATCM_WaitSet(uint32_t atcm_wait); - - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_bsc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_bsc.h deleted file mode 100644 index 998216ca1..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_bsc.h +++ /dev/null @@ -1,186 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* System Name : RZ/T1 Init program -* File Name : r_bsc.h -* Version : 0.1 -* Device : R7S910018 -* Abstract : Definitions for BSC functions -* Tool-Chain : GNUARM-NONEv14.02-EABI -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : BSC setting API of RZ/T1 -* Limitation : none -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 First Release -***********************************************************************************************************************/ - -#ifndef _R_BSC_HEADER_ -#define _R_BSC_HEADER_ - -/*********************************************************************************************************************** -Includes , "Project Includes" -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -#define BSC_IDLE_CYCLE_0 (0) -#define BSC_IDLE_CYCLE_1 (1) -#define BSC_IDLE_CYCLE_2 (2) -#define BSC_IDLE_CYCLE_4 (3) -#define BSC_IDLE_CYCLE_6 (4) -#define BSC_IDLE_CYCLE_8 (5) -#define BSC_IDLE_CYCLE_10 (6) -#define BSC_IDLE_CYCLE_12 (7) - -#define BSC_TYPE_NORMAL (0) -#define BSC_TYPE_BURST_ROM_ASYNC (1) -#define BSC_TYPE_MPX_IO (2) -#define BSC_TYPE_SRAM_BYTE (3) -#define BSC_TYPE_SDRAM (4) -#define BSC_TYPE_BURST_ROM_SYNC (7) - -#define BSC_WIDTH_8_BIT (1) -#define BSC_WIDTH_16_BIT (2) -#define BSC_WIDTH_32_BIT (3) - -#define BSC_DELAY_STATE_CYCLE_0_5 (0) -#define BSC_DELAY_STATE_CYCLE_1_5 (1) -#define BSC_DELAY_STATE_CYCLE_2_5 (2) -#define BSC_DELAY_STATE_CYCLE_3_5 (3) - -#define BSC_EXT_WAIT_VALID (0) -#define BSC_EXT_WAIT_IGNORED (1) - -#define BSC_ACCESS_WAIT_0 (0) -#define BSC_ACCESS_WAIT_1 (1) -#define BSC_ACCESS_WAIT_2 (2) -#define BSC_ACCESS_WAIT_3 (3) -#define BSC_ACCESS_WAIT_4 (4) -#define BSC_ACCESS_WAIT_5 (5) -#define BSC_ACCESS_WAIT_6 (6) -#define BSC_ACCESS_WAIT_8 (7) -#define BSC_ACCESS_WAIT_10 (8) -#define BSC_ACCESS_WAIT_12 (9) -#define BSC_ACCESS_WAIT_14 (10) -#define BSC_ACCESS_WAIT_18 (11) -#define BSC_ACCESS_WAIT_24 (12) - -#define BSC_WRITE_ACCESS_WAIT_SAME (0) -#define BSC_WRITE_ACCESS_WAIT_0 (1) -#define BSC_WRITE_ACCESS_WAIT_1 (2) -#define BSC_WRITE_ACCESS_WAIT_2 (3) -#define BSC_WRITE_ACCESS_WAIT_3 (4) -#define BSC_WRITE_ACCESS_WAIT_4 (5) -#define BSC_WRITE_ACCESS_WAIT_5 (6) -#define BSC_WRITE_ACCESS_WAIT_6 (7) - -#define BSC_BYTE_ENABLE_RD_WR (0) -#define BSC_BYTE_ENABLE_WE (1) - -#define BSC_CAS_LATENCY_1 (0) -#define BSC_CAS_LATENCY_2 (1) -#define BSC_CAS_LATENCY_3 (2) -#define BSC_CAS_LATENCY_4 (3) - -#define BSC_WTRC_IDLE_2 (0) -#define BSC_WTRC_IDLE_3 (1) -#define BSC_WTRC_IDLE_5 (2) -#define BSC_WTRC_IDLE_8 (3) - -#define BSC_TRWL_CYCLE_0 (0) -#define BSC_TRWL_CYCLE_1 (1) -#define BSC_TRWL_CYCLE_2 (2) -#define BSC_TRWL_CYCLE_3 (3) - -#define BSC_PRECHARGE_0 (0x00000000) -#define BSC_PRECHARGE_1 (0x00000008) -#define BSC_PRECHARGE_2 (0x00000010) -#define BSC_PRECHARGE_3 (0x00000018) - -#define BSC_WTRCD_WAIT_0 (0) -#define BSC_WTRCD_WAIT_1 (1) -#define BSC_WTRCD_WAIT_2 (2) -#define BSC_WTRCD_WAIT_3 (3) - -#define BSC_WTRP_WAIT_0 (0) -#define BSC_WTRP_WAIT_1 (1) -#define BSC_WTRP_WAIT_2 (2) -#define BSC_WTRP_WAIT_3 (3) - -#define BSC_ROW_11_BIT (0) -#define BSC_ROW_12_BIT (1) -#define BSC_ROW_13_BIT (2) - -#define BSC_COL_8_BIT (0) -#define BSC_COL_9_BIT (1) -#define BSC_COL_10_BIT (2) - -#define BSC_BACTV_AUTO (0) -#define BSC_BACTV_BANK (1) - -#define BSC_PDOWN_INVALID (0) -#define BSC_PDOWN_VALID (1) - -#define BSC_RMODE_AUTO (0) -#define BSC_RMODE_SELF (1) - -#define BSC_RFSH_NONE (0) -#define BSC_RFSH_DONE (1) - -#define BSC_DEEP_SELF (0) -#define BSC_DEEP_DEEP (1) - -#define BSC_PROTECT_KEY (0xA55A0000) - -#define BSC_RFSH_TIME_1 (0) -#define BSC_RFSH_TIME_2 (1) -#define BSC_RFSH_TIME_4 (2) -#define BSC_RFSH_TIME_6 (3) -#define BSC_RFSH_TIME_8 (4) - -#define BSC_CKS_DIV_STOP (0x00000000) -#define BSC_CKS_DIV_4 (0x00000008) -#define BSC_CKS_DIV_16 (0x00000010) -#define BSC_CKS_DIV_64 (0x00000018) -#define BSC_CKS_DIV_256 (0x00000020) -#define BSC_CKS_DIV_1024 (0x00000028) -#define BSC_CKS_DIV_2048 (0x00000030) -#define BSC_CKS_DIV_4096 (0x00000038) - -#define BSC_CMIE_DISABLE (0x00000000) -#define BSC_CMIE_ENABLE (0x00000040) - -/*********************************************************************************************************************** -Exported global variables and functions (to be accessed by other files) -***********************************************************************************************************************/ - - - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_ram_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_ram_init.h deleted file mode 100644 index 29e920b3a..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_ram_init.h +++ /dev/null @@ -1,64 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* System Name : RZ/T1 Init program -* File Name : r_ram.h -* Version : 0.1 -* Device : R7S910018 -* Abstract : API for internal extended RAM function -* Tool-Chain : GNUARM-NONEv14.02-EABI -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : Internal extended RAM setting API of RZ/T1 -* Limitation : none -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 First Release -***********************************************************************************************************************/ - -#ifndef _R_RAM_HEADER_ -#define _R_RAM_HEADER_ - - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ - - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Exported global variables and functions (to be accessed by other files) -***********************************************************************************************************************/ -void R_RAM_Init(void); -void R_RAM_ECCEnable(void); -void R_RAM_WriteEnable(void); -void R_RAM_WriteDisable(void); - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_reset.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_reset.h deleted file mode 100644 index 78d6c0590..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_reset.h +++ /dev/null @@ -1,62 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* System Name : RZ/T1 Init program -* File Name : r_reset.h -* Version : 0.1 -* Device : R7S910018 -* Abstract : API for reset function -* Tool-Chain : GNUARM-NONEv14.02-EABI -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : Reset function API of RZ/T1 -* Limitation : none -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 First Release -***********************************************************************************************************************/ - -#ifndef _R_RESET_HEADER_ -#define _R_RESET_HEADER_ - - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -#define RST_SOURCE_RES (0x00000002) -#define RST_SOURCE_ECM (0x00000004) -#define RST_SOURCE_SWR1 (0x00000008) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/* RESET and Low-Power function registers access control */ -void r_rst_write_enable(void); -void r_rst_write_disable(void); - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_system.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_system.h deleted file mode 100644 index d08bac6a7..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_system.h +++ /dev/null @@ -1,116 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* System Name : RZ/T1 Init program -* File Name : r_system.h -* Version : 0.1 -* Device : R7S910018 -* Abstract : Definitions for System -* Tool-Chain : GNUARM-NONEv14.02-EABI -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : Define the system settings ans value. -* Limitation : none -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 First Release -***********************************************************************************************************************/ - -#ifndef _R_SYSTEM_HEADER_ -#define _R_SYSTEM_HEADER_ - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ - -#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPCRA0 -#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPCRA1 -#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPCRA2 -#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPCRA3 -#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPCRA4 -#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPCRA5 -#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPCRA6 -#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPCRA7 -#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPCRA8 -#define MSTP_GPTA SYSTEM.MSTPCRA.BIT.MSTPCRA9 -#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPCRA11 - -#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPCRB1 -#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPCRB2 -#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPCRB3 -#define MSTP_SCIFA4 SYSTEM.MSTPCRB.BIT.MSTPCRB5 -#define MSTP_SCIFA3 SYSTEM.MSTPCRB.BIT.MSTPCRB6 -#define MSTP_SCIFA2 SYSTEM.MSTPCRB.BIT.MSTPCRB7 -#define MSTP_SCIFA1 SYSTEM.MSTPCRB.BIT.MSTPCRB8 -#define MSTP_SCIFA0 SYSTEM.MSTPCRB.BIT.MSTPCRB9 -#define MSTP_RSPI3 SYSTEM.MSTPCRB.BIT.MSTPCRB10 -#define MSTP_RSPI2 SYSTEM.MSTPCRB.BIT.MSTPCRB11 -#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPCRB12 -#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPCRB13 -#define MSTP_ETHERSW SYSTEM.MSTPCRB.BIT.MSTPCRB14 -#define MSTP_ECATC SYSTEM.MSTPCRB.BIT.MSTPCRB15 -#define MSTP_EMDIO SYSTEM.MSTPCRB.BIT.MSTPCRB16 -#define MSTP_ERMII SYSTEM.MSTPCRB.BIT.MSTPCRB17 -#define MSTP_HWRTOS SYSTEM.MSTPCRB.BIT.MSTPCRB18 -#define MSTP_CLKOUT25M SYSTEM.MSTPCRB.BIT.MSTPCRB19 - -#define MSTP_USB SYSTEM.MSTPCRC.BIT.MSTPCRC1 -#define MSTP_DSMIF SYSTEM.MSTPCRC.BIT.MSTPCRC2 -#define MSTP_TEMPS SYSTEM.MSTPCRC.BIT.MSTPCRC3 -#define MSTP_S12ADC1 SYSTEM.MSTPCRC.BIT.MSTPCRC4 -#define MSTP_S12ADC0 SYSTEM.MSTPCRC.BIT.MSTPCRC5 -#define MSTP_ELC SYSTEM.MSTPCRC.BIT.MSTPCRC6 -#define MSTP_BSC SYSTEM.MSTPCRC.BIT.MSTPCRC7 -#define MSTP_CKIO SYSTEM.MSTPCRC.BIT.MSTPCRC8 -#define MSTP_SPIBSC SYSTEM.MSTPCRC.BIT.MSTPCRC9 -#define MSTP_DOC SYSTEM.MSTPCRC.BIT.MSTPCRC10 -#define MSTP_CRC SYSTEM.MSTPCRC.BIT.MSTPCRC11 -#define MSTP_CLMA2 SYSTEM.MSTPCRC.BIT.MSTPCRC12 -#define MSTP_CLMA1 SYSTEM.MSTPCRC.BIT.MSTPCRC13 -#define MSTP_CLMA0 SYSTEM.MSTPCRC.BIT.MSTPCRC14 - -#define MSTP_SSI SYSTEM.MSTPCRD.BIT.MSTPCRD2 - -#define MSTP_DMAC1 SYSTEM.MSTPCRE.BIT.MSTPCRE4 -#define MSTP_DMAC0 SYSTEM.MSTPCRE.BIT.MSTPCRE5 - -#define MSTP_CORESIGHT SYSTEM.MSTPCRF.BIT.MSTPCRF0 - -#define __MSTP( x ) MSTP ## x -#define _MSTP( x ) __MSTP( x ) -#define MSTP( x ) _MSTP( _ ## x ) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Exported global variables and functions (to be accessed by other files) -***********************************************************************************************************************/ - -/* End _R_SYSTEM_HEADER_ */ -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_typedefs.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_typedefs.h deleted file mode 100644 index f9cc713d8..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/r_typedefs.h +++ /dev/null @@ -1,87 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* File Name : r_typedefs.h -* Device(s) : RZ/A1H (R7S910018) -* Tool-Chain : GNUARM-NONEv14.02-EABI -* H/W Platform : RSK+T1 CPU Board -* Description : basic type definition -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.10.2014 1.00 -***********************************************************************************************************************/ - - -/*********************************************************************************************************************** -Includes , "Project Includes" -***********************************************************************************************************************/ -#include -/* Multiple inclusion prevention macro */ -#ifndef R_TYPEDEFS_H -#define R_TYPEDEFS_H - - -/* in case has defined it. */ -#ifndef NULL -#define NULL (0) -#endif - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -#if !defined(__bool_true_false_are_defined) && !defined(__cplusplus) - -#define FALSE (0) -#define TRUE (1) - -#endif - -/* These two macros are used to suppress warnings generated by unused variables. - Writing to some registers require a read instruction following the write. - A dummy variable is declared and used to read the register written to. */ -#define UNUSED_PARAM(param) ((void)(param)) -#define UNUSED_VARIABLE(param) ((void)(param)) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ -typedef char char_t; -typedef unsigned int bool_t; -typedef int int_t; -typedef signed char int8_t; -typedef signed short int16_t; -typedef signed long int32_t; -typedef signed long long int64_t; -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned long uint32_t; -typedef unsigned long long uint64_t; -typedef float float32_t; -typedef double float64_t; -typedef long double float128_t; - -/* R_TYPEDEFS_H */ -#endif - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/siochar.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/siochar.h deleted file mode 100644 index 2f603bf4c..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/inc/siochar.h +++ /dev/null @@ -1,57 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* File Name : siochar.h -* Device(s) : RZ/A1H (R7S910018) -* Tool-Chain : GNUARM-NONEv14.02-EABI -* H/W Platform : RSK+T1 CPU Board -* Description : Sample Program - Terminal I/O header file -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.10.2014 1.00 -***********************************************************************************************************************/ - -/* Multiple inclusion prevention macro */ -#ifndef SIO_CHAR_H -#define SIO_CHAR_H - -/*********************************************************************************************************************** -Includes , "Project Includes" -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Functions Prototypes -***********************************************************************************************************************/ -int32_t sio_write (int32_t file_no, const char * buffer, uint32_t writing_b); -int32_t sio_read (int32_t file_no, char * buffer, uint32_t reading_b); - -void io_init_scifa2 (void); -char io_get_char (void); -void io_put_char (char buffer); - -/* SIO_CHAR_H */ -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/loader_init2.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/loader_init2.c deleted file mode 100644 index 394872d3e..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/loader_init2.c +++ /dev/null @@ -1,242 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* System Name : RZ/T1 Init program -* File Name : loader_init2.c -* Version : 0.1 -* Device : R7S910018 -* Abstract : Loader program 2 -* Tool-Chain : GNUARM-NONEv14.02-EABI -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : Initialise the peripheral settings of RZ/T1 -* Limitation : none -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 First Release -***********************************************************************************************************************/ - - -/*********************************************************************************************************************** -Includes , "Project Includes" -***********************************************************************************************************************/ -#include -#include "iodefine.h" -#include "r_cg_cgc.h" -#include "r_cg_mpc.h" -#include "r_system.h" -#include "r_reset.h" -#include "r_atcm_init.h" -#include "r_typedefs.h" - - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Private variables and functions -***********************************************************************************************************************/ -static void reset_check (void); -static void cpg_init (void); - -/*********************************************************************************************************************** -Imported global variables and functions (from other files) -***********************************************************************************************************************/ -extern void main(void); -extern void set_low_vec(void); -extern void cache_init(void); - -/*********************************************************************************************************************** -Exported global variables and functions (to be accessed by other files) -***********************************************************************************************************************/ -void loader_init2 (void); - -/*********************************************************************************************************************** -* Function Name : loader_init2 -* Description : Initialise system by loader program 2 -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -void loader_init2 (void) -{ - /* Check the reset source */ - reset_check(); - - /* Set CPU clock and LOCO clock */ - cpg_init(); - - /* Set ATCM access wait to 1-wait with optimisation */ - /* Caution: ATCM_WAIT_0 is permitted if CPUCLK = 150MHz or 300MHz. - ATCM_WAIT_1_OPT is permitted if CPUCLK = 450MHz or 600MHz.*/ - R_ATCM_WaitSet(ATCM_WAIT_1_OPT); - - /* Initialise I1, D1 Cache and MPU setting */ - cache_init(); - - /* Set RZ/T1 to Low-vector (SCTLR.V = 0) */ - set_low_vec(); - - /* Jump to _main() */ - main(); - -} - -/*********************************************************************************************************************** - End of function loader_init2 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* Function Name : reset_check -* Description : Check the reset source and execute the each sequence. -* When error source number 35 is generated, set P77 pin to High. -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -static void reset_check(void) -{ - volatile uint8_t result=0; - volatile uint32_t dummy=0; - - UNUSED_VARIABLE(result); - UNUSED_VARIABLE(dummy); - - /* Check the reset status flag and execute the each sequence */ - if (RST_SOURCE_ECM == SYSTEM.RSTSR0.LONG) - { - /* Enable writing to the RSTSR0 register */ - r_rst_write_enable(); - - /* Clear reset factor flag */ - SYSTEM.RSTSR0.LONG = 0x00000000; - - /* Disable writing to the RSTSR0 register */ - r_rst_write_disable(); - - /* Please coding the User program */ - - } - - /* Software reset 1 is generated */ - else if (RST_SOURCE_SWR1 == SYSTEM.RSTSR0.LONG) - { - /* Clear reset status flag */ - /* Enable writing to the RSTSR0 register */ - r_rst_write_enable(); - - /* Clear reset factor flag */ - SYSTEM.RSTSR0.LONG = 0x00000000; - - /* Disable writing to the RSTSR0 register */ - r_rst_write_disable(); - - /* Please coding the User program */ - - } - else if (RST_SOURCE_RES == SYSTEM.RSTSR0.LONG) // RES# pin reset is generated - { - /* Clear reset status flag */ - - /* Enable writing to the RSTSR0 register */ - r_rst_write_enable(); - - /* Clear reset factor flag */ - SYSTEM.RSTSR0.LONG = 0x00000000; - - /* Disable writing to the RSTSR0 register */ - r_rst_write_disable(); - - /* Please add user code */ - - } - - /* Any reset is not generated */ - else - { - /* Please add user code */ - } - -} - -/*********************************************************************************************************************** - End of function reset_check -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* Function Name : cpg_init -* Description : Set CPU clock and LOCO clock by CPG function -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -static void cpg_init(void) -{ - volatile uint32_t dummy=0; - - UNUSED_VARIABLE(dummy); - - /* Enables writing to the registers related to CPG function */ - R_CPG_WriteEnable(); - - /* Enables LOCO clock operation */ - SYSTEM.LOCOCR.BIT.LCSTP = CPG_LOCO_ENABLE; - - /* Set CPUCLK to 450MHz, and dummy read at three times */ - SYSTEM.PLL1CR.LONG = CPG_CPUCLK_450_MHz; - dummy = SYSTEM.PLL1CR.LONG; - dummy = SYSTEM.PLL1CR.LONG; - dummy = SYSTEM.PLL1CR.LONG; - - /* Enables PLL1 operation */ - SYSTEM.PLL1CR2.LONG = CPG_PLL1_ON; - - /* Disables writing to the registers related to CPG function */ - R_CPG_WriteDisable(); - - /* Wait about 100us for PLL1 (and LOCO) stabilisation */ - R_CPG_PLLWait(); - - /* Enables writing to the registers related to CPG function */ - R_CPG_WriteEnable(); - - /* Selects the PLL1 as clock source */ - SYSTEM.SCKCR2.LONG = CPG_SELECT_PLL1; - - /* Disables writing to the registers related to CPG function */ - R_CPG_WriteDisable(); - -} - -/*********************************************************************************************************************** - End of function cpg_init -***********************************************************************************************************************/ - - -/* End of File */ - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_atcm_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_atcm_init.c deleted file mode 100644 index 1c135f308..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_atcm_init.c +++ /dev/null @@ -1,111 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* System Name : RZ/T1 Init program -* File Name : r_atcm_init.c -* Version : 0.1 -* Device : R7S910018 -* Abstract : API for ATCM function -* Tool-Chain : GNUARM-NONEv14.02-EABI -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : ATCM access wait setting API of RZ/T1 -* Limitation : This wait setting could not be executed in ATCM program area. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 First Release -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Includes , "Project Includes" -***********************************************************************************************************************/ -#include -#include "iodefine.h" -#include "r_system.h" -#include "r_atcm_init.h" -#include "r_typedefs.h" - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -#define ATCM_WRITE_ENABLE (0x0000A508) -#define ATCM_WRITE_DISABLE (0x0000A500) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - - - -/*********************************************************************************************************************** -Imported global variables and functions (from other files) -***********************************************************************************************************************/ - - -/*********************************************************************************************************************** -Exported global variables and functions (to be accessed by other files) -***********************************************************************************************************************/ - - - -/*********************************************************************************************************************** -Private variables and functions -***********************************************************************************************************************/ - - - -/*********************************************************************************************************************** -* Function Name : R_ATCM_WaitSet -* Description : Sets ATCM access wait. -* Arguments : atcm_wait -* Wait settings for ATCM access -* Return Value : none -***********************************************************************************************************************/ -void R_ATCM_WaitSet(uint32_t atcm_wait) -{ - volatile uint32_t dummy=0; - - UNUSED_VARIABLE(dummy); - - /* Enables writing to the ATCM register */ - SYSTEM.PRCR.LONG = ATCM_WRITE_ENABLE; - dummy = SYSTEM.PRCR.LONG; - - /* Sets ATCM access wait to atcm_wait value */ - SYSTEM.SYTATCMWAIT.LONG = atcm_wait; - - /* Disables writing to the ATCM register */ - SYSTEM.PRCR.LONG = ATCM_WRITE_DISABLE; - dummy = SYSTEM.PRCR.LONG; - -} - -/*********************************************************************************************************************** - End of function R_ATCM_WaitSet -***********************************************************************************************************************/ - -/* End of File */ - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_ram_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_ram_init.c deleted file mode 100644 index 0decedda8..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_ram_init.c +++ /dev/null @@ -1,153 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* System Name : RZ/T1 Init program -* File Name : r_ram_init.c -* Version : 0.1 -* Device : R7S910018 -* Abstract : API for internal extended RAM function -* Tool-Chain : GNUARM-NONEv14.02-EABI -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : internal extended RAM setting API of RZ/T1 -* Limitation : none -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 First Release -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Includes , "Project Includes" -***********************************************************************************************************************/ -#include -#include "iodefine.h" -#include "r_system.h" -#include "r_ram_init.h" -#include "r_typedefs.h" - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -#define RAM_ECC_ENABLE (0x00000001) -#define RAM_ECC_DISABLE (0x00000000) -#define RAM_PROTECT (0x00000000) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - - - -/*********************************************************************************************************************** -Imported global variables and functions (from other files) -***********************************************************************************************************************/ - - -/*********************************************************************************************************************** -Exported global variables and functions (to be accessed by other files) -***********************************************************************************************************************/ - - - -/*********************************************************************************************************************** -Private variables and functions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* Function Name : R_RAM_ECCEnable -* Description : Enable ECC function for internal extended RAM. -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -void R_RAM_ECCEnable(void) -{ - /* Enables writing to the protected registers related to RAM function */ - R_RAM_WriteEnable(); - - /* Enable ECC function */ - ECCRAM.RAMEDC.LONG = RAM_ECC_ENABLE; - - /* Disables writing to the protected registers related to RAM function */ - R_RAM_WriteDisable(); - -} - -/*********************************************************************************************************************** - End of function R_RAM_ECCEnable -***********************************************************************************************************************/ - - -/*********************************************************************************************************************** -* Function Name : R_RAM_WriteEnable -* Description : Enable writing to the protected registers related to RAM. -* And dummy read the register in order to fix the register value. -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -void R_RAM_WriteEnable(void) -{ - volatile uint32_t dummy=0; - - UNUSED_VARIABLE(dummy); - - /* Special sequence for protect release */ - ECCRAM.RAMPCMD.LONG = 0x000000A5; // Write fixed value 0x000000A5 - ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value - ECCRAM.RAMPCMD.LONG = 0x0000FFFE; // Write inverted value of the expected value - ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value again - dummy = ECCRAM.RAMPCMD.LONG; - -} - -/*********************************************************************************************************************** - End of function R_RAM_WriteEnable -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* Function Name : R_RAM_WriteDisable -* Description : Disable writing to the protected registers related to RAM. -* And dummy read the register in order to fix the register value. -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -void R_RAM_WriteDisable(void) -{ - volatile uint32_t dummy=0; - - UNUSED_VARIABLE(dummy); - - /* Clear RAMPCMD register to zero */ - ECCRAM.RAMPCMD.LONG = RAM_PROTECT; - dummy = ECCRAM.RAMPCMD.LONG; - -} - -/*********************************************************************************************************************** - End of function R_RAM_WriteDisable -***********************************************************************************************************************/ - -/* End of File */ - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_reset.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_reset.c deleted file mode 100644 index 60fc61523..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/r_reset.c +++ /dev/null @@ -1,128 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* System Name : RZ/T1 Init program -* File Name : r_reset.c -* Version : 0.1 -* Device : R7S910018 -* Abstract : API for RESET and Low-Power function -* Tool-Chain : GNUARM-NONEv14.02-EABI -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : RESET and Low-Power API of RZ/T1 -* Limitation : none -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.05.2015 1.00 First Release -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Includes , "Project Includes" -***********************************************************************************************************************/ -#include -#include "iodefine.h" -#include "r_system.h" -#include "r_reset.h" -#include "r_typedefs.h" - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -#define RST_WRITE_ENABLE (0x0000A502) -#define RST_WRITE_DISABLE (0x0000A500) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - - - -/*********************************************************************************************************************** -Imported global variables and functions (from other files) -***********************************************************************************************************************/ - - -/*********************************************************************************************************************** -Exported global variables and functions (to be accessed by other files) -***********************************************************************************************************************/ - - - -/*********************************************************************************************************************** -Private variables and functions -***********************************************************************************************************************/ - - -/******************************************************************************* -* Function Name : r_rst_write_enable -* Description : Enables writing to the registers related to RESET and Low- -* Power function. And dummy read the register in order to fix -* the register value. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void r_rst_write_enable(void) -{ - volatile uint32_t dummy=0; - - UNUSED_VARIABLE(dummy); - - /* Enables writing to the Reset and Low-Power register */ - SYSTEM.PRCR.LONG = RST_WRITE_ENABLE; - dummy = SYSTEM.PRCR.LONG; - -} - -/******************************************************************************* - End of function r_rst_write_enable -*******************************************************************************/ - -/******************************************************************************* -* Function Name : r_rst_write_disable -* Description : Disables writing to the registers related to RESET and Low- -* Power function. And dummy read the register in order to fix -* the register value. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void r_rst_write_disable(void) -{ - volatile uint32_t dummy=0; - - UNUSED_VARIABLE(dummy); - - /* Disables writing to the Reset and Low-Power register */ - SYSTEM.PRCR.LONG = RST_WRITE_DISABLE; - dummy = SYSTEM.PRCR.LONG; - -} - -/*********************************************************************************************************************** - End of function r_rst_write_disable -***********************************************************************************************************************/ - -/* End of File */ - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/Interrupt_Entry_Stubs.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/Interrupt_Entry_Stubs.asm deleted file mode 100644 index 4668654ac..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/Interrupt_Entry_Stubs.asm +++ /dev/null @@ -1,117 +0,0 @@ -/* - FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - SECTION intvec:CODE:ROOT(2) - ARM - - EXTERN pxISRFunction - EXTERN FreeRTOS_Tick_Handler - EXTERN FreeRTOS_IRQ_Handler - EXTERN vCMT_1_Channel_0_ISR - EXTERN vCMT_1_Channel_1_ISR - - PUBLIC FreeRTOS_Tick_Handler_Entry - PUBLIC vCMT_1_Channel_0_ISR_Entry - PUBLIC vCMT_1_Channel_1_ISR_Entry - -FreeRTOS_Tick_Handler_Entry: - /* Save used registers (probably not necessary). */ - PUSH {r0-r1} - /* Save the address of the C portion of this handler in pxISRFunction. */ - LDR r0, =pxISRFunction - LDR R1, =FreeRTOS_Tick_Handler - STR R1, [r0] - /* Restore used registers then branch to the FreeRTOS IRQ handler. */ - POP {r0-r1} - B FreeRTOS_IRQ_Handler -/*-----------------------------------------------------------*/ - -vCMT_1_Channel_0_ISR_Entry: - /* Save used registers (probably not necessary). */ - PUSH {r0-r1} - /* Save the address of the C portion of this handler in pxISRFunction. */ - LDR r0, =pxISRFunction - LDR R1, =vCMT_1_Channel_0_ISR - STR R1, [r0] - /* Restore used registers then branch to the FreeRTOS IRQ handler. */ - POP {r0-r1} - B FreeRTOS_IRQ_Handler -/*-----------------------------------------------------------*/ - -vCMT_1_Channel_1_ISR_Entry: - /* Save used registers (probably not necessary). */ - PUSH {r0-r1} - /* Save the address of the C portion of this handler in pxISRFunction. */ - LDR r0, =pxISRFunction - LDR R1, =vCMT_1_Channel_1_ISR - STR R1, [r0] - /* Restore used registers then branch to the FreeRTOS IRQ handler. */ - POP {r0-r1} - B FreeRTOS_IRQ_Handler - - END diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZT1_init_RAM.mac b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZT1_init_RAM.mac deleted file mode 100644 index 795e779e8..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZT1_init_RAM.mac +++ /dev/null @@ -1,81 +0,0 @@ -/* - * - * C-SPY macro information - * - * __jtagCP15ReadReg(CRn, CRm, op1, op2) - * __jtagCP15WriteReg(CRn, CRm, op1, op2, value) - * __readMemory8(address, zone) - * __writeMemory8(value, address, zone) - * __writeMemory32(value, address, zone) - * - * - */ - -__init_TCM() -{ -__var v_reg; - - __message "Initialize ATCM"; - /* - MRC p15, 0, , c1, c0, 1 ; Read ACTLR - MCR p15, 0, , c1, c0, 1 ; Write ACTLR - */ - - /* enable ECC in ACTLR */ - v_reg = __jtagCP15ReadReg(1, 0, 0, 1); - v_reg = v_reg | 0x06000000; // set 26 and 25 bits for enabling ECC - __message "ACTRL: ", v_reg:%x; // output ACTRL value for check - __jtagCP15WriteReg(1, 0, 0, 1, v_reg); - - __fillMemory32(0x0, 0x00000000, "Memory", 0x20000, "Copy"); - __message "ATCM initialization finished"; -} - - -__init_VIC_ProvideHandler() -{ -__var v_reg; - - __message "Initialize VIC provide handler \n"; - /* - MRC p15, 0, , c1, c0, 0 ; Read SCTLR - MCR p15, 0, , c1, c0, 0 ; Write SCTLR - */ - - /* Set VIC to provide handler address */ - v_reg = __jtagCP15ReadReg(1, 0, 0, 0); - v_reg = v_reg | 0x01000000; // set 24 bit for setting VE bit - __jtagCP15WriteReg(1, 0, 0, 0, v_reg); - -} - -execUserPreload() -{ -__var t ; - - __message "Executing execUserPreload() function"; - - __hwReset(0); - __delay(100); - __init_TCM(); - - __message "FINISH Executing execUserPreload() function"; -} - - -execUserReset() -{ -__var t; - __message "Executing execUserReset() function"; - - __init_VIC_ProvideHandler(); - - t = #CPSR; // Clear CPSR.F bit - __message "CPSR ",t:%x; - t = t & 0xFFFFFFBF; - #CPSR = t; - t = #CPSR; - __message "CPSR ",t:%x; - - __message "FINISH Executing execUserReset() function"; -} diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZ_T1_init.icf b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZ_T1_init.icf deleted file mode 100644 index 2e86388b6..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/RZ_T1_init.icf +++ /dev/null @@ -1,163 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x40020040; -define symbol __ICFEDIT_region_ROM_end__ = 0x4008FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x00070000; -define symbol __ICFEDIT_region_RAM_end__ = 0x0007FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; -define symbol __ICFEDIT_size_svcstack__ = 0x200; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x100; -define symbol __ICFEDIT_size_undstack__ = 0x100; -define symbol __ICFEDIT_size_abtstack__ = 0x100; -define symbol __ICFEDIT_size_heap__ = 0x1000; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define symbol __region_USER_PRG_start__ = 0x00000040; -define symbol __region_USER_PRG_end__ = 0x0006FFFF; - -define symbol __region_D_LDR_DATA_start__ = 0x00800000; -define symbol __region_D_LDR_DATA_end__ = 0x00801FFF; -define symbol __region_D_LDR_PRG_start__ = 0x00802000; -define symbol __region_D_LDR_PRG_end__ = 0x00807FFF; - -define symbol __region_D_LDR_M3PRG_start__ = 0x04000000; -define symbol __region_D_LDR_M3PRG_end__ = 0x0407FFFF; - -define symbol __region_S_LDR_M3PRG_start__ = 0x00050000; -define symbol __region_S_LDR_M3PRG_end__ = 0x0006FFFF; - -define symbol __region_EXT_RAM1_start__ = 0x22000000; -define symbol __region_EXT_RAM1_end__ = 0x2207FFFF; -define symbol __region_EXT_RAM2_start__ = 0x24000000; -define symbol __region_EXT_RAM2_end__ = 0x2407FFFF; -define symbol __region_SPIBSC_start__ = 0x30000000; -define symbol __region_SPIBSC_end__ = 0x33FFFFFF; - -define symbol __region_CS0_start__ = 0x40000000; -define symbol __region_CS0_end__ = 0x43FFFFFF; -define symbol __region_CS1_start__ = 0x44000000; -define symbol __region_CS1_end__ = 0x47FFFFFF; -define symbol __region_CS2_start__ = 0x48000000; -define symbol __region_CS2_end__ = 0x4BFFFFFF; -define symbol __region_CS3_start__ = 0x4C000000; -define symbol __region_CS3_end__ = 0x4FFFFFFF; -define symbol __region_CS4_start__ = 0x50000000; -define symbol __region_CS4_end__ = 0x53FFFFFF; -define symbol __region_CS5_start__ = 0x54000000; -define symbol __region_CS5_end__ = 0x57FFFFFF; - -define region USER_PRG_region = mem:[from __region_USER_PRG_start__ to __region_USER_PRG_end__]; -define region D_LDR_DATA_region = mem:[from __region_D_LDR_DATA_start__ to __region_D_LDR_DATA_end__]; -define region D_LDR_PRG_region = mem:[from __region_D_LDR_PRG_start__ to __region_D_LDR_PRG_end__]; - -define region D_LDR_M3PRG_region = mem:[from __region_D_LDR_M3PRG_start__ to __region_D_LDR_M3PRG_end__]; -define region S_LDR_M3PRG_region = mem:[from __region_S_LDR_M3PRG_start__ to __region_S_LDR_M3PRG_end__]; - -define region EXT_RAM1_region = mem:[from __region_EXT_RAM1_start__ to __region_EXT_RAM1_end__]; -define region EXT_RAM2_region = mem:[from __region_EXT_RAM2_start__ to __region_EXT_RAM2_end__]; -define region SPIBSC_region = mem:[from __region_SPIBSC_start__ to __region_SPIBSC_end__]; -define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__]; -define region CS1_region = mem:[from __region_CS1_start__ to __region_CS1_end__]; -define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__]; -define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__]; -define region CS4_region = mem:[from __region_CS4_start__ to __region_CS4_end__]; -define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - - -define block LDR_PRG_RBLOCK with fixed order - { ro code object loader_init.o, - ro code object loader_init2.o, - ro code object r_atcm_init.o, - ro code object r_cpg.o, - ro code object r_ram_init.o, - ro code object r_mpc.o, - ro code object r_reset.o, - ro code object data_init.o, - ro code object copy_init3.o }; -define block LDR_DATA_ZBLOCK { section .bss object loader_init.o, - section .bss object loader_init2.o, - section .bss object r_atcm_init.o, - section .bss object r_cpg.o, - section .bss object r_ram_init.o, - section .bss object r_mpc.o, - section .bss object r_reset.o, - section .bss object data_init.o, - section .bss object copy_init3.o }; -define block LDR_DATA_RBLOCK { section .data_init object loader_init.o, - section .data_init object loader_init2.o, - section .data_init object r_atcm_init.o, - section .data_init object r_cpg.o, - section .data_init object r_ram_init.o, - section .data_init object r_mpc.o, - section .data_init object r_reset.o, - section .data_init object data_init.o, - section .data_init object copy_init3.o }; -define block LDR_DATA_WBLOCK { section .data object loader_init.o, - section .data object loader_init2.o, - section .data object r_atcm_init.o, - section .data object r_cpg.o, - section .data object r_ram_init.o, - section .data object r_mpc.o, - section .data object r_reset.o, - section .data object data_init.o, - section .data object copy_init3.o }; -define block VECTOR_RBLOCK { ro code object vector.o }; -define block USER_PRG_RBLOCK { ro code }; -define block USER_DATA_ZBLOCK { section .bss }; -define block USER_DATA_RBLOCK { section .data_init }; -define block USER_DATA_WBLOCK { section .data }; - -define block M3_PRG_RBLOCK { section __M3prg_init }; -define block M3_PRG_WBLOCK { section __M3prg }; - -initialize by copy { readwrite }; - -do not initialize { section .noinit, section .bss }; - -initialize manually { section __M3prg }; - -place at address mem:__ICFEDIT_intvec_start__ { block VECTOR_RBLOCK }; - -place in USER_PRG_region { block USER_PRG_RBLOCK, - block USER_DATA_RBLOCK, - readonly }; -place in RAM_region { readwrite }; -place in RAM_region { block USER_DATA_WBLOCK, - block USER_DATA_ZBLOCK, - block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, - block UND_STACK, block ABT_STACK, block HEAP }; -place in D_LDR_DATA_region { block LDR_DATA_WBLOCK, block LDR_DATA_ZBLOCK }; -place in D_LDR_PRG_region { block LDR_PRG_RBLOCK, - block LDR_DATA_RBLOCK }; - -place in S_LDR_M3PRG_region { block M3_PRG_RBLOCK }; -place in D_LDR_M3PRG_region { block M3_PRG_WBLOCK }; - -place in EXT_RAM1_region {}; -place in EXT_RAM2_region {}; -place in SPIBSC_region {}; -place in CS0_region {}; -place in CS1_region {}; -place in CS2_region {}; -place in CS3_region {}; -place in CS4_region {}; -place in CS5_region {}; diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_atcm_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_atcm_init.h deleted file mode 100644 index 977d508fc..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_atcm_init.h +++ /dev/null @@ -1,64 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_atcm.h -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for ATCM function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : ATCM access wait setting API of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -#ifndef _R_ATCM_HEADER_ -#define _R_ATCM_HEADER_ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define ATCM_WAIT_1_OPT (0) -#define ATCM_WAIT_1 (1) -#define ATCM_WAIT_0 (2) - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -void R_ATCM_WaitSet(uint32_t atcm_wait); - - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_bsc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_bsc.h deleted file mode 100644 index 926c3aaef..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_bsc.h +++ /dev/null @@ -1,186 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_cpg.h -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for CPG function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : BSC setting API of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -#ifndef _R_BSC_HEADER_ -#define _R_BSC_HEADER_ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define BSC_IDLE_CYCLE_0 (0) -#define BSC_IDLE_CYCLE_1 (1) -#define BSC_IDLE_CYCLE_2 (2) -#define BSC_IDLE_CYCLE_4 (3) -#define BSC_IDLE_CYCLE_6 (4) -#define BSC_IDLE_CYCLE_8 (5) -#define BSC_IDLE_CYCLE_10 (6) -#define BSC_IDLE_CYCLE_12 (7) - -#define BSC_TYPE_NORMAL (0) -#define BSC_TYPE_BURST_ROM_ASYNC (1) -#define BSC_TYPE_MPX_IO (2) -#define BSC_TYPE_SRAM_BYTE (3) -#define BSC_TYPE_SDRAM (4) -#define BSC_TYPE_BURST_ROM_SYNC (7) - -#define BSC_WIDTH_8_BIT (1) -#define BSC_WIDTH_16_BIT (2) -#define BSC_WIDTH_32_BIT (3) - -#define BSC_DELAY_STATE_CYCLE_0_5 (0) -#define BSC_DELAY_STATE_CYCLE_1_5 (1) -#define BSC_DELAY_STATE_CYCLE_2_5 (2) -#define BSC_DELAY_STATE_CYCLE_3_5 (3) - -#define BSC_EXT_WAIT_VALID (0) -#define BSC_EXT_WAIT_IGNORED (1) - -#define BSC_ACCESS_WAIT_0 (0) -#define BSC_ACCESS_WAIT_1 (1) -#define BSC_ACCESS_WAIT_2 (2) -#define BSC_ACCESS_WAIT_3 (3) -#define BSC_ACCESS_WAIT_4 (4) -#define BSC_ACCESS_WAIT_5 (5) -#define BSC_ACCESS_WAIT_6 (6) -#define BSC_ACCESS_WAIT_8 (7) -#define BSC_ACCESS_WAIT_10 (8) -#define BSC_ACCESS_WAIT_12 (9) -#define BSC_ACCESS_WAIT_14 (10) -#define BSC_ACCESS_WAIT_18 (11) -#define BSC_ACCESS_WAIT_24 (12) - -#define BSC_WRITE_ACCESS_WAIT_SAME (0) // Set same settings of WR[3:0]bit -#define BSC_WRITE_ACCESS_WAIT_0 (1) -#define BSC_WRITE_ACCESS_WAIT_1 (2) -#define BSC_WRITE_ACCESS_WAIT_2 (3) -#define BSC_WRITE_ACCESS_WAIT_3 (4) -#define BSC_WRITE_ACCESS_WAIT_4 (5) -#define BSC_WRITE_ACCESS_WAIT_5 (6) -#define BSC_WRITE_ACCESS_WAIT_6 (7) - -#define BSC_BYTE_ENABLE_RD_WR (0) -#define BSC_BYTE_ENABLE_WE (1) - -#define BSC_CAS_LATENCY_1 (0) -#define BSC_CAS_LATENCY_2 (1) -#define BSC_CAS_LATENCY_3 (2) -#define BSC_CAS_LATENCY_4 (3) - -#define BSC_WTRC_IDLE_2 (0) -#define BSC_WTRC_IDLE_3 (1) -#define BSC_WTRC_IDLE_5 (2) -#define BSC_WTRC_IDLE_8 (3) - -#define BSC_TRWL_CYCLE_0 (0) -#define BSC_TRWL_CYCLE_1 (1) -#define BSC_TRWL_CYCLE_2 (2) -#define BSC_TRWL_CYCLE_3 (3) - -#define BSC_PRECHARGE_0 (0x00000000) -#define BSC_PRECHARGE_1 (0x00000008) -#define BSC_PRECHARGE_2 (0x00000010) -#define BSC_PRECHARGE_3 (0x00000018) - -#define BSC_WTRCD_WAIT_0 (0) -#define BSC_WTRCD_WAIT_1 (1) -#define BSC_WTRCD_WAIT_2 (2) -#define BSC_WTRCD_WAIT_3 (3) - -#define BSC_WTRP_WAIT_0 (0) -#define BSC_WTRP_WAIT_1 (1) -#define BSC_WTRP_WAIT_2 (2) -#define BSC_WTRP_WAIT_3 (3) - -#define BSC_ROW_11_BIT (0) -#define BSC_ROW_12_BIT (1) -#define BSC_ROW_13_BIT (2) - -#define BSC_COL_8_BIT (0) -#define BSC_COL_9_BIT (1) -#define BSC_COL_10_BIT (2) - -#define BSC_BACTV_AUTO (0) -#define BSC_BACTV_BANK (1) - -#define BSC_PDOWN_INVALID (0) -#define BSC_PDOWN_VALID (1) - -#define BSC_RMODE_AUTO (0) -#define BSC_RMODE_SELF (1) - -#define BSC_RFSH_NONE (0) -#define BSC_RFSH_DONE (1) - -#define BSC_DEEP_SELF (0) -#define BSC_DEEP_DEEP (1) - -#define BSC_PROTECT_KEY (0xA55A0000) - -#define BSC_RFSH_TIME_1 (0) -#define BSC_RFSH_TIME_2 (1) -#define BSC_RFSH_TIME_4 (2) -#define BSC_RFSH_TIME_6 (3) -#define BSC_RFSH_TIME_8 (4) - -#define BSC_CKS_DIV_STOP (0x00000000) -#define BSC_CKS_DIV_4 (0x00000008) -#define BSC_CKS_DIV_16 (0x00000010) -#define BSC_CKS_DIV_64 (0x00000018) -#define BSC_CKS_DIV_256 (0x00000020) -#define BSC_CKS_DIV_1024 (0x00000028) -#define BSC_CKS_DIV_2048 (0x00000030) -#define BSC_CKS_DIV_4096 (0x00000038) - -#define BSC_CMIE_DISABLE (0x00000000) -#define BSC_CMIE_ENABLE (0x00000040) - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_cpg.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_cpg.h deleted file mode 100644 index 5dd55d605..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_cpg.h +++ /dev/null @@ -1,83 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_cpg.h -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for CPG function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : CPG setting API of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -#ifndef _R_CPG_HEADER_ -#define _R_CPG_HEADER_ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define CPG_CPUCLK_150_MHz (0) -#define CPG_CPUCLK_300_MHz (1) -#define CPG_CPUCLK_450_MHz (2) -#define CPG_CPUCLK_600_MHz (3) - -#define CPG_PLL1_OFF (0) -#define CPG_PLL1_ON (1) - -#define CPG_SELECT_PLL0 (0) -#define CPG_SELECT_PLL1 (1) - -#define CPG_CKIO_75_MHz (0) -#define CPG_CKIO_50_MHz (1) -#define CPG_CKIO_37_5_MHz (2) -#define CPG_CKIO_30_MHz (3) -#define CPG_CKIO_25_MHz (4) -#define CPG_CKIO_21_43_MHz (5) -#define CPG_CKIO_18_75_MHz (6) - -#define CPG_LOCO_ENABLE (0x00000000) -#define CPG_LOCO_DISABLE (0x00000001) - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -void R_CPG_WriteEnable(void); -void R_CPG_WriteDisable(void); -void R_CPG_PLL_Wait(void); - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ecm.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ecm.h deleted file mode 100644 index be645eec2..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ecm.h +++ /dev/null @@ -1,72 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_ecm.h -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for ecm function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : ecm function API of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -#ifndef _R_ECM_HEADER_ -#define _R_ECM_HEADER_ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define ECM_COMMAND_KEY (0x000000A5) - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ -typedef enum -{ - ECM_MASTER, - ECM_CHECKER, - ECM_COMMON, - ECM_TYPE_MAX -} ecm_reg_type_t; - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -void R_ECM_Init(void); -void R_ECM_CompareError_Wait(void); -uint8_t R_ECM_Write_Reg8(uint8_t reg_type, volatile unsigned char *reg, uint8_t value); -uint8_t R_ECM_Write_Reg32(uint8_t reg_type, volatile unsigned long *reg, uint32_t value); - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_icu_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_icu_init.h deleted file mode 100644 index be11be733..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_icu_init.h +++ /dev/null @@ -1,389 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_icu_init.h -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for ICU init -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : Initialize interrupt controller unit. -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -#ifndef _R_ICU_INIT_HEADER_ -#define _R_ICU_INIT_HEADER_ - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - -#define ICU_EXT_PIN_0 (0) -#define ICU_EXT_PIN_1 (1) -#define ICU_EXT_PIN_2 (2) -#define ICU_EXT_PIN_3 (3) -#define ICU_EXT_PIN_4 (4) -#define ICU_EXT_PIN_5 (5) -#define ICU_EXT_PIN_6 (6) -#define ICU_EXT_PIN_7 (7) -#define ICU_EXT_PIN_8 (8) -#define ICU_EXT_PIN_9 (9) -#define ICU_EXT_PIN_10 (10) -#define ICU_EXT_PIN_11 (11) -#define ICU_EXT_PIN_12 (12) -#define ICU_EXT_PIN_13 (13) -#define ICU_EXT_PIN_14 (14) -#define ICU_EXT_PIN_15 (15) - -#define ICU_DETECT_LOW (0x00) -#define ICU_DETECT_FALL (0x04) -#define ICU_DETECT_RISE (0x08) -#define ICU_DETECT_RISE_FALL (0x0C) - -#define ICU_DNF_DIVISION_1 (0) -#define ICU_DNF_DIVISION_8 (1) -#define ICU_DNF_DIVISION_32 (2) -#define ICU_DNF_DIVISION_64 (3) -#define ICU_DNF_NO_USE (4) - -#define ICU_VEC_NUM_1 (1) -#define ICU_VEC_NUM_2 (2) -#define ICU_VEC_NUM_3 (3) -#define ICU_VEC_NUM_4 (4) -#define ICU_VEC_NUM_5 (5) -#define ICU_VEC_NUM_6 (6) -#define ICU_VEC_NUM_7 (7) -#define ICU_VEC_NUM_8 (8) -#define ICU_VEC_NUM_9 (9) -#define ICU_VEC_NUM_10 (10) -#define ICU_VEC_NUM_11 (11) -#define ICU_VEC_NUM_12 (12) -#define ICU_VEC_NUM_13 (13) -#define ICU_VEC_NUM_14 (14) -#define ICU_VEC_NUM_15 (15) -#define ICU_VEC_NUM_16 (16) -#define ICU_VEC_NUM_17 (17) -#define ICU_VEC_NUM_18 (18) -#define ICU_VEC_NUM_19 (19) -#define ICU_VEC_NUM_20 (20) -#define ICU_VEC_NUM_21 (21) -#define ICU_VEC_NUM_22 (22) -#define ICU_VEC_NUM_23 (23) -#define ICU_VEC_NUM_24 (24) -#define ICU_VEC_NUM_25 (25) -#define ICU_VEC_NUM_26 (26) -#define ICU_VEC_NUM_27 (27) -#define ICU_VEC_NUM_28 (28) -#define ICU_VEC_NUM_29 (29) -#define ICU_VEC_NUM_30 (30) -#define ICU_VEC_NUM_31 (31) -#define ICU_VEC_NUM_32 (32) -#define ICU_VEC_NUM_33 (33) -#define ICU_VEC_NUM_34 (34) -#define ICU_VEC_NUM_35 (35) -#define ICU_VEC_NUM_36 (36) -#define ICU_VEC_NUM_37 (37) -#define ICU_VEC_NUM_38 (38) -#define ICU_VEC_NUM_39 (39) -#define ICU_VEC_NUM_40 (40) -#define ICU_VEC_NUM_41 (41) -#define ICU_VEC_NUM_42 (42) -#define ICU_VEC_NUM_43 (43) -#define ICU_VEC_NUM_44 (44) -#define ICU_VEC_NUM_45 (45) -#define ICU_VEC_NUM_46 (46) -#define ICU_VEC_NUM_47 (47) -#define ICU_VEC_NUM_48 (48) -#define ICU_VEC_NUM_49 (49) -#define ICU_VEC_NUM_50 (50) -#define ICU_VEC_NUM_51 (51) -#define ICU_VEC_NUM_52 (52) -#define ICU_VEC_NUM_53 (53) -#define ICU_VEC_NUM_54 (54) -#define ICU_VEC_NUM_55 (55) -#define ICU_VEC_NUM_56 (56) -#define ICU_VEC_NUM_57 (57) -#define ICU_VEC_NUM_58 (58) -#define ICU_VEC_NUM_59 (59) -#define ICU_VEC_NUM_60 (60) -#define ICU_VEC_NUM_61 (61) -#define ICU_VEC_NUM_62 (62) -#define ICU_VEC_NUM_63 (63) -#define ICU_VEC_NUM_64 (64) -#define ICU_VEC_NUM_65 (65) -#define ICU_VEC_NUM_66 (66) -#define ICU_VEC_NUM_67 (67) -#define ICU_VEC_NUM_68 (68) -#define ICU_VEC_NUM_69 (69) -#define ICU_VEC_NUM_70 (70) -#define ICU_VEC_NUM_73 (73) -#define ICU_VEC_NUM_74 (74) -#define ICU_VEC_NUM_75 (75) -#define ICU_VEC_NUM_76 (76) -#define ICU_VEC_NUM_77 (77) -#define ICU_VEC_NUM_78 (78) -#define ICU_VEC_NUM_79 (79) -#define ICU_VEC_NUM_80 (80) -#define ICU_VEC_NUM_81 (81) -#define ICU_VEC_NUM_82 (82) -#define ICU_VEC_NUM_83 (83) -#define ICU_VEC_NUM_84 (84) -#define ICU_VEC_NUM_85 (85) -#define ICU_VEC_NUM_86 (86) -#define ICU_VEC_NUM_87 (87) -#define ICU_VEC_NUM_88 (88) -#define ICU_VEC_NUM_89 (89) -#define ICU_VEC_NUM_90 (90) -#define ICU_VEC_NUM_91 (91) -#define ICU_VEC_NUM_92 (92) -#define ICU_VEC_NUM_93 (93) -#define ICU_VEC_NUM_94 (94) -#define ICU_VEC_NUM_95 (95) -#define ICU_VEC_NUM_96 (96) -#define ICU_VEC_NUM_97 (97) -#define ICU_VEC_NUM_98 (98) -#define ICU_VEC_NUM_99 (99) -#define ICU_VEC_NUM_100 (100) -#define ICU_VEC_NUM_101 (101) -#define ICU_VEC_NUM_102 (102) -#define ICU_VEC_NUM_103 (103) -#define ICU_VEC_NUM_104 (104) -#define ICU_VEC_NUM_105 (105) -#define ICU_VEC_NUM_106 (106) -#define ICU_VEC_NUM_107 (107) -#define ICU_VEC_NUM_108 (108) -#define ICU_VEC_NUM_109 (109) -#define ICU_VEC_NUM_110 (110) -#define ICU_VEC_NUM_111 (111) -#define ICU_VEC_NUM_112 (112) -#define ICU_VEC_NUM_113 (113) -#define ICU_VEC_NUM_114 (114) -#define ICU_VEC_NUM_115 (115) -#define ICU_VEC_NUM_116 (116) -#define ICU_VEC_NUM_117 (117) -#define ICU_VEC_NUM_118 (118) -#define ICU_VEC_NUM_119 (119) -#define ICU_VEC_NUM_120 (120) -#define ICU_VEC_NUM_121 (121) -#define ICU_VEC_NUM_122 (122) -#define ICU_VEC_NUM_123 (123) -#define ICU_VEC_NUM_124 (124) -#define ICU_VEC_NUM_125 (125) -#define ICU_VEC_NUM_126 (126) -#define ICU_VEC_NUM_127 (127) -#define ICU_VEC_NUM_128 (128) -#define ICU_VEC_NUM_145 (145) -#define ICU_VEC_NUM_146 (146) -#define ICU_VEC_NUM_147 (147) -#define ICU_VEC_NUM_148 (148) -#define ICU_VEC_NUM_149 (149) -#define ICU_VEC_NUM_150 (150) -#define ICU_VEC_NUM_151 (151) -#define ICU_VEC_NUM_152 (152) -#define ICU_VEC_NUM_153 (153) -#define ICU_VEC_NUM_154 (154) -#define ICU_VEC_NUM_155 (155) -#define ICU_VEC_NUM_156 (156) -#define ICU_VEC_NUM_157 (157) -#define ICU_VEC_NUM_158 (158) -#define ICU_VEC_NUM_159 (159) -#define ICU_VEC_NUM_160 (160) -#define ICU_VEC_NUM_161 (161) -#define ICU_VEC_NUM_162 (162) -#define ICU_VEC_NUM_163 (163) -#define ICU_VEC_NUM_164 (164) -#define ICU_VEC_NUM_165 (165) -#define ICU_VEC_NUM_166 (166) -#define ICU_VEC_NUM_167 (167) -#define ICU_VEC_NUM_168 (168) -#define ICU_VEC_NUM_169 (169) -#define ICU_VEC_NUM_170 (170) -#define ICU_VEC_NUM_171 (171) -#define ICU_VEC_NUM_172 (172) -#define ICU_VEC_NUM_173 (173) -#define ICU_VEC_NUM_174 (174) -#define ICU_VEC_NUM_175 (175) -#define ICU_VEC_NUM_176 (176) -#define ICU_VEC_NUM_177 (177) -#define ICU_VEC_NUM_178 (178) -#define ICU_VEC_NUM_179 (179) -#define ICU_VEC_NUM_180 (180) -#define ICU_VEC_NUM_181 (181) -#define ICU_VEC_NUM_182 (182) -#define ICU_VEC_NUM_183 (183) -#define ICU_VEC_NUM_184 (184) -#define ICU_VEC_NUM_185 (185) -#define ICU_VEC_NUM_186 (186) -#define ICU_VEC_NUM_187 (187) -#define ICU_VEC_NUM_188 (188) -#define ICU_VEC_NUM_189 (189) -#define ICU_VEC_NUM_190 (190) -#define ICU_VEC_NUM_191 (191) -#define ICU_VEC_NUM_192 (192) -#define ICU_VEC_NUM_193 (193) -#define ICU_VEC_NUM_194 (194) -#define ICU_VEC_NUM_195 (195) -#define ICU_VEC_NUM_196 (196) -#define ICU_VEC_NUM_197 (197) -#define ICU_VEC_NUM_198 (198) -#define ICU_VEC_NUM_199 (199) -#define ICU_VEC_NUM_200 (200) -#define ICU_VEC_NUM_201 (201) -#define ICU_VEC_NUM_202 (202) -#define ICU_VEC_NUM_203 (203) -#define ICU_VEC_NUM_204 (204) -#define ICU_VEC_NUM_205 (205) -#define ICU_VEC_NUM_206 (206) -#define ICU_VEC_NUM_207 (207) -#define ICU_VEC_NUM_208 (208) -#define ICU_VEC_NUM_209 (209) -#define ICU_VEC_NUM_210 (210) -#define ICU_VEC_NUM_211 (211) -#define ICU_VEC_NUM_212 (212) -#define ICU_VEC_NUM_213 (213) -#define ICU_VEC_NUM_214 (214) -#define ICU_VEC_NUM_215 (215) -#define ICU_VEC_NUM_216 (216) -#define ICU_VEC_NUM_217 (217) -#define ICU_VEC_NUM_218 (218) -#define ICU_VEC_NUM_219 (219) -#define ICU_VEC_NUM_220 (220) -#define ICU_VEC_NUM_221 (221) -#define ICU_VEC_NUM_222 (222) -#define ICU_VEC_NUM_223 (223) -#define ICU_VEC_NUM_224 (224) -#define ICU_VEC_NUM_225 (225) -#define ICU_VEC_NUM_226 (226) -#define ICU_VEC_NUM_227 (227) -#define ICU_VEC_NUM_228 (228) -#define ICU_VEC_NUM_229 (229) -#define ICU_VEC_NUM_230 (230) -#define ICU_VEC_NUM_231 (231) -#define ICU_VEC_NUM_232 (232) -#define ICU_VEC_NUM_233 (233) -#define ICU_VEC_NUM_234 (234) -#define ICU_VEC_NUM_235 (235) -#define ICU_VEC_NUM_236 (236) -#define ICU_VEC_NUM_237 (237) -#define ICU_VEC_NUM_238 (238) -#define ICU_VEC_NUM_239 (239) -#define ICU_VEC_NUM_240 (240) -#define ICU_VEC_NUM_241 (241) -#define ICU_VEC_NUM_242 (242) -#define ICU_VEC_NUM_243 (243) -#define ICU_VEC_NUM_246 (246) -#define ICU_VEC_NUM_247 (247) -#define ICU_VEC_NUM_248 (248) -#define ICU_VEC_NUM_249 (249) -#define ICU_VEC_NUM_250 (250) -#define ICU_VEC_NUM_251 (251) -#define ICU_VEC_NUM_252 (252) -#define ICU_VEC_NUM_254 (254) -#define ICU_VEC_NUM_256 (256) -#define ICU_VEC_NUM_257 (257) -#define ICU_VEC_NUM_258 (258) -#define ICU_VEC_NUM_259 (259) -#define ICU_VEC_NUM_260 (260) -#define ICU_VEC_NUM_261 (261) -#define ICU_VEC_NUM_262 (262) -#define ICU_VEC_NUM_263 (263) -#define ICU_VEC_NUM_264 (264) -#define ICU_VEC_NUM_265 (265) -#define ICU_VEC_NUM_266 (266) -#define ICU_VEC_NUM_267 (267) -#define ICU_VEC_NUM_268 (268) -#define ICU_VEC_NUM_269 (269) -#define ICU_VEC_NUM_270 (270) -#define ICU_VEC_NUM_271 (271) -#define ICU_VEC_NUM_272 (272) -#define ICU_VEC_NUM_273 (273) -#define ICU_VEC_NUM_274 (274) -#define ICU_VEC_NUM_275 (275) -#define ICU_VEC_NUM_276 (276) -#define ICU_VEC_NUM_277 (277) -#define ICU_VEC_NUM_278 (278) -#define ICU_VEC_NUM_279 (279) -#define ICU_VEC_NUM_280 (280) -#define ICU_VEC_NUM_281 (281) -#define ICU_VEC_NUM_282 (282) -#define ICU_VEC_NUM_283 (283) -#define ICU_VEC_NUM_284 (284) -#define ICU_VEC_NUM_285 (285) -#define ICU_VEC_NUM_286 (286) -#define ICU_VEC_NUM_287 (287) -#define ICU_VEC_NUM_288 (288) -#define ICU_VEC_NUM_289 (289) -#define ICU_VEC_NUM_290 (290) -#define ICU_VEC_NUM_291 (291) -#define ICU_VEC_NUM_292 (292) -#define ICU_VEC_NUM_293 (293) -#define ICU_VEC_NUM_294 (294) - -#define ICU_TYPE_LEVEL (0) -#define ICU_TYPE_EDGE (1) - -#define ICU_PRIORITY_0 (0) -#define ICU_PRIORITY_1 (1) -#define ICU_PRIORITY_2 (2) -#define ICU_PRIORITY_3 (3) -#define ICU_PRIORITY_4 (4) -#define ICU_PRIORITY_5 (5) -#define ICU_PRIORITY_6 (6) -#define ICU_PRIORITY_7 (7) -#define ICU_PRIORITY_8 (8) -#define ICU_PRIORITY_9 (9) -#define ICU_PRIORITY_10 (10) -#define ICU_PRIORITY_11 (11) -#define ICU_PRIORITY_12 (12) -#define ICU_PRIORITY_13 (13) -#define ICU_PRIORITY_14 (14) -#define ICU_PRIORITY_15 (15) - -#define ICU_IEC_MASK_SET (1) - -#define ICU_PIC_EDGE_CLEAR (1) - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -void R_ICU_Disable(uint32_t vec_num); -void R_ICU_Enable(uint32_t vec_num); -void R_ICU_ExtPinInit(uint16_t pin_num, uint8_t detect, uint32_t dnf_set); -void R_ICU_Regist(uint32_t vec_num, uint32_t type, uint32_t priority, uint32_t isr_addr); -void R_ICU_Disable(uint32_t vec_num); -void R_ICU_Enable(uint32_t vec_num); - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_mpc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_mpc.h deleted file mode 100644 index cd9d589b8..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_mpc.h +++ /dev/null @@ -1,118 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_mpc.h -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for MPC function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : MPC setting API of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -#ifndef _R_MPC_HEADER_ -#define _R_MPC_HEADER_ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define MPC_IRQ_DISABLE (0) -#define MPC_IRQ_ENABLE (1) - -#define MPC_PSEL_PT6_A21 (0x23) -#define MPC_PSEL_PT7_A22 (0x23) -#define MPC_PSEL_PK2_A23 (0x23) -#define MPC_PSEL_PK3_A24 (0x23) -#define MPC_PSEL_P97_A25 (0x23) -#define MPC_PSEL_P36_WE0_DQMLL (0x22) -#define MPC_PSEL_P37_WE1_DQMLU (0x22) -#define MPC_PSEL_PD1_CS1 (0x23) -#define MPC_PSEL_P45_CS2 (0x22) -#define MPC_PSEL_PT4_CS3 (0x23) -#define MPC_PSEL_P90_RAS (0x23) -#define MPC_PSEL_PK0_CAS (0x23) -#define MPC_PSEL_P24_RD_WR (0x22) -#define MPC_PSEL_P46_CKE (0x22) -#define MPC_PSEL_P10_CKIO (0x22) -#define MPC_PSEL_P23_A0 (0x22) -#define MPC_PSEL_PG0_A1 (0x22) -#define MPC_PSEL_PG1_A2 (0x22) -#define MPC_PSEL_PG2_A3 (0x22) -#define MPC_PSEL_PG3_A4 (0x22) -#define MPC_PSEL_PG4_A5 (0x22) -#define MPC_PSEL_PG5_A6 (0x22) -#define MPC_PSEL_PG6_A7 (0x22) -#define MPC_PSEL_PG7_A8 (0x22) -#define MPC_PSEL_PH0_A9 (0x22) -#define MPC_PSEL_PH1_A10 (0x22) -#define MPC_PSEL_PH2_A11 (0x22) -#define MPC_PSEL_PH3_A12 (0x22) -#define MPC_PSEL_PH4_A13 (0x22) -#define MPC_PSEL_PH5_A14 (0x22) -#define MPC_PSEL_PH6_A15 (0x22) -#define MPC_PSEL_PH7_A16 (0x22) -#define MPC_PSEL_P20_A17 (0x22) -#define MPC_PSEL_P25_A18 (0x22) -#define MPC_PSEL_P26_A19 (0x22) -#define MPC_PSEL_P27_A20 (0x22) -#define MPC_PSEL_P00_D0 (0x22) -#define MPC_PSEL_P01_D1 (0x22) -#define MPC_PSEL_P02_D2 (0x22) -#define MPC_PSEL_P03_D3 (0x22) -#define MPC_PSEL_P04_D4 (0x22) -#define MPC_PSEL_P05_D5 (0x22) -#define MPC_PSEL_P06_D6 (0x22) -#define MPC_PSEL_P07_D7 (0x22) -#define MPC_PSEL_PE0_D8 (0x22) -#define MPC_PSEL_PE1_D9 (0x22) -#define MPC_PSEL_PE2_D10 (0x22) -#define MPC_PSEL_PE3_D11 (0x22) -#define MPC_PSEL_PE4_D12 (0x22) -#define MPC_PSEL_PE5_D13 (0x22) -#define MPC_PSEL_PE6_D14 (0x22) -#define MPC_PSEL_PE7_D15 (0x22) -#define MPC_PSEL_P22_RD (0x22) -#define MPC_PSEL_P21_CS0 (0x22) - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -void R_MPC_WriteEnable(void); -void R_MPC_WriteDisable(void); - - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_port.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_port.h deleted file mode 100644 index 0142e5309..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_port.h +++ /dev/null @@ -1,76 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_port.h -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for PORT function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : PORT setting API of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -#ifndef _R_PORT_HEADER_ -#define _R_PORT_HEADER_ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define PORT_DIRECTION_HIZ (0) -#define PORT_DIRECTION_INPUT (2) -#define PORT_DIRECTION_OUTPUT (3) - -#define PORT_OUTPUT_LOW (0) -#define PORT_OUTPUT_HIGH (1) - -#define PORT_MODE_GENERAL (0) -#define PORT_MODE_PERIPHERAL (1) - -#define PORT_PULL_UPDOWN_DISABLE (0) -#define PORT_PULL_DOWN (1) -#define PORT_PULL_UP (2) - -#define PORT_P10_NORMAL_DRIVE (0) -#define PORT_P10_HIGH_DRIVE (1) - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ram_init.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ram_init.h deleted file mode 100644 index abcf59702..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_ram_init.h +++ /dev/null @@ -1,64 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_ram.h -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for internal extended RAM function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : Internal extended RAM setting API of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -#ifndef _R_RAM_HEADER_ -#define _R_RAM_HEADER_ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -void R_RAM_Init(void); -void R_RAM_ECC_Enable(void); -void R_RAM_WriteEnable(void); -void R_RAM_WriteDisable(void); - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_reset.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_reset.h deleted file mode 100644 index 06f6e3438..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_reset.h +++ /dev/null @@ -1,64 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_reset.h -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for reset function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : Reset function API of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -#ifndef _R_RESET_HEADER_ -#define _R_RESET_HEADER_ - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define RST_SOURCE_RES (0x00000002) -#define RST_SOURCE_ECM (0x00000004) -#define RST_SOURCE_SWR1 (0x00000008) - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ -void r_rst_write_enable(void); -void r_rst_write_disable(void); - -#endif - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_system.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_system.h deleted file mode 100644 index 9278ef210..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_system.h +++ /dev/null @@ -1,116 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_system.h -* Version : 0.1 -* Device : R7S9100xx -* Abstract : Definition for System -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : Define the system settings ans value. -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -#ifndef _R_SYSTEM_HEADER_ -#define _R_SYSTEM_HEADER_ - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - -#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPCRA0 -#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPCRA1 -#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPCRA2 -#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPCRA3 -#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPCRA4 -#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPCRA5 -#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPCRA6 -#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPCRA7 -#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPCRA8 -#define MSTP_GPTA SYSTEM.MSTPCRA.BIT.MSTPCRA9 -#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPCRA11 - -#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPCRB1 -#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPCRB2 -#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPCRB3 -#define MSTP_SCIFA4 SYSTEM.MSTPCRB.BIT.MSTPCRB5 -#define MSTP_SCIFA3 SYSTEM.MSTPCRB.BIT.MSTPCRB6 -#define MSTP_SCIFA2 SYSTEM.MSTPCRB.BIT.MSTPCRB7 -#define MSTP_SCIFA1 SYSTEM.MSTPCRB.BIT.MSTPCRB8 -#define MSTP_SCIFA0 SYSTEM.MSTPCRB.BIT.MSTPCRB9 -#define MSTP_RSPI3 SYSTEM.MSTPCRB.BIT.MSTPCRB10 -#define MSTP_RSPI2 SYSTEM.MSTPCRB.BIT.MSTPCRB11 -#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPCRB12 -#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPCRB13 -#define MSTP_ETHERSW SYSTEM.MSTPCRB.BIT.MSTPCRB14 -#define MSTP_ECATC SYSTEM.MSTPCRB.BIT.MSTPCRB15 -#define MSTP_EMDIO SYSTEM.MSTPCRB.BIT.MSTPCRB16 -#define MSTP_ERMII SYSTEM.MSTPCRB.BIT.MSTPCRB17 -#define MSTP_HWRTOS SYSTEM.MSTPCRB.BIT.MSTPCRB18 -#define MSTP_CLKOUT25M SYSTEM.MSTPCRB.BIT.MSTPCRB19 - -#define MSTP_USB SYSTEM.MSTPCRC.BIT.MSTPCRC1 -#define MSTP_DSMIF SYSTEM.MSTPCRC.BIT.MSTPCRC2 -#define MSTP_TEMPS SYSTEM.MSTPCRC.BIT.MSTPCRC3 -#define MSTP_S12ADC1 SYSTEM.MSTPCRC.BIT.MSTPCRC4 -#define MSTP_S12ADC0 SYSTEM.MSTPCRC.BIT.MSTPCRC5 -#define MSTP_ELC SYSTEM.MSTPCRC.BIT.MSTPCRC6 -#define MSTP_BSC SYSTEM.MSTPCRC.BIT.MSTPCRC7 -#define MSTP_CKIO SYSTEM.MSTPCRC.BIT.MSTPCRC8 -#define MSTP_SPIBSC SYSTEM.MSTPCRC.BIT.MSTPCRC9 -#define MSTP_DOC SYSTEM.MSTPCRC.BIT.MSTPCRC10 -#define MSTP_CRC SYSTEM.MSTPCRC.BIT.MSTPCRC11 -#define MSTP_CLMA2 SYSTEM.MSTPCRC.BIT.MSTPCRC12 -#define MSTP_CLMA1 SYSTEM.MSTPCRC.BIT.MSTPCRC13 -#define MSTP_CLMA0 SYSTEM.MSTPCRC.BIT.MSTPCRC14 - -#define MSTP_SSI SYSTEM.MSTPCRD.BIT.MSTPCRD2 - -#define MSTP_DMAC1 SYSTEM.MSTPCRE.BIT.MSTPCRE4 -#define MSTP_DMAC0 SYSTEM.MSTPCRE.BIT.MSTPCRE5 - -#define MSTP_CORESIGHT SYSTEM.MSTPCRF.BIT.MSTPCRF0 - -#define __MSTP( x ) MSTP ## x -#define _MSTP( x ) __MSTP( x ) -#define MSTP( x ) _MSTP( _ ## x ) - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -#endif // End _R_SYSTEM_HEADER_ - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_typedefs.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_typedefs.h deleted file mode 100644 index a4a339423..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/inc/r_typedefs.h +++ /dev/null @@ -1,79 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* File Name : r_typedefs.h -* Device(s) : RZ/A1H (R7S910018) -* Tool-Chain : GNUARM-NONEv14.02-EABI -* H/W Platform : RSK+T1 CPU Board -* Description : basic type definition -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* History : DD.MM.YYYY Version Description -* : 21.10.2014 1.00 -***********************************************************************************************************************/ - - -/*********************************************************************************************************************** -Includes , "Project Includes" -***********************************************************************************************************************/ -#include -/* Multiple inclusion prevention macro */ -#ifndef R_TYPEDEFS_H -#define R_TYPEDEFS_H - - -/* in case has defined it. */ -#ifndef NULL -#define NULL (0) -#endif - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -#if !defined(__bool_true_false_are_defined) && !defined(__cplusplus) - -#define FALSE (0) -#define TRUE (1) - -#endif - -/* These two macros are used to suppress warnings generated by unused variables. - Writing to some registers require a read instruction following the write. - A dummy variable is declared and used to read the register written to. */ -#define UNUSED_PARAM(param) ((void)(param)) -#define UNUSED_VARIABLE(param) ((void)(param)) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ -typedef char char_t; -typedef unsigned int bool_t; -typedef int int_t; -typedef float float32_t; -typedef double float64_t; -typedef long double float128_t; - -/* R_TYPEDEFS_H */ -#endif - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/RZ_T1_init.icf b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/RZ_T1_init.icf deleted file mode 100644 index 2e86388b6..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/RZ_T1_init.icf +++ /dev/null @@ -1,163 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x40020040; -define symbol __ICFEDIT_region_ROM_end__ = 0x4008FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x00070000; -define symbol __ICFEDIT_region_RAM_end__ = 0x0007FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x2000; -define symbol __ICFEDIT_size_svcstack__ = 0x200; -define symbol __ICFEDIT_size_irqstack__ = 0x100; -define symbol __ICFEDIT_size_fiqstack__ = 0x100; -define symbol __ICFEDIT_size_undstack__ = 0x100; -define symbol __ICFEDIT_size_abtstack__ = 0x100; -define symbol __ICFEDIT_size_heap__ = 0x1000; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define symbol __region_USER_PRG_start__ = 0x00000040; -define symbol __region_USER_PRG_end__ = 0x0006FFFF; - -define symbol __region_D_LDR_DATA_start__ = 0x00800000; -define symbol __region_D_LDR_DATA_end__ = 0x00801FFF; -define symbol __region_D_LDR_PRG_start__ = 0x00802000; -define symbol __region_D_LDR_PRG_end__ = 0x00807FFF; - -define symbol __region_D_LDR_M3PRG_start__ = 0x04000000; -define symbol __region_D_LDR_M3PRG_end__ = 0x0407FFFF; - -define symbol __region_S_LDR_M3PRG_start__ = 0x00050000; -define symbol __region_S_LDR_M3PRG_end__ = 0x0006FFFF; - -define symbol __region_EXT_RAM1_start__ = 0x22000000; -define symbol __region_EXT_RAM1_end__ = 0x2207FFFF; -define symbol __region_EXT_RAM2_start__ = 0x24000000; -define symbol __region_EXT_RAM2_end__ = 0x2407FFFF; -define symbol __region_SPIBSC_start__ = 0x30000000; -define symbol __region_SPIBSC_end__ = 0x33FFFFFF; - -define symbol __region_CS0_start__ = 0x40000000; -define symbol __region_CS0_end__ = 0x43FFFFFF; -define symbol __region_CS1_start__ = 0x44000000; -define symbol __region_CS1_end__ = 0x47FFFFFF; -define symbol __region_CS2_start__ = 0x48000000; -define symbol __region_CS2_end__ = 0x4BFFFFFF; -define symbol __region_CS3_start__ = 0x4C000000; -define symbol __region_CS3_end__ = 0x4FFFFFFF; -define symbol __region_CS4_start__ = 0x50000000; -define symbol __region_CS4_end__ = 0x53FFFFFF; -define symbol __region_CS5_start__ = 0x54000000; -define symbol __region_CS5_end__ = 0x57FFFFFF; - -define region USER_PRG_region = mem:[from __region_USER_PRG_start__ to __region_USER_PRG_end__]; -define region D_LDR_DATA_region = mem:[from __region_D_LDR_DATA_start__ to __region_D_LDR_DATA_end__]; -define region D_LDR_PRG_region = mem:[from __region_D_LDR_PRG_start__ to __region_D_LDR_PRG_end__]; - -define region D_LDR_M3PRG_region = mem:[from __region_D_LDR_M3PRG_start__ to __region_D_LDR_M3PRG_end__]; -define region S_LDR_M3PRG_region = mem:[from __region_S_LDR_M3PRG_start__ to __region_S_LDR_M3PRG_end__]; - -define region EXT_RAM1_region = mem:[from __region_EXT_RAM1_start__ to __region_EXT_RAM1_end__]; -define region EXT_RAM2_region = mem:[from __region_EXT_RAM2_start__ to __region_EXT_RAM2_end__]; -define region SPIBSC_region = mem:[from __region_SPIBSC_start__ to __region_SPIBSC_end__]; -define region CS0_region = mem:[from __region_CS0_start__ to __region_CS0_end__]; -define region CS1_region = mem:[from __region_CS1_start__ to __region_CS1_end__]; -define region CS2_region = mem:[from __region_CS2_start__ to __region_CS2_end__]; -define region CS3_region = mem:[from __region_CS3_start__ to __region_CS3_end__]; -define region CS4_region = mem:[from __region_CS4_start__ to __region_CS4_end__]; -define region CS5_region = mem:[from __region_CS5_start__ to __region_CS5_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; -define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; -define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; -define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; -define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - - -define block LDR_PRG_RBLOCK with fixed order - { ro code object loader_init.o, - ro code object loader_init2.o, - ro code object r_atcm_init.o, - ro code object r_cpg.o, - ro code object r_ram_init.o, - ro code object r_mpc.o, - ro code object r_reset.o, - ro code object data_init.o, - ro code object copy_init3.o }; -define block LDR_DATA_ZBLOCK { section .bss object loader_init.o, - section .bss object loader_init2.o, - section .bss object r_atcm_init.o, - section .bss object r_cpg.o, - section .bss object r_ram_init.o, - section .bss object r_mpc.o, - section .bss object r_reset.o, - section .bss object data_init.o, - section .bss object copy_init3.o }; -define block LDR_DATA_RBLOCK { section .data_init object loader_init.o, - section .data_init object loader_init2.o, - section .data_init object r_atcm_init.o, - section .data_init object r_cpg.o, - section .data_init object r_ram_init.o, - section .data_init object r_mpc.o, - section .data_init object r_reset.o, - section .data_init object data_init.o, - section .data_init object copy_init3.o }; -define block LDR_DATA_WBLOCK { section .data object loader_init.o, - section .data object loader_init2.o, - section .data object r_atcm_init.o, - section .data object r_cpg.o, - section .data object r_ram_init.o, - section .data object r_mpc.o, - section .data object r_reset.o, - section .data object data_init.o, - section .data object copy_init3.o }; -define block VECTOR_RBLOCK { ro code object vector.o }; -define block USER_PRG_RBLOCK { ro code }; -define block USER_DATA_ZBLOCK { section .bss }; -define block USER_DATA_RBLOCK { section .data_init }; -define block USER_DATA_WBLOCK { section .data }; - -define block M3_PRG_RBLOCK { section __M3prg_init }; -define block M3_PRG_WBLOCK { section __M3prg }; - -initialize by copy { readwrite }; - -do not initialize { section .noinit, section .bss }; - -initialize manually { section __M3prg }; - -place at address mem:__ICFEDIT_intvec_start__ { block VECTOR_RBLOCK }; - -place in USER_PRG_region { block USER_PRG_RBLOCK, - block USER_DATA_RBLOCK, - readonly }; -place in RAM_region { readwrite }; -place in RAM_region { block USER_DATA_WBLOCK, - block USER_DATA_ZBLOCK, - block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, - block UND_STACK, block ABT_STACK, block HEAP }; -place in D_LDR_DATA_region { block LDR_DATA_WBLOCK, block LDR_DATA_ZBLOCK }; -place in D_LDR_PRG_region { block LDR_PRG_RBLOCK, - block LDR_DATA_RBLOCK }; - -place in S_LDR_M3PRG_region { block M3_PRG_RBLOCK }; -place in D_LDR_M3PRG_region { block M3_PRG_WBLOCK }; - -place in EXT_RAM1_region {}; -place in EXT_RAM2_region {}; -place in SPIBSC_region {}; -place in CS0_region {}; -place in CS1_region {}; -place in CS2_region {}; -place in CS3_region {}; -place in CS4_region {}; -place in CS5_region {}; diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/exit.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/exit.c deleted file mode 100644 index 19b107e4b..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/exit.c +++ /dev/null @@ -1,84 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : exit.c -* Version : 0.1 -* Device : R7S9100xx -* Abstract : exit program -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : exit sequence from main function -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - -/******************************************************************************* -Private variables and functions -*******************************************************************************/ - -/******************************************************************************* -* Outline : exit processing -* Function Name: __exit -* Description : exit sequence from main function. -* Arguments : code -* The return value of main function. -* Return Value : none -*******************************************************************************/ -void __exit(int code) -{ - - while (1) - { - /* Please describe the exit sequence */ - } - -} -/******************************************************************************* - End of function __exit -*******************************************************************************/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init.asm deleted file mode 100644 index fe8b0fe71..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init.asm +++ /dev/null @@ -1,371 +0,0 @@ -;******************************************************************************* -; DISCLAIMER -; This software is supplied by Renesas Electronics Corporation and is only -; intended for use with Renesas products. No other uses are authorized. This -; software is owned by Renesas Electronics Corporation and is protected under -; all applicable laws, including copyright laws. -; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -; LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -; AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -; TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -; ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -; FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -; ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -; Renesas reserves the right, without notice, to make changes to this software -; and to discontinue the availability of this software. By using this software, -; you agree to the additional terms and conditions found by accessing the -; following link: -; http://www.renesas.com/disclaimer -; -; Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -;****************************************************************************** -;******************************************************************************* -; System Name : RZ/T1 Init program -; File Name : loader_init.asm -; Version : 0.1 -; Device : R7S9100xx -; Abstract : Loader program 1 -; Tool-Chain : IAR Embedded Workbench Ver.7.20 -; OS : not use -; H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -; Description : Description interrupt service routine of RZ/T1 -; Limitation : none -;****************************************************************************** -;******************************************************************************* -; History : DD.MM.YYYY Version Description -; : First Release -;****************************************************************************** - - SECTION IRQ_STACK:DATA:NOROOT(3) - SECTION FIQ_STACK:DATA:NOROOT(3) - SECTION SVC_STACK:DATA:NOROOT(3) - SECTION ABT_STACK:DATA:NOROOT(3) - SECTION UND_STACK:DATA:NOROOT(3) - SECTION CSTACK:DATA:NOROOT(3) - - SECTION LDR_DATA_RBLOCK:DATA:ROOT(2) - SECTION LDR_DATA_WBLOCK:DATA:ROOT(2) - - SECTION M3_PRG_RBLOCK:DATA:ROOT(2) - SECTION M3_PRG_WBLOCK:DATA:ROOT(2) - -; This program is allocated to section "d_ldr_prg" - SECTION d_ldr_prg:CODE:ROOT(2) - - ARM - - PUBLIC loader_init1 - PUBLIC set_low_vec - PUBLIC cache_init - PUBLIC mpu_init - IMPORT loader_init2 - - -;*********************************************************************** -; Function Name : loader_init1 -; Description : Initialize sysytem by loader program -; Arguments : none -; Return Value : none -;*********************************************************************** -loader_init1: - -stack_init: - ; Stack setting - cps #17 ; FIQ mode - ldr sp, =SFE(FIQ_STACK) - cps #18 ; IRQ mode - ldr sp, =SFE(IRQ_STACK) - cps #23 ; Abort mode - ldr sp, =SFE(ABT_STACK) - cps #27 ; Undef mode - ldr sp, =SFE(UND_STACK) - cps #31 ; System mode - ldr sp, =SFE(CSTACK) - cps #19 ; SVC mode - ldr sp, =SFE(SVC_STACK) - -vfp_init: - ; Initialize VFP setting - mrc p15, #0, r0, c1, c0, #2 ; Enables cp10 and cp11 accessing - orr r0, r0, #0xF00000 - mcr p15, #0, r0, c1, c0, #2 - isb ; Ensuring Context-changing - - mov r0, #0x40000000 ; Enables VFP operation - vmsr fpexc, r0 - -data_init: - ; Initialize variables has initialized value of loader_init2. - ; Variables has no initialized value already be initialized to zero - ; in boot sequence(Clear ATCM and BTCM). - ldr r0, =SFB(LDR_DATA_RBLOCK) - ldr r1, =SFB(LDR_DATA_WBLOCK) - ldr r2, =SIZEOF(LDR_DATA_WBLOCK) - cmp r2, #0 -#ifdef DUAL_CORE - beq m3_init -#else - beq jump_loader_init2 -#endif - -copy_to_LDR_DATA: - ldrb r3, [r0], #1 - strb r3, [r1], #1 - subs r2, r2, #1 - bne copy_to_LDR_DATA - dsb ; Ensuring data-changing - -#ifdef DUAL_CORE - -m3_init: - ; Initialize image for Cortex-M3 core - ldr r0, =SFB(M3_PRG_RBLOCK) - ldr r1, =SFB(M3_PRG_WBLOCK) - ldr r2, =SIZEOF(M3_PRG_WBLOCK) - cmp r2, #0 - beq jump_loader_init2 - -copy_to_M3_PRG: - ldrb r3, [r0], #1 - strb r3, [r1], #1 - subs r2, r2, #1 - bne copy_to_M3_PRG - dsb ; Ensuring data-changing - -#endif - - ; Jump to loader_init2 -jump_loader_init2: - ldr r0, =loader_init2 - bx r0 - -;*********************************************************************** -; Function Name : cache_init -; Description : Initialize I1, D1 cache and MPU settings -; Arguments : none -; Return Value : none -;*********************************************************************** - -;******************************************************************************* -; Macro definitions -;******************************************************************************* - -SCTLR_BR: dcd 0x00020000 -SCTLR_M: dcd 0x00000001 -SCTLR_I_C: dcd 0x00001004 - -DRBAR_REGION_0: dcd 0x04000000 ; Base address = 0400_0000h -DRACR_REGION_0: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share -DRSR_REGION_0: dcd 0x00000025 ; Size 512KB, MPU enable - -DRBAR_REGION_1: dcd 0x10000000 ; Base address = 1000_0000h -DRACR_REGION_1: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share -DRSR_REGION_1: dcd 0x00000033 ; Size 64MB, MPU enable - -DRBAR_REGION_2: dcd 0x20000000 ; Base address = 2000_0000h -DRACR_REGION_2: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share -DRSR_REGION_2: dcd 0x00000025 ; Size 512KB, MPU enable - -DRBAR_REGION_3: dcd 0x22000000 ; Base address = 2200_0000h -DRACR_REGION_3: dcd 0x00000307 ; R/W(full), Normal, Write-back no allocate, share -DRSR_REGION_3: dcd 0x00000033 ; Size 64MB, MPU enable - -DRBAR_REGION_4: dcd 0x30000000 ; Base address = 3000_0000h -DRACR_REGION_4: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share -DRSR_REGION_4: dcd 0x00000033 ; Size 64MB, MPU enable - -DRBAR_REGION_5: dcd 0x40000000 ; Base address = 4000_0000h -DRACR_REGION_5: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share -DRSR_REGION_5: dcd 0x00000035 ; Size 128MB, MPU enable - -DRBAR_REGION_6: dcd 0x48000000 ; Base address = 4800_0000h -DRACR_REGION_6: dcd 0x0000030F ; R/W(full), Normal, Write-back write allocate, share -DRSR_REGION_6: dcd 0x00000035 ; Size 128MB, MPU enable - -DRBAR_REGION_7: dcd 0x50000000 ; Base address = 5000_0000h -DRACR_REGION_7: dcd 0x00001305 ; R/W(full), XN, Device, share -DRSR_REGION_7: dcd 0x00000035 ; Size 128MB, MPU enable - -DRBAR_REGION_8: dcd 0x60000000 ; Base address = 6000_0000h -DRACR_REGION_8: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share -DRSR_REGION_8: dcd 0x00000035 ; Size 128MB, MPU enable - -DRBAR_REGION_9: dcd 0x68000000 ; Base address = 6800_0000h -DRACR_REGION_9: dcd 0x0000030C ; R/W(full), Normal, Non-cache, share -DRSR_REGION_9: dcd 0x00000035 ; Size 128MB, MPU enable - -DRBAR_REGION_10: dcd 0x70000000 ; Base address = 7000_0000h -DRACR_REGION_10: dcd 0x00001305 ; R/W(full), XN, Device, share -DRSR_REGION_10: dcd 0x00000035 ; Size 128MB, MPU enable - -DRBAR_REGION_11: dcd 0x80000000 ; Base address = 8000_0000h -DRACR_REGION_11: dcd 0x00001305 ; R/W(full), XN, Device, share -DRSR_REGION_11: dcd 0x0000003D ; Size 2GB, MPU enable - -cache_init: - push {lr} - -cache_invalidate: - ; Invalidate the I1, D1 cache - mov r0, #0 - mcr p15, #0, r0, c7, c5, #0 ; Invalidate all Instruction Caches (Write-value is Ignored) - isb ; Ensuring Context-changing - mcr p15, #0, r0, c15, c5, #0 ; Invalidate all Data Caches (Write-value is Ignored) - isb ; Ensuring Context-changing - - ; Adopt default memory map as background map. - ldr r0, SCTLR_BR ; Set SCTLR.BR bit to 1 - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, r0 - dsb - mcr p15, 0, r1, c1, c0, 0 - isb ; Ensuring Context-changing - - ; Initialize MPU settings (region 0 to 11) - ; Define region 0 - mov r0, #0 - ldr r1, DRBAR_REGION_0 - ldr r2, DRACR_REGION_0 - ldr r3, DRSR_REGION_0 - bl mpu_init - - ; Define region 1 - mov r0, #1 - ldr r1, DRBAR_REGION_1 - ldr r2, DRACR_REGION_1 - ldr r3, DRSR_REGION_1 - bl mpu_init - - ; Define region 2 - mov r0, #2 - ldr r1, DRBAR_REGION_2 - ldr r2, DRACR_REGION_2 - ldr r3, DRSR_REGION_2 - bl mpu_init - - ; Define region 3 - mov r0, #3 - ldr r1, DRBAR_REGION_3 - ldr r2, DRACR_REGION_3 - ldr r3, DRSR_REGION_3 - bl mpu_init - - ; Define region 4 - mov r0, #4 - ldr r1, DRBAR_REGION_4 - ldr r2, DRACR_REGION_4 - ldr r3, DRSR_REGION_4 - bl mpu_init - - ; Define region 5 - mov r0, #5 - ldr r1, DRBAR_REGION_5 - ldr r2, DRACR_REGION_5 - ldr r3, DRSR_REGION_5 - bl mpu_init - - ; Define region 6 - mov r0, #6 - ldr r1, DRBAR_REGION_6 - ldr r2, DRACR_REGION_6 - ldr r3, DRSR_REGION_6 - bl mpu_init - - ; Define region 7 - mov r0, #7 - ldr r1, DRBAR_REGION_7 - ldr r2, DRACR_REGION_7 - ldr r3, DRSR_REGION_7 - bl mpu_init - - ; Define region 8 - mov r0, #8 - ldr r1, DRBAR_REGION_8 - ldr r2, DRACR_REGION_8 - ldr r3, DRSR_REGION_8 - bl mpu_init - - ; Define region 9 - mov r0, #9 - ldr r1, DRBAR_REGION_9 - ldr r2, DRACR_REGION_9 - ldr r3, DRSR_REGION_9 - bl mpu_init - - ; Define region 10 - mov r0, #10 - ldr r1, DRBAR_REGION_10 - ldr r2, DRACR_REGION_10 - ldr r3, DRSR_REGION_10 - bl mpu_init - - ; Define region 11 - mov r0, #11 - ldr r1, DRBAR_REGION_11 - ldr r2, DRACR_REGION_11 - ldr r3, DRSR_REGION_11 - bl mpu_init - - ; Enables MPU operation - ldr r0, SCTLR_M ; Set SCTLR.M bit to 1 - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, r0 - dsb - mcr p15, 0, r1, c1, c0, 0 - isb ; Ensuring Context-changing - - ; Enables I1,D1 cache operation - ldr r0, SCTLR_I_C ; Set SCTLR.I and C bit to 1 - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, r0 - dsb - mcr p15, 0, r1, c1, c0, 0 - isb ; Ensuring Context-changing - - pop {pc} - bx lr - -;*********************************************************************** -; Function Name : mpu_init -; Description : Initialize MPU settings -; Arguments : none -; Return Value : none -;*********************************************************************** -mpu_init: - ; RGNR(MPU Memory Region Number Register) - mcr p15, #0, r0, c6, c2, #0 - isb ; Ensuring Context-changing - - ; DRBAR(Data Region Base Address Register) - mcr p15, #0, r1, c6, c1, #0 - isb ; Ensuring Context-changing - - ; DRACR(Data Region Access Control Register) - mcr p15, #0, r2, c6, c1, #4 - isb ; Ensuring Context-changing - - ; DRSR(Data Region Size and Enable Register) - mcr p15, #0, r3, c6, c1, #2 - isb ; Ensuring Context-changing - - bx lr - - -;*********************************************************************** -; Function Name : set_low_vec -; Description : Initialize sysytem by loader program -; Arguments : none -; Return Value : none -;*********************************************************************** -set_low_vec: - mrc p15, 0, r0, c1, c0, 0 ; Set SCTLR.V bit to 1 (low-vector) - and r0, r0, #0xFFFFDFFF - mcr p15, 0, r0, c1, c0, 0 - isb ; Ensuring Context-changing - - bx lr - - END -; End of File diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init2.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init2.c deleted file mode 100644 index 6593ad61f..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/loader_init2.c +++ /dev/null @@ -1,233 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : loader_init2.c -* Version : 0.1 -* Device : R7S9100xx -* Abstract : Loader program 2 -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : Initialize the peripheral settings of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ -#ifdef __ICCARM__ - -#pragma section="VECTOR_RBLOCK" -#pragma section="VECTOR_WBLOCK" -#pragma section="USER_PRG_RBLOCK" -#pragma section="USER_PRG_WBLOCK" -#pragma section="USER_DATA_RBLOCK" -#pragma section="USER_DATA_WBLOCK" - -#endif // __ICCARM__ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include -#include -#include "r_system.h" -#include "r_reset.h" -#include "r_cpg.h" -#include "r_atcm_init.h" -#include "r_port.h" -#include "r_mpc.h" -#include "r_ecm.h" - - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ -extern int _main(void); -extern void bus_init(void); -extern void set_low_vec(void); -extern void cache_init(void); -extern void __iar_data_init3(void); - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - -/******************************************************************************* -Private variables and functions -*******************************************************************************/ -void loader_init2(void); -void reset_check(void); -void cpg_init(void); - -/******************************************************************************* -* Function Name : loader_init2 -* Description : Initialize sysytem by loader program 2 -* Arguments : none -* Return Value : none -*******************************************************************************/ -void loader_init2(void) -{ - /* Check the reset source */ - reset_check(); - - /* Set CPU clock and LOCO clock */ - cpg_init(); - - /* Set ATCM access wait to 1-wait with optimization */ - /* Caution: ATCM_WAIT_0 is permitted if CPUCLK = 150MHz or 300MHz. - ATCM_WAIT_1_OPT is permitted if CPUCLK = 450MHz or 600MHz.*/ - R_ATCM_WaitSet(ATCM_WAIT_1_OPT); - - /* Copy the variable data */ - __iar_data_init3(); - - /* Initialize I1, D1 Cache and MPU setting */ - cache_init(); - - /* Set RZ/T1 to Low-vector (SCTLR.V = 0) */ - set_low_vec(); - - /* Jump to _main() */ - _main(); - -} - -/******************************************************************************* - End of function loader_init2 -*******************************************************************************/ - -/******************************************************************************* -* Function Name : reset_check -* Description : Check the reset source and execute the each sequence. -* When error source number 35 is generated, set P77 pin to High. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void reset_check(void) -{ - volatile uint8_t result; - volatile uint32_t dummy; - - /* Check the reset status flag and execute the each sequence */ - if (RST_SOURCE_ECM == SYSTEM.RSTSR0.LONG) // ECM reset is generated - { - /* Clear reset status flag */ - r_rst_write_enable(); // Enable writing to the RSTSR0 register - SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag - r_rst_write_disable(); // Disable writing to the RSTSR0 register - - /* Please coding the User program */ - - } - else if (RST_SOURCE_SWR1 == SYSTEM.RSTSR0.LONG) // Software reset 1 is generated - { - /* Clear reset status flag */ - r_rst_write_enable(); // Enable writing to the RSTSR0 register - SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag - r_rst_write_disable(); // Disable writing to the RSTSR0 register - - /* Please coding the User program */ - - } - else if (RST_SOURCE_RES == SYSTEM.RSTSR0.LONG) // RES# pin reset is generated - { - /* Clear reset status flag */ - r_rst_write_enable(); // Enable writing to the RSTSR0 register - SYSTEM.RSTSR0.LONG = 0x00000000; // Clear reset factor flag - r_rst_write_disable(); // Disable writing to the RSTSR0 register - - /* Please coding the User program */ - - } - else // Any reset is not generated - { - /* Please coding the User program */ - } - -} - -/******************************************************************************* - End of function reset_check -*******************************************************************************/ - -/******************************************************************************* -* Function Name : cpg_init -* Description : Set CPU clock and LOCO clock by CPG function -* Arguments : none -* Return Value : none -*******************************************************************************/ -void cpg_init(void) -{ - volatile uint32_t dummy; - - /* Enables writing to the registers related to CPG function */ - R_CPG_WriteEnable(); - - /* Enables LOCO clock operation */ - SYSTEM.LOCOCR.BIT.LCSTP = CPG_LOCO_ENABLE; - - /* Set CPUCLK to 450MHz, and dummy read at three times */ - SYSTEM.PLL1CR.LONG = CPG_CPUCLK_450_MHz; - dummy = SYSTEM.PLL1CR.LONG; - dummy = SYSTEM.PLL1CR.LONG; - dummy = SYSTEM.PLL1CR.LONG; - - /* Enables PLL1 operation */ - SYSTEM.PLL1CR2.LONG = CPG_PLL1_ON; - - /* Disables writing to the registers related to CPG function */ - R_CPG_WriteDisable(); - - /* Wait about 100us for PLL1 (and LOCO) stabilization */ - R_CPG_PLL_Wait(); - - /* Enables writing to the registers related to CPG function */ - R_CPG_WriteEnable(); - - /* Selects the PLL1 as clock source */ - SYSTEM.SCKCR2.LONG = CPG_SELECT_PLL1; - - /* Disables writing to the registers related to CPG function */ - R_CPG_WriteDisable(); - -} - -/******************************************************************************* - End of function cpg_init -*******************************************************************************/ - - -/* End of File */ - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_atcm_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_atcm_init.c deleted file mode 100644 index e15bf7bf8..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_atcm_init.c +++ /dev/null @@ -1,108 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_atcm_init.c -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for ATCM function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : ATCM access wait setting API of RZ/T1 -* Limitation : This wait setting could not be executed in ATCM program area. -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include -#include -#include "r_system.h" -#include "r_atcm_init.h" - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define ATCM_WRITE_ENABLE (0x0000A508) -#define ATCM_WRITE_DISABLE (0x0000A500) - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - - -/******************************************************************************* -Private variables and functions -*******************************************************************************/ - - - -/******************************************************************************* -* Function Name : R_ATCM_WaitSet -* Description : Sets ATCM access wait. -* Arguments : atcm_wait -* Wait settings for ATCM access -* Return Value : none -*******************************************************************************/ -void R_ATCM_WaitSet(uint32_t atcm_wait) -{ - volatile uint32_t dummy; - - /* Enables writing to the ATCM register */ - SYSTEM.PRCR.LONG = ATCM_WRITE_ENABLE; - dummy = SYSTEM.PRCR.LONG; - - /* Sets ATCM access wait to atcm_wait value */ - SYSTEM.SYTATCMWAIT.LONG = atcm_wait; - - /* Disables writing to the ATCM register */ - SYSTEM.PRCR.LONG = ATCM_WRITE_DISABLE; - dummy = SYSTEM.PRCR.LONG; - -} - -/******************************************************************************* - End of function R_ATCM_WaitSet -*******************************************************************************/ - -/* End of File */ - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_cpg.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_cpg.c deleted file mode 100644 index 17775f8bd..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_cpg.c +++ /dev/null @@ -1,162 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_cpg.c -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for CPG function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : CPG setting API of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include -#include -#include "r_system.h" -#include "r_cpg.h" -#include "r_reset.h" -#include "r_icu_init.h" - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define CPG_WRITE_ENABLE (0x0000A501) -#define CPG_WRITE_DISABLE (0x0000A500) - -#define CPG_CMT0_CLOCK_PCLKD_32 (1) -#define CPG_CMT0_CMI0_ENABLE (1) -#define CPG_CMT0_CONST_100_us (0xEA) -#define CPG_CMT0_START (1) -#define CPG_CMT0_STOP (0) - -#define CPG_CMT_REG_CLEAR (0x0000) - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - -/******************************************************************************* -Private variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name : R_CPG_PLL_Wait -* Description : Wait about 100us for PLL stabilization by using CMT0 -* Arguments : none -* Return Value : none -*******************************************************************************/ -void R_CPG_PLL_Wait(void) -{ - - /* Enables writing to the registers related to Reset and Low-Power function */ - r_rst_write_enable(); - - /* Release from the CMT0 module-stop state */ - MSTP(CMT0) = 0; - - /* Disables writing to the registers related to Reset and Low-Power function */ - r_rst_write_disable(); - - /* Set CMT0 to 100us interval operation */ - CMT0.CMCR.BIT.CKS = CPG_CMT0_CLOCK_PCLKD_32; // Count clock = PCLKD/32 - CMT0.CMCR.BIT.CMIE = CPG_CMT0_CMI0_ENABLE; // Enable CMI0 interrupt - CMT0.CMCNT = CPG_CMT_REG_CLEAR; // Clear CMCNT counter - CMT0.CMCOR = CPG_CMT0_CONST_100_us; // Set constant value for 100us - - - /* Set IRQ21(CMI0) for polloing sequence */ - VIC.IEC0.BIT.IEC21 = ICU_IEC_MASK_SET; // Mask IRQ21 interrupt - VIC.PLS0.BIT.PLS21 = ICU_TYPE_EDGE; // Set EDGE type interrupt - VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge - - /* Enable IRQ interrupt (Clear CPSR.I bit to 0) */ - asm("cpsie i"); // Clear CPSR.I bit to 0 - asm("isb"); // Ensuring Context-changing - - /* Start CMT0 count */ - CMT.CMSTR0.BIT.STR0 = CPG_CMT0_START; - - /* Wait for 100us (IRQ21 is generated) */ - while ( !(VIC.RAIS0.BIT.RAI21) ) - { - /* Wait */ - } - - /* Stop CMT0 count */ - CMT.CMSTR0.BIT.STR0 = CPG_CMT0_STOP; - - /* Initialize CMT0 settings and clear interrupt detection edge */ - CMT0.CMCR.WORD = CPG_CMT_REG_CLEAR; - CMT0.CMCNT = CPG_CMT_REG_CLEAR; - CMT0.CMCOR = CPG_CMT_REG_CLEAR; - CMT.CMSTR0.WORD = CPG_CMT_REG_CLEAR; - - VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge - - - /* Disable IRQ interrupt (Set CPSR.I bit to 1) */ - asm("cpsid i"); - asm("isb"); - - /* Enables writing to the registers related to Reset and Low-Power function */ - r_rst_write_enable(); - - /* Set CMT0 to module-stop state */ - MSTP(CMT0) = 1; - - /* Disables writing to the registers related to Reset and Low-Power function */ - r_rst_write_disable(); - - -} - -/******************************************************************************* - End of function R_CPG_PLL_Wait -*******************************************************************************/ - -/* End of File */ - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ecm.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ecm.c deleted file mode 100644 index c68b80dfb..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ecm.c +++ /dev/null @@ -1,289 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_ecm.c -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for ECM function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : ECM API of RZ/T1 -* Limitation : LOCO operation is necessary for clearing ERROROUT# pin. -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include -#include -#include "r_system.h" -#include "r_ecm.h" -#include "r_reset.h" -#include "r_icu_init.h" - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define ECM_CMT0_CLOCK_PCLKD_32 (1) -#define ECM_CMT0_CMI0_ENABLE (1) -#define ECM_CMT0_CONST_15_us (0x22) -#define ECM_CMT0_START (1) -#define ECM_CMT0_STOP (0) - -#define ECM_CMT_REG_CLEAR (0x0000) - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - - -/******************************************************************************* -Private variables and functions -*******************************************************************************/ -static uint32_t *g_pcmd_reg_adrr[ECM_TYPE_MAX] = -{ - (uint32_t *) &ECMM.ECMMPCMD0.LONG, - (uint32_t *) &ECMC.ECMCPCMD0.LONG, - (uint32_t *) &ECM.ECMPCMD1.LONG -}; - -/******************************************************************************* -* Function Name : R_ECM_Init -* Description : Initialize ECM function. -* - Clear all error source -* - Clear ERROROUT# pin output to in-active (High) level. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void R_ECM_Init(void) -{ - volatile uint8_t result; - - /* Clear all error source (ECMESSTC0, ECMESSTC1, ECMESSTC2) */ - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC0.LONG), 0xDFFFFFF7); - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC1.LONG), 0x000001FF); - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC2.LONG), 0x70000000); - - /* Mask all error source (ECMEMK0, ECMEMK1, ECMEMK2) for clearing ERROROUT# */ - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK0.LONG), 0xDFFFFFF7); - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK1.LONG), 0x000001FF); - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK2.LONG), 0x30000000); - - /* Mask ECM maskable, non-maskable interrupt and ECM reset of ECM compare match - error (ECMMICFG2, ECMNMICFG2, ECMIRCFG2) */ - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMMICFG2.LONG), 0x00000000); - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMNMICFG2.LONG), 0x00000000); - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMIRCFG2.LONG), 0x00000000); - - /* Clear ERROROUT# pin output to in-active (High) level */ - result = R_ECM_Write_Reg8(ECM_MASTER, &(ECMM.ECMMECLR.BYTE), 0x01); - result = R_ECM_Write_Reg8(ECM_CHECKER, &(ECMC.ECMCECLR.BYTE), 0x01); - - /* Wait 15us for ECM compare error stabilization */ - R_ECM_CompareError_Wait(); - - /* Clear ECM compare error (ECMESSTC2) again */ - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMESSTC2.LONG), 0x10000000); - - /* Initialize the all error mask settings (ECMEMK0, ECMEMK1, ECMEMK2) */ - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK0.LONG), 0x00000000); - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK1.LONG), 0x00000000); - result = R_ECM_Write_Reg32(ECM_COMMON, &(ECM.ECMEMK2.LONG), 0x00000000); - -} - -/******************************************************************************* - End of function R_ECM_Init -*******************************************************************************/ - -/******************************************************************************* -* Function Name : R_ECM_CompareError_Wait -* Description : Wait about 15 us for ECM compare error stabilizeation by using CMT0 -* Arguments : none -* Return Value : none -*******************************************************************************/ -void R_ECM_CompareError_Wait(void) -{ - /* Enables writing to the registers related to Reset and Low-Power function */ - r_rst_write_enable(); - - /* Release from the CMT0 module-stop state */ - MSTP(CMT0) = 0; - - /* Disables writing to the registers related to Reset and Low-Power function */ - r_rst_write_disable(); - - /* Set CMT0 to 100us interval operation */ - CMT0.CMCR.BIT.CKS = ECM_CMT0_CLOCK_PCLKD_32; // Count clock = PCLKD/32 - CMT0.CMCR.BIT.CMIE = ECM_CMT0_CMI0_ENABLE; // Enable CMI0 interrupt - CMT0.CMCNT = ECM_CMT_REG_CLEAR; // Clear CMCNT counter - CMT0.CMCOR = ECM_CMT0_CONST_15_us; // Set constant value for 15us - - - /* Set IRQ21(CMI0) for polloing sequence */ - VIC.IEC0.BIT.IEC21 = ICU_IEC_MASK_SET; // Mask IRQ21 interrupt - VIC.PLS0.BIT.PLS21 = ICU_TYPE_EDGE; // Set EDGE type interrupt - VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge - - /* Enable IRQ interrupt (Clear CPSR.I bit to 0) */ - asm("cpsie i"); // Clear CPSR.I bit to 0 - asm("isb"); // Ensuring Context-changing - - /* Start CMT0 count */ - CMT.CMSTR0.BIT.STR0 = ECM_CMT0_START; - - /* Wait for 15us (IRQ21 is generated) */ - while ( ! (VIC.RAIS0.BIT.RAI21) ) - { - /* Wait */ - } - - /* Stop CMT0 count */ - CMT.CMSTR0.BIT.STR0 = ECM_CMT0_STOP; - - /* Initialize CMT0 settings and clear interrupt detection edge */ - CMT0.CMCR.WORD = ECM_CMT_REG_CLEAR; - CMT0.CMCNT = ECM_CMT_REG_CLEAR; - CMT0.CMCOR = ECM_CMT_REG_CLEAR; - CMT.CMSTR0.WORD = ECM_CMT_REG_CLEAR; - - VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge - - - /* Disable IRQ interrupt (Set CPSR.I bit to 1) */ - asm("cpsid i"); - asm("isb"); - - /* Enables writing to the registers related to Reset and Low-Power function */ - r_rst_write_enable(); - - /* Set CMT0 to module-stop state */ - MSTP(CMT0) = 1; - - /* Disables writing to the registers related to Reset and Low-Power function */ - r_rst_write_disable(); - -} - -/******************************************************************************* - End of function R_ECM_CompareError_Wait -*******************************************************************************/ - - -/******************************************************************************* -* Function Name : R_ECM_Write_Reg8 -* Description : Writing the special sequence for 8-bit ECM protected register -* Arguments : reg_type -* The type of ECM register (ECM_MASETR, ECM_CHECKER, ECM_COMMON) -* *reg -* The address of ECM protected register -* value -* The 8-bit value of writing to protected register -* Return Value : none -*******************************************************************************/ -uint8_t R_ECM_Write_Reg8( uint8_t reg_type, volatile unsigned char *reg, uint8_t value) -{ - uint8_t result; - volatile uint8_t dummy_8; - volatile uint32_t dummy_32; - - /* Special write sequence */ - *g_pcmd_reg_adrr[reg_type] = ECM_COMMAND_KEY; // Write fixed value - dummy_32 = *g_pcmd_reg_adrr[reg_type]; - - *reg = value; // Write expected value - *reg = ~value; // Write inversed value of the expected value - *reg = value; // Write expected value - dummy_8 = *reg; - - /* Check the ECMPS register whether special sequence is success or failure - result = 0 : Special sequence is success. - = 1 : Special sequence is failure. */ - result = ECM.ECMPS.BYTE; - - return result; - -} -/******************************************************************************* - End of function R_ECM_Write_Reg8 -*******************************************************************************/ - -/******************************************************************************* -* Function Name : R_ECM_Write_Reg32 -* Description : Writing the special sequence for 32-bit ECM protected register -* Arguments : reg_type -* The type of ECM register (ECM_MASETR, ECM_CHECKER, ECM_COMMON) -* *reg -* The address of ECM protected register -* value -* The 32-bit value of writing to protected register -* Return Value : none -*******************************************************************************/ -uint8_t R_ECM_Write_Reg32( uint8_t reg_type, volatile unsigned long *reg, uint32_t value) -{ - uint8_t result; - volatile uint32_t dummy_32; - - /* Special write sequence */ - *g_pcmd_reg_adrr[reg_type] = ECM_COMMAND_KEY; // Write fixed value - dummy_32 = *g_pcmd_reg_adrr[reg_type]; - - *reg = value; // Write expected value - *reg = ~value; // Write inversed value of the expected value - *reg = value; // Write expected value - dummy_32 = *reg; - - /* Check the ECMPS register whether special sequence is success or failure - result = 0 : Special sequence is success. - = 1 : Special sequence is failure. */ - result = ECM.ECMPS.BYTE; - - return result; - -} -/******************************************************************************* - End of function R_ECM_Write_Reg32 -*******************************************************************************/ - -/* End of File */ - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_icu_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_icu_init.c deleted file mode 100644 index daf7ce037..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_icu_init.c +++ /dev/null @@ -1,329 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_icu_init.c -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for ICU init -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : Initialize the peripheral settings of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include -#include -#include "r_icu_init.h" -#include "r_system.h" -#include "r_mpc.h" -#include "r_ecm.h" - -/******************************************************************************* -Macro definitions -*******************************************************************************/ - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - -/******************************************************************************* -Private variables and functions -*******************************************************************************/ -#ifdef __ICCARM__ -#pragma type_attribute=__irq __arm -#endif // __ICCARM__ -void R_IRQ9_isr(void); - - - -/******************************************************************************* -* Function Name: R_ICU_Disable -* Description : Disable IRQ interrupt -* Arguments : vec_num - Vector interrupt number (1 to 294). -* Return Value : none -*******************************************************************************/ -void R_ICU_Disable(uint32_t vec_num) -{ - /* Define IECn register address pointer */ - volatile uint32_t *p_iec_base; - - /* Variable to specify register suffix */ - uint32_t reg_num; // IECn (n = reg_num) - uint32_t bit_num; // IECn.IECm (m = bit_num) - - /* Calcurate register address and register suffix number */ - if ( 255 >= vec_num ) // Vector number : 1 to 255 - { - /* Set each pointer base address as IEC0 */ - /* Casting the pointer to a (uint32_t *) is valid because this pointer - will reference 32 bit I/O register address */ - p_iec_base = (uint32_t*)&(VIC.IEC0.LONG); - - /* Calcurate register suffix number */ - reg_num = vec_num / 32; // IECn (n = reg_num) - bit_num = vec_num % 32; // IECn.IECm (m = bit_num) - } - else // Vector number : 256 to 294 - { - /* Set each pointer address as IEC8 */ - /* Casting the pointer to a (uint32_t *) is valid because this pointer - will reference 32 bit I/O register address */ - p_iec_base = (uint32_t*)&(VIC.IEC8.LONG); - - /* Calcurate register suffix number. And subtract 8 from reg_num - because IEC8 is base address in this case */ - reg_num = (vec_num / 32) - 8; // IECn (n = 8 + reg_num) - bit_num = (vec_num % 32); // IECn.IECm (m = bit_num) - } - - /* Set interrupt enable clear register (disable interrupt) */ - p_iec_base += reg_num; // Specify IECn register address - *p_iec_base |= ( 1 << bit_num ); // Set IECn.IECm bit - -} -/******************************************************************************* - End of function R_ICU_Disable -*******************************************************************************/ - -/******************************************************************************* -* Function Name: R_ICU_Enable -* Description : Enable IRQ interrupt -* Arguments : vec_num - Vector interrupt number (1 to 294). -* Return Value : none -*******************************************************************************/ -void R_ICU_Enable(uint32_t vec_num) -{ - /* Define IENn register address pointer */ - volatile uint32_t *p_ien_base; - - /* Variable to specify register suffix */ - uint32_t reg_num; // IENn (n = reg_num) - uint32_t bit_num; // IENn.IENm (m = bit_num) - - - /* Calcurate register address and register suffix number */ - if ( 255 >= vec_num ) // Vector number : 1 to 255 - { - /* Set each pointer base address as IEN0 */ - /* Casting the pointer to a (uint32_t *) is valid because this pointer - will reference 32 bit I/O register address */ - p_ien_base = (uint32_t*)&(VIC.IEN0.LONG); - - /* Calcurate register suffix number */ - reg_num = vec_num / 32; // IENn (n = reg_num) - bit_num = vec_num % 32; // IENn.IENm (m = bit_num) - } - else // Vector number : 256 to 294 - { - /* Set each pointer address as IEN8 */ - /* Casting the pointer to a (uint32_t *) is valid because this pointer - will reference 32 bit I/O register address */ - p_ien_base = (uint32_t*)&(VIC.IEN8.LONG); - - /* Calcurate register suffix number. And subtract 8 from reg_num - because IEN8 is base address in this case */ - reg_num = (vec_num / 32) - 8; // IENn (n = 8 + reg_num) - bit_num = (vec_num % 32); // IENn.IENm (m = bit_num) - } - - /* Set interrupt enable register (enable interrupt) */ - p_ien_base += reg_num; // Specify IENn register address - *p_ien_base |= ( 1 << bit_num ); // Set IENn.IENm bit - -} -/******************************************************************************* - End of function R_ICU_Enable -*******************************************************************************/ - -/******************************************************************************* -* Function Name: R_ICU_ExtPinInit -* Description : Initialize external interrupt pin setting. -* Arguments : pin_num - External interrupt pin number (0 to 15). - detect - Interrupt pin detection sense (Low, Fall, Rise, RIse&Fall). - dnf_set - Setting of degital noise filter -* Return Value : none -*******************************************************************************/ -void R_ICU_ExtPinInit(uint16_t pin_num, uint8_t detect, uint32_t dnf_set) -{ - /* Define IRQCRn register address pointer */ - /* Casting the pointer to a (void *) is valid because this pointer will - reference 32 bit I/O register address */ - volatile uint32_t *p_irqcr_base = (void *)(&(ICU.IRQCR0.LONG)); - - /* Disable digital noise filter (Clear IRQFLTEn bit (n = pin_num))*/ - ICU.IRQFLTE.LONG &= (0x0000FFFF & ~( 1 << pin_num )); - - /* Set IRQ detection sense */ - p_irqcr_base += pin_num; // Specify IRQCRn register address - *p_irqcr_base = detect; // Set IRQCRn.IRQMD[1:0] - - /* Set digital noise filter and enable */ - if ( ICU_DNF_NO_USE != dnf_set ) - { - /* Set digital noise filter */ - ICU.IRQFLTC.LONG &= ~( 3 << ( pin_num * 2 ) ); // Clear FCLKSELn[1:0] - ICU.IRQFLTC.LONG |= (dnf_set << ( pin_num * 2)); // Set FCLKSELn[1:0] to dnf_set value - - /* Enable digital noise filter */ - ICU.IRQFLTE.LONG |= ( 1 << pin_num ); - } - -} -/******************************************************************************* - End of function R_ICU_ExtPinInit -*******************************************************************************/ - - -/******************************************************************************* -* Function Name: R_ICU_Regist -* Description : Registration interrupt controller setting. -* Arguments : vec_num - Vector interrupt number (1 to 294). - type - IRQ detection type(Level or Edge). - priority - IRQ priority level ( Vector number 1 to 255 : 0 to 15, - Vector number 256 to 294 : 16 to 31) - isr_addr - Interrupt service routine address -* Return Value : none -*******************************************************************************/ -void R_ICU_Regist(uint32_t vec_num, uint32_t type, uint32_t priority, uint32_t isr_addr) -{ - /* Define PLSn, PRLn, VADn and PICn registers address pointer */ - volatile uint32_t *p_pls_base; - volatile uint32_t *p_prl_base; - volatile uint32_t *p_vad_base; - volatile uint32_t *p_pic_base; - - /* Variable to specify register suffix */ - uint32_t reg_num; // PLSn, PICn (n = reg_num) - uint32_t bit_num; // PLSn.PLSm, PICn.PICm (m = bit_num) - - - /* Calcurate register address and register suffix number */ - if ( 255 >= vec_num ) // Vector number : 1 to 255 - { - /* Set each pointer base address as PLS0, PRL1, VAD1 and PIC0 */ - /* Casting the pointer to a (uint32_t *) is valid because this pointer - will reference 32 bit I/O register address */ - p_pls_base = (uint32_t*)&(VIC.PLS0.LONG); - p_prl_base = (uint32_t*)&(VIC.PRL1.LONG); - p_vad_base = (uint32_t*)&(VIC.VAD1.LONG); - p_pic_base = (uint32_t*)&(VIC.PIC0.LONG); - - /* Calcurate register suffix number */ - reg_num = vec_num / 32; // PLSn, PICn (n = reg_num) - bit_num = vec_num % 32; // PLSn.PLSm, PICn.PICm (m = bit_num) - } - else // Vector number : 256 to 294 - { - /* Set each pointer address as PLS8, PRL256, VAD256 and PIC8 */ - /* Casting the pointer to a (uint32_t *) is valid because this pointer - will reference 32 bit I/O register address */ - p_pls_base = (uint32_t*)&(VIC.PLS8.LONG); - p_prl_base = (uint32_t*)&(VIC.PRL256.LONG); - p_vad_base = (uint32_t*)&(VIC.VAD256.LONG); - p_pic_base = (uint32_t*)&(VIC.PIC8.LONG); - - /* Calcurate register suffix number. And subtract 8 from reg_num - because PLS8 and PIC8 are base address in this case */ - reg_num = (vec_num / 32) - 8; // PLSn, PICn (n = 8 + reg_num) - bit_num = (vec_num % 32); // PLSn.PLSm, PICn.PICm (m = bit_num) - vec_num -= 255; // Offset (PRLn and VADn base is changed (eg. VAD1 to VAD256) - } - - /* Set interrupt detection type (Level or Edge) by PLSn */ - p_pls_base += reg_num; // Specify PLSn register address - *p_pls_base &= ~( 1 << bit_num ); // Clear PLSn.PLSm bit - *p_pls_base |= ( type << bit_num ); // Set PLSn.PLSm bit to type value - - /* Set interrupt priority level (0 to 15) or (16 to 31) */ - p_prl_base += ( vec_num - 1 ); // Specify PRLn register address - *p_prl_base = priority; // Set PRLn to priority value - - /* Set interrupt service routine address */ - p_vad_base += ( vec_num - 1 ); // Specify VADn register address - *p_vad_base = isr_addr; // Set VADn to isr_addr value - - /* Clear interrupt edge detection (edge type only)*/ - if ( ICU_TYPE_EDGE == type ) - { - p_pic_base += reg_num; // Specify PICn register address - *p_pic_base |= ( 1 << bit_num ); // Set PICn.PICm bit to 1 - } - -} - -/******************************************************************************* - End of function R_ICU_Regist -*******************************************************************************/ - -/******************************************************************************* -* Function Name: R_IRQ9_isr -* Description : Interrupt service routine of IRQ9 (IRQ5 pin interrupt). -* Toggle the P56 output level (LED1) -* Arguments : none -* Return Value : none -*******************************************************************************/ -#ifdef __ICCARM__ -#pragma type_attribute=__irq __arm -#endif // __ICCARM__ -void R_IRQ9_isr(void) -{ - /* Clear interrupt edge detection */ - VIC.PIC0.BIT.PIC9 = ICU_PIC_EDGE_CLEAR; - - /* Toggle the P56 output level(LED1) */ - PORT5.PODR.BIT.B6 ^= 1; - - /* End interrupt sequence (dummy writing to HVA0 register) */ - VIC.HVA0.LONG = 0x00000000; - -} - -/******************************************************************************* - End of function R_IRQ9_isr -*******************************************************************************/ - - -/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ram_init.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ram_init.c deleted file mode 100644 index e6f395ce5..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_ram_init.c +++ /dev/null @@ -1,148 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_ram_init.c -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for internal extended RAM function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : internal extended RAM setting API of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include -#include -#include "r_system.h" -#include "r_ram_init.h" - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define RAM_ECC_ENABLE (0x00000001) -#define RAM_ECC_DISABLE (0x00000000) -#define RAM_PROTECT (0x00000000) - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - - -/******************************************************************************* -Private variables and functions -*******************************************************************************/ - -/******************************************************************************* -* Function Name : R_RAM_ECC_Enable -* Description : Enable ECC function for internal extended RAM. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void R_RAM_ECC_Enable(void) -{ - /* Enables writing to the protected registers related to RAM function */ - R_RAM_WriteEnable(); - - /* Enable ECC function */ - ECCRAM.RAMEDC.LONG = RAM_ECC_ENABLE; - - /* Disables writing to the protected registers related to RAM function */ - R_RAM_WriteDisable(); - -} - -/******************************************************************************* - End of function R_RAM_ECC_Enable -*******************************************************************************/ - - -/******************************************************************************* -* Function Name : R_RAM_WriteEnable -* Description : Enable writing to the protected registers related to RAM. -* And dummy read the register in order to fix the register value. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void R_RAM_WriteEnable(void) -{ - volatile uint32_t dummy; - - /* Special sequence for protect release */ - ECCRAM.RAMPCMD.LONG = 0x000000A5; // Write fixed value 0x000000A5 - ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value - ECCRAM.RAMPCMD.LONG = 0x0000FFFE; // Write inversed value of the expected value - ECCRAM.RAMPCMD.LONG = 0x00000001; // Write expected value again - dummy = ECCRAM.RAMPCMD.LONG; - -} - -/******************************************************************************* - End of function R_RAM_WriteEnable -*******************************************************************************/ - -/******************************************************************************* -* Function Name : R_RAM_WriteDisable -* Description : Disable writing to the protected registers related to RAM. -* And dummy read the register in order to fix the register value. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void R_RAM_WriteDisable(void) -{ - volatile uint32_t dummy; - - /* Clear RAMPCMD register to zero */ - ECCRAM.RAMPCMD.LONG = RAM_PROTECT; - dummy = ECCRAM.RAMPCMD.LONG; - -} - -/******************************************************************************* - End of function R_RAM_WriteDisable -*******************************************************************************/ - -/* End of File */ - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_reset.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_reset.c deleted file mode 100644 index 615f75f64..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/r_reset.c +++ /dev/null @@ -1,123 +0,0 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/******************************************************************************* -* System Name : RZ/T1 Init program -* File Name : r_reset.c -* Version : 0.1 -* Device : R7S9100xx -* Abstract : API for RESET and Low-Power function -* Tool-Chain : IAR Embedded Workbench Ver.7.20 -* OS : not use -* H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -* Description : RESET and Low-Power API of RZ/T1 -* Limitation : none -*******************************************************************************/ -/******************************************************************************* -* History : DD.MM.YYYY Version Description -* : First Release -*******************************************************************************/ - -/******************************************************************************* -Includes , "Project Includes" -*******************************************************************************/ -#include -#include -#include "r_system.h" -#include "r_reset.h" - -/******************************************************************************* -Macro definitions -*******************************************************************************/ -#define RST_WRITE_ENABLE (0x0000A502) -#define RST_WRITE_DISABLE (0x0000A500) - -/******************************************************************************* -Typedef definitions -*******************************************************************************/ - - - -/******************************************************************************* -Imported global variables and functions (from other files) -*******************************************************************************/ - - -/******************************************************************************* -Exported global variables and functions (to be accessed by other files) -*******************************************************************************/ - - - -/******************************************************************************* -Private variables and functions -*******************************************************************************/ - - -/******************************************************************************* -* Function Name : r_rst_write_enable -* Description : Enables writing to the registers related to RESET and Low- -* Power function. And dummy read the register in order to fix -* the register value. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void r_rst_write_enable(void) -{ - volatile uint32_t dummy; - - /* Enables writing to the Reset and Low-Power register */ - SYSTEM.PRCR.LONG = RST_WRITE_ENABLE; - dummy = SYSTEM.PRCR.LONG; - -} - -/******************************************************************************* - End of function r_rst_write_enable -*******************************************************************************/ - -/******************************************************************************* -* Function Name : r_rst_write_disable -* Description : Disables writing to the registers related to RESET and Low- -* Power function. And dummy read the register in order to fix -* the register value. -* Arguments : none -* Return Value : none -*******************************************************************************/ -void r_rst_write_disable(void) -{ - volatile uint32_t dummy; - - /* Disables writing to the Reset and Low-Power register */ - SYSTEM.PRCR.LONG = RST_WRITE_DISABLE; - dummy = SYSTEM.PRCR.LONG; - -} - -/******************************************************************************* - End of function r_rst_write_disable -*******************************************************************************/ - -/* End of File */ - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/vector.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/vector.asm deleted file mode 100644 index 1e29b24ce..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/IAR/src/vector.asm +++ /dev/null @@ -1,73 +0,0 @@ -;******************************************************************************* -; DISCLAIMER -; This software is supplied by Renesas Electronics Corporation and is only -; intended for use with Renesas products. No other uses are authorized. This -; software is owned by Renesas Electronics Corporation and is protected under -; all applicable laws, including copyright laws. -; THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -; THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -; LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -; AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -; TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -; ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -; FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -; ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -; BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -; Renesas reserves the right, without notice, to make changes to this software -; and to discontinue the availability of this software. By using this software, -; you agree to the additional terms and conditions found by accessing the -; following link: -; http://www.renesas.com/disclaimer -; -; Copyright (C) 2014 Renesas Electronics Corporation. All rights reserved. -;****************************************************************************** -;******************************************************************************* -; System Name : RZ/T1 Init program -; File Name : vector.asm -; Version : 0.1 -; Device : R7S9100xx -; Abstract : vector address (in low vector) -; Tool-Chain : IAR Embedded Workbench Ver.7.20 -; OS : not use -; H/W Platform : Renesas Starter Kit for RZ/T1(Preliminary) -; Description : vector address for RZ/T1 (in low vector) -; Limitation : none -;****************************************************************************** -;******************************************************************************* -; History : DD.MM.YYYY Version Description -; : First Release -;****************************************************************************** - -/* This program is allocated to section "intvec" */ - SECTION intvec:CODE:ROOT(2) - - EXTERN FreeRTOS_SVC_Handler - - ARM - -reset_handler: - b reset_handler - -undefined_handler: - b undefined_handler - -svc_handler: - b FreeRTOS_SVC_Handler - -prefetch_handler: - b prefetch_handler - -abort_handler: - b abort_handler - -reserved_handler: - b reserved_handler - -irq_handler: - b irq_handler - -fiq_handler: - b fiq_handler - - END -; End of File diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/makefile.init b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/makefile.init deleted file mode 100644 index 9f2d24f6f..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/makefile.init +++ /dev/null @@ -1,5 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -PATH := $(PATH):C:\PROGRA~2\KPIT\GNUARM~1.02-\ARM-NO~1\ARM-NO~1\bin;C:\PROGRA~2\KPIT\GNUARM~1.02-\ARM-NO~1\ARM-NO~1\libexec\gcc\arm-none-eabi\4.9-GNUARM-NONE_v14.02 \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Blinky_Demo/main_blinky.c deleted file mode 100644 index 83d88be71..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Blinky_Demo/main_blinky.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky style - * project, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select - * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY - * in main.c. This file implements the simply blinky style version. - * - * NOTE 2: This file only contains the source code that is specific to the - * basic demo. Generic functions, such FreeRTOS hook functions, and functions - * required to configure the hardware are defined in main.c. - ****************************************************************************** - * - * main_blinky() creates one queue, and two tasks. It then starts the - * scheduler. - * - * The Queue Send Task: - * The queue send task is implemented by the prvQueueSendTask() function in - * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly - * block for 200 milliseconds, before sending the value 100 to the queue that - * was created within main_blinky(). Once the value is sent, the task loops - * back around to block for another 200 milliseconds...and so on. - * - * The Queue Receive Task: - * The queue receive task is implemented by the prvQueueReceiveTask() function - * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly - * blocks on attempts to read data from the queue that was created within - * main_blinky(). When data is received, the task checks the value of the - * data, and if the value equals the expected 100, toggles an LED. The 'block - * time' parameter passed to the queue receive function specifies that the - * task should be held in the Blocked state indefinitely to wait for data to - * be available on the queue. The queue receive task will only leave the - * Blocked state when the queue send task writes to the queue. As the queue - * send task writes to the queue every 200 milliseconds, the queue receive - * task leaves the Blocked state every 200 milliseconds, and therefore toggles - * the LED every 200 milliseconds. - */ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* Renesas includes. */ -#include "r_cg_macrodriver.h" -#include "r_cg_userdefine.h" - -/* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) - -/* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) - -/*-----------------------------------------------------------*/ - -/* - * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in - * main.c. - */ -void main_blinky( void ); - -/* - * The tasks as described in the comments at the top of this file. - */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The queue used by both tasks. */ -static QueueHandle_t xQueue = NULL; - -/*-----------------------------------------------------------*/ - -void main_blinky( void ) -{ - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - NULL, /* The parameter passed to the task - not used in this case. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvQueueSendTask( void *pvParameters ) -{ -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Remove compiler warning about unused parameter. */ - ( void ) pvParameters; - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } -} -/*-----------------------------------------------------------*/ - -static void prvQueueReceiveTask( void *pvParameters ) -{ -unsigned long ulReceivedValue; -const unsigned long ulExpectedValue = 100UL; - - /* Remove compiler warning about unused parameter. */ - ( void ) pvParameters; - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == ulExpectedValue ) - { - LED2 = !LED2; - ulReceivedValue = 0U; - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOSConfig.h deleted file mode 100644 index 49e1c887f..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOSConfig.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -#define configCPU_CLOCK_HZ 450000000 -#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 -#define configUSE_TICKLESS_IDLE 0 -#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 1 -#define configUSE_TICK_HOOK 1 -#define configMAX_PRIORITIES ( 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 120 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 38 * 1024 ) ) -#define configMAX_TASK_NAME_LEN ( 10 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configQUEUE_REGISTRY_SIZE 8 -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configGENERATE_RUN_TIME_STATS 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) -#define configTIMER_QUEUE_LENGTH 5 -#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_eTaskGetState 1 -#define INCLUDE_xEventGroupSetBitFromISR 1 -#define INCLUDE_xTimerPendFunctionCall 1 - -/* This demo makes use of one or more example stats formatting functions. These -format the raw data provided by the uxTaskGetSystemState() function in to human -readable ASCII form. See the notes in the implementation of vTaskList() within -FreeRTOS/Source/tasks.c for limitations. */ -#define configUSE_STATS_FORMATTING_FUNCTIONS 1 - -/* Cortex-R specific setting: FPU has 16 (rather than 32) d registers. */ -#define configFPU_D32 0 - -/* Cortex-R specific setting: The address of the register within the interrupt -controller from which the address of the current interrupt's handling function -can be obtained. */ -#define configINTERRUPT_VECTOR_ADDRESS - -/* Cortex-R specific setting: The address of End of Interrupt register within -the interrupt controller. */ -#define configEOI_ADDRESS 0xA0010200UL /* VIC HVA0 register */ - -/* Cortex-R specific setting: configCLEAR_TICK_INTERRUPT() is a macro that is -called by the RTOS kernel's tick handler to clear the source of the tick -interrupt. */ -#define configCLEAR_TICK_INTERRUPT() VIC.PIC9.LONG = 0x00001000UL; - -/* Prevent C code being included in assembly files when the IAR compiler is -used. */ -#ifndef __IASMARM__ - - /* Renesas hardware definitions. */ - #include "iodefine.h" - - /* Application specific definition. See _TBD_ for usage instructions. */ - typedef void (*ISRFunction_t)( void ); - - /* Normal assert() semantics without relying on the provision of an assert.h - header file. */ - #define configASSERT( x ) if( ( x ) == 0 ) { portDISABLE_INTERRUPTS(); for( ;; ); } - - - - /****** Hardware specific settings. *******************************************/ - - /* - * The application must provide a function that configures a peripheral to - * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() - * in FreeRTOSConfig.h to call the function. FreeRTOS_Tick_Handler() must - * be installed as the peripheral's interrupt handler. - */ - void vConfigureTickInterrupt( void ); - #define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt() - -#endif /* __IASMARM__ */ - -/* To allow the debugger to find the end of the interrupt stack frame. */ -#define configTASK_RETURN_ADDRESS NULL - -#endif /* FREERTOS_CONFIG_H */ - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOS_tick_config.c deleted file mode 100644 index 449274271..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOS_tick_config.c +++ /dev/null @@ -1,213 +0,0 @@ -/* - FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" - -/* Renesas includes. */ -#include "r_cg_macrodriver.h" -#include "r_cg_cmt.h" -#include "r_reset.h" - -/*-----------------------------------------------------------*/ - -/* - * Entry point for the FreeRTOS tick interrupt. This sets the pxISRFunction - * variable to point to the RTOS tick handler, then branches to the FreeRTOS - * IRQ handler. - */ -#ifdef __GNUC__ - static void FreeRTOS_Tick_Handler_Entry( void ) __attribute__((naked)); -#endif /* __GNUC__ */ -#ifdef __ICCARM__ - /* IAR requires the entry point to be in an assembly file. The function is - implemented in $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm. */ - extern void FreeRTOS_Tick_Handler_Entry( void ); -#endif /* __ICCARM__ */ - -/* - * The FreeRTOS IRQ handler, which is implemented in the RTOS port layer. - */ -extern void FreeRTOS_IRQ_Handler( void ); - -/* - * The function called by the FreeRTOS_IRQ_Handler() to call the actual - * peripheral handler. - */ -void vApplicationIRQHandler( void ); - -/*-----------------------------------------------------------*/ - -/* - * Variable used to hold the address of the interrupt handler the FreeRTOS IRQ - * handler will branch to. - */ -ISRFunction_t pxISRFunction = NULL; - -/*-----------------------------------------------------------*/ - -/* - * The application must provide a function that configures a peripheral to - * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() - * in FreeRTOSConfig.h to call the function. - */ -void vConfigureTickInterrupt( void ) -{ -uint32_t ulCompareMatchValue; -const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL; - - /* Disable CMI5 interrupt. */ - VIC.IEC9.LONG = 0x00001000UL; - - /* Cancel CMT stop state in LPC. */ - r_rst_write_enable(); - MSTP( CMT2 ) = 0U; - r_rst_write_disable(); - - /* Interrupt on compare match. */ - CMT5.CMCR.BIT.CMIE = 1; - - /* Calculate the compare match value. */ - ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider; - ulCompareMatchValue /= ulCMTClockDivider; - ulCompareMatchValue /= configTICK_RATE_HZ; - ulCompareMatchValue -= 1UL; - - /* Set the compare match value. */ - CMT5.CMCOR = ( unsigned short ) ulCompareMatchValue; - - /* Divide the PCLK by 8. */ - CMT5.CMCR.BIT.CKS = 0; - - CMT5.CMCNT = 0; - - /* Set CMI5 edge detection type. */ - VIC.PLS9.LONG |= 0x00001000UL; - - /* Set CMI5 priority level to the lowest possible. */ - VIC.PRL300.LONG = _CMT_PRIORITY_LEVEL31; - - /* Set CMI5 interrupt address */ - VIC.VAD300.LONG = ( uint32_t ) FreeRTOS_Tick_Handler_Entry; - - /* Enable CMI5 interrupt in ICU. */ - VIC.IEN9.LONG |= 0x00001000UL; - - /* Start CMT5 count. */ - CMT.CMSTR2.BIT.STR5 = 1U; -} -/*-----------------------------------------------------------*/ - -/* - * The function called by the FreeRTOS IRQ handler, after it has managed - * interrupt entry. This function creates a local copy of pxISRFunction before - * re-enabling interrupts and actually calling the handler pointed to by - * pxISRFunction. - */ -void vApplicationIRQHandler( void ) -{ -ISRFunction_t pxISRToCall = pxISRFunction; - - portENABLE_INTERRUPTS(); - - /* Call the installed ISR. */ - pxISRToCall(); -} -/*-----------------------------------------------------------*/ - -/* - * The RZ/T vectors directly to a peripheral specific interrupt handler, rather - * than using the Cortex-R IRQ vector. Therefore each interrupt handler - * installed by the application must follow the example below, which saves a - * pointer to a standard C function in the pxISRFunction variable, before - * branching to the FreeRTOS IRQ handler. The FreeRTOS IRQ handler then manages - * interrupt entry (including interrupt nesting), before calling the C function - * saved in the pxISRFunction variable. NOTE: This entry point is a naked - * function - do not add C code to this function. - */ -#ifdef __GNUC__ - /* The IAR equivalent is implemented in - $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */ - static void FreeRTOS_Tick_Handler_Entry( void ) - { - __asm volatile ( \ - "PUSH {r0-r1} \t\n" \ - "LDR r0, =pxISRFunction \t\n" \ - "LDR R1, =FreeRTOS_Tick_Handler \t\n" \ - "STR R1, [r0] \t\n" \ - "POP {r0-r1} \t\n" \ - "B FreeRTOS_IRQ_Handler " - ); - } -#endif /* __GNUC__ */ -/*-----------------------------------------------------------*/ - - - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.c deleted file mode 100644 index 5aee68feb..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/* - * This file contains the non-portable and therefore RZ/T specific parts of - * the IntQueue standard demo task - namely the configuration of the timers - * that generate the interrupts and the interrupt entry points. - */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "IntQueueTimer.h" -#include "IntQueue.h" - -/* Renesas includes. */ -#include "r_cg_macrodriver.h" -#include "r_cg_cmt.h" -#include "r_reset.h" - -#define tmrCMT_1_CHANNEL_0_HZ ( 4000UL ) -#define tmrCMT_1_CHANNEL_1_HZ ( 2011UL ) - -/* - * Handlers for the two timers used. See the documentation page - * for this port on TBD for more information on writing - * interrupt handlers. - */ -void vCMT_1_Channel_0_ISR( void ); -void vCMT_1_Channel_1_ISR( void ); - -/* - * Entry point for the handlers. These set the pxISRFunction variable to point - * to the C handler for each timer, then branch to the FreeRTOS IRQ handler. - */ -#ifdef __GNUC__ - static void vCMT_1_Channel_0_ISR_Entry( void ) __attribute__((naked)); - static void vCMT_1_Channel_1_ISR_Entry( void ) __attribute__((naked)); -#endif /* __GNUC__ */ -#ifdef __ICCARM__ - /* IAR requires the entry point to be in an assembly file. The functions - are implemented in $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm. */ - extern void vCMT_1_Channel_0_ISR_Entry( void ); - extern void vCMT_1_Channel_1_ISR_Entry( void ); -#endif /* __ICCARM__ */ -/*-----------------------------------------------------------*/ - -void vInitialiseTimerForIntQueueTest( void ) -{ -uint32_t ulCompareMatchValue; -const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL; - - /* Disable CMI2 and CMI3 interrupts. */ - VIC.IEC0.LONG = ( 1UL << 23UL ) | ( 1UL << 24UL ); - - /* Cancel CMT stop state in LPC. */ - r_rst_write_enable(); - MSTP( CMT1 ) = 0U; - r_rst_write_disable(); - - /* Interrupt on compare match. */ - CMT2.CMCR.BIT.CMIE = 1; - CMT3.CMCR.BIT.CMIE = 1; - - /* Calculate the compare match value. */ - ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider; - ulCompareMatchValue /= ulCMTClockDivider; - ulCompareMatchValue /= tmrCMT_1_CHANNEL_0_HZ; - ulCompareMatchValue -= 1UL; - CMT2.CMCOR = ( unsigned short ) ulCompareMatchValue; - - ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider; - ulCompareMatchValue /= ulCMTClockDivider; - ulCompareMatchValue /= tmrCMT_1_CHANNEL_1_HZ; - ulCompareMatchValue -= 1UL; - CMT3.CMCOR = ( unsigned short ) ulCompareMatchValue; - - /* Divide the PCLK by 8. */ - CMT2.CMCR.BIT.CKS = 0; - CMT3.CMCR.BIT.CKS = 0; - - /* Clear count to 0. */ - CMT2.CMCNT = 0; - CMT3.CMCNT = 0; - - /* Set CMI2 and CMI3 edge detection type. */ - VIC.PLS0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL ); - - /* Set CMI2 and CMI3 priority levels so they nest. */ - VIC.PRL23.LONG = _CMT_PRIORITY_LEVEL2; - VIC.PRL24.LONG = _CMT_PRIORITY_LEVEL9; - - /* Set CMI2 and CMI3 interrupt address. */ - VIC.VAD23.LONG = ( uint32_t ) vCMT_1_Channel_0_ISR_Entry; - VIC.VAD24.LONG = ( uint32_t ) vCMT_1_Channel_1_ISR_Entry; - - /* Enable CMI2 and CMI3 interrupts in ICU. */ - VIC.IEN0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL ); - - /* Start CMT1 channel 0 and 1 count. */ - CMT.CMSTR1.BIT.STR2 = 1U; - CMT.CMSTR1.BIT.STR3 = 1U; -} -/*-----------------------------------------------------------*/ - -void vCMT_1_Channel_0_ISR( void ) -{ - /* Clear the interrupt. */ - VIC.PIC0.LONG = ( 1UL << 23UL ); - - /* Call the handler that is part of the common code - this is where the - non-portable code ends and the actual test is performed. */ - portYIELD_FROM_ISR( xFirstTimerHandler() ); -} -/*-----------------------------------------------------------*/ - -void vCMT_1_Channel_1_ISR( void ) -{ - /* Clear the interrupt. */ - VIC.PIC0.LONG = ( 1UL << 24UL ); - - /* Call the handler that is part of the common code - this is where the - non-portable code ends and the actual test is performed. */ - portYIELD_FROM_ISR( xSecondTimerHandler() ); -} -/*-----------------------------------------------------------*/ - -/* - * The RZ/T vectors directly to a peripheral specific interrupt handler, rather - * than using the Cortex-R IRQ vector. Therefore each interrupt handler - * installed by the application must follow the examples below, which save a - * pointer to a standard C function in the pxISRFunction variable, before - * branching to the FreeRTOS IRQ handler. The FreeRTOS IRQ handler then manages - * interrupt entry (including interrupt nesting), before calling the C function - * saved in the pxISRFunction variable. NOTE: The entry points are naked - * functions - do not add C code to these functions. - */ -#ifdef __GNUC__ - /* The IAR equivalent is implemented in - $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */ - static void vCMT_1_Channel_0_ISR_Entry( void ) - { - __asm volatile ( \ - "PUSH {r0-r1} \t\n" \ - "LDR r0, =pxISRFunction \t\n" \ - "LDR r1, =vCMT_1_Channel_0_ISR \t\n" \ - "STR r1, [r0] \t\n" \ - "POP {r0-r1} \t\n" \ - "B FreeRTOS_IRQ_Handler " - ); - } -#endif /* __GNUC__ */ -/*-----------------------------------------------------------*/ - -#ifdef __GNUC__ - /* The IAR equivalent is implemented in - $PROJ_DIR$/System/IAR/Interrupt_Entry_Stubs.asm */ - static void vCMT_1_Channel_1_ISR_Entry( void ) - { - __asm volatile ( \ - "PUSH {r0-r1} \t\n" \ - "LDR r0, =pxISRFunction \t\n" \ - "LDR r1, =vCMT_1_Channel_1_ISR \t\n" \ - "STR r1, [r0] \t\n" \ - "POP {r0-r1} \t\n" \ - "B FreeRTOS_IRQ_Handler " - ); - } -#endif /* __GNUC__ */ - - - - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.h deleted file mode 100644 index fcf9f8c1f..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#ifndef INT_QUEUE_TIMER_H -#define INT_QUEUE_TIMER_H - -void vInitialiseTimerForIntQueueTest( void ); -portBASE_TYPE xTimer0Handler( void ); -portBASE_TYPE xTimer1Handler( void ); - -#endif - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/main_full.c deleted file mode 100644 index f80371559..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/main_full.c +++ /dev/null @@ -1,513 +0,0 @@ -/* - FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky - * style project, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to - * select between the two. See the notes on using - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the - * comprehensive version. - * - * NOTE 2: This file only contains the source code that is specific to the - * full demo. Generic functions, such FreeRTOS hook functions, and functions - * required to configure the hardware, are defined in main.c. - * - ****************************************************************************** - * - * main_full() creates all the demo application tasks and software timers, then - * starts the scheduler. The web documentation provides more details of the - * standard demo application tasks, which provide no particular functionality, - * but do provide a good example of how to use the FreeRTOS API. - * - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Reg test" tasks - These fill both the core and floating point registers with - * known values, then check that each register maintains its expected value for - * the lifetime of the task. Each task uses a different set of values. The reg - * test tasks execute with a very low priority, so get preempted very - * frequently. A register containing an unexpected value is indicative of an - * error in the context switching mechanism. - * - * "Check" task - The check task period is initially set to three seconds. The - * task checks that all the standard demo tasks, and the register check tasks, - * are not only still executing, but are executing without reporting any errors. - * If the check task discovers that a task has either stalled, or reported an - * error, then it changes its own execution period from the initial three - * seconds, to just 200ms. The check task also toggles an LED each time it is - * called. This provides a visual indication of the system status: If the LED - * toggles every three seconds, then no issues have been discovered. If the LED - * toggles every 200ms, then an issue has been discovered with at least one - * task. - */ - -/* Standard includes. */ -#include - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "semphr.h" - -/* Standard demo application includes. */ -#include "flop.h" -#include "semtest.h" -#include "dynamic.h" -#include "BlockQ.h" -#include "blocktim.h" -#include "countsem.h" -#include "GenQTest.h" -#include "recmutex.h" -#include "death.h" -#include "partest.h" -#include "comtest2.h" -#include "serial.h" -#include "TimerDemo.h" -#include "QueueOverwrite.h" -#include "IntQueue.h" -#include "EventGroupsDemo.h" -#include "TaskNotify.h" -#include "IntSemTest.h" - -/* Renesas includes. */ -#include "r_cg_macrodriver.h" -#include "r_cg_userdefine.h" - -/* Priorities for the demo application tasks. */ -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) -#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) -#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) -#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) - -/* The priority used by the UART command console task. */ -#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) - -/* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) - -/* The period after which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) - -/* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) - -/* Parameters that are passed into the register check tasks solely for the -purpose of ensuring parameters are passed into tasks correctly. */ -#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) -#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) - -/* The base period used by the timer test tasks. */ -#define mainTIMER_TEST_PERIOD ( 50 ) - -/*-----------------------------------------------------------*/ - -/* - * Entry point for the comprehensive demo (as opposed to the simple blinky - * demo). - */ -void main_full( void ); - -/* - * The full demo includes some functionality called from the tick hook. - */ -void vFullDemoTickHook( void ); - - /* - * The check task, as described at the top of this file. - */ -static void prvCheckTask( void *pvParameters ); - -/* - * Register check tasks, and the tasks used to write over and check the contents - * of the FPU registers, as described at the top of this file. The nature of - * these files necessitates that they are written in an assembly file, but the - * entry points are kept in the C file for the convenience of checking the task - * parameter. - */ -static void prvRegTestTaskEntry1( void *pvParameters ); -extern void vRegTest1Implementation( void ); -static void prvRegTestTaskEntry2( void *pvParameters ); -extern void vRegTest2Implementation( void ); - -/* - * A high priority task that does nothing other than execute at a pseudo random - * time to ensure the other test tasks don't just execute in a repeating - * pattern. - */ -static void prvPseudoRandomiser( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The following two variables are used to communicate the status of the -register check tasks to the check task. If the variables keep incrementing, -then the register check tasks have not discovered any errors. If a variable -stops incrementing, then an error has been found. */ -volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; - -/* String for display in the web server. It is set to an error message if the -check task detects an error. */ -const char *pcStatusMessage = "All tasks running without error"; -/*-----------------------------------------------------------*/ - -void main_full( void ) -{ - /* Start all the other standard demo/test tasks. They have no particular - functionality, but do demonstrate how to use the FreeRTOS API and test the - kernel port. */ - vStartInterruptQueueTasks(); - vStartDynamicPriorityTasks(); - vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartGenericQueueTasks( tskIDLE_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); - vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); - vStartEventGroupTasks(); - vStartTaskNotifyTask(); - vStartInterruptSemaphoreTasks(); - - /* Create the register check tasks, as described at the top of this file */ - xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); - xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); - - /* Create the task that just adds a little random behaviour. */ - xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); - - /* Create the task that performs the 'check' functionality, as described at - the top of this file. */ - xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); - - /* The set of tasks created by the following function call have to be - created last as they keep account of the number of tasks they expect to see - running. */ - vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was either insufficient FreeRTOS heap memory available for the idle - and/or timer tasks to be created, or vTaskStartScheduler() was called from - User mode. See the memory management section on the FreeRTOS web site for - more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The - mode from which main() is called is set in the C start up code and must be - a privileged mode (not user mode). */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvCheckTask( void *pvParameters ) -{ -TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; -TickType_t xLastExecutionTime; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorFound = pdFALSE; - - /* Just to stop compiler warnings. */ - ( void ) pvParameters; - - /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() - works correctly. */ - xLastExecutionTime = xTaskGetTickCount(); - - /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. The onboard LED is toggled on each iteration. - If an error is detected then the delay period is decreased from - mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the - effect of increasing the rate at which the onboard LED toggles, and in so - doing gives visual feedback of the system status. */ - for( ;; ) - { - /* Delay until it is time to execute again. */ - vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ - if( xAreIntQueueTasksStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 0UL; - } - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 1UL; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 2UL; - } - - if( xAreBlockingQueuesStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 3UL; - } - - if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 4UL; - } - - if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 5UL; - } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 6UL; - } - - if( xIsCreateTaskStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 7UL; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 8UL; - } - - if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) - { - ulErrorFound |= 1UL << 9UL; - } - - if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 10UL; - } - - if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) - { - ulErrorFound |= 1UL << 11UL; - } - - if( xAreEventGroupTasksStillRunning() != pdPASS ) - { - ulErrorFound |= 1UL << 12UL; - } - - if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 13UL; - } - - if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFound |= 1UL << 14UL; - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound |= 1UL << 15UL; - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound |= 1UL << 16UL; - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then - everything is ok. A faster toggle indicates an error. */ - LED2 = !LED2; - - if( ulErrorFound != pdFALSE ) - { - /* An error has been detected in one of the tasks - flash the LED - at a higher frequency to give visible feedback that something has - gone wrong (it might just be that the loop back connector required - by the comtest tasks has not been fitted). */ - xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; - pcStatusMessage = "Error found in at least one task."; - } - } -} -/*-----------------------------------------------------------*/ - -static void prvRegTestTaskEntry1( void *pvParameters ) -{ - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) - { - /* The reg test task also tests the floating point registers. Tasks - that use the floating point unit must call vPortTaskUsesFPU() before - any floating point instructions are executed. */ - vPortTaskUsesFPU(); - - /* Start the part of the test that is written in assembler. */ - vRegTest1Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check timer will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); -} -/*-----------------------------------------------------------*/ - -static void prvRegTestTaskEntry2( void *pvParameters ) -{ - /* Although the regtest task is written in assembler, its entry point is - written in C for convenience of checking the task parameter is being passed - in correctly. */ - if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) - { - /* The reg test task also tests the floating point registers. Tasks - that use the floating point unit must call vPortTaskUsesFPU() before - any floating point instructions are executed. */ - vPortTaskUsesFPU(); - - /* Start the part of the test that is written in assembler. */ - vRegTest2Implementation(); - } - - /* The following line will only execute if the task parameter is found to - be incorrect. The check timer will detect that the regtest loop counter is - not being incremented and flag an error. */ - vTaskDelete( NULL ); -} -/*-----------------------------------------------------------*/ - -static void prvPseudoRandomiser( void *pvParameters ) -{ -const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); -volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; - - /* This task does nothing other than ensure there is a little bit of - disruption in the scheduling pattern of the other tasks. Normally this is - done by generating interrupts at pseudo random times. */ - for( ;; ) - { - ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; - ulValue = ( ulNextRand >> 16UL ) & 0xffUL; - - if( ulValue < ulMinDelay ) - { - ulValue = ulMinDelay; - } - - vTaskDelay( ulValue ); - - while( ulValue > 0 ) - { - __asm volatile( "NOP" ); - __asm volatile( "NOP" ); - __asm volatile( "NOP" ); - __asm volatile( "NOP" ); - - ulValue--; - } - } -} -/*-----------------------------------------------------------*/ - -void vFullDemoTickHook( void ) -{ - /* The full demo includes a software timer demo/test that requires - prodding periodically from the tick interrupt. */ - vTimerPeriodicISRTests(); - - /* Call the periodic queue overwrite from ISR demo. */ - vQueueOverwritePeriodicISRDemo(); - - /* Call the periodic event group from ISR demo. */ - vPeriodicEventGroupsProcessing(); - - /* Use task notifications from an interrupt. */ - xNotifyTaskFromISR(); - - /* Use mutexes from interrupts. */ - vInterruptSemaphorePeriodicTest(); -} - - - - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_GCC.S b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_GCC.S deleted file mode 100644 index 8de8a6e8e..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_GCC.S +++ /dev/null @@ -1,464 +0,0 @@ -/* - FreeRTOS V8.2.2 - Copyright (C) 2014 Real Time Engineers Ltd. - - FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT - http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS tutorial books are available in pdf and paperback. * - * Complete, revised, and edited pdf reference manuals are also * - * available. * - * * - * Purchasing FreeRTOS documentation will not only help you, by * - * ensuring you get running as quickly as possible and with an * - * in-depth knowledge of how to use FreeRTOS, it will also help * - * the FreeRTOS project to continue with its mission of providing * - * professional grade, cross platform, de facto standard solutions * - * for microcontrollers - completely free of charge! * - * * - * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * - * * - * Thank you for using FreeRTOS, and thank you for your support! * - * * - *************************************************************************** - - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - - >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to - distribute a combined work that includes FreeRTOS without being obliged to - provide the source code for proprietary components outside of the FreeRTOS - kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. See the GNU General Public License for more - details. You should have received a copy of the GNU General Public License - and the FreeRTOS license exception along with FreeRTOS; if not itcan be - viewed here: http://www.freertos.org/a00114.html and also obtained by - writing to Real Time Engineers Ltd., contact details for whom are available - on the FreeRTOS WEB site. - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, and our new - fully thread aware and reentrant UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems, who sell the code with commercial support, - indemnification and middleware, under the OpenRTOS brand. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. -*/ - - .global vRegTest1Implementation - .global vRegTest2Implementation - .extern ulRegTest1LoopCounter - .extern ulRegTest2LoopCounter - - .text - .arm - - /* This function is explained in the comments at the top of main-full.c. */ -.type vRegTest1Implementation, %function -vRegTest1Implementation: - - /* Fill each general purpose register with a known value. */ - mov r0, #0xFF - mov r1, #0x11 - mov r2, #0x22 - mov r3, #0x33 - mov r4, #0x44 - mov r5, #0x55 - mov r6, #0x66 - mov r7, #0x77 - mov r8, #0x88 - mov r9, #0x99 - mov r10, #0xAA - mov r11, #0xBB - mov r12, #0xCC - mov r14, #0xEE - - - /* Fill each FPU register with a known value. */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - - /* Loop, checking each itteration that each register still contains the - expected value. */ -reg1_loop: - /* Yield to increase test coverage */ - svc 0 - - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #0xFF - bne reg1_error_loopf - cmp r1, #0x11 - bne reg1_error_loopf - vmov r0, r1, d1 - cmp r0, #0x22 - bne reg1_error_loopf - cmp r1, #0x33 - bne reg1_error_loopf - vmov r0, r1, d2 - cmp r0, #0x44 - bne reg1_error_loopf - cmp r1, #0x55 - bne reg1_error_loopf - vmov r0, r1, d3 - cmp r0, #0x66 - bne reg1_error_loopf - cmp r1, #0x77 - bne reg1_error_loopf - vmov r0, r1, d4 - cmp r0, #0x88 - bne reg1_error_loopf - cmp r1, #0x99 - bne reg1_error_loopf - vmov r0, r1, d5 - cmp r0, #0xAA - bne reg1_error_loopf - cmp r1, #0xBB - bne reg1_error_loopf - vmov r0, r1, d6 - cmp r0, #0xFF - bne reg1_error_loopf - cmp r1, #0x11 - bne reg1_error_loopf - vmov r0, r1, d7 - cmp r0, #0x22 - bne reg1_error_loopf - cmp r1, #0x33 - bne reg1_error_loopf - vmov r0, r1, d8 - cmp r0, #0x44 - bne reg1_error_loopf - cmp r1, #0x55 - bne reg1_error_loopf - vmov r0, r1, d9 - cmp r0, #0x66 - bne reg1_error_loopf - cmp r1, #0x77 - bne reg1_error_loopf - vmov r0, r1, d10 - cmp r0, #0x88 - bne reg1_error_loopf - cmp r1, #0x99 - bne reg1_error_loopf - vmov r0, r1, d11 - cmp r0, #0xAA - bne reg1_error_loopf - cmp r1, #0xBB - bne reg1_error_loopf - vmov r0, r1, d12 - cmp r0, #0xFF - bne reg1_error_loopf - cmp r1, #0x11 - bne reg1_error_loopf - vmov r0, r1, d13 - cmp r0, #0x22 - bne reg1_error_loopf - cmp r1, #0x33 - bne reg1_error_loopf - vmov r0, r1, d14 - cmp r0, #0x44 - bne reg1_error_loopf - cmp r1, #0x55 - bne reg1_error_loopf - vmov r0, r1, d15 - cmp r0, #0x66 - bne reg1_error_loopf - cmp r1, #0x77 - bne reg1_error_loopf - - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg1_loopf_pass - -reg1_error_loopf: - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg1_error_loopf - -reg1_loopf_pass: - - /* Test each general purpose register to check that it still contains the - expected known value, jumping to reg1_error_loop if any register contains - an unexpected value. */ - cmp r0, #0xFF - bne reg1_error_loop - cmp r1, #0x11 - bne reg1_error_loop - cmp r2, #0x22 - bne reg1_error_loop - cmp r3, #0x33 - bne reg1_error_loop - cmp r4, #0x44 - bne reg1_error_loop - cmp r5, #0x55 - bne reg1_error_loop - cmp r6, #0x66 - bne reg1_error_loop - cmp r7, #0x77 - bne reg1_error_loop - cmp r8, #0x88 - bne reg1_error_loop - cmp r9, #0x99 - bne reg1_error_loop - cmp r10, #0xAA - bne reg1_error_loop - cmp r11, #0xBB - bne reg1_error_loop - cmp r12, #0xCC - bne reg1_error_loop - cmp r14, #0xEE - bne reg1_error_loop - - /* Everything passed, increment the loop counter. */ - push { r0-r1 } - ldr r0, =ulRegTest1LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r0-r1 } - - /* Start again. */ - b reg1_loop - -reg1_error_loop: - /* If this line is hit then there was an error in a core register value. - The loop ensures the loop counter stops incrementing. */ - b reg1_error_loop - nop - -/*-----------------------------------------------------------*/ - -.type vRegTest2Implementation, %function -vRegTest2Implementation: - - /* Put a known value in each register. */ - mov r0, #0xFF000000 - mov r1, #0x11000000 - mov r2, #0x22000000 - mov r3, #0x33000000 - mov r4, #0x44000000 - mov r5, #0x55000000 - mov r6, #0x66000000 - mov r7, #0x77000000 - mov r8, #0x88000000 - mov r9, #0x99000000 - mov r10, #0xAA000000 - mov r11, #0xBB000000 - mov r12, #0xCC000000 - mov r14, #0xEE000000 - - /* Likewise the floating point registers */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - - /* Loop, checking each itteration that each register still contains the - expected value. */ -reg2_loop: - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #0xFF000000 - bne reg2_error_loopf - cmp r1, #0x11000000 - bne reg2_error_loopf - vmov r0, r1, d1 - cmp r0, #0x22000000 - bne reg2_error_loopf - cmp r1, #0x33000000 - bne reg2_error_loopf - vmov r0, r1, d2 - cmp r0, #0x44000000 - bne reg2_error_loopf - cmp r1, #0x55000000 - bne reg2_error_loopf - vmov r0, r1, d3 - cmp r0, #0x66000000 - bne reg2_error_loopf - cmp r1, #0x77000000 - bne reg2_error_loopf - vmov r0, r1, d4 - cmp r0, #0x88000000 - bne reg2_error_loopf - cmp r1, #0x99000000 - bne reg2_error_loopf - vmov r0, r1, d5 - cmp r0, #0xAA000000 - bne reg2_error_loopf - cmp r1, #0xBB000000 - bne reg2_error_loopf - vmov r0, r1, d6 - cmp r0, #0xFF000000 - bne reg2_error_loopf - cmp r1, #0x11000000 - bne reg2_error_loopf - vmov r0, r1, d7 - cmp r0, #0x22000000 - bne reg2_error_loopf - cmp r1, #0x33000000 - bne reg2_error_loopf - vmov r0, r1, d8 - cmp r0, #0x44000000 - bne reg2_error_loopf - cmp r1, #0x55000000 - bne reg2_error_loopf - vmov r0, r1, d9 - cmp r0, #0x66000000 - bne reg2_error_loopf - cmp r1, #0x77000000 - bne reg2_error_loopf - vmov r0, r1, d10 - cmp r0, #0x88000000 - bne reg2_error_loopf - cmp r1, #0x99000000 - bne reg2_error_loopf - vmov r0, r1, d11 - cmp r0, #0xAA000000 - bne reg2_error_loopf - cmp r1, #0xBB000000 - bne reg2_error_loopf - vmov r0, r1, d12 - cmp r0, #0xFF000000 - bne reg2_error_loopf - cmp r1, #0x11000000 - bne reg2_error_loopf - vmov r0, r1, d13 - cmp r0, #0x22000000 - bne reg2_error_loopf - cmp r1, #0x33000000 - bne reg2_error_loopf - vmov r0, r1, d14 - cmp r0, #0x44000000 - bne reg2_error_loopf - cmp r1, #0x55000000 - bne reg2_error_loopf - vmov r0, r1, d15 - cmp r0, #0x66000000 - bne reg2_error_loopf - cmp r1, #0x77000000 - bne reg2_error_loopf - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg2_loopf_pass - -reg2_error_loopf: - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg2_error_loopf - -reg2_loopf_pass: - - cmp r0, #0xFF000000 - bne reg2_error_loop - cmp r1, #0x11000000 - bne reg2_error_loop - cmp r2, #0x22000000 - bne reg2_error_loop - cmp r3, #0x33000000 - bne reg2_error_loop - cmp r4, #0x44000000 - bne reg2_error_loop - cmp r5, #0x55000000 - bne reg2_error_loop - cmp r6, #0x66000000 - bne reg2_error_loop - cmp r7, #0x77000000 - bne reg2_error_loop - cmp r8, #0x88000000 - bne reg2_error_loop - cmp r9, #0x99000000 - bne reg2_error_loop - cmp r10, #0xAA000000 - bne reg2_error_loop - cmp r11, #0xBB000000 - bne reg2_error_loop - cmp r12, #0xCC000000 - bne reg2_error_loop - cmp r14, #0xEE000000 - bne reg2_error_loop - - /* Everything passed, increment the loop counter. */ - push { r0-r1 } - ldr r0, =ulRegTest2LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r0-r1 } - - /* Start again. */ - b reg2_loop - -reg2_error_loop: - /* If this line is hit then there was an error in a core register value. - The loop ensures the loop counter stops incrementing. */ - b reg2_error_loop - nop - - - .end - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_IAR.asm b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_IAR.asm deleted file mode 100644 index 653edaaf4..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/reg_test_IAR.asm +++ /dev/null @@ -1,462 +0,0 @@ -/* - FreeRTOS V8.2.2 - Copyright (C) 2014 Real Time Engineers Ltd. - - FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT - http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS tutorial books are available in pdf and paperback. * - * Complete, revised, and edited pdf reference manuals are also * - * available. * - * * - * Purchasing FreeRTOS documentation will not only help you, by * - * ensuring you get running as quickly as possible and with an * - * in-depth knowledge of how to use FreeRTOS, it will also help * - * the FreeRTOS project to continue with its mission of providing * - * professional grade, cross platform, de facto standard solutions * - * for microcontrollers - completely free of charge! * - * * - * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * - * * - * Thank you for using FreeRTOS, and thank you for your support! * - * * - *************************************************************************** - - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation AND MODIFIED BY the FreeRTOS exception. - - >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to - distribute a combined work that includes FreeRTOS without being obliged to - provide the source code for proprietary components outside of the FreeRTOS - kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. See the GNU General Public License for more - details. You should have received a copy of the GNU General Public License - and the FreeRTOS license exception along with FreeRTOS; if not itcan be - viewed here: http://www.freertos.org/a00114.html and also obtained by - writing to Real Time Engineers Ltd., contact details for whom are available - on the FreeRTOS WEB site. - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, and our new - fully thread aware and reentrant UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems, who sell the code with commercial support, - indemnification and middleware, under the OpenRTOS brand. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. -*/ - - PUBLIC vRegTest1Implementation - PUBLIC vRegTest2Implementation - EXTERN ulRegTest1LoopCounter - EXTERN ulRegTest2LoopCounter - - SECTION intvec:CODE:ROOT(2) - ARM - - /* This function is explained in the comments at the top of main-full.c. */ -vRegTest1Implementation: - - /* Fill each general purpose register with a known value. */ - mov r0, #0xFF - mov r1, #0x11 - mov r2, #0x22 - mov r3, #0x33 - mov r4, #0x44 - mov r5, #0x55 - mov r6, #0x66 - mov r7, #0x77 - mov r8, #0x88 - mov r9, #0x99 - mov r10, #0xAA - mov r11, #0xBB - mov r12, #0xCC - mov r14, #0xEE - - - /* Fill each FPU register with a known value. */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - - /* Loop, checking each itteration that each register still contains the - expected value. */ -reg1_loop: - /* Yield to increase test coverage */ - svc 0 - - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #0xFF - bne reg1_error_loopf - cmp r1, #0x11 - bne reg1_error_loopf - vmov r0, r1, d1 - cmp r0, #0x22 - bne reg1_error_loopf - cmp r1, #0x33 - bne reg1_error_loopf - vmov r0, r1, d2 - cmp r0, #0x44 - bne reg1_error_loopf - cmp r1, #0x55 - bne reg1_error_loopf - vmov r0, r1, d3 - cmp r0, #0x66 - bne reg1_error_loopf - cmp r1, #0x77 - bne reg1_error_loopf - vmov r0, r1, d4 - cmp r0, #0x88 - bne reg1_error_loopf - cmp r1, #0x99 - bne reg1_error_loopf - vmov r0, r1, d5 - cmp r0, #0xAA - bne reg1_error_loopf - cmp r1, #0xBB - bne reg1_error_loopf - vmov r0, r1, d6 - cmp r0, #0xFF - bne reg1_error_loopf - cmp r1, #0x11 - bne reg1_error_loopf - vmov r0, r1, d7 - cmp r0, #0x22 - bne reg1_error_loopf - cmp r1, #0x33 - bne reg1_error_loopf - vmov r0, r1, d8 - cmp r0, #0x44 - bne reg1_error_loopf - cmp r1, #0x55 - bne reg1_error_loopf - vmov r0, r1, d9 - cmp r0, #0x66 - bne reg1_error_loopf - cmp r1, #0x77 - bne reg1_error_loopf - vmov r0, r1, d10 - cmp r0, #0x88 - bne reg1_error_loopf - cmp r1, #0x99 - bne reg1_error_loopf - vmov r0, r1, d11 - cmp r0, #0xAA - bne reg1_error_loopf - cmp r1, #0xBB - bne reg1_error_loopf - vmov r0, r1, d12 - cmp r0, #0xFF - bne reg1_error_loopf - cmp r1, #0x11 - bne reg1_error_loopf - vmov r0, r1, d13 - cmp r0, #0x22 - bne reg1_error_loopf - cmp r1, #0x33 - bne reg1_error_loopf - vmov r0, r1, d14 - cmp r0, #0x44 - bne reg1_error_loopf - cmp r1, #0x55 - bne reg1_error_loopf - vmov r0, r1, d15 - cmp r0, #0x66 - bne reg1_error_loopf - cmp r1, #0x77 - bne reg1_error_loopf - - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg1_loopf_pass - -reg1_error_loopf: - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg1_error_loopf - -reg1_loopf_pass: - - /* Test each general purpose register to check that it still contains the - expected known value, jumping to reg1_error_loop if any register contains - an unexpected value. */ - cmp r0, #0xFF - bne reg1_error_loop - cmp r1, #0x11 - bne reg1_error_loop - cmp r2, #0x22 - bne reg1_error_loop - cmp r3, #0x33 - bne reg1_error_loop - cmp r4, #0x44 - bne reg1_error_loop - cmp r5, #0x55 - bne reg1_error_loop - cmp r6, #0x66 - bne reg1_error_loop - cmp r7, #0x77 - bne reg1_error_loop - cmp r8, #0x88 - bne reg1_error_loop - cmp r9, #0x99 - bne reg1_error_loop - cmp r10, #0xAA - bne reg1_error_loop - cmp r11, #0xBB - bne reg1_error_loop - cmp r12, #0xCC - bne reg1_error_loop - cmp r14, #0xEE - bne reg1_error_loop - - /* Everything passed, increment the loop counter. */ - push { r0-r1 } - ldr r0, =ulRegTest1LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r0-r1 } - - /* Start again. */ - b reg1_loop - -reg1_error_loop: - /* If this line is hit then there was an error in a core register value. - The loop ensures the loop counter stops incrementing. */ - b reg1_error_loop - nop - -/*-----------------------------------------------------------*/ - -vRegTest2Implementation: - - /* Put a known value in each register. */ - mov r0, #0xFF000000 - mov r1, #0x11000000 - mov r2, #0x22000000 - mov r3, #0x33000000 - mov r4, #0x44000000 - mov r5, #0x55000000 - mov r6, #0x66000000 - mov r7, #0x77000000 - mov r8, #0x88000000 - mov r9, #0x99000000 - mov r10, #0xAA000000 - mov r11, #0xBB000000 - mov r12, #0xCC000000 - mov r14, #0xEE000000 - - /* Likewise the floating point registers */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - - /* Loop, checking each itteration that each register still contains the - expected value. */ -reg2_loop: - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #0xFF000000 - bne reg2_error_loopf - cmp r1, #0x11000000 - bne reg2_error_loopf - vmov r0, r1, d1 - cmp r0, #0x22000000 - bne reg2_error_loopf - cmp r1, #0x33000000 - bne reg2_error_loopf - vmov r0, r1, d2 - cmp r0, #0x44000000 - bne reg2_error_loopf - cmp r1, #0x55000000 - bne reg2_error_loopf - vmov r0, r1, d3 - cmp r0, #0x66000000 - bne reg2_error_loopf - cmp r1, #0x77000000 - bne reg2_error_loopf - vmov r0, r1, d4 - cmp r0, #0x88000000 - bne reg2_error_loopf - cmp r1, #0x99000000 - bne reg2_error_loopf - vmov r0, r1, d5 - cmp r0, #0xAA000000 - bne reg2_error_loopf - cmp r1, #0xBB000000 - bne reg2_error_loopf - vmov r0, r1, d6 - cmp r0, #0xFF000000 - bne reg2_error_loopf - cmp r1, #0x11000000 - bne reg2_error_loopf - vmov r0, r1, d7 - cmp r0, #0x22000000 - bne reg2_error_loopf - cmp r1, #0x33000000 - bne reg2_error_loopf - vmov r0, r1, d8 - cmp r0, #0x44000000 - bne reg2_error_loopf - cmp r1, #0x55000000 - bne reg2_error_loopf - vmov r0, r1, d9 - cmp r0, #0x66000000 - bne reg2_error_loopf - cmp r1, #0x77000000 - bne reg2_error_loopf - vmov r0, r1, d10 - cmp r0, #0x88000000 - bne reg2_error_loopf - cmp r1, #0x99000000 - bne reg2_error_loopf - vmov r0, r1, d11 - cmp r0, #0xAA000000 - bne reg2_error_loopf - cmp r1, #0xBB000000 - bne reg2_error_loopf - vmov r0, r1, d12 - cmp r0, #0xFF000000 - bne reg2_error_loopf - cmp r1, #0x11000000 - bne reg2_error_loopf - vmov r0, r1, d13 - cmp r0, #0x22000000 - bne reg2_error_loopf - cmp r1, #0x33000000 - bne reg2_error_loopf - vmov r0, r1, d14 - cmp r0, #0x44000000 - bne reg2_error_loopf - cmp r1, #0x55000000 - bne reg2_error_loopf - vmov r0, r1, d15 - cmp r0, #0x66000000 - bne reg2_error_loopf - cmp r1, #0x77000000 - bne reg2_error_loopf - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg2_loopf_pass - -reg2_error_loopf: - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg2_error_loopf - -reg2_loopf_pass: - - cmp r0, #0xFF000000 - bne reg2_error_loop - cmp r1, #0x11000000 - bne reg2_error_loop - cmp r2, #0x22000000 - bne reg2_error_loop - cmp r3, #0x33000000 - bne reg2_error_loop - cmp r4, #0x44000000 - bne reg2_error_loop - cmp r5, #0x55000000 - bne reg2_error_loop - cmp r6, #0x66000000 - bne reg2_error_loop - cmp r7, #0x77000000 - bne reg2_error_loop - cmp r8, #0x88000000 - bne reg2_error_loop - cmp r9, #0x99000000 - bne reg2_error_loop - cmp r10, #0xAA000000 - bne reg2_error_loop - cmp r11, #0xBB000000 - bne reg2_error_loop - cmp r12, #0xCC000000 - bne reg2_error_loop - cmp r14, #0xEE000000 - bne reg2_error_loop - - /* Everything passed, increment the loop counter. */ - push { r0-r1 } - ldr r0, =ulRegTest2LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r0-r1 } - - /* Start again. */ - b reg2_loop - -reg2_error_loop: - /* If this line is hit then there was an error in a core register value. - The loop ensures the loop counter stops incrementing. */ - b reg2_error_loop - nop - - - END - diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/iodefine.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/iodefine.h deleted file mode 100644 index 366367f10..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/iodefine.h +++ /dev/null @@ -1,45398 +0,0 @@ -/********************************************************************************/ -/* */ -/* Device : RZ/T1 */ -/* File Name : iodefine.h */ -/* Abstract : Definition of I/O Register. */ -/* History : V0.8 (2015-02-23) [Hardware Manual Revision : 0.8] */ -/* Note : This is a typical example. */ -/* */ -/* Copyright(c) 2015 Renesas Electronics Corp. ,All Rights Reserved. */ -/* */ -/********************************************************************************/ -#ifndef __RZT1___IODEFINE_HEADER__ -#define __RZT1___IODEFINE_HEADER__ -struct st_bsc -{ - union - { - unsigned long LONG; - struct - { - unsigned long :9; - unsigned long BSZ:2; - unsigned long :1; - unsigned long TYPE:3; - unsigned long :1; - unsigned long IWRRS:3; - unsigned long IWRRD:3; - unsigned long IWRWS:3; - unsigned long IWRWD:3; - unsigned long IWW:3; - unsigned long :1; - } BIT; - } CS0BCR; - union - { - unsigned long LONG; - struct - { - unsigned long :9; - unsigned long BSZ:2; - unsigned long :1; - unsigned long TYPE:3; - unsigned long :1; - unsigned long IWRRS:3; - unsigned long IWRRD:3; - unsigned long IWRWS:3; - unsigned long IWRWD:3; - unsigned long IWW:3; - unsigned long :1; - } BIT; - } CS1BCR; - union - { - unsigned long LONG; - struct - { - unsigned long :9; - unsigned long BSZ:2; - unsigned long :1; - unsigned long TYPE:3; - unsigned long :1; - unsigned long IWRRS:3; - unsigned long IWRRD:3; - unsigned long IWRWS:3; - unsigned long IWRWD:3; - unsigned long IWW:3; - unsigned long :1; - } BIT; - } CS2BCR; - union - { - unsigned long LONG; - struct - { - unsigned long :9; - unsigned long BSZ:2; - unsigned long :1; - unsigned long TYPE:3; - unsigned long :1; - unsigned long IWRRS:3; - unsigned long IWRRD:3; - unsigned long IWRWS:3; - unsigned long IWRWD:3; - unsigned long IWW:3; - unsigned long :1; - } BIT; - } CS3BCR; - union - { - unsigned long LONG; - struct - { - unsigned long :9; - unsigned long BSZ:2; - unsigned long :1; - unsigned long TYPE:3; - unsigned long :1; - unsigned long IWRRS:3; - unsigned long IWRRD:3; - unsigned long IWRWS:3; - unsigned long IWRWD:3; - unsigned long IWW:3; - unsigned long :1; - } BIT; - } CS4BCR; - union - { - unsigned long LONG; - struct - { - unsigned long :9; - unsigned long BSZ:2; - unsigned long :1; - unsigned long TYPE:3; - unsigned long :1; - unsigned long IWRRS:3; - unsigned long IWRRD:3; - unsigned long IWRWS:3; - unsigned long IWRWD:3; - unsigned long IWW:3; - unsigned long :1; - } BIT; - } CS5BCR; - char wk0[12]; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long HW:2; - unsigned long :4; - unsigned long WM:1; - unsigned long WR:4; - unsigned long SW:2; - unsigned long :7; - unsigned long BAS:1; - unsigned long :11; - } BIT; - } CS0WCR_0; - union - { - unsigned long LONG; - struct - { - unsigned long :6; - unsigned long WM:1; - unsigned long W:4; - unsigned long :5; - unsigned long BW:2; - unsigned long :2; - unsigned long BST:2; - unsigned long :10; - } BIT; - } CS0WCR_1; - union - { - unsigned long LONG; - struct - { - unsigned long :6; - unsigned long WM:1; - unsigned long W:4; - unsigned long :5; - unsigned long BW:2; - unsigned long :14; - } BIT; - } CS0WCR_2; - } CS0WCR; - union - { - unsigned long LONG; - struct - { - unsigned long HW:2; - unsigned long :4; - unsigned long WM:1; - unsigned long WR:4; - unsigned long SW:2; - unsigned long :3; - unsigned long WW:3; - unsigned long :1; - unsigned long BAS:1; - unsigned long :11; - } BIT; - } CS1WCR; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long :6; - unsigned long WM:1; - unsigned long WR:4; - unsigned long :9; - unsigned long BAS:1; - unsigned long :11; - } BIT; - } CS2WCR_0; - union - { - unsigned long LONG; - struct - { - unsigned long :7; - unsigned long A2CL:2; - unsigned long :23; - } BIT; - } CS2WCR_1; - } CS2WCR; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long :6; - unsigned long WM:1; - unsigned long WR:4; - unsigned long :9; - unsigned long BAS:1; - unsigned long :11; - } BIT; - } CS3WCR_0; - union - { - unsigned long LONG; - struct - { - unsigned long WTRC:2; - unsigned long :1; - unsigned long TRWL:2; - unsigned long :2; - unsigned long A3CL:2; - unsigned long :1; - unsigned long WTRCD:2; - unsigned long :1; - unsigned long WTRP:2; - unsigned long :17; - } BIT; - } CS3WCR_1; - } CS3WCR; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long HW:2; - unsigned long :4; - unsigned long WM:1; - unsigned long WR:4; - unsigned long SW:2; - unsigned long :3; - unsigned long WW:3; - unsigned long :1; - unsigned long BAS:1; - unsigned long :11; - } BIT; - } CS4WCR_0; - union - { - unsigned long LONG; - struct - { - unsigned long HW:2; - unsigned long :4; - unsigned long WM:1; - unsigned long W:4; - unsigned long SW:2; - unsigned long :3; - unsigned long BW:2; - unsigned long :2; - unsigned long BST:2; - unsigned long :10; - } BIT; - } CS4WCR_1; - } CS4WCR; - union - { - unsigned long LONG; - struct - { - unsigned long HW:2; - unsigned long :4; - unsigned long WM:1; - unsigned long WR:4; - unsigned long SW:2; - unsigned long :3; - unsigned long WW:3; - unsigned long :1; - unsigned long MPXWBAS:1; - unsigned long SZSEL:1; - unsigned long :10; - } BIT; - } CS5WCR; - char wk1[12]; - union - { - unsigned long LONG; - struct - { - unsigned long A3COL:2; - unsigned long :1; - unsigned long A3ROW:2; - unsigned long :3; - unsigned long BACTV:1; - unsigned long PDOWN:1; - unsigned long RMODE:1; - unsigned long RFSH:1; - unsigned long :1; - unsigned long DEEP:1; - unsigned long :2; - unsigned long A2COL:2; - unsigned long :1; - unsigned long A2ROW:2; - unsigned long :11; - } BIT; - } SDCR; - union - { - unsigned long LONG; - } RTCSR; - unsigned long RTCNT; - unsigned long RTCOR; - char wk2[4]; - unsigned long TOSCOR0; - unsigned long TOSCOR1; - unsigned long TOSCOR2; - unsigned long TOSCOR3; - unsigned long TOSCOR4; - unsigned long TOSCOR5; - char wk3[8]; - union - { - unsigned long LONG; - struct - { - unsigned long CS0TOSTF:1; - unsigned long CS1TOSTF:1; - unsigned long CS2TOSTF:1; - unsigned long CS3TOSTF:1; - unsigned long CS4TOSTF:1; - unsigned long CS5TOSTF:1; - unsigned long :26; - } BIT; - } TOSTR; - union - { - unsigned long LONG; - struct - { - unsigned long CS0TOEN:1; - unsigned long CS1TOEN:1; - unsigned long CS2TOEN:1; - unsigned long CS3TOEN:1; - unsigned long CS4TOEN:1; - unsigned long CS5TOEN:1; - unsigned long :26; - } BIT; - } TOENR; - char wk4[2948]; - union - { - unsigned long LONG; - } CKIOSET; - char wk5[236]; - union - { - unsigned char BYTE; - } CKIOKEY; -}; - -struct st_clma0 -{ - union - { - unsigned char BYTE; - } CLMA0CTL0; - char wk0[7]; - union - { - unsigned short WORD; - struct - { - unsigned short CLMAnCMPL:12; - unsigned short :4; - } BIT; - } CLMA0CMPL; - char wk1[2]; - union - { - unsigned short WORD; - struct - { - unsigned short CLMAnCMPH:12; - unsigned short :4; - } BIT; - } CLMA0CMPH; - char wk2[2]; - union - { - unsigned char BYTE; - } CLMA0PCMD; - char wk3[3]; - union - { - unsigned char BYTE; - struct - { - unsigned char CLMAnPRERR:1; - unsigned char :7; - } BIT; - } CLMA0PS; -}; - -struct st_clma1 -{ - union - { - unsigned char BYTE; - } CLMA1CTL0; - char wk0[7]; - union - { - unsigned short WORD; - struct - { - unsigned short CLMAnCMPL:12; - unsigned short :4; - } BIT; - } CLMA1CMPL; - char wk1[2]; - union - { - unsigned short WORD; - struct - { - unsigned short CLMAnCMPH:12; - unsigned short :4; - } BIT; - } CLMA1CMPH; - char wk2[2]; - union - { - unsigned char BYTE; - } CLMA1PCMD; - char wk3[3]; - union - { - unsigned char BYTE; - struct - { - unsigned char CLMAnPRERR:1; - unsigned char :7; - } BIT; - } CLMA1PS; -}; - -struct st_clma2 -{ - union - { - unsigned char BYTE; - } CLMA2CTL0; - char wk0[7]; - union - { - unsigned short WORD; - struct - { - unsigned short CLMAnCMPL:12; - unsigned short :4; - } BIT; - } CLMA2CMPL; - char wk1[2]; - union - { - unsigned short WORD; - struct - { - unsigned short CLMAnCMPH:12; - unsigned short :4; - } BIT; - } CLMA2CMPH; - char wk2[2]; - union - { - unsigned char BYTE; - } CLMA2PCMD; - char wk3[3]; - union - { - unsigned char BYTE; - struct - { - unsigned char CLMAnPRERR:1; - unsigned char :7; - } BIT; - } CLMA2PS; -}; - -struct st_cmt -{ - union - { - unsigned short WORD; - struct - { - unsigned short STR0:1; - unsigned short STR1:1; - unsigned short :14; - } BIT; - } CMSTR0; - char wk0[30]; - union - { - unsigned short WORD; - struct - { - unsigned short STR2:1; - unsigned short STR3:1; - unsigned short :14; - } BIT; - } CMSTR1; - char wk1[30]; - union - { - unsigned short WORD; - struct - { - unsigned short STR4:1; - unsigned short STR5:1; - unsigned short :14; - } BIT; - } CMSTR2; -}; - -struct st_cmt0 -{ - union - { - unsigned short WORD; - struct - { - unsigned short CKS:2; - unsigned short :4; - unsigned short CMIE:1; - unsigned short :9; - } BIT; - } CMCR; - unsigned short CMCNT; - unsigned short CMCOR; -}; - -struct st_cmtw -{ - union - { - unsigned long LONG; - struct - { - unsigned long NF0EN:1; - unsigned long NF1EN:1; - unsigned long NFCS0:2; - unsigned long :28; - } BIT; - } NFCR0; - union - { - unsigned long LONG; - struct - { - unsigned long NF2EN:1; - unsigned long NF3EN:1; - unsigned long NFCS1:2; - unsigned long :28; - } BIT; - } NFCR1; - char wk0[8]; - union - { - unsigned long LONG; - struct - { - unsigned long DMERSL:3; - unsigned long :29; - } BIT; - } ECDMESLR; -}; - -struct st_cmtw0 -{ - union - { - unsigned short WORD; - struct - { - unsigned short STR:1; - unsigned short :15; - } BIT; - } CMWSTR; - char wk0[2]; - union - { - unsigned short WORD; - struct - { - unsigned short CKS:2; - unsigned short :1; - unsigned short CMWIE:1; - unsigned short IC0IE:1; - unsigned short IC1IE:1; - unsigned short OC0IE:1; - unsigned short OC1IE:1; - unsigned short :1; - unsigned short CMS:1; - unsigned short :3; - unsigned short CCLR:3; - } BIT; - } CMWCR; - char wk1[2]; - union - { - unsigned short WORD; - struct - { - unsigned short IC0:2; - unsigned short IC1:2; - unsigned short IC0E:1; - unsigned short IC1E:1; - unsigned short :2; - unsigned short OC0:2; - unsigned short OC1:2; - unsigned short OC0E:1; - unsigned short OC1E:1; - unsigned short :1; - unsigned short CMWE:1; - } BIT; - } CMWIOR; - char wk2[6]; - unsigned long CMWCNT; - unsigned long CMWCOR; - unsigned long CMWICR0; - unsigned long CMWICR1; - unsigned long CMWOCR0; - unsigned long CMWOCR1; -}; - -struct st_crc -{ - union - { - unsigned long LONG; - struct - { - unsigned long DCRA0CIN:32; - } BIT; - } CRCDIR; - union - { - unsigned long LONG; - struct - { - unsigned long DCRA0COUT:32; - } BIT; - } CRCDOR; - char wk0[24]; - union - { - unsigned char BYTE; - struct - { - unsigned char DCRA0POL:2; - unsigned char :2; - unsigned char DCRA0ISZ:2; - unsigned char :2; - } BIT; - } CRCCR; -}; - -struct st_dma0 -{ - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_0_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_0_W; - } N0SA_0; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_0; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_0; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_0_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_0_W; - } N1SA_0; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_0; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_0; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_0; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_0; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_0; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_0; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_0; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_0; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_0; - char wk0[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_0; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_0; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_1_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_1_W; - } N0SA_1; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_1; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_1; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_1_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_1_W; - } N1SA_1; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_1; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_1; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_1; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_1; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_1; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_1; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_1; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_1; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_1; - char wk1[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_1; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_1; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_2_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_2_W; - } N0SA_2; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_2; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_2; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_2_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_2_W; - } N1SA_2; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_2; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_2; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_2; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_2; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_2; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_2; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_2; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_2; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_2; - char wk2[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_2; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_2; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_3_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_3_W; - } N0SA_3; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_3; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_3; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_3_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_3_W; - } N1SA_3; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_3; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_3; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_3; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_3; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_3; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_3; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_3; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_3; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_3; - char wk3[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_3; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_3; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_4_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_4_W; - } N0SA_4; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_4; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_4; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_4_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_4_W; - } N1SA_4; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_4; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_4; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_4; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_4; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_4; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_4; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_4; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_4; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_4; - char wk4[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_4; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_4; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_5_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_5_W; - } N0SA_5; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_5; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_5; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_5_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_5_W; - } N1SA_5; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_5; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_5; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_5; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_5; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_5; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_5; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_5; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_5; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_5; - char wk5[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_5; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_5; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_6_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_6_W; - } N0SA_6; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_6; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_6; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_6_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_6_W; - } N1SA_6; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_6; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_6; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_6; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_6; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_6; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_6; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_6; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_6; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_6; - char wk6[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_6; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_6; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_7_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_7_W; - } N0SA_7; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_7; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_7; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_7_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_7_W; - } N1SA_7; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_7; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_7; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_7; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_7; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_7; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_7; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_7; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_7; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_7; - char wk7[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_7; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_7; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_0; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_0; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_0; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_0; - char wk8[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_1; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_1; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_1; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_1; - char wk9[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_2; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_2; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_2; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_2; - char wk10[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_3; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_3; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_3; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_3; - char wk11[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_4; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_4; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_4; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_4; - char wk12[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_5; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_5; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_5; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_5; - char wk13[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_6; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_6; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_6; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_6; - char wk14[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_7; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_7; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_7; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_7; - char wk15[16]; - union - { - unsigned long LONG; - struct - { - unsigned long PR:1; - unsigned long :31; - } BIT; - } DMAC0_DCTRL_A; - union - { - unsigned long LONG; - struct - { - unsigned long :8; - unsigned long DITVL:8; - unsigned long :16; - } BIT; - } DMAC0_DSCITVL_A; - char wk16[8]; - union - { - unsigned long LONG; - struct - { - unsigned long EN08:1; - unsigned long EN19:1; - unsigned long EN210:1; - unsigned long EN311:1; - unsigned long EN412:1; - unsigned long EN513:1; - unsigned long EN614:1; - unsigned long EN715:1; - unsigned long :24; - } BIT; - } DMAC0_DST_EN_A; - union - { - unsigned long LONG; - struct - { - unsigned long ER08:1; - unsigned long ER19:1; - unsigned long ER210:1; - unsigned long ER311:1; - unsigned long ER412:1; - unsigned long ER513:1; - unsigned long ER614:1; - unsigned long ER715:1; - unsigned long :24; - } BIT; - } DMAC0_DST_ER_A; - union - { - unsigned long LONG; - struct - { - unsigned long END08:1; - unsigned long END19:1; - unsigned long END210:1; - unsigned long END311:1; - unsigned long END412:1; - unsigned long END513:1; - unsigned long END614:1; - unsigned long END715:1; - unsigned long :24; - } BIT; - } DMAC0_DST_END_A; - char wk17[4]; - union - { - unsigned long LONG; - struct - { - unsigned long SUS08:1; - unsigned long SUS19:1; - unsigned long SUS210:1; - unsigned long SUS311:1; - unsigned long SUS412:1; - unsigned long SUS513:1; - unsigned long SUS614:1; - unsigned long SUS715:1; - unsigned long :24; - } BIT; - } DMAC0_DST_SUS_A; - char wk18[220]; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_8_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_8_W; - } N0SA_8; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_8; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_8; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_8_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_8_W; - } N1SA_8; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_8; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_8; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_8; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_8; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_8; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_8; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_8; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_8; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_8; - char wk19[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_8; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_8; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_9_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_9_W; - } N0SA_9; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_9; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_9; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_9_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_9_W; - } N1SA_9; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_9; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_9; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_9; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_9; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_9; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_9; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_9; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_9; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_9; - char wk20[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_9; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_9; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_10_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_10_W; - } N0SA_10; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_10; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_10; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_10_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_10_W; - } N1SA_10; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_10; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_10; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_10; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_10; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_10; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_10; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_10; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_10; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_10; - char wk21[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_10; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_10; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_11_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_11_W; - } N0SA_11; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_11; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_11; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_11_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_11_W; - } N1SA_11; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_11; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_11; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_11; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_11; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_11; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_11; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_11; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_11; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_11; - char wk22[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_11; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_11; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_12_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_12_W; - } N0SA_12; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_12; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_12; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_12_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_12_W; - } N1SA_12; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_12; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_12; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_12; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_12; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_12; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_12; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_12; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_12; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_12; - char wk23[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_12; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_12; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_13_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_13_W; - } N0SA_13; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_13; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_13; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_13_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_13_W; - } N1SA_13; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_13; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_13; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_13; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_13; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_13; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_13; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_13; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_13; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_13; - char wk24[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_13; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_13; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_14_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_14_W; - } N0SA_14; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_14; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_14; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_14_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_14_W; - } N1SA_14; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_14; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_14; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_14; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_14; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_14; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_14; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_14; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_14; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_14; - char wk25[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_14; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_14; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N0SA_15_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N0SA_15_W; - } N0SA_15; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N0DA_15; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N0TB_15; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC0_N1SA_15_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC0_N1SA_15_W; - } N1SA_15; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC0_N1DA_15; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC0_N1TB_15; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC0_CRSA_15; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC0_CRDA_15; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC0_CRTB_15; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC0_CHSTAT_15; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC0_CHCTRL_15; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC0_CHCFG_15; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC0_CHITVL_15; - char wk26[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC0_NXLA_15; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC0_CRLA_15; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_8; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_8; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_8; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_8; - char wk27[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_9; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_9; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_9; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_9; - char wk28[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_10; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_10; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_10; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_10; - char wk29[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_11; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_11; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_11; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_11; - char wk30[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_12; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_12; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_12; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_12; - char wk31[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_13; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_13; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_13; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_13; - char wk32[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_14; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_14; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_14; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_14; - char wk33[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC0_SCNT_15; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC0_SSKP_15; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC0_DCNT_15; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC0_DSKP_15; - char wk34[16]; - union - { - unsigned long LONG; - struct - { - unsigned long PR:1; - unsigned long :31; - } BIT; - } DMAC0_DCTRL_B; - union - { - unsigned long LONG; - struct - { - unsigned long :8; - unsigned long DITVL:8; - unsigned long :16; - } BIT; - } DMAC0_DSCITVL_B; - char wk35[8]; - union - { - unsigned long LONG; - struct - { - unsigned long EN08:1; - unsigned long EN19:1; - unsigned long EN210:1; - unsigned long EN311:1; - unsigned long EN412:1; - unsigned long EN513:1; - unsigned long EN614:1; - unsigned long EN715:1; - unsigned long :24; - } BIT; - } DMAC0_DST_EN_B; - union - { - unsigned long LONG; - struct - { - unsigned long ER08:1; - unsigned long ER19:1; - unsigned long ER210:1; - unsigned long ER311:1; - unsigned long ER412:1; - unsigned long ER513:1; - unsigned long ER614:1; - unsigned long ER715:1; - unsigned long :24; - } BIT; - } DMAC0_DST_ER_B; - union - { - unsigned long LONG; - struct - { - unsigned long END08:1; - unsigned long END19:1; - unsigned long END210:1; - unsigned long END311:1; - unsigned long END412:1; - unsigned long END513:1; - unsigned long END614:1; - unsigned long END715:1; - unsigned long :24; - } BIT; - } DMAC0_DST_END_B; - char wk36[4]; - union - { - unsigned long LONG; - struct - { - unsigned long SUS08:1; - unsigned long SUS19:1; - unsigned long SUS210:1; - unsigned long SUS311:1; - unsigned long SUS412:1; - unsigned long SUS513:1; - unsigned long SUS614:1; - unsigned long SUS715:1; - unsigned long :24; - } BIT; - } DMAC0_DST_SUS_B; - char wk37[202972]; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL0; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL1; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL2; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL3; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL4; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL5; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL6; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL7; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL8; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL9; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL10; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL11; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL12; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL13; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL14; - union - { - unsigned long LONG; - struct - { - unsigned long IFC0:8; - unsigned long :24; - } BIT; - } DMA0SEL15; -}; - -struct st_dma1 -{ - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_0_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_0_W; - } N0SA_0; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_0; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_0; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_0_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_0_W; - } N1SA_0; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_0; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_0; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_0; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_0; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_0; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_0; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_0; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_0; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_0; - char wk0[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_0; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_0; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_1_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_1_W; - } N0SA_1; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_1; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_1; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_1_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_1_W; - } N1SA_1; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_1; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_1; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_1; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_1; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_1; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_1; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_1; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_1; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_1; - char wk1[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_1; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_1; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_2_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_2_W; - } N0SA_2; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_2; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_2; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_2_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_2_W; - } N1SA_2; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_2; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_2; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_2; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_2; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_2; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_2; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_2; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_2; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_2; - char wk2[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_2; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_2; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_3_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_3_W; - } N0SA_3; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_3; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_3; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_3_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_3_W; - } N1SA_3; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_3; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_3; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_3; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_3; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_3; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_3; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_3; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_3; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_3; - char wk3[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_3; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_3; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_4_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_4_W; - } N0SA_4; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_4; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_4; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_4_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_4_W; - } N1SA_4; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_4; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_4; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_4; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_4; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_4; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_4; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_4; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_4; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_4; - char wk4[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_4; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_4; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_5_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_5_W; - } N0SA_5; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_5; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_5; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_5_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_5_W; - } N1SA_5; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_5; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_5; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_5; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_5; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_5; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_5; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_5; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_5; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_5; - char wk5[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_5; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_5; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_6_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_6_W; - } N0SA_6; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_6; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_6; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_6_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_6_W; - } N1SA_6; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_6; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_6; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_6; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_6; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_6; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_6; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_6; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_6; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_6; - char wk6[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_6; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_6; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_7_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_7_W; - } N0SA_7; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_7; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_7; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_7_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_7_W; - } N1SA_7; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_7; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_7; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_7; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_7; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_7; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_7; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_7; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_7; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_7; - char wk7[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_7; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_7; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_0; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_0; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_0; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_0; - char wk8[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_1; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_1; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_1; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_1; - char wk9[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_2; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_2; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_2; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_2; - char wk10[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_3; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_3; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_3; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_3; - char wk11[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_4; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_4; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_4; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_4; - char wk12[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_5; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_5; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_5; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_5; - char wk13[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_6; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_6; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_6; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_6; - char wk14[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_7; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_7; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_7; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_7; - char wk15[16]; - union - { - unsigned long LONG; - struct - { - unsigned long PR:1; - unsigned long :31; - } BIT; - } DMAC1_DCTRL_A; - union - { - unsigned long LONG; - struct - { - unsigned long :8; - unsigned long DITVL:8; - unsigned long :16; - } BIT; - } DMAC1_DSCITVL_A; - char wk16[8]; - union - { - unsigned long LONG; - struct - { - unsigned long EN08:1; - unsigned long EN19:1; - unsigned long EN210:1; - unsigned long EN311:1; - unsigned long EN412:1; - unsigned long EN513:1; - unsigned long EN614:1; - unsigned long EN715:1; - unsigned long :24; - } BIT; - } DMAC1_DST_EN_A; - union - { - unsigned long LONG; - struct - { - unsigned long ER08:1; - unsigned long ER19:1; - unsigned long ER210:1; - unsigned long ER311:1; - unsigned long ER412:1; - unsigned long ER513:1; - unsigned long ER614:1; - unsigned long ER715:1; - unsigned long :24; - } BIT; - } DMAC1_DST_ER_A; - union - { - unsigned long LONG; - struct - { - unsigned long END08:1; - unsigned long END19:1; - unsigned long END210:1; - unsigned long END311:1; - unsigned long END412:1; - unsigned long END513:1; - unsigned long END614:1; - unsigned long END715:1; - unsigned long :24; - } BIT; - } DMAC1_DST_END_A; - char wk17[4]; - union - { - unsigned long LONG; - struct - { - unsigned long SUS08:1; - unsigned long SUS19:1; - unsigned long SUS210:1; - unsigned long SUS311:1; - unsigned long SUS412:1; - unsigned long SUS513:1; - unsigned long SUS614:1; - unsigned long SUS715:1; - unsigned long :24; - } BIT; - } DMAC1_DST_SUS_A; - char wk18[220]; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_8_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_8_W; - } N0SA_8; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_8; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_8; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_8_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_8_W; - } N1SA_8; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_8; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_8; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_8; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_8; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_8; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_8; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_8; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_8; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_8; - char wk19[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_8; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_8; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_9_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_9_W; - } N0SA_9; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_9; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_9; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_9_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_9_W; - } N1SA_9; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_9; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_9; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_9; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_9; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_9; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_9; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_9; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_9; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_9; - char wk20[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_9; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_9; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_10_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_10_W; - } N0SA_10; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_10; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_10; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_10_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_10_W; - } N1SA_10; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_10; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_10; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_10; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_10; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_10; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_10; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_10; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_10; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_10; - char wk21[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_10; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_10; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_11_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_11_W; - } N0SA_11; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_11; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_11; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_11_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_11_W; - } N1SA_11; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_11; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_11; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_11; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_11; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_11; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_11; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_11; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_11; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_11; - char wk22[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_11; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_11; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_12_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_12_W; - } N0SA_12; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_12; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_12; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_12_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_12_W; - } N1SA_12; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_12; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_12; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_12; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_12; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_12; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_12; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_12; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_12; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_12; - char wk23[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_12; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_12; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_13_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_13_W; - } N0SA_13; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_13; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_13; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_13_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_13_W; - } N1SA_13; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_13; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_13; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_13; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_13; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_13; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_13; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_13; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_13; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_13; - char wk24[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_13; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_13; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_14_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_14_W; - } N0SA_14; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_14; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_14; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_14_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_14_W; - } N1SA_14; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_14; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_14; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_14; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_14; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_14; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_14; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_14; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_14; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_14; - char wk25[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_14; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_14; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N0SA_15_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N0SA_15_W; - } N0SA_15; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N0DA_15; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N0TB_15; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SA:32; - } BIT; - } DMAC1_N1SA_15_N; - union - { - unsigned long LONG; - struct - { - unsigned long WD:32; - } BIT; - } DMAC1_N1SA_15_W; - } N1SA_15; - union - { - unsigned long LONG; - struct - { - unsigned long DA:32; - } BIT; - } DMAC1_N1DA_15; - union - { - unsigned long LONG; - struct - { - unsigned long TB:32; - } BIT; - } DMAC1_N1TB_15; - union - { - unsigned long LONG; - struct - { - unsigned long CRSA:32; - } BIT; - } DMAC1_CRSA_15; - union - { - unsigned long LONG; - struct - { - unsigned long CRDA:32; - } BIT; - } DMAC1_CRDA_15; - union - { - unsigned long LONG; - struct - { - unsigned long CRTB:32; - } BIT; - } DMAC1_CRTB_15; - union - { - unsigned long LONG; - struct - { - unsigned long EN:1; - unsigned long RQST:1; - unsigned long TACT:1; - unsigned long SUS:1; - unsigned long ER:1; - unsigned long END:1; - unsigned long :1; - unsigned long SR:1; - unsigned long DL:1; - unsigned long DW:1; - unsigned long DER:1; - unsigned long MODE:1; - unsigned long :4; - unsigned long INTM:1; - unsigned long DMARQM:1; - unsigned long SWPRQ:1; - unsigned long :5; - unsigned long DNUM:8; - } BIT; - } DMAC1_CHSTAT_15; - union - { - unsigned long LONG; - struct - { - unsigned long SETEN:1; - unsigned long CLREN:1; - unsigned long :1; - unsigned long SWRST:1; - unsigned long CLRRQ:1; - unsigned long CLREND:1; - unsigned long :1; - unsigned long CLRDE:1; - unsigned long SETSUS:1; - unsigned long CLRSUS:1; - unsigned long :2; - unsigned long SETREN:1; - unsigned long :1; - unsigned long SETSSWPRQ:1; - unsigned long :1; - unsigned long SETINTM:1; - unsigned long CLRINTM:1; - unsigned long SETDMARQM:1; - unsigned long CLRDMARQM:1; - unsigned long :12; - } BIT; - } DMAC1_CHCTRL_15; - union - { - unsigned long LONG; - struct - { - unsigned long SEL:3; - unsigned long REQD:1; - unsigned long LOEN:1; - unsigned long HIEN:1; - unsigned long LVL:1; - unsigned long :1; - unsigned long AM:3; - unsigned long DRRP:1; - unsigned long SDS:4; - unsigned long DDS:4; - unsigned long SAD:1; - unsigned long DAD:1; - unsigned long TM:1; - unsigned long WONLY:1; - unsigned long DEM:1; - unsigned long :1; - unsigned long DIM:1; - unsigned long SBE:1; - unsigned long RSEL:1; - unsigned long RSW:1; - unsigned long REN:1; - unsigned long DMS:1; - } BIT; - } DMAC1_CHCFG_15; - union - { - unsigned long LONG; - struct - { - unsigned long ITVL:16; - unsigned long :16; - } BIT; - } DMAC1_CHITVL_15; - char wk26[4]; - union - { - unsigned long LONG; - struct - { - unsigned long NXLA:32; - } BIT; - } DMAC1_NXLA_15; - union - { - unsigned long LONG; - struct - { - unsigned long CRLA:32; - } BIT; - } DMAC1_CRLA_15; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_8; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_8; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_8; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_8; - char wk27[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_9; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_9; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_9; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_9; - char wk28[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_10; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_10; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_10; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_10; - char wk29[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_11; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_11; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_11; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_11; - char wk30[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_12; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_12; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_12; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_12; - char wk31[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_13; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_13; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_13; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_13; - char wk32[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_14; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_14; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_14; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_14; - char wk33[16]; - union - { - unsigned long LONG; - struct - { - unsigned long SCNT:32; - } BIT; - } DMAC1_SCNT_15; - union - { - unsigned long LONG; - struct - { - unsigned long SSKP:32; - } BIT; - } DMAC1_SSKP_15; - union - { - unsigned long LONG; - struct - { - unsigned long DCNT:32; - } BIT; - } DMAC1_DCNT_15; - union - { - unsigned long LONG; - struct - { - unsigned long DSKP:32; - } BIT; - } DMAC1_DSKP_15; - char wk34[16]; - union - { - unsigned long LONG; - struct - { - unsigned long PR:1; - unsigned long :31; - } BIT; - } DMAC1_DCTRL_B; - union - { - unsigned long LONG; - struct - { - unsigned long :8; - unsigned long DITVL:8; - unsigned long :16; - } BIT; - } DMAC1_DSCITVL_B; - char wk35[8]; - union - { - unsigned long LONG; - struct - { - unsigned long EN08:1; - unsigned long EN19:1; - unsigned long EN210:1; - unsigned long EN311:1; - unsigned long EN412:1; - unsigned long EN513:1; - unsigned long EN614:1; - unsigned long EN715:1; - unsigned long :24; - } BIT; - } DMAC1_DST_EN_B; - union - { - unsigned long LONG; - struct - { - unsigned long ER08:1; - unsigned long ER19:1; - unsigned long ER210:1; - unsigned long ER311:1; - unsigned long ER412:1; - unsigned long ER513:1; - unsigned long ER614:1; - unsigned long ER715:1; - unsigned long :24; - } BIT; - } DMAC1_DST_ER_B; - union - { - unsigned long LONG; - struct - { - unsigned long END08:1; - unsigned long END19:1; - unsigned long END210:1; - unsigned long END311:1; - unsigned long END412:1; - unsigned long END513:1; - unsigned long END614:1; - unsigned long END715:1; - unsigned long :24; - } BIT; - } DMAC1_DST_END_B; - char wk36[4]; - union - { - unsigned long LONG; - struct - { - unsigned long SUS08:1; - unsigned long SUS19:1; - unsigned long SUS210:1; - unsigned long SUS311:1; - unsigned long SUS412:1; - unsigned long SUS513:1; - unsigned long SUS614:1; - unsigned long SUS715:1; - unsigned long :24; - } BIT; - } DMAC1_DST_SUS_B; - char wk37[198940]; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL0; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL1; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL2; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL3; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL4; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL5; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL6; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL7; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL8; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL9; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL10; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL11; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL12; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL13; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL14; - union - { - unsigned long LONG; - struct - { - unsigned long IFC1:8; - unsigned long :24; - } BIT; - } DMA1SEL15; -}; - -struct st_dmac -{ - union - { - unsigned long LONG; - struct - { - unsigned long :9; - unsigned long DPRTY:2; - unsigned long :13; - unsigned long AL0:1; - unsigned long AL1:1; - unsigned long AL2:1; - unsigned long :1; - unsigned long TL0:1; - unsigned long TL1:1; - unsigned long TL2:1; - unsigned long :1; - } BIT; - } CMNCR; - char wk0[598140]; - union - { - unsigned long LONG; - struct - { - unsigned long DMREQ0:1; - unsigned long DMREQ1:1; - unsigned long :30; - } BIT; - } DMASTG; -}; - -struct st_doc -{ - union - { - unsigned char BYTE; - struct - { - unsigned char OMS:2; - unsigned char DCSEL:1; - unsigned char :1; - unsigned char DOPCIE:1; - unsigned char DOPCF:1; - unsigned char DOPCFCL:1; - unsigned char :1; - } BIT; - } DOCR; - char wk0[1]; - unsigned short DODIR; - unsigned short DODSR; -}; - -struct st_dsmif -{ - union - { - unsigned long LONG; - struct - { - unsigned long ENABLE:1; - unsigned long :7; - unsigned long SINC1SEL:2; - unsigned long :2; - unsigned long WORD1GEN:3; - unsigned long :1; - unsigned long BITSHIFT1:4; - unsigned long SINC2SEL:2; - unsigned long :2; - unsigned long WORD2GEN:3; - unsigned long :1; - unsigned long BITSHIFT2:4; - } BIT; - } UVWCTL; - union - { - unsigned long LONG; - struct - { - unsigned long ERUI:1; - unsigned long ERVI:1; - unsigned long ERWI:1; - unsigned long :1; - unsigned long ERUSC:1; - unsigned long ERVSC:1; - unsigned long ERWSC:1; - unsigned long :1; - unsigned long ERUVWIGND:1; - unsigned long :23; - } BIT; - } UVWSTA; - union - { - unsigned long LONG; - struct - { - unsigned long CMPUVWIUNDER:16; - unsigned long :16; - } BIT; - } UVWIUNCMP; - union - { - unsigned long LONG; - struct - { - unsigned long CMPUVWIOVER:16; - unsigned long :16; - } BIT; - } UVWIOVCMP; - union - { - unsigned long LONG; - struct - { - unsigned long CMPUVWSCUNDER:13; - unsigned long :19; - } BIT; - } UVWSCUNCMP; - union - { - unsigned long LONG; - struct - { - unsigned long CMPUVWSCOVER:13; - unsigned long :19; - } BIT; - } UVWSCOVCMP; - union - { - unsigned long LONG; - struct - { - unsigned long CMPUVWIGNDUNDER:18; - unsigned long :14; - } BIT; - } UVWIGUNCMP; - union - { - unsigned long LONG; - struct - { - unsigned long CMPUVWIGNDOVER:18; - unsigned long :14; - } BIT; - } UVWIGOVCMP; - union - { - unsigned long LONG; - struct - { - unsigned long U1DATA:16; - unsigned long :16; - } BIT; - } U1DATA; - union - { - unsigned long LONG; - struct - { - unsigned long U1CDATA:16; - unsigned long :16; - } BIT; - } U1CDATA; - union - { - unsigned long LONG; - struct - { - unsigned long U1VDATA:16; - unsigned long :16; - } BIT; - } U1VDATA; - union - { - unsigned long LONG; - struct - { - unsigned long U2DATA:16; - unsigned long :16; - } BIT; - } U2DATA; - union - { - unsigned long LONG; - struct - { - unsigned long V1DATA:16; - unsigned long :16; - } BIT; - } V1DATA; - union - { - unsigned long LONG; - struct - { - unsigned long V1CDATA:16; - unsigned long :16; - } BIT; - } V1CDATA; - union - { - unsigned long LONG; - struct - { - unsigned long V1VDATA:16; - unsigned long :16; - } BIT; - } V1VDATA; - union - { - unsigned long LONG; - struct - { - unsigned long V2DATA:16; - unsigned long :16; - } BIT; - } V2DATA; - union - { - unsigned long LONG; - struct - { - unsigned long W1DATA:16; - unsigned long :16; - } BIT; - } W1DATA; - union - { - unsigned long LONG; - struct - { - unsigned long W1CDATA:16; - unsigned long :16; - } BIT; - } W1CDATA; - union - { - unsigned long LONG; - struct - { - unsigned long W1VDATA:16; - unsigned long :16; - } BIT; - } W1VDATA; - union - { - unsigned long LONG; - struct - { - unsigned long W2DATA:16; - unsigned long :16; - } BIT; - } W2DATA; - char wk0[48]; - union - { - unsigned long LONG; - struct - { - unsigned long ENABLE:1; - unsigned long :7; - unsigned long SINC1SEL:2; - unsigned long :2; - unsigned long WORD1GEN:3; - unsigned long :1; - unsigned long BITSHIFT1:4; - unsigned long SINC2SEL:2; - unsigned long :2; - unsigned long WORD2GEN:3; - unsigned long :1; - unsigned long BITSHIFT2:4; - } BIT; - } XYZCTL; - union - { - unsigned long LONG; - struct - { - unsigned long ERXI:1; - unsigned long :3; - unsigned long ERXSC:1; - unsigned long :27; - } BIT; - } XYZSTA; - union - { - unsigned long LONG; - struct - { - unsigned long CMPXIUNDER:16; - unsigned long :16; - } BIT; - } XYZIUNCMP; - union - { - unsigned long LONG; - struct - { - unsigned long CMPXIOVER:16; - unsigned long :16; - } BIT; - } XYZIOVCMP; - union - { - unsigned long LONG; - struct - { - unsigned long CMPXSCUNDER:13; - unsigned long :19; - } BIT; - } XYZSCUNCMP; - union - { - unsigned long LONG; - struct - { - unsigned long CMPXSCOVER:13; - unsigned long :19; - } BIT; - } XYZSCOVCMP; - char wk1[8]; - union - { - unsigned long LONG; - struct - { - unsigned long X1DATA:16; - unsigned long :16; - } BIT; - } X1DATA; - union - { - unsigned long LONG; - struct - { - unsigned long X1CDATA:16; - unsigned long :16; - } BIT; - } X1CDATA; - union - { - unsigned long LONG; - struct - { - unsigned long X1VDATA:16; - unsigned long :16; - } BIT; - } X1VDATA; - char wk2[16]; - union - { - unsigned long LONG; - struct - { - unsigned long X2DATA:16; - unsigned long :16; - } BIT; - } X2DATA; -}; - -struct st_ecatc -{ - union - { - unsigned long LONG; - struct - { - unsigned long OADD0:1; - unsigned long OADD1:1; - unsigned long OADD2:1; - unsigned long OADD3:1; - unsigned long OADD4:1; - unsigned long :27; - } BIT; - } CATOFFADD; - union - { - unsigned long LONG; - struct - { - unsigned long I2CSIZE:1; - unsigned long :31; - } BIT; - } CATEMMD; - char wk0[4]; - union - { - unsigned long LONG; - struct - { - unsigned long TXSFT00:1; - unsigned long TXSFT01:1; - unsigned long TXSFT10:1; - unsigned long TXSFT11:1; - unsigned long :28; - } BIT; - } CATTXCSFT; - char wk1[69360]; - union - { - unsigned char BYTE; - struct - { - unsigned char TYPE:8; - } BIT; - } TYPE; - union - { - unsigned char BYTE; - struct - { - unsigned char REV:8; - } BIT; - } REVISION; - union - { - unsigned short WORD; - struct - { - unsigned short BUILD:16; - } BIT; - } BUILD; - union - { - unsigned char BYTE; - struct - { - unsigned char NUMFMMU:8; - } BIT; - } FMMU_NUM; - union - { - unsigned char BYTE; - struct - { - unsigned char NUMSYNC:8; - } BIT; - } SYNC_MANAGER; - union - { - unsigned char BYTE; - struct - { - unsigned char RAMSIZE:8; - } BIT; - } RAM_SIZE; - union - { - unsigned char BYTE; - struct - { - unsigned char P0:2; - unsigned char P1:2; - unsigned char P2:2; - unsigned char P3:2; - } BIT; - } PORT_DESC; - union - { - unsigned short WORD; - struct - { - unsigned short FMMU:1; - unsigned short :1; - unsigned short DC:1; - unsigned short DCWID:1; - unsigned short :2; - unsigned short LINKDECMII:1; - unsigned short FCS:1; - unsigned short DCSYNC:1; - unsigned short LRW:1; - unsigned short RWSUPP:1; - unsigned short FSCONFIG:1; - unsigned short :4; - } BIT; - } FEATURE; - char wk2[6]; - union - { - unsigned short WORD; - struct - { - unsigned short NODADDR:16; - } BIT; - } STATION_ADR; - union - { - unsigned short WORD; - struct - { - unsigned short NODALIADDR:16; - } BIT; - } STATION_ALIAS; - char wk3[12]; - union - { - unsigned char BYTE; - struct - { - unsigned char ENABLE:1; - unsigned char :7; - } BIT; - } WR_REG_ENABLE; - union - { - unsigned char BYTE; - struct - { - unsigned char PROTECT:1; - unsigned char :7; - } BIT; - } WR_REG_PROTECT; - char wk4[14]; - union - { - unsigned char BYTE; - struct - { - unsigned char ENABLE:1; - unsigned char :7; - } BIT; - } ESC_WR_ENABLE; - union - { - unsigned char BYTE; - struct - { - unsigned char PROTECT:1; - unsigned char :7; - } BIT; - } ESC_WR_PROTECT; - char wk5[14]; - union - { - union - { - unsigned char BYTE; - } ESC_RESET_ECAT_W; - union - { - unsigned char BYTE; - } ESC_RESET_ECAT_R; - } RESET_ECAT; - union - { - union - { - unsigned char BYTE; - } ESC_RESET_PDI_W; - union - { - unsigned char BYTE; - } ESC_RESET_PDI_R; - } RESET_PDI; - char wk6[190]; - union - { - unsigned long LONG; - struct - { - unsigned long FWDRULE:1; - unsigned long TEMPUSE:1; - unsigned long :6; - unsigned long LP0:2; - unsigned long LP1:2; - unsigned long LP2:2; - unsigned long LP3:2; - unsigned long RXFIFO:3; - unsigned long :5; - unsigned long STAALIAS:1; - unsigned long :7; - } BIT; - } ESC_DL_CONTROL; - char wk7[4]; - union - { - unsigned short WORD; - struct - { - unsigned short RWOFFSET:16; - } BIT; - } PHYSICAL_RW_OFFSET; - char wk8[6]; - union - { - unsigned short WORD; - struct - { - unsigned short PDIOPE:1; - unsigned short PDIWDST:1; - unsigned short ENHLINKD:1; - unsigned short :1; - unsigned short PHYP0:1; - unsigned short PHYP1:1; - unsigned short PHYP2:1; - unsigned short PHYP3:1; - unsigned short LP0:1; - unsigned short COMP0:1; - unsigned short LP1:1; - unsigned short COMP1:1; - unsigned short LP2:1; - unsigned short COMP2:1; - unsigned short LP3:1; - unsigned short COMP3:1; - } BIT; - } ESC_DL_STATUS; - char wk9[14]; - union - { - unsigned short WORD; - struct - { - unsigned short INISTATE:4; - unsigned short ERRINDACK:1; - unsigned short :11; - } BIT; - } AL_CONTROL; - char wk10[14]; - union - { - unsigned short WORD; - struct - { - unsigned short ACTSTATE:4; - unsigned short ERR:1; - unsigned short :11; - } BIT; - } AL_STATUS; - char wk11[2]; - union - { - unsigned short WORD; - struct - { - unsigned short STATUSCODE:16; - } BIT; - } AL_STATUS_CODE; - char wk12[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char LEDCODE:4; - unsigned char OVERRIDEEN:1; - unsigned char :3; - } BIT; - } RUN_LED_OVERRIDE; - union - { - unsigned char BYTE; - struct - { - unsigned char LEDCODE:4; - unsigned char OVERRIDEEN:1; - unsigned char :3; - } BIT; - } ERR_LED_OVERRIDE; - char wk13[6]; - union - { - unsigned char BYTE; - struct - { - unsigned char PDI:8; - } BIT; - } PDI_CONTROL; - union - { - unsigned char BYTE; - struct - { - unsigned char DEVEMU:1; - unsigned char ENLALLP:1; - unsigned char DCSYNC:1; - unsigned char DCLATCH:1; - unsigned char ENLP0:1; - unsigned char ENLP1:1; - unsigned char ENLP2:1; - unsigned char ENLP3:1; - } BIT; - } ESC_CONFIG; - char wk14[14]; - union - { - unsigned char BYTE; - struct - { - unsigned char ONCHIPBUSCLK:5; - unsigned char ONCHIPBUS:3; - } BIT; - } PDI_CONFIG; - union - { - unsigned char BYTE; - struct - { - unsigned char SYNC0OUT:2; - unsigned char SYNCLAT0:1; - unsigned char SYNC0MAP:1; - unsigned char :1; - unsigned char SYNC1OUT:1; - unsigned char SYNCLAT1:1; - unsigned char SYNC1MAP:1; - } BIT; - } SYNC_LATCH_CONFIG; - union - { - unsigned short WORD; - struct - { - unsigned short DATABUSWID:1; - unsigned short :15; - } BIT; - } EXT_PDI_CONFIG; - char wk15[172]; - union - { - unsigned short WORD; - struct - { - unsigned short ECATEVMASK:16; - } BIT; - } ECAT_EVENT_MASK; - char wk16[2]; - union - { - unsigned long LONG; - struct - { - unsigned long ALEVMASK:32; - } BIT; - } AL_EVENT_MASK; - char wk17[8]; - union - { - unsigned short WORD; - struct - { - unsigned short DCLATCH:1; - unsigned short :1; - unsigned short DLSTA:1; - unsigned short ALSTA:1; - unsigned short SMSTA0:1; - unsigned short SMSTA1:1; - unsigned short SMSTA2:1; - unsigned short SMSTA3:1; - unsigned short SMSTA4:1; - unsigned short SMSTA5:1; - unsigned short SMSTA6:1; - unsigned short SMSTA7:1; - unsigned short :4; - } BIT; - } ECAT_EVENT_REQ; - char wk18[14]; - union - { - unsigned long LONG; - struct - { - unsigned long ALCTRL:1; - unsigned long DCLATCH:1; - unsigned long DCSYNC0STA:1; - unsigned long DCSYNC1STA:1; - unsigned long SYNCACT:1; - unsigned long :1; - unsigned long WDPD:1; - unsigned long :1; - unsigned long SMINT0:1; - unsigned long SMINT1:1; - unsigned long SMINT2:1; - unsigned long SMINT3:1; - unsigned long SMINT4:1; - unsigned long SMINT5:1; - unsigned long SMINT6:1; - unsigned long SMINT7:1; - unsigned long :16; - } BIT; - } AL_EVENT_REQ; - char wk19[220]; - union - { - unsigned short WORD; - struct - { - unsigned short RXERRCNT:16; - } BIT; - } RX_ERR_COUNT0; - union - { - unsigned short WORD; - struct - { - unsigned short RXERRCNT:16; - } BIT; - } RX_ERR_COUNT1; - char wk20[4]; - union - { - unsigned char BYTE; - struct - { - unsigned char FWDERRCNT:8; - } BIT; - } FWD_RX_ERR_COUNT0; - union - { - unsigned char BYTE; - struct - { - unsigned char FWDERRCNT:8; - } BIT; - } FWD_RX_ERR_COUNT1; - char wk21[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char EPUERRCNT:8; - } BIT; - } ECAT_PROC_ERR_COUNT; - union - { - unsigned char BYTE; - struct - { - unsigned char PDIERRCNT:8; - } BIT; - } PDI_ERR_COUNT; - char wk22[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char LOSTLINKCNT:8; - } BIT; - } LOST_LINK_COUNT0; - union - { - unsigned char BYTE; - struct - { - unsigned char LOSTLINKCNT:8; - } BIT; - } LOST_LINK_COUNT1; - char wk23[238]; - union - { - unsigned short WORD; - struct - { - unsigned short WDDIV:16; - } BIT; - } WD_DIVIDE; - char wk24[14]; - union - { - unsigned short WORD; - struct - { - unsigned short WDTIMPDI:16; - } BIT; - } WDT_PDI; - char wk25[14]; - union - { - unsigned short WORD; - struct - { - unsigned short WDTIMPD:16; - } BIT; - } WDT_DATA; - char wk26[30]; - union - { - unsigned short WORD; - struct - { - unsigned short WDSTAPD:1; - unsigned short :15; - } BIT; - } WDS_DATA; - union - { - unsigned char BYTE; - struct - { - unsigned char WDCNTPD:8; - } BIT; - } WDC_DATA; - union - { - unsigned char BYTE; - struct - { - unsigned char WDCNTPDI:8; - } BIT; - } WDC_PDI; - char wk27[188]; - union - { - unsigned char BYTE; - struct - { - unsigned char CTRLPDI:1; - unsigned char FORCEECAT:1; - unsigned char :6; - } BIT; - } EEP_CONF; - union - { - unsigned char BYTE; - struct - { - unsigned char PDIACCESS:1; - unsigned char :7; - } BIT; - } EEP_STATE; - union - { - unsigned short WORD; - struct - { - unsigned short ECATWREN:1; - unsigned short :5; - unsigned short READBYTE:1; - unsigned short PROMSIZE:1; - unsigned short COMMAND:3; - unsigned short CKSUMERR:1; - unsigned short LOADSTA:1; - unsigned short ACKCMDERR:1; - unsigned short WRENERR:1; - unsigned short BUSY:1; - } BIT; - } EEP_CONT_STAT; - union - { - unsigned long LONG; - struct - { - unsigned long ADDRESS:32; - } BIT; - } EEP_ADR; - union - { - unsigned long LONG; - struct - { - unsigned long LODATA:16; - unsigned long HIDATA:16; - } BIT; - } EEP_DATA; - char wk28[4]; - union - { - unsigned short WORD; - struct - { - unsigned short WREN:1; - unsigned short PDICTRL:1; - unsigned short MILINK:1; - unsigned short PHYOFFSET:5; - unsigned short COMMAND:2; - unsigned short :3; - unsigned short READERR:1; - unsigned short CMDERR:1; - unsigned short BUSY:1; - } BIT; - } MII_CONT_STAT; - union - { - unsigned char BYTE; - struct - { - unsigned char PHYADDR:5; - unsigned char :3; - } BIT; - } PHY_ADR; - union - { - unsigned char BYTE; - struct - { - unsigned char PHYREGADDR:5; - unsigned char :3; - } BIT; - } PHY_REG_ADR; - union - { - unsigned short WORD; - struct - { - unsigned short PHYREGDATA:16; - } BIT; - } PHY_DATA; - union - { - unsigned char BYTE; - struct - { - unsigned char ACSMII:1; - unsigned char :7; - } BIT; - } MII_ECAT_ACS_STAT; - union - { - unsigned char BYTE; - struct - { - unsigned char ACSMII:1; - unsigned char FORPDI:1; - unsigned char :6; - } BIT; - } MII_PDI_ACS_STAT; - union - { - unsigned char BYTE; - struct - { - unsigned char PHYLINKSTA:1; - unsigned char LINKSTA:1; - unsigned char LINKSTAERR:1; - unsigned char READERR:1; - unsigned char LINKPARTERR:1; - unsigned char PHYCONFIG:1; - unsigned char :2; - } BIT; - } PHY_STATUS0; - union - { - unsigned char BYTE; - struct - { - unsigned char PHYLINKSTA:1; - unsigned char LINKSTA:1; - unsigned char LINKSTAERR:1; - unsigned char READERR:1; - unsigned char LINKPARTERR:1; - unsigned char PHYCONFIG:1; - unsigned char :2; - } BIT; - } PHY_STATUS1; - char wk29[230]; - struct - { - union - { - unsigned long LONG; - struct - { - unsigned long LSTAADR:32; - } BIT; - } L_START_ADR; - union - { - unsigned short WORD; - struct - { - unsigned short FMMULEN:16; - } BIT; - } LEN; - union - { - unsigned char BYTE; - struct - { - unsigned char LSTABIT:3; - unsigned char :5; - } BIT; - } L_START_BIT; - union - { - unsigned char BYTE; - struct - { - unsigned char LSTABIT:3; - unsigned char :5; - } BIT; - } L_STOP_BIT; - union - { - unsigned short WORD; - struct - { - unsigned short PHYSTAADR:16; - } BIT; - } P_START_ADR; - union - { - unsigned char BYTE; - struct - { - unsigned char PHYSTABIT:3; - unsigned char :5; - } BIT; - } P_START_BIT; - union - { - unsigned char BYTE; - struct - { - unsigned char READ:1; - unsigned char WRITE:1; - unsigned char :6; - } BIT; - } TYPE; - union - { - unsigned char BYTE; - struct - { - unsigned char ACTIVATE:1; - unsigned char :7; - } BIT; - } ACT; - char fmmu_wk[3]; - } FMMU[8]; - char wk37[0x180]; - struct - { - union - { - unsigned short WORD; - struct - { - unsigned short SMSTAADDR:16; - } BIT; - } P_START_ADR; - union - { - unsigned short WORD; - struct - { - unsigned short SMLEN:16; - } BIT; - } LEN; - union - { - unsigned char BYTE; - struct - { - unsigned char OPEMODE:2; - unsigned char DIR:2; - unsigned char IRQECAT:1; - unsigned char IRQPDI:1; - unsigned char WDTRGEN:1; - unsigned char :1; - } BIT; - } CONTROL; - union - { - unsigned char BYTE; - struct - { - unsigned char INTWR:1; - unsigned char INTRD:1; - unsigned char :1; - unsigned char MAILBOX:1; - unsigned char BUFFERED:2; - unsigned char RDBUF:1; - unsigned char WRBUF:1; - } BIT; - } STATUS; - union - { - unsigned char BYTE; - struct - { - unsigned char SMEN:1; - unsigned char REPEATREQ:1; - unsigned char :4; - unsigned char LATCHECAT:1; - unsigned char LATCHPDI:1; - } BIT; - } ACT; - union - { - unsigned char BYTE; - struct - { - unsigned char DEACTIVE:1; - unsigned char REPEATACK:1; - unsigned char :6; - } BIT; - } PDI_CONT; - } SM[8]; - char wk38[192]; - union - { - unsigned long LONG; - struct - { - unsigned long RCVTIME0:32; - } BIT; - } DC_RCV_TIME_PORT0; - union - { - unsigned long LONG; - struct - { - unsigned long RCVTIME1:32; - } BIT; - } DC_RCV_TIME_PORT1; - char wk39[8]; - union - { - unsigned long long LONGLONG; - } DC_SYS_TIME; - union - { - unsigned long long LONGLONG; - } DC_RCV_TIME_UNIT; - union - { - unsigned long long LONGLONG; - } DC_SYS_TIME_OFFSET; - union - { - unsigned long LONG; - struct - { - unsigned long SYSTIMDLY:32; - } BIT; - } DC_SYS_TIME_DELAY; - union - { - unsigned long LONG; - struct - { - unsigned long LOCALCOPY:1; - unsigned long DIFF:31; - } BIT; - } DC_SYS_TIME_DIFF; - union - { - unsigned short WORD; - struct - { - unsigned short :1; - unsigned short SPDCNTSTRT:15; - } BIT; - } DC_SPEED_COUNT_START; - union - { - unsigned short WORD; - struct - { - unsigned short SPDCNTDIFF:16; - } BIT; - } DC_SPEED_COUNT_DIFF; - union - { - unsigned char BYTE; - struct - { - unsigned char :4; - unsigned char SYSTIMDEP:4; - } BIT; - } DC_SYS_TIME_DIFF_FIL_DEPTH; - union - { - unsigned char BYTE; - struct - { - unsigned char :4; - unsigned char CLKPERDEP:4; - } BIT; - } DC_SPEED_COUNT_FIL_DEPTH; - char wk40[74]; - union - { - unsigned char BYTE; - struct - { - unsigned char :2; - unsigned char LATCH1:1; - unsigned char LATCH0:1; - unsigned char :3; - unsigned char SYNCOUT:1; - } BIT; - } DC_CYC_CONT; - union - { - unsigned char BYTE; - struct - { - unsigned char DBGPULSE:1; - unsigned char NEARFUTURE:1; - unsigned char STARTTIME:1; - unsigned char EXTSTARTTIME:1; - unsigned char AUTOACT:1; - unsigned char SYNC1:1; - unsigned char SYNC0:1; - unsigned char SYNCACT:1; - } BIT; - } DC_ACT; - union - { - unsigned short WORD; - struct - { - unsigned short PULSELEN:16; - } BIT; - } DC_PULSE_LEN; - union - { - unsigned char BYTE; - struct - { - unsigned char :5; - unsigned char STARTTIME:1; - unsigned char SYNC1ACT:1; - unsigned char SYNC0ACT:1; - } BIT; - } DC_ACT_STAT; - char wk41[9]; - union - { - unsigned char BYTE; - struct - { - unsigned char :7; - unsigned char SYNC0STA:1; - } BIT; - } DC_SYNC0_STAT; - union - { - unsigned char BYTE; - struct - { - unsigned char :7; - unsigned char SYNC1STA:1; - } BIT; - } DC_SYNC1_STAT; - union - { - unsigned long long LONGLONG; - } DC_CYC_START_TIME; - union - { - unsigned long long LONGLONG; - } DC_NEXT_SYNC1_PULSE; - union - { - unsigned long LONG; - struct - { - unsigned long SYNC0CYC:32; - } BIT; - } DC_SYNC0_CYC_TIME; - union - { - unsigned long LONG; - struct - { - unsigned long SYNC1CYC:32; - } BIT; - } DC_SYNC1_CYC_TIME; - union - { - unsigned char BYTE; - struct - { - unsigned char :6; - unsigned char NEGEDGE:1; - unsigned char POSEDGE:1; - } BIT; - } DC_LATCH0_CONT; - union - { - unsigned char BYTE; - struct - { - unsigned char :6; - unsigned char NEGEDGE:1; - unsigned char POSEDGE:1; - } BIT; - } DC_LATCH1_CONT; - char wk42[4]; - union - { - unsigned char BYTE; - struct - { - unsigned char :5; - unsigned char PINSTATE:1; - unsigned char EVENTNEG:1; - unsigned char EVENTPOS:1; - } BIT; - } DC_LATCH0_STAT; - union - { - unsigned char BYTE; - struct - { - unsigned char :5; - unsigned char PINSTATE:1; - unsigned char EVENTNEG:1; - unsigned char EVENTPOS:1; - } BIT; - } DC_LATCH1_STAT; - union - { - unsigned long long LONGLONG; - } DC_LATCH0_TIME_POS; - union - { - unsigned long long LONGLONG; - } DC_LATCH0_TIME_NEG; - union - { - unsigned long long LONGLONG; - } DC_LATCH1_TIME_POS; - union - { - unsigned long long LONGLONG; - } DC_LATCH1_TIME_NEG; - char wk43[32]; - union - { - unsigned long LONG; - struct - { - unsigned long ECATCHANGE:32; - } BIT; - } DC_ECAT_CNG_EV_TIME; - char wk44[4]; - union - { - unsigned long LONG; - struct - { - unsigned long PDISTART:32; - } BIT; - } DC_PDI_START_EV_TIME; - union - { - unsigned long LONG; - struct - { - unsigned long PDICHANGE:32; - } BIT; - } DC_PDI_CNG_EV_TIME; - char wk45[1024]; - union - { - unsigned long long LONGLONG; - } PRODUCT_ID; - union - { - unsigned long long LONGLONG; - } VENDOR_ID; -}; - -struct st_eccram -{ - union - { - unsigned long LONG; - } RAMPCMD; - char wk0[252]; - union - { - unsigned long LONG; - struct - { - unsigned long :31; - unsigned long ECC_ENABLE:1; - } BIT; - } RAMEDC; - union - { - unsigned long LONG; - struct - { - unsigned long :16; - unsigned long DBE_DIST15:1; - unsigned long DBE_DIST14:1; - unsigned long DBE_DIST13:1; - unsigned long DBE_DIST12:1; - unsigned long DBE_DIST11:1; - unsigned long DBE_DIST10:1; - unsigned long DBE_DIST9:1; - unsigned long DBE_DIST8:1; - unsigned long DBE_DIST7:1; - unsigned long DBE_DIST6:1; - unsigned long DBE_DIST5:1; - unsigned long DBE_DIST4:1; - unsigned long DBE_DIST3:1; - unsigned long DBE_DIST2:1; - unsigned long DBE_DIST1:1; - unsigned long DBE_DIST0:1; - } BIT; - } RAMEEC; - union - { - unsigned long LONG; - struct - { - unsigned long :16; - unsigned long DBE_RAM15:1; - unsigned long DBE_RAM14:1; - unsigned long DBE_RAM13:1; - unsigned long DBE_RAM12:1; - unsigned long DBE_RAM11:1; - unsigned long DBE_RAM10:1; - unsigned long DBE_RAM9:1; - unsigned long DBE_RAM8:1; - unsigned long DBE_RAM7:1; - unsigned long DBE_RAM6:1; - unsigned long DBE_RAM5:1; - unsigned long DBE_RAM4:1; - unsigned long DBE_RAM3:1; - unsigned long DBE_RAM2:1; - unsigned long DBE_RAM1:1; - unsigned long DBE_RAM0:1; - } BIT; - } RAMDBEST; - union - { - unsigned long LONG; - struct - { - unsigned long :12; - unsigned long BANK:2; - unsigned long ADDRESS:16; - unsigned long :1; - unsigned long LOCK:1; - } BIT; - } RAMDBEAD; - union - { - unsigned long LONG; - struct - { - unsigned long :28; - unsigned long ERRCOUNT:4; - } BIT; - } RAMDBECNT; -}; - -struct st_ecm -{ - union - { - unsigned char BYTE; - } ECMEPCFG; - char wk0[3]; - union - { - unsigned long LONG; - } ECMMICFG0; - union - { - unsigned long LONG; - } ECMMICFG1; - union - { - unsigned long LONG; - } ECMMICFG2; - union - { - unsigned long LONG; - } ECMNMICFG0; - union - { - unsigned long LONG; - } ECMNMICFG1; - union - { - unsigned long LONG; - } ECMNMICFG2; - union - { - unsigned long LONG; - } ECMIRCFG0; - union - { - unsigned long LONG; - } ECMIRCFG1; - union - { - unsigned long LONG; - } ECMIRCFG2; - union - { - unsigned long LONG; - } ECMEMK0; - union - { - unsigned long LONG; - } ECMEMK1; - union - { - unsigned long LONG; - } ECMEMK2; - union - { - unsigned long LONG; - } ECMESSTC0; - union - { - unsigned long LONG; - } ECMESSTC1; - union - { - unsigned long LONG; - } ECMESSTC2; - union - { - unsigned long LONG; - } ECMPCMD1; - union - { - unsigned char BYTE; - struct - { - unsigned char ECMPRERR:1; - unsigned char :7; - } BIT; - } ECMPS; - char wk1[3]; - union - { - unsigned long LONG; - } ECMPE0; - union - { - unsigned long LONG; - } ECMPE1; - union - { - unsigned long LONG; - } ECMPE2; - union - { - unsigned char BYTE; - } ECMDTMCTL; - char wk2[3]; - union - { - unsigned short WORD; - struct - { - unsigned short ECMTDMR:16; - } BIT; - } ECMDTMR; - char wk3[2]; - union - { - unsigned long LONG; - } ECMDTMCMP; - union - { - unsigned long LONG; - } ECMDTMCFG0; - union - { - unsigned long LONG; - } ECMDTMCFG1; - union - { - unsigned long LONG; - } ECMDTMCFG2; - union - { - unsigned long LONG; - } ECMDTMCFG3; - union - { - unsigned long LONG; - } ECMDTMCFG4; - union - { - unsigned long LONG; - } ECMDTMCFG5; - union - { - unsigned long LONG; - } ECMEOCCFG; -}; - -struct st_ecmc -{ - union - { - unsigned char BYTE; - } ECMCESET; - char wk0[3]; - union - { - unsigned char BYTE; - } ECMCECLR; - char wk1[3]; - union - { - unsigned long LONG; - struct - { - unsigned long ECMCSSE000:1; - unsigned long ECMCSSE001:1; - unsigned long ECMCSSE002:1; - unsigned long :1; - unsigned long ECMCSSE004:1; - unsigned long ECMCSSE005:1; - unsigned long ECMCSSE006:1; - unsigned long ECMCSSE007:1; - unsigned long ECMCSSE008:1; - unsigned long ECMCSSE009:1; - unsigned long ECMCSSE010:1; - unsigned long ECMCSSE011:1; - unsigned long ECMCSSE012:1; - unsigned long ECMCSSE013:1; - unsigned long ECMCSSE014:1; - unsigned long ECMCSSE015:1; - unsigned long ECMCSSE016:1; - unsigned long ECMCSSE017:1; - unsigned long ECMCSSE018:1; - unsigned long ECMCSSE019:1; - unsigned long ECMCSSE020:1; - unsigned long ECMCSSE021:1; - unsigned long ECMCSSE022:1; - unsigned long ECMCSSE023:1; - unsigned long ECMCSSE024:1; - unsigned long ECMCSSE025:1; - unsigned long ECMCSSE026:1; - unsigned long ECMCSSE027:1; - unsigned long ECMCSSE028:1; - unsigned long :1; - unsigned long ECMCSSE030:1; - unsigned long ECMCSSE031:1; - } BIT; - } ECMCESSTR0; - union - { - unsigned long LONG; - struct - { - unsigned long ECMCSSE100:1; - unsigned long ECMCSSE101:1; - unsigned long ECMCSSE202:1; - unsigned long :1; - unsigned long ECMCSSE104:1; - unsigned long ECMCSSE105:1; - unsigned long ECMCSSE106:1; - unsigned long ECMCSSE107:1; - unsigned long ECMCSSE108:1; - unsigned long :23; - } BIT; - } ECMCESSTR1; - union - { - unsigned long LONG; - struct - { - unsigned long :28; - unsigned long ECMCSSE228:1; - unsigned long ECMCSSE229:1; - unsigned long ECMCSSE230:1; - unsigned long ECMCSSE231:1; - } BIT; - } ECMCESSTR2; - union - { - unsigned long LONG; - struct - { - unsigned long ECMC0REG:8; - unsigned long :24; - } BIT; - } ECMCPCMD0; -}; - -struct st_ecmm -{ - union - { - unsigned char BYTE; - } ECMMESET; - char wk0[3]; - union - { - unsigned char BYTE; - } ECMMECLR; - char wk1[3]; - union - { - unsigned long LONG; - struct - { - unsigned long ECMMSSE000:1; - unsigned long ECMMSSE001:1; - unsigned long ECMMSSE002:1; - unsigned long :1; - unsigned long ECMMSSE004:1; - unsigned long ECMMSSE005:1; - unsigned long ECMMSSE006:1; - unsigned long ECMMSSE007:1; - unsigned long ECMMSSE008:1; - unsigned long ECMMSSE009:1; - unsigned long ECMMSSE010:1; - unsigned long ECMMSSE011:1; - unsigned long ECMMSSE012:1; - unsigned long ECMMSSE013:1; - unsigned long ECMMSSE014:1; - unsigned long ECMMSSE015:1; - unsigned long ECMMSSE016:1; - unsigned long ECMMSSE017:1; - unsigned long ECMMSSE018:1; - unsigned long ECMMSSE019:1; - unsigned long ECMMSSE020:1; - unsigned long ECMMSSE021:1; - unsigned long ECMMSSE022:1; - unsigned long ECMMSSE023:1; - unsigned long ECMMSSE024:1; - unsigned long ECMMSSE025:1; - unsigned long ECMMSSE026:1; - unsigned long ECMMSSE027:1; - unsigned long ECMMSSE028:1; - unsigned long :1; - unsigned long ECMMSSE030:1; - unsigned long ECMMSSE031:1; - } BIT; - } ECMMESSTR0; - union - { - unsigned long LONG; - struct - { - unsigned long ECMMSSE100:1; - unsigned long ECMMSSE101:1; - unsigned long ECMMSSE102:1; - unsigned long :1; - unsigned long ECMMSSE104:1; - unsigned long ECMMSSE105:1; - unsigned long ECMMSSE106:1; - unsigned long ECMMSSE107:1; - unsigned long ECMMSSE108:1; - unsigned long :23; - } BIT; - } ECMMESSTR1; - union - { - unsigned long LONG; - struct - { - unsigned long :28; - unsigned long ECMMSSE228:1; - unsigned long ECMMSSE229:1; - unsigned long ECMMSSE230:1; - unsigned long ECMMSSE231:1; - } BIT; - } ECMMESSTR2; - union - { - unsigned long LONG; - struct - { - unsigned long ECMM0REG:8; - unsigned long :24; - } BIT; - } ECMMPCMD0; -}; - -struct st_elc -{ - union - { - unsigned char BYTE; - struct - { - unsigned char :7; - unsigned char ELCON:1; - } BIT; - } ELCR; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR0; - char wk0[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR3; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR4; - char wk1[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR7; - char wk2[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR10; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR11; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR12; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR13; - char wk3[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR15; - char wk4[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR18; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR19; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR20; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR21; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR22; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR23; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR24; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR25; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR26; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR27; - char wk5[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char MTU0MD:2; - unsigned char :4; - unsigned char MTU3MD:2; - } BIT; - } ELOPA; - union - { - unsigned char BYTE; - struct - { - unsigned char MTU4MD:2; - unsigned char :6; - } BIT; - } ELOPB; - union - { - unsigned char BYTE; - struct - { - unsigned char :2; - unsigned char CMT1MD:2; - unsigned char :4; - } BIT; - } ELOPC; - union - { - unsigned char BYTE; - struct - { - unsigned char DSU0MD:2; - unsigned char DSU1MD:2; - unsigned char DSX0MD:2; - unsigned char DSX1MD:2; - } BIT; - } ELOPD; - union - { - unsigned char BYTE; - struct - { - unsigned char PGRn0:1; - unsigned char PGRn1:1; - unsigned char PGRn2:1; - unsigned char PGRn3:1; - unsigned char PGRn4:1; - unsigned char PGRn5:1; - unsigned char PGRn6:1; - unsigned char PGRn7:1; - } BIT; - } PGR1; - union - { - unsigned char BYTE; - struct - { - unsigned char PGRn0:1; - unsigned char PGRn1:1; - unsigned char PGRn2:1; - unsigned char PGRn3:1; - unsigned char PGRn4:1; - unsigned char PGRn5:1; - unsigned char PGRn6:1; - unsigned char PGRn7:1; - } BIT; - } PGR2; - union - { - unsigned char BYTE; - struct - { - unsigned char PGCIn:2; - unsigned char PGCOVEn:1; - unsigned char :1; - unsigned char PGCOn:3; - unsigned char :1; - } BIT; - } PGC1; - union - { - unsigned char BYTE; - struct - { - unsigned char PGCIn:2; - unsigned char PGCOVEn:1; - unsigned char :1; - unsigned char PGCOn:3; - unsigned char :1; - } BIT; - } PGC2; - union - { - unsigned char BYTE; - struct - { - unsigned char PDBFn0:1; - unsigned char PDBFn1:1; - unsigned char PDBFn2:1; - unsigned char PDBFn3:1; - unsigned char PDBFn4:1; - unsigned char PDBFn5:1; - unsigned char PDBFn6:1; - unsigned char PDBFn7:1; - } BIT; - } PDBF1; - union - { - unsigned char BYTE; - struct - { - unsigned char PDBFn0:1; - unsigned char PDBFn1:1; - unsigned char PDBFn2:1; - unsigned char PDBFn3:1; - unsigned char PDBFn4:1; - unsigned char PDBFn5:1; - unsigned char PDBFn6:1; - unsigned char PDBFn7:1; - } BIT; - } PDBF2; - union - { - unsigned char BYTE; - struct - { - unsigned char PSBn:3; - unsigned char PSPn:2; - unsigned char PSMn:2; - unsigned char :1; - } BIT; - } PEL0; - union - { - unsigned char BYTE; - struct - { - unsigned char PSBn:3; - unsigned char PSPn:2; - unsigned char PSMn:2; - unsigned char :1; - } BIT; - } PEL1; - union - { - unsigned char BYTE; - struct - { - unsigned char PSBn:3; - unsigned char PSPn:2; - unsigned char PSMn:2; - unsigned char :1; - } BIT; - } PEL2; - union - { - unsigned char BYTE; - struct - { - unsigned char PSBn:3; - unsigned char PSPn:2; - unsigned char PSMn:2; - unsigned char :1; - } BIT; - } PEL3; - union - { - unsigned char BYTE; - struct - { - unsigned char SEG:1; - unsigned char :5; - unsigned char WE:1; - unsigned char WI:1; - } BIT; - } ELSEGR; - char wk6[3]; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR33; - char wk7[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR35; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR36; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR37; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR38; - char wk8[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR41; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR42; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR43; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR44; - union - { - unsigned char BYTE; - struct - { - unsigned char ELS:8; - } BIT; - } ELSR45; - char wk9[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPU0MD:2; - unsigned char TPU1MD:2; - unsigned char TPU2MD:2; - unsigned char TPU3MD:2; - } BIT; - } ELOPF; - char wk10[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char CMTW0MD:2; - unsigned char :6; - } BIT; - } ELOPH; - union - { - unsigned char BYTE; - struct - { - unsigned char GPT0MD:3; - unsigned char :1; - unsigned char GPT1MD:3; - unsigned char :1; - } BIT; - } ELOPI; - union - { - unsigned char BYTE; - struct - { - unsigned char GPT2MD:3; - unsigned char :1; - unsigned char GPT3MD:3; - unsigned char :1; - } BIT; - } ELOPJ; -}; - -struct st_etherc -{ - union - { - unsigned long LONG; - } ETSPCMD; - union - { - unsigned long LONG; - struct - { - unsigned long MAC:3; - unsigned long :29; - } BIT; - } MACSEL; - union - { - unsigned long LONG; - struct - { - unsigned long MODE:5; - unsigned long :3; - unsigned long FULLD:1; - unsigned long :1; - unsigned long RMII_CRS_MODE:1; - unsigned long :21; - } BIT; - } MII_CTRL0; - union - { - unsigned long LONG; - struct - { - unsigned long MODE:5; - unsigned long :3; - unsigned long FULLD:1; - unsigned long :1; - unsigned long RMII_CRS_MODE:1; - unsigned long :21; - } BIT; - } MII_CTRL1; - union - { - unsigned long LONG; - struct - { - unsigned long MODE:5; - unsigned long :3; - unsigned long FULLD:1; - unsigned long :1; - unsigned long RMII_CRS_MODE:1; - unsigned long :21; - } BIT; - } MII_CTRL2; - char wk0[260]; - union - { - unsigned long LONG; - struct - { - unsigned long CATRST:1; - unsigned long SWRST:1; - unsigned long PHYRST:1; - unsigned long PHYRST2:1; - unsigned long MIICRST:1; - unsigned long :27; - } BIT; - } ETHSFTRST; - char wk1[196324]; - union - { - unsigned long LONG; - struct - { - unsigned long SYSC:16; - unsigned long :16; - } BIT; - } SYSC; - union - { - unsigned long LONG; - struct - { - unsigned long R4B:32; - } BIT; - } R4; - union - { - unsigned long LONG; - struct - { - unsigned long R5B:32; - } BIT; - } R5; - union - { - unsigned long LONG; - struct - { - unsigned long R6B:32; - } BIT; - } R6; - union - { - unsigned long LONG; - struct - { - unsigned long R7B:32; - } BIT; - } R7; - char wk2[12]; - union - { - unsigned long LONG; - struct - { - unsigned long R0B:32; - } BIT; - } R0; - union - { - unsigned long LONG; - struct - { - unsigned long R1B:32; - } BIT; - } R1; - char wk3[4068]; - union - { - unsigned long LONG; - struct - { - unsigned long TXID:32; - } BIT; - } GMAC_TXID; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOUFLOW:1; - unsigned long RETRYN:4; - unsigned long LCOLLIS:1; - unsigned long UNDERFW:1; - unsigned long OVERFW:1; - unsigned long CSERR:1; - unsigned long MCOLLIS:1; - unsigned long SCOLLIS:1; - unsigned long TFAIL:1; - unsigned long TABT:1; - unsigned long TCMP:1; - unsigned long :18; - } BIT; - } GMAC_TXRESULT; - char wk4[12]; - union - { - unsigned long LONG; - struct - { - unsigned long :30; - unsigned long DUPMODE:1; - unsigned long ETHMODE:1; - } BIT; - } GMAC_MODE; - union - { - unsigned long LONG; - struct - { - unsigned long :9; - unsigned long RRTTH:3; - unsigned long RFULLTH:2; - unsigned long REMPTH:2; - unsigned long :12; - unsigned long RAMASKEN:1; - unsigned long SFRXFIFO:1; - unsigned long MFILLTEREN:1; - unsigned long AFILLTEREN:1; - } BIT; - } GMAC_RXMODE; - union - { - unsigned long LONG; - struct - { - unsigned long :6; - unsigned long TRBMODE:2; - unsigned long :1; - unsigned long TFULLTH:2; - unsigned long TEMPTH:3; - unsigned long FSTTH:2; - unsigned long :10; - unsigned long SFOP:1; - unsigned long RTRANSLC:1; - unsigned long SPTXEN:1; - unsigned long SF:1; - unsigned long LPTXEN:1; - unsigned long RTRANSDEN:1; - } BIT; - } GMAC_TXMODE; - char wk5[4]; - union - { - unsigned long LONG; - struct - { - unsigned long :13; - unsigned long RXRST:1; - unsigned long :1; - unsigned long TXRST:1; - unsigned long :15; - unsigned long ALLRST:1; - } BIT; - } GMAC_RESET; - char wk6[76]; - union - { - unsigned long LONG; - struct - { - unsigned long PPDATA1:32; - } BIT; - } GMAC_PAUSE1; - union - { - unsigned long LONG; - struct - { - unsigned long PPDATA2:32; - } BIT; - } GMAC_PAUSE2; - union - { - unsigned long LONG; - struct - { - unsigned long PPDATA3:32; - } BIT; - } GMAC_PAUSE3; - union - { - unsigned long LONG; - struct - { - unsigned long PPDATA4:32; - } BIT; - } GMAC_PAUSE4; - union - { - unsigned long LONG; - struct - { - unsigned long PPDATA5:32; - } BIT; - } GMAC_PAUSE5; - char wk7[4]; - union - { - unsigned long LONG; - struct - { - unsigned long :31; - unsigned long PPRXEN:1; - } BIT; - } GMAC_FLWCTL; - union - { - unsigned long LONG; - struct - { - unsigned long :31; - unsigned long PPR:1; - } BIT; - } GMAC_PAUSPKT; - union - { - unsigned long LONG; - struct - { - unsigned long DATA:16; - unsigned long REGADDR:5; - unsigned long PHYADDR:5; - unsigned long RWDV:1; - unsigned long :5; - } BIT; - } GMAC_MIIM; - char wk8[92]; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR0A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR0B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR1A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR1B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR2A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR2B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR3A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR3B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR4A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR4B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR5A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR5B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR6A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR6B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR7A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR7B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR8A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR8B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR9A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR9B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR10A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR10B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR11A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR11B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR12A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR12B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR13A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR13B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR14A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR14B; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR1B:8; - unsigned long MADDR2B:8; - unsigned long MADDR3B:8; - unsigned long MADDR4B:8; - } BIT; - } GMAC_ADR15A; - union - { - unsigned long LONG; - struct - { - unsigned long MADDR5B:8; - unsigned long MADDR6B:8; - unsigned long BITMSK:8; - unsigned long :8; - } BIT; - } GMAC_ADR15B; - char wk9[128]; - union - { - unsigned long LONG; - struct - { - unsigned long :17; - unsigned long RSW:12; - unsigned long RRT:1; - unsigned long REMP:1; - unsigned long RFULL:1; - } BIT; - } GMAC_RXFIFO; - union - { - unsigned long LONG; - struct - { - unsigned long :24; - unsigned long TRBFR:3; - unsigned long TSTATUS:3; - unsigned long TEMP:1; - unsigned long TFULL:1; - } BIT; - } GMAC_TXFIFO; - union - { - unsigned long LONG; - struct - { - unsigned long RTCPIPEN:1; - unsigned long TTCPIPEN:1; - unsigned long RTCPIPACC:1; - unsigned long :29; - } BIT; - } GMAC_ACC; - char wk10[20]; - union - { - unsigned long LONG; - struct - { - unsigned long RMACEN:1; - unsigned long :31; - } BIT; - } GMAC_RXMAC_ENA; - union - { - unsigned long LONG; - struct - { - unsigned long :31; - unsigned long LPMEN:1; - } BIT; - } GMAC_LPI_MODE; - union - { - unsigned long LONG; - struct - { - unsigned long LPWTIME:16; - unsigned long LPRDEF:16; - } BIT; - } GMAC_LPI_TIMING; - char wk11[3796]; - union - { - unsigned long LONG; - struct - { - unsigned long ADDR:16; - unsigned long WORD:12; - unsigned long VALID:1; - unsigned long :2; - unsigned long NOEMP:1; - } BIT; - } BUFID; - char wk12[4092]; - union - { - unsigned long LONG; - } SPCMD; - char wk13[12]; - union - { - unsigned long LONG; - struct - { - unsigned long EMACRST:1; - unsigned long :31; - } BIT; - } EMACRST; -}; - -struct st_ethersw -{ - union - { - unsigned long LONG; - struct - { - unsigned long SWLINK0:1; - unsigned long SWLINK1:1; - unsigned long CATLINK0:1; - unsigned long CATLINK1:1; - unsigned long :28; - } BIT; - } ETHPHYLNK; - char wk0[248]; - union - { - unsigned long LONG; - struct - { - unsigned long SWTAGTYP:16; - unsigned long :15; - unsigned long SWTAGEN:1; - } BIT; - } ETHSWMTC; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long P0HDMODE:1; - unsigned long :1; - unsigned long P1HDMODE:1; - unsigned long :28; - } BIT; - } ETHSWMD; - char wk1[232]; - union - { - unsigned long LONG; - struct - { - unsigned long OUTEN:1; - unsigned long :31; - } BIT; - } SWTMEN; - union - { - unsigned long LONG; - struct - { - unsigned long TMSTSEC:32; - } BIT; - } SWTMSTSEC; - union - { - unsigned long LONG; - struct - { - unsigned long TMSTNS:32; - } BIT; - } SWTMSTNS; - union - { - unsigned long LONG; - struct - { - unsigned long TMPSEC:32; - } BIT; - } SWTMPSEC; - union - { - unsigned long LONG; - struct - { - unsigned long TMPNS:32; - } BIT; - } SWTMPNS; - union - { - unsigned long LONG; - struct - { - unsigned long TMWTH:16; - unsigned long :16; - } BIT; - } SWTMWTH; - char wk2[20]; - union - { - unsigned long LONG; - struct - { - unsigned long TMLATSEC:32; - } BIT; - } SWTMLATSEC; - union - { - unsigned long LONG; - struct - { - unsigned long TMLATNS:32; - } BIT; - } SWTMLATNS; - char wk3[3540]; - union - { - unsigned long LONG; - struct - { - unsigned long P0ENA:1; - unsigned long P1ENA:1; - unsigned long P2ENA:1; - unsigned long :29; - } BIT; - } PORT_ENA; - union - { - unsigned long LONG; - struct - { - unsigned long P0UCASTDM:1; - unsigned long P1UCASTDM:1; - unsigned long P2UCASTDM:1; - unsigned long :29; - } BIT; - } UCAST_DEFAULT_MASK; - char wk4[4]; - union - { - unsigned long LONG; - struct - { - unsigned long P0BCASTDM:1; - unsigned long P1BCASTDM:1; - unsigned long P2BCASTDM:1; - unsigned long :29; - } BIT; - } BCAST_DEFAULT_MASK; - union - { - unsigned long LONG; - struct - { - unsigned long P0MCASTDM:1; - unsigned long P1MCASTDM:1; - unsigned long P2MCASTDM:1; - unsigned long :29; - } BIT; - } MCAST_DEFAULT_MASK; - union - { - unsigned long LONG; - struct - { - unsigned long P0BLOCKEN:1; - unsigned long P1BLOCKEN:1; - unsigned long P2BLOCKEN:1; - unsigned long :13; - unsigned long P0LEARNDIS:1; - unsigned long P1LEARNDIS:1; - unsigned long P2LEARNDIS:1; - unsigned long :13; - } BIT; - } INPUT_LERAN_BLOCK; - union - { - unsigned long LONG; - struct - { - unsigned long PORT:2; - unsigned long :3; - unsigned long MSGTRANS:1; - unsigned long ENABLE:1; - unsigned long DISCARD:1; - unsigned long :5; - unsigned long PRIORITY:3; - unsigned long P0PORTMASK:1; - unsigned long P1PORTMASK:1; - unsigned long :14; - } BIT; - } MGMT_CONFIG; - union - { - unsigned long LONG; - struct - { - unsigned long :31; - unsigned long STATSRESET:1; - } BIT; - } MODE_CONFIG; - char wk5[12]; - union - { - unsigned long LONG; - struct - { - unsigned long VLANTAGID:16; - unsigned long :16; - } BIT; - } VLAN_TAG_ID; - char wk6[72]; - union - { - unsigned long LONG; - struct - { - unsigned long BUSYINIT:1; - unsigned long NOCELL:1; - unsigned long MEMFULL:1; - unsigned long MEMFULL_LT:1; - unsigned long :2; - unsigned long DEQUEGRANT:1; - unsigned long :9; - unsigned long CELLAVILABLE:16; - } BIT; - } OQMGR_STATUS; - union - { - unsigned long LONG; - struct - { - unsigned long MINCELLS:5; - unsigned long :27; - } BIT; - } QMGR_MINCELLS; - union - { - unsigned long LONG; - struct - { - unsigned long STMINCELLS:5; - unsigned long :27; - } BIT; - } QMGR_ST_MINCELLS; - union - { - unsigned long LONG; - struct - { - unsigned long P0CGS:1; - unsigned long P1CGS:1; - unsigned long P2CGS:1; - unsigned long :29; - } BIT; - } QMGR_CGS_STAT; - union - { - unsigned long LONG; - struct - { - unsigned long P0TXFIFOST:1; - unsigned long P1TXFIFOST:1; - unsigned long P2TXFIFOST:1; - unsigned long :13; - unsigned long P0RXFIFOAV:1; - unsigned long P1RXFIFOAV:1; - unsigned long P2RXFIFOAV:1; - unsigned long :13; - } BIT; - } QMGR_IFACE_STAT; - union - { - unsigned long LONG; - struct - { - unsigned long QUEUE0:5; - unsigned long :3; - unsigned long QUEUE1:5; - unsigned long :3; - unsigned long QUEUE2:5; - unsigned long :3; - unsigned long QUEUE3:5; - unsigned long :3; - } BIT; - } QMGR_WEIGHTS; - char wk7[104]; - union - { - unsigned long LONG; - struct - { - unsigned long PRIORITY0:3; - unsigned long PRIORITY1:3; - unsigned long PRIORITY2:3; - unsigned long PRIORITY3:3; - unsigned long PRIORITY4:3; - unsigned long PRIORITY5:3; - unsigned long PRIORITY6:3; - unsigned long PRIORITY7:3; - unsigned long :8; - } BIT; - } VLAN_PRIORITY[3]; - char wk8[52]; - union - { - unsigned long LONG; - struct - { - unsigned long ADDRESS:8; - unsigned long IPV6SELECT:1; - unsigned long PRIORITY:2; - unsigned long :20; - unsigned long READ:1; - } BIT; - } IP_PRIORITY0; - union - { - unsigned long LONG; - struct - { - unsigned long ADDRESS:8; - unsigned long IPV6SELECT:1; - unsigned long PRIORITY:2; - unsigned long :20; - unsigned long READ:1; - } BIT; - } IP_PRIORITY1; - union - { - unsigned long LONG; - struct - { - unsigned long ADDRESS:8; - unsigned long IPV6SELECT:1; - unsigned long PRIORITY:2; - unsigned long :20; - unsigned long READ:1; - } BIT; - } IP_PRIORITY2; - char wk9[52]; - union - { - unsigned long LONG; - struct - { - unsigned long VLANEN:1; - unsigned long IPEN:1; - unsigned long :2; - unsigned long DEFAULTPRI:3; - unsigned long :25; - } BIT; - } PRIORITY_CFG[3]; - char wk10[52]; - union - { - unsigned long LONG; - struct - { - unsigned long HUBEN:1; - unsigned long DIR0TO1EN:1; - unsigned long DIR1TO0EN:1; - unsigned long BROCAFILEN:1; - unsigned long HUBIPG:4; - unsigned long :24; - } BIT; - } HUB_CONTROL; - union - { - unsigned long LONG; - struct - { - unsigned long NUM1TO0:32; - } BIT; - } HUB_STATS; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD1n:8; - unsigned long MACADD2n:8; - unsigned long MACADD3n:8; - unsigned long MACADD4n:8; - } BIT; - } HUB_FLT_MAC0lo; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD5n:8; - unsigned long MACADD6n:8; - unsigned long MASKCOMP:8; - unsigned long FORCEFOW:1; - unsigned long :7; - } BIT; - } HUB_FLT_MAC0hi; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD1n:8; - unsigned long MACADD2n:8; - unsigned long MACADD3n:8; - unsigned long MACADD4n:8; - } BIT; - } HUB_FLT_MAC1lo; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD5n:8; - unsigned long MACADD6n:8; - unsigned long MASKCOMP:8; - unsigned long FORCEFOW:1; - unsigned long :7; - } BIT; - } HUB_FLT_MAC1hi; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD1n:8; - unsigned long MACADD2n:8; - unsigned long MACADD3n:8; - unsigned long MACADD4n:8; - } BIT; - } HUB_FLT_MAC2lo; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD5n:8; - unsigned long MACADD6n:8; - unsigned long MASKCOMP:8; - unsigned long FORCEFOW:1; - unsigned long :7; - } BIT; - } HUB_FLT_MAC2hi; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD1n:8; - unsigned long MACADD2n:8; - unsigned long MACADD3n:8; - unsigned long MACADD4n:8; - } BIT; - } HUB_FLT_MAC3lo; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD5n:8; - unsigned long MACADD6n:8; - unsigned long MASKCOMP:8; - unsigned long FORCEFOW:1; - unsigned long :7; - } BIT; - } HUB_FLT_MAC3hi; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD1n:8; - unsigned long MACADD2n:8; - unsigned long MACADD3n:8; - unsigned long MACADD4n:8; - } BIT; - } HUB_FLT_MAC4lo; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD5n:8; - unsigned long MACADD6n:8; - unsigned long MASKCOMP:8; - unsigned long FORCEFOW:1; - unsigned long :7; - } BIT; - } HUB_FLT_MAC4hi; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD1n:8; - unsigned long MACADD2n:8; - unsigned long MACADD3n:8; - unsigned long MACADD4n:8; - } BIT; - } HUB_FLT_MAC5lo; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD5n:8; - unsigned long MACADD6n:8; - unsigned long MASKCOMP:8; - unsigned long FORCEFOW:1; - unsigned long :7; - } BIT; - } HUB_FLT_MAC5hi; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD1n:8; - unsigned long MACADD2n:8; - unsigned long MACADD3n:8; - unsigned long MACADD4n:8; - } BIT; - } HUB_FLT_MAC6lo; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD5n:8; - unsigned long MACADD6n:8; - unsigned long MASKCOMP:8; - unsigned long FORCEFOW:1; - unsigned long :7; - } BIT; - } HUB_FLT_MAC6hi; - char wk11[256]; - unsigned long TOTAL_BYT_FRM; - unsigned long TOTAL_BYT_DISC; - unsigned long TOTAL_FRM; - unsigned long TOTAL_DISC; - unsigned long ODISC0; - unsigned long IDISC_BLOCKED0; - unsigned long ODISC1; - unsigned long IDISC_BLOCKED1; - unsigned long ODISC2; - unsigned long IDISC_BLOCKED2; - char wk12[472]; - union - { - unsigned long LONG; - struct - { - unsigned long SRCADD1:8; - unsigned long SRCADD2:8; - unsigned long SRCADD3:8; - unsigned long SRCADD4:8; - } BIT; - } LRN_REC_A; - union - { - unsigned long LONG; - struct - { - unsigned long SRCADD5:8; - unsigned long SRCADD6:8; - unsigned long HASH:8; - unsigned long PORT:4; - unsigned long :4; - } BIT; - } LRN_REC_B; - union - { - unsigned long LONG; - struct - { - unsigned long LERNAVAL:1; - unsigned long :31; - } BIT; - } LRN_STATUS; - char wk13[0x4000-0x050C]; - char ADR_TABLE[0x8000-0x4000]; - struct - { - char mac_wk01[8]; - union - { - unsigned long LONG; - struct - { - unsigned long TXENA:1; - unsigned long RXENA:1; - unsigned long :11; - unsigned long SWRESET:1; - unsigned long :9; - unsigned long CNTRLREMEN:1; - unsigned long NOLGTHCHK:1; - unsigned long :1; - unsigned long RXERRDISC:1; - unsigned long :4; - unsigned long CNTRESET:1; - } BIT; - } COMMAND_CONFIG; - char mac_wk02[8]; - union - { - unsigned long LONG; - struct - { - unsigned long FRMLEN:14; - unsigned long :18; - } BIT; - } FRM_LENGTH; - char mac_wk03[4]; - unsigned long RX_SECTION_EMPTY; - unsigned long RX_SECTION_FULL; - unsigned long TX_SECTION_EMPTY; - unsigned long TX_SECTION_FULL; - unsigned long RX_ALMOST_EMPTY; - unsigned long RX_ALMOST_FULL; - unsigned long TX_ALMOST_EMPTY; - unsigned long TX_ALMOST_FULL; - char mac_wk04[28]; - union - { - unsigned long LONG; - struct - { - unsigned long :8; - unsigned long SPEEDP0:1; - unsigned long :1; - unsigned long HDPP0:1; - unsigned long :1; - unsigned long SPEEDP1:1; - unsigned long :1; - unsigned long HDPP1:1; - unsigned long :17; - } BIT; - } MAC_STATUS; - union - { - unsigned long LONG; - struct - { - unsigned long TXIPGLEN:5; - unsigned long :27; - } BIT; - } TX_IPG_LENGTH; - char mac_wk05[160]; - unsigned long etherStatsOctets; - unsigned long OctetsOK; - unsigned long aAlignmentErrors; - unsigned long aPAUSEMACCtrlFrames; - unsigned long FramesOK; - unsigned long CRCErrors; - unsigned long VLANOK; - unsigned long ifInErrors; - unsigned long ifInUcastPkts; - unsigned long ifInMulticastPkts; - unsigned long ifInBroadcastPkts; - unsigned long etherStatsDropEvents; - unsigned long etherStatsPkts; - unsigned long etherStatsUndersizePkts; - unsigned long etherStatsPkts64Octets; - unsigned long etherStatsPkts65to127Octets; - unsigned long etherStatsPkts128to255Octets; - unsigned long etherStatsPkts256to511Octets; - unsigned long etherStatsPkts512to1023Octets; - unsigned long etherStatsPkts1024to1518Octets; - unsigned long etherStatsPkts1519toMax; - unsigned long etherStatsOversizePkts; - unsigned long etherStatsJabbers; - unsigned long etherStatsFragments; - unsigned long aMACControlFramesReceived; - unsigned long aFrameTooLong; - char mac_wk06[4]; - unsigned long StackedVLANOK; - char mac_wk07[16]; - unsigned long TXetherStatsOctets; - unsigned long TxOctetsOK; - char mac_wk08[4]; - unsigned long TXaPAUSEMACCtrlFrames; - unsigned long TxFramesOK; - unsigned long TxCRCErrors; - unsigned long TxVLANOK; - unsigned long ifOutErrors; - unsigned long ifUcastPkts; - unsigned long ifMulticastPkts; - unsigned long ifBroadcastPkts; - unsigned long TXetherStatsDropEvents; - unsigned long TXetherStatsPkts; - unsigned long TXetherStatsUndersizePkts; - unsigned long TXetherStatsPkts64Octets; - unsigned long TXetherStatsPkts65to127Octets; - unsigned long TXetherStatsPkts128to255Octets; - unsigned long TXetherStatsPkts256to511Octets; - unsigned long TXetherStatsPkts512to1023Octets; - unsigned long TXetherStatsPkts1024to1518Octets; - unsigned long TXetherStatsPkts1519toMax; - unsigned long TXetherStatsOversizePkts; - unsigned long TXetherStatsJabbers; - unsigned long TXetherStatsFragments; - unsigned long aMACControlFrames; - unsigned long TXaFrameTooLong; - char mac_wk09[4]; - unsigned long aMultipleCollisions; - unsigned long aSingleCollisions; - unsigned long aLateCollisions; - unsigned long aExcessCollisions; - char mac_wk10[0xA000-0x81FC]; - } MAC[2]; - char wk32[4]; - union - { - unsigned long LONG; - struct - { - unsigned long IRQENA:1; - unsigned long IRQEVTOFF:1; - unsigned long IRQEVTPERD:1; - unsigned long IRQTIMOVER:1; - unsigned long IRQTEST:1; - unsigned long :7; - unsigned long IRQTXENAP0:1; - unsigned long IRQTXENAP1:1; - unsigned long :18; - } BIT; - } TSM_CONFIG; - union - { - unsigned long LONG; - struct - { - unsigned long IRQENA:1; - unsigned long IRQEVTOFF:1; - unsigned long IRQEVTPERD:1; - unsigned long IRQTIMOVER:1; - unsigned long IRQTEST:1; - unsigned long :7; - unsigned long IRQTXP0:1; - unsigned long IRQTXP1:1; - unsigned long :18; - } BIT; - } TSM_IRQ_STAT_ACK; - char wk33[20]; - union - { - unsigned long LONG; - struct - { - unsigned long TSVALID:1; - unsigned long TSOVR:1; - unsigned long TSKEEP:1; - unsigned long :29; - } BIT; - } PORT0_CTRL; - union - { - unsigned long LONG; - struct - { - unsigned long TSREG:32; - } BIT; - } PORT0_TIME; - union - { - unsigned long LONG; - struct - { - unsigned long TSVALID:1; - unsigned long TSOVR:1; - unsigned long TSKEEP:1; - unsigned long :29; - } BIT; - } PORT1_CTRL; - union - { - unsigned long LONG; - struct - { - unsigned long TSREG:32; - } BIT; - } PORT1_TIME; - char wk34[240]; - union - { - unsigned long LONG; - struct - { - unsigned long TMENA:1; - unsigned long :1; - unsigned long EVTOFFENA:1; - unsigned long :1; - unsigned long EVTPERIENA:1; - unsigned long EVTPERIRST:1; - unsigned long :3; - unsigned long RST:1; - unsigned long :1; - unsigned long CAPTR:1; - unsigned long PLUS1:1; - unsigned long :19; - } BIT; - } ATIME_CTRL; - union - { - unsigned long LONG; - struct - { - unsigned long TMR:32; - } BIT; - } ATIME; - union - { - unsigned long LONG; - struct - { - unsigned long OFFSET:32; - } BIT; - } ATIME_OFFSET; - union - { - unsigned long LONG; - struct - { - unsigned long TIMPEREVET:32; - } BIT; - } ATIME_EVT_PERIOD; - union - { - unsigned long LONG; - struct - { - unsigned long DRIFCORVAL:31; - unsigned long :1; - } BIT; - } ATIME_CORR; - union - { - unsigned long LONG; - struct - { - unsigned long CLKPERD:7; - unsigned long :1; - unsigned long CORRINC:7; - unsigned long :1; - unsigned long OFFSCORRINC:7; - unsigned long :9; - } BIT; - } ATIME_INC; - union - { - unsigned long LONG; - struct - { - unsigned long SECTIM:32; - } BIT; - } ATIME_SEC; - union - { - unsigned long LONG; - struct - { - unsigned long OFFCOR:32; - } BIT; - } ATIME_CORR_OFFS; - char wk35[7872]; - union - { - unsigned long LONG; - struct - { - unsigned long DLRENA:1; - unsigned long :3; - unsigned long BECTIMOUT:1; - unsigned long :3; - unsigned long CYCMCLK:8; - unsigned long :16; - } BIT; - } DLR_CONTROL; - union - { - unsigned long LONG; - struct - { - unsigned long BEAREV0:1; - unsigned long BEAREV1:1; - unsigned long :6; - unsigned long CURRSTA:8; - unsigned long LINSTAP0:1; - unsigned long LINSTAP1:1; - unsigned long :6; - unsigned long NETTOPGY:8; - } BIT; - } DLR_STATUS; - union - { - unsigned long LONG; - struct - { - unsigned long ETHTYPDLR:16; - unsigned long :16; - } BIT; - } DLR_ETH_TYP; - union - { - unsigned long LONG; - struct - { - unsigned long IRQCHNGENA:1; - unsigned long IRQFLUENA:1; - unsigned long IRQSTOPP0:1; - unsigned long IRQSTOPP1:1; - unsigned long IRQBECTOUT0:1; - unsigned long IRQBECTOUT1:1; - unsigned long IRQSUPENA:1; - unsigned long IRQLINKENA0:1; - unsigned long IRQLINKENA1:1; - unsigned long IRQSUPIGENA:1; - unsigned long IRQIPADDREN:1; - unsigned long IRQINVTMREN:1; - unsigned long IRQBECENA0:1; - unsigned long IRQBECENA1:1; - unsigned long IRQFRMDSP0:1; - unsigned long IRQFRMDSP1:1; - unsigned long :14; - unsigned long ATOMICOR:1; - unsigned long ATOMICAND:1; - } BIT; - } DLR_IRQ_CTRL; - union - { - unsigned long LONG; - struct - { - unsigned long STACHANGE:1; - unsigned long FLUEVENT:1; - unsigned long STOPNBCHK0:1; - unsigned long STOPNBCHK1:1; - unsigned long BECTMRP0:1; - unsigned long BECTMRP1:1; - unsigned long SUPRCHAG:1; - unsigned long LINKSTAP0:1; - unsigned long LINKSTAP1:1; - unsigned long SUPIGNBEC:1; - unsigned long IPCHANEVET:1; - unsigned long INVTMR:1; - unsigned long BECFRAP0:1; - unsigned long BECFRAP1:1; - unsigned long FRMDISP0:1; - unsigned long FRMDISP1:1; - unsigned long :16; - } BIT; - } DLR_IRQ_STAT_ACK; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD1:8; - unsigned long MACADD2:8; - unsigned long MACADD3:8; - unsigned long MACADD4:8; - } BIT; - } LOC_MAClo; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD5:8; - unsigned long MACADD6:8; - unsigned long :16; - } BIT; - } LOC_MAChi; - char wk36[4]; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD1:8; - unsigned long MACADD2:8; - unsigned long MACADD3:8; - unsigned long MACADD4:8; - } BIT; - } SUPR_MAClo; - union - { - unsigned long LONG; - struct - { - unsigned long MACADD5:8; - unsigned long MACADD6:8; - unsigned long SUPRPRE:8; - unsigned long :8; - } BIT; - } SUPR_MAChi; - union - { - unsigned long LONG; - struct - { - unsigned long RINGSTATE:8; - unsigned long VLANVALID:1; - unsigned long :7; - unsigned long VLANCI:16; - } BIT; - } STATE_VLAN; - union - { - unsigned long LONG; - struct - { - unsigned long BECTMOUT:32; - } BIT; - } BEC_TMOUT; - union - { - unsigned long LONG; - struct - { - unsigned long BECINTVAL:32; - } BIT; - } BEC_INTRVL; - union - { - unsigned long LONG; - struct - { - unsigned long SPVIP:32; - } BIT; - } SUPR_IPADR; - union - { - unsigned long LONG; - struct - { - unsigned long DLRRINGTPY:8; - unsigned long DLRRINGVER:8; - unsigned long SOURP:8; - unsigned long :8; - } BIT; - } ETH_STYP_VER; - union - { - unsigned long LONG; - struct - { - unsigned long INVBECTMOUT:32; - } BIT; - } INV_TMOUT; - unsigned long SEQ_ID; - char wk37[28]; - unsigned long RX_STAT0; - unsigned long RX_ERR_STAT0; - unsigned long TX_STAT0; - char wk38[4]; - unsigned long RX_STAT1; - unsigned long RX_ERR_STAT1; - unsigned long TX_STAT1; -}; - -struct st_gpt -{ - union - { - unsigned short WORD; - struct - { - unsigned short CST0:1; - unsigned short CST1:1; - unsigned short CST2:1; - unsigned short CST3:1; - unsigned short :12; - } BIT; - } GTSTR; - union - { - unsigned short WORD; - struct - { - unsigned short NFA0EN:1; - unsigned short NFB0EN:1; - unsigned short NFA1EN:1; - unsigned short NFB1EN:1; - unsigned short NFA2EN:1; - unsigned short NFB2EN:1; - unsigned short NFA3EN:1; - unsigned short NFB3EN:1; - unsigned short NFCS0:2; - unsigned short NFCS1:2; - unsigned short NFCS2:2; - unsigned short NFCS3:2; - } BIT; - } NFCR; - union - { - unsigned short WORD; - struct - { - unsigned short CSHW0:2; - unsigned short CSHW1:2; - unsigned short CSHW2:2; - unsigned short CSHW3:2; - unsigned short CPHW0:2; - unsigned short CPHW1:2; - unsigned short CPHW2:2; - unsigned short CPHW3:2; - } BIT; - } GTHSCR; - union - { - unsigned short WORD; - struct - { - unsigned short CCHW0:2; - unsigned short CCHW1:2; - unsigned short CCHW2:2; - unsigned short CCHW3:2; - unsigned short CCSW0:1; - unsigned short CCSW1:1; - unsigned short CCSW2:1; - unsigned short CCSW3:1; - unsigned short :4; - } BIT; - } GTHCCR; - union - { - unsigned short WORD; - struct - { - unsigned short CSHSL0:4; - unsigned short CSHSL1:4; - unsigned short CSHSL2:4; - unsigned short CSHSL3:4; - } BIT; - } GTHSSR; - union - { - unsigned short WORD; - struct - { - unsigned short CSHPL0:4; - unsigned short CSHPL1:4; - unsigned short CSHPL2:4; - unsigned short CSHPL3:4; - } BIT; - } GTHPSR; - union - { - unsigned short WORD; - struct - { - unsigned short WP0:1; - unsigned short WP1:1; - unsigned short WP2:1; - unsigned short WP3:1; - unsigned short :12; - } BIT; - } GTWP; - union - { - unsigned short WORD; - struct - { - unsigned short SYNC0:2; - unsigned short :2; - unsigned short SYNC1:2; - unsigned short :2; - unsigned short SYNC2:2; - unsigned short :2; - unsigned short SYNC3:2; - unsigned short :2; - } BIT; - } GTSYNC; - union - { - unsigned short WORD; - struct - { - unsigned short ETIPEN:1; - unsigned short ETINEN:1; - unsigned short :11; - unsigned short GTENFCS:2; - unsigned short GTETRGEN:1; - } BIT; - } GTETINT; - char wk0[2]; - union - { - unsigned short WORD; - struct - { - unsigned short BD00:1; - unsigned short BD01:1; - unsigned short BD02:1; - unsigned short BD03:1; - unsigned short BD10:1; - unsigned short BD11:1; - unsigned short BD12:1; - unsigned short BD13:1; - unsigned short BD20:1; - unsigned short BD21:1; - unsigned short BD22:1; - unsigned short BD23:1; - unsigned short BD30:1; - unsigned short BD31:1; - unsigned short BD32:1; - unsigned short BD33:1; - } BIT; - } GTBDR; - char wk1[2]; - union - { - unsigned short WORD; - struct - { - unsigned short SWP0:1; - unsigned short SWP1:1; - unsigned short SWP2:1; - unsigned short SWP3:1; - unsigned short :12; - } BIT; - } GTSWP; -}; - -struct st_gpt0 -{ - union - { - unsigned short WORD; - struct - { - unsigned short GTIOA:6; - unsigned short OADFLT:1; - unsigned short OAHLD:1; - unsigned short GTIOB:6; - unsigned short OBDFLT:1; - unsigned short OBHLD:1; - } BIT; - } GTIOR; - union - { - unsigned short WORD; - struct - { - unsigned short GTINTA:1; - unsigned short GTINTB:1; - unsigned short GTINTC:1; - unsigned short GTINTD:1; - unsigned short GTINTE:1; - unsigned short GTINTF:1; - unsigned short GTINTPR:2; - unsigned short :3; - unsigned short EINT:1; - unsigned short ADTRAUEN:1; - unsigned short ADTRADEN:1; - unsigned short ADTRBUEN:1; - unsigned short ADTRBDEN:1; - } BIT; - } GTINTAD; - union - { - unsigned short WORD; - struct - { - unsigned short MD:3; - unsigned short :5; - unsigned short TPCS:2; - unsigned short :2; - unsigned short CCLR:2; - unsigned short :2; - } BIT; - } GTCR; - union - { - unsigned short WORD; - struct - { - unsigned short CCRA:2; - unsigned short CCRB:2; - unsigned short PR:2; - unsigned short CCRSWT:1; - unsigned short :1; - unsigned short ADTTA:2; - unsigned short ADTDA:1; - unsigned short :1; - unsigned short ADTTB:2; - unsigned short ADTDB:1; - unsigned short :1; - } BIT; - } GTBER; - union - { - unsigned short WORD; - struct - { - unsigned short UD:1; - unsigned short UDF:1; - unsigned short :14; - } BIT; - } GTUDC; - union - { - unsigned short WORD; - struct - { - unsigned short ITLA:1; - unsigned short ITLB:1; - unsigned short ITLC:1; - unsigned short ITLD:1; - unsigned short ITLE:1; - unsigned short ITLF:1; - unsigned short IVTC:2; - unsigned short IVTT:3; - unsigned short :1; - unsigned short ADTAL:1; - unsigned short :1; - unsigned short ADTBL:1; - unsigned short :1; - } BIT; - } GTITC; - union - { - unsigned short WORD; - struct - { - unsigned short :8; - unsigned short ITCNT:3; - unsigned short DTEF:1; - unsigned short :3; - unsigned short TUCF:1; - } BIT; - } GTST; - unsigned short GTCNT; - unsigned short GTCCRA; - unsigned short GTCCRB; - unsigned short GTCCRC; - unsigned short GTCCRD; - unsigned short GTCCRE; - unsigned short GTCCRF; - unsigned short GTPR; - unsigned short GTPBR; - unsigned short GTPDBR; - char wk0[2]; - unsigned short GTADTRA; - unsigned short GTADTBRA; - unsigned short GTADTDBRA; - char wk1[2]; - unsigned short GTADTRB; - unsigned short GTADTBRB; - unsigned short GTADTDBRB; - char wk2[2]; - union - { - unsigned short WORD; - struct - { - unsigned short NEA:1; - unsigned short NEB:1; - unsigned short NVA:1; - unsigned short NVB:1; - unsigned short NFS:4; - unsigned short NFV:1; - unsigned short :3; - unsigned short SWN:1; - unsigned short :1; - unsigned short OAE:1; - unsigned short OBE:1; - } BIT; - } GTONCR; - union - { - unsigned short WORD; - struct - { - unsigned short TDE:1; - unsigned short :3; - unsigned short TDBUE:1; - unsigned short TDBDE:1; - unsigned short :2; - unsigned short TDFER:1; - unsigned short :7; - } BIT; - } GTDTCR; - unsigned short GTDVU; - unsigned short GTDVD; - unsigned short GTDBU; - unsigned short GTDBD; - union - { - unsigned short WORD; - struct - { - unsigned short SOS:2; - unsigned short :14; - } BIT; - } GTSOS; - union - { - unsigned short WORD; - struct - { - unsigned short SOTR:1; - unsigned short :15; - } BIT; - } GTSOTR; -}; - -struct st_icu -{ - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR0; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR1; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR2; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR3; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR4; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR5; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR6; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR7; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR8; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR9; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR10; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR11; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR12; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR13; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR14; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long IRQMD:2; - unsigned long :28; - } BIT; - } IRQCR15; - union - { - unsigned long LONG; - struct - { - unsigned long FLTEN0:1; - unsigned long FLTEN1:1; - unsigned long FLTEN2:1; - unsigned long FLTEN3:1; - unsigned long FLTEN4:1; - unsigned long FLTEN5:1; - unsigned long FLTEN6:1; - unsigned long FLTEN7:1; - unsigned long FLTEN8:1; - unsigned long FLTEN9:1; - unsigned long FLTEN10:1; - unsigned long FLTEN11:1; - unsigned long FLTEN12:1; - unsigned long FLTEN13:1; - unsigned long FLTEN14:1; - unsigned long FLTEN15:1; - unsigned long :16; - } BIT; - } IRQFLTE; - union - { - unsigned long LONG; - struct - { - unsigned long FCLKSEL0:2; - unsigned long FCLKSEL1:2; - unsigned long FCLKSEL2:2; - unsigned long FCLKSEL3:2; - unsigned long FCLKSEL4:2; - unsigned long FCLKSEL5:2; - unsigned long FCLKSEL6:2; - unsigned long FCLKSEL7:2; - unsigned long FCLKSEL8:2; - unsigned long FCLKSEL9:2; - unsigned long FCLKSEL10:2; - unsigned long FCLKSEL11:2; - unsigned long FCLKSEL12:2; - unsigned long FCLKSEL13:2; - unsigned long FCLKSEL14:2; - unsigned long FCLKSEL15:2; - } BIT; - } IRQFLTC; - union - { - unsigned long LONG; - struct - { - unsigned long NMIST:1; - unsigned long ECMST:1; - unsigned long :30; - } BIT; - } NMISR; - union - { - unsigned long LONG; - struct - { - unsigned long NMICLR:1; - unsigned long ECMCLR:1; - unsigned long :30; - } BIT; - } NMICLR; - union - { - unsigned long LONG; - struct - { - unsigned long :3; - unsigned long NMIMD:1; - unsigned long :28; - } BIT; - } NMICR; - union - { - unsigned long LONG; - struct - { - unsigned long NFLTEN:1; - unsigned long :31; - } BIT; - } NMIFLTE; - union - { - unsigned long LONG; - struct - { - unsigned long NFCLKSEL:2; - unsigned long :30; - } BIT; - } NMIFLTC; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long EPHYMD:2; - unsigned long :28; - } BIT; - } EPHYCR0; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long EPHYMD:2; - unsigned long :28; - } BIT; - } EPHYCR1; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long EPHYMD:2; - unsigned long :28; - } BIT; - } EPHYCR2; - union - { - unsigned long LONG; - struct - { - unsigned long EFLTEN0:1; - unsigned long EFLTEN1:1; - unsigned long EFLTEN2:1; - unsigned long :29; - } BIT; - } EPHYFLTE; - union - { - unsigned long LONG; - struct - { - unsigned long EFCLKSEL0:2; - unsigned long EFCLKSEL1:2; - unsigned long EFCLKSEL2:2; - unsigned long :26; - } BIT; - } EPHYFLTC; - union - { - unsigned long LONG; - struct - { - unsigned long DFLTEN0:1; - unsigned long DFLTEN1:1; - unsigned long DFLTEN2:1; - unsigned long :29; - } BIT; - } DREQFLTE; - union - { - unsigned long LONG; - struct - { - unsigned long DFCLKSEL0:2; - unsigned long DFCLKSEL1:2; - unsigned long DFCLKSEL2:2; - unsigned long :26; - } BIT; - } DREQFLTC; - char wk0[24]; - union - { - unsigned long LONG; - struct - { - unsigned long CM3INT:1; - unsigned long :15; - unsigned long CR4INT:1; - unsigned long :15; - } BIT; - } CPUINT; -}; - -struct st_iwdt -{ - union - { - unsigned char BYTE; - struct - { - unsigned char REFRESH:8; - } BIT; - } IWDTRR; - char wk0[1]; - union - { - unsigned short WORD; - struct - { - unsigned short TOPS:2; - unsigned short :2; - unsigned short CKS:4; - unsigned short RPES:2; - unsigned short :2; - unsigned short RPSS:2; - unsigned short :2; - } BIT; - } IWDTCR; - union - { - unsigned short WORD; - struct - { - unsigned short CNTVAL:14; - unsigned short UNDFF:1; - unsigned short REFEF:1; - } BIT; - } IWDTSR; - union - { - unsigned char BYTE; - struct - { - unsigned char :7; - unsigned char RSTIRQS:1; - } BIT; - } IWDTRCR; -}; - -struct st_mpc -{ - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } P00PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } P01PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } P02PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } P03PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } P04PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } P05PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } P06PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } P07PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P10PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P11PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P12PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P13PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P14PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P15PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P16PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P17PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P20PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P21PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P22PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P23PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P24PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P25PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P26PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P27PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P30PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P31PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P32PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P33PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P34PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P35PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P36PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P37PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P40PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P41PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P42PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P43PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P44PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P45PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P46PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P47PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P50PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P51PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P52PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P53PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P54PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P55PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P56PFS; - char wk0[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P60PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P61PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P62PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P63PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P64PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P65PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P66PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P67PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P70PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P71PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P72PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P73PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P74PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P75PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P76PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } P77PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P80PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P81PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P82PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P83PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P84PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P85PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P86PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P87PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P90PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P91PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P92PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P93PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P94PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P95PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P96PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char ASEL:1; - } BIT; - } P97PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PA0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PA1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PA2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PA3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PA4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PA5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PA6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PA7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PB0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PB1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PB2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PB3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PB4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PB5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PB6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PB7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PC0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PC1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PC2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PC3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PC4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PC5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PC6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PC7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :1; - unsigned char ASEL:1; - } BIT; - } PD0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :1; - unsigned char ASEL:1; - } BIT; - } PD1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :1; - unsigned char ASEL:1; - } BIT; - } PD2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :1; - unsigned char ASEL:1; - } BIT; - } PD3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :1; - unsigned char ASEL:1; - } BIT; - } PD4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :1; - unsigned char ASEL:1; - } BIT; - } PD5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :1; - unsigned char ASEL:1; - } BIT; - } PD6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :1; - unsigned char ASEL:1; - } BIT; - } PD7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PE0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PE1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PE2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PE3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PE4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PE5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PE6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PE7PFS; - char wk1[5]; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PF5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PF6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PF7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PG0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PG1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PG2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PG3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PG4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PG5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PG6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PG7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PH0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PH1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PH2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PH3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PH4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PH5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PH6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PH7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PJ0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PJ1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PJ2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PJ3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PJ4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PJ5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PJ6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PJ7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PK0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PK1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PK2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PK3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PK4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PK5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PK6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PK7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PL0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PL1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PL2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PL3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PL4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PL5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PL6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PL7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PM0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PM1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PM2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PM3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PM4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PM5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PM6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PM7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PN0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PN1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PN2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PN3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PN4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PN5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PN6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PN7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PP0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PP1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PP2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PP3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PP4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PP5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PP6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char :2; - } BIT; - } PP7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PR0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PR1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PR2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PR3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PR4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PR5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PR6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PR7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PS0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PS1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PS2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PS3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PS4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PS5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PS6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PS7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PT0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PT1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PT2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PT3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PT4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PT5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PT6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PT7PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PU0PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PU1PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PU2PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PU3PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PU4PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PU5PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PU6PFS; - union - { - unsigned char BYTE; - struct - { - unsigned char PSEL:6; - unsigned char ISEL:1; - unsigned char :1; - } BIT; - } PU7PFS; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char :6; - unsigned char PFSWE:1; - unsigned char B0WI:1; - } BIT; - } PWPR; -}; - -struct st_mtu -{ - union - { - unsigned char BYTE; - struct - { - unsigned char OE3B:1; - unsigned char OE4A:1; - unsigned char OE4B:1; - unsigned char OE3D:1; - unsigned char OE4C:1; - unsigned char OE4D:1; - unsigned char :2; - } BIT; - } TOERA; - char wk0[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char UF:1; - unsigned char VF:1; - unsigned char WF:1; - unsigned char FB:1; - unsigned char P:1; - unsigned char N:1; - unsigned char BDC:1; - unsigned char :1; - } BIT; - } TGCRA; - union - { - unsigned char BYTE; - struct - { - unsigned char OLSP:1; - unsigned char OLSN:1; - unsigned char TOCS:1; - unsigned char TOCL:1; - unsigned char :2; - unsigned char PSYE:1; - unsigned char :1; - } BIT; - } TOCR1A; - union - { - unsigned char BYTE; - struct - { - unsigned char OLS1P:1; - unsigned char OLS1N:1; - unsigned char OLS2P:1; - unsigned char OLS2N:1; - unsigned char OLS3P:1; - unsigned char OLS3N:1; - unsigned char BF:2; - } BIT; - } TOCR2A; - char wk1[4]; - unsigned short TCDRA; - unsigned short TDDRA; - char wk2[8]; - unsigned short TCNTSA; - unsigned short TCBRA; - char wk3[12]; - union - { - unsigned char BYTE; - struct - { - unsigned char T4VCOR:3; - unsigned char T4VEN:1; - unsigned char T3ACOR:3; - unsigned char T3AEN:1; - } BIT; - } TITCR1A; - union - { - unsigned char BYTE; - struct - { - unsigned char T4VCNT:3; - unsigned char :1; - unsigned char T3ACNT:3; - unsigned char :1; - } BIT; - } TITCNT1A; - union - { - unsigned char BYTE; - struct - { - unsigned char BTE:2; - unsigned char :6; - } BIT; - } TBTERA; - char wk4[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TDER:1; - unsigned char :7; - } BIT; - } TDERA; - char wk5[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char OLS1P:1; - unsigned char OLS1N:1; - unsigned char OLS2P:1; - unsigned char OLS2N:1; - unsigned char OLS3P:1; - unsigned char OLS3N:1; - unsigned char :2; - } BIT; - } TOLBRA; - char wk6[3]; - union - { - unsigned char BYTE; - struct - { - unsigned char TITM:1; - unsigned char :7; - } BIT; - } TITMRA; - union - { - unsigned char BYTE; - struct - { - unsigned char TRG4COR:3; - unsigned char :5; - } BIT; - } TITCR2A; - union - { - unsigned char BYTE; - struct - { - unsigned char TRG4CNT:3; - unsigned char :5; - } BIT; - } TITCNT2A; - char wk7[35]; - union - { - unsigned char BYTE; - struct - { - unsigned char WRE:1; - unsigned char SCC:1; - unsigned char :5; - unsigned char CCE:1; - } BIT; - } TWCRA; - char wk8[15]; - union - { - unsigned char BYTE; - struct - { - unsigned char DRS:1; - unsigned char :7; - } BIT; - } TMDR2A; - char wk9[15]; - union - { - unsigned char BYTE; - struct - { - unsigned char CST0:1; - unsigned char CST1:1; - unsigned char CST2:1; - unsigned char CST8:1; - unsigned char :2; - unsigned char CST3:1; - unsigned char CST4:1; - } BIT; - } TSTRA; - union - { - unsigned char BYTE; - struct - { - unsigned char SYNC0:1; - unsigned char SYNC1:1; - unsigned char SYNC2:1; - unsigned char :3; - unsigned char SYNC3:1; - unsigned char SYNC4:1; - } BIT; - } TSYRA; - union - { - unsigned char BYTE; - struct - { - unsigned char SCH7:1; - unsigned char SCH6:1; - unsigned char :1; - unsigned char SCH4:1; - unsigned char SCH3:1; - unsigned char SCH2:1; - unsigned char SCH1:1; - unsigned char SCH0:1; - } BIT; - } TCSYSTR; - char wk10[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char RWE:1; - unsigned char :7; - } BIT; - } TRWERA; - char wk11[1925]; - union - { - unsigned char BYTE; - struct - { - unsigned char OE6B:1; - unsigned char OE7A:1; - unsigned char OE7B:1; - unsigned char OE6D:1; - unsigned char OE7C:1; - unsigned char OE7D:1; - unsigned char :2; - } BIT; - } TOERB; - char wk12[3]; - union - { - unsigned char BYTE; - struct - { - unsigned char OLSP:1; - unsigned char OLSN:1; - unsigned char TOCS:1; - unsigned char TOCL:1; - unsigned char :2; - unsigned char PSYE:1; - unsigned char :1; - } BIT; - } TOCR1B; - union - { - unsigned char BYTE; - struct - { - unsigned char OLS1P:1; - unsigned char OLS1N:1; - unsigned char OLS2P:1; - unsigned char OLS2N:1; - unsigned char OLS3P:1; - unsigned char OLS3N:1; - unsigned char BF:2; - } BIT; - } TOCR2B; - char wk13[4]; - unsigned short TCDRB; - unsigned short TDDRB; - char wk14[8]; - unsigned short TCNTSB; - unsigned short TCBRB; - char wk15[12]; - union - { - unsigned char BYTE; - struct - { - unsigned char T7VCOR:3; - unsigned char T7VEN:1; - unsigned char T6ACOR:3; - unsigned char T6AEN:1; - } BIT; - } TITCR1B; - union - { - unsigned char BYTE; - struct - { - unsigned char T7VCNT:3; - unsigned char :1; - unsigned char T6ACNT:3; - unsigned char :1; - } BIT; - } TITCNT1B; - union - { - unsigned char BYTE; - struct - { - unsigned char BTE:2; - unsigned char :6; - } BIT; - } TBTERB; - char wk16[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TDER:1; - unsigned char :7; - } BIT; - } TDERB; - char wk17[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char OLS1P:1; - unsigned char OLS1N:1; - unsigned char OLS2P:1; - unsigned char OLS2N:1; - unsigned char OLS3P:1; - unsigned char OLS3N:1; - unsigned char :2; - } BIT; - } TOLBRB; - char wk18[3]; - union - { - unsigned char BYTE; - struct - { - unsigned char TITM:1; - unsigned char :7; - } BIT; - } TITMRB; - union - { - unsigned char BYTE; - struct - { - unsigned char TRG7COR:3; - unsigned char :5; - } BIT; - } TITCR2B; - union - { - unsigned char BYTE; - struct - { - unsigned char TRG7CNT:3; - unsigned char :5; - } BIT; - } TITCNT2B; - char wk19[35]; - union - { - unsigned char BYTE; - struct - { - unsigned char WRE:1; - unsigned char SCC:1; - unsigned char :5; - unsigned char CCE:1; - } BIT; - } TWCRB; - char wk20[15]; - union - { - unsigned char BYTE; - struct - { - unsigned char DRS:1; - unsigned char :7; - } BIT; - } TMDR2B; - char wk21[15]; - union - { - unsigned char BYTE; - struct - { - unsigned char :6; - unsigned char CST6:1; - unsigned char CST7:1; - } BIT; - } TSTRB; - union - { - unsigned char BYTE; - struct - { - unsigned char :6; - unsigned char SYNC6:1; - unsigned char SYNC7:1; - } BIT; - } TSYRB; - char wk22[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char RWE:1; - unsigned char :7; - } BIT; - } TRWERB; -}; - -struct st_mtu0 -{ - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR0; - char wk0[8]; - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCSC:2; - unsigned char :2; - } BIT; - } NFCRC; - char wk1[102]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char BFE:1; - unsigned char :1; - } BIT; - } TMDR1; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIORH; - union - { - unsigned char BYTE; - struct - { - unsigned char IOC:4; - unsigned char IOD:4; - } BIT; - } TIORL; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char :2; - unsigned char TTGE:1; - } BIT; - } TIER; - char wk2[1]; - unsigned short TCNT; - unsigned short TGRA; - unsigned short TGRB; - unsigned short TGRC; - unsigned short TGRD; - char wk3[16]; - unsigned short TGRE; - unsigned short TGRF; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEE:1; - unsigned char TGIEF:1; - unsigned char :5; - unsigned char TTGE2:1; - } BIT; - } TIER2; - char wk4[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TTSA:1; - unsigned char TTSB:1; - unsigned char TTSE:1; - unsigned char :5; - } BIT; - } TBTM; - char wk5[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC2:3; - unsigned char :5; - } BIT; - } TCR2; -}; - -struct st_mtu1 -{ - char wk0[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR1; - char wk1[238]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char :4; - } BIT; - } TMDR1; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIOR; - char wk2[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char :2; - unsigned char TCIEV:1; - unsigned char TCIEU:1; - unsigned char :1; - unsigned char TTGE:1; - } BIT; - } TIER; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char :2; - unsigned char TCFV:1; - unsigned char TCFU:1; - unsigned char :1; - unsigned char TCFD:1; - } BIT; - } TSR; - unsigned short TCNT; - unsigned short TGRA; - unsigned short TGRB; - char wk3[4]; - union - { - unsigned char BYTE; - struct - { - unsigned char I1AE:1; - unsigned char I1BE:1; - unsigned char I2AE:1; - unsigned char I2BE:1; - unsigned char :4; - } BIT; - } TICCR; - union - { - unsigned char BYTE; - struct - { - unsigned char LWA:1; - unsigned char PHCKSEL:1; - unsigned char :6; - } BIT; - } TMDR3; - char wk4[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC2:3; - unsigned char PCB:2; - unsigned char :3; - } BIT; - } TCR2; - char wk5[11]; - unsigned long TCNTLW; - unsigned long TGRALW; - unsigned long TGRBLW; -}; - -struct st_mtu2 -{ - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR2; - char wk0[365]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char :4; - } BIT; - } TMDR1; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIOR; - char wk1[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char :2; - unsigned char TCIEV:1; - unsigned char TCIEU:1; - unsigned char :1; - unsigned char TTGE:1; - } BIT; - } TIER; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char :2; - unsigned char TCFV:1; - unsigned char TCFU:1; - unsigned char :1; - unsigned char TCFD:1; - } BIT; - } TSR; - unsigned short TCNT; - unsigned short TGRA; - unsigned short TGRB; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC2:3; - unsigned char PCB:2; - unsigned char :3; - } BIT; - } TCR2; -}; - -struct st_mtu3 -{ - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - char wk0[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char :2; - } BIT; - } TMDR1; - char wk1[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIORH; - union - { - unsigned char BYTE; - struct - { - unsigned char IOC:4; - unsigned char IOD:4; - } BIT; - } TIORL; - char wk2[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char :2; - unsigned char TTGE:1; - } BIT; - } TIER; - char wk3[7]; - unsigned short TCNT; - char wk4[6]; - unsigned short TGRA; - unsigned short TGRB; - char wk5[8]; - unsigned short TGRC; - unsigned short TGRD; - char wk6[4]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char TGFC:1; - unsigned char TGFD:1; - unsigned char TCFV:1; - unsigned char :2; - unsigned char TCFD:1; - } BIT; - } TSR; - char wk7[11]; - union - { - unsigned char BYTE; - struct - { - unsigned char TTSA:1; - unsigned char TTSB:1; - unsigned char :6; - } BIT; - } TBTM; - char wk8[19]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC2:3; - unsigned char :5; - } BIT; - } TCR2; - char wk9[37]; - unsigned short TGRE; - char wk10[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR3; -}; - -struct st_mtu4 -{ - char wk0[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - char wk1[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char :2; - } BIT; - } TMDR1; - char wk2[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIORH; - union - { - unsigned char BYTE; - struct - { - unsigned char IOC:4; - unsigned char IOD:4; - } BIT; - } TIORL; - char wk3[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char :1; - unsigned char TTGE2:1; - unsigned char TTGE:1; - } BIT; - } TIER; - char wk4[8]; - unsigned short TCNT; - char wk5[8]; - unsigned short TGRA; - unsigned short TGRB; - char wk6[8]; - unsigned short TGRC; - unsigned short TGRD; - char wk7[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char TGFC:1; - unsigned char TGFD:1; - unsigned char TCFV:1; - unsigned char :2; - unsigned char TCFD:1; - } BIT; - } TSR; - char wk8[11]; - union - { - unsigned char BYTE; - struct - { - unsigned char TTSA:1; - unsigned char TTSB:1; - unsigned char :6; - } BIT; - } TBTM; - char wk9[6]; - union - { - unsigned short WORD; - struct - { - unsigned short ITB4VE:1; - unsigned short ITB3AE:1; - unsigned short ITA4VE:1; - unsigned short ITA3AE:1; - unsigned short DT4BE:1; - unsigned short UT4BE:1; - unsigned short DT4AE:1; - unsigned short UT4AE:1; - unsigned short :6; - unsigned short BF:2; - } BIT; - } TADCR; - char wk10[2]; - unsigned short TADCORA; - unsigned short TADCORB; - unsigned short TADCOBRA; - unsigned short TADCOBRB; - char wk11[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC2:3; - unsigned char :5; - } BIT; - } TCR2; - char wk12[38]; - unsigned short TGRE; - unsigned short TGRF; - char wk13[28]; - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR4; -}; - -struct st_mtu5 -{ - char wk0[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char NFUEN:1; - unsigned char NFVEN:1; - unsigned char NFWEN:1; - unsigned char :1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR5; - char wk1[490]; - unsigned short TCNTU; - unsigned short TGRU; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:2; - unsigned char :6; - } BIT; - } TCRU; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC2:3; - unsigned char CKEG:2; - unsigned char :3; - } BIT; - } TCR2U; - union - { - unsigned char BYTE; - struct - { - unsigned char IOC:5; - unsigned char :3; - } BIT; - } TIORU; - char wk2[9]; - unsigned short TCNTV; - unsigned short TGRV; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:2; - unsigned char :6; - } BIT; - } TCRV; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC2:3; - unsigned char CKEG:2; - unsigned char :3; - } BIT; - } TCR2V; - union - { - unsigned char BYTE; - struct - { - unsigned char IOC:5; - unsigned char :3; - } BIT; - } TIORV; - char wk3[9]; - unsigned short TCNTW; - unsigned short TGRW; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:2; - unsigned char :6; - } BIT; - } TCRW; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC2:3; - unsigned char CKEG:2; - unsigned char :3; - } BIT; - } TCR2W; - union - { - unsigned char BYTE; - struct - { - unsigned char IOC:5; - unsigned char :3; - } BIT; - } TIORW; - char wk4[11]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIE5W:1; - unsigned char TGIE5V:1; - unsigned char TGIE5U:1; - unsigned char :5; - } BIT; - } TIER; - char wk5[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char CSTW5:1; - unsigned char CSTV5:1; - unsigned char CSTU5:1; - unsigned char :5; - } BIT; - } TSTR; - char wk6[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char CMPCLR5W:1; - unsigned char CMPCLR5V:1; - unsigned char CMPCLR5U:1; - unsigned char :5; - } BIT; - } TCNTCMPCLR; -}; - -struct st_mtu6 -{ - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - char wk0[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char :2; - } BIT; - } TMDR1; - char wk1[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIORH; - union - { - unsigned char BYTE; - struct - { - unsigned char IOC:4; - unsigned char IOD:4; - } BIT; - } TIORL; - char wk2[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char :2; - unsigned char TTGE:1; - } BIT; - } TIER; - char wk3[7]; - unsigned short TCNT; - char wk4[6]; - unsigned short TGRA; - unsigned short TGRB; - char wk5[8]; - unsigned short TGRC; - unsigned short TGRD; - char wk6[4]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char TGFC:1; - unsigned char TGFD:1; - unsigned char TCFV:1; - unsigned char :2; - unsigned char TCFD:1; - } BIT; - } TSR; - char wk7[11]; - union - { - unsigned char BYTE; - struct - { - unsigned char TTSA:1; - unsigned char TTSB:1; - unsigned char :6; - } BIT; - } TBTM; - char wk8[19]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC2:3; - unsigned char :5; - } BIT; - } TCR2; - char wk9[3]; - union - { - unsigned char BYTE; - struct - { - unsigned char CE2B:1; - unsigned char CE2A:1; - unsigned char CE1B:1; - unsigned char CE1A:1; - unsigned char CE0D:1; - unsigned char CE0C:1; - unsigned char CE0B:1; - unsigned char CE0A:1; - } BIT; - } TSYCR; - char wk10[33]; - unsigned short TGRE; - char wk11[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR6; -}; - -struct st_mtu7 -{ - char wk0[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - char wk1[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char :2; - } BIT; - } TMDR1; - char wk2[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIORH; - union - { - unsigned char BYTE; - struct - { - unsigned char IOC:4; - unsigned char IOD:4; - } BIT; - } TIORL; - char wk3[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char :1; - unsigned char TTGE2:1; - unsigned char TTGE:1; - } BIT; - } TIER; - char wk4[8]; - unsigned short TCNT; - char wk5[8]; - unsigned short TGRA; - unsigned short TGRB; - char wk6[8]; - unsigned short TGRC; - unsigned short TGRD; - char wk7[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char TGFC:1; - unsigned char TGFD:1; - unsigned char TCFV:1; - unsigned char :2; - unsigned char TCFD:1; - } BIT; - } TSR; - char wk8[11]; - union - { - unsigned char BYTE; - struct - { - unsigned char TTSA:1; - unsigned char TTSB:1; - unsigned char :6; - } BIT; - } TBTM; - char wk9[6]; - union - { - unsigned short WORD; - struct - { - unsigned short ITB7VE:1; - unsigned short ITB6AE:1; - unsigned short ITA7VE:1; - unsigned short ITA6AE:1; - unsigned short DT7BE:1; - unsigned short UT7BE:1; - unsigned short DT7AE:1; - unsigned short UT7AE:1; - unsigned short :6; - unsigned short BF:2; - } BIT; - } TADCR; - char wk10[2]; - unsigned short TADCORA; - unsigned short TADCORB; - unsigned short TADCOBRA; - unsigned short TADCOBRB; - char wk11[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC2:3; - unsigned char :5; - } BIT; - } TCR2; - char wk12[38]; - unsigned short TGRE; - unsigned short TGRF; - char wk13[28]; - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR7; -}; - -struct st_mtu8 -{ - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR8; - char wk0[871]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char :2; - } BIT; - } TMDR1; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIORH; - union - { - unsigned char BYTE; - struct - { - unsigned char IOC:4; - unsigned char IOD:4; - } BIT; - } TIORL; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char :3; - } BIT; - } TIER; - char wk1[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC2:3; - unsigned char :5; - } BIT; - } TCR2; - char wk2[1]; - unsigned long TCNT; - unsigned long TGRA; - unsigned long TGRB; - unsigned long TGRC; - unsigned long TGRD; -}; - -struct st_poe -{ - union - { - unsigned short WORD; - struct - { - unsigned short POE0M:2; - unsigned short :6; - unsigned short PIE1:1; - unsigned short :3; - unsigned short POE0F:1; - unsigned short :3; - } BIT; - } ICSR1; - union - { - unsigned short WORD; - struct - { - unsigned short :8; - unsigned short OIE1:1; - unsigned short OCE1:1; - unsigned short :5; - unsigned short OSF1:1; - } BIT; - } OCSR1; - union - { - unsigned short WORD; - struct - { - unsigned short POE4M:2; - unsigned short :6; - unsigned short PIE2:1; - unsigned short :3; - unsigned short POE4F:1; - unsigned short :3; - } BIT; - } ICSR2; - union - { - unsigned short WORD; - struct - { - unsigned short :8; - unsigned short OIE2:1; - unsigned short OCE2:1; - unsigned short :5; - unsigned short OSF2:1; - } BIT; - } OCSR2; - union - { - unsigned short WORD; - struct - { - unsigned short POE8M:2; - unsigned short :6; - unsigned short PIE3:1; - unsigned short POE8E:1; - unsigned short :2; - unsigned short POE8F:1; - unsigned short :3; - } BIT; - } ICSR3; - union - { - unsigned char BYTE; - struct - { - unsigned char MTUCH34HIZ:1; - unsigned char MTUCH67HIZ:1; - unsigned char MTUCH0HIZ:1; - unsigned char :1; - unsigned char GPT3HIZ:1; - unsigned char :3; - } BIT; - } SPOER; - union - { - unsigned char BYTE; - struct - { - unsigned char MTU0AZE:1; - unsigned char MTU0BZE:1; - unsigned char MTU0CZE:1; - unsigned char MTU0DZE:1; - unsigned char :4; - } BIT; - } POECR1; - union - { - unsigned short WORD; - struct - { - unsigned short MTU7BDZE:1; - unsigned short MTU7ACZE:1; - unsigned short MTU6BDZE:1; - unsigned short :5; - unsigned short MTU4BDZE:1; - unsigned short MTU4ACZE:1; - unsigned short MTU3BDZE:1; - unsigned short :5; - } BIT; - } POECR2; - union - { - unsigned short WORD; - struct - { - unsigned short :9; - unsigned short GPT3ABZE:1; - unsigned short :6; - } BIT; - } POECR3; - union - { - unsigned short WORD; - struct - { - unsigned short :2; - unsigned short IC2ADDMT34ZE:1; - unsigned short IC3ADDMT34ZE:1; - unsigned short IC4ADDMT34ZE:1; - unsigned short IC5ADDMT34ZE:1; - unsigned short :3; - unsigned short IC1ADDMT67ZE:1; - unsigned short :1; - unsigned short IC3ADDMT67ZE:1; - unsigned short IC4ADDMT67ZE:1; - unsigned short IC5ADDMT67ZE:1; - unsigned short :2; - } BIT; - } POECR4; - union - { - unsigned short WORD; - struct - { - unsigned short :1; - unsigned short IC1ADDMT0ZE:1; - unsigned short IC2ADDMT0ZE:1; - unsigned short :1; - unsigned short IC4ADDMT0ZE:1; - unsigned short IC5ADDMT0ZE:1; - unsigned short :10; - } BIT; - } POECR5; - union - { - unsigned short WORD; - struct - { - unsigned short :9; - unsigned short IC1ADDGPT3ZE:1; - unsigned short IC2ADDGPT3ZE:1; - unsigned short IC3ADDGPT3ZE:1; - unsigned short IC4ADDGPT3ZE:1; - unsigned short :3; - } BIT; - } POECR6; - union - { - unsigned short WORD; - struct - { - unsigned short POE10M:2; - unsigned short :6; - unsigned short PIE4:1; - unsigned short POE10E:1; - unsigned short :2; - unsigned short POE10F:1; - unsigned short :3; - } BIT; - } ICSR4; - union - { - unsigned short WORD; - struct - { - unsigned short POE10M:2; - unsigned short :6; - unsigned short PIE5:1; - unsigned short POE10E:1; - unsigned short :2; - unsigned short POE10F:1; - unsigned short :3; - } BIT; - } ICSR5; - union - { - unsigned short WORD; - struct - { - unsigned short OLSG0A:1; - unsigned short OLSG0B:1; - unsigned short OLSG1A:1; - unsigned short OLSG1B:1; - unsigned short OLSG2A:1; - unsigned short OLSG2B:1; - unsigned short :1; - unsigned short OLSEN:1; - unsigned short :8; - } BIT; - } ALR1; - union - { - unsigned short WORD; - struct - { - unsigned short :9; - unsigned short OSTSTE:1; - unsigned short :2; - unsigned short OSTSTF:1; - unsigned short :3; - } BIT; - } ICSR6; - char wk0[5]; - union - { - unsigned char BYTE; - struct - { - unsigned char G3ASEL:4; - unsigned char G3BSEL:4; - } BIT; - } G3SELR; - union - { - unsigned char BYTE; - struct - { - unsigned char M0ASEL:4; - unsigned char M0BSEL:4; - } BIT; - } M0SELR1; - union - { - unsigned char BYTE; - struct - { - unsigned char M0CSEL:4; - unsigned char M0DSEL:4; - } BIT; - } M0SELR2; - union - { - unsigned char BYTE; - struct - { - unsigned char M3BSEL:4; - unsigned char M3DSEL:4; - } BIT; - } M3SELR; - union - { - unsigned char BYTE; - struct - { - unsigned char M4ASEL:4; - unsigned char M4CSEL:4; - } BIT; - } M4SELR1; - union - { - unsigned char BYTE; - struct - { - unsigned char M4BSEL:4; - unsigned char M4DSEL:4; - } BIT; - } M4SELR2; -}; - -struct st_port0 -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[62]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[127]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_port1 -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[61]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[128]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; - char wk4[62]; - union - { - unsigned short WORD; - struct - { - unsigned char H; - unsigned char L; - } BYTE; - struct - { - unsigned char B0:1; - unsigned char :8; - unsigned char :7; - } BIT; - } DSCR; -}; - -struct st_port2 -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[60]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[129]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_port3 -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[59]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[130]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_port4 -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[58]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[131]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_port5 -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[57]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[132]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_port6 -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[56]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[133]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_port7 -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[55]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[134]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_port8 -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[54]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[135]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_port9 -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[53]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[136]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_porta -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[52]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[137]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portb -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[51]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[138]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portc -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[50]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; -}; - -struct st_portd -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[49]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[140]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_porte -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[48]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[141]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portf -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[47]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[142]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portg -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[46]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[143]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_porth -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[45]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[144]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portj -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[44]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[145]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portk -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[43]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[146]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portl -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[42]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[147]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portm -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[41]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[148]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portn -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[40]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[149]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portp -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[39]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[150]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portr -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[38]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[151]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_ports -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[37]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[152]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portt -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[36]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[153]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_portu -{ - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PDR; - char wk0[35]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PODR; - char wk1[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PIDR; - char wk2[31]; - union - { - unsigned char BYTE; - struct - { - unsigned char B0:1; - unsigned char B1:1; - unsigned char B2:1; - unsigned char B3:1; - unsigned char B4:1; - unsigned char B5:1; - unsigned char B6:1; - unsigned char B7:1; - } BIT; - } PMR; - char wk3[154]; - union - { - unsigned short WORD; - struct - { - unsigned short B0:2; - unsigned short B1:2; - unsigned short B2:2; - unsigned short B3:2; - unsigned short B4:2; - unsigned short B5:2; - unsigned short B6:2; - unsigned short B7:2; - } BIT; - } PCR; -}; - -struct st_ppg0 -{ - union - { - unsigned char BYTE; - struct - { - unsigned char G0CMS:2; - unsigned char G1CMS:2; - unsigned char G2CMS:2; - unsigned char G3CMS:2; - } BIT; - } PCR; - union - { - unsigned char BYTE; - struct - { - unsigned char G0NOV:1; - unsigned char G1NOV:1; - unsigned char G2NOV:1; - unsigned char G3NOV:1; - unsigned char G0INV:1; - unsigned char G1INV:1; - unsigned char G2INV:1; - unsigned char G3INV:1; - } BIT; - } PMR; - union - { - unsigned char BYTE; - struct - { - unsigned char NDER8:1; - unsigned char NDER9:1; - unsigned char NDER10:1; - unsigned char NDER11:1; - unsigned char NDER12:1; - unsigned char NDER13:1; - unsigned char NDER14:1; - unsigned char NDER15:1; - } BIT; - } NDERH; - union - { - unsigned char BYTE; - struct - { - unsigned char NDER0:1; - unsigned char NDER1:1; - unsigned char NDER2:1; - unsigned char NDER3:1; - unsigned char NDER4:1; - unsigned char NDER5:1; - unsigned char NDER6:1; - unsigned char NDER7:1; - } BIT; - } NDERL; - union - { - unsigned char BYTE; - struct - { - unsigned char POD8:1; - unsigned char POD9:1; - unsigned char POD10:1; - unsigned char POD11:1; - unsigned char POD12:1; - unsigned char POD13:1; - unsigned char POD14:1; - unsigned char POD15:1; - } BIT; - } PODRH; - union - { - unsigned char BYTE; - struct - { - unsigned char POD0:1; - unsigned char POD1:1; - unsigned char POD2:1; - unsigned char POD3:1; - unsigned char POD4:1; - unsigned char POD5:1; - unsigned char POD6:1; - unsigned char POD7:1; - } BIT; - } PODRL; - union - { - unsigned char BYTE; - struct - { - unsigned char NDR8:1; - unsigned char NDR9:1; - unsigned char NDR10:1; - unsigned char NDR11:1; - unsigned char NDR12:1; - unsigned char NDR13:1; - unsigned char NDR14:1; - unsigned char NDR15:1; - } BIT; - } NDRH; - union - { - unsigned char BYTE; - struct - { - unsigned char NDR0:1; - unsigned char NDR1:1; - unsigned char NDR2:1; - unsigned char NDR3:1; - unsigned char NDR4:1; - unsigned char NDR5:1; - unsigned char NDR6:1; - unsigned char NDR7:1; - } BIT; - } NDRL; - union - { - unsigned char BYTE; - struct - { - unsigned char NDR8:1; - unsigned char NDR9:1; - unsigned char NDR10:1; - unsigned char NDR11:1; - unsigned char NDR12:1; - unsigned char NDR13:1; - unsigned char NDR14:1; - unsigned char NDR15:1; - } BIT; - } NDRH2; - union - { - unsigned char BYTE; - struct - { - unsigned char NDR0:1; - unsigned char NDR1:1; - unsigned char NDR2:1; - unsigned char NDR3:1; - unsigned char NDR4:1; - unsigned char NDR5:1; - unsigned char NDR6:1; - unsigned char NDR7:1; - } BIT; - } NDRL2; -}; - -struct st_ppg1 -{ - union - { - unsigned char BYTE; - struct - { - unsigned char G0CMS:2; - unsigned char G1CMS:2; - unsigned char G2CMS:2; - unsigned char G3CMS:2; - } BIT; - } PCR; - union - { - unsigned char BYTE; - struct - { - unsigned char G0NOV:1; - unsigned char G1NOV:1; - unsigned char G2NOV:1; - unsigned char G3NOV:1; - unsigned char G0INV:1; - unsigned char G1INV:1; - unsigned char G2INV:1; - unsigned char G3INV:1; - } BIT; - } PMR; - union - { - unsigned char BYTE; - struct - { - unsigned char NDER8:1; - unsigned char NDER9:1; - unsigned char NDER10:1; - unsigned char NDER11:1; - unsigned char NDER12:1; - unsigned char NDER13:1; - unsigned char NDER14:1; - unsigned char NDER15:1; - } BIT; - } NDERH; - union - { - unsigned char BYTE; - struct - { - unsigned char NDER0:1; - unsigned char NDER1:1; - unsigned char NDER2:1; - unsigned char NDER3:1; - unsigned char NDER4:1; - unsigned char NDER5:1; - unsigned char NDER6:1; - unsigned char NDER7:1; - } BIT; - } NDERL; - union - { - unsigned char BYTE; - struct - { - unsigned char POD8:1; - unsigned char POD9:1; - unsigned char POD10:1; - unsigned char POD11:1; - unsigned char POD12:1; - unsigned char POD13:1; - unsigned char POD14:1; - unsigned char POD15:1; - } BIT; - } PODRH; - union - { - unsigned char BYTE; - struct - { - unsigned char POD0:1; - unsigned char POD1:1; - unsigned char POD2:1; - unsigned char POD3:1; - unsigned char POD4:1; - unsigned char POD5:1; - unsigned char POD6:1; - unsigned char POD7:1; - } BIT; - } PODRL; - union - { - unsigned char BYTE; - struct - { - unsigned char NDR8:1; - unsigned char NDR9:1; - unsigned char NDR10:1; - unsigned char NDR11:1; - unsigned char NDR12:1; - unsigned char NDR13:1; - unsigned char NDR14:1; - unsigned char NDR15:1; - } BIT; - } NDRH; - union - { - unsigned char BYTE; - struct - { - unsigned char NDR0:1; - unsigned char NDR1:1; - unsigned char NDR2:1; - unsigned char NDR3:1; - unsigned char NDR4:1; - unsigned char NDR5:1; - unsigned char NDR6:1; - unsigned char NDR7:1; - } BIT; - } NDRL; - union - { - unsigned char BYTE; - struct - { - unsigned char NDR8:1; - unsigned char NDR9:1; - unsigned char NDR10:1; - unsigned char NDR11:1; - unsigned char NDR12:1; - unsigned char NDR13:1; - unsigned char NDR14:1; - unsigned char NDR15:1; - } BIT; - } NDRH2; - union - { - unsigned char BYTE; - struct - { - unsigned char NDR0:1; - unsigned char NDR1:1; - unsigned char NDR2:1; - unsigned char NDR3:1; - unsigned char NDR4:1; - unsigned char NDR5:1; - unsigned char NDR6:1; - unsigned char NDR7:1; - } BIT; - } NDRL2; - union - { - unsigned char BYTE; - struct - { - unsigned char PTRSL:1; - unsigned char :7; - } BIT; - } PTRSLR; -}; - -struct st_riic -{ - union - { - unsigned char BYTE; - struct - { - unsigned char SDAI:1; - unsigned char SCLI:1; - unsigned char SDAO:1; - unsigned char SCLO:1; - unsigned char SOWP:1; - unsigned char CLO:1; - unsigned char IICRST:1; - unsigned char ICE:1; - } BIT; - } ICCR1; - union - { - unsigned char BYTE; - struct - { - unsigned char :1; - unsigned char ST:1; - unsigned char RS:1; - unsigned char SP:1; - unsigned char :1; - unsigned char TRS:1; - unsigned char MST:1; - unsigned char BBSY:1; - } BIT; - } ICCR2; - union - { - unsigned char BYTE; - struct - { - unsigned char BC:3; - unsigned char BCWP:1; - unsigned char CKS:3; - unsigned char MTWP:1; - } BIT; - } ICMR1; - union - { - unsigned char BYTE; - struct - { - unsigned char TMOS:1; - unsigned char TMOL:1; - unsigned char TMOH:1; - unsigned char :1; - unsigned char SDDL:3; - unsigned char DLCS:1; - } BIT; - } ICMR2; - union - { - unsigned char BYTE; - struct - { - unsigned char NF:2; - unsigned char ACKBR:1; - unsigned char ACKBT:1; - unsigned char ACKWP:1; - unsigned char RDRFS:1; - unsigned char WAIT:1; - unsigned char :1; - } BIT; - } ICMR3; - union - { - unsigned char BYTE; - struct - { - unsigned char TMOE:1; - unsigned char MALE:1; - unsigned char NALE:1; - unsigned char SALE:1; - unsigned char NACKE:1; - unsigned char NFE:1; - unsigned char SCLE:1; - unsigned char :1; - } BIT; - } ICFER; - union - { - unsigned char BYTE; - struct - { - unsigned char SAR0E:1; - unsigned char SAR1E:1; - unsigned char SAR2E:1; - unsigned char GCAE:1; - unsigned char :1; - unsigned char DIDE:1; - unsigned char :2; - } BIT; - } ICSER; - union - { - unsigned char BYTE; - struct - { - unsigned char TMOIE:1; - unsigned char ALIE:1; - unsigned char STIE:1; - unsigned char SPIE:1; - unsigned char NAKIE:1; - unsigned char RIE:1; - unsigned char TEIE:1; - unsigned char TIE:1; - } BIT; - } ICIER; - union - { - unsigned char BYTE; - struct - { - unsigned char AAS0:1; - unsigned char AAS1:1; - unsigned char AAS2:1; - unsigned char GCA:1; - unsigned char :1; - unsigned char DID:1; - unsigned char :2; - } BIT; - } ICSR1; - union - { - unsigned char BYTE; - struct - { - unsigned char TMOF:1; - unsigned char AL:1; - unsigned char START:1; - unsigned char STOP:1; - unsigned char NACKF:1; - unsigned char RDRF:1; - unsigned char TEND:1; - unsigned char TDRE:1; - } BIT; - } ICSR2; - union - { - unsigned char BYTE; - struct - { - unsigned char SVA0:1; - unsigned char SVA:7; - } BIT; - } ICSARL0; - union - { - unsigned char BYTE; - struct - { - unsigned char FS:1; - unsigned char SVA:2; - unsigned char :5; - } BIT; - } ICSARU0; - union - { - unsigned char BYTE; - struct - { - unsigned char SVA0:1; - unsigned char SVA:7; - } BIT; - } ICSARL1; - union - { - unsigned char BYTE; - struct - { - unsigned char FS:1; - unsigned char SVA:2; - unsigned char :5; - } BIT; - } ICSARU1; - union - { - unsigned char BYTE; - struct - { - unsigned char SVA0:1; - unsigned char SVA:7; - } BIT; - } ICSARL2; - union - { - unsigned char BYTE; - struct - { - unsigned char FS:1; - unsigned char SVA:2; - unsigned char :5; - } BIT; - } ICSARU2; - union - { - unsigned char BYTE; - struct - { - unsigned char BRL:5; - unsigned char :3; - } BIT; - } ICBRL; - union - { - unsigned char BYTE; - struct - { - unsigned char BRH:5; - unsigned char :3; - } BIT; - } ICBRH; - unsigned char ICDRT; - unsigned char ICDRR; -}; - -struct st_rscan -{ - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long BRP:10; - unsigned long :6; - unsigned long TSEG1:4; - unsigned long TSEG2:3; - unsigned long :1; - unsigned long SJW:2; - unsigned long :6; - } BIT; - } RSCAN0C0CFG; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CHMDC:2; - unsigned char CSLPR:1; - unsigned char RTBO:1; - unsigned char :4; - unsigned char BEIE:1; - unsigned char EWIE:1; - unsigned char EPIE:1; - unsigned char BOEIE:1; - unsigned char BORIE:1; - unsigned char OLIE:1; - unsigned char BLIE:1; - unsigned char ALIE:1; - unsigned char TAIE:1; - unsigned char :4; - unsigned char BOM:2; - unsigned char ERRD:1; - unsigned char CTME:1; - unsigned char CTMS:2; - unsigned char :5; - } BIT; - } RSCAN0C0CTR; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CRSTSTS:1; - unsigned char CHLTSTS:1; - unsigned char CSLPSTS:1; - unsigned char EPSTS:1; - unsigned char BOSTS:1; - unsigned char TRMSTS:1; - unsigned char RECSTS:1; - unsigned char COMSTS:1; - unsigned char :8; - unsigned char REC:8; - unsigned char TEC:8; - } BIT; - } RSCAN0C0STS; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long BEF:1; - unsigned long EWF:1; - unsigned long EPF:1; - unsigned long BOEF:1; - unsigned long BORF:1; - unsigned long OVLF:1; - unsigned long BLF:1; - unsigned long ALF:1; - unsigned long SERR:1; - unsigned long FERR:1; - unsigned long AERR:1; - unsigned long CERR:1; - unsigned long B1ERR:1; - unsigned long B0ERR:1; - unsigned long ADERR:1; - unsigned long :1; - unsigned long CRCREG:15; - unsigned long :1; - } BIT; - } RSCAN0C0ERFL; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long BRP:10; - unsigned long :6; - unsigned long TSEG1:4; - unsigned long TSEG2:3; - unsigned long :1; - unsigned long SJW:2; - unsigned long :6; - } BIT; - } RSCAN0C1CFG; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CHMDC:2; - unsigned char CSLPR:1; - unsigned char RTBO:1; - unsigned char :4; - unsigned char BEIE:1; - unsigned char EWIE:1; - unsigned char EPIE:1; - unsigned char BOEIE:1; - unsigned char BORIE:1; - unsigned char OLIE:1; - unsigned char BLIE:1; - unsigned char ALIE:1; - unsigned char TAIE:1; - unsigned char :4; - unsigned char BOM:2; - unsigned char ERRD:1; - unsigned char CTME:1; - unsigned char CTMS:2; - unsigned char :5; - } BIT; - } RSCAN0C1CTR; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CRSTSTS:1; - unsigned char CHLTSTS:1; - unsigned char CSLPSTS:1; - unsigned char EPSTS:1; - unsigned char BOSTS:1; - unsigned char TRMSTS:1; - unsigned char RECSTS:1; - unsigned char COMSTS:1; - unsigned char :8; - unsigned char REC:8; - unsigned char TEC:8; - } BIT; - } RSCAN0C1STS; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long BEF:1; - unsigned long EWF:1; - unsigned long EPF:1; - unsigned long BOEF:1; - unsigned long BORF:1; - unsigned long OVLF:1; - unsigned long BLF:1; - unsigned long ALF:1; - unsigned long SERR:1; - unsigned long FERR:1; - unsigned long AERR:1; - unsigned long CERR:1; - unsigned long B1ERR:1; - unsigned long B0ERR:1; - unsigned long ADERR:1; - unsigned long :1; - unsigned long CRCREG:15; - unsigned long :1; - } BIT; - } RSCAN0C1ERFL; - char wk0[100]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TPRI:1; - unsigned long DCE:1; - unsigned long DRE:1; - unsigned long MME:1; - unsigned long DCS:1; - unsigned long :3; - unsigned long TSP:4; - unsigned long TSSS:1; - unsigned long TSBTCS:3; - unsigned long ITRCP:16; - } BIT; - } RSCAN0GCFG; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char GMDC:2; - unsigned char GSLPR:1; - unsigned char :5; - unsigned char DEIE:1; - unsigned char MEIE:1; - unsigned char THLEIE:1; - unsigned char :5; - unsigned char TSRST:1; - unsigned char :7; - unsigned char :8; - } BIT; - } RSCAN0GCTR; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char GRSTSTS:1; - unsigned char GHLTSTS:1; - unsigned char GSLPSTS:1; - unsigned char GRAMINIT:1; - unsigned char :4; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0GSTS; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char DEF:1; - unsigned char MES:1; - unsigned char THLES:1; - unsigned char :5; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0GERFL; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned long TS:16; - unsigned long :16; - } BIT; - } RSCAN0GTSC; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char AFLPN:5; - unsigned char :3; - unsigned char AFLDAE:1; - unsigned char :7; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0GAFLECTR; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char RNC1:8; - unsigned char RNC0:8; - } BIT; - } RSCAN0GAFLCFG0; - char wk1[4]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char NRXMB:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RMNB; - union - { - unsigned long LONG; - struct - { - unsigned short RMNSq_l; - unsigned short RMNSq_h; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - } RSCAN0RMND0; - char wk2[12]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFE:1; - unsigned char RFIE:1; - unsigned char :6; - unsigned char RFDC:3; - unsigned char :1; - unsigned char RFIM:1; - unsigned char RFIGCV:3; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFCC0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFE:1; - unsigned char RFIE:1; - unsigned char :6; - unsigned char RFDC:3; - unsigned char :1; - unsigned char RFIM:1; - unsigned char RFIGCV:3; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFCC1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFE:1; - unsigned char RFIE:1; - unsigned char :6; - unsigned char RFDC:3; - unsigned char :1; - unsigned char RFIM:1; - unsigned char RFIGCV:3; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFCC2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFE:1; - unsigned char RFIE:1; - unsigned char :6; - unsigned char RFDC:3; - unsigned char :1; - unsigned char RFIM:1; - unsigned char RFIGCV:3; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFCC3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFE:1; - unsigned char RFIE:1; - unsigned char :6; - unsigned char RFDC:3; - unsigned char :1; - unsigned char RFIM:1; - unsigned char RFIGCV:3; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFCC4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFE:1; - unsigned char RFIE:1; - unsigned char :6; - unsigned char RFDC:3; - unsigned char :1; - unsigned char RFIM:1; - unsigned char RFIGCV:3; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFCC5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFE:1; - unsigned char RFIE:1; - unsigned char :6; - unsigned char RFDC:3; - unsigned char :1; - unsigned char RFIM:1; - unsigned char RFIGCV:3; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFCC6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFE:1; - unsigned char RFIE:1; - unsigned char :6; - unsigned char RFDC:3; - unsigned char :1; - unsigned char RFIM:1; - unsigned char RFIGCV:3; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFCC7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFEMP:1; - unsigned char RFFLL:1; - unsigned char RFMLT:1; - unsigned char RFIF:1; - unsigned char :4; - unsigned char RFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFSTS0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFEMP:1; - unsigned char RFFLL:1; - unsigned char RFMLT:1; - unsigned char RFIF:1; - unsigned char :4; - unsigned char RFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFSTS1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFEMP:1; - unsigned char RFFLL:1; - unsigned char RFMLT:1; - unsigned char RFIF:1; - unsigned char :4; - unsigned char RFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFSTS2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFEMP:1; - unsigned char RFFLL:1; - unsigned char RFMLT:1; - unsigned char RFIF:1; - unsigned char :4; - unsigned char RFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFSTS3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFEMP:1; - unsigned char RFFLL:1; - unsigned char RFMLT:1; - unsigned char RFIF:1; - unsigned char :4; - unsigned char RFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFSTS4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFEMP:1; - unsigned char RFFLL:1; - unsigned char RFMLT:1; - unsigned char RFIF:1; - unsigned char :4; - unsigned char RFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFSTS5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFEMP:1; - unsigned char RFFLL:1; - unsigned char RFMLT:1; - unsigned char RFIF:1; - unsigned char :4; - unsigned char RFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFSTS6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFEMP:1; - unsigned char RFFLL:1; - unsigned char RFMLT:1; - unsigned char RFIF:1; - unsigned char :4; - unsigned char RFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFSTS7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFPCTR0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFPCTR1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFPCTR2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFPCTR3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFPCTR4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFPCTR5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFPCTR6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFPCTR7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFE:1; - unsigned char CFRXIE:1; - unsigned char CFTXIE:1; - unsigned char :5; - unsigned char CFDC:3; - unsigned char :1; - unsigned char CFIM:1; - unsigned char CFIGCV:3; - unsigned char CFM:2; - unsigned char CFITSS:1; - unsigned char CFITR:1; - unsigned char CFTML:4; - unsigned char CFITT:8; - } BIT; - } RSCAN0CFCC0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFE:1; - unsigned char CFRXIE:1; - unsigned char CFTXIE:1; - unsigned char :5; - unsigned char CFDC:3; - unsigned char :1; - unsigned char CFIM:1; - unsigned char CFIGCV:3; - unsigned char CFM:2; - unsigned char CFITSS:1; - unsigned char CFITR:1; - unsigned char CFTML:4; - unsigned char CFITT:8; - } BIT; - } RSCAN0CFCC1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFE:1; - unsigned char CFRXIE:1; - unsigned char CFTXIE:1; - unsigned char :5; - unsigned char CFDC:3; - unsigned char :1; - unsigned char CFIM:1; - unsigned char CFIGCV:3; - unsigned char CFM:2; - unsigned char CFITSS:1; - unsigned char CFITR:1; - unsigned char CFTML:4; - unsigned char CFITT:8; - } BIT; - } RSCAN0CFCC2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFE:1; - unsigned char CFRXIE:1; - unsigned char CFTXIE:1; - unsigned char :5; - unsigned char CFDC:3; - unsigned char :1; - unsigned char CFIM:1; - unsigned char CFIGCV:3; - unsigned char CFM:2; - unsigned char CFITSS:1; - unsigned char CFITR:1; - unsigned char CFTML:4; - unsigned char CFITT:8; - } BIT; - } RSCAN0CFCC3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFE:1; - unsigned char CFRXIE:1; - unsigned char CFTXIE:1; - unsigned char :5; - unsigned char CFDC:3; - unsigned char :1; - unsigned char CFIM:1; - unsigned char CFIGCV:3; - unsigned char CFM:2; - unsigned char CFITSS:1; - unsigned char CFITR:1; - unsigned char CFTML:4; - unsigned char CFITT:8; - } BIT; - } RSCAN0CFCC4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFE:1; - unsigned char CFRXIE:1; - unsigned char CFTXIE:1; - unsigned char :5; - unsigned char CFDC:3; - unsigned char :1; - unsigned char CFIM:1; - unsigned char CFIGCV:3; - unsigned char CFM:2; - unsigned char CFITSS:1; - unsigned char CFITR:1; - unsigned char CFTML:4; - unsigned char CFITT:8; - } BIT; - } RSCAN0CFCC5; - char wk3[72]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFEMP:1; - unsigned char CFFLL:1; - unsigned char CFMLT:1; - unsigned char CFRXIF:1; - unsigned char CFTXIF:1; - unsigned char :3; - unsigned char CFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFSTS0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFEMP:1; - unsigned char CFFLL:1; - unsigned char CFMLT:1; - unsigned char CFRXIF:1; - unsigned char CFTXIF:1; - unsigned char :3; - unsigned char CFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFSTS1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFEMP:1; - unsigned char CFFLL:1; - unsigned char CFMLT:1; - unsigned char CFRXIF:1; - unsigned char CFTXIF:1; - unsigned char :3; - unsigned char CFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFSTS2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFEMP:1; - unsigned char CFFLL:1; - unsigned char CFMLT:1; - unsigned char CFRXIF:1; - unsigned char CFTXIF:1; - unsigned char :3; - unsigned char CFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFSTS3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFEMP:1; - unsigned char CFFLL:1; - unsigned char CFMLT:1; - unsigned char CFRXIF:1; - unsigned char CFTXIF:1; - unsigned char :3; - unsigned char CFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFSTS4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFEMP:1; - unsigned char CFFLL:1; - unsigned char CFMLT:1; - unsigned char CFRXIF:1; - unsigned char CFTXIF:1; - unsigned char :3; - unsigned char CFMC:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFSTS5; - char wk4[72]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFPCTR0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFPCTR1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFPCTR2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFPCTR3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFPCTR4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CFPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFPCTR5; - char wk5[72]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RF0EMP:1; - unsigned char RF1EMP:1; - unsigned char RF2EMP:1; - unsigned char RF3EMP:1; - unsigned char RF4EMP:1; - unsigned char RF5EMP:1; - unsigned char RF6EMP:1; - unsigned char RF7EMP:1; - unsigned char CF0EMP:1; - unsigned char CF1EMP:1; - unsigned char CF2EMP:1; - unsigned char CF3EMP:1; - unsigned char CF4EMP:1; - unsigned char CF5EMP:1; - unsigned char :2; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0FESTS; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RF0FLL:1; - unsigned char RF1FLL:1; - unsigned char RF2FLL:1; - unsigned char RF3FLL:1; - unsigned char RF4FLL:1; - unsigned char RF5FLL:1; - unsigned char RF6FLL:1; - unsigned char RF7FLL:1; - unsigned char CF0FLL:1; - unsigned char CF1FLL:1; - unsigned char CF2FLL:1; - unsigned char CF3FLL:1; - unsigned char CF4FLL:1; - unsigned char CF5FLL:1; - unsigned char :2; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0FFSTS; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RF0MLT:1; - unsigned char RF1MLT:1; - unsigned char RF2MLT:1; - unsigned char RF3MLT:1; - unsigned char RF4MLT:1; - unsigned char RF5MLT:1; - unsigned char RF6MLT:1; - unsigned char RF7MLT:1; - unsigned char CF0MLT:1; - unsigned char CF1MLT:1; - unsigned char CF2MLT:1; - unsigned char CF3MLT:1; - unsigned char CF4MLT:1; - unsigned char CF5MLT:1; - unsigned char :2; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0FMSTS; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char RF0IF:1; - unsigned char RF1IF:1; - unsigned char RF2IF:1; - unsigned char RF3IF:1; - unsigned char RF4IF:1; - unsigned char RF5IF:1; - unsigned char RF6IF:1; - unsigned char RF7IF:1; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0RFISTS; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CF0RXIF:1; - unsigned char CF1RXIF:1; - unsigned char CF2RXIF:1; - unsigned char CF3RXIF:1; - unsigned char CF4RXIF:1; - unsigned char CF5RXIF:1; - unsigned char :2; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFRISTS; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char CF0TXIF:1; - unsigned char CF1TXIF:1; - unsigned char CF2TXIF:1; - unsigned char CF3TXIF:1; - unsigned char CF4TXIF:1; - unsigned char CF5TXIF:1; - unsigned char :2; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0CFTISTS; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC0; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC1; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC2; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC3; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC4; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC5; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC6; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC7; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC8; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC9; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC10; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC11; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC12; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC13; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC14; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC15; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC16; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC17; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC18; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC19; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC20; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC21; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC22; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC23; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC24; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC25; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC26; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC27; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC28; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC29; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC30; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTR:1; - unsigned char TMTAR:1; - unsigned char TMOM:1; - unsigned char :5; - } BIT; - } RSCAN0TMC31; - char wk6[96]; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS0; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS1; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS2; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS3; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS4; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS5; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS6; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS7; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS8; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS9; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS10; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS11; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS12; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS13; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS14; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS15; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS16; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS17; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS18; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS19; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS20; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS21; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS22; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS23; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS24; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS25; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS26; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS27; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS28; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS29; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS30; - union - { - unsigned char BYTE; - struct - { - unsigned char TMTSTS:1; - unsigned char TMTRF:2; - unsigned char TMTRM:1; - unsigned char TMTARM:1; - unsigned char :3; - } BIT; - } RSCAN0TMSTS31; - char wk7[96]; - union - { - unsigned long LONG; - struct - { - unsigned short TMTRSTSp_l; - unsigned short TMTRSTSp_h; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - } RSCAN0TMTRSTS0; - char wk8[12]; - union - { - unsigned long LONG; - struct - { - unsigned short TMTARSTSp_l; - unsigned short TMTARSTSp_h; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - } RSCAN0TMTARSTS0; - char wk9[12]; - union - { - unsigned long LONG; - struct - { - unsigned short TMTCSTSp_l; - unsigned short TMTCSTSp_h; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - } RSCAN0TMTCSTS0; - char wk10[12]; - union - { - unsigned long LONG; - struct - { - unsigned short TMTASTSp_l; - unsigned short TMTASTSp_h; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - } RSCAN0TMTASTS0; - char wk11[12]; - union - { - unsigned long LONG; - struct - { - unsigned short TMIEp_l; - unsigned short TMIEp_h; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - } RSCAN0TMIEC0; - char wk12[12]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char TXQE:1; - unsigned char :7; - unsigned char TXQDC:4; - unsigned char TXQIE:1; - unsigned char TXQIM:1; - unsigned char :2; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0TXQCC0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char TXQE:1; - unsigned char :7; - unsigned char TXQDC:4; - unsigned char TXQIE:1; - unsigned char TXQIM:1; - unsigned char :2; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0TXQCC1; - char wk13[24]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char TXQEMP:1; - unsigned char TXQFLL:1; - unsigned char TXQIF:1; - unsigned char :5; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0TXQSTS0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char TXQEMP:1; - unsigned char TXQFLL:1; - unsigned char TXQIF:1; - unsigned char :5; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0TXQSTS1; - char wk14[24]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char TXQPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0TXQPCTR0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char TXQPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0TXQPCTR1; - char wk15[24]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char THLE:1; - unsigned char :7; - unsigned char THLIE:1; - unsigned char THLIM:1; - unsigned char THLDTE:1; - unsigned char :5; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0THLCC0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char THLE:1; - unsigned char :7; - unsigned char THLIE:1; - unsigned char THLIM:1; - unsigned char THLDTE:1; - unsigned char :5; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0THLCC1; - char wk16[24]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char THLEMP:1; - unsigned char THLFLL:1; - unsigned char THLELT:1; - unsigned char THLIF:1; - unsigned char :4; - unsigned char THLMC:5; - unsigned char :3; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0THLSTS0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char THLEMP:1; - unsigned char THLFLL:1; - unsigned char THLELT:1; - unsigned char THLIF:1; - unsigned char :4; - unsigned char THLMC:5; - unsigned char :3; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0THLSTS1; - char wk17[24]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char THLPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0THLPCTR0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char THLPC:8; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0THLPCTR1; - char wk18[24]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char TSIF0:1; - unsigned char TAIF0:1; - unsigned char TQIF0:1; - unsigned char CFTIF0:1; - unsigned char THIF0:1; - unsigned char :3; - unsigned char TSIF1:1; - unsigned char TAIF1:1; - unsigned char TQIF1:1; - unsigned char CFTIF1:1; - unsigned char THIF1:1; - unsigned char :3; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0GTINTSTS0; - char wk19[4]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char C0ICBCE:1; - unsigned char C1ICBCE:1; - unsigned char :6; - unsigned char :8; - unsigned char RTMPS:7; - unsigned char :1; - unsigned char :8; - } BIT; - } RSCAN0GTSTCFG; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char ICBCTME:1; - unsigned char :1; - unsigned char RTME:1; - unsigned char :5; - unsigned char :8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0GTSTCTR; - char wk20[12]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - } RSCAN0GLOCKK; - char wk21[128]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP00; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP01; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP02; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP03; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP04; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP05; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP15; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP06; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP16; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP07; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP17; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID8; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM8; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP08; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP18; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID9; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM9; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP09; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP19; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP010; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP110; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP011; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP111; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP012; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP112; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP013; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP113; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP014; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP114; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLID:29; - unsigned long GAFLLB:1; - unsigned long GAFLRTR:1; - unsigned long GAFLIDE:1; - } BIT; - } RSCAN0GAFLID15; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLIDM:29; - unsigned long :1; - unsigned long GAFLRTRM:1; - unsigned long GAFLIDEM:1; - } BIT; - } RSCAN0GAFLM15; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long :8; - unsigned long GAFLRMDP:7; - unsigned long GAFLRMV:1; - unsigned long GAFLPTR:12; - unsigned long GAFLDLC:4; - } BIT; - } RSCAN0GAFLP015; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long GAFLFDPr:8; - unsigned long GAFLFDP:18; - unsigned long :6; - } BIT; - } RSCAN0GAFLP115; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF00; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF01; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF02; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF03; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF04; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF05; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF15; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF06; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF16; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF07; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF17; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID8; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR8; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF08; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF18; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID9; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR9; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF09; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF19; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF010; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF110; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF011; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF111; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF012; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF112; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF013; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF113; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF014; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF114; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID15; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR15; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF015; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF115; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID16; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR16; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF016; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF116; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID17; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR17; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF017; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF117; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID18; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR18; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF018; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF118; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID19; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR19; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF019; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF119; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID20; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR20; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF020; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF120; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID21; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR21; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF021; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF121; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID22; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR22; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF022; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF122; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID23; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR23; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF023; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF123; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID24; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR24; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF024; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF124; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID25; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR25; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF025; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF125; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID26; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR26; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF026; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF126; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID27; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR27; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF027; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF127; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID28; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR28; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF028; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF128; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID29; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR29; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF029; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF129; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID30; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR30; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF030; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF130; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMID:29; - unsigned long :1; - unsigned long RMRTR:1; - unsigned long RMIDE:1; - } BIT; - } RSCAN0RMID31; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RMTS:16; - unsigned long RMPTR:12; - unsigned long RMDLC:4; - } BIT; - } RSCAN0RMPTR31; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB0; - unsigned char RMDB1; - unsigned char RMDB2; - unsigned char RMDB3; - } BYTE; - } RSCAN0RMDF031; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RMDB4; - unsigned char RMDB5; - unsigned char RMDB6; - unsigned char RMDB7; - } BYTE; - } RSCAN0RMDF131; - char wk22[1536]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFID:29; - unsigned long :1; - unsigned long RFRTR:1; - unsigned long RFIDE:1; - } BIT; - } RSCAN0RFID0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFTS:16; - unsigned long RFPTR:12; - unsigned long RFDLC:4; - } BIT; - } RSCAN0RFPTR0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB0; - unsigned char RFDB1; - unsigned char RFDB2; - unsigned char RFDB3; - } BYTE; - } RSCAN0RFDF00; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB4; - unsigned char RFDB5; - unsigned char RFDB6; - unsigned char RFDB7; - } BYTE; - } RSCAN0RFDF10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFID:29; - unsigned long :1; - unsigned long RFRTR:1; - unsigned long RFIDE:1; - } BIT; - } RSCAN0RFID1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFTS:16; - unsigned long RFPTR:12; - unsigned long RFDLC:4; - } BIT; - } RSCAN0RFPTR1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB0; - unsigned char RFDB1; - unsigned char RFDB2; - unsigned char RFDB3; - } BYTE; - } RSCAN0RFDF01; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB4; - unsigned char RFDB5; - unsigned char RFDB6; - unsigned char RFDB7; - } BYTE; - } RSCAN0RFDF11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFID:29; - unsigned long :1; - unsigned long RFRTR:1; - unsigned long RFIDE:1; - } BIT; - } RSCAN0RFID2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFTS:16; - unsigned long RFPTR:12; - unsigned long RFDLC:4; - } BIT; - } RSCAN0RFPTR2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB0; - unsigned char RFDB1; - unsigned char RFDB2; - unsigned char RFDB3; - } BYTE; - } RSCAN0RFDF02; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB4; - unsigned char RFDB5; - unsigned char RFDB6; - unsigned char RFDB7; - } BYTE; - } RSCAN0RFDF12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFID:29; - unsigned long :1; - unsigned long RFRTR:1; - unsigned long RFIDE:1; - } BIT; - } RSCAN0RFID3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFTS:16; - unsigned long RFPTR:12; - unsigned long RFDLC:4; - } BIT; - } RSCAN0RFPTR3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB0; - unsigned char RFDB1; - unsigned char RFDB2; - unsigned char RFDB3; - } BYTE; - } RSCAN0RFDF03; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB4; - unsigned char RFDB5; - unsigned char RFDB6; - unsigned char RFDB7; - } BYTE; - } RSCAN0RFDF13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFID:29; - unsigned long :1; - unsigned long RFRTR:1; - unsigned long RFIDE:1; - } BIT; - } RSCAN0RFID4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFTS:16; - unsigned long RFPTR:12; - unsigned long RFDLC:4; - } BIT; - } RSCAN0RFPTR4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB0; - unsigned char RFDB1; - unsigned char RFDB2; - unsigned char RFDB3; - } BYTE; - } RSCAN0RFDF04; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB4; - unsigned char RFDB5; - unsigned char RFDB6; - unsigned char RFDB7; - } BYTE; - } RSCAN0RFDF14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFID:29; - unsigned long :1; - unsigned long RFRTR:1; - unsigned long RFIDE:1; - } BIT; - } RSCAN0RFID5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFTS:16; - unsigned long RFPTR:12; - unsigned long RFDLC:4; - } BIT; - } RSCAN0RFPTR5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB0; - unsigned char RFDB1; - unsigned char RFDB2; - unsigned char RFDB3; - } BYTE; - } RSCAN0RFDF05; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB4; - unsigned char RFDB5; - unsigned char RFDB6; - unsigned char RFDB7; - } BYTE; - } RSCAN0RFDF15; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFID:29; - unsigned long :1; - unsigned long RFRTR:1; - unsigned long RFIDE:1; - } BIT; - } RSCAN0RFID6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFTS:16; - unsigned long RFPTR:12; - unsigned long RFDLC:4; - } BIT; - } RSCAN0RFPTR6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB0; - unsigned char RFDB1; - unsigned char RFDB2; - unsigned char RFDB3; - } BYTE; - } RSCAN0RFDF06; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB4; - unsigned char RFDB5; - unsigned char RFDB6; - unsigned char RFDB7; - } BYTE; - } RSCAN0RFDF16; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFID:29; - unsigned long :1; - unsigned long RFRTR:1; - unsigned long RFIDE:1; - } BIT; - } RSCAN0RFID7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RFTS:16; - unsigned long RFPTR:12; - unsigned long RFDLC:4; - } BIT; - } RSCAN0RFPTR7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB0; - unsigned char RFDB1; - unsigned char RFDB2; - unsigned char RFDB3; - } BYTE; - } RSCAN0RFDF07; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char RFDB4; - unsigned char RFDB5; - unsigned char RFDB6; - unsigned char RFDB7; - } BYTE; - } RSCAN0RFDF17; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFID:29; - unsigned long THLEN:1; - unsigned long CFRTR:1; - unsigned long CFIDE:1; - } BIT; - } RSCAN0CFID0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFTS:16; - unsigned long CFPTR:12; - unsigned long CFDLC:4; - } BIT; - } RSCAN0CFPTR0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB0; - unsigned char CFDB1; - unsigned char CFDB2; - unsigned char CFDB3; - } BYTE; - } RSCAN0CFDF00; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB4; - unsigned char CFDB5; - unsigned char CFDB6; - unsigned char CFDB7; - } BYTE; - } RSCAN0CFDF10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFID:29; - unsigned long THLEN:1; - unsigned long CFRTR:1; - unsigned long CFIDE:1; - } BIT; - } RSCAN0CFID1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFTS:16; - unsigned long CFPTR:12; - unsigned long CFDLC:4; - } BIT; - } RSCAN0CFPTR1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB0; - unsigned char CFDB1; - unsigned char CFDB2; - unsigned char CFDB3; - } BYTE; - } RSCAN0CFDF01; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB4; - unsigned char CFDB5; - unsigned char CFDB6; - unsigned char CFDB7; - } BYTE; - } RSCAN0CFDF11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFID:29; - unsigned long THLEN:1; - unsigned long CFRTR:1; - unsigned long CFIDE:1; - } BIT; - } RSCAN0CFID2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFTS:16; - unsigned long CFPTR:12; - unsigned long CFDLC:4; - } BIT; - } RSCAN0CFPTR2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB0; - unsigned char CFDB1; - unsigned char CFDB2; - unsigned char CFDB3; - } BYTE; - } RSCAN0CFDF02; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB4; - unsigned char CFDB5; - unsigned char CFDB6; - unsigned char CFDB7; - } BYTE; - } RSCAN0CFDF12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFID:29; - unsigned long THLEN:1; - unsigned long CFRTR:1; - unsigned long CFIDE:1; - } BIT; - } RSCAN0CFID3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFTS:16; - unsigned long CFPTR:12; - unsigned long CFDLC:4; - } BIT; - } RSCAN0CFPTR3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB0; - unsigned char CFDB1; - unsigned char CFDB2; - unsigned char CFDB3; - } BYTE; - } RSCAN0CFDF03; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB4; - unsigned char CFDB5; - unsigned char CFDB6; - unsigned char CFDB7; - } BYTE; - } RSCAN0CFDF13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFID:29; - unsigned long THLEN:1; - unsigned long CFRTR:1; - unsigned long CFIDE:1; - } BIT; - } RSCAN0CFID4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFTS:16; - unsigned long CFPTR:12; - unsigned long CFDLC:4; - } BIT; - } RSCAN0CFPTR4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB0; - unsigned char CFDB1; - unsigned char CFDB2; - unsigned char CFDB3; - } BYTE; - } RSCAN0CFDF04; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB4; - unsigned char CFDB5; - unsigned char CFDB6; - unsigned char CFDB7; - } BYTE; - } RSCAN0CFDF14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFID:29; - unsigned long THLEN:1; - unsigned long CFRTR:1; - unsigned long CFIDE:1; - } BIT; - } RSCAN0CFID5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long CFTS:16; - unsigned long CFPTR:12; - unsigned long CFDLC:4; - } BIT; - } RSCAN0CFPTR5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB0; - unsigned char CFDB1; - unsigned char CFDB2; - unsigned char CFDB3; - } BYTE; - } RSCAN0CFDF05; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char CFDB4; - unsigned char CFDB5; - unsigned char CFDB6; - unsigned char CFDB7; - } BYTE; - } RSCAN0CFDF15; - char wk23[288]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF00; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF01; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF02; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF03; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF04; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF05; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF15; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF06; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF16; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF07; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF17; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID8; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR8; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF08; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF18; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID9; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR9; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF09; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF19; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF010; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF110; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF011; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF111; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF012; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF112; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF013; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF113; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF014; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF114; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID15; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR15; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF015; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF115; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID16; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR16; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF016; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF116; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID17; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR17; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF017; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF117; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID18; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR18; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF018; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF118; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID19; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR19; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF019; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF119; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID20; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR20; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF020; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF120; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID21; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR21; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF021; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF121; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID22; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR22; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF022; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF122; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID23; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR23; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF023; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF123; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID24; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR24; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF024; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF124; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID25; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR25; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF025; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF125; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID26; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR26; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF026; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF126; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID27; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR27; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF027; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF127; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID28; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR28; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF028; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF128; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID29; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR29; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF029; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF129; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID30; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR30; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF030; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF130; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long TMID:29; - unsigned long THLEN:1; - unsigned long TMRTR:1; - unsigned long TMIDE:1; - } BIT; - } RSCAN0TMID31; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char :8; - unsigned char :8; - unsigned char TMPTR:8; - unsigned char :4; - unsigned char TMDLC:4; - } BIT; - } RSCAN0TMPTR31; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB0; - unsigned char TMDB1; - unsigned char TMDB2; - unsigned char TMDB3; - } BYTE; - } RSCAN0TMDF031; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char TMDB4; - unsigned char TMDB5; - unsigned char TMDB6; - unsigned char TMDB7; - } BYTE; - } RSCAN0TMDF131; - char wk24[1536]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char BT:3; - unsigned char BN:4; - unsigned char :1; - unsigned char TID:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0THLACC0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char BT:3; - unsigned char BN:4; - unsigned char :1; - unsigned char TID:8; - unsigned char :8; - unsigned char :8; - } BIT; - } RSCAN0THLACC1; - char wk25[248]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC7; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC8; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC9; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC10; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC11; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC12; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC13; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC14; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC15; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC16; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC17; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC18; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC19; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC20; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC21; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC22; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC23; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC24; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC25; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC26; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC27; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC28; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC29; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC30; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC31; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC32; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC33; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC34; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC35; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC36; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC37; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC38; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC39; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC40; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC41; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC42; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC43; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC44; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC45; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC46; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC47; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC48; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC49; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC50; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC51; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC52; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC53; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC54; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC55; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC56; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC57; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC58; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC59; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC60; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC61; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC62; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDTA:32; - } BIT; - } RSCAN0RPGACC63; - char wk26[5632]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned char ECEMF:1; - unsigned char ECER1F:1; - unsigned char ECER2F:1; - unsigned char EC1EDIC:1; - unsigned char EC2EDIC:1; - unsigned char EC1ECP:1; - unsigned char ECERVF:1; - unsigned char ECTHM:1; - unsigned char :1; - unsigned char ECER1C:1; - unsigned char ECER2C:1; - unsigned char ECOVFF:1; - unsigned char :2; - unsigned char EMCA0:1; - unsigned char EMCA1:1; - unsigned char ECSEDF0:1; - unsigned char ECDEDF0:1; - unsigned char ECSEDF1:1; - unsigned char ECDEDF1:1; - unsigned char ECSEDF2:1; - unsigned char ECDEDF2:1; - unsigned char ECSEDF3:1; - unsigned char ECDEDF3:1; - unsigned char ECSEDF4:1; - unsigned char ECDEDF4:1; - unsigned char ECSEDF5:1; - unsigned char ECDEDF5:1; - unsigned char ECSEDF6:1; - unsigned char ECDEDF6:1; - unsigned char ECSEDF7:1; - unsigned char ECDEDF7:1; - } BIT; - } ECCRCANCTL; - char wk27[12]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long ECEADz:11; - unsigned long :21; - } BIT; - } ECCRCANEAD0; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long ECEADz:11; - unsigned long :21; - } BIT; - } ECCRCANEAD1; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long ECEADz:11; - unsigned long :21; - } BIT; - } ECCRCANEAD2; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long ECEADz:11; - unsigned long :21; - } BIT; - } ECCRCANEAD3; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long ECEADz:11; - unsigned long :21; - } BIT; - } ECCRCANEAD4; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long ECEADz:11; - unsigned long :21; - } BIT; - } ECCRCANEAD5; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long ECEADz:11; - unsigned long :21; - } BIT; - } ECCRCANEAD6; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long ECEADz:11; - unsigned long :21; - } BIT; - } ECCRCANEAD7; -}; - -struct st_rspi -{ - union - { - unsigned char BYTE; - struct - { - unsigned char SPMS:1; - unsigned char TXMD:1; - unsigned char MODFEN:1; - unsigned char MSTR:1; - unsigned char SPEIE:1; - unsigned char SPTIE:1; - unsigned char SPE:1; - unsigned char SPRIE:1; - } BIT; - } SPCR; - union - { - unsigned char BYTE; - struct - { - unsigned char SSL0P:1; - unsigned char SSL1P:1; - unsigned char SSL2P:1; - unsigned char SSL3P:1; - unsigned char :4; - } BIT; - } SSLP; - union - { - unsigned char BYTE; - struct - { - unsigned char SPLP:1; - unsigned char SPLP2:1; - unsigned char SPOM:1; - unsigned char :1; - unsigned char MOIFV:1; - unsigned char MOIFE:1; - unsigned char :2; - } BIT; - } SPPCR; - union - { - unsigned char BYTE; - struct - { - unsigned char OVRF:1; - unsigned char IDLNF:1; - unsigned char MODF:1; - unsigned char PERF:1; - unsigned char :4; - } BIT; - } SPSR; - union - { - unsigned long LONG; - struct - { - unsigned short L; - unsigned short H; - } WORD; - } SPDR; - union - { - unsigned char BYTE; - struct - { - unsigned char SPSLN:3; - unsigned char :5; - } BIT; - } SPSCR; - union - { - unsigned char BYTE; - struct - { - unsigned char SPCP:3; - unsigned char :1; - unsigned char SPECM:3; - unsigned char :1; - } BIT; - } SPSSR; - unsigned char SPBR; - union - { - unsigned char BYTE; - struct - { - unsigned char SPFC:2; - unsigned char :2; - unsigned char SPRDTD:1; - unsigned char SPLW:1; - unsigned char :2; - } BIT; - } SPDCR; - union - { - unsigned char BYTE; - struct - { - unsigned char SCKDL:3; - unsigned char :5; - } BIT; - } SPCKD; - union - { - unsigned char BYTE; - struct - { - unsigned char SLNDL:3; - unsigned char :5; - } BIT; - } SSLND; - union - { - unsigned char BYTE; - struct - { - unsigned char SPNDL:3; - unsigned char :5; - } BIT; - } SPND; - union - { - unsigned char BYTE; - struct - { - unsigned char SPPE:1; - unsigned char SPOE:1; - unsigned char SPIIE:1; - unsigned char PTE:1; - unsigned char SCKASE:1; - unsigned char :3; - } BIT; - } SPCR2; - union - { - unsigned short WORD; - struct - { - unsigned short CPHA:1; - unsigned short CPOL:1; - unsigned short BRDV:2; - unsigned short SSLy:3; - unsigned short SSLKP:1; - unsigned short SPB:4; - unsigned short LSBF:1; - unsigned short SPNDEN:1; - unsigned short SLNDEN:1; - unsigned short SCKDEN:1; - } BIT; - } SPCMD0; - union - { - unsigned short WORD; - struct - { - unsigned short CPHA:1; - unsigned short CPOL:1; - unsigned short BRDV:2; - unsigned short SSLy:3; - unsigned short SSLKP:1; - unsigned short SPB:4; - unsigned short LSBF:1; - unsigned short SPNDEN:1; - unsigned short SLNDEN:1; - unsigned short SCKDEN:1; - } BIT; - } SPCMD1; - union - { - unsigned short WORD; - struct - { - unsigned short CPHA:1; - unsigned short CPOL:1; - unsigned short BRDV:2; - unsigned short SSLy:3; - unsigned short SSLKP:1; - unsigned short SPB:4; - unsigned short LSBF:1; - unsigned short SPNDEN:1; - unsigned short SLNDEN:1; - unsigned short SCKDEN:1; - } BIT; - } SPCMD2; - union - { - unsigned short WORD; - struct - { - unsigned short CPHA:1; - unsigned short CPOL:1; - unsigned short BRDV:2; - unsigned short SSLy:3; - unsigned short SSLKP:1; - unsigned short SPB:4; - unsigned short LSBF:1; - unsigned short SPNDEN:1; - unsigned short SLNDEN:1; - unsigned short SCKDEN:1; - } BIT; - } SPCMD3; - union - { - unsigned short WORD; - struct - { - unsigned short CPHA:1; - unsigned short CPOL:1; - unsigned short BRDV:2; - unsigned short SSLy:3; - unsigned short SSLKP:1; - unsigned short SPB:4; - unsigned short LSBF:1; - unsigned short SPNDEN:1; - unsigned short SLNDEN:1; - unsigned short SCKDEN:1; - } BIT; - } SPCMD4; - union - { - unsigned short WORD; - struct - { - unsigned short CPHA:1; - unsigned short CPOL:1; - unsigned short BRDV:2; - unsigned short SSLy:3; - unsigned short SSLKP:1; - unsigned short SPB:4; - unsigned short LSBF:1; - unsigned short SPNDEN:1; - unsigned short SLNDEN:1; - unsigned short SCKDEN:1; - } BIT; - } SPCMD5; - union - { - unsigned short WORD; - struct - { - unsigned short CPHA:1; - unsigned short CPOL:1; - unsigned short BRDV:2; - unsigned short SSLy:3; - unsigned short SSLKP:1; - unsigned short SPB:4; - unsigned short LSBF:1; - unsigned short SPNDEN:1; - unsigned short SLNDEN:1; - unsigned short SCKDEN:1; - } BIT; - } SPCMD6; - union - { - unsigned short WORD; - struct - { - unsigned short CPHA:1; - unsigned short CPOL:1; - unsigned short BRDV:2; - unsigned short SSLy:3; - unsigned short SSLKP:1; - unsigned short SPB:4; - unsigned short LSBF:1; - unsigned short SPNDEN:1; - unsigned short SLNDEN:1; - unsigned short SCKDEN:1; - } BIT; - } SPCMD7; -}; - -struct st_s12adc0 -{ - union - { - unsigned short WORD; - struct - { - unsigned short DBLANS:5; - unsigned short :1; - unsigned short GBADIE:1; - unsigned short DBLE:1; - unsigned short EXTRG:1; - unsigned short TRGE:1; - unsigned short :2; - unsigned short ADIE:1; - unsigned short ADCS:2; - unsigned short ADST:1; - } BIT; - } ADCSR; - char wk0[2]; - union - { - unsigned short WORD; - struct - { - unsigned short ANSA:16; - } BIT; - } ADANSA; - char wk1[2]; - union - { - unsigned short WORD; - struct - { - unsigned short ADS:16; - } BIT; - } ADADS; - char wk2[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char ADC:2; - unsigned char :5; - unsigned char AVEE:1; - } BIT; - } ADADC; - char wk3[1]; - union - { - unsigned short WORD; - struct - { - unsigned short :1; - unsigned short ADPRC:2; - unsigned short :2; - unsigned short ACE:1; - unsigned short :2; - unsigned short DIAGVAL:2; - unsigned short DIAGLD:1; - unsigned short DIAGM:1; - unsigned short :3; - unsigned short ADRFMT:1; - } BIT; - } ADCER; - union - { - unsigned short WORD; - struct - { - unsigned short TRSB:6; - unsigned short :2; - unsigned short TRSA:6; - unsigned short :2; - } BIT; - } ADSTRGR; - union - { - unsigned short WORD; - struct - { - unsigned short TSSAD:1; - unsigned short :7; - unsigned short TSSA:1; - unsigned short :1; - unsigned short TSSB:1; - unsigned short :5; - } BIT; - } ADEXICR; - union - { - unsigned short WORD; - struct - { - unsigned short ANSB:16; - } BIT; - } ADANSB; - char wk4[2]; - unsigned short ADDBLDR; - unsigned short ADTSDR; - char wk5[2]; - unsigned short ADRD; - unsigned short ADDR0; - unsigned short ADDR1; - unsigned short ADDR2; - unsigned short ADDR3; - unsigned short ADDR4; - unsigned short ADDR5; - unsigned short ADDR6; - unsigned short ADDR7; - char wk6[48]; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR0; - char wk7[5]; - union - { - unsigned short WORD; - struct - { - unsigned short SSTSH:8; - unsigned short SHANS:4; - unsigned short :4; - } BIT; - } ADSHCR; - char wk8[8]; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTRT; - char wk9[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR1; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR2; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR3; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR4; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR5; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR6; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR7; - union - { - unsigned char BYTE; - struct - { - unsigned char ADNDIS:5; - unsigned char :3; - } BIT; - } ADDISCR; - char wk10[5]; - union - { - unsigned short WORD; - struct - { - unsigned short PGS:1; - unsigned short GBRSCN:1; - unsigned short :13; - unsigned short GBRP:1; - } BIT; - } ADGSPCR; - char wk11[2]; - unsigned short ADDBLDRA; - unsigned short ADDBLDRB; - char wk12[8]; - union - { - unsigned char BYTE; - struct - { - unsigned char :6; - unsigned char WCMPE:1; - unsigned char CMPIE:1; - } BIT; - } ADCMPCR; - char wk13[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char CMPSTS:1; - unsigned char :7; - } BIT; - } ADCMPANSER; - union - { - unsigned char BYTE; - struct - { - unsigned char CMPLTS:1; - unsigned char :7; - } BIT; - } ADCMPLER; - union - { - unsigned short WORD; - struct - { - unsigned short CMPS:16; - } BIT; - } ADCMPANSR; - char wk14[2]; - union - { - unsigned short WORD; - struct - { - unsigned short CMPL:16; - } BIT; - } ADCMPLR; - char wk15[2]; - unsigned short ADCMPDR0; - unsigned short ADCMPDR1; - union - { - unsigned short WORD; - struct - { - unsigned short CMPF:16; - } BIT; - } ADCMPSR; - char wk16[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char CMPFTS:1; - unsigned char :7; - } BIT; - } ADCMPSER; - char wk17[35]; - union - { - unsigned char BYTE; - struct - { - unsigned char TDLV:2; - unsigned char :5; - unsigned char TDE:1; - } BIT; - } ADTDCR; - char wk18[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char :2; - unsigned char OWEIE:1; - unsigned char :5; - } BIT; - } ADERCR; - union - { - unsigned char BYTE; - struct - { - unsigned char :2; - unsigned char OWEC:1; - unsigned char :5; - } BIT; - } ADERCLR; - char wk19[6]; - union - { - unsigned short WORD; - struct - { - unsigned short OWE:16; - } BIT; - } ADOWER; - char wk20[2]; - union - { - unsigned short WORD; - struct - { - unsigned short DBOWE:1; - unsigned short DAOWE:1; - unsigned short DOWE:1; - unsigned short DIAGOWE:1; - unsigned short TSOWE:1; - unsigned short :11; - } BIT; - } ADOWEER; -}; - -struct st_s12adc1 -{ - union - { - unsigned short WORD; - struct - { - unsigned short DBLANS:5; - unsigned short :1; - unsigned short GBADIE:1; - unsigned short DBLE:1; - unsigned short EXTRG:1; - unsigned short TRGE:1; - unsigned short :2; - unsigned short ADIE:1; - unsigned short ADCS:2; - unsigned short ADST:1; - } BIT; - } ADCSR; - char wk0[2]; - union - { - unsigned short WORD; - struct - { - unsigned short ANSA:16; - } BIT; - } ADANSA; - char wk1[2]; - union - { - unsigned short WORD; - struct - { - unsigned short ADS:16; - } BIT; - } ADADS; - char wk2[2]; - union - { - unsigned char BYTE; - struct - { - unsigned char ADC:2; - unsigned char :5; - unsigned char AVEE:1; - } BIT; - } ADADC; - char wk3[1]; - union - { - unsigned short WORD; - struct - { - unsigned short :1; - unsigned short ADPRC:2; - unsigned short :2; - unsigned short ACE:1; - unsigned short :2; - unsigned short DIAGVAL:2; - unsigned short DIAGLD:1; - unsigned short DIAGM:1; - unsigned short :3; - unsigned short ADRFMT:1; - } BIT; - } ADCER; - union - { - unsigned short WORD; - struct - { - unsigned short TRSB:6; - unsigned short :2; - unsigned short TRSA:6; - unsigned short :2; - } BIT; - } ADSTRGR; - union - { - unsigned short WORD; - struct - { - unsigned short :13; - unsigned short EXSEL:2; - unsigned short EXOEN:1; - } BIT; - } ADEXICR; - union - { - unsigned short WORD; - struct - { - unsigned short ANSB:16; - } BIT; - } ADANSB; - char wk4[2]; - unsigned short ADDBLDR; - char wk5[4]; - unsigned short ADRD; - unsigned short ADDR0; - unsigned short ADDR1; - unsigned short ADDR2; - unsigned short ADDR3; - unsigned short ADDR4; - unsigned short ADDR5; - unsigned short ADDR6; - unsigned short ADDR7; - unsigned short ADDR8; - unsigned short ADDR9; - unsigned short ADDR10; - unsigned short ADDR11; - unsigned short ADDR12; - unsigned short ADDR13; - unsigned short ADDR14; - unsigned short ADDR15; - char wk6[32]; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR0; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTRL; - char wk7[17]; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR1; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR2; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR3; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR4; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR5; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR6; - union - { - unsigned char BYTE; - struct - { - unsigned char SST:8; - } BIT; - } ADSSTR7; - union - { - unsigned char BYTE; - struct - { - unsigned char ADNDIS:5; - unsigned char :3; - } BIT; - } ADDISCR; - char wk8[5]; - union - { - unsigned short WORD; - struct - { - unsigned short PGS:1; - unsigned short GBRSCN:1; - unsigned short :13; - unsigned short GBRP:1; - } BIT; - } ADGSPCR; - char wk9[2]; - unsigned short ADDBLDRA; - unsigned short ADDBLDRB; - char wk10[8]; - union - { - unsigned char BYTE; - struct - { - unsigned char :6; - unsigned char WCMPE:1; - unsigned char CMPIE:1; - } BIT; - } ADCMPCR; - char wk11[3]; - union - { - unsigned short WORD; - struct - { - unsigned short CMPS:16; - } BIT; - } ADCMPANSR; - char wk12[2]; - union - { - unsigned short WORD; - struct - { - unsigned short CMPL:16; - } BIT; - } ADCMPLR; - char wk13[2]; - unsigned short ADCMPDR0; - unsigned short ADCMPDR1; - union - { - unsigned short WORD; - struct - { - unsigned short CMPF:16; - } BIT; - } ADCMPSR; - char wk14[38]; - union - { - unsigned char BYTE; - struct - { - unsigned char TDLV:2; - unsigned char :5; - unsigned char TDE:1; - } BIT; - } ADTDCR; - char wk15[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char :2; - unsigned char OWEIE:1; - unsigned char :5; - } BIT; - } ADERCR; - union - { - unsigned char BYTE; - struct - { - unsigned char :2; - unsigned char OWEC:1; - unsigned char :5; - } BIT; - } ADERCLR; - char wk16[6]; - union - { - unsigned short WORD; - struct - { - unsigned short OWE:16; - } BIT; - } ADOWER; - char wk17[2]; - union - { - unsigned short WORD; - struct - { - unsigned short DBOWE:1; - unsigned short DAOWE:1; - unsigned short DOWE:1; - unsigned short DIAGOWE:1; - unsigned short TSOWE:1; - unsigned short :11; - } BIT; - } ADOWEER; -}; - -struct st_scifa -{ - union - { - unsigned short WORD; - struct - { - unsigned short CKS:2; - unsigned short :1; - unsigned short STOP:1; - unsigned short PM:1; - unsigned short PE:1; - unsigned short CHR:1; - unsigned short CM:1; - unsigned short :8; - } BIT; - } SMR; - union - { - unsigned char BRR; - unsigned char MDDR; - } BRR_MDDR; - char wk0[1]; - union - { - unsigned short WORD; - struct - { - unsigned short CKE:2; - unsigned short TEIE:1; - unsigned short REIE:1; - unsigned short RE:1; - unsigned short TE:1; - unsigned short RIE:1; - unsigned short TIE:1; - unsigned short :8; - } BIT; - } SCR; - unsigned char FTDR; - char wk1[1]; - union - { - unsigned short WORD; - struct - { - unsigned short DR:1; - unsigned short RDF:1; - unsigned short PER:1; - unsigned short FER:1; - unsigned short BRK:1; - unsigned short TDFE:1; - unsigned short TEND:1; - unsigned short ER:1; - unsigned short :8; - } BIT; - } FSR; - unsigned char FRDR; - char wk2[1]; - union - { - unsigned short WORD; - struct - { - unsigned short LOOP:1; - unsigned short RFRST:1; - unsigned short TFRST:1; - unsigned short MCE:1; - unsigned short TTRG:2; - unsigned short RTRG:2; - unsigned short RSTRG:3; - unsigned short :5; - } BIT; - } FCR; - union - { - unsigned short WORD; - struct - { - unsigned short R:5; - unsigned short :3; - unsigned short T:5; - unsigned short :3; - } BIT; - } FDR; - union - { - unsigned short WORD; - struct - { - unsigned short SPB2DT:1; - unsigned short SPB2IO:1; - unsigned short SCKDT:1; - unsigned short SCKIO:1; - unsigned short CTS2DT:1; - unsigned short CTS2IO:1; - unsigned short RTS2DT:1; - unsigned short RTS2IO:1; - unsigned short :8; - } BIT; - } SPTR; - union - { - unsigned short WORD; - struct - { - unsigned short ORER:1; - unsigned short :1; - unsigned short FER:4; - unsigned short :2; - unsigned short PER:4; - unsigned short :4; - } BIT; - } LSR; - union - { - unsigned char BYTE; - struct - { - unsigned char ABCS0:1; - unsigned char :1; - unsigned char NFEN:1; - unsigned char DIR:1; - unsigned char MDDRS:1; - unsigned char BRME:1; - unsigned char :1; - unsigned char BGDM:1; - } BIT; - } SEMR; - char wk3[1]; - union - { - unsigned short WORD; - struct - { - unsigned short TFTC:5; - unsigned short :2; - unsigned short TTRGS:1; - unsigned short RFTC:5; - unsigned short :2; - unsigned short RTRGS:1; - } BIT; - } FTCR; -}; - -struct st_spibsc -{ - union - { - unsigned long LONG; - struct - { - unsigned long BSZ:2; - unsigned long :1; - unsigned long CPOL:1; - unsigned long SSLP:1; - unsigned long CPHAR:1; - unsigned long CPHAT:1; - unsigned long :1; - unsigned long IO0FV:2; - unsigned long :2; - unsigned long IO2FV:2; - unsigned long IO3FV:2; - unsigned long MOIIO0:2; - unsigned long MOIIO1:2; - unsigned long MOIIO2:2; - unsigned long MOIIO3:2; - unsigned long SFDE:1; - unsigned long :6; - unsigned long MD:1; - } BIT; - } CMNCR; - union - { - unsigned long LONG; - struct - { - unsigned long SCKDL:3; - unsigned long :5; - unsigned long SLNDL:3; - unsigned long :5; - unsigned long SPNDL:3; - unsigned long :13; - } BIT; - } SSLDR; - union - { - unsigned long LONG; - struct - { - unsigned long BRDV:2; - unsigned long :6; - unsigned long SPBR:8; - unsigned long :16; - } BIT; - } SPBCR; - union - { - unsigned long LONG; - struct - { - unsigned long SSLE:1; - unsigned long :7; - unsigned long RBE:1; - unsigned long RCF:1; - unsigned long :6; - unsigned long RBURST:4; - unsigned long :4; - unsigned long SSLN:1; - unsigned long :7; - } BIT; - } DRCR; - union - { - unsigned long LONG; - struct - { - unsigned long OCMD:8; - unsigned long :8; - unsigned long CMD:8; - unsigned long :8; - } BIT; - } DRCMR; - union - { - unsigned long LONG; - struct - { - unsigned long EAC:3; - unsigned long :13; - unsigned long EAV:8; - unsigned long :8; - } BIT; - } DREAR; - union - { - unsigned long LONG; - struct - { - unsigned long OPD0:8; - unsigned long OPD1:8; - unsigned long OPD2:8; - unsigned long OPD3:8; - } BIT; - } DROPR; - union - { - unsigned long LONG; - struct - { - unsigned long :4; - unsigned long OPDE:4; - unsigned long ADE:4; - unsigned long OCDE:1; - unsigned long :1; - unsigned long CDE:1; - unsigned long DME:1; - unsigned long DRDB:2; - unsigned long :2; - unsigned long OPDB:2; - unsigned long :2; - unsigned long ADB:2; - unsigned long :2; - unsigned long OCDB:2; - unsigned long CDB:2; - } BIT; - } DRENR; - union - { - unsigned long LONG; - struct - { - unsigned long SPIE:1; - unsigned long SPIWE:1; - unsigned long SPIRE:1; - unsigned long :5; - unsigned long SSLKP:1; - unsigned long :23; - } BIT; - } SMCR; - union - { - unsigned long LONG; - struct - { - unsigned long OCMD:8; - unsigned long :8; - unsigned long CMD:8; - unsigned long :8; - } BIT; - } SMCMR; - union - { - unsigned long LONG; - struct - { - unsigned long ADR:24; - unsigned long ADRE:8; - } BIT; - } SMADR; - union - { - unsigned long LONG; - struct - { - unsigned long OPD0:8; - unsigned long OPD1:8; - unsigned long OPD2:8; - unsigned long OPD3:8; - } BIT; - } SMOPR; - union - { - unsigned long LONG; - struct - { - unsigned long SPIDE:4; - unsigned long OPDE:4; - unsigned long ADE:4; - unsigned long OCDE:1; - unsigned long :1; - unsigned long CDE:1; - unsigned long DME:1; - unsigned long SPIDB:2; - unsigned long :2; - unsigned long OPDB:2; - unsigned long :2; - unsigned long ADB:2; - unsigned long :2; - unsigned long OCDB:2; - unsigned long CDB:2; - } BIT; - } SMENR; - char wk0[4]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long RDATA0:32; - } BIT; - } SMRDR0; - char wk1[4]; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long WDATA0:32; - } BIT; - } SMWDR0; - char wk2[4]; - union - { - unsigned long LONG; - struct - { - unsigned long TEND:1; - unsigned long SSLF:1; - unsigned long :30; - } BIT; - } CMNSR; - char wk3[12]; - union - { - unsigned long LONG; - struct - { - unsigned long DMCYC:3; - unsigned long :13; - unsigned long DMDB:2; - unsigned long :14; - } BIT; - } DRDMCR; - char wk4[4]; - union - { - unsigned long LONG; - struct - { - unsigned long DMCYC:3; - unsigned long :13; - unsigned long DMDB:2; - unsigned long :14; - } BIT; - } SMDMCR; -}; - -struct st_ssi -{ - union - { - unsigned long LONG; - struct - { - unsigned long REN:1; - unsigned long TEN:1; - unsigned long :1; - unsigned long MUEN:1; - unsigned long CKDV:4; - unsigned long DEL:1; - unsigned long PDTA:1; - unsigned long SDTA:1; - unsigned long SPDP:1; - unsigned long SWSP:1; - unsigned long SCKP:1; - unsigned long SWSD:1; - unsigned long SCKD:1; - unsigned long SWL:3; - unsigned long DWL:3; - unsigned long CHNL:2; - unsigned long :1; - unsigned long IIEN:1; - unsigned long ROIEN:1; - unsigned long RUIEN:1; - unsigned long TOIEN:1; - unsigned long TUIEN:1; - unsigned long CKS:1; - unsigned long :1; - } BIT; - } SSICR; - union - { - unsigned long LONG; - struct - { - unsigned long IDST:1; - unsigned long RSWNO:1; - unsigned long :2; - unsigned long TSWNO:1; - unsigned long :20; - unsigned long IIRQ:1; - unsigned long ROIRQ:1; - unsigned long RUIRQ:1; - unsigned long TOIRQ:1; - unsigned long TUIRQ:1; - unsigned long :2; - } BIT; - } SSISR; - char wk0[8]; - union - { - unsigned long LONG; - struct - { - unsigned long RFRST:1; - unsigned long TFRST:1; - unsigned long RIE:1; - unsigned long TIE:1; - unsigned long RTRG:2; - unsigned long TTRG:2; - unsigned long :23; - unsigned long AUCKE:1; - } BIT; - } SSIFCR; - union - { - unsigned long LONG; - struct - { - unsigned long RDF:1; - unsigned long :7; - unsigned long RDC:4; - unsigned long :4; - unsigned long TDE:1; - unsigned long :7; - unsigned long TDC:4; - unsigned long :4; - } BIT; - } SSIFSR; - unsigned long SSIFTDR; - unsigned long SSIFRDR; - union - { - unsigned long LONG; - struct - { - unsigned long :8; - unsigned long CONT:1; - unsigned long :23; - } BIT; - } SSITDMR; -}; - -struct st_system -{ - union - { - unsigned long LONG; - struct - { - unsigned long PCKG:2; - unsigned long PCKF:2; - unsigned long PCKE:2; - unsigned long :2; - unsigned long CKIO:3; - unsigned long :1; - unsigned long ETCKE:1; - unsigned long :1; - unsigned long ETCKD:2; - unsigned long SERICK:1; - unsigned long :3; - unsigned long TCLK:1; - unsigned long :11; - } BIT; - } SCKCR; - union - { - unsigned long LONG; - struct - { - unsigned long CKSEL0:1; - unsigned long :31; - } BIT; - } SCKCR2; - union - { - unsigned long LONG; - struct - { - unsigned long DSSEL0:1; - unsigned long DSCK0:3; - unsigned long DSINV0:1; - unsigned long DSCHSEL:1; - unsigned long :10; - unsigned long DSSEL1:1; - unsigned long DSCK1:3; - unsigned long DSINV1:1; - unsigned long :11; - } BIT; - } DSCR; - char wk0[8]; - union - { - unsigned long LONG; - struct - { - unsigned long CPUCKSEL:2; - unsigned long :30; - } BIT; - } PLL1CR; - union - { - unsigned long LONG; - struct - { - unsigned long PLL1EN:1; - unsigned long :31; - } BIT; - } PLL1CR2; - char wk1[4]; - union - { - unsigned long LONG; - struct - { - unsigned long LCSTP:1; - unsigned long :31; - } BIT; - } LOCOCR; - char wk2[8]; - union - { - unsigned long LONG; - struct - { - unsigned long OSTDIE:1; - unsigned long :6; - unsigned long OSTDE:1; - unsigned long :24; - } BIT; - } OSTDCR; - char wk3[432]; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long TRF:1; - unsigned long ECMRF:1; - unsigned long SWR1F:1; - unsigned long :28; - } BIT; - } RSTSR0; - char wk4[12]; - union - { - unsigned long LONG; - } SWRR1; - char wk5[12]; - union - { - unsigned long LONG; - } SWRR2; - char wk6[36]; - union - { - unsigned long LONG; - struct - { - unsigned long MRUSBF:1; - unsigned long MRUSBH:1; - unsigned long :30; - } BIT; - } MRCTLC; - char wk7[180]; - union - { - unsigned long LONG; - struct - { - unsigned long MSTPCRA0:1; - unsigned long MSTPCRA1:1; - unsigned long MSTPCRA2:1; - unsigned long MSTPCRA3:1; - unsigned long MSTPCRA4:1; - unsigned long MSTPCRA5:1; - unsigned long MSTPCRA6:1; - unsigned long MSTPCRA7:1; - unsigned long MSTPCRA8:1; - unsigned long MSTPCRA9:1; - unsigned long :1; - unsigned long MSTPCRA11:1; - unsigned long :20; - } BIT; - } MSTPCRA; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long MSTPCRB1:1; - unsigned long MSTPCRB2:1; - unsigned long MSTPCRB3:1; - unsigned long :1; - unsigned long MSTPCRB5:1; - unsigned long MSTPCRB6:1; - unsigned long MSTPCRB7:1; - unsigned long MSTPCRB8:1; - unsigned long MSTPCRB9:1; - unsigned long MSTPCRB10:1; - unsigned long MSTPCRB11:1; - unsigned long MSTPCRB12:1; - unsigned long MSTPCRB13:1; - unsigned long MSTPCRB14:1; - unsigned long MSTPCRB15:1; - unsigned long MSTPCRB16:1; - unsigned long MSTPCRB17:1; - unsigned long MSTPCRB18:1; - unsigned long MSTPCRB19:1; - unsigned long :12; - } BIT; - } MSTPCRB; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long MSTPCRC1:1; - unsigned long MSTPCRC2:1; - unsigned long MSTPCRC3:1; - unsigned long MSTPCRC4:1; - unsigned long MSTPCRC5:1; - unsigned long MSTPCRC6:1; - unsigned long MSTPCRC7:1; - unsigned long MSTPCRC8:1; - unsigned long MSTPCRC9:1; - unsigned long MSTPCRC10:1; - unsigned long MSTPCRC11:1; - unsigned long MSTPCRC12:1; - unsigned long MSTPCRC13:1; - unsigned long MSTPCRC14:1; - unsigned long :17; - } BIT; - } MSTPCRC; - union - { - unsigned long LONG; - struct - { - unsigned long :2; - unsigned long MSTPCRD2:1; - unsigned long :29; - } BIT; - } MSTPCRD; - union - { - unsigned long LONG; - struct - { - unsigned long :4; - unsigned long MSTPCRE4:1; - unsigned long MSTPCRE5:1; - unsigned long :26; - } BIT; - } MSTPCRE; - union - { - unsigned long LONG; - struct - { - unsigned long MSTPCRF0:1; - unsigned long :31; - } BIT; - } MSTPCRF; - char wk8[1256]; - union - { - unsigned long LONG; - struct - { - unsigned long ATCMWAIT:2; - unsigned long :30; - } BIT; - } SYTATCMWAIT; - char wk9[284]; - union - { - unsigned long LONG; - struct - { - unsigned long SEMFEN:1; - unsigned long :31; - } BIT; - } SYTSEMFEN; - char wk10[12]; - union - { - unsigned long LONG; - struct - { - unsigned long SEMF0:1; - unsigned long :31; - } BIT; - } SYTSEMF0; - union - { - unsigned long LONG; - struct - { - unsigned long SEMF1:1; - unsigned long :31; - } BIT; - } SYTSEMF1; - union - { - unsigned long LONG; - struct - { - unsigned long SEMF2:1; - unsigned long :31; - } BIT; - } SYTSEMF2; - union - { - unsigned long LONG; - struct - { - unsigned long SEMF3:1; - unsigned long :31; - } BIT; - } SYTSEMF3; - union - { - unsigned long LONG; - struct - { - unsigned long SEMF4:1; - unsigned long :31; - } BIT; - } SYTSEMF4; - union - { - unsigned long LONG; - struct - { - unsigned long SEMF5:1; - unsigned long :31; - } BIT; - } SYTSEMF5; - union - { - unsigned long LONG; - struct - { - unsigned long SEMF6:1; - unsigned long :31; - } BIT; - } SYTSEMF6; - union - { - unsigned long LONG; - struct - { - unsigned long SEMF7:1; - unsigned long :31; - } BIT; - } SYTSEMF7; - char wk11[176]; - union - { - unsigned long LONG; - struct - { - unsigned long SWVSEL:2; - unsigned long :30; - } BIT; - } DBGIFCNT; - char wk12[92]; - union - { - unsigned long LONG; - struct - { - unsigned long MD0:1; - unsigned long MD1:1; - unsigned long MD2:1; - unsigned long :29; - } BIT; - } MDMONR; - char wk13[28]; - union - { - unsigned long LONG; - struct - { - unsigned long MSKC:1; - unsigned long MSKM:1; - unsigned long :30; - } BIT; - } ECMMCNT; - char wk14[124]; - union - { - unsigned long LONG; - } PRCR; -}; - -struct st_tpu0 -{ - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR; - char wk0[7]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char ICSELB:1; - unsigned char ICSELD:1; - } BIT; - } TMDR; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIORH; - union - { - unsigned char BYTE; - struct - { - unsigned char IOC:4; - unsigned char IOD:4; - } BIT; - } TIORL; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char TCIEU:1; - unsigned char :1; - unsigned char TTGE:1; - } BIT; - } TIER; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char TGFC:1; - unsigned char TGFD:1; - unsigned char TCFV:1; - unsigned char TCFU:1; - unsigned char :1; - unsigned char TCFD:1; - } BIT; - } TSR; - unsigned short TCNT; - unsigned short TGRA; - unsigned short TGRB; - unsigned short TGRC; - unsigned short TGRD; -}; - -struct st_tpu1 -{ - char wk0[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR; - char wk1[22]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char ICSELB:1; - unsigned char ICSELD:1; - } BIT; - } TMDR; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIOR; - char wk2[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char TCIEU:1; - unsigned char :1; - unsigned char TTGE:1; - } BIT; - } TIER; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char TGFC:1; - unsigned char TGFD:1; - unsigned char TCFV:1; - unsigned char TCFU:1; - unsigned char :1; - unsigned char TCFD:1; - } BIT; - } TSR; - unsigned short TCNT; - unsigned short TGRA; - unsigned short TGRB; -}; - -struct st_tpu2 -{ - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR; - char wk0[37]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char ICSELB:1; - unsigned char ICSELD:1; - } BIT; - } TMDR; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIOR; - char wk1[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char TCIEU:1; - unsigned char :1; - unsigned char TTGE:1; - } BIT; - } TIER; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char TGFC:1; - unsigned char TGFD:1; - unsigned char TCFV:1; - unsigned char TCFU:1; - unsigned char :1; - unsigned char TCFD:1; - } BIT; - } TSR; - unsigned short TCNT; - unsigned short TGRA; - unsigned short TGRB; -}; - -struct st_tpu3 -{ - char wk0[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR; - char wk1[52]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char ICSELB:1; - unsigned char ICSELD:1; - } BIT; - } TMDR; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIORH; - union - { - unsigned char BYTE; - struct - { - unsigned char IOC:4; - unsigned char IOD:4; - } BIT; - } TIORL; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char TCIEU:1; - unsigned char :1; - unsigned char TTGE:1; - } BIT; - } TIER; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char TGFC:1; - unsigned char TGFD:1; - unsigned char TCFV:1; - unsigned char TCFU:1; - unsigned char :1; - unsigned char TCFD:1; - } BIT; - } TSR; - unsigned short TCNT; - unsigned short TGRA; - unsigned short TGRB; - unsigned short TGRC; - unsigned short TGRD; -}; - -struct st_tpu4 -{ - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR; - char wk0[67]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char ICSELB:1; - unsigned char ICSELD:1; - } BIT; - } TMDR; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIOR; - char wk1[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char TCIEU:1; - unsigned char :1; - unsigned char TTGE:1; - } BIT; - } TIER; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char TGFC:1; - unsigned char TGFD:1; - unsigned char TCFV:1; - unsigned char TCFU:1; - unsigned char :1; - unsigned char TCFD:1; - } BIT; - } TSR; - unsigned short TCNT; - unsigned short TGRA; - unsigned short TGRB; -}; - -struct st_tpu5 -{ - char wk0[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char NFAEN:1; - unsigned char NFBEN:1; - unsigned char NFCEN:1; - unsigned char NFDEN:1; - unsigned char NFCS:2; - unsigned char :2; - } BIT; - } NFCR; - char wk1[82]; - union - { - unsigned char BYTE; - struct - { - unsigned char TPSC:3; - unsigned char CKEG:2; - unsigned char CCLR:3; - } BIT; - } TCR; - union - { - unsigned char BYTE; - struct - { - unsigned char MD:4; - unsigned char BFA:1; - unsigned char BFB:1; - unsigned char ICSELB:1; - unsigned char ICSELD:1; - } BIT; - } TMDR; - union - { - unsigned char BYTE; - struct - { - unsigned char IOA:4; - unsigned char IOB:4; - } BIT; - } TIOR; - char wk2[1]; - union - { - unsigned char BYTE; - struct - { - unsigned char TGIEA:1; - unsigned char TGIEB:1; - unsigned char TGIEC:1; - unsigned char TGIED:1; - unsigned char TCIEV:1; - unsigned char TCIEU:1; - unsigned char :1; - unsigned char TTGE:1; - } BIT; - } TIER; - union - { - unsigned char BYTE; - struct - { - unsigned char TGFA:1; - unsigned char TGFB:1; - unsigned char TGFC:1; - unsigned char TGFD:1; - unsigned char TCFV:1; - unsigned char TCFU:1; - unsigned char :1; - unsigned char TCFD:1; - } BIT; - } TSR; - unsigned short TCNT; - unsigned short TGRA; - unsigned short TGRB; -}; - -struct st_tpua -{ - union - { - unsigned char BYTE; - struct - { - unsigned char CST0:1; - unsigned char CST1:1; - unsigned char CST2:1; - unsigned char CST3:1; - unsigned char CST4:1; - unsigned char CST5:1; - unsigned char :2; - } BIT; - } TSTRA; - union - { - unsigned char BYTE; - struct - { - unsigned char SYNC0:1; - unsigned char SYNC1:1; - unsigned char SYNC2:1; - unsigned char SYNC3:1; - unsigned char SYNC4:1; - unsigned char SYNC5:1; - unsigned char :2; - } BIT; - } TSYRA; - char wk0[126]; - union - { - unsigned char BYTE; - struct - { - unsigned char CST0:1; - unsigned char CST1:1; - unsigned char CST2:1; - unsigned char CST3:1; - unsigned char CST4:1; - unsigned char CST5:1; - unsigned char :2; - } BIT; - } TSTRB; - union - { - unsigned char BYTE; - struct - { - unsigned char SYNC0:1; - unsigned char SYNC1:1; - unsigned char SYNC2:1; - unsigned char SYNC3:1; - unsigned char SYNC4:1; - unsigned char SYNC5:1; - unsigned char :2; - } BIT; - } TSYRB; -}; - -struct st_tpusl -{ - union - { - unsigned long LONG; - struct - { - unsigned long TPU0EN:1; - unsigned long :1; - unsigned long FBSL0:3; - unsigned long :3; - unsigned long TPU1EN:1; - unsigned long :1; - unsigned long FBSL1:3; - unsigned long :19; - } BIT; - } PWMFBSLR; -}; - -struct st_tsn -{ - union - { - unsigned char BYTE; - struct - { - unsigned char :4; - unsigned char TSOE:1; - unsigned char :2; - unsigned char TSEN:1; - } BIT; - } TSCR; -}; - -struct st_usbf -{ - union - { - unsigned short WORD; - struct - { - unsigned short USBE:1; - unsigned short :3; - unsigned short DPRPU:1; - unsigned short DRPD:1; - unsigned short :1; - unsigned short HSE:1; - unsigned short :8; - } BIT; - } SYSCFG0; - union - { - unsigned short WORD; - struct - { - unsigned short BWAIT:6; - unsigned short :10; - } BIT; - } SYSCFG1; - union - { - unsigned short WORD; - struct - { - unsigned short LNST:2; - unsigned short :14; - } BIT; - } SYSSTS0; - char wk0[2]; - union - { - unsigned short WORD; - struct - { - unsigned short RHST:3; - unsigned short :5; - unsigned short WKUP:1; - unsigned short :7; - } BIT; - } DVSTCTR0; - char wk1[2]; - union - { - unsigned short WORD; - struct - { - unsigned short UTST:4; - unsigned short :12; - } BIT; - } TESTMODE; - char wk2[2]; - union - { - unsigned short WORD; - struct - { - unsigned short :4; - unsigned short TENDE:1; - unsigned short :7; - unsigned short DFACC:2; - unsigned short :2; - } BIT; - } D0FBCFG; - union - { - unsigned short WORD; - struct - { - unsigned short :4; - unsigned short TENDE:1; - unsigned short :7; - unsigned short DFACC:2; - unsigned short :2; - } BIT; - } D1FBCFG; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } CFIFO; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D0FIFO; - union - { - unsigned long LONG; - struct - { - unsigned short H; - unsigned short L; - } WORD; - struct - { - unsigned char HH; - unsigned char HL; - unsigned char LH; - unsigned char LL; - } BYTE; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D1FIFO; - union - { - unsigned short WORD; - struct - { - unsigned short CURPIPE:4; - unsigned short :1; - unsigned short ISEL:1; - unsigned short :2; - unsigned short BIGEND:1; - unsigned short :1; - unsigned short MBW:2; - unsigned short :2; - unsigned short REW:1; - unsigned short RCNT:1; - } BIT; - } CFIFOSEL; - union - { - unsigned short WORD; - struct - { - unsigned short DTLN:12; - unsigned short :1; - unsigned short FRDY:1; - unsigned short BCLR:1; - unsigned short BVAL:1; - } BIT; - } CFIFOCTR; - char wk3[4]; - union - { - unsigned short WORD; - struct - { - unsigned short CURPIPE:4; - unsigned short :4; - unsigned short BIGEND:1; - unsigned short :1; - unsigned short MBW:2; - unsigned short DREQE:1; - unsigned short DCLRM:1; - unsigned short REW:1; - unsigned short RCNT:1; - } BIT; - } D0FIFOSEL; - union - { - unsigned short WORD; - struct - { - unsigned short DTLN:12; - unsigned short :1; - unsigned short FRDY:1; - unsigned short BCLR:1; - unsigned short BVAL:1; - } BIT; - } D0FIFOCTR; - union - { - unsigned short WORD; - struct - { - unsigned short CURPIPE:4; - unsigned short :4; - unsigned short BIGEND:1; - unsigned short :1; - unsigned short MBW:2; - unsigned short DREQE:1; - unsigned short DCLRM:1; - unsigned short REW:1; - unsigned short RCNT:1; - } BIT; - } D1FIFOSEL; - union - { - unsigned short WORD; - struct - { - unsigned short DTLN:12; - unsigned short :1; - unsigned short FRDY:1; - unsigned short BCLR:1; - unsigned short BVAL:1; - } BIT; - } D1FIFOCTR; - union - { - unsigned short WORD; - struct - { - unsigned short :8; - unsigned short BRDYE:1; - unsigned short NRDYE:1; - unsigned short BEMPE:1; - unsigned short CTRE:1; - unsigned short DVSE:1; - unsigned short SOFE:1; - unsigned short RSME:1; - unsigned short VBSE:1; - } BIT; - } INTENB0; - char wk4[4]; - union - { - unsigned short WORD; - struct - { - unsigned short PIPEBRDYE:10; - unsigned short :6; - } BIT; - } BRDYENB; - union - { - unsigned short WORD; - struct - { - unsigned short PIPENRDYE:10; - unsigned short :6; - } BIT; - } NRDYENB; - union - { - unsigned short WORD; - struct - { - unsigned short PIPEBEMPE:10; - unsigned short :6; - } BIT; - } BEMPENB; - union - { - unsigned short WORD; - struct - { - unsigned short :4; - unsigned short EDGESTS:1; - unsigned short INTL:1; - unsigned short BRDYM:1; - unsigned short :9; - } BIT; - } SOFCFG; - char wk5[2]; - union - { - unsigned short WORD; - struct - { - unsigned short CTSQ:3; - unsigned short VALID:1; - unsigned short DVSQ:3; - unsigned short VBSTS:1; - unsigned short BRDY:1; - unsigned short NRDY:1; - unsigned short BEMP:1; - unsigned short CTRT:1; - unsigned short DVST:1; - unsigned short SOFR:1; - unsigned short RESM:1; - unsigned short VBINT:1; - } BIT; - } INTSTS0; - char wk6[4]; - union - { - unsigned short WORD; - struct - { - unsigned short PIPEBRDY:10; - unsigned short :6; - } BIT; - } BRDYSTS; - union - { - unsigned short WORD; - struct - { - unsigned short PIPENRDY:10; - unsigned short :6; - } BIT; - } NRDYSTS; - union - { - unsigned short WORD; - struct - { - unsigned short PIPEBEMP:10; - unsigned short :6; - } BIT; - } BEMPSTS; - union - { - unsigned short WORD; - struct - { - unsigned short FRNM:11; - unsigned short :3; - unsigned short CRCE:1; - unsigned short OVRN:1; - } BIT; - } FRMNUM; - union - { - unsigned short WORD; - struct - { - unsigned short UFRNM:3; - unsigned short :13; - } BIT; - } UFRMNUM; - union - { - unsigned short WORD; - struct - { - unsigned short USBADDR:7; - unsigned short :9; - } BIT; - } USBADDR; - char wk7[2]; - union - { - unsigned short WORD; - struct - { - unsigned short bmRequestType:8; - unsigned short bRequest:8; - } BIT; - } USBREQ; - union - { - unsigned short WORD; - struct - { - unsigned short wValue:16; - } BIT; - } USBVAL; - union - { - unsigned short WORD; - struct - { - unsigned short wIndex:16; - } BIT; - } USBINDX; - union - { - unsigned short WORD; - struct - { - unsigned short wLength:16; - } BIT; - } USBLENG; - unsigned short DCPCFG; - union - { - unsigned short WORD; - struct - { - unsigned short MXPS:7; - unsigned short :9; - } BIT; - } DCPMAXP; - union - { - unsigned short WORD; - struct - { - unsigned short PID:2; - unsigned short CCPL:1; - unsigned short :2; - unsigned short PBUSY:1; - unsigned short SQMON:1; - unsigned short SQSET:1; - unsigned short SQCLR:1; - unsigned short :6; - unsigned short BSTS:1; - } BIT; - } DCPCTR; - char wk8[2]; - union - { - unsigned short WORD; - struct - { - unsigned short PIPESEL:4; - unsigned short :12; - } BIT; - } PIPESEL; - char wk9[2]; - union - { - unsigned short WORD; - struct - { - unsigned short EPNUM:4; - unsigned short DIR:1; - unsigned short :2; - unsigned short SHTNAK:1; - unsigned short CNTMD:1; - unsigned short DBLB:1; - unsigned short BFRE:1; - unsigned short :3; - unsigned short TYPE:2; - } BIT; - } PIPECFG; - union - { - unsigned short WORD; - struct - { - unsigned short BUFNMB:8; - unsigned short :2; - unsigned short BUFSIZE:5; - unsigned short :1; - } BIT; - } PIPEBUF; - union - { - unsigned short WORD; - struct - { - unsigned short MXPS:11; - unsigned short :5; - } BIT; - } PIPEMAXP; - union - { - unsigned short WORD; - struct - { - unsigned short IITV:3; - unsigned short :9; - unsigned short IFIS:1; - unsigned short :3; - } BIT; - } PIPEPERI; - union - { - unsigned short WORD; - struct - { - unsigned short PID:2; - unsigned short :3; - unsigned short PBUSY:1; - unsigned short SQMON:1; - unsigned short SQSET:1; - unsigned short SQCLR:1; - unsigned short ACLRM:1; - unsigned short ATREPM:1; - unsigned short :3; - unsigned short INBUFM:1; - unsigned short BSTS:1; - } BIT; - } PIPE1CTR; - union - { - unsigned short WORD; - struct - { - unsigned short PID:2; - unsigned short :3; - unsigned short PBUSY:1; - unsigned short SQMON:1; - unsigned short SQSET:1; - unsigned short SQCLR:1; - unsigned short ACLRM:1; - unsigned short ATREPM:1; - unsigned short :3; - unsigned short INBUFM:1; - unsigned short BSTS:1; - } BIT; - } PIPE2CTR; - union - { - unsigned short WORD; - struct - { - unsigned short PID:2; - unsigned short :3; - unsigned short PBUSY:1; - unsigned short SQMON:1; - unsigned short SQSET:1; - unsigned short SQCLR:1; - unsigned short ACLRM:1; - unsigned short ATREPM:1; - unsigned short :3; - unsigned short INBUFM:1; - unsigned short BSTS:1; - } BIT; - } PIPE3CTR; - union - { - unsigned short WORD; - struct - { - unsigned short PID:2; - unsigned short :3; - unsigned short PBUSY:1; - unsigned short SQMON:1; - unsigned short SQSET:1; - unsigned short SQCLR:1; - unsigned short ACLRM:1; - unsigned short ATREPM:1; - unsigned short :3; - unsigned short INBUFM:1; - unsigned short BSTS:1; - } BIT; - } PIPE4CTR; - union - { - unsigned short WORD; - struct - { - unsigned short PID:2; - unsigned short :3; - unsigned short PBUSY:1; - unsigned short SQMON:1; - unsigned short SQSET:1; - unsigned short SQCLR:1; - unsigned short ACLRM:1; - unsigned short ATREPM:1; - unsigned short :3; - unsigned short INBUFM:1; - unsigned short BSTS:1; - } BIT; - } PIPE5CTR; - union - { - unsigned short WORD; - struct - { - unsigned short PID:2; - unsigned short :3; - unsigned short PBUSY:1; - unsigned short SQMON:1; - unsigned short SQSET:1; - unsigned short SQCLR:1; - unsigned short ACLRM:1; - unsigned short :5; - unsigned short BSTS:1; - } BIT; - } PIPE6CTR; - union - { - unsigned short WORD; - struct - { - unsigned short PID:2; - unsigned short :3; - unsigned short PBUSY:1; - unsigned short SQMON:1; - unsigned short SQSET:1; - unsigned short SQCLR:1; - unsigned short ACLRM:1; - unsigned short :5; - unsigned short BSTS:1; - } BIT; - } PIPE7CTR; - union - { - unsigned short WORD; - struct - { - unsigned short PID:2; - unsigned short :3; - unsigned short PBUSY:1; - unsigned short SQMON:1; - unsigned short SQSET:1; - unsigned short SQCLR:1; - unsigned short ACLRM:1; - unsigned short :5; - unsigned short BSTS:1; - } BIT; - } PIPE8CTR; - union - { - unsigned short WORD; - struct - { - unsigned short PID:2; - unsigned short :3; - unsigned short PBUSY:1; - unsigned short SQMON:1; - unsigned short SQSET:1; - unsigned short SQCLR:1; - unsigned short ACLRM:1; - unsigned short :5; - unsigned short BSTS:1; - } BIT; - } PIPE9CTR; - char wk10[14]; - union - { - unsigned short WORD; - struct - { - unsigned short :8; - unsigned short TRCLR:1; - unsigned short TRENB:1; - unsigned short :6; - } BIT; - } PIPE1TRE; - union - { - unsigned short WORD; - struct - { - unsigned short TRNCNT:16; - } BIT; - } PIPE1TRN; - union - { - unsigned short WORD; - struct - { - unsigned short :8; - unsigned short TRCLR:1; - unsigned short TRENB:1; - unsigned short :6; - } BIT; - } PIPE2TRE; - union - { - unsigned short WORD; - struct - { - unsigned short TRNCNT:16; - } BIT; - } PIPE2TRN; - union - { - unsigned short WORD; - struct - { - unsigned short :8; - unsigned short TRCLR:1; - unsigned short TRENB:1; - unsigned short :6; - } BIT; - } PIPE3TRE; - union - { - unsigned short WORD; - struct - { - unsigned short TRNCNT:16; - } BIT; - } PIPE3TRN; - union - { - unsigned short WORD; - struct - { - unsigned short :8; - unsigned short TRCLR:1; - unsigned short TRENB:1; - unsigned short :6; - } BIT; - } PIPE4TRE; - union - { - unsigned short WORD; - struct - { - unsigned short TRNCNT:16; - } BIT; - } PIPE4TRN; - union - { - unsigned short WORD; - struct - { - unsigned short :8; - unsigned short TRCLR:1; - unsigned short TRENB:1; - unsigned short :6; - } BIT; - } PIPE5TRE; - union - { - unsigned short WORD; - struct - { - unsigned short TRNCNT:16; - } BIT; - } PIPE5TRN; - char wk11[92]; - unsigned short LPCTRL; - union - { - unsigned short WORD; - struct - { - unsigned short :14; - unsigned short SUSPM:1; - unsigned short :1; - } BIT; - } LPSTS; - unsigned short PHYFUNCTR; - char wk12[90]; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D0FIFOB0; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D0FIFOB1; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D0FIFOB2; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D0FIFOB3; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D0FIFOB4; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D0FIFOB5; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D0FIFOB6; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D0FIFOB7; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D1FIFOB0; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D1FIFOB1; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D1FIFOB2; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D1FIFOB3; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D1FIFOB4; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D1FIFOB5; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D1FIFOB6; - union - { - unsigned long LONG; - struct - { - unsigned long FIFOPORT:32; - } BIT; - } D1FIFOB7; - union - { - unsigned short WORD; - struct - { - unsigned short P1PORTSEL:2; - unsigned short PHYPD:1; - unsigned short PHYRESET:1; - unsigned short PHYVBUSIN:1; - unsigned short :11; - } BIT; - } PHYSET1; -}; - -struct st_usbh -{ - union - { - unsigned long LONG; - struct - { - unsigned long Revision:8; - unsigned long :24; - } BIT; - } HcRevision; - union - { - unsigned long LONG; - struct - { - unsigned long CBSR:2; - unsigned long PLE:1; - unsigned long IE:1; - unsigned long CLE:1; - unsigned long BLE:1; - unsigned long HCFS:2; - unsigned long :1; - unsigned long RWC:1; - unsigned long RWE:1; - unsigned long :21; - } BIT; - } HcControl; - union - { - unsigned long LONG; - struct - { - unsigned long HCR:1; - unsigned long CLF:1; - unsigned long BLF:1; - unsigned long OCR:1; - unsigned long :12; - unsigned long SOC:2; - unsigned long :14; - } BIT; - } HcCommandStatus; - union - { - unsigned long LONG; - struct - { - unsigned long SO:1; - unsigned long WDH:1; - unsigned long SF:1; - unsigned long RD:1; - unsigned long UE:1; - unsigned long FNO:1; - unsigned long RHSC:1; - unsigned long :25; - } BIT; - } HcIntStatus; - union - { - unsigned long LONG; - struct - { - unsigned long SOE:1; - unsigned long WDHE:1; - unsigned long SFE:1; - unsigned long RDE:1; - unsigned long UEE:1; - unsigned long FNOE:1; - unsigned long RHSCE:1; - unsigned long :24; - unsigned long MIE:1; - } BIT; - } HcIntEnable; - union - { - unsigned long LONG; - struct - { - unsigned long SOD:1; - unsigned long WDHD:1; - unsigned long SFD:1; - unsigned long RDD:1; - unsigned long UED:1; - unsigned long FNOD:1; - unsigned long RHSCD:1; - unsigned long :24; - unsigned long MID:1; - } BIT; - } HcIntDisable; - union - { - unsigned long LONG; - struct - { - unsigned long :8; - unsigned long HcHCCA:24; - } BIT; - } HcHCCA; - union - { - unsigned long LONG; - struct - { - unsigned long :4; - unsigned long PeriodicCurrentED:28; - } BIT; - } HcPeriodCurED; - union - { - unsigned long LONG; - struct - { - unsigned long :4; - unsigned long ControlHeadED:28; - } BIT; - } HcContHeadED; - union - { - unsigned long LONG; - struct - { - unsigned long :4; - unsigned long ControlCurrentED:28; - } BIT; - } HcContCurrentED; - union - { - unsigned long LONG; - struct - { - unsigned long :4; - unsigned long BulkHeadED:28; - } BIT; - } HcBulkHeadED; - union - { - unsigned long LONG; - struct - { - unsigned long :4; - unsigned long BulkCurrentED:28; - } BIT; - } HcBulkCurrentED; - union - { - unsigned long LONG; - struct - { - unsigned long :4; - unsigned long DoneHead:28; - } BIT; - } HcDoneHead; - union - { - unsigned long LONG; - struct - { - unsigned long FI:14; - unsigned long :2; - unsigned long FSMPS:15; - unsigned long FIT:1; - } BIT; - } HcFmInterval; - union - { - unsigned long LONG; - struct - { - unsigned long FR:14; - unsigned long :17; - unsigned long FRT:1; - } BIT; - } HcFmRemaining; - union - { - unsigned long LONG; - struct - { - unsigned long FrameNumber:16; - unsigned long :16; - } BIT; - } HcFmNumber; - union - { - unsigned long LONG; - struct - { - unsigned long PeriodicStart:14; - unsigned long :18; - } BIT; - } HcPeriodicStart; - union - { - unsigned long LONG; - struct - { - unsigned long HcLSThreshold:12; - unsigned long :20; - } BIT; - } HcLSThreshold; - union - { - unsigned long LONG; - struct - { - unsigned long NDP:8; - unsigned long PSM:1; - unsigned long NPS:1; - unsigned long DT:1; - unsigned long OCPM:1; - unsigned long NOCP:1; - unsigned long :11; - unsigned long POTPGT:8; - } BIT; - } HcRhDescriptorA; - union - { - unsigned long LONG; - struct - { - unsigned long DR:16; - unsigned long PPCM:16; - } BIT; - } HcRhDescriptorB; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long CGP:1; - unsigned long OCI:1; - unsigned long :13; - unsigned long SRWE:1; - unsigned long SGP:1; - unsigned long OCIC:1; - unsigned long :13; - unsigned long CRWE:1; - } BIT; - } HcRhStatus_A; - union - { - unsigned long LONG; - struct - { - unsigned long LPS:1; - unsigned long OCI:1; - unsigned long :13; - unsigned long DRWE:1; - unsigned long LPSC:1; - unsigned long OCIC:1; - unsigned long :13; - unsigned long CRWE:1; - } BIT; - } HcRhStatus_B; - } HcRhStatus; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long CPE:1; - unsigned long SPE:1; - unsigned long SPS:1; - unsigned long CSS:1; - unsigned long SPR:1; - unsigned long :3; - unsigned long SPP:1; - unsigned long CPP:1; - unsigned long :6; - unsigned long CSC:1; - unsigned long PESC:1; - unsigned long PSSC:1; - unsigned long OCIC:1; - unsigned long PRSC:1; - unsigned long :11; - } BIT; - } HcRhPortStatus1_A; - union - { - unsigned long LONG; - struct - { - unsigned long CCS:1; - unsigned long PES:1; - unsigned long PSS:1; - unsigned long POCI:1; - unsigned long PRS:1; - unsigned long :3; - unsigned long PPS:1; - unsigned long LSDA:1; - unsigned long :6; - unsigned long CSC:1; - unsigned long PESC:1; - unsigned long PSSC:1; - unsigned long OCIC:1; - unsigned long PRSC:1; - unsigned long :11; - } BIT; - } HcRhPortStatus1_B; - } HcRhPortStatus1; - char wk0[4008]; - union - { - unsigned long LONG; - struct - { - unsigned long CapabilityRegistersLength:8; - unsigned long :8; - unsigned long InterfaceVersionNumber:16; - } BIT; - } CAPL_VERSION; - union - { - unsigned long LONG; - struct - { - unsigned long N_PORTS:4; - unsigned long PPC:1; - unsigned long :2; - unsigned long PortRoutingRules:1; - unsigned long N_PCC:4; - unsigned long N_CC:4; - unsigned long P_INDICATOR:1; - unsigned long :3; - unsigned long DebugPortNumber:4; - unsigned long :8; - } BIT; - } HCSPARAMS; - union - { - unsigned long LONG; - struct - { - unsigned long AC64:1; - unsigned long PFLF:1; - unsigned long ASPC:1; - unsigned long :1; - unsigned long IST:4; - unsigned long EECP:8; - unsigned long :16; - } BIT; - } HCCPARAMS; - union - { - unsigned long LONG; - struct - { - unsigned long CompanionPortRoute:32; - } BIT; - } HCSP_PORTROUTE; - char wk1[16]; - union - { - unsigned long LONG; - struct - { - unsigned long RS:1; - unsigned long HCRESET:1; - unsigned long FrameListSize:2; - unsigned long PeriodicScheduleEnable:1; - unsigned long ASPME:1; - unsigned long InterruptonAsyncAdvanceDoorbell:1; - unsigned long LightHostControllerReset:1; - unsigned long ASPMC:2; - unsigned long :1; - unsigned long AsynchronousScheduleParkModeEnable:1; - unsigned long :4; - unsigned long InterruptThresholdControl:8; - unsigned long :8; - } BIT; - } USBCMD; - union - { - unsigned long LONG; - struct - { - unsigned long USBINT:1; - unsigned long USBERRINT:1; - unsigned long PortChangeDetect:1; - unsigned long FrameListRollover:1; - unsigned long HostSystemError:1; - unsigned long InterruptonAsyncAdvance:1; - unsigned long :6; - unsigned long HCHalted:1; - unsigned long Reclamation:1; - unsigned long PeriodicScheduleStatus:1; - unsigned long AsynchronousScheduleStatus:1; - unsigned long :16; - } BIT; - } USBSTS; - union - { - unsigned long LONG; - struct - { - unsigned long USBInterruptEnable:1; - unsigned long USBErrorInterruptEnable:1; - unsigned long PortChangeInterruptEnable:1; - unsigned long FrameListRolloverEnable:1; - unsigned long HostSystemErrorEnable:1; - unsigned long InterruptonAsyncAdvanceEnable:1; - unsigned long :26; - } BIT; - } USBINTR; - union - { - unsigned long LONG; - struct - { - unsigned long FrameIndex:14; - unsigned long :18; - } BIT; - } FRINDEX; - union - { - unsigned long LONG; - struct - { - unsigned long CTRLDSSEGMENT:32; - } BIT; - } CTRLDSSEGMENT; - union - { - unsigned long LONG; - struct - { - unsigned long :12; - unsigned long BaseAddressLow:20; - } BIT; - } PERIODICLIST; - union - { - unsigned long LONG; - struct - { - unsigned long :5; - unsigned long LPL:27; - } BIT; - } ASYNCLISTADDR; - char wk2[36]; - union - { - unsigned long LONG; - struct - { - unsigned long CF:1; - unsigned long :31; - } BIT; - } CONFIGFLAG; - union - { - unsigned long LONG; - struct - { - unsigned long CurrentConnectStatus:1; - unsigned long ConnectStatusChange:1; - unsigned long PortEnabledDisabled:1; - unsigned long PortEnableDisableChange:1; - unsigned long OvercurrentActive:1; - unsigned long OvercurrentChange:1; - unsigned long ForcePortResume:1; - unsigned long Suspend:1; - unsigned long PortReset:1; - unsigned long :1; - unsigned long LineStatus:2; - unsigned long PP:1; - unsigned long PortOwner:1; - unsigned long PortIndicatorControl:2; - unsigned long PortTestControl:4; - unsigned long WKCNNT_E:1; - unsigned long WKDSCNNT_E:1; - unsigned long WKOC_E:1; - unsigned long :9; - } BIT; - } PORTSC1; - char wk3[61336]; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long VendorID:16; - unsigned long DeviceID:16; - } BIT; - } VID_DID_O; - union - { - unsigned long LONG; - struct - { - unsigned long VENDOR_ID:16; - unsigned long DEVICE_ID:16; - } BIT; - } VID_DID_A; - } VID_DID; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long IOSpace:1; - unsigned long MemorySpace:1; - unsigned long BusMaster:1; - unsigned long SpecialCycle:1; - unsigned long MemoryWriteandInvalidateEnable:1; - unsigned long VGAPaletteSnoop:1; - unsigned long ParityErrorResponse:1; - unsigned long WaitCycleControl:1; - unsigned long SERREnable:1; - unsigned long FastBacktoBackEnable:1; - unsigned long :10; - unsigned long CapabilitiesList:1; - unsigned long :2; - unsigned long FastBacktoBackCapable:1; - unsigned long DataParityErrorDetected:1; - unsigned long DevselTiming:2; - unsigned long SignaledTargetAbort:1; - unsigned long ReceivedTargetAbort:1; - unsigned long ReceivedMasterAbort:1; - unsigned long SignaledSystemError:1; - unsigned long DetectedParityError:1; - } BIT; - } CMND_STS_O; - union - { - unsigned long LONG; - struct - { - unsigned long IOEN:1; - unsigned long MEMEN:1; - unsigned long MASTEREN:1; - unsigned long SPECIALC:1; - unsigned long MWINVEN:1; - unsigned long VGAPSNP:1; - unsigned long PERREN:1; - unsigned long STEPCTR:1; - unsigned long SERREN:1; - unsigned long FBTBEN:1; - unsigned long :10; - unsigned long CAPLIST:1; - unsigned long CAP66M:1; - unsigned long :1; - unsigned long FBTBCAP:1; - unsigned long MDPERR:1; - unsigned long DEVTIM:2; - unsigned long SIGTABORT:1; - unsigned long RETABORT:1; - unsigned long REMABORT:1; - unsigned long SIGSERR:1; - unsigned long DETPERR:1; - } BIT; - } CMND_STS_A; - } CMND_STS; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long RevisionID:8; - unsigned long ProgrammingIF:8; - unsigned long SubClass:8; - unsigned long BaseClass:8; - } BIT; - } REVID_CC_O; - union - { - unsigned long LONG; - struct - { - unsigned long REVISION_ID:8; - unsigned long CLASS_CODE:24; - } BIT; - } REVID_CC_A; - } REVID_CC; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long CacheLineSize:8; - unsigned long LatencyTimer:8; - unsigned long HeaderType:8; - unsigned long BIST:8; - } BIT; - } CLS_LT_HT_BIST_O; - union - { - unsigned long LONG; - struct - { - unsigned long CACHE_LINE_SIZE:8; - unsigned long LATENCY_TIMER:8; - unsigned long HEADER_TYPE:8; - unsigned long BIST:8; - } BIT; - } CLS_LT_HT_BIST_A; - } CLS_LT_HT_BIST; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long MemorySpaceIndicator:1; - unsigned long Type:2; - unsigned long Prefetchable:1; - unsigned long OHCIBaseAddress:28; - } BIT; - } BASEAD_O; - union - { - unsigned long LONG; - struct - { - unsigned long MEM:1; - unsigned long TYPE:2; - unsigned long PREFETCH:1; - unsigned long :6; - unsigned long PCICOM_BASEADR:22; - } BIT; - } BASEAD_A; - } BASEAD; - union - { - unsigned long LONG; - struct - { - unsigned long MEM:1; - unsigned long TYPE:2; - unsigned long PREFETCH:1; - unsigned long :24; - unsigned long PCI_WIN1_BASEADR:4; - } BIT; - } WIN1_BASEAD; - char wk4[20]; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long SubsystemVendorID:16; - unsigned long SubsystemID:16; - } BIT; - } SSVID_SSID_O; - union - { - unsigned long LONG; - struct - { - unsigned long SUBSYS_VENDOR_ID:16; - unsigned long SUBSYS_ID:16; - } BIT; - } SSVID_SSID_A; - } SSVID_SSID; - union - { - unsigned long LONG; - struct - { - unsigned long ROMDecodeEnable:1; - unsigned long :9; - unsigned long ExpansionROMBaseAddress:22; - } BIT; - } EROM_BASEAD; - union - { - unsigned long LONG; - struct - { - unsigned long CapabilityPointer:8; - unsigned long :24; - } BIT; - } CAPPTR; - char wk5[4]; - union - { - union - { - unsigned long LONG; - struct - { - unsigned long InterruptLine:8; - unsigned long InterruptPin:8; - unsigned long MINGnt:8; - unsigned long MaxLatency:8; - } BIT; - } INTR_LINE_PIN_O; - union - { - unsigned long LONG; - struct - { - unsigned long INT_LINE:8; - unsigned long INT_PIN:8; - unsigned long MIN_GNT:8; - unsigned long MAX_LAT:8; - } BIT; - } INTR_LINE_PIN_A; - } INTR_LINE_PIN; - union - { - unsigned long LONG; - struct - { - unsigned long CapabilityIdentifier:8; - unsigned long NextItemPointer:8; - unsigned long Version:3; - unsigned long PMECLK:1; - unsigned long :1; - unsigned long DSI:1; - unsigned long AUXCurrent:3; - unsigned long D1Support:1; - unsigned long D2Support:1; - unsigned long PMESupport:5; - } BIT; - } CAPID_NIP_PMCAP; - union - { - unsigned long LONG; - struct - { - unsigned long PowerState:2; - unsigned long :6; - unsigned long PMEEnable:1; - unsigned long DataSelect:4; - unsigned long DataScale:2; - unsigned long PMEStatus:1; - unsigned long :6; - unsigned long B2_B3:1; - unsigned long BPCCEnable:1; - unsigned long Data:8; - } BIT; - } PMC_STS_PMCSR; - char wk6[152]; - union - { - unsigned long LONG; - struct - { - unsigned long Port_no:2; - unsigned long :5; - unsigned long ID_Write_Enable:1; - unsigned long :5; - unsigned long HyperSpeedtransferControl1:1; - unsigned long :5; - unsigned long HyperSpeedtransferControl2:5; - unsigned long potpgt:8; - } BIT; - } EXT1; - union - { - unsigned long LONG; - struct - { - unsigned long EHCI_mask:1; - unsigned long HyperSpeedtransferControl3:1; - unsigned long :14; - unsigned long RUNRAMConnectCheck:1; - unsigned long RAMConnectCheckENDFlag:1; - unsigned long RAMConnectCheckResult:1; - unsigned long :13; - } BIT; - } EXT2; - char wk7[24]; - union - { - unsigned long LONG; - struct - { - unsigned long VendorID:16; - unsigned long DeviceID:16; - } BIT; - } VID_DID_E; - union - { - unsigned long LONG; - struct - { - unsigned long IOSpace:1; - unsigned long MemorySpace:1; - unsigned long BusMaster:1; - unsigned long SpecialCycle:1; - unsigned long MemoryWriteandInvalidateEnable:1; - unsigned long VGAPaletteSnoop:1; - unsigned long ParityErrorResponse:1; - unsigned long WaitCycleControl:1; - unsigned long SERREnable:1; - unsigned long FastBacktoBackEnable:1; - unsigned long :10; - unsigned long CapabilitiesList:1; - unsigned long Capable66MHz:1; - unsigned long :1; - unsigned long FastBacktoBackCapable:1; - unsigned long DataParityErrorDetected:1; - unsigned long DevselTiming:2; - unsigned long SignaledTargetAbort:1; - unsigned long ReceivedTargetAbort:1; - unsigned long ReceivedMasterAbort:1; - unsigned long SignaledSystemError:1; - unsigned long DetectedParityError:1; - } BIT; - } CMND_STS_E; - union - { - unsigned long LONG; - struct - { - unsigned long RevisionID:8; - unsigned long ProgrammingIF:8; - unsigned long SubClass:8; - unsigned long BaseClass:8; - } BIT; - } REVID_CC_E; - union - { - unsigned long LONG; - struct - { - unsigned long CacheLineSize:8; - unsigned long LatencyTimer:8; - unsigned long HeaderType:8; - unsigned long BIST:8; - } BIT; - } CLS_LT_HT_BIST_E; - union - { - unsigned long LONG; - struct - { - unsigned long MemorySpaceIndicator:1; - unsigned long Type:2; - unsigned long Prefetchable:1; - unsigned long EHCIBaseAddress:28; - } BIT; - } BASEAD_E; - char wk8[24]; - union - { - unsigned long LONG; - struct - { - unsigned long SubsystemVendorID:16; - unsigned long SubsystemID:16; - } BIT; - } SSVID_SSID_E; - union - { - unsigned long LONG; - struct - { - unsigned long ROMDecodeEnable:1; - unsigned long :9; - unsigned long ExpansionROMBaseAddress:22; - } BIT; - } EROM_BASEAD_E; - union - { - unsigned long LONG; - struct - { - unsigned long CapabilityPointer:8; - unsigned long :24; - } BIT; - } CAPPTR_E; - char wk9[4]; - union - { - unsigned long LONG; - struct - { - unsigned long InterruptLine:8; - unsigned long InterruptPin:8; - unsigned long MinGnt:8; - unsigned long MaxLatency:8; - } BIT; - } INTR_LINE_PIN_E; - union - { - unsigned long LONG; - struct - { - unsigned long CapabilityIdentifier:8; - unsigned long NextItemPointer:8; - unsigned long Version:3; - unsigned long PMECLK:1; - unsigned long :1; - unsigned long DSI:1; - unsigned long AUXCurrent:3; - unsigned long D1Support:1; - unsigned long D2Support:1; - unsigned long PMESupport:5; - } BIT; - } CAPID_NIP_PMCAP_E; - union - { - unsigned long LONG; - struct - { - unsigned long PowerState:2; - unsigned long :6; - unsigned long PMEEnable:1; - unsigned long DataSelect:4; - unsigned long DataScale:2; - unsigned long PMEStatus:1; - unsigned long :6; - unsigned long B2_B3:1; - unsigned long BPCCEnable:1; - unsigned long Data:8; - } BIT; - } PMC_STS_PMCSR_E; - char wk10[24]; - union - { - unsigned long LONG; - struct - { - unsigned long SBRN:8; - unsigned long FLADJ:8; - unsigned long PORTWAKECAP:16; - } BIT; - } SBRN_FLADJ_PW; - char wk11[124]; - unsigned long EXT1_E; - unsigned long EXT2_E; - char wk12[1560]; - union - { - unsigned long LONG; - struct - { - unsigned long PREFETCH:2; - unsigned long :26; - unsigned long AHB_BASEADR:4; - } BIT; - } PCIAHB_WIN1_CTR; - char wk13[12]; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long PCICMD:3; - unsigned long :7; - unsigned long PCIWIN1_BASEADR:21; - } BIT; - } AHBPCI_WIN1_CTR; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long PCICMD:3; - unsigned long :1; - unsigned long BURST_EN:1; - unsigned long :10; - unsigned long PCIWIN2_BASEADR:16; - } BIT; - } AHBPCI_WIN2_CTR; - char wk14[8]; - union - { - unsigned long LONG; - struct - { - unsigned long SIGTABORT_INTEN:1; - unsigned long RETABORT_INTEN:1; - unsigned long REMABORT_INTEN:1; - unsigned long PERR_INTEN:1; - unsigned long SIGSERR_INTEN:1; - unsigned long RESERR_INTEN:1; - unsigned long :6; - unsigned long PCIAHB_WIN1_INTEN:1; - unsigned long PCIAHB_WIN2_INTEN:1; - unsigned long :2; - unsigned long USBH_INTAEN:1; - unsigned long USBH_INTBEN:1; - unsigned long :1; - unsigned long USBH_PMEEN:1; - unsigned long :12; - } BIT; - } PCI_INT_ENABLE; - union - { - unsigned long LONG; - struct - { - unsigned long SIGTABORT_INT:1; - unsigned long RETABORT_INT:1; - unsigned long REMABORT_INT:1; - unsigned long PERR_INT:1; - unsigned long SIGSERR_INT:1; - unsigned long RESERR_INT:1; - unsigned long :6; - unsigned long PCIAHB_WIN1_INT:1; - unsigned long PCIAHB_WIN2_INT:1; - unsigned long :2; - unsigned long USBH_INTA:1; - unsigned long USBH_INTB:1; - unsigned long :1; - unsigned long USBH_PME:1; - unsigned long :12; - } BIT; - } PCI_INT_STATUS; - char wk15[8]; - union - { - unsigned long LONG; - struct - { - unsigned long MMODE_HTRANS:1; - unsigned long MMODE_BYTE_BURST:1; - unsigned long MMODE_WR_INCR:1; - unsigned long :4; - unsigned long MMODE_HBUSREQ:1; - unsigned long :9; - unsigned long SMODE_READY_CTR:1; - unsigned long :14; - } BIT; - } AHB_BUS_CTR; - union - { - unsigned long LONG; - struct - { - unsigned long USBH_RST:1; - unsigned long PCICLK_MASK:1; - unsigned long :7; - unsigned long PCI_AHB_WIN2_EN:1; - unsigned long PCI_AHB_WIN1_SIZE:2; - unsigned long :20; - } BIT; - } USBCTR; - char wk16[8]; - union - { - unsigned long LONG; - struct - { - unsigned long PCIREQ0:1; - unsigned long PCIREQ1:1; - unsigned long :10; - unsigned long PCIBP_MODE:1; - unsigned long :19; - } BIT; - } PCI_ARBITER_CTR; - char wk17[4]; - union - { - unsigned long LONG; - struct - { - unsigned long MinorRevisionID:16; - unsigned long MajorRevisionID:16; - } BIT; - } PCI_UNIT_REV; -}; - -struct st_vic -{ - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long IRQ1:1; - unsigned long IRQ2:1; - unsigned long IRQ3:1; - unsigned long IRQ4:1; - unsigned long IRQ5:1; - unsigned long IRQ6:1; - unsigned long IRQ7:1; - unsigned long IRQ8:1; - unsigned long IRQ9:1; - unsigned long IRQ10:1; - unsigned long IRQ11:1; - unsigned long IRQ12:1; - unsigned long IRQ13:1; - unsigned long IRQ14:1; - unsigned long IRQ15:1; - unsigned long IRQ16:1; - unsigned long IRQ17:1; - unsigned long IRQ18:1; - unsigned long IRQ19:1; - unsigned long IRQ20:1; - unsigned long IRQ21:1; - unsigned long IRQ22:1; - unsigned long IRQ23:1; - unsigned long IRQ24:1; - unsigned long IRQ25:1; - unsigned long IRQ26:1; - unsigned long IRQ27:1; - unsigned long IRQ28:1; - unsigned long IRQ29:1; - unsigned long IRQ30:1; - unsigned long IRQ31:1; - } BIT; - } IRQS0; - union - { - unsigned long LONG; - struct - { - unsigned long IRQ32:1; - unsigned long IRQ33:1; - unsigned long IRQ34:1; - unsigned long IRQ35:1; - unsigned long IRQ36:1; - unsigned long IRQ37:1; - unsigned long IRQ38:1; - unsigned long IRQ39:1; - unsigned long IRQ40:1; - unsigned long IRQ41:1; - unsigned long IRQ42:1; - unsigned long IRQ43:1; - unsigned long IRQ44:1; - unsigned long IRQ45:1; - unsigned long IRQ46:1; - unsigned long IRQ47:1; - unsigned long IRQ48:1; - unsigned long IRQ49:1; - unsigned long IRQ50:1; - unsigned long IRQ51:1; - unsigned long IRQ52:1; - unsigned long IRQ53:1; - unsigned long IRQ54:1; - unsigned long IRQ55:1; - unsigned long IRQ56:1; - unsigned long IRQ57:1; - unsigned long IRQ58:1; - unsigned long IRQ59:1; - unsigned long IRQ60:1; - unsigned long IRQ61:1; - unsigned long IRQ62:1; - unsigned long IRQ63:1; - } BIT; - } IRQS1; - union - { - unsigned long LONG; - struct - { - unsigned long IRQ64:1; - unsigned long IRQ65:1; - unsigned long IRQ66:1; - unsigned long IRQ67:1; - unsigned long IRQ68:1; - unsigned long IRQ69:1; - unsigned long IRQ70:1; - unsigned long IRQ71:1; - unsigned long IRQ72:1; - unsigned long IRQ73:1; - unsigned long IRQ74:1; - unsigned long IRQ75:1; - unsigned long IRQ76:1; - unsigned long IRQ77:1; - unsigned long IRQ78:1; - unsigned long IRQ79:1; - unsigned long IRQ80:1; - unsigned long IRQ81:1; - unsigned long IRQ82:1; - unsigned long IRQ83:1; - unsigned long IRQ84:1; - unsigned long IRQ85:1; - unsigned long IRQ86:1; - unsigned long IRQ87:1; - unsigned long IRQ88:1; - unsigned long IRQ89:1; - unsigned long IRQ90:1; - unsigned long IRQ91:1; - unsigned long IRQ92:1; - unsigned long IRQ93:1; - unsigned long IRQ94:1; - unsigned long IRQ95:1; - } BIT; - } IRQS2; - union - { - unsigned long LONG; - struct - { - unsigned long IRQ96:1; - unsigned long IRQ97:1; - unsigned long IRQ98:1; - unsigned long IRQ99:1; - unsigned long IRQ100:1; - unsigned long IRQ101:1; - unsigned long IRQ102:1; - unsigned long IRQ103:1; - unsigned long IRQ104:1; - unsigned long IRQ105:1; - unsigned long IRQ106:1; - unsigned long IRQ107:1; - unsigned long IRQ108:1; - unsigned long IRQ109:1; - unsigned long IRQ110:1; - unsigned long IRQ111:1; - unsigned long IRQ112:1; - unsigned long IRQ113:1; - unsigned long IRQ114:1; - unsigned long IRQ115:1; - unsigned long IRQ116:1; - unsigned long IRQ117:1; - unsigned long IRQ118:1; - unsigned long IRQ119:1; - unsigned long IRQ120:1; - unsigned long IRQ121:1; - unsigned long IRQ122:1; - unsigned long IRQ123:1; - unsigned long IRQ124:1; - unsigned long IRQ125:1; - unsigned long IRQ126:1; - unsigned long IRQ127:1; - } BIT; - } IRQS3; - union - { - unsigned long LONG; - struct - { - unsigned long IRQ128:1; - unsigned long IRQ129:1; - unsigned long IRQ130:1; - unsigned long IRQ131:1; - unsigned long IRQ132:1; - unsigned long IRQ133:1; - unsigned long IRQ134:1; - unsigned long IRQ135:1; - unsigned long IRQ136:1; - unsigned long IRQ137:1; - unsigned long IRQ138:1; - unsigned long IRQ139:1; - unsigned long IRQ140:1; - unsigned long IRQ141:1; - unsigned long IRQ142:1; - unsigned long IRQ143:1; - unsigned long IRQ144:1; - unsigned long IRQ145:1; - unsigned long IRQ146:1; - unsigned long IRQ147:1; - unsigned long IRQ148:1; - unsigned long IRQ149:1; - unsigned long IRQ150:1; - unsigned long IRQ151:1; - unsigned long IRQ152:1; - unsigned long IRQ153:1; - unsigned long IRQ154:1; - unsigned long IRQ155:1; - unsigned long IRQ156:1; - unsigned long IRQ157:1; - unsigned long IRQ158:1; - unsigned long IRQ159:1; - } BIT; - } IRQS4; - union - { - unsigned long LONG; - struct - { - unsigned long IRQ160:1; - unsigned long IRQ161:1; - unsigned long IRQ162:1; - unsigned long IRQ163:1; - unsigned long IRQ164:1; - unsigned long IRQ165:1; - unsigned long IRQ166:1; - unsigned long IRQ167:1; - unsigned long IRQ168:1; - unsigned long IRQ169:1; - unsigned long IRQ170:1; - unsigned long IRQ171:1; - unsigned long IRQ172:1; - unsigned long IRQ173:1; - unsigned long IRQ174:1; - unsigned long IRQ175:1; - unsigned long IRQ176:1; - unsigned long IRQ177:1; - unsigned long IRQ178:1; - unsigned long IRQ179:1; - unsigned long IRQ180:1; - unsigned long IRQ181:1; - unsigned long IRQ182:1; - unsigned long IRQ183:1; - unsigned long IRQ184:1; - unsigned long IRQ185:1; - unsigned long IRQ186:1; - unsigned long IRQ187:1; - unsigned long IRQ188:1; - unsigned long IRQ189:1; - unsigned long IRQ190:1; - unsigned long IRQ191:1; - } BIT; - } IRQS5; - union - { - unsigned long LONG; - struct - { - unsigned long IRQ192:1; - unsigned long IRQ193:1; - unsigned long IRQ194:1; - unsigned long IRQ195:1; - unsigned long IRQ196:1; - unsigned long IRQ197:1; - unsigned long IRQ198:1; - unsigned long IRQ199:1; - unsigned long IRQ200:1; - unsigned long IRQ201:1; - unsigned long IRQ202:1; - unsigned long IRQ203:1; - unsigned long IRQ204:1; - unsigned long IRQ205:1; - unsigned long IRQ206:1; - unsigned long IRQ207:1; - unsigned long IRQ208:1; - unsigned long IRQ209:1; - unsigned long IRQ210:1; - unsigned long IRQ211:1; - unsigned long IRQ212:1; - unsigned long IRQ213:1; - unsigned long IRQ214:1; - unsigned long IRQ215:1; - unsigned long IRQ216:1; - unsigned long IRQ217:1; - unsigned long IRQ218:1; - unsigned long IRQ219:1; - unsigned long IRQ220:1; - unsigned long IRQ221:1; - unsigned long IRQ222:1; - unsigned long IRQ223:1; - } BIT; - } IRQS6; - union - { - unsigned long LONG; - struct - { - unsigned long IRQ224:1; - unsigned long IRQ225:1; - unsigned long IRQ226:1; - unsigned long IRQ227:1; - unsigned long IRQ228:1; - unsigned long IRQ229:1; - unsigned long IRQ230:1; - unsigned long IRQ231:1; - unsigned long IRQ232:1; - unsigned long IRQ233:1; - unsigned long IRQ234:1; - unsigned long IRQ235:1; - unsigned long IRQ236:1; - unsigned long IRQ237:1; - unsigned long IRQ238:1; - unsigned long IRQ239:1; - unsigned long IRQ240:1; - unsigned long IRQ241:1; - unsigned long IRQ242:1; - unsigned long IRQ243:1; - unsigned long IRQ244:1; - unsigned long IRQ245:1; - unsigned long IRQ246:1; - unsigned long IRQ247:1; - unsigned long IRQ248:1; - unsigned long IRQ249:1; - unsigned long IRQ250:1; - unsigned long IRQ251:1; - unsigned long IRQ252:1; - unsigned long IRQ253:1; - unsigned long IRQ254:1; - unsigned long IRQ255:1; - } BIT; - } IRQS7; - char wk0[32]; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long RAI1:1; - unsigned long RAI2:1; - unsigned long RAI3:1; - unsigned long RAI4:1; - unsigned long RAI5:1; - unsigned long RAI6:1; - unsigned long RAI7:1; - unsigned long RAI8:1; - unsigned long RAI9:1; - unsigned long RAI10:1; - unsigned long RAI11:1; - unsigned long RAI12:1; - unsigned long RAI13:1; - unsigned long RAI14:1; - unsigned long RAI15:1; - unsigned long RAI16:1; - unsigned long RAI17:1; - unsigned long RAI18:1; - unsigned long RAI19:1; - unsigned long RAI20:1; - unsigned long RAI21:1; - unsigned long RAI22:1; - unsigned long RAI23:1; - unsigned long RAI24:1; - unsigned long RAI25:1; - unsigned long RAI26:1; - unsigned long RAI27:1; - unsigned long RAI28:1; - unsigned long RAI29:1; - unsigned long RAI30:1; - unsigned long RAI31:1; - } BIT; - } RAIS0; - union - { - unsigned long LONG; - struct - { - unsigned long RAI32:1; - unsigned long RAI33:1; - unsigned long RAI34:1; - unsigned long RAI35:1; - unsigned long RAI36:1; - unsigned long RAI37:1; - unsigned long RAI38:1; - unsigned long RAI39:1; - unsigned long RAI40:1; - unsigned long RAI41:1; - unsigned long RAI42:1; - unsigned long RAI43:1; - unsigned long RAI44:1; - unsigned long RAI45:1; - unsigned long RAI46:1; - unsigned long RAI47:1; - unsigned long RAI48:1; - unsigned long RAI49:1; - unsigned long RAI50:1; - unsigned long RAI51:1; - unsigned long RAI52:1; - unsigned long RAI53:1; - unsigned long RAI54:1; - unsigned long RAI55:1; - unsigned long RAI56:1; - unsigned long RAI57:1; - unsigned long RAI58:1; - unsigned long RAI59:1; - unsigned long RAI60:1; - unsigned long RAI61:1; - unsigned long RAI62:1; - unsigned long RAI63:1; - } BIT; - } RAIS1; - union - { - unsigned long LONG; - struct - { - unsigned long RAI64:1; - unsigned long RAI65:1; - unsigned long RAI66:1; - unsigned long RAI67:1; - unsigned long RAI68:1; - unsigned long RAI69:1; - unsigned long RAI70:1; - unsigned long RAI71:1; - unsigned long RAI72:1; - unsigned long RAI73:1; - unsigned long RAI74:1; - unsigned long RAI75:1; - unsigned long RAI76:1; - unsigned long RAI77:1; - unsigned long RAI78:1; - unsigned long RAI79:1; - unsigned long RAI80:1; - unsigned long RAI81:1; - unsigned long RAI82:1; - unsigned long RAI83:1; - unsigned long RAI84:1; - unsigned long RAI85:1; - unsigned long RAI86:1; - unsigned long RAI87:1; - unsigned long RAI88:1; - unsigned long RAI89:1; - unsigned long RAI90:1; - unsigned long RAI91:1; - unsigned long RAI92:1; - unsigned long RAI93:1; - unsigned long RAI94:1; - unsigned long RAI95:1; - } BIT; - } RAIS2; - union - { - unsigned long LONG; - struct - { - unsigned long RAI96:1; - unsigned long RAI97:1; - unsigned long RAI98:1; - unsigned long RAI99:1; - unsigned long RAI100:1; - unsigned long RAI101:1; - unsigned long RAI102:1; - unsigned long RAI103:1; - unsigned long RAI104:1; - unsigned long RAI105:1; - unsigned long RAI106:1; - unsigned long RAI107:1; - unsigned long RAI108:1; - unsigned long RAI109:1; - unsigned long RAI110:1; - unsigned long RAI111:1; - unsigned long RAI112:1; - unsigned long RAI113:1; - unsigned long RAI114:1; - unsigned long RAI115:1; - unsigned long RAI116:1; - unsigned long RAI117:1; - unsigned long RAI118:1; - unsigned long RAI119:1; - unsigned long RAI120:1; - unsigned long RAI121:1; - unsigned long RAI122:1; - unsigned long RAI123:1; - unsigned long RAI124:1; - unsigned long RAI125:1; - unsigned long RAI126:1; - unsigned long RAI127:1; - } BIT; - } RAIS3; - union - { - unsigned long LONG; - struct - { - unsigned long RAI128:1; - unsigned long RAI129:1; - unsigned long RAI130:1; - unsigned long RAI131:1; - unsigned long RAI132:1; - unsigned long RAI133:1; - unsigned long RAI134:1; - unsigned long RAI135:1; - unsigned long RAI136:1; - unsigned long RAI137:1; - unsigned long RAI138:1; - unsigned long RAI139:1; - unsigned long RAI140:1; - unsigned long RAI141:1; - unsigned long RAI142:1; - unsigned long RAI143:1; - unsigned long RAI144:1; - unsigned long RAI145:1; - unsigned long RAI146:1; - unsigned long RAI147:1; - unsigned long RAI148:1; - unsigned long RAI149:1; - unsigned long RAI150:1; - unsigned long RAI151:1; - unsigned long RAI152:1; - unsigned long RAI153:1; - unsigned long RAI154:1; - unsigned long RAI155:1; - unsigned long RAI156:1; - unsigned long RAI157:1; - unsigned long RAI158:1; - unsigned long RAI159:1; - } BIT; - } RAIS4; - union - { - unsigned long LONG; - struct - { - unsigned long RAI160:1; - unsigned long RAI161:1; - unsigned long RAI162:1; - unsigned long RAI163:1; - unsigned long RAI164:1; - unsigned long RAI165:1; - unsigned long RAI166:1; - unsigned long RAI167:1; - unsigned long RAI168:1; - unsigned long RAI169:1; - unsigned long RAI170:1; - unsigned long RAI171:1; - unsigned long RAI172:1; - unsigned long RAI173:1; - unsigned long RAI174:1; - unsigned long RAI175:1; - unsigned long RAI176:1; - unsigned long RAI177:1; - unsigned long RAI178:1; - unsigned long RAI179:1; - unsigned long RAI180:1; - unsigned long RAI181:1; - unsigned long RAI182:1; - unsigned long RAI183:1; - unsigned long RAI184:1; - unsigned long RAI185:1; - unsigned long RAI186:1; - unsigned long RAI187:1; - unsigned long RAI188:1; - unsigned long RAI189:1; - unsigned long RAI190:1; - unsigned long RAI191:1; - } BIT; - } RAIS5; - union - { - unsigned long LONG; - struct - { - unsigned long RAI192:1; - unsigned long RAI193:1; - unsigned long RAI194:1; - unsigned long RAI195:1; - unsigned long RAI196:1; - unsigned long RAI197:1; - unsigned long RAI198:1; - unsigned long RAI199:1; - unsigned long RAI200:1; - unsigned long RAI201:1; - unsigned long RAI202:1; - unsigned long RAI203:1; - unsigned long RAI204:1; - unsigned long RAI205:1; - unsigned long RAI206:1; - unsigned long RAI207:1; - unsigned long RAI208:1; - unsigned long RAI209:1; - unsigned long RAI210:1; - unsigned long RAI211:1; - unsigned long RAI212:1; - unsigned long RAI213:1; - unsigned long RAI214:1; - unsigned long RAI215:1; - unsigned long RAI216:1; - unsigned long RAI217:1; - unsigned long RAI218:1; - unsigned long RAI219:1; - unsigned long RAI220:1; - unsigned long RAI221:1; - unsigned long RAI222:1; - unsigned long RAI223:1; - } BIT; - } RAIS6; - union - { - unsigned long LONG; - struct - { - unsigned long RAI224:1; - unsigned long RAI225:1; - unsigned long RAI226:1; - unsigned long RAI227:1; - unsigned long RAI228:1; - unsigned long RAI229:1; - unsigned long RAI230:1; - unsigned long RAI231:1; - unsigned long RAI232:1; - unsigned long RAI233:1; - unsigned long RAI234:1; - unsigned long RAI235:1; - unsigned long RAI236:1; - unsigned long RAI237:1; - unsigned long RAI238:1; - unsigned long RAI239:1; - unsigned long RAI240:1; - unsigned long RAI241:1; - unsigned long RAI242:1; - unsigned long RAI243:1; - unsigned long RAI244:1; - unsigned long RAI245:1; - unsigned long RAI246:1; - unsigned long RAI247:1; - unsigned long RAI248:1; - unsigned long RAI249:1; - unsigned long RAI250:1; - unsigned long RAI251:1; - unsigned long RAI252:1; - unsigned long RAI253:1; - unsigned long RAI254:1; - unsigned long RAI255:1; - } BIT; - } RAIS7; - char wk1[32]; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long IEN1:1; - unsigned long IEN2:1; - unsigned long IEN3:1; - unsigned long IEN4:1; - unsigned long IEN5:1; - unsigned long IEN6:1; - unsigned long IEN7:1; - unsigned long IEN8:1; - unsigned long IEN9:1; - unsigned long IEN10:1; - unsigned long IEN11:1; - unsigned long IEN12:1; - unsigned long IEN13:1; - unsigned long IEN14:1; - unsigned long IEN15:1; - unsigned long IEN16:1; - unsigned long IEN17:1; - unsigned long IEN18:1; - unsigned long IEN19:1; - unsigned long IEN20:1; - unsigned long IEN21:1; - unsigned long IEN22:1; - unsigned long IEN23:1; - unsigned long IEN24:1; - unsigned long IEN25:1; - unsigned long IEN26:1; - unsigned long IEN27:1; - unsigned long IEN28:1; - unsigned long IEN29:1; - unsigned long IEN30:1; - unsigned long IEN31:1; - } BIT; - } IEN0; - union - { - unsigned long LONG; - struct - { - unsigned long IEN32:1; - unsigned long IEN33:1; - unsigned long IEN34:1; - unsigned long IEN35:1; - unsigned long IEN36:1; - unsigned long IEN37:1; - unsigned long IEN38:1; - unsigned long IEN39:1; - unsigned long IEN40:1; - unsigned long IEN41:1; - unsigned long IEN42:1; - unsigned long IEN43:1; - unsigned long IEN44:1; - unsigned long IEN45:1; - unsigned long IEN46:1; - unsigned long IEN47:1; - unsigned long IEN48:1; - unsigned long IEN49:1; - unsigned long IEN50:1; - unsigned long IEN51:1; - unsigned long IEN52:1; - unsigned long IEN53:1; - unsigned long IEN54:1; - unsigned long IEN55:1; - unsigned long IEN56:1; - unsigned long IEN57:1; - unsigned long IEN58:1; - unsigned long IEN59:1; - unsigned long IEN60:1; - unsigned long IEN61:1; - unsigned long IEN62:1; - unsigned long IEN63:1; - } BIT; - } IEN1; - union - { - unsigned long LONG; - struct - { - unsigned long IEN64:1; - unsigned long IEN65:1; - unsigned long IEN66:1; - unsigned long IEN67:1; - unsigned long IEN68:1; - unsigned long IEN69:1; - unsigned long IEN70:1; - unsigned long IEN71:1; - unsigned long IEN72:1; - unsigned long IEN73:1; - unsigned long IEN74:1; - unsigned long IEN75:1; - unsigned long IEN76:1; - unsigned long IEN77:1; - unsigned long IEN78:1; - unsigned long IEN79:1; - unsigned long IEN80:1; - unsigned long IEN81:1; - unsigned long IEN82:1; - unsigned long IEN83:1; - unsigned long IEN84:1; - unsigned long IEN85:1; - unsigned long IEN86:1; - unsigned long IEN87:1; - unsigned long IEN88:1; - unsigned long IEN89:1; - unsigned long IEN90:1; - unsigned long IEN91:1; - unsigned long IEN92:1; - unsigned long IEN93:1; - unsigned long IEN94:1; - unsigned long IEN95:1; - } BIT; - } IEN2; - union - { - unsigned long LONG; - struct - { - unsigned long IEN96:1; - unsigned long IEN97:1; - unsigned long IEN98:1; - unsigned long IEN99:1; - unsigned long IEN100:1; - unsigned long IEN101:1; - unsigned long IEN102:1; - unsigned long IEN103:1; - unsigned long IEN104:1; - unsigned long IEN105:1; - unsigned long IEN106:1; - unsigned long IEN107:1; - unsigned long IEN108:1; - unsigned long IEN109:1; - unsigned long IEN110:1; - unsigned long IEN111:1; - unsigned long IEN112:1; - unsigned long IEN113:1; - unsigned long IEN114:1; - unsigned long IEN115:1; - unsigned long IEN116:1; - unsigned long IEN117:1; - unsigned long IEN118:1; - unsigned long IEN119:1; - unsigned long IEN120:1; - unsigned long IEN121:1; - unsigned long IEN122:1; - unsigned long IEN123:1; - unsigned long IEN124:1; - unsigned long IEN125:1; - unsigned long IEN126:1; - unsigned long IEN127:1; - } BIT; - } IEN3; - union - { - unsigned long LONG; - struct - { - unsigned long IEN128:1; - unsigned long IEN129:1; - unsigned long IEN130:1; - unsigned long IEN131:1; - unsigned long IEN132:1; - unsigned long IEN133:1; - unsigned long IEN134:1; - unsigned long IEN135:1; - unsigned long IEN136:1; - unsigned long IEN137:1; - unsigned long IEN138:1; - unsigned long IEN139:1; - unsigned long IEN140:1; - unsigned long IEN141:1; - unsigned long IEN142:1; - unsigned long IEN143:1; - unsigned long IEN144:1; - unsigned long IEN145:1; - unsigned long IEN146:1; - unsigned long IEN147:1; - unsigned long IEN148:1; - unsigned long IEN149:1; - unsigned long IEN150:1; - unsigned long IEN151:1; - unsigned long IEN152:1; - unsigned long IEN153:1; - unsigned long IEN154:1; - unsigned long IEN155:1; - unsigned long IEN156:1; - unsigned long IEN157:1; - unsigned long IEN158:1; - unsigned long IEN159:1; - } BIT; - } IEN4; - union - { - unsigned long LONG; - struct - { - unsigned long IEN160:1; - unsigned long IEN161:1; - unsigned long IEN162:1; - unsigned long IEN163:1; - unsigned long IEN164:1; - unsigned long IEN165:1; - unsigned long IEN166:1; - unsigned long IEN167:1; - unsigned long IEN168:1; - unsigned long IEN169:1; - unsigned long IEN170:1; - unsigned long IEN171:1; - unsigned long IEN172:1; - unsigned long IEN173:1; - unsigned long IEN174:1; - unsigned long IEN175:1; - unsigned long IEN176:1; - unsigned long IEN177:1; - unsigned long IEN178:1; - unsigned long IEN179:1; - unsigned long IEN180:1; - unsigned long IEN181:1; - unsigned long IEN182:1; - unsigned long IEN183:1; - unsigned long IEN184:1; - unsigned long IEN185:1; - unsigned long IEN186:1; - unsigned long IEN187:1; - unsigned long IEN188:1; - unsigned long IEN189:1; - unsigned long IEN190:1; - unsigned long IEN191:1; - } BIT; - } IEN5; - union - { - unsigned long LONG; - struct - { - unsigned long IEN192:1; - unsigned long IEN193:1; - unsigned long IEN194:1; - unsigned long IEN195:1; - unsigned long IEN196:1; - unsigned long IEN197:1; - unsigned long IEN198:1; - unsigned long IEN199:1; - unsigned long IEN200:1; - unsigned long IEN201:1; - unsigned long IEN202:1; - unsigned long IEN203:1; - unsigned long IEN204:1; - unsigned long IEN205:1; - unsigned long IEN206:1; - unsigned long IEN207:1; - unsigned long IEN208:1; - unsigned long IEN209:1; - unsigned long IEN210:1; - unsigned long IEN211:1; - unsigned long IEN212:1; - unsigned long IEN213:1; - unsigned long IEN214:1; - unsigned long IEN215:1; - unsigned long IEN216:1; - unsigned long IEN217:1; - unsigned long IEN218:1; - unsigned long IEN219:1; - unsigned long IEN220:1; - unsigned long IEN221:1; - unsigned long IEN222:1; - unsigned long IEN223:1; - } BIT; - } IEN6; - union - { - unsigned long LONG; - struct - { - unsigned long IEN224:1; - unsigned long IEN225:1; - unsigned long IEN226:1; - unsigned long IEN227:1; - unsigned long IEN228:1; - unsigned long IEN229:1; - unsigned long IEN230:1; - unsigned long IEN231:1; - unsigned long IEN232:1; - unsigned long IEN233:1; - unsigned long IEN234:1; - unsigned long IEN235:1; - unsigned long IEN236:1; - unsigned long IEN237:1; - unsigned long IEN238:1; - unsigned long IEN239:1; - unsigned long IEN240:1; - unsigned long IEN241:1; - unsigned long IEN242:1; - unsigned long IEN243:1; - unsigned long IEN244:1; - unsigned long IEN245:1; - unsigned long IEN246:1; - unsigned long IEN247:1; - unsigned long IEN248:1; - unsigned long IEN249:1; - unsigned long IEN250:1; - unsigned long IEN251:1; - unsigned long IEN252:1; - unsigned long IEN253:1; - unsigned long IEN254:1; - unsigned long IEN255:1; - } BIT; - } IEN7; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long IEC1:1; - unsigned long IEC2:1; - unsigned long IEC3:1; - unsigned long IEC4:1; - unsigned long IEC5:1; - unsigned long IEC6:1; - unsigned long IEC7:1; - unsigned long IEC8:1; - unsigned long IEC9:1; - unsigned long IEC10:1; - unsigned long IEC11:1; - unsigned long IEC12:1; - unsigned long IEC13:1; - unsigned long IEC14:1; - unsigned long IEC15:1; - unsigned long IEC16:1; - unsigned long IEC17:1; - unsigned long IEC18:1; - unsigned long IEC19:1; - unsigned long IEC20:1; - unsigned long IEC21:1; - unsigned long IEC22:1; - unsigned long IEC23:1; - unsigned long IEC24:1; - unsigned long IEC25:1; - unsigned long IEC26:1; - unsigned long IEC27:1; - unsigned long IEC28:1; - unsigned long IEC29:1; - unsigned long IEC30:1; - unsigned long IEC31:1; - } BIT; - } IEC0; - union - { - unsigned long LONG; - struct - { - unsigned long IEC32:1; - unsigned long IEC33:1; - unsigned long IEC34:1; - unsigned long IEC35:1; - unsigned long IEC36:1; - unsigned long IEC37:1; - unsigned long IEC38:1; - unsigned long IEC39:1; - unsigned long IEC40:1; - unsigned long IEC41:1; - unsigned long IEC42:1; - unsigned long IEC43:1; - unsigned long IEC44:1; - unsigned long IEC45:1; - unsigned long IEC46:1; - unsigned long IEC47:1; - unsigned long IEC48:1; - unsigned long IEC49:1; - unsigned long IEC50:1; - unsigned long IEC51:1; - unsigned long IEC52:1; - unsigned long IEC53:1; - unsigned long IEC54:1; - unsigned long IEC55:1; - unsigned long IEC56:1; - unsigned long IEC57:1; - unsigned long IEC58:1; - unsigned long IEC59:1; - unsigned long IEC60:1; - unsigned long IEC61:1; - unsigned long IEC62:1; - unsigned long IEC63:1; - } BIT; - } IEC1; - union - { - unsigned long LONG; - struct - { - unsigned long IEC64:1; - unsigned long IEC65:1; - unsigned long IEC66:1; - unsigned long IEC67:1; - unsigned long IEC68:1; - unsigned long IEC69:1; - unsigned long IEC70:1; - unsigned long IEC71:1; - unsigned long IEC72:1; - unsigned long IEC73:1; - unsigned long IEC74:1; - unsigned long IEC75:1; - unsigned long IEC76:1; - unsigned long IEC77:1; - unsigned long IEC78:1; - unsigned long IEC79:1; - unsigned long IEC80:1; - unsigned long IEC81:1; - unsigned long IEC82:1; - unsigned long IEC83:1; - unsigned long IEC84:1; - unsigned long IEC85:1; - unsigned long IEC86:1; - unsigned long IEC87:1; - unsigned long IEC88:1; - unsigned long IEC89:1; - unsigned long IEC90:1; - unsigned long IEC91:1; - unsigned long IEC92:1; - unsigned long IEC93:1; - unsigned long IEC94:1; - unsigned long IEC95:1; - } BIT; - } IEC2; - union - { - unsigned long LONG; - struct - { - unsigned long IEC96:1; - unsigned long IEC97:1; - unsigned long IEC98:1; - unsigned long IEC99:1; - unsigned long IEC100:1; - unsigned long IEC101:1; - unsigned long IEC102:1; - unsigned long IEC103:1; - unsigned long IEC104:1; - unsigned long IEC105:1; - unsigned long IEC106:1; - unsigned long IEC107:1; - unsigned long IEC108:1; - unsigned long IEC109:1; - unsigned long IEC110:1; - unsigned long IEC111:1; - unsigned long IEC112:1; - unsigned long IEC113:1; - unsigned long IEC114:1; - unsigned long IEC115:1; - unsigned long IEC116:1; - unsigned long IEC117:1; - unsigned long IEC118:1; - unsigned long IEC119:1; - unsigned long IEC120:1; - unsigned long IEC121:1; - unsigned long IEC122:1; - unsigned long IEC123:1; - unsigned long IEC124:1; - unsigned long IEC125:1; - unsigned long IEC126:1; - unsigned long IEC127:1; - } BIT; - } IEC3; - union - { - unsigned long LONG; - struct - { - unsigned long IEC128:1; - unsigned long IEC129:1; - unsigned long IEC130:1; - unsigned long IEC131:1; - unsigned long IEC132:1; - unsigned long IEC133:1; - unsigned long IEC134:1; - unsigned long IEC135:1; - unsigned long IEC136:1; - unsigned long IEC137:1; - unsigned long IEC138:1; - unsigned long IEC139:1; - unsigned long IEC140:1; - unsigned long IEC141:1; - unsigned long IEC142:1; - unsigned long IEC143:1; - unsigned long IEC144:1; - unsigned long IEC145:1; - unsigned long IEC146:1; - unsigned long IEC147:1; - unsigned long IEC148:1; - unsigned long IEC149:1; - unsigned long IEC150:1; - unsigned long IEC151:1; - unsigned long IEC152:1; - unsigned long IEC153:1; - unsigned long IEC154:1; - unsigned long IEC155:1; - unsigned long IEC156:1; - unsigned long IEC157:1; - unsigned long IEC158:1; - unsigned long IEC159:1; - } BIT; - } IEC4; - union - { - unsigned long LONG; - struct - { - unsigned long IEC160:1; - unsigned long IEC161:1; - unsigned long IEC162:1; - unsigned long IEC163:1; - unsigned long IEC164:1; - unsigned long IEC165:1; - unsigned long IEC166:1; - unsigned long IEC167:1; - unsigned long IEC168:1; - unsigned long IEC169:1; - unsigned long IEC170:1; - unsigned long IEC171:1; - unsigned long IEC172:1; - unsigned long IEC173:1; - unsigned long IEC174:1; - unsigned long IEC175:1; - unsigned long IEC176:1; - unsigned long IEC177:1; - unsigned long IEC178:1; - unsigned long IEC179:1; - unsigned long IEC180:1; - unsigned long IEC181:1; - unsigned long IEC182:1; - unsigned long IEC183:1; - unsigned long IEC184:1; - unsigned long IEC185:1; - unsigned long IEC186:1; - unsigned long IEC187:1; - unsigned long IEC188:1; - unsigned long IEC189:1; - unsigned long IEC190:1; - unsigned long IEC191:1; - } BIT; - } IEC5; - union - { - unsigned long LONG; - struct - { - unsigned long IEC192:1; - unsigned long IEC193:1; - unsigned long IEC194:1; - unsigned long IEC195:1; - unsigned long IEC196:1; - unsigned long IEC197:1; - unsigned long IEC198:1; - unsigned long IEC199:1; - unsigned long IEC200:1; - unsigned long IEC201:1; - unsigned long IEC202:1; - unsigned long IEC203:1; - unsigned long IEC204:1; - unsigned long IEC205:1; - unsigned long IEC206:1; - unsigned long IEC207:1; - unsigned long IEC208:1; - unsigned long IEC209:1; - unsigned long IEC210:1; - unsigned long IEC211:1; - unsigned long IEC212:1; - unsigned long IEC213:1; - unsigned long IEC214:1; - unsigned long IEC215:1; - unsigned long IEC216:1; - unsigned long IEC217:1; - unsigned long IEC218:1; - unsigned long IEC219:1; - unsigned long IEC220:1; - unsigned long IEC221:1; - unsigned long IEC222:1; - unsigned long IEC223:1; - } BIT; - } IEC6; - union - { - unsigned long LONG; - struct - { - unsigned long IEC224:1; - unsigned long IEC225:1; - unsigned long IEC226:1; - unsigned long IEC227:1; - unsigned long IEC228:1; - unsigned long IEC229:1; - unsigned long IEC230:1; - unsigned long IEC231:1; - unsigned long IEC232:1; - unsigned long IEC233:1; - unsigned long IEC234:1; - unsigned long IEC235:1; - unsigned long IEC236:1; - unsigned long IEC237:1; - unsigned long IEC238:1; - unsigned long IEC239:1; - unsigned long IEC240:1; - unsigned long IEC241:1; - unsigned long IEC242:1; - unsigned long IEC243:1; - unsigned long IEC244:1; - unsigned long IEC245:1; - unsigned long IEC246:1; - unsigned long IEC247:1; - unsigned long IEC248:1; - unsigned long IEC249:1; - unsigned long IEC250:1; - unsigned long IEC251:1; - unsigned long IEC252:1; - unsigned long IEC253:1; - unsigned long IEC254:1; - unsigned long IEC255:1; - } BIT; - } IEC7; - char wk2[64]; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long PLS1:1; - unsigned long PLS2:1; - unsigned long PLS3:1; - unsigned long PLS4:1; - unsigned long PLS5:1; - unsigned long PLS6:1; - unsigned long PLS7:1; - unsigned long PLS8:1; - unsigned long PLS9:1; - unsigned long PLS10:1; - unsigned long PLS11:1; - unsigned long PLS12:1; - unsigned long PLS13:1; - unsigned long PLS14:1; - unsigned long PLS15:1; - unsigned long PLS16:1; - unsigned long PLS17:1; - unsigned long PLS18:1; - unsigned long PLS19:1; - unsigned long PLS20:1; - unsigned long PLS21:1; - unsigned long PLS22:1; - unsigned long PLS23:1; - unsigned long PLS24:1; - unsigned long PLS25:1; - unsigned long PLS26:1; - unsigned long PLS27:1; - unsigned long PLS28:1; - unsigned long PLS29:1; - unsigned long PLS30:1; - unsigned long PLS31:1; - } BIT; - } PLS0; - union - { - unsigned long LONG; - struct - { - unsigned long PLS32:1; - unsigned long PLS33:1; - unsigned long PLS34:1; - unsigned long PLS35:1; - unsigned long PLS36:1; - unsigned long PLS37:1; - unsigned long PLS38:1; - unsigned long PLS39:1; - unsigned long PLS40:1; - unsigned long PLS41:1; - unsigned long PLS42:1; - unsigned long PLS43:1; - unsigned long PLS44:1; - unsigned long PLS45:1; - unsigned long PLS46:1; - unsigned long PLS47:1; - unsigned long PLS48:1; - unsigned long PLS49:1; - unsigned long PLS50:1; - unsigned long PLS51:1; - unsigned long PLS52:1; - unsigned long PLS53:1; - unsigned long PLS54:1; - unsigned long PLS55:1; - unsigned long PLS56:1; - unsigned long PLS57:1; - unsigned long PLS58:1; - unsigned long PLS59:1; - unsigned long PLS60:1; - unsigned long PLS61:1; - unsigned long PLS62:1; - unsigned long PLS63:1; - } BIT; - } PLS1; - union - { - unsigned long LONG; - struct - { - unsigned long PLS64:1; - unsigned long PLS65:1; - unsigned long PLS66:1; - unsigned long PLS67:1; - unsigned long PLS68:1; - unsigned long PLS69:1; - unsigned long PLS70:1; - unsigned long PLS71:1; - unsigned long PLS72:1; - unsigned long PLS73:1; - unsigned long PLS74:1; - unsigned long PLS75:1; - unsigned long PLS76:1; - unsigned long PLS77:1; - unsigned long PLS78:1; - unsigned long PLS79:1; - unsigned long PLS80:1; - unsigned long PLS81:1; - unsigned long PLS82:1; - unsigned long PLS83:1; - unsigned long PLS84:1; - unsigned long PLS85:1; - unsigned long PLS86:1; - unsigned long PLS87:1; - unsigned long PLS88:1; - unsigned long PLS89:1; - unsigned long PLS90:1; - unsigned long PLS91:1; - unsigned long PLS92:1; - unsigned long PLS93:1; - unsigned long PLS94:1; - unsigned long PLS95:1; - } BIT; - } PLS2; - union - { - unsigned long LONG; - struct - { - unsigned long PLS96:1; - unsigned long PLS97:1; - unsigned long PLS98:1; - unsigned long PLS99:1; - unsigned long PLS100:1; - unsigned long PLS101:1; - unsigned long PLS102:1; - unsigned long PLS103:1; - unsigned long PLS104:1; - unsigned long PLS105:1; - unsigned long PLS106:1; - unsigned long PLS107:1; - unsigned long PLS108:1; - unsigned long PLS109:1; - unsigned long PLS110:1; - unsigned long PLS111:1; - unsigned long PLS112:1; - unsigned long PLS113:1; - unsigned long PLS114:1; - unsigned long PLS115:1; - unsigned long PLS116:1; - unsigned long PLS117:1; - unsigned long PLS118:1; - unsigned long PLS119:1; - unsigned long PLS120:1; - unsigned long PLS121:1; - unsigned long PLS122:1; - unsigned long PLS123:1; - unsigned long PLS124:1; - unsigned long PLS125:1; - unsigned long PLS126:1; - unsigned long PLS127:1; - } BIT; - } PLS3; - union - { - unsigned long LONG; - struct - { - unsigned long PLS128:1; - unsigned long PLS129:1; - unsigned long PLS130:1; - unsigned long PLS131:1; - unsigned long PLS132:1; - unsigned long PLS133:1; - unsigned long PLS134:1; - unsigned long PLS135:1; - unsigned long PLS136:1; - unsigned long PLS137:1; - unsigned long PLS138:1; - unsigned long PLS139:1; - unsigned long PLS140:1; - unsigned long PLS141:1; - unsigned long PLS142:1; - unsigned long PLS143:1; - unsigned long PLS144:1; - unsigned long PLS145:1; - unsigned long PLS146:1; - unsigned long PLS147:1; - unsigned long PLS148:1; - unsigned long PLS149:1; - unsigned long PLS150:1; - unsigned long PLS151:1; - unsigned long PLS152:1; - unsigned long PLS153:1; - unsigned long PLS154:1; - unsigned long PLS155:1; - unsigned long PLS156:1; - unsigned long PLS157:1; - unsigned long PLS158:1; - unsigned long PLS159:1; - } BIT; - } PLS4; - union - { - unsigned long LONG; - struct - { - unsigned long PLS160:1; - unsigned long PLS161:1; - unsigned long PLS162:1; - unsigned long PLS163:1; - unsigned long PLS164:1; - unsigned long PLS165:1; - unsigned long PLS166:1; - unsigned long PLS167:1; - unsigned long PLS168:1; - unsigned long PLS169:1; - unsigned long PLS170:1; - unsigned long PLS171:1; - unsigned long PLS172:1; - unsigned long PLS173:1; - unsigned long PLS174:1; - unsigned long PLS175:1; - unsigned long PLS176:1; - unsigned long PLS177:1; - unsigned long PLS178:1; - unsigned long PLS179:1; - unsigned long PLS180:1; - unsigned long PLS181:1; - unsigned long PLS182:1; - unsigned long PLS183:1; - unsigned long PLS184:1; - unsigned long PLS185:1; - unsigned long PLS186:1; - unsigned long PLS187:1; - unsigned long PLS188:1; - unsigned long PLS189:1; - unsigned long PLS190:1; - unsigned long PLS191:1; - } BIT; - } PLS5; - union - { - unsigned long LONG; - struct - { - unsigned long PLS192:1; - unsigned long PLS193:1; - unsigned long PLS194:1; - unsigned long PLS195:1; - unsigned long PLS196:1; - unsigned long PLS197:1; - unsigned long PLS198:1; - unsigned long PLS199:1; - unsigned long PLS200:1; - unsigned long PLS201:1; - unsigned long PLS202:1; - unsigned long PLS203:1; - unsigned long PLS204:1; - unsigned long PLS205:1; - unsigned long PLS206:1; - unsigned long PLS207:1; - unsigned long PLS208:1; - unsigned long PLS209:1; - unsigned long PLS210:1; - unsigned long PLS211:1; - unsigned long PLS212:1; - unsigned long PLS213:1; - unsigned long PLS214:1; - unsigned long PLS215:1; - unsigned long PLS216:1; - unsigned long PLS217:1; - unsigned long PLS218:1; - unsigned long PLS219:1; - unsigned long PLS220:1; - unsigned long PLS221:1; - unsigned long PLS222:1; - unsigned long PLS223:1; - } BIT; - } PLS6; - union - { - unsigned long LONG; - struct - { - unsigned long PLS224:1; - unsigned long PLS225:1; - unsigned long PLS226:1; - unsigned long PLS227:1; - unsigned long PLS228:1; - unsigned long PLS229:1; - unsigned long PLS230:1; - unsigned long PLS231:1; - unsigned long PLS232:1; - unsigned long PLS233:1; - unsigned long PLS234:1; - unsigned long PLS235:1; - unsigned long PLS236:1; - unsigned long PLS237:1; - unsigned long PLS238:1; - unsigned long PLS239:1; - unsigned long PLS240:1; - unsigned long PLS241:1; - unsigned long PLS242:1; - unsigned long PLS243:1; - unsigned long PLS244:1; - unsigned long PLS245:1; - unsigned long PLS246:1; - unsigned long PLS247:1; - unsigned long PLS248:1; - unsigned long PLS249:1; - unsigned long PLS250:1; - unsigned long PLS251:1; - unsigned long PLS252:1; - unsigned long PLS253:1; - unsigned long PLS254:1; - unsigned long PLS255:1; - } BIT; - } PLS7; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long PIC1:1; - unsigned long PIC2:1; - unsigned long PIC3:1; - unsigned long PIC4:1; - unsigned long PIC5:1; - unsigned long PIC6:1; - unsigned long PIC7:1; - unsigned long PIC8:1; - unsigned long PIC9:1; - unsigned long PIC10:1; - unsigned long PIC11:1; - unsigned long PIC12:1; - unsigned long PIC13:1; - unsigned long PIC14:1; - unsigned long PIC15:1; - unsigned long PIC16:1; - unsigned long PIC17:1; - unsigned long PIC18:1; - unsigned long PIC19:1; - unsigned long PIC20:1; - unsigned long PIC21:1; - unsigned long PIC22:1; - unsigned long PIC23:1; - unsigned long PIC24:1; - unsigned long PIC25:1; - unsigned long PIC26:1; - unsigned long PIC27:1; - unsigned long PIC28:1; - unsigned long PIC29:1; - unsigned long PIC30:1; - unsigned long PIC31:1; - } BIT; - } PIC0; - union - { - unsigned long LONG; - struct - { - unsigned long PIC32:1; - unsigned long PIC33:1; - unsigned long PIC34:1; - unsigned long PIC35:1; - unsigned long PIC36:1; - unsigned long PIC37:1; - unsigned long PIC38:1; - unsigned long PIC39:1; - unsigned long PIC40:1; - unsigned long PIC41:1; - unsigned long PIC42:1; - unsigned long PIC43:1; - unsigned long PIC44:1; - unsigned long PIC45:1; - unsigned long PIC46:1; - unsigned long PIC47:1; - unsigned long PIC48:1; - unsigned long PIC49:1; - unsigned long PIC50:1; - unsigned long PIC51:1; - unsigned long PIC52:1; - unsigned long PIC53:1; - unsigned long PIC54:1; - unsigned long PIC55:1; - unsigned long PIC56:1; - unsigned long PIC57:1; - unsigned long PIC58:1; - unsigned long PIC59:1; - unsigned long PIC60:1; - unsigned long PIC61:1; - unsigned long PIC62:1; - unsigned long PIC63:1; - } BIT; - } PIC1; - union - { - unsigned long LONG; - struct - { - unsigned long PIC64:1; - unsigned long PIC65:1; - unsigned long PIC66:1; - unsigned long PIC67:1; - unsigned long PIC68:1; - unsigned long PIC69:1; - unsigned long PIC70:1; - unsigned long PIC71:1; - unsigned long PIC72:1; - unsigned long PIC73:1; - unsigned long PIC74:1; - unsigned long PIC75:1; - unsigned long PIC76:1; - unsigned long PIC77:1; - unsigned long PIC78:1; - unsigned long PIC79:1; - unsigned long PIC80:1; - unsigned long PIC81:1; - unsigned long PIC82:1; - unsigned long PIC83:1; - unsigned long PIC84:1; - unsigned long PIC85:1; - unsigned long PIC86:1; - unsigned long PIC87:1; - unsigned long PIC88:1; - unsigned long PIC89:1; - unsigned long PIC90:1; - unsigned long PIC91:1; - unsigned long PIC92:1; - unsigned long PIC93:1; - unsigned long PIC94:1; - unsigned long PIC95:1; - } BIT; - } PIC2; - union - { - unsigned long LONG; - struct - { - unsigned long PIC96:1; - unsigned long PIC97:1; - unsigned long PIC98:1; - unsigned long PIC99:1; - unsigned long PIC100:1; - unsigned long PIC101:1; - unsigned long PIC102:1; - unsigned long PIC103:1; - unsigned long PIC104:1; - unsigned long PIC105:1; - unsigned long PIC106:1; - unsigned long PIC107:1; - unsigned long PIC108:1; - unsigned long PIC109:1; - unsigned long PIC110:1; - unsigned long PIC111:1; - unsigned long PIC112:1; - unsigned long PIC113:1; - unsigned long PIC114:1; - unsigned long PIC115:1; - unsigned long PIC116:1; - unsigned long PIC117:1; - unsigned long PIC118:1; - unsigned long PIC119:1; - unsigned long PIC120:1; - unsigned long PIC121:1; - unsigned long PIC122:1; - unsigned long PIC123:1; - unsigned long PIC124:1; - unsigned long PIC125:1; - unsigned long PIC126:1; - unsigned long PIC127:1; - } BIT; - } PIC3; - union - { - unsigned long LONG; - struct - { - unsigned long PIC128:1; - unsigned long PIC129:1; - unsigned long PIC130:1; - unsigned long PIC131:1; - unsigned long PIC132:1; - unsigned long PIC133:1; - unsigned long PIC134:1; - unsigned long PIC135:1; - unsigned long PIC136:1; - unsigned long PIC137:1; - unsigned long PIC138:1; - unsigned long PIC139:1; - unsigned long PIC140:1; - unsigned long PIC141:1; - unsigned long PIC142:1; - unsigned long PIC143:1; - unsigned long PIC144:1; - unsigned long PIC145:1; - unsigned long PIC146:1; - unsigned long PIC147:1; - unsigned long PIC148:1; - unsigned long PIC149:1; - unsigned long PIC150:1; - unsigned long PIC151:1; - unsigned long PIC152:1; - unsigned long PIC153:1; - unsigned long PIC154:1; - unsigned long PIC155:1; - unsigned long PIC156:1; - unsigned long PIC157:1; - unsigned long PIC158:1; - unsigned long PIC159:1; - } BIT; - } PIC4; - union - { - unsigned long LONG; - struct - { - unsigned long PIC160:1; - unsigned long PIC161:1; - unsigned long PIC162:1; - unsigned long PIC163:1; - unsigned long PIC164:1; - unsigned long PIC165:1; - unsigned long PIC166:1; - unsigned long PIC167:1; - unsigned long PIC168:1; - unsigned long PIC169:1; - unsigned long PIC170:1; - unsigned long PIC171:1; - unsigned long PIC172:1; - unsigned long PIC173:1; - unsigned long PIC174:1; - unsigned long PIC175:1; - unsigned long PIC176:1; - unsigned long PIC177:1; - unsigned long PIC178:1; - unsigned long PIC179:1; - unsigned long PIC180:1; - unsigned long PIC181:1; - unsigned long PIC182:1; - unsigned long PIC183:1; - unsigned long PIC184:1; - unsigned long PIC185:1; - unsigned long PIC186:1; - unsigned long PIC187:1; - unsigned long PIC188:1; - unsigned long PIC189:1; - unsigned long PIC190:1; - unsigned long PIC191:1; - } BIT; - } PIC5; - union - { - unsigned long LONG; - struct - { - unsigned long PIC192:1; - unsigned long PIC193:1; - unsigned long PIC194:1; - unsigned long PIC195:1; - unsigned long PIC196:1; - unsigned long PIC197:1; - unsigned long PIC198:1; - unsigned long PIC199:1; - unsigned long PIC200:1; - unsigned long PIC201:1; - unsigned long PIC202:1; - unsigned long PIC203:1; - unsigned long PIC204:1; - unsigned long PIC205:1; - unsigned long PIC206:1; - unsigned long PIC207:1; - unsigned long PIC208:1; - unsigned long PIC209:1; - unsigned long PIC210:1; - unsigned long PIC211:1; - unsigned long PIC212:1; - unsigned long PIC213:1; - unsigned long PIC214:1; - unsigned long PIC215:1; - unsigned long PIC216:1; - unsigned long PIC217:1; - unsigned long PIC218:1; - unsigned long PIC219:1; - unsigned long PIC220:1; - unsigned long PIC221:1; - unsigned long PIC222:1; - unsigned long PIC223:1; - } BIT; - } PIC6; - union - { - unsigned long LONG; - struct - { - unsigned long PIC224:1; - unsigned long PIC225:1; - unsigned long PIC226:1; - unsigned long PIC227:1; - unsigned long PIC228:1; - unsigned long PIC229:1; - unsigned long PIC230:1; - unsigned long PIC231:1; - unsigned long PIC232:1; - unsigned long PIC233:1; - unsigned long PIC234:1; - unsigned long PIC235:1; - unsigned long PIC236:1; - unsigned long PIC237:1; - unsigned long PIC238:1; - unsigned long PIC239:1; - unsigned long PIC240:1; - unsigned long PIC241:1; - unsigned long PIC242:1; - unsigned long PIC243:1; - unsigned long PIC244:1; - unsigned long PIC245:1; - unsigned long PIC246:1; - unsigned long PIC247:1; - unsigned long PIC248:1; - unsigned long PIC249:1; - unsigned long PIC250:1; - unsigned long PIC251:1; - unsigned long PIC252:1; - unsigned long PIC253:1; - unsigned long PIC254:1; - unsigned long PIC255:1; - } BIT; - } PIC7; - char wk3[128]; - union - { - unsigned long LONG; - struct - { - unsigned long PRLM0:1; - unsigned long PRLM1:1; - unsigned long PRLM2:1; - unsigned long PRLM3:1; - unsigned long PRLM4:1; - unsigned long PRLM5:1; - unsigned long PRLM6:1; - unsigned long PRLM7:1; - unsigned long PRLM8:1; - unsigned long PRLM9:1; - unsigned long PRLM10:1; - unsigned long PRLM11:1; - unsigned long PRLM12:1; - unsigned long PRLM13:1; - unsigned long PRLM14:1; - unsigned long PRLM15:1; - unsigned long :16; - } BIT; - } PRLM0; - union - { - unsigned long LONG; - struct - { - unsigned long PRLC0:1; - unsigned long PRLC1:1; - unsigned long PRLC2:1; - unsigned long PRLC3:1; - unsigned long PRLC4:1; - unsigned long PRLC5:1; - unsigned long PRLC6:1; - unsigned long PRLC7:1; - unsigned long PRLC8:1; - unsigned long PRLC9:1; - unsigned long PRLC10:1; - unsigned long PRLC11:1; - unsigned long PRLC12:1; - unsigned long PRLC13:1; - unsigned long PRLC14:1; - unsigned long PRLC15:1; - unsigned long :16; - } BIT; - } PRLC0; - union - { - unsigned long LONG; - struct - { - unsigned long UE:1; - unsigned long :31; - } BIT; - } UEN0; - char wk4[52]; - union - { - unsigned long LONG; - } HVA0; - char wk5[12]; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long ISS1:1; - unsigned long ISS2:1; - unsigned long ISS3:1; - unsigned long ISS4:1; - unsigned long ISS5:1; - unsigned long ISS6:1; - unsigned long ISS7:1; - unsigned long ISS8:1; - unsigned long ISS9:1; - unsigned long ISS10:1; - unsigned long ISS11:1; - unsigned long ISS12:1; - unsigned long ISS13:1; - unsigned long ISS14:1; - unsigned long ISS15:1; - unsigned long ISS16:1; - unsigned long ISS17:1; - unsigned long ISS18:1; - unsigned long ISS19:1; - unsigned long ISS20:1; - unsigned long ISS21:1; - unsigned long ISS22:1; - unsigned long ISS23:1; - unsigned long ISS24:1; - unsigned long ISS25:1; - unsigned long ISS26:1; - unsigned long ISS27:1; - unsigned long ISS28:1; - unsigned long ISS29:1; - unsigned long ISS30:1; - unsigned long ISS31:1; - } BIT; - } ISS0; - union - { - unsigned long LONG; - struct - { - unsigned long ISS32:1; - unsigned long ISS33:1; - unsigned long ISS34:1; - unsigned long ISS35:1; - unsigned long ISS36:1; - unsigned long ISS37:1; - unsigned long ISS38:1; - unsigned long ISS39:1; - unsigned long ISS40:1; - unsigned long ISS41:1; - unsigned long ISS42:1; - unsigned long ISS43:1; - unsigned long ISS44:1; - unsigned long ISS45:1; - unsigned long ISS46:1; - unsigned long ISS47:1; - unsigned long ISS48:1; - unsigned long ISS49:1; - unsigned long ISS50:1; - unsigned long ISS51:1; - unsigned long ISS52:1; - unsigned long ISS53:1; - unsigned long ISS54:1; - unsigned long ISS55:1; - unsigned long ISS56:1; - unsigned long ISS57:1; - unsigned long ISS58:1; - unsigned long ISS59:1; - unsigned long ISS60:1; - unsigned long ISS61:1; - unsigned long ISS62:1; - unsigned long ISS63:1; - } BIT; - } ISS1; - union - { - unsigned long LONG; - struct - { - unsigned long ISS64:1; - unsigned long ISS65:1; - unsigned long ISS66:1; - unsigned long ISS67:1; - unsigned long ISS68:1; - unsigned long ISS69:1; - unsigned long ISS70:1; - unsigned long ISS71:1; - unsigned long ISS72:1; - unsigned long ISS73:1; - unsigned long ISS74:1; - unsigned long ISS75:1; - unsigned long ISS76:1; - unsigned long ISS77:1; - unsigned long ISS78:1; - unsigned long ISS79:1; - unsigned long ISS80:1; - unsigned long ISS81:1; - unsigned long ISS82:1; - unsigned long ISS83:1; - unsigned long ISS84:1; - unsigned long ISS85:1; - unsigned long ISS86:1; - unsigned long ISS87:1; - unsigned long ISS88:1; - unsigned long ISS89:1; - unsigned long ISS90:1; - unsigned long ISS91:1; - unsigned long ISS92:1; - unsigned long ISS93:1; - unsigned long ISS94:1; - unsigned long ISS95:1; - } BIT; - } ISS2; - union - { - unsigned long LONG; - struct - { - unsigned long ISS96:1; - unsigned long ISS97:1; - unsigned long ISS98:1; - unsigned long ISS99:1; - unsigned long ISS100:1; - unsigned long ISS101:1; - unsigned long ISS102:1; - unsigned long ISS103:1; - unsigned long ISS104:1; - unsigned long ISS105:1; - unsigned long ISS106:1; - unsigned long ISS107:1; - unsigned long ISS108:1; - unsigned long ISS109:1; - unsigned long ISS110:1; - unsigned long ISS111:1; - unsigned long ISS112:1; - unsigned long ISS113:1; - unsigned long ISS114:1; - unsigned long ISS115:1; - unsigned long ISS116:1; - unsigned long ISS117:1; - unsigned long ISS118:1; - unsigned long ISS119:1; - unsigned long ISS120:1; - unsigned long ISS121:1; - unsigned long ISS122:1; - unsigned long ISS123:1; - unsigned long ISS124:1; - unsigned long ISS125:1; - unsigned long ISS126:1; - unsigned long ISS127:1; - } BIT; - } ISS3; - union - { - unsigned long LONG; - struct - { - unsigned long ISS128:1; - unsigned long ISS129:1; - unsigned long ISS130:1; - unsigned long ISS131:1; - unsigned long ISS132:1; - unsigned long ISS133:1; - unsigned long ISS134:1; - unsigned long ISS135:1; - unsigned long ISS136:1; - unsigned long ISS137:1; - unsigned long ISS138:1; - unsigned long ISS139:1; - unsigned long ISS140:1; - unsigned long ISS141:1; - unsigned long ISS142:1; - unsigned long ISS143:1; - unsigned long ISS144:1; - unsigned long ISS145:1; - unsigned long ISS146:1; - unsigned long ISS147:1; - unsigned long ISS148:1; - unsigned long ISS149:1; - unsigned long ISS150:1; - unsigned long ISS151:1; - unsigned long ISS152:1; - unsigned long ISS153:1; - unsigned long ISS154:1; - unsigned long ISS155:1; - unsigned long ISS156:1; - unsigned long ISS157:1; - unsigned long ISS158:1; - unsigned long ISS159:1; - } BIT; - } ISS4; - union - { - unsigned long LONG; - struct - { - unsigned long ISS160:1; - unsigned long ISS161:1; - unsigned long ISS162:1; - unsigned long ISS163:1; - unsigned long ISS164:1; - unsigned long ISS165:1; - unsigned long ISS166:1; - unsigned long ISS167:1; - unsigned long ISS168:1; - unsigned long ISS169:1; - unsigned long ISS170:1; - unsigned long ISS171:1; - unsigned long ISS172:1; - unsigned long ISS173:1; - unsigned long ISS174:1; - unsigned long ISS175:1; - unsigned long ISS176:1; - unsigned long ISS177:1; - unsigned long ISS178:1; - unsigned long ISS179:1; - unsigned long ISS180:1; - unsigned long ISS181:1; - unsigned long ISS182:1; - unsigned long ISS183:1; - unsigned long ISS184:1; - unsigned long ISS185:1; - unsigned long ISS186:1; - unsigned long ISS187:1; - unsigned long ISS188:1; - unsigned long ISS189:1; - unsigned long ISS190:1; - unsigned long ISS191:1; - } BIT; - } ISS5; - union - { - unsigned long LONG; - struct - { - unsigned long ISS192:1; - unsigned long ISS193:1; - unsigned long ISS194:1; - unsigned long ISS195:1; - unsigned long ISS196:1; - unsigned long ISS197:1; - unsigned long ISS198:1; - unsigned long ISS199:1; - unsigned long ISS200:1; - unsigned long ISS201:1; - unsigned long ISS202:1; - unsigned long ISS203:1; - unsigned long ISS204:1; - unsigned long ISS205:1; - unsigned long ISS206:1; - unsigned long ISS207:1; - unsigned long ISS208:1; - unsigned long ISS209:1; - unsigned long ISS210:1; - unsigned long ISS211:1; - unsigned long ISS212:1; - unsigned long ISS213:1; - unsigned long ISS214:1; - unsigned long ISS215:1; - unsigned long ISS216:1; - unsigned long ISS217:1; - unsigned long ISS218:1; - unsigned long ISS219:1; - unsigned long ISS220:1; - unsigned long ISS221:1; - unsigned long ISS222:1; - unsigned long ISS223:1; - } BIT; - } ISS6; - union - { - unsigned long LONG; - struct - { - unsigned long ISS224:1; - unsigned long ISS225:1; - unsigned long ISS226:1; - unsigned long ISS227:1; - unsigned long ISS228:1; - unsigned long ISS229:1; - unsigned long ISS230:1; - unsigned long ISS231:1; - unsigned long ISS232:1; - unsigned long ISS233:1; - unsigned long ISS234:1; - unsigned long ISS235:1; - unsigned long ISS236:1; - unsigned long ISS237:1; - unsigned long ISS238:1; - unsigned long ISS239:1; - unsigned long ISS240:1; - unsigned long ISS241:1; - unsigned long ISS242:1; - unsigned long ISS243:1; - unsigned long ISS244:1; - unsigned long ISS245:1; - unsigned long ISS246:1; - unsigned long ISS247:1; - unsigned long ISS248:1; - unsigned long ISS249:1; - unsigned long ISS250:1; - unsigned long ISS251:1; - unsigned long ISS252:1; - unsigned long ISS253:1; - unsigned long ISS254:1; - unsigned long ISS255:1; - } BIT; - } ISS7; - union - { - unsigned long LONG; - struct - { - unsigned long :1; - unsigned long ISC1:1; - unsigned long ISC2:1; - unsigned long ISC3:1; - unsigned long ISC4:1; - unsigned long ISC5:1; - unsigned long ISC6:1; - unsigned long ISC7:1; - unsigned long ISC8:1; - unsigned long ISC9:1; - unsigned long ISC10:1; - unsigned long ISC11:1; - unsigned long ISC12:1; - unsigned long ISC13:1; - unsigned long ISC14:1; - unsigned long ISC15:1; - unsigned long ISC16:1; - unsigned long ISC17:1; - unsigned long ISC18:1; - unsigned long ISC19:1; - unsigned long ISC20:1; - unsigned long ISC21:1; - unsigned long ISC22:1; - unsigned long ISC23:1; - unsigned long ISC24:1; - unsigned long ISC25:1; - unsigned long ISC26:1; - unsigned long ISC27:1; - unsigned long ISC28:1; - unsigned long ISC29:1; - unsigned long ISC30:1; - unsigned long ISC31:1; - } BIT; - } ISC0; - union - { - unsigned long LONG; - struct - { - unsigned long ISC32:1; - unsigned long ISC33:1; - unsigned long ISC34:1; - unsigned long ISC35:1; - unsigned long ISC36:1; - unsigned long ISC37:1; - unsigned long ISC38:1; - unsigned long ISC39:1; - unsigned long ISC40:1; - unsigned long ISC41:1; - unsigned long ISC42:1; - unsigned long ISC43:1; - unsigned long ISC44:1; - unsigned long ISC45:1; - unsigned long ISC46:1; - unsigned long ISC47:1; - unsigned long ISC48:1; - unsigned long ISC49:1; - unsigned long ISC50:1; - unsigned long ISC51:1; - unsigned long ISC52:1; - unsigned long ISC53:1; - unsigned long ISC54:1; - unsigned long ISC55:1; - unsigned long ISC56:1; - unsigned long ISC57:1; - unsigned long ISC58:1; - unsigned long ISC59:1; - unsigned long ISC60:1; - unsigned long ISC61:1; - unsigned long ISC62:1; - unsigned long ISC63:1; - } BIT; - } ISC1; - union - { - unsigned long LONG; - struct - { - unsigned long ISC64:1; - unsigned long ISC65:1; - unsigned long ISC66:1; - unsigned long ISC67:1; - unsigned long ISC68:1; - unsigned long ISC69:1; - unsigned long ISC70:1; - unsigned long ISC71:1; - unsigned long ISC72:1; - unsigned long ISC73:1; - unsigned long ISC74:1; - unsigned long ISC75:1; - unsigned long ISC76:1; - unsigned long ISC77:1; - unsigned long ISC78:1; - unsigned long ISC79:1; - unsigned long ISC80:1; - unsigned long ISC81:1; - unsigned long ISC82:1; - unsigned long ISC83:1; - unsigned long ISC84:1; - unsigned long ISC85:1; - unsigned long ISC86:1; - unsigned long ISC87:1; - unsigned long ISC88:1; - unsigned long ISC89:1; - unsigned long ISC90:1; - unsigned long ISC91:1; - unsigned long ISC92:1; - unsigned long ISC93:1; - unsigned long ISC94:1; - unsigned long ISC95:1; - } BIT; - } ISC2; - union - { - unsigned long LONG; - struct - { - unsigned long ISC96:1; - unsigned long ISC97:1; - unsigned long ISC98:1; - unsigned long ISC99:1; - unsigned long ISC100:1; - unsigned long ISC101:1; - unsigned long ISC102:1; - unsigned long ISC103:1; - unsigned long ISC104:1; - unsigned long ISC105:1; - unsigned long ISC106:1; - unsigned long ISC107:1; - unsigned long ISC108:1; - unsigned long ISC109:1; - unsigned long ISC110:1; - unsigned long ISC111:1; - unsigned long ISC112:1; - unsigned long ISC113:1; - unsigned long ISC114:1; - unsigned long ISC115:1; - unsigned long ISC116:1; - unsigned long ISC117:1; - unsigned long ISC118:1; - unsigned long ISC119:1; - unsigned long ISC120:1; - unsigned long ISC121:1; - unsigned long ISC122:1; - unsigned long ISC123:1; - unsigned long ISC124:1; - unsigned long ISC125:1; - unsigned long ISC126:1; - unsigned long ISC127:1; - } BIT; - } ISC3; - union - { - unsigned long LONG; - struct - { - unsigned long ISC128:1; - unsigned long ISC129:1; - unsigned long ISC130:1; - unsigned long ISC131:1; - unsigned long ISC132:1; - unsigned long ISC133:1; - unsigned long ISC134:1; - unsigned long ISC135:1; - unsigned long ISC136:1; - unsigned long ISC137:1; - unsigned long ISC138:1; - unsigned long ISC139:1; - unsigned long ISC140:1; - unsigned long ISC141:1; - unsigned long ISC142:1; - unsigned long ISC143:1; - unsigned long ISC144:1; - unsigned long ISC145:1; - unsigned long ISC146:1; - unsigned long ISC147:1; - unsigned long ISC148:1; - unsigned long ISC149:1; - unsigned long ISC150:1; - unsigned long ISC151:1; - unsigned long ISC152:1; - unsigned long ISC153:1; - unsigned long ISC154:1; - unsigned long ISC155:1; - unsigned long ISC156:1; - unsigned long ISC157:1; - unsigned long ISC158:1; - unsigned long ISC159:1; - } BIT; - } ISC4; - union - { - unsigned long LONG; - struct - { - unsigned long ISC160:1; - unsigned long ISC161:1; - unsigned long ISC162:1; - unsigned long ISC163:1; - unsigned long ISC164:1; - unsigned long ISC165:1; - unsigned long ISC166:1; - unsigned long ISC167:1; - unsigned long ISC168:1; - unsigned long ISC169:1; - unsigned long ISC170:1; - unsigned long ISC171:1; - unsigned long ISC172:1; - unsigned long ISC173:1; - unsigned long ISC174:1; - unsigned long ISC175:1; - unsigned long ISC176:1; - unsigned long ISC177:1; - unsigned long ISC178:1; - unsigned long ISC179:1; - unsigned long ISC180:1; - unsigned long ISC181:1; - unsigned long ISC182:1; - unsigned long ISC183:1; - unsigned long ISC184:1; - unsigned long ISC185:1; - unsigned long ISC186:1; - unsigned long ISC187:1; - unsigned long ISC188:1; - unsigned long ISC189:1; - unsigned long ISC190:1; - unsigned long ISC191:1; - } BIT; - } ISC5; - union - { - unsigned long LONG; - struct - { - unsigned long ISC192:1; - unsigned long ISC193:1; - unsigned long ISC194:1; - unsigned long ISC195:1; - unsigned long ISC196:1; - unsigned long ISC197:1; - unsigned long ISC198:1; - unsigned long ISC199:1; - unsigned long ISC200:1; - unsigned long ISC201:1; - unsigned long ISC202:1; - unsigned long ISC203:1; - unsigned long ISC204:1; - unsigned long ISC205:1; - unsigned long ISC206:1; - unsigned long ISC207:1; - unsigned long ISC208:1; - unsigned long ISC209:1; - unsigned long ISC210:1; - unsigned long ISC211:1; - unsigned long ISC212:1; - unsigned long ISC213:1; - unsigned long ISC214:1; - unsigned long ISC215:1; - unsigned long ISC216:1; - unsigned long ISC217:1; - unsigned long ISC218:1; - unsigned long ISC219:1; - unsigned long ISC220:1; - unsigned long ISC221:1; - unsigned long ISC222:1; - unsigned long ISC223:1; - } BIT; - } ISC6; - union - { - unsigned long LONG; - struct - { - unsigned long ISC224:1; - unsigned long ISC225:1; - unsigned long ISC226:1; - unsigned long ISC227:1; - unsigned long ISC228:1; - unsigned long ISC229:1; - unsigned long ISC230:1; - unsigned long ISC231:1; - unsigned long ISC232:1; - unsigned long ISC233:1; - unsigned long ISC234:1; - unsigned long ISC235:1; - unsigned long ISC236:1; - unsigned long ISC237:1; - unsigned long ISC238:1; - unsigned long ISC239:1; - unsigned long ISC240:1; - unsigned long ISC241:1; - unsigned long ISC242:1; - unsigned long ISC243:1; - unsigned long ISC244:1; - unsigned long ISC245:1; - unsigned long ISC246:1; - unsigned long ISC247:1; - unsigned long ISC248:1; - unsigned long ISC249:1; - unsigned long ISC250:1; - unsigned long ISC251:1; - unsigned long ISC252:1; - unsigned long ISC253:1; - unsigned long ISC254:1; - unsigned long ISC255:1; - } BIT; - } ISC7; - char wk6[436]; - union - { - unsigned long LONG; - struct - { - unsigned long VAD1:32; - } BIT; - } VAD1; - union - { - unsigned long LONG; - struct - { - unsigned long VAD2:32; - } BIT; - } VAD2; - union - { - unsigned long LONG; - struct - { - unsigned long VAD3:32; - } BIT; - } VAD3; - union - { - unsigned long LONG; - struct - { - unsigned long VAD4:32; - } BIT; - } VAD4; - union - { - unsigned long LONG; - struct - { - unsigned long VAD5:32; - } BIT; - } VAD5; - union - { - unsigned long LONG; - struct - { - unsigned long VAD6:32; - } BIT; - } VAD6; - union - { - unsigned long LONG; - struct - { - unsigned long VAD7:32; - } BIT; - } VAD7; - union - { - unsigned long LONG; - struct - { - unsigned long VAD8:32; - } BIT; - } VAD8; - union - { - unsigned long LONG; - struct - { - unsigned long VAD9:32; - } BIT; - } VAD9; - union - { - unsigned long LONG; - struct - { - unsigned long VAD10:32; - } BIT; - } VAD10; - union - { - unsigned long LONG; - struct - { - unsigned long VAD11:32; - } BIT; - } VAD11; - union - { - unsigned long LONG; - struct - { - unsigned long VAD12:32; - } BIT; - } VAD12; - union - { - unsigned long LONG; - struct - { - unsigned long VAD13:32; - } BIT; - } VAD13; - union - { - unsigned long LONG; - struct - { - unsigned long VAD14:32; - } BIT; - } VAD14; - union - { - unsigned long LONG; - struct - { - unsigned long VAD15:32; - } BIT; - } VAD15; - union - { - unsigned long LONG; - struct - { - unsigned long VAD16:32; - } BIT; - } VAD16; - union - { - unsigned long LONG; - struct - { - unsigned long VAD17:32; - } BIT; - } VAD17; - union - { - unsigned long LONG; - struct - { - unsigned long VAD18:32; - } BIT; - } VAD18; - union - { - unsigned long LONG; - struct - { - unsigned long VAD19:32; - } BIT; - } VAD19; - union - { - unsigned long LONG; - struct - { - unsigned long VAD20:32; - } BIT; - } VAD20; - union - { - unsigned long LONG; - struct - { - unsigned long VAD21:32; - } BIT; - } VAD21; - union - { - unsigned long LONG; - struct - { - unsigned long VAD22:32; - } BIT; - } VAD22; - union - { - unsigned long LONG; - struct - { - unsigned long VAD23:32; - } BIT; - } VAD23; - union - { - unsigned long LONG; - struct - { - unsigned long VAD24:32; - } BIT; - } VAD24; - union - { - unsigned long LONG; - struct - { - unsigned long VAD25:32; - } BIT; - } VAD25; - union - { - unsigned long LONG; - struct - { - unsigned long VAD26:32; - } BIT; - } VAD26; - union - { - unsigned long LONG; - struct - { - unsigned long VAD27:32; - } BIT; - } VAD27; - union - { - unsigned long LONG; - struct - { - unsigned long VAD28:32; - } BIT; - } VAD28; - union - { - unsigned long LONG; - struct - { - unsigned long VAD29:32; - } BIT; - } VAD29; - union - { - unsigned long LONG; - struct - { - unsigned long VAD30:32; - } BIT; - } VAD30; - union - { - unsigned long LONG; - struct - { - unsigned long VAD31:32; - } BIT; - } VAD31; - union - { - unsigned long LONG; - struct - { - unsigned long VAD32:32; - } BIT; - } VAD32; - union - { - unsigned long LONG; - struct - { - unsigned long VAD33:32; - } BIT; - } VAD33; - union - { - unsigned long LONG; - struct - { - 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VAD182; - union - { - unsigned long LONG; - struct - { - unsigned long VAD183:32; - } BIT; - } VAD183; - union - { - unsigned long LONG; - struct - { - unsigned long VAD184:32; - } BIT; - } VAD184; - union - { - unsigned long LONG; - struct - { - unsigned long VAD185:32; - } BIT; - } VAD185; - union - { - unsigned long LONG; - struct - { - unsigned long VAD186:32; - } BIT; - } VAD186; - union - { - unsigned long LONG; - struct - { - unsigned long VAD187:32; - } BIT; - } VAD187; - union - { - unsigned long LONG; - struct - { - unsigned long VAD188:32; - } BIT; - } VAD188; - union - { - unsigned long LONG; - struct - { - unsigned long VAD189:32; - } BIT; - } VAD189; - union - { - unsigned long LONG; - struct - { - unsigned long VAD190:32; - } BIT; - } VAD190; - union - { - unsigned long LONG; - struct - { - unsigned long VAD191:32; - } BIT; - } VAD191; - union - { - unsigned long LONG; - struct - { - unsigned long VAD192:32; - } BIT; - } VAD192; - union - { - unsigned long LONG; - struct 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VAD203; - union - { - unsigned long LONG; - struct - { - unsigned long VAD204:32; - } BIT; - } VAD204; - union - { - unsigned long LONG; - struct - { - unsigned long VAD205:32; - } BIT; - } VAD205; - union - { - unsigned long LONG; - struct - { - unsigned long VAD206:32; - } BIT; - } VAD206; - union - { - unsigned long LONG; - struct - { - unsigned long VAD207:32; - } BIT; - } VAD207; - union - { - unsigned long LONG; - struct - { - unsigned long VAD208:32; - } BIT; - } VAD208; - union - { - unsigned long LONG; - struct - { - unsigned long VAD209:32; - } BIT; - } VAD209; - union - { - unsigned long LONG; - struct - { - unsigned long VAD210:32; - } BIT; - } VAD210; - union - { - unsigned long LONG; - struct - { - unsigned long VAD211:32; - } BIT; - } VAD211; - union - { - unsigned long LONG; - struct - { - unsigned long VAD212:32; - } BIT; - } VAD212; - union - { - unsigned long LONG; - struct - { - unsigned long VAD213:32; - } BIT; - } VAD213; - union - { - unsigned long LONG; - struct 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LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL1; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL2; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL3; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL4; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL5; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL6; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL7; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL8; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL9; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL10; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL11; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL12; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL13; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL14; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL15; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL16; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL17; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL18; - union - { - unsigned long LONG; - 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struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL37; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL38; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL39; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL40; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL41; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL42; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL43; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL44; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL45; - union - { - unsigned long LONG; - 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struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL55; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL56; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL57; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL58; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL59; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL60; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL61; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL62; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL63; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL64; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL65; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL66; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL67; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL68; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL69; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL70; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL71; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL72; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL73; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL74; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL75; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL76; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL77; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL78; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL79; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL80; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL81; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL82; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL83; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL84; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL85; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL86; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL87; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL88; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL89; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL90; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL91; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL92; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL93; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL94; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL95; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL96; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL97; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL98; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL99; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL100; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL101; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL102; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL103; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL104; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL105; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL106; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL107; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL108; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL109; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL110; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL111; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL112; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL113; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL114; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL115; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL116; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL117; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL118; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL119; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL120; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL121; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL122; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL123; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL124; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL125; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL126; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL127; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL128; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL129; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL130; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL131; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL132; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL133; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL134; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL135; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL136; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL137; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL138; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL139; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL140; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL141; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL142; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL143; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL144; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL145; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL146; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL147; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL148; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL149; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL150; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL151; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL152; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL153; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL154; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL155; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL156; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL157; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL158; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL159; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL160; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL161; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - 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PRL:4; - unsigned long :28; - } BIT; - } PRL171; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL172; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL173; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL174; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL175; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL176; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL177; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL178; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL179; - union - { - unsigned long LONG; - struct - { - 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struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL189; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL190; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL191; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL192; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL193; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL194; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL195; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL196; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL197; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL198; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL199; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL200; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL201; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL202; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL203; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL204; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL205; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL206; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL207; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL208; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL209; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL210; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL211; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL212; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL213; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL214; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL215; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL216; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL217; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL218; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL219; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL220; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL221; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL222; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL223; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL224; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL225; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL226; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL227; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL228; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL229; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL230; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL231; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL232; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL233; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL234; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL235; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL236; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL237; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL238; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL239; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL240; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL241; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL242; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL243; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL244; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL245; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL246; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL247; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL248; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL249; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL250; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL251; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL252; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL253; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL254; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL255; - char wk8[1024]; - union - { - unsigned long LONG; - struct - { - unsigned long IRQ256:1; - unsigned long IRQ257:1; - unsigned long IRQ258:1; - unsigned long IRQ259:1; - unsigned long IRQ260:1; - unsigned long IRQ261:1; - unsigned long IRQ262:1; - unsigned long IRQ263:1; - unsigned long IRQ264:1; - unsigned long IRQ265:1; - unsigned long IRQ266:1; - unsigned long IRQ267:1; - unsigned long IRQ268:1; - unsigned long IRQ269:1; - unsigned long IRQ270:1; - unsigned long IRQ271:1; - unsigned long IRQ272:1; - unsigned long IRQ273:1; - unsigned long IRQ274:1; - unsigned long IRQ275:1; - unsigned long IRQ276:1; - unsigned long IRQ277:1; - unsigned long IRQ278:1; - unsigned long IRQ279:1; - unsigned long IRQ280:1; - unsigned long IRQ281:1; - unsigned long IRQ282:1; - unsigned long IRQ283:1; - unsigned long IRQ284:1; - unsigned long IRQ285:1; - unsigned long IRQ286:1; - unsigned long IRQ287:1; - } BIT; - } IRQS8; - union - { - unsigned long LONG; - struct - { - unsigned long IRQ288:1; - unsigned long IRQ289:1; - unsigned long IRQ290:1; - unsigned long IRQ291:1; - unsigned long IRQ292:1; - unsigned long IRQ293:1; - unsigned long IRQ294:1; - unsigned long IRQ295:1; - unsigned long IRQ296:1; - unsigned long IRQ297:1; - unsigned long IRQ298:1; - unsigned long IRQ299:1; - unsigned long IRQ300:1; - unsigned long :19; - } BIT; - } IRQS9; - char wk9[56]; - union - { - unsigned long LONG; - struct - { - unsigned long RAI256:1; - unsigned long RAI257:1; - unsigned long RAI258:1; - unsigned long RAI259:1; - unsigned long RAI260:1; - unsigned long RAI261:1; - unsigned long RAI262:1; - unsigned long RAI263:1; - unsigned long RAI264:1; - unsigned long RAI265:1; - unsigned long RAI266:1; - unsigned long RAI267:1; - unsigned long RAI268:1; - unsigned long RAI269:1; - unsigned long RAI270:1; - unsigned long RAI271:1; - unsigned long RAI272:1; - unsigned long RAI273:1; - unsigned long RAI274:1; - unsigned long RAI275:1; - unsigned long RAI276:1; - unsigned long RAI277:1; - unsigned long RAI278:1; - unsigned long RAI279:1; - unsigned long RAI280:1; - unsigned long RAI281:1; - unsigned long RAI282:1; - unsigned long RAI283:1; - unsigned long RAI284:1; - unsigned long RAI285:1; - unsigned long RAI286:1; - unsigned long RAI287:1; - } BIT; - } RAIS8; - union - { - unsigned long LONG; - struct - { - unsigned long RAI288:1; - unsigned long RAI289:1; - unsigned long RAI290:1; - unsigned long RAI291:1; - unsigned long RAI292:1; - unsigned long RAI293:1; - unsigned long RAI294:1; - unsigned long RAI295:1; - unsigned long RAI296:1; - unsigned long RAI297:1; - unsigned long RAI298:1; - unsigned long RAI299:1; - unsigned long RAI300:1; - unsigned long :19; - } BIT; - } RAIS9; - char wk10[56]; - union - { - unsigned long LONG; - struct - { - unsigned long IEN256:1; - unsigned long IEN257:1; - unsigned long IEN258:1; - unsigned long IEN259:1; - unsigned long IEN260:1; - unsigned long IEN261:1; - unsigned long IEN262:1; - unsigned long IEN263:1; - unsigned long IEN264:1; - unsigned long IEN265:1; - unsigned long IEN266:1; - unsigned long IEN267:1; - unsigned long IEN268:1; - unsigned long IEN269:1; - unsigned long IEN270:1; - unsigned long IEN271:1; - unsigned long IEN272:1; - unsigned long IEN273:1; - unsigned long IEN274:1; - unsigned long IEN275:1; - unsigned long IEN276:1; - unsigned long IEN277:1; - unsigned long IEN278:1; - unsigned long IEN279:1; - unsigned long IEN280:1; - unsigned long IEN281:1; - unsigned long IEN282:1; - unsigned long IEN283:1; - unsigned long IEN284:1; - unsigned long IEN285:1; - unsigned long IEN286:1; - unsigned long IEN287:1; - } BIT; - } IEN8; - union - { - unsigned long LONG; - struct - { - unsigned long IEN288:1; - unsigned long IEN289:1; - unsigned long IEN290:1; - unsigned long IEN291:1; - unsigned long IEN292:1; - unsigned long IEN293:1; - unsigned long IEN294:1; - unsigned long IEN295:1; - unsigned long IEN296:1; - unsigned long IEN297:1; - unsigned long IEN298:1; - unsigned long IEN299:1; - unsigned long IEN300:1; - unsigned long :19; - } BIT; - } IEN9; - char wk11[24]; - union - { - unsigned long LONG; - struct - { - unsigned long IEC256:1; - unsigned long IEC257:1; - unsigned long IEC258:1; - unsigned long IEC259:1; - unsigned long IEC260:1; - unsigned long IEC261:1; - unsigned long IEC262:1; - unsigned long IEC263:1; - unsigned long IEC264:1; - unsigned long IEC265:1; - unsigned long IEC266:1; - unsigned long IEC267:1; - unsigned long IEC268:1; - unsigned long IEC269:1; - unsigned long IEC270:1; - unsigned long IEC271:1; - unsigned long IEC272:1; - unsigned long IEC273:1; - unsigned long IEC274:1; - unsigned long IEC275:1; - unsigned long IEC276:1; - unsigned long IEC277:1; - unsigned long IEC278:1; - unsigned long IEC279:1; - unsigned long IEC280:1; - unsigned long IEC281:1; - unsigned long IEC282:1; - unsigned long IEC283:1; - unsigned long IEC284:1; - unsigned long IEC285:1; - unsigned long IEC286:1; - unsigned long IEC287:1; - } BIT; - } IEC8; - union - { - unsigned long LONG; - struct - { - unsigned long IEC288:1; - unsigned long IEC289:1; - unsigned long IEC290:1; - unsigned long IEC291:1; - unsigned long IEC292:1; - unsigned long IEC293:1; - unsigned long IEC294:1; - unsigned long IEC295:1; - unsigned long IEC296:1; - unsigned long IEC297:1; - unsigned long IEC298:1; - unsigned long IEC299:1; - unsigned long IEC300:1; - unsigned long :19; - } BIT; - } IEC9; - char wk12[88]; - union - { - unsigned long LONG; - struct - { - unsigned long PLS256:1; - unsigned long PLS257:1; - unsigned long PLS258:1; - unsigned long PLS259:1; - unsigned long PLS260:1; - unsigned long PLS261:1; - unsigned long PLS262:1; - unsigned long PLS263:1; - unsigned long PLS264:1; - unsigned long PLS265:1; - unsigned long PLS266:1; - unsigned long PLS267:1; - unsigned long PLS268:1; - unsigned long PLS269:1; - unsigned long PLS270:1; - unsigned long PLS271:1; - unsigned long PLS272:1; - unsigned long PLS273:1; - unsigned long PLS274:1; - unsigned long PLS275:1; - unsigned long PLS276:1; - unsigned long PLS277:1; - unsigned long PLS278:1; - unsigned long PLS279:1; - unsigned long PLS280:1; - unsigned long PLS281:1; - unsigned long PLS282:1; - unsigned long PLS283:1; - unsigned long PLS284:1; - unsigned long PLS285:1; - unsigned long PLS286:1; - unsigned long PLS287:1; - } BIT; - } PLS8; - union - { - unsigned long LONG; - struct - { - unsigned long PLS288:1; - unsigned long PLS289:1; - unsigned long PLS290:1; - unsigned long PLS291:1; - unsigned long PLS292:1; - unsigned long PLS293:1; - unsigned long PLS294:1; - unsigned long PLS295:1; - unsigned long PLS296:1; - unsigned long PLS297:1; - unsigned long PLS298:1; - unsigned long PLS299:1; - unsigned long PLS300:1; - unsigned long :19; - } BIT; - } PLS9; - char wk13[24]; - union - { - unsigned long LONG; - struct - { - unsigned long PIC256:1; - unsigned long PIC257:1; - unsigned long PIC258:1; - unsigned long PIC259:1; - unsigned long PIC260:1; - unsigned long PIC261:1; - unsigned long PIC262:1; - unsigned long PIC263:1; - unsigned long PIC264:1; - unsigned long PIC265:1; - unsigned long PIC266:1; - unsigned long PIC267:1; - unsigned long PIC268:1; - unsigned long PIC269:1; - unsigned long PIC270:1; - unsigned long PIC271:1; - unsigned long PIC272:1; - unsigned long PIC273:1; - unsigned long PIC274:1; - unsigned long PIC275:1; - unsigned long PIC276:1; - unsigned long PIC277:1; - unsigned long PIC278:1; - unsigned long PIC279:1; - unsigned long PIC280:1; - unsigned long PIC281:1; - unsigned long PIC282:1; - unsigned long PIC283:1; - unsigned long PIC284:1; - unsigned long PIC285:1; - unsigned long PIC286:1; - unsigned long PIC287:1; - } BIT; - } PIC8; - union - { - unsigned long LONG; - struct - { - unsigned long PIC288:1; - unsigned long PIC289:1; - unsigned long PIC290:1; - unsigned long PIC291:1; - unsigned long PIC292:1; - unsigned long PIC293:1; - unsigned long PIC294:1; - unsigned long PIC295:1; - unsigned long PIC296:1; - unsigned long PIC297:1; - unsigned long PIC298:1; - unsigned long PIC299:1; - unsigned long PIC300:1; - unsigned long :19; - } BIT; - } PIC9; - char wk14[152]; - union - { - unsigned long LONG; - struct - { - unsigned long PRLM0:1; - unsigned long PRLM1:1; - unsigned long PRLM2:1; - unsigned long PRLM3:1; - unsigned long PRLM4:1; - unsigned long PRLM5:1; - unsigned long PRLM6:1; - unsigned long PRLM7:1; - unsigned long PRLM8:1; - unsigned long PRLM9:1; - unsigned long PRLM10:1; - unsigned long PRLM11:1; - unsigned long PRLM12:1; - unsigned long PRLM13:1; - unsigned long PRLM14:1; - unsigned long PRLM15:1; - unsigned long :16; - } BIT; - } PRLM1; - union - { - unsigned long LONG; - struct - { - unsigned long PRLC0:1; - unsigned long PRLC1:1; - unsigned long PRLC2:1; - unsigned long PRLC3:1; - unsigned long PRLC4:1; - unsigned long PRLC5:1; - unsigned long PRLC6:1; - unsigned long PRLC7:1; - unsigned long PRLC8:1; - unsigned long PRLC9:1; - unsigned long PRLC10:1; - unsigned long PRLC11:1; - unsigned long PRLC12:1; - unsigned long PRLC13:1; - unsigned long PRLC14:1; - unsigned long PRLC15:1; - unsigned long :16; - } BIT; - } PRLC1; - union - { - unsigned long LONG; - struct - { - unsigned long UE:1; - unsigned long :31; - } BIT; - } UEN1; - char wk15[68]; - union - { - unsigned long LONG; - struct - { - unsigned long ISS256:1; - unsigned long ISS257:1; - unsigned long ISS258:1; - unsigned long ISS259:1; - unsigned long ISS260:1; - unsigned long ISS261:1; - unsigned long ISS262:1; - unsigned long ISS263:1; - unsigned long ISS264:1; - unsigned long ISS265:1; - unsigned long ISS266:1; - unsigned long ISS267:1; - unsigned long ISS268:1; - unsigned long ISS269:1; - unsigned long ISS270:1; - unsigned long ISS271:1; - unsigned long ISS272:1; - unsigned long ISS273:1; - unsigned long ISS274:1; - unsigned long ISS275:1; - unsigned long ISS276:1; - unsigned long ISS277:1; - unsigned long ISS278:1; - unsigned long SS279:1; - unsigned long ISS280:1; - unsigned long ISS281:1; - unsigned long ISS282:1; - unsigned long ISS283:1; - unsigned long ISS284:1; - unsigned long ISS285:1; - unsigned long ISS286:1; - unsigned long ISS287:1; - } BIT; - } ISS8; - union - { - unsigned long LONG; - struct - { - unsigned long ISS288:1; - unsigned long ISS289:1; - unsigned long ISS290:1; - unsigned long ISS291:1; - unsigned long ISS292:1; - unsigned long ISS293:1; - unsigned long ISS294:1; - unsigned long ISS295:1; - unsigned long ISS296:1; - unsigned long ISS297:1; - unsigned long ISS298:1; - unsigned long ISS299:1; - unsigned long ISS300:1; - unsigned long :19; - } BIT; - } ISS9; - char wk16[24]; - union - { - unsigned long LONG; - struct - { - unsigned long ISC256:1; - unsigned long ISC257:1; - unsigned long ISC258:1; - unsigned long ISC259:1; - unsigned long ISC260:1; - unsigned long ISC261:1; - unsigned long ISC262:1; - unsigned long ISC263:1; - unsigned long ISC264:1; - unsigned long ISC265:1; - unsigned long ISC266:1; - unsigned long ISC267:1; - unsigned long ISC268:1; - unsigned long ISC269:1; - unsigned long ISC270:1; - unsigned long ISC271:1; - unsigned long ISC272:1; - unsigned long ISC273:1; - unsigned long ISC274:1; - unsigned long ISC275:1; - unsigned long ISC276:1; - unsigned long ISC277:1; - unsigned long ISC278:1; - unsigned long ISC279:1; - unsigned long ISC280:1; - unsigned long ISC281:1; - unsigned long ISC282:1; - unsigned long ISC283:1; - unsigned long ISC284:1; - unsigned long ISC285:1; - unsigned long ISC286:1; - unsigned long ISC287:1; - } BIT; - } ISC8; - union - { - unsigned long LONG; - struct - { - unsigned long ISC288:1; - unsigned long ISC289:1; - unsigned long ISC290:1; - unsigned long ISC291:1; - unsigned long ISC292:1; - unsigned long ISC293:1; - unsigned long ISC294:1; - unsigned long ISC295:1; - unsigned long ISC296:1; - unsigned long ISC297:1; - unsigned long ISC298:1; - unsigned long ISC299:1; - unsigned long ISC300:1; - unsigned long :19; - } BIT; - } ISC9; - char wk17[456]; - union - { - unsigned long LONG; - struct - { - unsigned long VAD256:32; - } BIT; - } VAD256; - union - { - unsigned long LONG; - struct - { - unsigned long VAD257:32; - } BIT; - } VAD257; - union - { - unsigned long LONG; - struct - { - unsigned long VAD258:32; - } BIT; - } VAD258; - union - { - unsigned long LONG; - struct - { - unsigned long VAD259:32; - } BIT; - } VAD259; - union - { - unsigned long LONG; - struct - { - unsigned long VAD260:32; - } BIT; - } VAD260; - union - { - unsigned long LONG; - struct - { - unsigned long VAD261:32; - } BIT; - } VAD261; - union - { - unsigned long LONG; - struct - { - unsigned long VAD262:32; - } BIT; - } VAD262; - union - { - unsigned long LONG; - struct - { - unsigned long VAD263:32; - } BIT; - } VAD263; - union - { - unsigned long LONG; - struct - { - unsigned long VAD264:32; - } BIT; - } VAD264; - union - { - unsigned long LONG; - struct - { - unsigned long VAD265:32; - } BIT; - } VAD265; - union - { - unsigned long LONG; - struct - { - unsigned long VAD266:32; - } BIT; - } VAD266; - union - { - unsigned long LONG; - struct - { - unsigned long VAD267:32; - } BIT; - } VAD267; - union - { - unsigned long LONG; - struct - { - unsigned long VAD268:32; - } BIT; - } VAD268; - union - { - unsigned long LONG; - struct - { - unsigned long VAD269:32; - } BIT; - } VAD269; - union - { - unsigned long LONG; - struct - { - unsigned long VAD270:32; - } BIT; - } VAD270; - union - { - unsigned long LONG; - struct - { - unsigned long VAD271:32; - } BIT; - } VAD271; - union - { - unsigned long LONG; - struct - { - unsigned long VAD272:32; - } BIT; - } VAD272; - union - { - unsigned long LONG; - struct - { - unsigned long VAD273:32; - } BIT; - } VAD273; - union - { - unsigned long LONG; - struct - { - unsigned long VAD274:32; - } BIT; - } VAD274; - union - { - unsigned long LONG; - struct - { - unsigned long VAD275:32; - } BIT; - } VAD275; - union - { - unsigned long LONG; - struct - { - unsigned long VAD276:32; - } BIT; - } VAD276; - union - { - unsigned long LONG; - struct - { - unsigned long VAD277:32; - } BIT; - } VAD277; - union - { - unsigned long LONG; - struct - { - unsigned long VAD278:32; - } BIT; - } VAD278; - union - { - unsigned long LONG; - struct - { - unsigned long VAD279:32; - } BIT; - } VAD279; - union - { - unsigned long LONG; - struct - { - unsigned long VAD280:32; - } BIT; - } VAD280; - union - { - unsigned long LONG; - struct - { - unsigned long VAD281:32; - } BIT; - } VAD281; - union - { - unsigned long LONG; - struct - { - unsigned long VAD282:32; - } BIT; - } VAD282; - union - { - unsigned long LONG; - struct - { - unsigned long VAD283:32; - } BIT; - } VAD283; - union - { - unsigned long LONG; - struct - { - unsigned long VAD284:32; - } BIT; - } VAD284; - union - { - unsigned long LONG; - struct - { - unsigned long VAD285:32; - } BIT; - } VAD285; - union - { - unsigned long LONG; - struct - { - unsigned long VAD286:32; - } BIT; - } VAD286; - union - { - unsigned long LONG; - struct - { - unsigned long VAD287:32; - } BIT; - } VAD287; - union - { - unsigned long LONG; - struct - { - unsigned long VAD288:32; - } BIT; - } VAD288; - union - { - unsigned long LONG; - struct - { - unsigned long VAD289:32; - } BIT; - } VAD289; - union - { - unsigned long LONG; - struct - { - unsigned long VAD290:32; - } BIT; - } VAD290; - union - { - unsigned long LONG; - struct - { - unsigned long VAD291:32; - } BIT; - } VAD291; - union - { - unsigned long LONG; - struct - { - unsigned long VAD292:32; - } BIT; - } VAD292; - union - { - unsigned long LONG; - struct - { - unsigned long VAD293:32; - } BIT; - } VAD293; - union - { - unsigned long LONG; - struct - { - unsigned long VAD294:32; - } BIT; - } VAD294; - union - { - unsigned long LONG; - struct - { - unsigned long VAD295:32; - } BIT; - } VAD295; - union - { - unsigned long LONG; - struct - { - unsigned long VAD296:32; - } BIT; - } VAD296; - union - { - unsigned long LONG; - struct - { - unsigned long VAD297:32; - } BIT; - } VAD297; - union - { - unsigned long LONG; - struct - { - unsigned long VAD298:32; - } BIT; - } VAD298; - union - { - unsigned long LONG; - struct - { - unsigned long VAD299:32; - } BIT; - } VAD299; - union - { - unsigned long LONG; - struct - { - unsigned long VAD300:32; - } BIT; - } VAD300; - char wk18[844]; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL256; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL257; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL258; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL259; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL260; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL261; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL262; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL263; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL264; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL265; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL266; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL267; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL268; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL269; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL270; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL271; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL272; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL273; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL274; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL275; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL276; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL277; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL278; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL279; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL280; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL281; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL282; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL283; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL284; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL285; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL286; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL287; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL288; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL289; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL290; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL291; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL292; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL293; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL294; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL295; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL296; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL297; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL298; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL299; - union - { - unsigned long LONG; - struct - { - unsigned long PRL:4; - unsigned long :28; - } BIT; - } PRL300; -}; - -struct st_wdt -{ - union - { - unsigned char BYTE; - struct - { - unsigned char REFRESH:8; - } BIT; - } WDTRR; - char wk0[1]; - union - { - unsigned short WORD; - struct - { - unsigned short TOPS:2; - unsigned short :2; - unsigned short CKS:4; - unsigned short RPES:2; - unsigned short :2; - unsigned short RPSS:2; - unsigned short :2; - } BIT; - } WDTCR; - union - { - unsigned short WORD; - struct - { - unsigned short CNTVAL:14; - unsigned short UNDFF:1; - unsigned short REFEF:1; - } BIT; - } WDTSR; - union - { - unsigned char BYTE; - struct - { - unsigned char :7; - unsigned char RSTIRQS:1; - } BIT; - } WDTRCR; -}; - -//------------------------------------- -// Peripheral I/O region -//------------------------------------- -#ifdef _RZT1_REGISTER_CORTEX_M3_ -#define PERI_BASE (0x40000000UL) -#else -#define PERI_BASE (0xA0000000UL) -#endif - -#define BSC (*(volatile struct st_bsc *)(PERI_BASE + 0x00002004)) -#define CLMA0 (*(volatile struct st_clma0 *)(PERI_BASE + 0x00090000)) -#define CLMA1 (*(volatile struct st_clma1 *)(PERI_BASE + 0x00090020)) -#define CLMA2 (*(volatile struct st_clma2 *)(PERI_BASE + 0x00090040)) -#define CMT (*(volatile struct st_cmt *)(PERI_BASE + 0x00080000)) -#define CMT0 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080002)) -#define CMT1 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080008)) -#define CMT2 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080022)) -#define CMT3 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080028)) -#define CMT4 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080042)) -#define CMT5 (*(volatile struct st_cmt0 *)(PERI_BASE + 0x00080048)) -#define CMTW (*(volatile struct st_cmtw *)(PERI_BASE + 0x00080400)) -#define CMTW0 (*(volatile struct st_cmtw0 *)(PERI_BASE + 0x00080300)) -#define CMTW1 (*(volatile struct st_cmtw0 *)(PERI_BASE + 0x00080380)) -#define CRC (*(volatile struct st_crc *)(PERI_BASE + 0x0007C000)) -#define DMA0 (*(volatile struct st_dma0 *)(PERI_BASE + 0x00062000)) -#define DMA1 (*(volatile struct st_dma1 *)(PERI_BASE + 0x00063000)) -#define DMAC (*(volatile struct st_dmac *)(PERI_BASE + 0x00002000)) -#define DOC (*(volatile struct st_doc *)(PERI_BASE + 0x00081200)) -#define DSMIF (*(volatile struct st_dsmif *)(PERI_BASE + 0x00072000)) -#define ECATC (*(volatile struct st_ecatc *)(PERI_BASE + 0x000BF100)) -#define ECCRAM (*(volatile struct st_eccram *)(PERI_BASE + 0x000F3000)) -#define ECM (*(volatile struct st_ecm *)(PERI_BASE + 0x0007D080)) -#define ECMC (*(volatile struct st_ecmc *)(PERI_BASE + 0x0007D040)) -#define ECMM (*(volatile struct st_ecmm *)(PERI_BASE + 0x0007D000)) -#define ELC (*(volatile struct st_elc *)(PERI_BASE + 0x00080B00)) -#define ETHERC (*(volatile struct st_etherc *)(PERI_BASE + 0x000BF000)) -#define ETHERSW (*(volatile struct st_ethersw *)(PERI_BASE + 0x000BF014)) -#define GPT (*(volatile struct st_gpt *)(PERI_BASE + 0x0006C000)) -#define GPT0 (*(volatile struct st_gpt0 *)(PERI_BASE + 0x0006C100)) -#define GPT1 (*(volatile struct st_gpt0 *)(PERI_BASE + 0x0006C180)) -#define GPT2 (*(volatile struct st_gpt0 *)(PERI_BASE + 0x0006C200)) -#define GPT3 (*(volatile struct st_gpt0 *)(PERI_BASE + 0x0006C280)) -#define ICU (*(volatile struct st_icu *)(PERI_BASE + 0x00094200)) -#define IWDT (*(volatile struct st_iwdt *)(PERI_BASE + 0x00080700)) -#define MPC (*(volatile struct st_mpc *)(PERI_BASE + 0x00000200)) -#define MTU (*(volatile struct st_mtu *)(PERI_BASE + 0x0006A00A)) -#define MTU0 (*(volatile struct st_mtu0 *)(PERI_BASE + 0x0006A090)) -#define MTU1 (*(volatile struct st_mtu1 *)(PERI_BASE + 0x0006A090)) -#define MTU2 (*(volatile struct st_mtu2 *)(PERI_BASE + 0x0006A092)) -#define MTU3 (*(volatile struct st_mtu3 *)(PERI_BASE + 0x0006A000)) -#define MTU4 (*(volatile struct st_mtu4 *)(PERI_BASE + 0x0006A000)) -#define MTU5 (*(volatile struct st_mtu5 *)(PERI_BASE + 0x0006A894)) -#define MTU6 (*(volatile struct st_mtu6 *)(PERI_BASE + 0x0006A800)) -#define MTU7 (*(volatile struct st_mtu7 *)(PERI_BASE + 0x0006A800)) -#define MTU8 (*(volatile struct st_mtu8 *)(PERI_BASE + 0x0006A098)) -#define POE3 (*(volatile struct st_poe *)(PERI_BASE + 0x00080800)) -#define PORT0 (*(volatile struct st_port0 *)(PERI_BASE + 0x00000000)) -#define PORT1 (*(volatile struct st_port1 *)(PERI_BASE + 0x00000002)) -#define PORT2 (*(volatile struct st_port2 *)(PERI_BASE + 0x00000004)) -#define PORT3 (*(volatile struct st_port3 *)(PERI_BASE + 0x00000006)) -#define PORT4 (*(volatile struct st_port4 *)(PERI_BASE + 0x00000008)) -#define PORT5 (*(volatile struct st_port5 *)(PERI_BASE + 0x0000000A)) -#define PORT6 (*(volatile struct st_port6 *)(PERI_BASE + 0x0000000C)) -#define PORT7 (*(volatile struct st_port7 *)(PERI_BASE + 0x0000000E)) -#define PORT8 (*(volatile struct st_port8 *)(PERI_BASE + 0x00000010)) -#define PORT9 (*(volatile struct st_port9 *)(PERI_BASE + 0x00000012)) -#define PORTA (*(volatile struct st_porta *)(PERI_BASE + 0x00000014)) -#define PORTB (*(volatile struct st_portb *)(PERI_BASE + 0x00000016)) -#define PORTC (*(volatile struct st_portc *)(PERI_BASE + 0x00000018)) -#define PORTD (*(volatile struct st_portd *)(PERI_BASE + 0x0000001A)) -#define PORTE (*(volatile struct st_porte *)(PERI_BASE + 0x0000001C)) -#define PORTF (*(volatile struct st_portf *)(PERI_BASE + 0x0000001E)) -#define PORTG (*(volatile struct st_portg *)(PERI_BASE + 0x00000020)) -#define PORTH (*(volatile struct st_porth *)(PERI_BASE + 0x00000022)) -#define PORTJ (*(volatile struct st_portj *)(PERI_BASE + 0x00000024)) -#define PORTK (*(volatile struct st_portk *)(PERI_BASE + 0x00000026)) -#define PORTL (*(volatile struct st_portl *)(PERI_BASE + 0x00000028)) -#define PORTM (*(volatile struct st_portm *)(PERI_BASE + 0x0000002A)) -#define PORTN (*(volatile struct st_portn *)(PERI_BASE + 0x0000002C)) -#define PORTP (*(volatile struct st_portp *)(PERI_BASE + 0x0000002E)) -#define PORTR (*(volatile struct st_portr *)(PERI_BASE + 0x00000030)) -#define PORTS (*(volatile struct st_ports *)(PERI_BASE + 0x00000032)) -#define PORTT (*(volatile struct st_portt *)(PERI_BASE + 0x00000034)) -#define PORTU (*(volatile struct st_portu *)(PERI_BASE + 0x00000036)) -#define PPG0 (*(volatile struct st_ppg0 *)(PERI_BASE + 0x00080506)) -#define PPG1 (*(volatile struct st_ppg1 *)(PERI_BASE + 0x00080516)) -#define RIIC0 (*(volatile struct st_riic *)(PERI_BASE + 0x00080900)) -#define RIIC1 (*(volatile struct st_riic *)(PERI_BASE + 0x00080940)) -#define RSCAN (*(volatile struct st_rscan *)(PERI_BASE + 0x00078000)) -#define RSPI0 (*(volatile struct st_rspi *)(PERI_BASE + 0x00068000)) -#define RSPI1 (*(volatile struct st_rspi *)(PERI_BASE + 0x00068400)) -#define RSPI2 (*(volatile struct st_rspi *)(PERI_BASE + 0x00068800)) -#define RSPI3 (*(volatile struct st_rspi *)(PERI_BASE + 0x00068C00)) -#define S12ADC0 (*(volatile struct st_s12adc0 *)(PERI_BASE + 0x0008C000)) -#define S12ADC1 (*(volatile struct st_s12adc1 *)(PERI_BASE + 0x0008C400)) -#define SCIFA0 (*(volatile struct st_scifa *)(PERI_BASE + 0x00065000)) -#define SCIFA1 (*(volatile struct st_scifa *)(PERI_BASE + 0x00065400)) -#define SCIFA2 (*(volatile struct st_scifa *)(PERI_BASE + 0x00065800)) -#define SCIFA3 (*(volatile struct st_scifa *)(PERI_BASE + 0x00065C00)) -#define SCIFA4 (*(volatile struct st_scifa *)(PERI_BASE + 0x00066000)) -#define SPIBSC (*(volatile struct st_spibsc *)(PERI_BASE + 0x00005000)) -#define SSI (*(volatile struct st_ssi *)(PERI_BASE + 0x00081000)) -#define SYSTEM (*(volatile struct st_system *)(PERI_BASE + 0x000B0020)) -#define TPU0 (*(volatile struct st_tpu0 *)(PERI_BASE + 0x00080108)) -#define TPU1 (*(volatile struct st_tpu1 *)(PERI_BASE + 0x00080108)) -#define TPU2 (*(volatile struct st_tpu2 *)(PERI_BASE + 0x0008010A)) -#define TPU3 (*(volatile struct st_tpu3 *)(PERI_BASE + 0x0008010A)) -#define TPU4 (*(volatile struct st_tpu4 *)(PERI_BASE + 0x0008010C)) -#define TPU5 (*(volatile struct st_tpu5 *)(PERI_BASE + 0x0008010C)) -#define TPU6 (*(volatile struct st_tpu0 *)(PERI_BASE + 0x00080188)) -#define TPU7 (*(volatile struct st_tpu1 *)(PERI_BASE + 0x00080188)) -#define TPU8 (*(volatile struct st_tpu2 *)(PERI_BASE + 0x0008018A)) -#define TPU9 (*(volatile struct st_tpu3 *)(PERI_BASE + 0x0008018A)) -#define TPU10 (*(volatile struct st_tpu4 *)(PERI_BASE + 0x0008018C)) -#define TPU11 (*(volatile struct st_tpu5 *)(PERI_BASE + 0x0008018C)) -#define TPUA (*(volatile struct st_tpua *)(PERI_BASE + 0x00080100)) -#define TPUSL (*(volatile struct st_tpusl *)(PERI_BASE + 0x00080200)) -#define TSN (*(volatile struct st_tsn *)(PERI_BASE + 0x00080A00)) -#define USBf (*(volatile struct st_usbf *)(PERI_BASE + 0x00060000)) -#define USBh (*(volatile struct st_usbh *)(PERI_BASE + 0x00040000)) -#define VIC (*(volatile struct st_vic *)(PERI_BASE + 0x00010000)) -#define WDT0 (*(volatile struct st_wdt *)(PERI_BASE + 0x00080600)) -#define WDT1 (*(volatile struct st_wdt *)(PERI_BASE + 0x00080620)) - -#endif diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.c deleted file mode 100644 index d88bae003..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.c +++ /dev/null @@ -1,212 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_cgc.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for CGC module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_cgc.h" -/* Start user code for include. Do not edit comment generated here */ -#include "r_reset.h" -#include "r_system.h" -#include "r_typedefs.h" -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -/* Start user code for global. Do not edit comment generated here */ - -#define CPG_WRITE_ENABLE (0x0000A501) -#define CPG_WRITE_DISABLE (0x0000A500) - -#define CPG_CMT0_CLOCK_PCLKD_32 (1) -#define CPG_CMT0_CMI0_ENABLE (1) -#define CPG_CMT0_CONST_100_US (0xEA) -#define CPG_CMT0_START (1) -#define CPG_CMT0_STOP (0) - -#define CPG_CMT_REG_CLEAR (0x0000) - -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -* Function Name: R_CGC_Create -* Description : This function initializes the clock generator. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_CGC_Create(void) -{ - uint16_t w_count; - - /* LOCO circuit disable */ - SYSTEM.LOCOCR.BIT.LCSTP = 1U; - - /* Systen clock control register setting */ - SYSTEM.SCKCR.LONG = _CGC_CKIO_0 | _CGC_TCLK_0 | _CGC_PCLKE_0 | _CGC_PCLKF_0 | _CGC_PCLKG_0 | _CGC_SERICLK_0 | - _CGC_ETCKE_0 | _CGC_ETCKD_0; - - /* Set the CPU frequency for PLL1 */ - SYSTEM.PLL1CR.BIT.CPUCKSEL = _CGC_PLL1_CPUCKSEL_600; - - /* PLL1 circuit enable */ - SYSTEM.PLL1CR2.BIT.PLL1EN = 1U; - - /* Wait 100us for PLL1 stabilization */ - for (w_count = 0U; w_count < _CGC_PLL_WAIT_CYCLE; w_count++) - { - nop(); - } - - /* Set system clock register 2 to PLL1 */ - SYSTEM.SCKCR2.BIT.CKSEL0 = 1U; - - /* Delta-sigma interface operation setting, DSCLK0 and DSCLK1 both in master mode */ - SYSTEM.DSCR.LONG = _CGC_DSSEL0_MASTER | _CGC_DSCLK0_0 | _CGC_DSSEL1_MASTER | _CGC_DSCLK1_0; -} - -/* Start user code for adding. Do not edit comment generated here */ - -/*********************************************************************************************************************** -* Function Name : R_CPG_WriteEnable -* Description : Enables writing to the registers related to CPG function. -* And dummy read the register in order to fix the register value. -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -void R_CPG_WriteEnable(void) -{ - volatile uint32_t dummy = 0; - - UNUSED_VARIABLE(dummy); - - /* Enables writing to the CPG register */ - SYSTEM.PRCR.LONG = CPG_WRITE_ENABLE; - dummy = SYSTEM.PRCR.LONG; - -} - -/*********************************************************************************************************************** - End of function R_CPG_WriteEnable -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* Function Name : R_CPG_WriteDisable -* Description : Disables writing to the registers related to CPG function. -* And dummy read the register in order to fix the register value. -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -void R_CPG_WriteDisable(void) -{ - volatile uint32_t dummy = 0; - - UNUSED_VARIABLE(dummy); - - /* Disables writing to the CPG register */ - SYSTEM.PRCR.LONG = CPG_WRITE_DISABLE; - dummy = SYSTEM.PRCR.LONG; - -} - -/*********************************************************************************************************************** - End of function R_CPG_WriteDisable -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* Function Name : R_CPG_PLLWait -* Description : Wait about 100us for PLL stabilisation by using CMT0 -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -void R_CPG_PLLWait(void) -{ - - /* Enables writing to the registers related to Reset and Low-Power function */ - r_rst_write_enable(); - - /* Release from the CMT0 module-stop state */ - MSTP(CMT0) = 0; - - /* Disables writing to the registers related to Reset and Low-Power function */ - r_rst_write_disable(); - - /* Set CMT0 to 100us interval operation */ - CMT0.CMCR.BIT.CKS = CPG_CMT0_CLOCK_PCLKD_32; - CMT0.CMCR.BIT.CMIE = CPG_CMT0_CMI0_ENABLE; - CMT0.CMCNT = CPG_CMT_REG_CLEAR; - CMT0.CMCOR = CPG_CMT0_CONST_100_US; - - /* Set IRQ21(CMI0) for polling sequence */ - VIC.IEC0.BIT.IEC21 = 1U; - VIC.PLS0.BIT.PLS21 = 1U; - VIC.PIC0.BIT.PIC21 = 1U; - - /* Start CMT0 count */ - CMT.CMSTR0.BIT.STR0 = CPG_CMT0_START; - - /* Wait for 100us (IRQ21 is generated) */ - while ( !(VIC.RAIS0.BIT.RAI21) ) - { - /* Wait */ - } - - /* Stop CMT0 count */ - CMT.CMSTR0.BIT.STR0 = CPG_CMT0_STOP; - - /* Initialise CMT0 settings and clear interrupt detection edge */ - CMT0.CMCR.WORD = CPG_CMT_REG_CLEAR; - CMT0.CMCNT = CPG_CMT_REG_CLEAR; - CMT0.CMCOR = CPG_CMT_REG_CLEAR; - CMT.CMSTR0.WORD = CPG_CMT_REG_CLEAR; - - VIC.PIC0.BIT.PIC21 = 1U; - - /* Enables writing to the registers related to Reset and Low-Power function */ - r_rst_write_enable(); - - /* Set CMT0 to module-stop state */ - MSTP(CMT0) = 1; - - /* Disables writing to the registers related to Reset and Low-Power function */ - r_rst_write_disable(); -} - -/*********************************************************************************************************************** - End of function R_CPG_PLLWait -***********************************************************************************************************************/ - -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.h deleted file mode 100644 index b70f13a67..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc.h +++ /dev/null @@ -1,203 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_cgc.h -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for CGC module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ -#ifndef CGC_H -#define CGC_H - -/*********************************************************************************************************************** -Macro definitions (Register bit) -***********************************************************************************************************************/ -/* - System Clock Control Register (SCKCR) -*/ -/* Peripheral Module Clock G (PCLKG) */ -#define _CGC_PCLKG_0 (0x00000000UL) /* 60 MHz */ -#define _CGC_PCLKG_1 (0x00000001UL) /* 30 MHz */ -#define _CGC_PCLKG_2 (0x00000002UL) /* 15 MHz */ -#define _CGC_PCLKG_3 (0x00000003UL) /* 7.5 MHz */ -/* Peripheral Module Clock F (PCLKF) */ -#define _CGC_PCLKF_0 (0x00000000UL) /* 60 MHz */ -#define _CGC_PCLKF_1 (0x00000004UL) /* 30 MHz */ -#define _CGC_PCLKF_2 (0x00000008UL) /* 15 MHz */ -#define _CGC_PCLKF_3 (0x0000000CUL) /* 7.5 MHz */ -/* Peripheral Module Clock E (PCLKE) */ -#define _CGC_PCLKE_0 (0x00000000UL) /* 75 MHz */ -#define _CGC_PCLKE_1 (0x00000010UL) /* 37.5 MHz */ -#define _CGC_PCLKE_2 (0x00000020UL) /* 18.75 MHz */ -/* External Bus Clock (CKIO) */ -#define _CGC_CKIO_0 (0x00000000UL) /* 75 MHz */ -#define _CGC_CKIO_1 (0x00000100UL) /* 50 MHz */ -#define _CGC_CKIO_2 (0x00000200UL) /* 37.5 MHz */ -#define _CGC_CKIO_3 (0x00000300UL) /* 30 MHz */ -#define _CGC_CKIO_4 (0x00000400UL) /* 25 MHz */ -#define _CGC_CKIO_5 (0x00000500UL) /* 21.43 MHz */ -#define _CGC_CKIO_6 (0x00000600UL) /* 18.75 MHz */ -/* Ether Clock E (ETCLKE) */ -#define _CGC_ETCKE_0 (0x00000000UL) /* 25 MHz */ -#define _CGC_ETCKE_1 (0x00001000UL) /* 50 MHz */ -#define _CGC_ETCKE_2 (0x00003000UL) /* 25 MHz */ -/* Ether Clock D (ETCLKD) */ -#define _CGC_ETCKD_0 (0x00000000UL) /* 12.5 MHz */ -#define _CGC_ETCKD_1 (0x00004000UL) /* 6.25 MHz */ -#define _CGC_ETCKD_2 (0x00008000UL) /* 3.125 MHz */ -#define _CGC_ETCKD_3 (0x0000C000UL) /* 1.563 MHz */ -/* High-Speed Serial Clock (SERICLK) */ -#define _CGC_SERICLK_0 (0x00000000UL) /* 150 MHz */ -#define _CGC_SERICLK_1 (0x00010000UL) /* 120 MHz */ -/* USB Clock (USBMCLK) */ -#define _CGC_UCK_0 (0x00000000UL) /* 50 MHz */ -#define _CGC_UCK_1 (0x00020000UL) /* 24 MHz */ -/* Trace Interface Clock (TCLK) */ -#define _CGC_TCLK_0 (0x00000000UL) /* 150 MHz */ -#define _CGC_TCLK_1 (0x00100000UL) /* 75 MHz */ - -/* - System Clock Control Register 2 (SCKCR2) -*/ -#define _CGC_SKSEL0_PLL0 (0x00000000UL) /* PLL0 */ -#define _CGC_SKSEL0_PLL1 (0x00000001UL) /* PLL1 */ - -/* - Delta-Sigma Interface Clock Control Register (DSCR) -*/ -#define _CGC_DSSEL0_SLAVE (0x00000000UL) /* Supplied from outside the LSI (slave operation) */ -#define _CGC_DSSEL0_MASTER (0x00000001UL) /* Supplied from CGC (master operation) */ -#define _CGC_DSCLK0_0 (0x00000000UL) /* 25 MHz */ -#define _CGC_DSCLK0_1 (0x00000002UL) /* 18.75 MHz */ -#define _CGC_DSCLK0_2 (0x00000004UL) /* 12.5 MHz */ -#define _CGC_DSCLK0_3 (0x00000006UL) /* 9.375 MHz */ -#define _CGC_DSCLK0_4 (0x00000008UL) /* 6.25 MHz */ -#define _CGC_DSCLK0_POL_NORMAL (0x00000000UL) /* Polarity not inverted (master and slave operation) */ -#define _CGC_DSCLK0_POL_INVERT (0x00000010UL) /* Polarity inverted (master and slave operation) */ -#define _CGC_DSCLK0_SLAVE_MCLK0_2 (0x00000000UL) /* Clock input to MCLK0,MCLK1,MCLK2 pins are used */ -#define _CGC_DSCLK0_SLAVE_MCLK0 (0x00000020UL) /* Clock input to MCLK0 pin is used */ -#define _CGC_DSSEL1_SLAVE (0x00000000UL) /* Supplied from outside the LSI (slave operation) */ -#define _CGC_DSSEL1_MASTER (0x00010000UL) /* Supplied from CGC (master operation) */ -#define _CGC_DSCLK1_0 (0x00000000UL) /* 25 MHz */ -#define _CGC_DSCLK1_1 (0x00020000UL) /* 18.75 MHz */ -#define _CGC_DSCLK1_2 (0x00040000UL) /* 12.5 MHz */ -#define _CGC_DSCLK1_3 (0x00060000UL) /* 9.375 MHz */ -#define _CGC_DSCLK1_4 (0x00080000UL) /* 6.25 MHz */ -#define _CGC_DSCLK1_POL_NORMAL (0x00000000UL) /* Polarity not inverted (master and slave operation) */ -#define _CGC_DSCLK1_POL_INVERT (0x00100000UL) /* Polarity inverted (master and slave operation) */ - -/* - PLL1 Control Register (PLL1CR) -*/ -#define _CGC_PLL1_CPUCKSEL_150 (0x00U) /* 150 MHz */ -#define _CGC_PLL1_CPUCKSEL_300 (0x01U) /* 300 MHz */ -#define _CGC_PLL1_CPUCKSEL_450 (0x02U) /* 450 MHz */ -#define _CGC_PLL1_CPUCKSEL_600 (0x03U) /* 600 MHz */ - -/* - PLL1 Control Register 2 (PLL1CR2) -*/ -#define _CGC_PLL1_DISABLE (0x00000000UL) /* PLL1 stops */ -#define _CGC_PLL1_ENABLE (0x00000001UL) /* PLL1 runs */ - -/* - Low-Speed On-Chip Oscillator Control Register (LOCOCR) -*/ -#define _CGC_LOCO_RUN (0x00000000UL) /* LOCO Run */ -#define _CGC_LOCO_STOP (0x00000001UL) /* LOCO Stop */ - -/* - Oscillation Stop Detection Control Register (OSTDCR) -*/ -/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */ -#define _CGC_OSC_STOP_DET_INT_DISABLE (0x00000000UL) /* Stop detection interrupt is disabled */ -#define _CGC_OSC_STOP_DET_INT_ENABLE (0x00000001UL) /* Stop detection interrupt is enabled */ -/* Oscillation Stop Detection Function Enable (OSTDE) */ -#define _CGC_OSC_STOP_DET_DISABLE (0x00000000UL) /* Oscillation stop detection function is disabled */ -#define _CGC_OSC_STOP_DET_ENABLE (0x00000080UL) /* Oscillation stop detection function is enabled */ - -/* - ECM Non-maskable Interrupt Configuration Register 0 (ECMNMICFG0) -*/ -#define _ECM_NMI_OSC_STOP_DISABLE (0x00000000UL) /* Stop detection NMI interrupt is disabled */ -#define _ECM_NMI_OSC_STOP_ENABLE (0x00080000UL) /* Stop detection NMI interrupt is enabled */ - -/* - ECM Maskable Interrupt Configuration Register 0 (ECMMICFG0) -*/ -#define _ECM_MI_OSC_STOP_DISABLE (0x00000000UL) /* Stop detection Maskable interrupt is disabled */ -#define _ECM_MI_OSC_STOP_ENABLE (0x00080000UL) /* Stop detection Maskable interrupt is enabled */ - -/* - Debugging Interface Control Register (DBGIFCNT) -*/ -#define _SWV_SEL_NOOUTPUT (0x00000000UL) /* SWV output is not output */ -#define _SWV_SEL_TDO (0x00000001UL) /* SWV output is output from the TDO pin */ -#define _SWV_SEL_TRACEDATA0 (0x00000002UL) /* SWV output is output from the TRACEDATA0 pin */ -#define _SWV_SEL_TRACECTL (0x00000003UL) /* SWV output is output from the TRACECTL pin */ - - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -#define _CGC_PLL_WAIT_CYCLE (0x1D4CU) /* Wait 100us when switch clock source in PLL0 and PLL1 */ -#define _CGC_LOCO_WAIT_CYCLE (0x0BB8U) /* Wait 40us for LOCO oscillation stabilization */ - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Global functions -***********************************************************************************************************************/ -void R_CGC_Create(void); - -/* Start user code for function. Do not edit comment generated here */ - -void R_CPG_PLLWait(void); -void R_CPG_WriteEnable(void); -void R_CPG_WriteDisable(void); - -#define CPG_CPUCLK_150_MHz (0) -#define CPG_CPUCLK_300_MHz (1) -#define CPG_CPUCLK_450_MHz (2) -#define CPG_CPUCLK_600_MHz (3) - -#define CPG_PLL1_OFF (0) -#define CPG_PLL1_ON (1) - -#define CPG_SELECT_PLL0 (0) -#define CPG_SELECT_PLL1 (1) - -#define CPG_CKIO_75_MHz (0) -#define CPG_CKIO_50_MHz (1) -#define CPG_CKIO_37_5_MHz (2) -#define CPG_CKIO_30_MHz (3) -#define CPG_CKIO_25_MHz (4) -#define CPG_CKIO_21_43_MHz (5) -#define CPG_CKIO_18_75_MHz (6) - -#define CPG_LOCO_ENABLE (0x00000000) -#define CPG_LOCO_DISABLE (0x00000001) - -/* End user code. Do not edit comment generated here */ -#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc_user.c deleted file mode 100644 index debe5a292..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cgc_user.c +++ /dev/null @@ -1,52 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_cgc_user.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for CGC module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_cgc.h" -/* Start user code for include. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -/* Start user code for global. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.h deleted file mode 100644 index c2e456863..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt.h +++ /dev/null @@ -1,112 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_cmt.h -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for CMT module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ -#ifndef CMT_H -#define CMT_H - -/*********************************************************************************************************************** -Macro definitions (Register bit) -***********************************************************************************************************************/ -/* - Compare Match Timer Control Register (CMCR) -*/ -/* Clock Select (CKS[1:0]) */ -#define _CMT_CMCR_CKS_PCLK8 (0x0000U) /* PCLK/8 */ -#define _CMT_CMCR_CKS_PCLK32 (0x0001U) /* PCLK/32 */ -#define _CMT_CMCR_CKS_PCLK128 (0x0002U) /* PCLK/128 */ -#define _CMT_CMCR_CKS_PCLK512 (0x0003U) /* PCLK/512 */ -/* Compare Match Interrupt Enable (CMIE) */ -#define _CMT_CMCR_CMIE_DISABLE (0x0000U) /* Compare match interrupt (CMIn) disabled */ -#define _CMT_CMCR_CMIE_ENABLE (0x0040U) /* Compare match interrupt (CMIn) enabled */ - -/* - Interrupt Priority Level Store Register n (PRLn) -*/ -/* Interrupt Priority Level Store (PRL[3:0]) */ -#define _CMT_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */ -#define _CMT_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */ -#define _CMT_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */ -#define _CMT_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */ -#define _CMT_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */ -#define _CMT_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */ -#define _CMT_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */ -#define _CMT_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */ -#define _CMT_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */ -#define _CMT_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */ -#define _CMT_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */ -#define _CMT_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */ -#define _CMT_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */ -#define _CMT_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */ -#define _CMT_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */ -#define _CMT_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */ -#define _CMT_PRIORITY_LEVEL16 (0x00000000UL) /* Level 16 */ -#define _CMT_PRIORITY_LEVEL17 (0x00000001UL) /* Level 17 */ -#define _CMT_PRIORITY_LEVEL18 (0x00000002UL) /* Level 18 */ -#define _CMT_PRIORITY_LEVEL19 (0x00000003UL) /* Level 19 */ -#define _CMT_PRIORITY_LEVEL20 (0x00000004UL) /* Level 20 */ -#define _CMT_PRIORITY_LEVEL21 (0x00000005UL) /* Level 21 */ -#define _CMT_PRIORITY_LEVEL22 (0x00000006UL) /* Level 22 */ -#define _CMT_PRIORITY_LEVEL23 (0x00000007UL) /* Level 23 */ -#define _CMT_PRIORITY_LEVEL24 (0x00000008UL) /* Level 24 */ -#define _CMT_PRIORITY_LEVEL25 (0x00000009UL) /* Level 25 */ -#define _CMT_PRIORITY_LEVEL26 (0x0000000AUL) /* Level 26 */ -#define _CMT_PRIORITY_LEVEL27 (0x0000000BUL) /* Level 27 */ -#define _CMT_PRIORITY_LEVEL28 (0x0000000CUL) /* Level 28 */ -#define _CMT_PRIORITY_LEVEL29 (0x0000000DUL) /* Level 29 */ -#define _CMT_PRIORITY_LEVEL30 (0x0000000EUL) /* Level 30 */ -#define _CMT_PRIORITY_LEVEL31 (0x0000000FUL) /* Level 31 (lowest) */ - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -/* Compare Match Timer Constant Register (CMCOR) */ -#define _CMT4_CMCOR_VALUE (0x0008U) -/* Compare Match Timer Constant Register (CMCOR) */ -#define _CMT5_CMCOR_VALUE (0x249EU) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Global functions -***********************************************************************************************************************/ -void R_CMT4_Create(void); -void R_CMT4_Start(void); -void R_CMT4_Stop(void); -void R_CMT5_Create(void); -void R_CMT5_Start(void); -void R_CMT5_Stop(void); - -/* Start user code for function. Do not edit comment generated here */ - -/* Counters used to generate user's delay period */ -extern volatile uint32_t g_time_ms_count; -extern volatile uint32_t g_time_us_count; - -/* End user code. Do not edit comment generated here */ -#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt_user.c deleted file mode 100644 index ae2d886af..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_cmt_user.c +++ /dev/null @@ -1,99 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_cmt_user.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for CMT module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_cmt.h" -/* Start user code for include. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -/* Start user code for global. Do not edit comment generated here */ - -/* Counters used to generate user's delay period */ -volatile uint32_t g_time_ms_count; -volatile uint32_t g_time_us_count; - -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -* Function Name: r_cmt_cmi4_interrupt -* Description : This function is CMI4 interrupt service routine. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void r_cmt_cmi4_interrupt(void) -{ - /* Clear the interrupt source CMI4 */ - VIC.PIC9.LONG = 0x00000800UL; - - /* Start user code. Do not edit comment generated here */ - - /* Decrement the count value */ - g_time_us_count--; - - /* End user code. Do not edit comment generated here */ - - /* Dummy write */ - VIC.HVA0.LONG = 0x00000000UL; -} -/*********************************************************************************************************************** -* Function Name: r_cmt_cmi5_interrupt -* Description : This function is CMI5 interrupt service routine. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void r_cmt_cmi5_interrupt(void) -{ - /* Clear the interrupt source CMI5 */ - VIC.PIC9.LONG = 0x00001000UL; - - /* Start user code. Do not edit comment generated here */ - - /* Decrement the count value */ - g_time_ms_count--; - - /* End user code. Do not edit comment generated here */ - - /* Dummy write */ - VIC.HVA0.LONG = 0x00000000UL; -} - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.c deleted file mode 100644 index b8cd5b323..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.c +++ /dev/null @@ -1,102 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_icu.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for ICU module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_icu.h" -/* Start user code for include. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -/* Start user code for global. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -* Function Name: R_ICU_Create -* Description : This function initializes ICU module. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_ICU_Create(void) -{ - - /* Disable IRQ12 interrupt */ - VIC.IEC0.LONG = 0x00010000UL; - - /* Set IRQ12 edge detection type */ - VIC.PLS0.LONG |= 0x00010000UL; - ICU.IRQCR12.BIT.IRQMD = (uint8_t)_ICU_IRQ_EDGE_FALLING; - - /* Enable IRQ12 digital filter */ - ICU.IRQFLTE.BIT.FLTEN12 = 1U; - - /* Set IRQ12 digital filter clock */ - ICU.IRQFLTC.BIT.FCLKSEL12 = _ICU_IRQ12_FILTER_PCLKB_64; - - /* Set IRQ12 Priority */ - VIC.PRL16.LONG = _ICU_PRIORITY_LEVEL3; - - /* Set IRQ12 interupt address */ - VIC.VAD16.LONG = (uint32_t)r_icu_irq12_interrupt; -} -/*********************************************************************************************************************** -* Function Name: R_ICU_IRQ12_Start -* Description : This function enables IRQ12 interrupt. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_ICU_IRQ12_Start(void) -{ - /* Enable IRQ12 interrupt */ - VIC.IEN0.LONG |= 0x00010000UL; -} -/*********************************************************************************************************************** -* Function Name: R_ICU_IRQ12_Stop -* Description : This function disables IRQ12 interrupt. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_ICU_IRQ12_Stop(void) -{ - /* Disable IRQ12 interrupt */ - VIC.IEC0.LONG = 0x00010000UL; -} - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.h deleted file mode 100644 index acd76789a..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu.h +++ /dev/null @@ -1,326 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_icu.h -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for ICU module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ -#ifndef ICU_H -#define ICU_H - -/*********************************************************************************************************************** -Macro definitions (Register bit) -***********************************************************************************************************************/ - -/* - DMAC Software Activation Register (DMASTG) -*/ -/* DMA Unit 0 Software Activation (DMREQ0) */ -#define _DMA_UNIT0_SOFTWARE_ACTIVATION_DISABLE (0x00U) /* DMA transfer is not requested for DMA Unit 0*/ -#define _DMA_UNIT0_SOFTWARE_ACTIVATION_ENABLE (0x01U) /* DMA transfer is requested for DMA Unit 0 */ -/* DMA Unit 1 Software Activation (DMREQ1) */ -#define _DMA_UNIT1_SOFTWARE_ACTIVATION_DISABLE (0x00U) /* DMA transfer is not requested for DMA Unit 1*/ -#define _DMA_UNIT1_SOFTWARE_ACTIVATION_ENABLE (0x02U) /* DMA transfer is requested for DMA Unit 1*/ - -/* - IRQ Control Register i (IRQCRi) (i = 0 to 15) -*/ -/* IRQ Detection Sense Select (IRQMD[1:0]) */ -#define _ICU_IRQ_EDGE_LOW_LEVEL (0x00U) /* Low level */ -#define _ICU_IRQ_EDGE_FALLING (0x01U) /* Falling edge */ -#define _ICU_IRQ_EDGE_RISING (0x02U) /* Rising edge */ -#define _ICU_IRQ_EDGE_BOTH (0x03U) /* Rising and falling edge */ - -/* - IRQ Pin Digital Noise Filter Enable Register 0 (IRQFLTE) -*/ -/* IRQn Digital Noise Filter Enable (FLTEN0n) */ -#define _ICU_IRQn_FILTER_DISABLE (0x00000000UL) /* IRQn digital noise filter is disabled */ -#define _ICU_IRQ0_FILTER_ENABLE (0x00000001UL) /* IRQ0 digital noise filter is enabled */ -#define _ICU_IRQ1_FILTER_ENABLE (0x00000002UL) /* IRQ1 digital noise filter is enabled */ -#define _ICU_IRQ2_FILTER_ENABLE (0x00000004UL) /* IRQ2 digital noise filter is enabled */ -#define _ICU_IRQ3_FILTER_ENABLE (0x00000008UL) /* IRQ3 digital noise filter is enabled */ -#define _ICU_IRQ4_FILTER_ENABLE (0x00000010UL) /* IRQ4 digital noise filter is enabled */ -#define _ICU_IRQ5_FILTER_ENABLE (0x00000020UL) /* IRQ5 digital noise filter is enabled */ -#define _ICU_IRQ6_FILTER_ENABLE (0x00000040UL) /* IRQ6 digital noise filter is enabled */ -#define _ICU_IRQ7_FILTER_ENABLE (0x00000080UL) /* IRQ7 digital noise filter is enabled */ -#define _ICU_IRQ8_FILTER_ENABLE (0x00000100UL) /* IRQ8 digital noise filter is enabled */ -#define _ICU_IRQ9_FILTER_ENABLE (0x00000200UL) /* IRQ9 digital noise filter is enabled */ -#define _ICU_IRQ10_FILTER_ENABLE (0x00000400UL) /* IRQ10 digital noise filter is enabled */ -#define _ICU_IRQ11_FILTER_ENABLE (0x00000800UL) /* IRQ11 digital noise filter is enabled */ -#define _ICU_IRQ12_FILTER_ENABLE (0x00001000UL) /* IRQ12 digital noise filter is enabled */ -#define _ICU_IRQ13_FILTER_ENABLE (0x00002000UL) /* IRQ13 digital noise filter is enabled */ -#define _ICU_IRQ14_FILTER_ENABLE (0x00004000UL) /* IRQ14 digital noise filter is enabled */ -#define _ICU_IRQ15_FILTER_ENABLE (0x00008000UL) /* IRQ15 digital noise filter is enabled */ - -/* - IRQ Pin Digital Filter Setting Register (IRQFLTC) -*/ -/* IRQn Digital Filter Sampling Clock (FCLKSELn[1:0]) */ -#define _ICU_IRQ0_FILTER_PCLKB (0x00U) /* IRQ0 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ0_FILTER_PCLKB_8 (0x01U) /* IRQ0 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ0_FILTER_PCLKB_32 (0x02U) /* IRQ0 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ0_FILTER_PCLKB_64 (0x03U) /* IRQ0 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ1_FILTER_PCLKB (0x00U) /* IRQ1 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ1_FILTER_PCLKB_8 (0x01U) /* IRQ1 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ1_FILTER_PCLKB_32 (0x02U) /* IRQ1 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ1_FILTER_PCLKB_64 (0x03U) /* IRQ1 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ2_FILTER_PCLKB (0x00U) /* IRQ2 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ2_FILTER_PCLKB_8 (0x01U) /* IRQ2 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ2_FILTER_PCLKB_32 (0x02U) /* IRQ2 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ2_FILTER_PCLKB_64 (0x03U) /* IRQ2 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ3_FILTER_PCLKB (0x00U) /* IRQ3 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ3_FILTER_PCLKB_8 (0x01U) /* IRQ3 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ3_FILTER_PCLKB_32 (0x02U) /* IRQ3 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ3_FILTER_PCLKB_64 (0x03U) /* IRQ3 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ4_FILTER_PCLKB (0x00U) /* IRQ4 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ4_FILTER_PCLKB_8 (0x01U) /* IRQ4 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ4_FILTER_PCLKB_32 (0x02U) /* IRQ4 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ4_FILTER_PCLKB_64 (0x03U) /* IRQ4 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ5_FILTER_PCLKB (0x00U) /* IRQ5 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ5_FILTER_PCLKB_8 (0x01U) /* IRQ5 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ5_FILTER_PCLKB_32 (0x02U) /* IRQ5 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ5_FILTER_PCLKB_64 (0x03U) /* IRQ5 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ6_FILTER_PCLKB (0x00U) /* IRQ6 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ6_FILTER_PCLKB_8 (0x01U) /* IRQ6 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ6_FILTER_PCLKB_32 (0x02U) /* IRQ6 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ6_FILTER_PCLKB_64 (0x03U) /* IRQ6 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ7_FILTER_PCLKB (0x00U) /* IRQ7 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ7_FILTER_PCLKB_8 (0x01U) /* IRQ7 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ7_FILTER_PCLKB_32 (0x02U) /* IRQ7 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ7_FILTER_PCLKB_64 (0x03U) /* IRQ7 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ8_FILTER_PCLKB (0x00U) /* IRQ8 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ8_FILTER_PCLKB_8 (0x01U) /* IRQ8 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ8_FILTER_PCLKB_32 (0x02U) /* IRQ8 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ8_FILTER_PCLKB_64 (0x03U) /* IRQ8 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ9_FILTER_PCLKB (0x00U) /* IRQ9 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ9_FILTER_PCLKB_8 (0x01U) /* IRQ9 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ9_FILTER_PCLKB_32 (0x02U) /* IRQ9 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ9_FILTER_PCLKB_64 (0x03U) /* IRQ9 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ10_FILTER_PCLKB (0x00U) /* IRQ10 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ10_FILTER_PCLKB_8 (0x01U) /* IRQ10 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ10_FILTER_PCLKB_32 (0x02U) /* IRQ10 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ10_FILTER_PCLKB_64 (0x03U) /* IRQ10 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ11_FILTER_PCLKB (0x00U) /* IRQ11 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ11_FILTER_PCLKB_8 (0x01U) /* IRQ11 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ11_FILTER_PCLKB_32 (0x02U) /* IRQ11 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ11_FILTER_PCLKB_64 (0x03U) /* IRQ11 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ12_FILTER_PCLKB (0x00U) /* IRQ12 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ12_FILTER_PCLKB_8 (0x01U) /* IRQ12 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ12_FILTER_PCLKB_32 (0x02U) /* IRQ12 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ12_FILTER_PCLKB_64 (0x03U) /* IRQ12 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ13_FILTER_PCLKB (0x00U) /* IRQ13 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ13_FILTER_PCLKB_8 (0x01U) /* IRQ13 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ13_FILTER_PCLKB_32 (0x02U) /* IRQ13 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ13_FILTER_PCLKB_64 (0x03U) /* IRQ13 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ14_FILTER_PCLKB (0x00U) /* IRQ14 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ14_FILTER_PCLKB_8 (0x01U) /* IRQ14 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ14_FILTER_PCLKB_32 (0x02U) /* IRQ14 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ14_FILTER_PCLKB_64 (0x03U) /* IRQ14 sample clock run at every PCLKB/64 cycle */ -#define _ICU_IRQ15_FILTER_PCLKB (0x00U) /* IRQ15 sample clock run at every PCLKB cycle */ -#define _ICU_IRQ15_FILTER_PCLKB_8 (0x01U) /* IRQ15 sample clock run at every PCLKB/8 cycle */ -#define _ICU_IRQ15_FILTER_PCLKB_32 (0x02U) /* IRQ15 sample clock run at every PCLKB/32 cycle */ -#define _ICU_IRQ15_FILTER_PCLKB_64 (0x03U) /* IRQ15 sample clock run at every PCLKB/64 cycle */ - -/* - Interrupt Source Priority Register n (IPRn) -*/ -/* Interrupt Priority Level Select (IPR[3:0]) */ -#define _ICU_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (interrupt disabled) */ -#define _ICU_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */ -#define _ICU_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */ -#define _ICU_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */ -#define _ICU_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */ -#define _ICU_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */ -#define _ICU_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */ -#define _ICU_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */ -#define _ICU_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */ -#define _ICU_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */ -#define _ICU_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */ -#define _ICU_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */ -#define _ICU_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */ -#define _ICU_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */ -#define _ICU_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */ -#define _ICU_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 (highest) */ - -/* - NMI Pin Interrupt Control Register (NMICR) -*/ -/* NMI Detection Sense Selection (NMIMD) */ -#define _ICU_NMI_DETECTION_SENSE_FALLING (0x00U) /* Falling edge */ -#define _ICU_NMI_DETECTION_SENSE_RISING (0x08U) /* Rising edge */ - -/* - DMA Noise Filter Setting Register (DMAINT) -*/ -/* DMA Digital Noise Filter Sampling Clock (DREQFLTC[1:0]) */ -#define _ICU_DMAINT0_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */ -#define _ICU_DMAINT0_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */ -#define _ICU_DMAINT0_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */ -#define _ICU_DMAINT0_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */ -#define _ICU_DMAINT1_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */ -#define _ICU_DMAINT1_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */ -#define _ICU_DMAINT1_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */ -#define _ICU_DMAINT1_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */ -#define _ICU_DMAINT2_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */ -#define _ICU_DMAINT2_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */ -#define _ICU_DMAINT2_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */ -#define _ICU_DMAINT2_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */ - -/* - NMI Pin Digital Noise Filter Setting Register (NMIFLTC) -*/ -/* NMI Digital Noise Filter Sampling Clock (NFCLKSEL[1:0]) */ -#define _ICU_NMI_FILTER_PCLKB (0x00U) /* NMI sample clock is run at every PCLKB cycle */ -#define _ICU_NMI_FILTER_PCLKB_8 (0x01U) /* NMI sample clock is run at every PCLKB/8 cycle */ -#define _ICU_NMI_FILTER_PCLKB_32 (0x02U) /* NMI sample clock is run at every PCLKB/32 cycle */ -#define _ICU_NMI_FILTER_PCLKB_64 (0x03U) /* NMI sample clock is run at every PCLKB/64 cycle */ - -/* - EtherPHY Control Register i (EPHYCRi) (i = 0 to 2) -*/ -/* EtherPHYn interrupt Detection Setting (EPHYMD[1:0]) */ -#define _ICU_ETHERPHY0_EDGE_LOW_LEVEL (0x00U) /* Low level */ -#define _ICU_ETHERPHY0_EDGE_FALLING (0x01U) /* Falling edge */ -#define _ICU_ETHERPHY0_EDGE_RISING (0x02U) /* Rising edge */ -#define _ICU_ETHERPHY0_EDGE_BOTH (0x03U) /* Rising and falling edge */ -#define _ICU_ETHERPHY1_EDGE_LOW_LEVEL (0x00U) /* Low level */ -#define _ICU_ETHERPHY1_EDGE_FALLING (0x01U) /* Falling edge */ -#define _ICU_ETHERPHY1_EDGE_RISING (0x02U) /* Rising edge */ -#define _ICU_ETHERPHY1_EDGE_BOTH (0x03U) /* Rising and falling edge */ -#define _ICU_ETHERPHY2_EDGE_LOW_LEVEL (0x00U) /* Low level */ -#define _ICU_ETHERPHY2_EDGE_FALLING (0x01U) /* Falling edge */ -#define _ICU_ETHERPHY2_EDGE_RISING (0x02U) /* Rising edge */ -#define _ICU_ETHERPHY2_EDGE_BOTH (0x03U) /* Rising and falling edge */ - -/* - EtherPHY Interrupt Request Pin Digital Noise Filter Enable Register 0 (EPHYFLTE) -*/ -/* EtherPHYn Interrupt Digital Noise Filter Enable (EFLTENn) */ -#define _ICU_ETHERPHYn_FILTER_DISABLE (0x00U) /* ETHER PHY0 digital noise filter is disabled */ -#define _ICU_ETHERPHY0_FILTER_ENABLE (0x01U) /* ETHER PHY0 digital noise filter is enabled */ -#define _ICU_ETHERPHY1_FILTER_ENABLE (0x01U) /* ETHER PHY1 digital noise filter is enabled */ -#define _ICU_ETHERPHY2_FILTER_ENABLE (0x01U) /* ETHER PHY2 digital noise filter is enabled */ - -/* - EtherPHY Interrupt Request Pin Digital Filter Setting Register (EPHYFLTC) -*/ -/* EtherPHYn Interrupts Digital Noise Filter Sampling Clock (EFCLKSELn[1:0]) */ -#define _ICU_ETHPHYI0_FILTER_PCLKB (0x00U) /* ETHER PHY0 sample clock is run at every PCLKB cycle */ -#define _ICU_ETHPHYI0_FILTER_PCLKB_8 (0x01U) /* ETHER PHY0 sample clock is run at every PCLKB/8 cycle */ -#define _ICU_ETHPHYI0_FILTER_PCLKB_32 (0x02U) /* ETHER PHY0 sample clock is run at every PCLKB/32 cycle */ -#define _ICU_ETHPHYI0_FILTER_PCLKB_64 (0x03U) /* ETHER PHY0 sample clock is run at every PCLKB/64 cycle */ -#define _ICU_ETHPHYI1_FILTER_PCLKB (0x00U) /* ETHER PHY1 sample clock is run at every PCLKB cycle */ -#define _ICU_ETHPHYI1_FILTER_PCLKB_8 (0x01U) /* ETHER PHY1 sample clock is run at every PCLKB/8 cycle */ -#define _ICU_ETHPHYI1_FILTER_PCLKB_32 (0x02U) /* ETHER PHY1 sample clock is run at every PCLKB/32 cycle */ -#define _ICU_ETHPHYI1_FILTER_PCLKB_64 (0x03U) /* ETHER PHY1 sample clock is run at every PCLKB/64 cycle */ -#define _ICU_ETHPHYI2_FILTER_PCLKB (0x00U) /* ETHER PHY2 sample clock is run at every PCLKB cycle */ -#define _ICU_ETHPHYI2_FILTER_PCLKB_8 (0x01U) /* ETHER PHY2 sample clock is run at every PCLKB/8 cycle */ -#define _ICU_ETHPHYI2_FILTER_PCLKB_32 (0x02U) /* ETHER PHY2 sample clock is run at every PCLKB/32 cycle */ -#define _ICU_ETHPHYI2_FILTER_PCLKB_64 (0x03U) /* ETHER PHY2 sample clock is run at every PCLKB/64 cycle */ - -/* - External DMA Request Pin Digital Noise Enable Register (DREQFLTE) -*/ -/* DREQn Digital Noise Filter Enable (DFLTENn) */ -#define _ICU_DREQn_FILTER_DISABLE (0x00U) /* Digital noise filter is disabled */ -#define _ICU_DREQ0_FILTER_ENABLE (0x01U) /* DREQ0 Digital noise filter is enabled */ -#define _ICU_DREQ1_FILTER_ENABLE (0x01U) /* DREQ1 Digital noise filter is enabled */ -#define _ICU_DREQ2_FILTER_ENABLE (0x01U) /* DREQ2 Digital noise filter is enabled */ - -/* - External DMA Request Pin Digital Noise Setting Register (DREQFLTC) -*/ -/* DREQn Digital Noise Filter Sampling Clock (DFCLKSELn[1:0]) */ -#define _ICU_DREQ0_FILTER_PCLKB (0x00U) /* DREQ0 sample clock is run at every PCLKB cycle */ -#define _ICU_DREQ0_FILTER_PCLKB_8 (0x01U) /* DREQ0 sample clock is run at every PCLKB/8 cycle */ -#define _ICU_DREQ0_FILTER_PCLKB_32 (0x02U) /* DREQ0 sample clock is run at every PCLKB/32 cycle */ -#define _ICU_DREQ0_FILTER_PCLKB_64 (0x03U) /* DREQ0 sample clock is run at every PCLKB/64 cycle */ -#define _ICU_DREQ1_FILTER_PCLKB (0x00U) /* DREQ1 sample clock is run at every PCLKB cycle */ -#define _ICU_DREQ1_FILTER_PCLKB_8 (0x01U) /* DREQ1 sample clock is run at every PCLKB/8 cycle */ -#define _ICU_DREQ1_FILTER_PCLKB_32 (0x02U) /* DREQ1 sample clock is run at every PCLKB/32 cycle */ -#define _ICU_DREQ1_FILTER_PCLKB_64 (0x03U) /* DREQ1 sample clock is run at every PCLKB/64 cycle */ -#define _ICU_DREQ2_FILTER_PCLKB (0x00U) /* DREQ2 sample clock is run at every PCLKB cycle */ -#define _ICU_DREQ2_FILTER_PCLKB_8 (0x01U) /* DREQ2 sample clock is run at every PCLKB/8 cycle */ -#define _ICU_DREQ2_FILTER_PCLKB_32 (0x02U) /* DREQ2 sample clock is run at every PCLKB/32 cycle */ -#define _ICU_DREQ2_FILTER_PCLKB_64 (0x03U) /* DREQ2 sample clock is run at every PCLKB/64 cycle */ - -/* - User Mode Enable Register 0 (UEN0) -*/ -/* Interrupt control register access selection (UE) */ -#define _ICU_UEN0_CTRL_REG_ACCESS_DISABLE (0x00000000UL) /* Disables access in user mode. */ -#define _ICU_UEN0_CTRL_REG_ACCESS_ENABLE (0x00000001UL) /* Enables access in user mode. */ - -/* - User Mode Enable Register 1 (UEN1) -*/ -/* Interrupt control register access selection (UE) */ -#define _ICU_UEN1_CTRL_REG_ACCESS_DISABLE (0x00000000UL) /* Disables access in user mode. */ -#define _ICU_UEN1_CTRL_REG_ACCESS_ENABLE (0x00000001UL) /* Enables access in user mode. */ - - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Global functions -***********************************************************************************************************************/ -void R_ICU_Create(void); -void R_ICU_IRQ12_Start(void); -void R_ICU_IRQ12_Stop(void); - -/* Start user code for function. Do not edit comment generated here */ - -#define SW1_PRESS_FLG (0x01) -#define SW2_PRESS_FLG (0x02) -#define SW3_PRESS_FLG (0x04) - -#define SW1_HELD_FLG (0x10) -#define SW2_HELD_FLG (0x20) -#define SW3_HELD_FLG (0x40) - -#define SW1_SET_FLG_MASK (0xEE) -#define SW2_SET_FLG_MASK (0xDD) -#define SW3_SET_FLG_MASK (0xBB) - -#define SW_ALL_OFF (0xF8) - -#define SW1_INPUT_STATE (PORT3.PIDR.BIT.B5) -#define SW2_INPUT_STATE (PORTN.PIDR.BIT.B5) -#define SW3_INPUT_STATE (PORT4.PIDR.BIT.B4) - -#define SW1_OUTPUT_PIN (PORT3.PODR.BIT.B5) -#define SW2_OUTPUT_PIN (PORTN.PODR.BIT.B5) -#define SW3_OUTPUT_PIN (PORT4.PODR.BIT.B4) - -/* Stores switch states detected via interrupts */ -extern volatile uint8_t g_switch_press_flg; - -/* End user code. Do not edit comment generated here */ -#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu_user.c deleted file mode 100644 index 8dac89a7c..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_icu_user.c +++ /dev/null @@ -1,76 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_icu_user.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for ICU module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_icu.h" -/* Start user code for include. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -/* Start user code for global. Do not edit comment generated here */ - -/* Stores switch states detected via interrupts */ -volatile uint8_t g_switch_press_flg = 0u; - -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -* Function Name: r_icu_irq12_interrupt -* Description : This function handles the irqn pin interrupt. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -#ifdef __ICCARM__ - __irq __arm -#endif /* __ICCARM__ */ -void r_icu_irq12_interrupt(void) -{ - VIC.PIC0.LONG = 0x00010000UL; - /* Start user code. Do not edit comment generated here */ - - /* Set global switch flag to indicate SW3 is pressed */ - g_switch_press_flg |= SW3_PRESS_FLG; - - /* End user code. Do not edit comment generated here */ - VIC.HVA0.LONG = 0x00000000UL; -} - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h deleted file mode 100644 index 2f0f9357c..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_interrupthandlers.h +++ /dev/null @@ -1,79 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_interrupthandlers.h -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file declares interrupt handlers. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ -#ifndef INTERRUPT_HANDLERS_H -#define INTERRUPT_HANDLERS_H - -/*********************************************************************************************************************** -Macro definitions (Register bit) -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Global functions -***********************************************************************************************************************/ -/* FIQ exception handler */ -#ifdef __ICCARM__ - __irq __arm void r_fiq_handler(void); - - /* ICU IRQ12 */ - __irq __arm void r_icu_irq12_interrupt(void); - - /* RSPI1 SPTI1 */ - __irq __arm void r_rspi1_transmit_interrupt(void); - - /* RSPI1 SPEI1 */ - __irq __arm void r_rspi1_error_interrupt(void); - - /* RSPI1 SPII1 */ - __irq __arm void r_rspi1_idle_interrupt(void); -#endif /* __ICCARM__ */ - -#ifdef __GNUC__ - void r_fiq_handler(void) __attribute__((interrupt ("FIQ"))); - - /* ICU IRQ12 */ - void r_icu_irq12_interrupt(void) __attribute__((interrupt ("IRQ"))); - - /* RSPI1 SPTI1 */ - void r_rspi1_transmit_interrupt(void) __attribute__((interrupt ("IRQ"))); - - /* RSPI1 SPEI1 */ - void r_rspi1_error_interrupt(void) __attribute__((interrupt ("IRQ"))); - - /* RSPI1 SPII1 */ - void r_rspi1_idle_interrupt(void) __attribute__((interrupt ("IRQ"))); -#endif /* __GNUC__ */ - -#endif diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_intprg.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_intprg.c deleted file mode 100644 index 256ffaae7..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_intprg.c +++ /dev/null @@ -1,87 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_intprg.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : Set the non-maskable interrupt. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -/*********************************************************************************************************************** -* Function Name: r_set_exception_handler -* Description : None -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void r_set_exception_handler(void) -{ - uint32_t *pointer; - - /* FIQ exception handler address */ - pointer = (uint32_t *)0x1c; - - /* Branch to next address instruction */ - *pointer ++ = 0xeaffffff; - - /* LDR PC,[PC, #-0x04], load r_fiq_handler address to PC */ - *pointer ++ = 0xe51ff004; - - /* DC32 r_fiq_handler, define the r_fiq_handler address */ - *pointer = (uint32_t)r_fiq_handler; - - /* Start user code. Do not edit comment generated here */ - /* End user code. Do not edit comment generated here */ -} -/*********************************************************************************************************************** -* Function Name: r_fiq_handler -* Description : None -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -#ifdef __ICCARM__ - __irq __arm -#endif /* __ICCARM__ */ -void r_fiq_handler(void) -{ - while(1); - /* Start user code. Do not edit comment generated here */ - /* End user code. Do not edit comment generated here */ -} - - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_macrodriver.h deleted file mode 100644 index 79afd916a..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_macrodriver.h +++ /dev/null @@ -1,149 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_macrodriver.h -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements general head file. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ -#ifndef MODULEID_H -#define MODULEID_H -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include -#include "iodefine.h" -#include "r_cg_interrupthandlers.h" -#include "r_cg_mpc.h" - - -/*********************************************************************************************************************** -Macro definitions (Register bit) -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -#ifndef __TYPEDEF__ -#define DI() asm("cpsid i") /* Disable IRQ interrupt (Set CPSR.I bit to 1) */ -#define EI() asm("cpsie i") /* Enable IRQ interrupt (Clear CPSR.I bit to 0) */ -#define nop() asm("nop") - -/* Status list definition */ -#define MD_STATUSBASE (0x00U) -#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ -#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ -#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ -#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ -#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ - -/* Error list definition */ -#define MD_ERRORBASE (0x80U) -#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ -#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ -#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ -#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ -#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ -#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ -#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ - -/* MSTP macro definition */ -#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPCRA0 -#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPCRA1 -#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPCRA2 -#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPCRA3 -#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPCRA4 -#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPCRA5 -#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPCRA6 -#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPCRA7 -#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPCRA8 -#define MSTP_GPTA SYSTEM.MSTPCRA.BIT.MSTPCRA9 -#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPCRA11 - -#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPCRB1 -#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPCRB2 -#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPCRB3 -#define MSTP_SCIFA4 SYSTEM.MSTPCRB.BIT.MSTPCRB5 -#define MSTP_SCIFA3 SYSTEM.MSTPCRB.BIT.MSTPCRB6 -#define MSTP_SCIFA2 SYSTEM.MSTPCRB.BIT.MSTPCRB7 -#define MSTP_SCIFA1 SYSTEM.MSTPCRB.BIT.MSTPCRB8 -#define MSTP_SCIFA0 SYSTEM.MSTPCRB.BIT.MSTPCRB9 -#define MSTP_RSPI3 SYSTEM.MSTPCRB.BIT.MSTPCRB10 -#define MSTP_RSPI2 SYSTEM.MSTPCRB.BIT.MSTPCRB11 -#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPCRB12 -#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPCRB13 -#define MSTP_ETHERSW SYSTEM.MSTPCRB.BIT.MSTPCRB14 -#define MSTP_ECATC SYSTEM.MSTPCRB.BIT.MSTPCRB15 -#define MSTP_EMDIO SYSTEM.MSTPCRB.BIT.MSTPCRB16 -#define MSTP_ERMII SYSTEM.MSTPCRB.BIT.MSTPCRB17 -#define MSTP_HWRTOS SYSTEM.MSTPCRB.BIT.MSTPCRB18 -#define MSTP_CLKOUT25M SYSTEM.MSTPCRB.BIT.MSTPCRB19 - -#define MSTP_USB SYSTEM.MSTPCRC.BIT.MSTPCRC1 -#define MSTP_DSMIF SYSTEM.MSTPCRC.BIT.MSTPCRC2 -#define MSTP_TEMPS SYSTEM.MSTPCRC.BIT.MSTPCRC3 -#define MSTP_S12ADC1 SYSTEM.MSTPCRC.BIT.MSTPCRC4 -#define MSTP_S12ADC0 SYSTEM.MSTPCRC.BIT.MSTPCRC5 -#define MSTP_ELC SYSTEM.MSTPCRC.BIT.MSTPCRC6 -#define MSTP_BSC SYSTEM.MSTPCRC.BIT.MSTPCRC7 -#define MSTP_CKIO SYSTEM.MSTPCRC.BIT.MSTPCRC8 -#define MSTP_SPIBSC SYSTEM.MSTPCRC.BIT.MSTPCRC9 -#define MSTP_DOC SYSTEM.MSTPCRC.BIT.MSTPCRC10 -#define MSTP_CRC SYSTEM.MSTPCRC.BIT.MSTPCRC11 -#define MSTP_CLMA2 SYSTEM.MSTPCRC.BIT.MSTPCRC12 -#define MSTP_CLMA1 SYSTEM.MSTPCRC.BIT.MSTPCRC13 -#define MSTP_CLMA0 SYSTEM.MSTPCRC.BIT.MSTPCRC14 - -#define MSTP_SSI SYSTEM.MSTPCRD.BIT.MSTPCRD2 - -#define MSTP_DMAC1 SYSTEM.MSTPCRE.BIT.MSTPCRE4 -#define MSTP_DMAC0 SYSTEM.MSTPCRE.BIT.MSTPCRE5 - -#define MSTP_CORESIGHT SYSTEM.MSTPCRF.BIT.MSTPCRF0 - -#define __MSTP( x ) MSTP ## x -#define _MSTP( x ) __MSTP( x ) -#define MSTP( x ) _MSTP( _ ## x ) -#endif - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ -#ifndef __TYPEDEF__ - #ifndef __ICCARM__ - typedef signed char int8_t; - typedef unsigned char uint8_t; - typedef signed short int16_t; - typedef unsigned short uint16_t; - typedef signed long int32_t; - typedef unsigned long uint32_t; - #endif /* __ICCARM__ */ - typedef unsigned short MD_STATUS; - #define __TYPEDEF__ -#endif - - -/*********************************************************************************************************************** -Global functions -***********************************************************************************************************************/ - -#endif diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.c deleted file mode 100644 index 56a770f87..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.c +++ /dev/null @@ -1,155 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_mpc.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : Setting of port and mpc registers. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -#include "r_typedefs.h" -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_mpc.h" -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* Function Name: R_MPC_Create -* Description : This function initializes the Port I/O. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_MPC_Create(void) -{ - /* Set RSPCK1 pin */ - MPC.PN3PFS.BYTE |= 0x0EU; - PORTN.PMR.BYTE |= 0x08U; - /* Set MOSI1 pin */ - MPC.PN2PFS.BYTE |= 0x0EU; - PORTN.PMR.BYTE |= 0x04U; - /* Set MISO1 pin */ - MPC.PN1PFS.BYTE |= 0x0EU; - PORTN.PMR.BYTE |= 0x02U; - /* Set SSL10 pin */ - MPC.PN0PFS.BYTE |= 0x0EU; - PORTN.PMR.BYTE |= 0x01U; - /* Set SSL11 pin */ - MPC.PN4PFS.BYTE |= 0x0EU; - PORTN.PMR.BYTE |= 0x10U; - /* Set TXD2 pin */ - MPC.P91PFS.BYTE |= 0x0BU; - PORT9.PMR.BYTE |= 0x02U; - /* Set RXD2 pin */ - MPC.P92PFS.BYTE |= 0x0BU; - PORT9.PMR.BYTE |= 0x04U; - /* Set IRQ12 pin */ - MPC.P44PFS.BYTE |= 0x40U; - PORT4.PMR.BYTE &= 0xEFU; - PORT4.PDR.WORD &= 0xFEFFU; - PORT4.PDR.WORD |= 0x0200U; - /* Set TIOCB9 pin */ - MPC.PL0PFS.BYTE |= 0x03U; - PORTL.PMR.BYTE |= 0x01U; - /* Set TIOCC9 pin */ - MPC.PU4PFS.BYTE |= 0x03U; - PORTU.PMR.BYTE |= 0x10U; - /* Set TIOCD9 pin */ - MPC.PN5PFS.BYTE |= 0x03U; - PORTN.PMR.BYTE |= 0x20U; - - R_MPC_Create_UserInit(); -} -/*********************************************************************************************************************** -* Function Name: R_MPC_Create_UserInit -* Description : This function adds user code after initializing modules pin setting. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_MPC_Create_UserInit(void) -{ - /* Start user code. Do not edit comment generated here */ - /* End user code. Do not edit comment generated here */ -} - -/* Start user code for adding. Do not edit comment generated here */ - -/*********************************************************************************************************************** -* Function Name : R_MPC_WriteEnable -* Description : Enables writing to the PmnPFS register (m = 0-9, A-U, n = 0-7). - And dummy read the register in order to fix the register value. -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -void R_MPC_WriteEnable(void) -{ - volatile uint8_t dummy=0; - - UNUSED_VARIABLE(dummy); - - /* Enables writing to the PmnPFS register */ - MPC.PWPR.BYTE = MPC_PFSWE_WRITE_ENABLE; - dummy = MPC.PWPR.BYTE; - MPC.PWPR.BYTE = MPC_PFS_WRITE_ENABLE; - dummy = MPC.PWPR.BYTE; - -} - -/*********************************************************************************************************************** - End of function R_MPC_WriteEnable -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* Function Name : R_MPC_WriteDisable -* Description : Disables writing to the PmnPFS register (m = 0-9, A-U, n = 0-7). - And dummy read the register in order to fix the register value. -* Arguments : none -* Return Value : none -***********************************************************************************************************************/ -void R_MPC_WriteDisable(void) -{ - volatile uint8_t dummy=0; - - UNUSED_PARAM(dummy); - - /* Disables writing to the PmnPFS register */ - MPC.PWPR.BYTE = MPC_PFS_WRITE_DISABLE; - dummy = MPC.PWPR.BYTE; - -} - -/*********************************************************************************************************************** - End of function R_MPC_WriteDisable -***********************************************************************************************************************/ - -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.h deleted file mode 100644 index 1ebdf96ba..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_mpc.h +++ /dev/null @@ -1,49 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_mpc.h -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : Header file of mpc file. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ -#ifndef _MPC_H -#define _MPC_H - -/*********************************************************************************************************************** -Macro definitions (Register bit) -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Global functions -***********************************************************************************************************************/ -void R_MPC_Create(void); -void R_MPC_Create_UserInit(void); - -#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.c deleted file mode 100644 index 4c5032379..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.c +++ /dev/null @@ -1,69 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_port.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for Port module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_port.h" -/* Start user code for include. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -/* Start user code for global. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -* Function Name: R_PORT_Create -* Description : This function initializes the Port I/O. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_PORT_Create(void) -{ - PORT5.PODR.BYTE = _Pm1_OUTPUT_1; - PORT6.PODR.BYTE = _Pm7_OUTPUT_1; - PORT5.PDR.WORD = _Pm1_MODE_OUTPUT | _Pm6_MODE_OUTPUT; - PORT6.PDR.WORD = _Pm7_MODE_OUTPUT; - PORT7.PDR.WORD = _Pm4_MODE_OUTPUT | _Pm6_MODE_OUTPUT | _Pm7_MODE_OUTPUT; - PORTA.PDR.WORD = _Pm0_MODE_OUTPUT; - PORTF.PDR.WORD = _Pm7_MODE_OUTPUT; - PORTM.PDR.WORD = _Pm2_MODE_OUTPUT | _Pm3_MODE_OUTPUT; -} - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.h deleted file mode 100644 index f92e679da..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port.h +++ /dev/null @@ -1,135 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_port.h -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for Port module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ -#ifndef PORT_H -#define PORT_H - -/*********************************************************************************************************************** -Macro definitions (Register bit) -***********************************************************************************************************************/ -/* - Port Direction Register (PDR) -*/ -/* Pmn Direction Control (B0 - B15) */ -#define _Pm0_MODE_NOT_USED (0x0000U) /* Pm0 not used (Hi-z input protection) */ -#define _Pm0_MODE_INPUT (0x0002U) /* Pm0 as input */ -#define _Pm0_MODE_OUTPUT (0x0003U) /* Pm0 as output */ -#define _Pm1_MODE_NOT_USED (0x0000U) /* Pm1 not used (Hi-z input protection) */ -#define _Pm1_MODE_INPUT (0x0008U) /* Pm1 as input */ -#define _Pm1_MODE_OUTPUT (0x000CU) /* Pm1 as output */ -#define _Pm2_MODE_NOT_USED (0x0000U) /* Pm2 not used (Hi-z input protection) */ -#define _Pm2_MODE_INPUT (0x0020U) /* Pm2 as input */ -#define _Pm2_MODE_OUTPUT (0x0030U) /* Pm2 as output */ -#define _Pm3_MODE_NOT_USED (0x0000U) /* Pm3 not used (Hi-z input protection) */ -#define _Pm3_MODE_INPUT (0x0080U) /* Pm3 as input */ -#define _Pm3_MODE_OUTPUT (0x00C0U) /* Pm3 as output */ -#define _Pm4_MODE_NOT_USED (0x0000U) /* Pm4 not used (Hi-z input protection) */ -#define _Pm4_MODE_INPUT (0x0200U) /* Pm4 as input */ -#define _Pm4_MODE_OUTPUT (0x0300U) /* Pm4 as output */ -#define _Pm5_MODE_NOT_USED (0x0000U) /* Pm5 not used (Hi-z input protection) */ -#define _Pm5_MODE_INPUT (0x0800U) /* Pm5 as input */ -#define _Pm5_MODE_OUTPUT (0x0C00U) /* Pm5 as output */ -#define _Pm6_MODE_NOT_USED (0x0000U) /* Pm6 not used (Hi-z input protection) */ -#define _Pm6_MODE_INPUT (0x2000U) /* Pm6 as input */ -#define _Pm6_MODE_OUTPUT (0x3000U) /* Pm6 as output */ -#define _Pm7_MODE_NOT_USED (0x0000U) /* Pm7 not used (Hi-z input protection) */ -#define _Pm7_MODE_INPUT (0x8000U) /* Pm7 as input */ -#define _Pm7_MODE_OUTPUT (0xC000U) /* Pm7 as output */ - -/* - Port Output Data Register (PODR) -*/ -/* Pmn Output Data Store (B0 - B7) */ -#define _Pm0_OUTPUT_0 (0x00U) /* Output low at B0 */ -#define _Pm0_OUTPUT_1 (0x01U) /* Output high at B0 */ -#define _Pm1_OUTPUT_0 (0x00U) /* Output low at B1 */ -#define _Pm1_OUTPUT_1 (0x02U) /* Output high at B1 */ -#define _Pm2_OUTPUT_0 (0x00U) /* Output low at B2 */ -#define _Pm2_OUTPUT_1 (0x04U) /* Output high at B2 */ -#define _Pm3_OUTPUT_0 (0x00U) /* Output low at B3 */ -#define _Pm3_OUTPUT_1 (0x08U) /* Output high at B3 */ -#define _Pm4_OUTPUT_0 (0x00U) /* Output low at B4 */ -#define _Pm4_OUTPUT_1 (0x10U) /* Output high at B4 */ -#define _Pm5_OUTPUT_0 (0x00U) /* Output low at B5 */ -#define _Pm5_OUTPUT_1 (0x20U) /* Output high at B5 */ -#define _Pm6_OUTPUT_0 (0x00U) /* Output low at B6 */ -#define _Pm6_OUTPUT_1 (0x40U) /* Output high at B6 */ -#define _Pm7_OUTPUT_0 (0x00U) /* Output low at B7 */ -#define _Pm7_OUTPUT_1 (0x80U) /* Output high at B7 */ - -/* - Pull-Up/Pull-Down Control Register (PCR) -*/ -/* Pmn Input Pull-Up Resistor Control (B0 - B15) */ -#define _Pm0_PULLUPDOWN_DISABLE (0x0000U) /* Pm0 pull-up resistor and pull-down resistor not connected */ -#define _Pm0_PULLUPDOWN_PULLDOWN_ON (0x0001U) /* Pm0 pull-down resistor connected */ -#define _Pm0_PULLUPDOWN_PULLUP_ON (0x0002U) /* Pm0 pull-up resistor connected */ -#define _Pm1_PULLUPDOWN_DISABLE (0x0000U) /* Pm1 pull-up resistor and pull-down resistor not connected */ -#define _Pm1_PULLUPDOWN_PULLDOWN_ON (0x0004U) /* Pm1 pull-down resistor connected */ -#define _Pm1_PULLUPDOWN_PULLUP_ON (0x0008U) /* Pm1 pull-up resistor connected */ -#define _Pm2_PULLUPDOWN_DISABLE (0x0000U) /* Pm2 pull-up resistor and pull-down resistor not connected */ -#define _Pm2_PULLUPDOWN_PULLDOWN_ON (0x0010U) /* Pm2 pull-down resistor connected */ -#define _Pm2_PULLUPDOWN_PULLUP_ON (0x0020U) /* Pm2 pull-up resistor connected */ -#define _Pm3_PULLUPDOWN_DISABLE (0x0000U) /* Pm3 pull-up resistor and pull-down resistor not connected */ -#define _Pm3_PULLUPDOWN_PULLDOWN_ON (0x0040U) /* Pm3 pull-down resistor connected */ -#define _Pm3_PULLUPDOWN_PULLUP_ON (0x0080U) /* Pm3 pull-up resistor connected */ -#define _Pm4_PULLUPDOWN_DISABLE (0x0000U) /* Pm4 pull-up resistor and pull-down resistor not connected */ -#define _Pm4_PULLUPDOWN_PULLDOWN_ON (0x0100U) /* Pm4 pull-down resistor connected */ -#define _Pm4_PULLUPDOWN_PULLUP_ON (0x0200U) /* Pm4 pull-up resistor connected */ -#define _Pm5_PULLUPDOWN_DISABLE (0x0000U) /* Pm5 pull-up resistor and pull-down resistor not connected */ -#define _Pm5_PULLUPDOWN_PULLDOWN_ON (0x0400U) /* Pm5 pull-down resistor connected */ -#define _Pm5_PULLUPDOWN_PULLUP_ON (0x0800U) /* Pm5 pull-up resistor connected */ -#define _Pm6_PULLUPDOWN_DISABLE (0x0000U) /* Pm6 pull-up resistor and pull-down resistor not connected */ -#define _Pm6_PULLUPDOWN_PULLDOWN_ON (0x1000U) /* Pm6 pull-down resistor connected */ -#define _Pm6_PULLUPDOWN_PULLUP_ON (0x2000U) /* Pm6 pull-up resistor connected */ -#define _Pm7_PULLUPDOWN_DISABLE (0x0000U) /* Pm7 pull-up resistor and pull-down resistor not connected */ -#define _Pm7_PULLUPDOWN_PULLDOWN_ON (0x4000U) /* Pm7 pull-down resistor connected */ -#define _Pm7_PULLUPDOWN_PULLUP_ON (0x8000U) /* Pm7 pull-up resistor connected */ - -/* - Drive Capacity Control Register (DSCR) -*/ -/* P10 Drive Capacity Control (B0) */ -#define _Pm0_HIDRV_OFF (0x0000U) /* P10 Normal drive output */ -#define _Pm0_HIDRV_ON (0x0001U) /* P10 High-drive output */ - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Global functions -***********************************************************************************************************************/ -void R_PORT_Create(void); - -/* Start user code for function. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port_user.c deleted file mode 100644 index db2c2b166..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_port_user.c +++ /dev/null @@ -1,52 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_port_user.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for Port module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_port.h" -/* Start user code for include. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -/* Start user code for global. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.c deleted file mode 100644 index 2e9325ae0..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.c +++ /dev/null @@ -1,196 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_rspi.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for RSPI module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_rspi.h" -/* Start user code for include. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -const uint32_t * gp_rspi1_tx_address; /* RSPI1 transmit buffer address */ -uint16_t g_rspi1_tx_count; /* RSPI1 transmit data number */ -/* Start user code for global. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - - - -/*********************************************************************************************************************** -* Function Name: R_RSPI1_Create -* Description : This function initializes the RSPI1 module. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_RSPI1_Create(void) -{ - /* Disable RSPI interrupts */ - VIC.IEC2.LONG = 0x00200000UL; /* Disable SPTI1 interrupt */ - VIC.IEC2.LONG = 0x00400000UL; /* Disable SPEI1 interrupt */ - VIC.IEC2.LONG = 0x00800000UL; /* Disable SPII1 interrupt */ - - /* Set interrupt detection type */ - VIC.PLS2.LONG |= 0x00200000UL; /* Set SPTI1 edge detection interrupt */ - - /* Cancel RSPI module stop state */ - MSTP(RSPI1) = 0U; - - /* Disable RSPI function */ - RSPI1.SPCR.BIT.SPE = 0U; - - /* Set control registers */ - RSPI1.SPPCR.BYTE = _RSPI_MOSI_LEVEL_HIGH | _RSPI_MOSI_FIXING_MOIFV_BIT | _RSPI_OUTPUT_PIN_CMOS | _RSPI_LOOPBACK_DISABLED | _RSPI_LOOPBACK2_DISABLED; - RSPI1.SPBR = _RSPI1_DIVISOR; - RSPI1.SPDCR.BYTE = _RSPI_ACCESS_LONGWORD | _RSPI_FRAMES_1; - RSPI1.SPSCR.BYTE = _RSPI_SEQUENCE_LENGTH_1; - RSPI1.SSLP.BYTE = _RSPI_SSL0_POLARITY_LOW | _RSPI_SSL1_POLARITY_LOW; - RSPI1.SPCKD.BYTE = _RSPI_RSPCK_DELAY_1; - RSPI1.SSLND.BYTE = _RSPI_SSL_NEGATION_DELAY_1; - RSPI1.SPND.BYTE = _RSPI_NEXT_ACCESS_DELAY_1; - RSPI1.SPCR2.BYTE = _RSPI_PARITY_DISABLE; - RSPI1.SPCMD0.WORD = _RSPI_RSPCK_SAMPLING_EVEN | _RSPI_RSPCK_POLARITY_HIGH | _RSPI_BASE_BITRATE_1 | - _RSPI_SIGNAL_ASSERT_SSL0 | _RSPI_SSL_KEEP_DISABLE | _RSPI_DATA_LENGTH_BITS_8 | - _RSPI_MSB_FIRST | _RSPI_NEXT_ACCESS_DELAY_DISABLE | _RSPI_NEGATION_DELAY_DISABLE | - _RSPI_RSPCK_DELAY_DISABLE; - - /* Set SPTI1 priority level */ - VIC.PRL85.LONG = _RSPI_PRIORITY_LEVEL6; - - /* Set SPEI1 priority level */ - VIC.PRL86.LONG = _RSPI_PRIORITY_LEVEL5; - - /* Set SPII1 priority level */ - VIC.PRL87.LONG = _RSPI_PRIORITY_LEVEL7; - - /* Set SPTI1 interrupt address */ - VIC.VAD85.LONG = (uint32_t)r_rspi1_transmit_interrupt; - - /* Set SPEI1 interrupt address */ - VIC.VAD86.LONG = (uint32_t)r_rspi1_error_interrupt; - - /* Set SPII1 interrupt address */ - VIC.VAD87.LONG = (uint32_t)r_rspi1_idle_interrupt; - - RSPI1.SPCR.BYTE = _RSPI_MODE_SPI | _RSPI_TRANSMIT_ONLY | _RSPI_MASTER_MODE; -} - -/*********************************************************************************************************************** -* Function Name: R_RSPI1_Start -* Description : This function starts the RSPI1 module operation. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_RSPI1_Start(void) -{ - volatile uint8_t dummy; - - /* Enable RSPI interrupts */ - VIC.IEN2.LONG |= 0x00200000UL; /* Enable SPTI1 interrupt */ - VIC.IEN2.LONG |= 0x00400000UL; /* Enable SPEI1 interrupt */ - VIC.IEN2.LONG |= 0x00800000UL; /* Enable SPII1 interrupt */ - - /* Clear error sources */ - dummy = RSPI1.SPSR.BYTE; - ( void ) dummy; - RSPI1.SPSR.BYTE = 0x00U; - - /* Disable idle interrupt */ - RSPI1.SPCR2.BIT.SPIIE = 0U; -} - -/*********************************************************************************************************************** -* Function Name: R_RSPI1_Stop -* Description : This function stops the RSPI1 module operation. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_RSPI1_Stop(void) -{ - /* Disable RSPI interrupts */ - VIC.IEC2.LONG = 0x00200000UL; /* Disable SPTI1 interrupt */ - VIC.IEC2.LONG = 0x00400000UL; /* Disable SPEI1 interrupt */ - VIC.IEC2.LONG = 0x00800000UL; /* Disable SPII1 interrupt */ - - /* Disable RSPI function */ - RSPI1.SPCR.BIT.SPE = 0U; -} -/*********************************************************************************************************************** -* Function Name: R_RSPI1_Send -* Description : This function sends RSPI1 data. -* Arguments : tx_buf - -* transfer buffer pointer (not used when data is handled by DMAC) -* tx_num - -* buffer size -* Return Value : status - -* MD_OK or MD_ARGERROR -***********************************************************************************************************************/ -MD_STATUS R_RSPI1_Send(const uint32_t * tx_buf, uint16_t tx_num) -{ - MD_STATUS status = MD_OK; - - if (tx_num < 1U) - { - status = MD_ARGERROR; - } - else - { - gp_rspi1_tx_address = tx_buf; - g_rspi1_tx_count = tx_num; - - /* Enable transmit interrupt */ - RSPI1.SPCR.BIT.SPTIE = 1U; - - /* Enable error interrupt */ - RSPI1.SPCR.BIT.SPEIE = 1U; - - /* Enable idle interrupt */ - RSPI1.SPCR2.BIT.SPIIE = 1U; - - /* Enable RSPI function */ - RSPI1.SPCR.BIT.SPE = 1U; - } - - return (status); -} - - - - - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.h deleted file mode 100644 index e5c4b24a1..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi.h +++ /dev/null @@ -1,274 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_rspi.h -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for RSPI module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ -#ifndef RSPI_H -#define RSPI_H - -/*********************************************************************************************************************** -Macro definitions (Register bit) -***********************************************************************************************************************/ -/* - RSPI Control Register (SPCR) -*/ -/* RSPI Mode Select (SPMS) */ -#define _RSPI_MODE_SPI (0x00U) /* SPI operation (four-wire method) */ -#define _RSPI_MODE_CLOCK_SYNCHRONOUS (0x01U) /* Clock synchronous operation (three-wire method) */ -/* Communications Operating Mode Select (TXMD) */ -#define _RSPI_FULL_DUPLEX_SYNCHRONOUS (0x00U) /* Full-duplex synchronous serial communications */ -#define _RSPI_TRANSMIT_ONLY (0x02U) /* Serial communications with transmit only operations */ -/* Mode Fault Error Detection Enable (MODFEN) */ -#define _RSPI_MODE_FAULT_DETECT_DISABLED (0x00U) /* Disables the detection of mode fault error */ -#define _RSPI_MODE_FAULT_DETECT_ENABLED (0x04U) /* Enables the detection of mode fault error */ -/* RSPI Master/Slave Mode Select (MSTR) */ -#define _RSPI_SLAVE_MODE (0x00U) /* Slave mode */ -#define _RSPI_MASTER_MODE (0x08U) /* Master mode */ -/* RSPI Error Interrupt Enable (SPEIE) */ -#define _RSPI_ERROR_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI error interrupt */ -#define _RSPI_ERROR_INTERRUPT_ENABLED (0x10U) /* Enables the generation of RSPI error interrupt */ -/* RSPI Transmit Interrupt Enable (SPTIE) */ -#define _RSPI_TRANSMIT_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI transmit interrupt */ -#define _RSPI_TRANSMIT_INTERRUPT_ENABLED (0x20U) /* Enables the generation of RSPI transmit interrupt */ -/* RSPI Function Enable (SPE) */ -#define _RSPI_FUNCTION_DISABLED (0x00U) /* Disables the RSPI function */ -#define _RSPI_FUNCTION_ENABLED (0x40U) /* Enables the RSPI function */ -/* RSPI Receive Interrupt Enable (SPRIE) */ -#define _RSPI_RECEIVE_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI receive interrupt */ -#define _RSPI_RECEIVE_INTERRUPT_ENABLED (0x80U) /* Enables the generation of RSPI receive interrupt */ - -/* - RSPI Slave Select Polarity Register (SSLP) -*/ -/* SSL0 Signal Polarity Setting (SSL0P) */ -#define _RSPI_SSL0_POLARITY_LOW (0x00U) /* SSL0 signal is active low */ -#define _RSPI_SSL0_POLARITY_HIGH (0x01U) /* SSL0 signal is active high */ -/* SSL1 Signal Polarity Setting (SSL1P) */ -#define _RSPI_SSL1_POLARITY_LOW (0x00U) /* SSL1 signal is active low */ -#define _RSPI_SSL1_POLARITY_HIGH (0x02U) /* SSL1 signal is active high */ -/* SSL2 Signal Polarity Setting (SSL2P) */ -#define _RSPI_SSL2_POLARITY_LOW (0x00U) /* SSL2 signal is active low */ -#define _RSPI_SSL2_POLARITY_HIGH (0x04U) /* SSL2 signal is active high */ -/* SSL3 Signal Polarity Setting (SSL3P) */ -#define _RSPI_SSL3_POLARITY_LOW (0x00U) /* SSL3 signal is active low */ -#define _RSPI_SSL3_POLARITY_HIGH (0x08U) /* SSL3 signal is active high */ - -/* - RSPI Pin Control Register (SPPCR) -*/ -/* RSPI Loopback (SPLP) */ -#define _RSPI_LOOPBACK_DISABLED (0x00U) /* Normal mode */ -#define _RSPI_LOOPBACK_ENABLED (0x01U) /* Loopback mode (reversed transmit data = receive data) */ -/* RSPI Loopback 2 (SPLP2) */ -#define _RSPI_LOOPBACK2_DISABLED (0x00U) /* Normal mode */ -#define _RSPI_LOOPBACK2_ENABLED (0x02U) /* Loopback mode (transmit data = receive data) */ -/* Output pin mode (SPOM) */ -#define _RSPI_OUTPUT_PIN_CMOS (0x00U) /* CMOS output */ -#define _RSPI_OUTPUT_PIN_OPEN_DRAIN (0x04U) /* Open-drain output */ -/* MOSI Idle Fixed Value (MOIFV) */ -#define _RSPI_MOSI_LEVEL_LOW (0x00U) /* Level output on MOSIA during idling corresponds to low */ -#define _RSPI_MOSI_LEVEL_HIGH (0x10U) /* Level output on MOSIA during idling corresponds to high */ -/* MOSI Idle Value Fixing Enable (MOIFE) */ -#define _RSPI_MOSI_FIXING_PREV_TRANSFER (0x00U) /* MOSI output value equals final data from previous transfer */ -#define _RSPI_MOSI_FIXING_MOIFV_BIT (0x20U) /* MOSI output value equals the value set in the MOIFV bit */ - -/* - RSPI Sequence Control Register (SPSCR) -*/ -/* RSPI Sequence Length Specification (SPSLN[2:0]) */ -#define _RSPI_SEQUENCE_LENGTH_1 (0x00U) /* 0 -> 0... */ -#define _RSPI_SEQUENCE_LENGTH_2 (0x01U) /* 0 -> 1 -> 0... */ -#define _RSPI_SEQUENCE_LENGTH_3 (0x02U) /* 0 -> 1 -> 2 -> 0... */ -#define _RSPI_SEQUENCE_LENGTH_4 (0x03U) /* 0 -> 1 -> 2 -> 3 -> 0... */ -#define _RSPI_SEQUENCE_LENGTH_5 (0x04U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 0... */ -#define _RSPI_SEQUENCE_LENGTH_6 (0x05U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 0... */ -#define _RSPI_SEQUENCE_LENGTH_7 (0x06U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 0... */ -#define _RSPI_SEQUENCE_LENGTH_8 (0x07U) /* 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 6 -> 7 -> 0... */ - -/* - RSPI Data Control Register (SPDCR) -*/ -/* Number of Frames Specification (SPFC[1:0]) */ -#define _RSPI_FRAMES_1 (0x00U) /* 1 frame */ -#define _RSPI_FRAMES_2 (0x01U) /* 2 frames */ -#define _RSPI_FRAMES_3 (0x02U) /* 3 frames */ -#define _RSPI_FRAMES_4 (0x03U) /* 4 frames */ -/* RSPI Receive/Transmit Data Selection (SPRDTD) */ -#define _RSPI_READ_SPDR_RX_BUFFER (0x00U) /* read SPDR values from receive buffer */ -#define _RSPI_READ_SPDR_TX_BUFFER (0x10U) /* read SPDR values from transmit buffer (transmit buffer empty) */ -/* RSPI Longword Access/Word Access Specification (SPLW) */ -#define _RSPI_ACCESS_WORD (0x00U) /* SPDR is accessed in words */ -#define _RSPI_ACCESS_LONGWORD (0x20U) /* SPDR is accessed in longwords */ - -/* - RSPI Clock Delay Register (SPCKD) -*/ -/* RSPCK Delay Setting (SCKDL[2:0]) */ -#define _RSPI_RSPCK_DELAY_1 (0x00U) /* 1 RSPCK */ -#define _RSPI_RSPCK_DELAY_2 (0x01U) /* 2 RSPCK */ -#define _RSPI_RSPCK_DELAY_3 (0x02U) /* 3 RSPCK */ -#define _RSPI_RSPCK_DELAY_4 (0x03U) /* 4 RSPCK */ -#define _RSPI_RSPCK_DELAY_5 (0x04U) /* 5 RSPCK */ -#define _RSPI_RSPCK_DELAY_6 (0x05U) /* 6 RSPCK */ -#define _RSPI_RSPCK_DELAY_7 (0x06U) /* 7 RSPCK */ -#define _RSPI_RSPCK_DELAY_8 (0x07U) /* 8 RSPCK */ - -/* - RSPI Slave Select Negation Delay Register (SSLND) -*/ -/* SSL Negation Delay Setting (SLNDL[2:0]) */ -#define _RSPI_SSL_NEGATION_DELAY_1 (0x00U) /* 1 RSPCK */ -#define _RSPI_SSL_NEGATION_DELAY_2 (0x01U) /* 2 RSPCK */ -#define _RSPI_SSL_NEGATION_DELAY_3 (0x02U) /* 3 RSPCK */ -#define _RSPI_SSL_NEGATION_DELAY_4 (0x03U) /* 4 RSPCK */ -#define _RSPI_SSL_NEGATION_DELAY_5 (0x04U) /* 5 RSPCK */ -#define _RSPI_SSL_NEGATION_DELAY_6 (0x05U) /* 6 RSPCK */ -#define _RSPI_SSL_NEGATION_DELAY_7 (0x06U) /* 7 RSPCK */ -#define _RSPI_SSL_NEGATION_DELAY_8 (0x07U) /* 8 RSPCK */ - -/* - RSPI Next-Access Delay Register (SPND) -*/ -/* RSPI Next-Access Delay Setting (SPNDL[2:0]) */ -#define _RSPI_NEXT_ACCESS_DELAY_1 (0x00U) /* 1 RSPCK + 2 SERICLK */ -#define _RSPI_NEXT_ACCESS_DELAY_2 (0x01U) /* 2 RSPCK + 2 SERICLK */ -#define _RSPI_NEXT_ACCESS_DELAY_3 (0x02U) /* 3 RSPCK + 2 SERICLK */ -#define _RSPI_NEXT_ACCESS_DELAY_4 (0x03U) /* 4 RSPCK + 2 SERICLK */ -#define _RSPI_NEXT_ACCESS_DELAY_5 (0x04U) /* 5 RSPCK + 2 SERICLK */ -#define _RSPI_NEXT_ACCESS_DELAY_6 (0x05U) /* 6 RSPCK + 2 SERICLK */ -#define _RSPI_NEXT_ACCESS_DELAY_7 (0x06U) /* 7 RSPCK + 2 SERICLK */ -#define _RSPI_NEXT_ACCESS_DELAY_8 (0x07U) /* 8 RSPCK + 2 SERICLK */ - -/* - RSPI Control Register 2 (SPCR2) -*/ -/* Parity Enable (SPPE) */ -#define _RSPI_PARITY_DISABLE (0x00U) /* Does not add parity bit to transmit data */ -#define _RSPI_PARITY_ENABLE (0x01U) /* Adds the parity bit to transmit data */ -/* Parity Mode (SPOE) */ -#define _RSPI_PARITY_EVEN (0x00U) /* Selects even parity for use in transmission and reception */ -#define _RSPI_PARITY_ODD (0x02U) /* Selects odd parity for use in transmission and reception */ -/* RSPI Idle Interrupt Enable (SPIIE) */ -#define _RSPI_IDLE_INTERRUPT_DISABLED (0x00U) /* Disables the generation of RSPI idle interrupt */ -#define _RSPI_IDLE_INTERRUPT_ENABLED (0x04U) /* Enables the generation of RSPI idle interrupt */ -/* Parity Self-Testing (PTE) */ -#define _RSPI_SELF_TEST_DISABLED (0x00U) /* Disables the self-diagnosis function of the parity circuit */ -#define _RSPI_SELF_TEST_ENABLED (0x08U) /* Enables the self-diagnosis function of the parity circuit */ -/* RSPCK Auto-Stop Function Enable (SCKASE) */ -#define _RSPI_AUTO_STOP_DISABLED (0x00U) /* Disables the RSPCK auto-stop function */ -#define _RSPI_AUTO_STOP_ENABLED (0x10U) /* Enables the RSPCK auto-stop function */ - -/* - RSPI Command Registers 0 to 7 (SPCMD0 to SPCMD7) -*/ -/* RSPCK Phase Setting (CPHA) */ -#define _RSPI_RSPCK_SAMPLING_ODD (0x0000U) /* Data sampling on odd edge, data variation on even edge */ -#define _RSPI_RSPCK_SAMPLING_EVEN (0x0001U) /* Data variation on odd edge, data sampling on even edge */ -/* RSPCK Polarity Setting (CPOL) */ -#define _RSPI_RSPCK_POLARITY_LOW (0x0000U) /* RSPCK is low when idle */ -#define _RSPI_RSPCK_POLARITY_HIGH (0x0002U) /* RSPCK is high when idle */ -/* Bit Rate Division Setting (BRDV[1:0]) */ -#define _RSPI_BASE_BITRATE_1 (0x0000U) /* These bits select the base bit rate */ -#define _RSPI_BASE_BITRATE_2 (0x0004U) /* These bits select the base bit rate divided by 2 */ -#define _RSPI_BASE_BITRATE_4 (0x0008U) /* These bits select the base bit rate divided by 4 */ -#define _RSPI_BASE_BITRATE_8 (0x000CU) /* These bits select the base bit rate divided by 8 */ -/* SSL Signal Assertion Setting (SSLA[2:0]) */ -#define _RSPI_SIGNAL_ASSERT_SSL0 (0x0000U) /* SSL0 */ -#define _RSPI_SIGNAL_ASSERT_SSL1 (0x0010U) /* SSL1 */ -#define _RSPI_SIGNAL_ASSERT_SSL2 (0x0020U) /* SSL2 */ -#define _RSPI_SIGNAL_ASSERT_SSL3 (0x0030U) /* SSL3 */ -/* SSL Signal Level Keeping (SSLKP) */ -#define _RSPI_SSL_KEEP_DISABLE (0x0000U) /* Negates all SSL signals upon completion of transfer */ -#define _RSPI_SSL_KEEP_ENABLE (0x0080U) /* Keep SSL level from end of transfer till next access */ -/* RSPI Data Length Setting (SPB[3:0]) */ -#define _RSPI_DATA_LENGTH_BITS_8 (0x0400U) /* 8 bits */ -#define _RSPI_DATA_LENGTH_BITS_9 (0x0800U) /* 9 bits */ -#define _RSPI_DATA_LENGTH_BITS_10 (0x0900U) /* 10 bits */ -#define _RSPI_DATA_LENGTH_BITS_11 (0x0A00U) /* 11 bits */ -#define _RSPI_DATA_LENGTH_BITS_12 (0x0B00U) /* 12 bits */ -#define _RSPI_DATA_LENGTH_BITS_13 (0x0C00U) /* 13 bits */ -#define _RSPI_DATA_LENGTH_BITS_14 (0x0D00U) /* 14 bits */ -#define _RSPI_DATA_LENGTH_BITS_15 (0x0E00U) /* 15 bits */ -#define _RSPI_DATA_LENGTH_BITS_16 (0x0F00U) /* 16 bits */ -#define _RSPI_DATA_LENGTH_BITS_20 (0x0000U) /* 20 bits */ -#define _RSPI_DATA_LENGTH_BITS_24 (0x0100U) /* 24 bits */ -#define _RSPI_DATA_LENGTH_BITS_32 (0x0200U) /* 32 bits */ -/* RSPI LSB First (LSBF) */ -#define _RSPI_MSB_FIRST (0x0000U) /* MSB first */ -#define _RSPI_LSB_FIRST (0x1000U) /* LSB first */ -/* RSPI Next-Access Delay Enable (SPNDEN) */ -#define _RSPI_NEXT_ACCESS_DELAY_DISABLE (0x0000U) /* Next-access delay of 1 RSPCK + 2 SERICLK */ -#define _RSPI_NEXT_ACCESS_DELAY_ENABLE (0x2000U) /* Next-access delay equal to setting of SPND register */ -/* SSL Negation Delay Setting Enable (SLNDEN) */ -#define _RSPI_NEGATION_DELAY_DISABLE (0x0000U) /* SSL negation delay of 1 RSPCK */ -#define _RSPI_NEGATION_DELAY_ENABLE (0x4000U) /* SSL negation delay equal to setting of SSLND register */ -/* RSPCK Delay Setting Enable (SCKDEN) */ -#define _RSPI_RSPCK_DELAY_DISABLE (0x0000U) /* RSPCK delay of 1 RSPCK */ -#define _RSPI_RSPCK_DELAY_ENABLE (0x8000U) /* RSPCK delay equal to setting of the SPCKD register */ - -/* - Interrupt Priority Level Store Register n (PRLn) -*/ -/* Interrupt Priority Level Store (PRL[3:0]) */ -#define _RSPI_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */ -#define _RSPI_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */ -#define _RSPI_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */ -#define _RSPI_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */ -#define _RSPI_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */ -#define _RSPI_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */ -#define _RSPI_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */ -#define _RSPI_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */ -#define _RSPI_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */ -#define _RSPI_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */ -#define _RSPI_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */ -#define _RSPI_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */ -#define _RSPI_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */ -#define _RSPI_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */ -#define _RSPI_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */ -#define _RSPI_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */ - - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -#define _RSPI1_DIVISOR (0x4AU) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Global functions -***********************************************************************************************************************/ -void R_RSPI1_Create(void); -void R_RSPI1_Start(void); -void R_RSPI1_Stop(void); -MD_STATUS R_RSPI1_Send(const uint32_t * tx_buf, uint16_t tx_num); -void r_rspi1_callback_transmitend(void); -void r_rspi1_callback_error(uint8_t err_type); - -/* Start user code for function. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#endif diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi_user.c deleted file mode 100644 index 9f8c97390..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_rspi_user.c +++ /dev/null @@ -1,197 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_rspi_user.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for RSPI module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_rspi.h" -/* Start user code for include. Do not edit comment generated here */ -#include "r_typedefs.h" -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -extern const uint32_t * gp_rspi1_tx_address; /* RSPI1 transmit buffer address */ -extern uint16_t g_rspi1_tx_count; /* RSPI1 transmit data number */ -/* Start user code for global. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -* Function Name: r_rspi1_transmit_interrupt -* Description : This function is SPTI1 interrupt service routine. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -#ifdef __ICCARM__ - __irq __arm -#endif /* __ICCARM__ */ -void r_rspi1_transmit_interrupt(void) -{ - uint16_t frame_cnt; - - /* Clear the interrupt source */ - VIC.PIC2.LONG = 0x00200000UL; - - for (frame_cnt = 0U; frame_cnt < (_RSPI_FRAMES_1 + 1U); frame_cnt++) - { - if (g_rspi1_tx_count > 0U) - { - /* Write data for transmission */ - RSPI1.SPDR.LONG = (*(uint32_t*)gp_rspi1_tx_address); - gp_rspi1_tx_address++; - g_rspi1_tx_count--; - } - else - { - /* Disable transmit interrupt */ - RSPI1.SPCR.BIT.SPTIE = 0U; - - /* Enable idle interrupt */ - RSPI1.SPCR2.BIT.SPIIE = 1U; - break; - } - } - - /* Dummy write */ - VIC.HVA0.LONG = 0x00000000UL; -} -/*********************************************************************************************************************** -* Function Name: r_rspi1_error_interrupt -* Description : This function is SPEI1 interrupt service routine. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -#ifdef __ICCARM__ - __irq __arm -#endif /* __ICCARM__ */ -void r_rspi1_error_interrupt(void) -{ - uint8_t err_type; - - /* Disable RSPI function */ - RSPI1.SPCR.BIT.SPE = 0U; - - /* Disable transmit interrupt */ - RSPI1.SPCR.BIT.SPTIE = 0U; - - /* Disable error interrupt */ - RSPI1.SPCR.BIT.SPEIE = 0U; - - /* Disable idle interrupt */ - RSPI1.SPCR2.BIT.SPIIE = 0U; - - /* Clear error sources */ - err_type = RSPI1.SPSR.BYTE; - RSPI1.SPSR.BYTE = 0xA0U; - - if (err_type != 0U) - { - r_rspi1_callback_error(err_type); - } - /* Wait the interrupt signal is disabled */ - while (0U != (VIC.IRQS2.LONG & 0x00400000UL)) - { - VIC.IEC2.LONG = 0x00400000UL; - } - - VIC.IEN2.LONG |= 0x00400000UL; - - /* Dummy write */ - VIC.HVA0.LONG = 0x00000000UL; -} -/*********************************************************************************************************************** -* Function Name: r_rspi1_idle_interrupt -* Description : This function is SPII1 interrupt service routine. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -#ifdef __ICCARM__ - __irq __arm -#endif /* __ICCARM__ */ -void r_rspi1_idle_interrupt(void) -{ - /* Disable RSPI function */ - RSPI1.SPCR.BIT.SPE = 0U; - - /* Disable idle interrupt */ - RSPI1.SPCR2.BIT.SPIIE = 0U; - - r_rspi1_callback_transmitend(); - - /* Wait the interrupt signal is disabled */ - while (0U != (VIC.IRQS2.LONG & 0x00800000UL)) - { - VIC.IEC2.LONG = 0x00800000UL; - } - - VIC.IEN2.LONG |= 0x00800000UL; - - /* Dummy write */ - VIC.HVA0.LONG = 0x00000000UL; -} -/*********************************************************************************************************************** -* Function Name: r_rspi1_callback_transmitend -* Description : This function is a callback function when RSPI1 finishes transmission. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void r_rspi1_callback_transmitend(void) -{ - /* Start user code. Do not edit comment generated here */ - /* End user code. Do not edit comment generated here */ -} - - -/*********************************************************************************************************************** -* Function Name: r_rspi1_callback_error -* Description : This function is a callback function when RSPI1 error occurs. -* Arguments : err_type - -* error type value -* Return Value : None -***********************************************************************************************************************/ -void r_rspi1_callback_error(uint8_t err_type) -{ - /* Start user code. Do not edit comment generated here */ - - /* Used to suppress the warning message generated for unused variables */ - UNUSED_VARIABLE(err_type); - - /* End user code. Do not edit comment generated here */ -} - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_systeminit.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_systeminit.c deleted file mode 100644 index 996abb8bb..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_systeminit.c +++ /dev/null @@ -1,95 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_systeminit.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements system initializing function. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_cgc.h" -#include "r_cg_icu.h" -#include "r_cg_port.h" -#include "r_cg_tpu.h" -#include "r_cg_rspi.h" -#include "r_cg_mpc.h" -/* Start user code for include. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -/* Start user code for global. Do not edit comment generated here */ - -void R_Systeminit(void); - -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -* Function Name: R_Systeminit -* Description : This function initializes every macro. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_Systeminit(void) -{ - DI(); - - /* Enable writing to registers related to operating modes, LPC, CGC and ATCM */ - SYSTEM.PRCR.LONG = 0x0000A50BU; - - /* Enable writing to MPC pin function control registers */ - MPC.PWPR.BIT.B0WI = 0U; - MPC.PWPR.BIT.PFSWE = 1U; - - r_set_exception_handler(); - - /* Set peripheral settings */ - R_CGC_Create(); - R_ICU_Create(); - R_PORT_Create(); - R_TPU_Create(); - R_RSPI1_Create(); - R_MPC_Create(); - - /* Disable writing to MPC pin function control registers */ - MPC.PWPR.BIT.PFSWE = 0U; - MPC.PWPR.BIT.B0WI = 1U; - - /* Enable protection */ - SYSTEM.PRCR.LONG = 0x0000A500U; - EI(); -} - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.c deleted file mode 100644 index 77af3eafb..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.c +++ /dev/null @@ -1,98 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_tpu.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for TPU module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_tpu.h" -/* Start user code for include. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -/* Start user code for global. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -* Function Name: R_TPU_Create -* Description : This function initializes the TPU Unit0 module. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_TPU_Create(void) -{ - /* Cancel TPU stop state in LPC */ - MSTP(TPU1) = 0U; - - /* Stop all channels */ - TPUA.TSTRB.BYTE = 0x00U; - - /* Channel 9 is used as normal mode */ - TPU9.TCR.BYTE = _TPU_PCLKD_4096 | _TPU_CKEG_IT_R | _TPU_CKCL_DIS; - TPU9.TIER.BYTE |= _TPU_TGIEA_DISABLE | _TPU_TGIEB_DISABLE | _TPU_TGIEC_DISABLE | _TPU_TGIED_DISABLE | - _TPU_TCIEV_DISABLE | _TPU_TTGE_DISABLE; - TPU9.TIORH.BYTE = _TPU_IOB_IR | _TPU_IOA_DISABLE; - TPU9.TIORL.BYTE = _TPU_IOD_IR | _TPU_IOC_IR; - TPU9.TGRA = _TPU9_TCNTA_VALUE; - TPU9.TMDR.BYTE = _TPU_NORMAL | _TPU_BFA_NORMAL | _TPU_BFB_NORMAL | _TPU_ICSELB_BPIN | _TPU_ICSELD_DPIN; - - /* Internal PWM feedback function status */ - TPUSL.PWMFBSLR.LONG = _TPU_TPU0EN_DISABLE | _TPU_TPU1EN_DISABLE; -} -/*********************************************************************************************************************** -* Function Name: R_TPU9_Start -* Description : This function starts TPU channel 9 counter. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_TPU9_Start(void) -{ - TPUA.TSTRB.BIT.CST3 = 1U; -} -/*********************************************************************************************************************** -* Function Name: R_TPU9_Stop -* Description : This function stops TPU channel 9 counter. -* Arguments : None -* Return Value : None -***********************************************************************************************************************/ -void R_TPU9_Stop(void) -{ - TPUA.TSTRB.BIT.CST3 = 0U; -} - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.h deleted file mode 100644 index 46b9ae450..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu.h +++ /dev/null @@ -1,328 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_tpu.h -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for TPU module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ -#ifndef TPU_H -#define TPU_H - -/*********************************************************************************************************************** -Macro definitions (Register bit) -***********************************************************************************************************************/ -/* - Timer Control Register (TCR) -*/ -/* Time Prescaler Select (TPSC[2:0]) */ -#define _TPU_PCLKD_1 (0x00U) /* Internal clock: counts on PCLKD/1 */ -#define _TPU_PCLKD_4 (0x01U) /* Internal clock: counts on PCLKD/4 */ -#define _TPU_PCLKD_16 (0x02U) /* Internal clock: counts on PCLKD/16 */ -#define _TPU_PCLKD_64 (0x03U) /* Internal clock: counts on PCLKD/64 */ -#define _TPU_PCLKD_256 (0x06U) /* Internal clock: counts on PCLKD/256 */ -#define _TPU2_PCLKD_1024 (0x07U) /* TPU2 Internal clock: counts on PCLKD/1024 */ -#define _TPU3_PCLKD_1024 (0x05U) /* TPU3 Internal clock: counts on PCLKD/1024 */ -#define _TPU4_PCLKD_1024 (0x06U) /* TPU4 Internal clock: counts on PCLKD/1024 */ -#define _TPU8_PCLKD_1024 (0x07U) /* TPU8 Internal clock: counts on PCLKD/1024 */ -#define _TPU9_PCLKD_1024 (0x05U) /* TPU9 Internal clock: counts on PCLKD/1024 */ -#define _TPU10_PCLKD_1024 (0x06U) /* TPU10 Internal clock: counts on PCLKD/1024 */ -#define _TPU_PCLKD_4096 (0x07U) /* Internal clock: counts on PCLKD/4096 */ -#define _TPU_TCLKA (0x04U) /* External clock: counts on TCLKA pin input */ -#define _TPU_TCLKB (0x05U) /* External clock: counts on TCLKB pin input */ -#define _TPU_TCLKC_06 (0x06U) /* External clock: counts on TCLKC pin input */ -#define _TPU_TCLKC_05 (0x05U) /* External clock: counts on TCLKC pin input */ -#define _TPU_TCLKD (0x07U) /* External clock: counts on TCLKD pin input */ -#define _TPU_TCLKE (0x04U) /* External clock: counts on TCLKE pin input */ -#define _TPU_TCLKF (0x05U) /* External clock: counts on TCLKF pin input */ -#define _TPU_TCLKG_06 (0x06U) /* External clock: counts on TCLKG pin input */ -#define _TPU_TCLKG_05 (0x05U) /* External clock: counts on TCLKG pin input */ -#define _TPU_TCLKH (0x07U) /* External clock: counts on TCLKH pin input */ -#define _TPU2_COUNT (0x07U) /* TPU1: Counts on TPU2.TCNT counter overflow/underflow */ -#define _TPU5_COUNT (0x07U) /* TPU4: Counts on TPU5.TCNT counter overflow/underflow */ -#define _TPU8_COUNT (0x07U) /* TPU7: Counts on TPU8.TCNT counter overflow/underflow */ -#define _TPU11_COUNT (0x07U) /* TPU10: Counts on TPU11.TCNT counter overflow/underflow */ -/* Clock Edge Select (CKEG[1:0]) */ -#define _TPU_CKEG_IT_F (0x00U) /* Internal Clock: Count at falling edge */ -#define _TPU_CKEG_EX_R (0x00U) /* External Clock: Count at rising edge */ -#define _TPU_CKEG_IT_R (0x08U) /* Internal Clock: Count at rising edge */ -#define _TPU_CKEG_EX_F (0x08U) /* External Clock: Count at falling edge */ -#define _TPU_CKEG_BOTH (0x10U) /* Count at both edge */ -/* Counter Clear Select (CCLR[2:0]) */ -#define _TPU_CKCL_DIS (0x00U) /* TCNT clearing disabled */ -#define _TPU_CKCL_A (0x20U) /* TCNT cleared by TGRA compare match/input capture */ -#define _TPU_CKCL_B (0x40U) /* TCNT cleared by TGRB compare match/input capture */ -#define _TPU_CKCL_SYN (0x60U) /* TCNT cleared by counter clearing in another synchronous channel */ -#define _TPU_CKCL_C (0xA0U) /* TCNT cleared by TGRC compare match/input capture */ -#define _TPU_CKCL_D (0xC0U) /* TCNT cleared by TGRD compare match/input capture */ - -/* - Timer Mode Register (TMDR) -*/ -/* Mode Select (MD[3:0]) */ -#define _TPU_NORMAL (0x00U) /* Normal mode */ -#define _TPU_PWM1 (0x02U) /* PWM mode 1 */ -#define _TPU_PWM2 (0x03U) /* PWM mode 2 */ -#define _TPU_COT1 (0x04U) /* Phase counting mode 1 */ -#define _TPU_COT2 (0x05U) /* Phase counting mode 2 */ -#define _TPU_COT3 (0x06U) /* Phase counting mode 3 */ -#define _TPU_COT4 (0x07U) /* Phase counting mode 4 */ -/* Buffer Operation A (BFA) */ -#define _TPU_BFA_NORMAL (0x00U) /* TPUm.TGRA operates normally (m = 0, 3, 6, 9) */ -#define _TPU_BFA_BUFFER (0x10U) /* TPUm.TGRA and TPUm.TGRC used together for buffer operation */ -/* Buffer Operation B (BFB) */ -#define _TPU_BFB_NORMAL (0x00U) /* TPUm.TGRB operates normally (m = 0, 3, 6, 9) */ -#define _TPU_BFB_BUFFER (0x20U) /* TPUm.TGRB and TPUm.TGRD used together for buffer operation */ -/* TGRB Input Capture Input Select (ICSELB) */ -#define _TPU_ICSELB_BPIN (0x00U) /* Input capture input source is TIOCBn pin */ -#define _TPU_ICSELB_APIN (0x40U) /* Input capture input source is TIOCAn pin (n = 0 to 11) */ -/* TGRD Input Capture Input Select (ICSELD) */ -#define _TPU_ICSELD_DPIN (0x00U) /* Input capture input source is TIOCDn pin */ -#define _TPU_ICSELD_CPIN (0x80U) /* Input capture input source is TIOCCn pin (n = 0, 3, 6, 9) */ - -/* - Timer I/O Control Register (TIOR) -*/ -/* I/O Control A (IOA[3:0]) for TPU0.TIORH, TPU1.TIOR, TPU2.TIOR, TPU3.TIORH, TPU4.TIORH, TPU5.TIOR - TPU6.TIORH, TPU7.TIOR, TPU8.TIOR, TPU9.TIORH, TPU10.TIOR, TPU11.TIOR*/ -#define _TPU_IOA_DISABLE (0x00U) /* Output prohibited */ -#define _TPU_IOA_LL (0x01U) /* Initial output is low. Low output at compare match */ -#define _TPU_IOA_LH (0x02U) /* Initial output is low. High output at compare match */ -#define _TPU_IOA_LT (0x03U) /* Initial output is low. Toggle output at compare match */ -#define _TPU_IOA_HL (0x05U) /* Initial output is high. Low output at compare match */ -#define _TPU_IOA_HH (0x06U) /* Initial output is high. High output at compare match */ -#define _TPU_IOA_HT (0x07U) /* Initial output is high. Toggle output at compare match */ -#define _TPU_IOA_IR (0x08U) /* Input capture at rising edge. */ -#define _TPU_IOA_IF (0x09U) /* Input capture at falling edge */ -#define _TPU_IOA_IB (0x0AU) /* Input capture at both edges */ -#define _TPU_IOA_EX (0x0CU) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count - or TPU7.TCNT or TPU10.TCNT up-count/down-count */ -#define _TPU_IOA_TGRA (0x0DU) /* Input capture at TPU0.TGRA or TPU3.TGRA compare match/input capture - or TPU6.TGRA or TPU9.TGRA compare match/input capture */ -/* I/O Control B (IOB[3:0]) for TPU0.TIORH, TPU1.TIOR, TPU2.TIOR, TPU3.TIORH, TPU4.TIORH, TPU5.TIOR - TPU6.TIORH, TPU7.TIOR, TPU8.TIOR, TPU9.TIORH, TPU10.TIOR, TPU11.TIOR*/ -#define _TPU_IOB_DISABLE (0x00U) /* Output prohibited */ -#define _TPU_IOB_LL (0x10U) /* Initial output is low. Low output at compare match */ -#define _TPU_IOB_LH (0x20U) /* Initial output is low. High output at compare match */ -#define _TPU_IOB_LT (0x30U) /* Initial output is low. Toggle output at compare match */ -#define _TPU_IOB_HL (0x50U) /* Initial output is high. Low output at compare match */ -#define _TPU_IOB_HH (0x60U) /* Initial output is high. High output at compare match */ -#define _TPU_IOB_HT (0x70U) /* Initial output is high. Toggle output at compare match */ -#define _TPU_IOB_IR (0x80U) /* Input capture at rising edge */ -#define _TPU_IOB_IF (0x90U) /* Input capture at falling edge */ -#define _TPU_IOB_IB (0xA0U) /* Input capture at both edges. */ -#define _TPU_IOB_EX (0xC0U) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count - or TPU7.TCNT or TPU10.TCNT up-count/down-count*/ -#define _TPU_IOB_TGRC (0xD0U) /* Input capture at TPU0.TGRC or TPU3.TGRC compare match/input capture - or TPU6.TGRC or TPU9.TGRC compare match/input capture*/ -/* I/O Control C (IOC[3:0]) for TPU0.TIORL, TPU3.TIORL, TPU6.TIORL, TPU9.TIORL */ -#define _TPU_IOC_DISABLE (0x00U) /* Output prohibited */ -#define _TPU_IOC_LL (0x01U) /* Initial output is low. Low output at compare match */ -#define _TPU_IOC_LH (0x02U) /* Initial output is low. High output at compare match */ -#define _TPU_IOC_LT (0x03U) /* Initial output is low. Toggle output at compare match */ -#define _TPU_IOC_HL (0x05U) /* Initial output is high. Low output at compare match. */ -#define _TPU_IOC_HH (0x06U) /* Initial output is high. High output at compare match. */ -#define _TPU_IOC_HT (0x07U) /* Initial output is high. Toggle output at compare match. */ -#define _TPU_IOC_IR (0x08U) /* Input capture at rising edge. */ -#define _TPU_IOC_IF (0x09U) /* Input capture at falling edge. */ -#define _TPU_IOC_IB (0x0AU) /* Input capture at both edges. */ -#define _TPU_IOC_EX (0x0CU) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count - or TPU7.TCNT or TPU10.TCNT up-count/down-count. */ -/* I/O Control D (IOD[3:0]) for TPU0.TIORL, TPU3.TIORL, TPU6.TIORL, TPU9.TIOR */ -#define _TPU_IOD_DISABLE (0x00U) /* Output prohibited */ -#define _TPU_IOD_LL (0x10U) /* Initial output is low. Low output at compare match */ -#define _TPU_IOD_LH (0x20U) /* Initial output is low. High output at compare match */ -#define _TPU_IOD_LT (0x30U) /* Initial output is low. Toggle output at compare match */ -#define _TPU_IOD_HL (0x50U) /* Initial output is high. Low output at compare match. */ -#define _TPU_IOD_HH (0x60U) /* Initial output is high. High output at compare match. */ -#define _TPU_IOD_HT (0x70U) /* Initial output is high. Toggle output at compare match. */ -#define _TPU_IOD_IR (0x80U) /* Input capture at rising edge. */ -#define _TPU_IOD_IF (0x90U) /* Input capture at falling edge. */ -#define _TPU_IOD_IB (0xA0U) /* Input capture at both edges. */ -#define _TPU_IOD_EX (0xC0U) /* Input capture at TPU1.TCNT or TPU4.TCNT up-count/down-count - or TPU7.TCNT or TPU10.TCNT up-count/down-count. */ - -/* - Timer Start Registers (TSTRA) -*/ -/* Counter Start 0 (CST0) */ -#define _TPU_CST0_OFF (0x00U) /* TPU0.TCNT performs count stop */ -#define _TPU_CST0_ON (0x01U) /* TPU0.TCNT performs count operation */ -/* Counter Start 1 (CST1) */ -#define _TPU_CST1_OFF (0x00U) /* TPU1.TCNT performs count stop */ -#define _TPU_CST1_ON (0x02U) /* TPU1.TCNT performs count operation */ -/* Counter Start 2 (CST2) */ -#define _TPU_CST2_OFF (0x00U) /* TPU3.TCNT performs count stop */ -#define _TPU_CST2_ON (0x04U) /* TPU3.TCNT performs count operation */ -/* Counter Start 3 (CST3) */ -#define _TPU_CST3_OFF (0x00U) /* TPU3.TCNT performs count stop */ -#define _TPU_CST3_ON (0x08U) /* TPU3.TCNT performs count operation */ -/* Counter Start 4 (CST4) */ -#define _TPU_CST4_OFF (0x00U) /* TPU4.TCNT performs count stop */ -#define _TPU_CST4_ON (0x10U) /* TPU4.TCNT performs count operation */ -/* Counter Start 5 (CST5) */ -#define _TPU_CST5_OFF (0x00U) /* TPU5.TCNT performs count stop */ -#define _TPU_CST5_ON (0x20U) /* TPU5.TCNT performs count operation */ - -/* - Timer Start Registers (TSTRB) -*/ -/* Counter Start 6 (CST0) */ -#define _TPU_CST6_OFF (0x00U) /* TPU6.TCNT performs count stop */ -#define _TPU_CST6_ON (0x01U) /* TPU6.TCNT performs count operation */ -/* Counter Start 7 (CST1) */ -#define _TPU_CST7_OFF (0x00U) /* TPU7.TCNT performs count stop */ -#define _TPU_CST7_ON (0x02U) /* TPU7.TCNT performs count operation */ -/* Counter Start 8 (CST2) */ -#define _TPU_CST8_OFF (0x00U) /* TPU8.TCNT performs count stop */ -#define _TPU_CST8_ON (0x04U) /* TPU8.TCNT performs count operation */ -/* Counter Start 9 (CST3) */ -#define _TPU_CST9_OFF (0x00U) /* TPU9.TCNT performs count stop */ -#define _TPU_CST9_ON (0x08U) /* TPU9.TCNT performs count operation */ -/* Counter Start 10 (CST4) */ -#define _TPU_CST10_OFF (0x00U) /* TPU10.TCNT performs count stop */ -#define _TPU_CST10_ON (0x10U) /* TPU10.TCNT performs count operation */ -/* Counter Start 11 (CST5) */ -#define _TPU_CST11_OFF (0x00U) /* TPU11.TCNT performs count stop */ -#define _TPU_CST11_ON (0x20U) /* TPU11.TCNT performs count operation */ - -/* - Noise Filter Control Register (NFCR) -*/ -/* Noise Filter A Enable Bit (NFAEN) */ -#define _TPU_NFAEN_DISABLE (0x00U) /* The noise filter for the TIOCAm pin is disabled */ -#define _TPU_NFAEN_ENABLE (0x01U) /* The noise filter for the TIOCAm pin is enabled */ -/* Noise Filter B Enable Bit (NFBEN) */ -#define _TPU_NFBEN_DISABLE (0x00U) /* The noise filter for the TIOCBm pin is disabled */ -#define _TPU_NFBEN_ENABLE (0x02U) /* The noise filter for the TIOCBm pin is enabled */ -/* Noise Filter C Enable Bit (NFCEN) */ -#define _TPU_NFCEN_DISABLE (0x00U) /* The noise filter for the TIOCCm pin is disabled */ -#define _TPU_NFCEN_ENABLE (0x04U) /* The noise filter for the TIOCCm pin is enabled */ -/* Noise Filter D Enable Bit (NFDEN) */ -#define _TPU_NFDEN_DISABLE (0x00U) /* The noise filter for the TIOCDm pin is disabled */ -#define _TPU_NFDEN_ENABLE (0x08U) /* The noise filter for the TIOCDm pin is enabled */ -/* Noise Filter Clock Select (NFCS[1:0]) */ -#define _TPU_NFCS_PCLKD_1 (0x00U) /* PCLKD/1 */ -#define _TPU_NFCS_PCLKD_8 (0x10U) /* PCLKD/8 */ -#define _TPU_NFCS_PCLKD_32 (0x20U) /* PCLKD/32 */ -#define _TPU_NFCS_EXCLK (0x30U) /* The clock source for counting is the external clock */ - -/* - PWM Feedback Select Register (PWMFBSLR) -*/ -/* TPU (Unit 0) Internal PWM Feedback Enable (TPU0EN)*/ -#define _TPU_TPU0EN_DISABLE (0x00000000UL) /* Internal PWM feedback input function unit 0 is disabled */ -#define _TPU_TPU0EN_ENABLE (0x00000001UL) /* Internal PWM feedback input function unit 0 is enabled */ -/* Internal PWM Feedback Input Source Select 0 (FBSL0[2:0]) */ -#define _TPU0_PWM_SIG_MTU34 (0x00000010UL) /* PWM output signals of MTU3 and MTU4 */ -#define _TPU0_PWM_SIG_MTU67 (0x00000014UL) /* PWM output signals of MTU6 and MTU7 */ -#define _TPU0_PWM_SIG_GPT02 (0x00000018UL) /* PWM output signals of GPT0 to GPT2 */ -/* TPU (Unit 1) Internal PWM Feedback Enable (TPU1EN)*/ -#define _TPU_TPU1EN_DISABLE (0x00000000UL) /* Internal PWM feedback input function unit 1 is disabled */ -#define _TPU_TPU1EN_ENABLE (0x00000100UL) /* Internal PWM feedback input function unit 1 is enabled */ -/* Internal PWM Feedback Input Source Select 1 (FBSL1[2:0]) */ -#define _TPU1_PWM_SIG_MTU34 (0x00001000UL) /* PWM output signals of MTU3 and MTU4 */ -#define _TPU1_PWM_SIG_MTU67 (0x00001400UL) /* PWM output signals of MTU6 and MTU7 */ -#define _TPU1_PWM_SIG_GPT02 (0x00001800UL) /* PWM output signals of GPT0 to GPT2 */ -/* - Timer Interrupt Enable Register (TIER) -*/ -/* TGR Interrupt Enable A (TGIEA) */ -#define _TPU_TGIEA_DISABLE (0x00U) /* Interrupt requests TGIA disabled */ -#define _TPU_TGIEA_ENABLE (0x01U) /* Interrupt requests TGIA enabled */ -/* TGR Interrupt Enable B (TGIEB) */ -#define _TPU_TGIEB_DISABLE (0x00U) /* Interrupt requests TGIB disabled */ -#define _TPU_TGIEB_ENABLE (0x02U) /* Interrupt requests TGIB enabled */ -/* TGR Interrupt Enable C (TGIEC) */ -#define _TPU_TGIEC_DISABLE (0x00U) /* Interrupt requests TGIC disabled */ -#define _TPU_TGIEC_ENABLE (0x04U) /* Interrupt requests TGIC enabled */ -/* TGR Interrupt Enable D (TGIED) */ -#define _TPU_TGIED_DISABLE (0x00U) /* Interrupt requests TGID disabled */ -#define _TPU_TGIED_ENABLE (0x08U) /* Interrupt requests TGID enabled */ -/* Overflow Interrupt Enable (TCIEV) */ -#define _TPU_TCIEV_DISABLE (0x00U) /* Interrupt requests TCIV disabled */ -#define _TPU_TCIEV_ENABLE (0x10U) /* Interrupt requests TCIV enabled */ -/* Underflow Interrupt Enable (TCIEU) */ -#define _TPU_TCIEU_DISABLE (0x00U) /* Interrupt requests TCIU disabled */ -#define _TPU_TCIEU_ENABLE (0x20U) /* Interrupt requests TCIU enabled */ -/* A/D Converter Start Request Enable (TTGE) */ -#define _TPU_TTGE_DISABLE (0x00U) /* A/D converter start request generation disabled */ -#define _TPU_TTGE_ENABLE (0x80U) /* A/D converter start request generation enabled */ - -/* - Interrupt Source Priority Register n (PRLn) -*/ -/* Interrupt Priority Level Select (PRL[3:0]) */ -#define _TPU_PRIORITY_LEVEL0 (0x00000000UL) /* Level 0 (highest) */ -#define _TPU_PRIORITY_LEVEL1 (0x00000001UL) /* Level 1 */ -#define _TPU_PRIORITY_LEVEL2 (0x00000002UL) /* Level 2 */ -#define _TPU_PRIORITY_LEVEL3 (0x00000003UL) /* Level 3 */ -#define _TPU_PRIORITY_LEVEL4 (0x00000004UL) /* Level 4 */ -#define _TPU_PRIORITY_LEVEL5 (0x00000005UL) /* Level 5 */ -#define _TPU_PRIORITY_LEVEL6 (0x00000006UL) /* Level 6 */ -#define _TPU_PRIORITY_LEVEL7 (0x00000007UL) /* Level 7 */ -#define _TPU_PRIORITY_LEVEL8 (0x00000008UL) /* Level 8 */ -#define _TPU_PRIORITY_LEVEL9 (0x00000009UL) /* Level 9 */ -#define _TPU_PRIORITY_LEVEL10 (0x0000000AUL) /* Level 10 */ -#define _TPU_PRIORITY_LEVEL11 (0x0000000BUL) /* Level 11 */ -#define _TPU_PRIORITY_LEVEL12 (0x0000000CUL) /* Level 12 */ -#define _TPU_PRIORITY_LEVEL13 (0x0000000DUL) /* Level 13 */ -#define _TPU_PRIORITY_LEVEL14 (0x0000000EUL) /* Level 14 */ -#define _TPU_PRIORITY_LEVEL15 (0x0000000FUL) /* Level 15 */ -#define _TPU_PRIORITY_LEVEL16 (0x00000000UL) /* Level 16 */ -#define _TPU_PRIORITY_LEVEL17 (0x00000001UL) /* Level 17 */ -#define _TPU_PRIORITY_LEVEL18 (0x00000002UL) /* Level 18 */ -#define _TPU_PRIORITY_LEVEL19 (0x00000003UL) /* Level 19 */ -#define _TPU_PRIORITY_LEVEL20 (0x00000004UL) /* Level 20 */ -#define _TPU_PRIORITY_LEVEL21 (0x00000005UL) /* Level 21 */ -#define _TPU_PRIORITY_LEVEL22 (0x00000006UL) /* Level 22 */ -#define _TPU_PRIORITY_LEVEL23 (0x00000007UL) /* Level 23 */ -#define _TPU_PRIORITY_LEVEL24 (0x00000008UL) /* Level 24 */ -#define _TPU_PRIORITY_LEVEL25 (0x00000009UL) /* Level 25 */ -#define _TPU_PRIORITY_LEVEL26 (0x0000000AUL) /* Level 26 */ -#define _TPU_PRIORITY_LEVEL27 (0x0000000BUL) /* Level 27 */ -#define _TPU_PRIORITY_LEVEL28 (0x0000000CUL) /* Level 28 */ -#define _TPU_PRIORITY_LEVEL29 (0x0000000DUL) /* Level 29 */ -#define _TPU_PRIORITY_LEVEL30 (0x0000000EUL) /* Level 30 */ -#define _TPU_PRIORITY_LEVEL31 (0x0000000FUL) /* Level 31 (lowest) */ - - -/*********************************************************************************************************************** -Macro definitions -***********************************************************************************************************************/ -/* TGRA value channel 9 */ -#define _TPU9_TCNTA_VALUE (0x0726U) - -/*********************************************************************************************************************** -Typedef definitions -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Global functions -***********************************************************************************************************************/ -void R_TPU_Create(void); -void R_TPU9_Start(void); -void R_TPU9_Stop(void); - -/* Start user code for function. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu_user.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu_user.c deleted file mode 100644 index 8d1fc9a89..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_tpu_user.c +++ /dev/null @@ -1,52 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_tpu_user.c -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file implements device driver for TPU module. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -Pragma directive -***********************************************************************************************************************/ -/* Start user code for pragma. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - -/*********************************************************************************************************************** -Includes -***********************************************************************************************************************/ -#include "r_cg_macrodriver.h" -#include "r_cg_tpu.h" -/* Start user code for include. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ -#include "r_cg_userdefine.h" - -/*********************************************************************************************************************** -Global variables and functions -***********************************************************************************************************************/ -/* Start user code for global. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ - - -/* Start user code for adding. Do not edit comment generated here */ -/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_userdefine.h b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_userdefine.h deleted file mode 100644 index 2db8e0c19..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_userdefine.h +++ /dev/null @@ -1,72 +0,0 @@ -/*********************************************************************************************************************** -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. -* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED -* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY -* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, -* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR -* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* -* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. -***********************************************************************************************************************/ - -/*********************************************************************************************************************** -* File Name : r_cg_userdefine.h -* Version : Code Generator for RZ/T1 V1.00.00.09 [02 Mar 2015] -* Device(s) : R7S910018CBG -* Tool-Chain : GCCARM -* Description : This file includes user definition. -* Creation Date: 22/04/2015 -***********************************************************************************************************************/ -#ifndef _USER_DEF_H -#define _USER_DEF_H - -/*********************************************************************************************************************** -User definitions -***********************************************************************************************************************/ - -/* Start user code for function. Do not edit comment generated here */ - -#define MPC_PFSWE_WRITE_ENABLE (0x00) -#define MPC_PFS_WRITE_ENABLE (0x40) -#define MPC_PFS_WRITE_DISABLE (0x80) - -#define MPC_IRQ_DISABLE (0) -#define MPC_IRQ_ENABLE (1) - -/* Define LED states */ -#define LED_ON (1U) -#define LED_OFF (0U) - -/* Define user LEDs mode register pins */ -#define LED0_MODE (PORTF.PMR.BIT.B7) -#define LED1_MODE (PORT5.PMR.BIT.B6) -#define LED2_MODE (PORT7.PMR.BIT.B7) -#define LED3_MODE (PORTA.PMR.BIT.B0) - -/* Define user LEDs direction's pins */ -#define LED0_DIR (PORTF.PDR.BIT.B7) -#define LED1_DIR (PORT5.PDR.BIT.B6) -#define LED2_DIR (PORT7.PDR.BIT.B7) -#define LED3_DIR (PORTA.PDR.BIT.B0) - -/* Define user LEDs */ -#define LED0 (PORTF.PODR.BIT.B7) -#define LED1 (PORT5.PODR.BIT.B6) -#define LED2 (PORT7.PODR.BIT.B7) -#define LED3 (PORTA.PODR.BIT.B0) - -void R_MPC_WriteEnable (void); -void R_MPC_WriteDisable (void); - -extern void r_set_exception_handler(void); - -/* End user code. Do not edit comment generated here */ -#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c b/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c deleted file mode 100644 index 730e617a5..000000000 --- a/FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. - All rights reserved - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - *************************************************************************** - >>! NOTE: The modification to the GPL is included to allow you to !<< - >>! distribute a combined work that includes FreeRTOS without being !<< - >>! obliged to provide the source code for proprietary components !<< - >>! outside of the FreeRTOS kernel. !<< - *************************************************************************** - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available on the following - link: http://www.freertos.org/a00114.html - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that is more than just the market leader, it * - * is the industry's de facto standard. * - * * - * Help yourself get started quickly while simultaneously helping * - * to support the FreeRTOS project by purchasing a FreeRTOS * - * tutorial book, reference manual, or both: * - * http://www.FreeRTOS.org/Documentation * - * * - *************************************************************************** - - http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading - the FAQ page "My application does not run, what could be wrong?". Have you - defined configASSERT()? - - http://www.FreeRTOS.org/support - In return for receiving this top quality - embedded software for free we request you assist our global community by - participating in the support forum. - - http://www.FreeRTOS.org/training - Investing in training allows your team to - be as productive as possible as early as possible. Now you can receive - FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers - Ltd, and the world's leading authority on the world's leading RTOS. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. - Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. - - http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High - Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and commercial middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * This project provides two demo applications. A simple blinky style project, - * and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to - * select between the two. The simply blinky demo is implemented and described - * in main_blinky.c. The more comprehensive test and demo application is - * implemented and described in main_full.c. - * - * This file implements the code that is not demo specific, including the - * hardware setup, standard FreeRTOS hook functions, and the ISR hander called - * by the RTOS after interrupt entry (including nesting) has been taken care of. - * - * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON - * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO - * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! - * - */ - -/* Standard includes. */ -#include "string.h" - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* Renesas includes. */ -#include "r_cg_macrodriver.h" -#include "r_cg_icu.h" -#include "r_cg_rspi.h" -#include "r_system.h" -#include "r_reset.h" -#include "r_cg_userdefine.h" - -/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 - -/*-----------------------------------------------------------*/ - -/* - * The GCC start up code does not include a routine to clear the BSS segment to - * 0 (as would be normal before calling main()), so the BSS is cleared manually - * using the following function. - */ -static void prvClearBSS( void ); - -/* - * Configure the hardware as necessary to run this demo. - */ -static void prvSetupHardware( void ); - -/* - * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. - * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. - */ -#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - extern void main_blinky( void ); -#else - extern void main_full( void ); -#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ - -/* Prototypes for the standard FreeRTOS callback/hook functions implemented -within this file. */ -void vApplicationMallocFailedHook( void ); -void vApplicationIdleHook( void ); -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); -void vApplicationTickHook( void ); - -/* Prototype for the IRQ handler called by the generic Cortex-A5 RTOS port -layer. */ -void vApplicationIRQHandler( void ); - -/* Library initialisation. */ -extern void R_Systeminit( void ); - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* The start up code does not include a routine to clear the BSS segment to - 0 (as would be normal before calling main()), so the BSS is cleared manually - using the following function. */ - prvClearBSS(); - - /* Configure the hardware ready to run the demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - R_Systeminit(); -} -/*-----------------------------------------------------------*/ - -void vApplicationMallocFailedHook( void ) -{ - /* Called if a call to pvPortMalloc() fails because there is insufficient - free memory available in the FreeRTOS heap. pvPortMalloc() is called - internally by FreeRTOS API functions that create tasks, queues, software - timers, and semaphores. The size of the FreeRTOS heap is set by the - configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); -} -/*-----------------------------------------------------------*/ - -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) -{ - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - - /* Force an assert. */ - configASSERT( ( volatile void * ) NULL ); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ -volatile size_t xFreeHeapSpace; - - /* This is just a trivial example of an idle hook. It is called on each - cycle of the idle task. It must *NOT* attempt to block. In this case the - idle task just queries the amount of FreeRTOS heap that remains. See the - memory management section on the http://www.FreeRTOS.org web site for memory - management options. If there is a lot of heap memory free then the - configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up - RAM. */ - xFreeHeapSpace = xPortGetFreeHeapSize(); - - /* Remove compiler warning about xFreeHeapSpace being set but never used. */ - ( void ) xFreeHeapSpace; -} -/*-----------------------------------------------------------*/ - -void vApplicationTickHook( void ) -{ - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 - { - extern void vFullDemoTickHook( void ); - - vFullDemoTickHook(); - } - #endif -} -/*-----------------------------------------------------------*/ - -static void prvClearBSS( void ) -{ -#ifdef __GNUC__ - /* The GCC start up files seem to be missing code to clear the BSS, so it - is done manually here. */ - extern uint32_t __bss_start__[]; - extern uint32_t __bss_end__[]; - size_t xSize; - - /* Zero out bss. */ - xSize = ( ( size_t ) __bss_end__ ) - ( ( size_t ) __bss_start__ ); - memset( ( void * ) __bss_start__, 0x00, xSize ); -#endif /* __GNUC__ */ -} - - - diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-default.mk b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-default.mk index c852fc32f..4a62422e9 100644 --- a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-default.mk +++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-default.mk @@ -462,626 +462,626 @@ ${OBJECTDIR}/_ext/1477011893/main_blinky.o: ../src/Blinky_Demo/main_blinky.c nb @${MKDIR} "${OBJECTDIR}/_ext/1477011893" @${RM} ${OBJECTDIR}/_ext/1477011893/main_blinky.o.d @${RM} ${OBJECTDIR}/_ext/1477011893/main_blinky.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1477011893/main_blinky.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1477011893/main_blinky.o.d" -o ${OBJECTDIR}/_ext/1477011893/main_blinky.o ../src/Blinky_Demo/main_blinky.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1477011893/main_blinky.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1477011893/main_blinky.o.d" -o ${OBJECTDIR}/_ext/1477011893/main_blinky.o ../src/Blinky_Demo/main_blinky.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1884096877/heap_2.o: ../../../Source/portable/MemMang/heap_2.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1884096877" @${RM} ${OBJECTDIR}/_ext/1884096877/heap_2.o.d @${RM} ${OBJECTDIR}/_ext/1884096877/heap_2.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1884096877/heap_2.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1884096877/heap_2.o.d" -o ${OBJECTDIR}/_ext/1884096877/heap_2.o ../../../Source/portable/MemMang/heap_2.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1884096877/heap_2.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1884096877/heap_2.o.d" -o ${OBJECTDIR}/_ext/1884096877/heap_2.o ../../../Source/portable/MemMang/heap_2.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/582319769/port.o: ../../../Source/portable/MPLAB/PIC32MEC14xx/port.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/582319769" @${RM} ${OBJECTDIR}/_ext/582319769/port.o.d @${RM} ${OBJECTDIR}/_ext/582319769/port.o - @${FIXDEPS} "${OBJECTDIR}/_ext/582319769/port.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/582319769/port.o.d" -o ${OBJECTDIR}/_ext/582319769/port.o ../../../Source/portable/MPLAB/PIC32MEC14xx/port.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/582319769/port.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/582319769/port.o.d" -o ${OBJECTDIR}/_ext/582319769/port.o ../../../Source/portable/MPLAB/PIC32MEC14xx/port.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/449926602/event_groups.o: ../../../Source/event_groups.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/449926602" @${RM} ${OBJECTDIR}/_ext/449926602/event_groups.o.d @${RM} ${OBJECTDIR}/_ext/449926602/event_groups.o - @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/event_groups.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/event_groups.o.d" -o ${OBJECTDIR}/_ext/449926602/event_groups.o ../../../Source/event_groups.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/event_groups.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/event_groups.o.d" -o ${OBJECTDIR}/_ext/449926602/event_groups.o ../../../Source/event_groups.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/449926602/list.o: ../../../Source/list.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/449926602" @${RM} ${OBJECTDIR}/_ext/449926602/list.o.d @${RM} ${OBJECTDIR}/_ext/449926602/list.o - @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/list.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/list.o.d" -o ${OBJECTDIR}/_ext/449926602/list.o ../../../Source/list.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/list.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/list.o.d" -o ${OBJECTDIR}/_ext/449926602/list.o ../../../Source/list.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/449926602/queue.o: ../../../Source/queue.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/449926602" @${RM} ${OBJECTDIR}/_ext/449926602/queue.o.d @${RM} ${OBJECTDIR}/_ext/449926602/queue.o - @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/queue.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) 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-I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/tasks.o.d" -o ${OBJECTDIR}/_ext/449926602/tasks.o ../../../Source/tasks.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/449926602/timers.o: ../../../Source/timers.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/449926602" @${RM} ${OBJECTDIR}/_ext/449926602/timers.o.d @${RM} ${OBJECTDIR}/_ext/449926602/timers.o - @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/timers.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/449926602/timers.o.d" -o ${OBJECTDIR}/_ext/449926602/timers.o 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nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o ../src/MEC14xx/mec14xx_gpio.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) 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-I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o ../src/MEC14xx/mec14xx_jtvic.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o ../src/MEC14xx/mec14xx_jtvic.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o: ../src/MEC14xx/mec14xx_system.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o ../src/MEC14xx/mec14xx_system.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o ../src/MEC14xx/mec14xx_system.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o: ../src/MEC14xx/mec14xx_tfdp.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o ../src/MEC14xx/mec14xx_tfdp.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o ../src/MEC14xx/mec14xx_tfdp.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o: ../src/MEC14xx/mec14xx_timers.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o ../src/MEC14xx/mec14xx_timers.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o ../src/MEC14xx/mec14xx_timers.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1360937237/main.o: ../src/main.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1360937237" @${RM} ${OBJECTDIR}/_ext/1360937237/main.o.d @${RM} ${OBJECTDIR}/_ext/1360937237/main.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1360937237/main.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1360937237/main.o.d" -o ${OBJECTDIR}/_ext/1360937237/main.o ../src/main.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1360937237/main.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -D__DEBUG -D__MPLAB_DEBUGGER_ICD3=1 -fframe-base-loclist -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1360937237/main.o.d" -o ${OBJECTDIR}/_ext/1360937237/main.o ../src/main.c -D__DEBUG -Wall -Wextra else ${OBJECTDIR}/_ext/1477011893/main_blinky.o: ../src/Blinky_Demo/main_blinky.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1477011893" @${RM} ${OBJECTDIR}/_ext/1477011893/main_blinky.o.d @${RM} ${OBJECTDIR}/_ext/1477011893/main_blinky.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1477011893/main_blinky.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} 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../../../Source/portable/MemMang/heap_2.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1884096877" @${RM} ${OBJECTDIR}/_ext/1884096877/heap_2.o.d @${RM} ${OBJECTDIR}/_ext/1884096877/heap_2.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1884096877/heap_2.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1884096877/heap_2.o.d" -o ${OBJECTDIR}/_ext/1884096877/heap_2.o ../../../Source/portable/MemMang/heap_2.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1884096877/heap_2.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" 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../../../Source/portable/MPLAB/PIC32MEC14xx/port.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/582319769/port.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/582319769/port.o.d" -o ${OBJECTDIR}/_ext/582319769/port.o ../../../Source/portable/MPLAB/PIC32MEC14xx/port.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/449926602/event_groups.o: ../../../Source/event_groups.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/449926602" @${RM} ${OBJECTDIR}/_ext/449926602/event_groups.o.d @${RM} ${OBJECTDIR}/_ext/449926602/event_groups.o - @${FIXDEPS} "${OBJECTDIR}/_ext/449926602/event_groups.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c 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-rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1662639563/girq26.o.d" -o ${OBJECTDIR}/_ext/1662639563/girq26.o ../src/MEC14xx/interrupts/girq26.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1662639563/girqs.o: ../src/MEC14xx/interrupts/girqs.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1662639563" @${RM} ${OBJECTDIR}/_ext/1662639563/girqs.o.d @${RM} ${OBJECTDIR}/_ext/1662639563/girqs.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1662639563/girqs.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1662639563/girqs.o.d" -o ${OBJECTDIR}/_ext/1662639563/girqs.o ../src/MEC14xx/interrupts/girqs.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1662639563/girqs.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1662639563/girqs.o.d" -o ${OBJECTDIR}/_ext/1662639563/girqs.o ../src/MEC14xx/interrupts/girqs.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o: ../src/MEC14xx/startup/MPLAB/default-on-bootstrap.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1068550557" @${RM} ${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o.d @${RM} ${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o.d" -o ${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o ../src/MEC14xx/startup/MPLAB/default-on-bootstrap.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o.d" -o ${OBJECTDIR}/_ext/1068550557/default-on-bootstrap.o ../src/MEC14xx/startup/MPLAB/default-on-bootstrap.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1068550557/on_reset.o: ../src/MEC14xx/startup/MPLAB/on_reset.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1068550557" @${RM} ${OBJECTDIR}/_ext/1068550557/on_reset.o.d @${RM} ${OBJECTDIR}/_ext/1068550557/on_reset.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1068550557/on_reset.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1068550557/on_reset.o.d" -o ${OBJECTDIR}/_ext/1068550557/on_reset.o ../src/MEC14xx/startup/MPLAB/on_reset.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1068550557/on_reset.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1068550557/on_reset.o.d" -o ${OBJECTDIR}/_ext/1068550557/on_reset.o ../src/MEC14xx/startup/MPLAB/on_reset.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o: ../src/MEC14xx/mec14xx_bbled.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o ../src/MEC14xx/mec14xx_bbled.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_bbled.o ../src/MEC14xx/mec14xx_bbled.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o: ../src/MEC14xx/mec14xx_gpio.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o ../src/MEC14xx/mec14xx_gpio.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_gpio.o ../src/MEC14xx/mec14xx_gpio.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o: ../src/MEC14xx/mec14xx_jtvic.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o ../src/MEC14xx/mec14xx_jtvic.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_jtvic.o ../src/MEC14xx/mec14xx_jtvic.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o: ../src/MEC14xx/mec14xx_system.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o ../src/MEC14xx/mec14xx_system.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_system.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_system.o ../src/MEC14xx/mec14xx_system.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o: ../src/MEC14xx/mec14xx_tfdp.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o ../src/MEC14xx/mec14xx_tfdp.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_tfdp.o ../src/MEC14xx/mec14xx_tfdp.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o: ../src/MEC14xx/mec14xx_timers.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1376193940" @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d @${RM} ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o ../src/MEC14xx/mec14xx_timers.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o.d" -o ${OBJECTDIR}/_ext/1376193940/mec14xx_timers.o ../src/MEC14xx/mec14xx_timers.c -D__DEBUG -Wall -Wextra ${OBJECTDIR}/_ext/1360937237/main.o: ../src/main.c nbproject/Makefile-${CND_CONF}.mk @${MKDIR} "${OBJECTDIR}/_ext/1360937237" @${RM} ${OBJECTDIR}/_ext/1360937237/main.o.d @${RM} ${OBJECTDIR}/_ext/1360937237/main.o - @${FIXDEPS} "${OBJECTDIR}/_ext/1360937237/main.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -O3 -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1360937237/main.o.d" -o ${OBJECTDIR}/_ext/1360937237/main.o ../src/main.c -D__DEBUG -Wall -Wextra + @${FIXDEPS} "${OBJECTDIR}/_ext/1360937237/main.o.d" $(SILENT) -rsi ${MP_CC_DIR}../ -c ${MP_CC} $(MP_EXTRA_CC_PRE) -g -x c -c -mprocessor=$(MP_PROCESSOR_OPTION) -ffunction-sections -mmicromips -I"../src" -I"../src/include" -I"../../../Source/include" -I"../../../Source/portable/MPLAB/PIC32MEC14xx" -I"../src/MEC14xx" -I"../../Common/include" -I"../src/Full_Demo" -MMD -MF "${OBJECTDIR}/_ext/1360937237/main.o.d" -o ${OBJECTDIR}/_ext/1360937237/main.o ../src/main.c -D__DEBUG -Wall -Wextra endif diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-genesis.properties b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-genesis.properties index 9ae1d91ed..cad03b61e 100644 --- a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-genesis.properties +++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/Makefile-genesis.properties @@ -1,8 +1,8 @@ # -#Sat Sep 12 19:52:29 BST 2015 +#Sun Sep 13 08:07:29 BST 2015 default.com-microchip-mplab-nbide-toolchainXC32-XC32LanguageToolchain.md5=a29d9df60dd9a7849837c8f5ca17a004 default.languagetoolchain.dir=C\:\\DevTools\\Microchip\\xc32\\v1.33\\bin -configurations-xml=1488628682f58c9c6bf4eb01175324a8 +configurations-xml=30deb6920812925f770c8a369802918a com-microchip-mplab-nbide-embedded-makeproject-MakeProject.md5=47805b5596804b87cda41e61096929be default.languagetoolchain.version=1.33 host.platform=windows diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/configurations.xml b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/configurations.xml index 6e1f4aff7..83135a2b9 100644 --- a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/configurations.xml +++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/configurations.xml @@ -244,7 +244,7 @@ - + diff --git a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/private/private.xml b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/private/private.xml index 2cb574f8d..d9ec1062e 100644 --- a/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/private/private.xml +++ b/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/PIC32MEC14xx_RTOSDemo.X/nbproject/private/private.xml @@ -16,15 +16,12 @@ file:/C:/Users/m91145/Documents/OS%20IDE%20Specialist%20Team/FreeRTOS%20MEC%20Port/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/IntQueueTimer_isr.S - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/default-on-bootstrap.c - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/tasks.c - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crt0.S - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/list.c - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/on_reset.c - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crti.S file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/main.c - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/MEC14xx/startup/MPLAB/crtn.S - file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Blinky_Demo/main_blinky.c + file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/FreeRTOSConfig.h + file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port.c + file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Source/tasks.c + file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/main_full.c + file:/C:/E/Dev/FreeRTOS/WorkingCopy/FreeRTOS/Demo/PIC32MEC14xx_MPLAB/src/Full_Demo/timertest.c diff --git a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo_GCC.launch b/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo_GCC.launch deleted file mode 100644 index 6bbe77a1a..000000000 --- a/FreeRTOS/Demo/RX100-RSK_GCC_e2studio/RTOSDemo_GCC.launch +++ /dev/null @@ -1,78 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.cproject b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.cproject index 017cce7d2..29d7efc14 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.cproject +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.cproject @@ -99,8 +99,11 @@ + + + - + @@ -114,6 +117,10 @@ - + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.project b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.project index 40109d0cb..2aaee4c2d 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.project +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.project @@ -42,6 +42,15 @@ + + 1442930329366 + + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-settings + + 1442848178229 src/FreeRTOS_Source @@ -226,7 +235,7 @@ FREERTOS_ROOT - $%7BPARENT-4-PROJECT_LOC%7D + $%7BPARENT-3-PROJECT_LOC%7D diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/language.settings.xml b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/language.settings.xml index 9db58ebe7..77df28c89 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/language.settings.xml +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/.settings/language.settings.xml @@ -3,7 +3,7 @@ - + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..3ef1570c0 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewd @@ -0,0 +1,771 @@ + + + + 2 + + Debug + + RX + + 1 + + C-SPY + 3 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RXEMUE20 + 4 + + 4 + 1 + 1 + + + + + + + + + + + + + + + RXE2LITE + 1 + + 0 + 1 + 1 + + + + + + + + + + + + + + + RXJLINK + 4 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + SIMRX + 1 + + 1 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + RX + + 0 + + C-SPY + 3 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RXEMUE20 + 4 + + 4 + 1 + 0 + + + + + + + + + + + + + + + RXE2LITE + 1 + + 0 + 1 + 0 + + + + + + + + + + + + + + + RXJLINK + 4 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + SIMRX + 1 + + 1 + 1 + 0 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewp b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..5cda01ab9 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.ewp @@ -0,0 +1,2044 @@ + + + + 2 + + Debug + + RX + + 1 + + General + 6 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRX + 8 + + 17 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARX + 6 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 1 + + 0 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 4 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 1 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + RX + + 0 + + General + 6 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRX + 8 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARX + 6 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 1 + + 0 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 4 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 1 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Blinky_Demo + + $PROJ_DIR$\src\Blinky_Demo\main_blinky.c + + + + cg_src + + $PROJ_DIR$\src\cg_src\r_cg_cgc.c + + + $PROJ_DIR$\src\cg_src\r_cg_hardware_setup.c + + + $PROJ_DIR$\src\cg_src\r_cg_port.c + + + $PROJ_DIR$\src\cg_src\r_cg_sci.c + + + + FreeRTOS_Source + + portable + + MemMang + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + + + + $PROJ_DIR$\..\..\Source\portable\IAR\RX100\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\RX100\port_asm.s + + + + $PROJ_DIR$\..\..\Source\event_groups.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\Source\timers.c + + + + Full_Demo + + Standard_Demo_Tasks + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\blocktim.c + + + $PROJ_DIR$\..\Common\Minimal\countsem.c + + + $PROJ_DIR$\..\Common\Minimal\death.c + + + $PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c + + + $PROJ_DIR$\..\Common\Minimal\flop.c + + + $PROJ_DIR$\..\Common\Minimal\GenQTest.c + + + $PROJ_DIR$\..\Common\Minimal\IntQueue.c + + + $PROJ_DIR$\..\Common\Minimal\IntSemTest.c + + + $PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c + + + $PROJ_DIR$\..\Common\Minimal\recmutex.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\..\Common\Minimal\TaskNotify.c + + + $PROJ_DIR$\..\Common\Minimal\TimerDemo.c + + + + $PROJ_DIR$\src\Full_Demo\IntQueueTimer.c + + + $PROJ_DIR$\src\Full_Demo\main_full.c + + + $PROJ_DIR$\src\Full_Demo\RegTest_IAR.s + + + + $PROJ_DIR$\src\FreeRTOSConfig.h + + + $PROJ_DIR$\src\main.c + + + $PROJ_DIR$\src\rskrx113def.h + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.eww b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat new file mode 100644 index 000000000..000a07c7c --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%1" == "" goto debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl new file mode 100644 index 000000000..048724e75 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl @@ -0,0 +1,39 @@ + -B + +"-p" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\config\debugger\ior5f51138.ddf" + +"--endian" + +"l" + +"--double" + +"64" + +"--core" + +"rxv1" + +"--int" + +"32" + +"--no_fpu" + +"-d" + +"emue20" + +"--drv_mode" + +"debugging" + +"--drv_communication" + +"USB" + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl new file mode 100644 index 000000000..0d8b5cdf6 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxproc.dll" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxe1e20.dll" + +"C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX113-RSK_GCC_e2studio_IAR\Debug\Exe\RTOSDemo.out" + +--plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxbat.dll" + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..4f7e51010 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,244 @@ + + + + + + + 20 + 1622 + + + 20 + 1216 + 324 + 81 + + + + 255 + 27 + 27 + 27 + + + + + Disassembly + _I0 + + + 500 + 20 + + + + 2 + 0 + 0 + + + 1 + 1 + + + + 2 + 0 + 0 + + + + + + + + + TabID-6594-3339 + Debug Log + Debug-Log + + + + TabID-6072-3348 + Build + Build + + + + 0 + + + + + TabID-17343-3342 + Workspace + Workspace + + + RTOSDemo + + + + + 0 + + + + + + TextEditor + $WS_DIR$\src\main.c + 0 + 0 + 0 + 0 + 0 + 66 + 5312 + 5312 + + + TextEditor + $WS_DIR$\src\Full_Demo\RegTest_IAR.s + 0 + 0 + 0 + 0 + 0 + 144 + 5881 + 5881 + + + TextEditor + $WS_DIR$\..\Common\Minimal\flop.c + 0 + 0 + 0 + 0 + 0 + 126 + 6956 + 6956 + + + TextEditor + $WS_DIR$\..\Common\Minimal\TimerDemo.c + 0 + 0 + 0 + 0 + 0 + 242 + 12612 + 12612 + + + TextEditor + $WS_DIR$\..\Common\Minimal\IntQueue.c + 0 + 0 + 0 + 0 + 0 + 381 + 0 + 0 + + + TextEditor + $WS_DIR$\src\Full_Demo\IntQueueTimer.c + 0 + 0 + 0 + 0 + 0 + 154 + 7349 + 7349 + + 5 + + 0 + + + 1000000 + 1000000 + + + 1 + + + + + + + iaridepm.enu1 + + + + + + + debuggergui.enu1 + + + + + + + + + + -2 + -2 + 718 + 329 + -2 + -2 + 200 + 200 + 119048 + 203252 + 197024 + 731707 + + + + + + + + + + + + + + + + -2 + -2 + 198 + 1682 + -2 + -2 + 1684 + 200 + 1002381 + 203252 + 119048 + 203252 + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..faba72123 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni @@ -0,0 +1,250 @@ +[DebugChecksum] +Checksum=-126027898 +[CodeCoverage] +Enabled=_ 0 +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[CallStack] +ShowArgs=0 +[Disassembly] +MixedMode=1 +[E1/E20] +BlockBits=15 +B0=1,0 +B1=1,1024 +B2=1,2048 +B3=1,3072 +StartEnabled=0 +StartSymbol= +StopEnabled=0 +StopSymbol= +RecordingCondition=0 +TraceMode=0 +TraceOutput=0 +TraceType=0 +TraceCapacity=0 +TraceRestart=0 +TraceTimeStamp=0 +TraceTimestampDivision=0 +TraceDataTransfer=1 +TraceStackOperation=1 +TraceStringOperation=1 +TraceArithmeticalOperation=1 +TraceLogicalOperation=1 +TraceBitOperation=1 +TraceFPU=1 +TraceException=1 +OperatingFrequency=0.000000 +PerfEnabled=0 +PerfCondition=0,0 +PerfDisplayTime=0,0 +PerfOnlyOnce=0,0 +PerfUse64Bit=0 +ChipName=R5F571ML +PinMode=0 +RegMode=0 +Endian=0 +ExtMemBlockNum=55 +ExtMemEndian_000=0 +ExtMemCondAccess_000=0 +ExtMemEndian_001=0 +ExtMemCondAccess_001=0 +ExtMemEndian_002=0 +ExtMemCondAccess_002=0 +ExtMemEndian_003=0 +ExtMemCondAccess_003=0 +ExtMemEndian_004=0 +ExtMemCondAccess_004=0 +ExtMemEndian_005=0 +ExtMemCondAccess_005=0 +ExtMemEndian_006=0 +ExtMemCondAccess_006=0 +ExtMemEndian_007=0 +ExtMemCondAccess_007=0 +ExtMemEndian_008=0 +ExtMemCondAccess_008=0 +ExtMemEndian_009=0 +ExtMemCondAccess_009=0 +ExtMemEndian_010=0 +ExtMemCondAccess_010=0 +ExtMemEndian_011=0 +ExtMemCondAccess_011=0 +ExtMemEndian_012=0 +ExtMemCondAccess_012=0 +ExtMemEndian_013=0 +ExtMemCondAccess_013=0 +ExtMemEndian_014=0 +ExtMemCondAccess_014=0 +ExtMemEndian_015=0 +ExtMemCondAccess_015=0 +ExtMemEndian_016=0 +ExtMemCondAccess_016=0 +ExtMemEndian_017=0 +ExtMemCondAccess_017=0 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+ExtMemCondAccess_040=0 +ExtMemEndian_041=0 +ExtMemCondAccess_041=0 +ExtMemEndian_042=0 +ExtMemCondAccess_042=0 +ExtMemEndian_043=0 +ExtMemCondAccess_043=0 +ExtMemEndian_044=0 +ExtMemCondAccess_044=0 +ExtMemEndian_045=0 +ExtMemCondAccess_045=0 +ExtMemEndian_046=0 +ExtMemCondAccess_046=0 +ExtMemEndian_047=0 +ExtMemCondAccess_047=0 +ExtMemEndian_048=0 +ExtMemCondAccess_048=0 +ExtMemEndian_049=0 +ExtMemCondAccess_049=0 +ExtMemEndian_050=0 +ExtMemCondAccess_050=0 +ExtMemEndian_051=0 +ExtMemCondAccess_051=0 +ExtMemEndian_052=0 +ExtMemCondAccess_052=0 +ExtMemEndian_053=0 +ExtMemCondAccess_053=0 +ExtMemEndian_054=0 +ExtMemCondAccess_054=0 +InputClock=25.000000 +ICLK=240.000000 +AllowClkSrcChange=0 +WorkRamStart=4096 +ComunicationSelect=0 +UseExtal=1 +JtagClock=10 +FINE=2000000 +EraseFlash=1,0 +DebugFlags=0,0 +EmulatorMode=0 +PowerTargetFromEmulator=1 +Voltage=0 +UseExtFlashFile_0=0 +ExtFlashFile_0= +EraseExtFlashBeforeDownload_0=0 +UseExtFlashFile_1=0 +ExtFlashFile_1= +EraseExtFlashBeforeDownload_1=0 +UseExtFlashFile_2=0 +ExtFlashFile_2= +EraseExtFlashBeforeDownload_2=0 +UseExtFlashFile_3=0 +ExtFlashFile_3= +EraseExtFlashBeforeDownload_3=0 +NeedInitExtMem=0 +NeedInit=0 +[CallStackLog] +Enabled=0 +[CallStackStripe] +ShowTiming=1 +[InterruptLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +SumSortOrder=0 +[DataLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +[Breakpoints2] +Count=0 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +Base=0 +UseAuto=0 +TypeViolation=1 +UnspecRange=1 +ActionState=1 +[Simulator] +Freq=98000000 +[DataSample] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +[DriverProfiling] +Enabled=0 +Mode=1 +Graph=0 +Symbiont=0 +Exclusions= +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Breakpoints] +Count=0 +[Monitor Execution] +Leave target running=0 +Release target=0 +[Trace1] +Enabled=0 +ShowSource=1 +[Aliases] +Count=0 +SuppressDialog=0 diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..26fa889f3 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,77 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 310272727 + + + + + + + 20121632481 + + + 20 + 1622 + + + + + + + + + TabID-13537-752 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Blinky_DemoRTOSDemo/FreeRTOS_SourceRTOSDemo/FreeRTOS_Source/portableRTOSDemo/Full_DemoRTOSDemo/Full_Demo/Standard_Demo_TasksRTOSDemo/cg_src + + + + 0 + + + TabID-29660-3316 + Build + Build + + + + TabID-19897-23353 + Debug Log + Debug-Log + + + + + 0 + + + + + + TextEditor$WS_DIR$\src\main.c000008351065106TextEditor$WS_DIR$\..\..\Source\tasks.c0000012964934349343TextEditor$WS_DIR$\..\Common\Minimal\IntQueue.c000003351674016740TextEditor$WS_DIR$\..\..\Source\portable\IAR\RX100\port.c0000000030100000010000001 + + + + + + + iaridepm.enu1-2-2627400-2-2200200119048203252239286639228-2-23131682-2-216843151002381320122119048203252 + + + + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos new file mode 100644 index 000000000..ecdc2c482 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos @@ -0,0 +1,2 @@ +[MainWindow] +WindowPlacement=_ 519 0 1619 872 3 diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h index cca782733..50f3250c9 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h @@ -71,8 +71,14 @@ #ifndef FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H -/* Hardware specifics. */ -#include "iodefine.h" +#ifdef __ICCRX__ + #include + #include +#endif + +#ifdef __GNUC__ + #include "iodefine.h" +#endif /*----------------------------------------------------------- * Application specific definitions. diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c index e6f42a206..5fc16a555 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c @@ -81,12 +81,6 @@ #include "IntQueueTimer.h" #include "IntQueue.h" -/* Hardware specifics. */ -#include "iodefine.h" - -void vIntQTimerISR0( void ) __attribute__ ((interrupt)); -void vIntQTimerISR1( void ) __attribute__ ((interrupt)); - #define tmrTIMER_0_1_FREQUENCY ( 2000UL ) #define tmrTIMER_2_3_FREQUENCY ( 2111UL ) @@ -98,7 +92,7 @@ void vInitialiseTimerForIntQueueTest( void ) /* Give write access. */ SYSTEM.PRCR.WORD = 0xa502; - /* Cascade two 8bit timer channels to generate the interrupts. + /* Cascade two 8bit timer channels to generate the interrupts. 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are utilised for this test. */ @@ -121,11 +115,11 @@ void vInitialiseTimerForIntQueueTest( void ) /* 16 bit operation ( count from timer 1,2 ). */ TMR0.TCCR.BIT.CSS = 3; TMR2.TCCR.BIT.CSS = 3; - + /* Use PCLK as the input. */ TMR1.TCCR.BIT.CSS = 1; TMR3.TCCR.BIT.CSS = 1; - + /* Divide PCLK by 8. */ TMR1.TCCR.BIT.CKS = 2; TMR3.TCCR.BIT.CKS = 2; @@ -148,25 +142,46 @@ void vInitialiseTimerForIntQueueTest( void ) } /*-----------------------------------------------------------*/ -/* On vector 128. */ -void vIntQTimerISR0( void ) -{ - /* Enable interrupts to allow interrupt nesting. */ - __asm volatile( "setpsw i" ); +#ifdef __GNUC__ + + void vIntQTimerISR0( void ) __attribute__ ((interrupt)); + void vIntQTimerISR1( void ) __attribute__ ((interrupt)); + + void vIntQTimerISR0( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xFirstTimerHandler() ); + } + /*-----------------------------------------------------------*/ + void vIntQTimerISR1( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xSecondTimerHandler() ); + } + +#endif /* __GNUC__ */ + +#ifdef __ICCRX__ + +#pragma vector = VECT_TMR0_CMIA0 +__interrupt void vT0_1InterruptHandler( void ) +{ + __enable_interrupt(); portYIELD_FROM_ISR( xFirstTimerHandler() ); } /*-----------------------------------------------------------*/ -/* On vector 129. */ -void vIntQTimerISR1( void ) +#pragma vector = VECT_TMR2_CMIA2 +__interrupt void vT2_3InterruptHandler( void ) { - /* Enable interrupts to allow interrupt nesting. */ - __asm volatile( "setpsw i" ); - + __enable_interrupt(); portYIELD_FROM_ISR( xSecondTimerHandler() ); } - - +#endif /* __ICCRX__ */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S deleted file mode 100644 index 0d8d1e4cf..000000000 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S +++ /dev/null @@ -1,235 +0,0 @@ -;/* -; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. -; All rights reserved -; -; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. -; -; *************************************************************************** -; * * -; * FreeRTOS provides completely free yet professionally developed, * -; * robust, strictly quality controlled, supported, and cross * -; * platform software that has become a de facto standard. * -; * * -; * Help yourself get started quickly and support the FreeRTOS * -; * project by purchasing a FreeRTOS tutorial book, reference * -; * manual, or both from: http://www.FreeRTOS.org/Documentation * -; * * -; * Thank you! * -; * * -; *************************************************************************** -; -; This file is part of the FreeRTOS distribution. -; -; FreeRTOS is free software; you can redistribute it and/or modify it under -; the terms of the GNU General Public License (version 2) as published by the -; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. -; -; >>! NOTE: The modification to the GPL is included to allow you to distribute -; >>! a combined work that includes FreeRTOS without being obliged to provide -; >>! the source code for proprietary components outside of the FreeRTOS -; >>! kernel. -; -; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY -; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS -; FOR A PARTICULAR PURPOSE. Full license text is available from the following -; link: http://www.freertos.org/a00114.html -; -; 1 tab == 4 spaces! -; -; *************************************************************************** -; * * -; * Having a problem? Start by reading the FAQ "My application does * -; * not run, what could be wrong?" * -; * * -; * http://www.FreeRTOS.org/FAQHelp.html * -; * * -; *************************************************************************** -; -; http://www.FreeRTOS.org - Documentation, books, training, latest versions, -; license and Real Time Engineers Ltd. contact details.; -; -; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, -; including FreeRTOS+Trace - an indispensable productivity tool, a DOS -; compatible FAT file system, and our tiny thread aware UDP/IP stack. -; -; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High -; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS -; licenses offer ticketed support, indemnification and middleware. -; -; http://www.SafeRTOS.com - High Integrity Systems also provide a safety -; engineered and independently SIL3 certified version for use in safety and -; mission critical applications that require provable dependability. -; -; 1 tab == 4 spaces! -;*/ - - .global _vRegTest1Implementation - .global _vRegTest2Implementation - - .extern _ulRegTest1LoopCounter - .extern _ulRegTest2LoopCounter - - .text - - -;/* This function is explained in the comments at the top of main.c. */ -_vRegTest1Implementation: - - ; Put a known value in each register. - MOV.L #1, R1 - MOV.L #2, R2 - MOV.L #3, R3 - MOV.L #4, R4 - MOV.L #5, R5 - MOV.L #6, R6 - MOV.L #7, R7 - MOV.L #8, R8 - MOV.L #9, R9 - MOV.L #10, R10 - MOV.L #11, R11 - MOV.L #12, R12 - MOV.L #13, R13 - MOV.L #14, R14 - MOV.L #15, R15 - - ; Loop, checking each itteration that each register still contains the - ; expected value. -TestLoop1: - - ; Push the registers that are going to get clobbered. - PUSHM R14-R15 - - ; Increment the loop counter to show this task is still getting CPU time. - MOV.L #_ulRegTest1LoopCounter, R14 - MOV.L [ R14 ], R15 - ADD #1, R15 - MOV.L R15, [ R14 ] - - ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register. - MOV.L #1, R14 - MOV.L #0872E0H, R15 - MOV.B R14, [R15] - NOP - NOP - - ; Restore the clobbered registers. - POPM R14-R15 - - ; Now compare each register to ensure it still contains the value that was - ; set before this loop was entered. - CMP #1, R1 - BNE RegTest1Error - CMP #2, R2 - BNE RegTest1Error - CMP #3, R3 - BNE RegTest1Error - CMP #4, R4 - BNE RegTest1Error - CMP #5, R5 - BNE RegTest1Error - CMP #6, R6 - BNE RegTest1Error - CMP #7, R7 - BNE RegTest1Error - CMP #8, R8 - BNE RegTest1Error - CMP #9, R9 - BNE RegTest1Error - CMP #10, R10 - BNE RegTest1Error - CMP #11, R11 - BNE RegTest1Error - CMP #12, R12 - BNE RegTest1Error - CMP #13, R13 - BNE RegTest1Error - CMP #14, R14 - BNE RegTest1Error - CMP #15, R15 - BNE RegTest1Error - - ; All comparisons passed, start a new itteratio of this loop. - BRA TestLoop1 - -RegTest1Error: - ; A compare failed, just loop here so the loop counter stops incrementing - ; causing the check task to indicate the error. - BRA RegTest1Error -;/*-----------------------------------------------------------*/ - -;/* This function is explained in the comments at the top of main.c. */ -_vRegTest2Implementation: - - ; Put a known value in each register. - MOV.L #10, R1 - MOV.L #20, R2 - MOV.L #30, R3 - MOV.L #40, R4 - MOV.L #50, R5 - MOV.L #60, R6 - MOV.L #70, R7 - MOV.L #80, R8 - MOV.L #90, R9 - MOV.L #100, R10 - MOV.L #110, R11 - MOV.L #120, R12 - MOV.L #130, R13 - MOV.L #140, R14 - MOV.L #150, R15 - - ; Loop, checking on each itteration that each register still contains the - ; expected value. -TestLoop2: - - ; Push the registers that are going to get clobbered. - PUSHM R14-R15 - - ; Increment the loop counter to show this task is still getting CPU time. - MOV.L #_ulRegTest2LoopCounter, R14 - MOV.L [ R14 ], R15 - ADD #1, R15 - MOV.L R15, [ R14 ] - - ; Restore the clobbered registers. - POPM R14-R15 - - CMP #10, R1 - BNE RegTest2Error - CMP #20, R2 - BNE RegTest2Error - CMP #30, R3 - BNE RegTest2Error - CMP #40, R4 - BNE RegTest2Error - CMP #50, R5 - BNE RegTest2Error - CMP #60, R6 - BNE RegTest2Error - CMP #70, R7 - BNE RegTest2Error - CMP #80, R8 - BNE RegTest2Error - CMP #90, R9 - BNE RegTest2Error - CMP #100, R10 - BNE RegTest2Error - CMP #110, R11 - BNE RegTest2Error - CMP #120, R12 - BNE RegTest2Error - CMP #130, R13 - BNE RegTest2Error - CMP #140, R14 - BNE RegTest2Error - CMP #150, R15 - BNE RegTest2Error - - ; All comparisons passed, start a new itteratio of this loop. - BRA TestLoop2 - -RegTest2Error: - ; A compare failed, just loop here so the loop counter stops incrementing - ; - causing the check task to indicate the error. - BRA RegTest2Error - - .END diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_GCC.S b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_GCC.S new file mode 100644 index 000000000..0d8d1e4cf --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_GCC.S @@ -0,0 +1,235 @@ +;/* +; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. +; All rights reserved +; +; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. +; +; *************************************************************************** +; * * +; * FreeRTOS provides completely free yet professionally developed, * +; * robust, strictly quality controlled, supported, and cross * +; * platform software that has become a de facto standard. * +; * * +; * Help yourself get started quickly and support the FreeRTOS * +; * project by purchasing a FreeRTOS tutorial book, reference * +; * manual, or both from: http://www.FreeRTOS.org/Documentation * +; * * +; * Thank you! * +; * * +; *************************************************************************** +; +; This file is part of the FreeRTOS distribution. +; +; FreeRTOS is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License (version 2) as published by the +; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. +; +; >>! NOTE: The modification to the GPL is included to allow you to distribute +; >>! a combined work that includes FreeRTOS without being obliged to provide +; >>! the source code for proprietary components outside of the FreeRTOS +; >>! kernel. +; +; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +; FOR A PARTICULAR PURPOSE. Full license text is available from the following +; link: http://www.freertos.org/a00114.html +; +; 1 tab == 4 spaces! +; +; *************************************************************************** +; * * +; * Having a problem? Start by reading the FAQ "My application does * +; * not run, what could be wrong?" * +; * * +; * http://www.FreeRTOS.org/FAQHelp.html * +; * * +; *************************************************************************** +; +; http://www.FreeRTOS.org - Documentation, books, training, latest versions, +; license and Real Time Engineers Ltd. contact details.; +; +; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, +; including FreeRTOS+Trace - an indispensable productivity tool, a DOS +; compatible FAT file system, and our tiny thread aware UDP/IP stack. +; +; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High +; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS +; licenses offer ticketed support, indemnification and middleware. +; +; http://www.SafeRTOS.com - High Integrity Systems also provide a safety +; engineered and independently SIL3 certified version for use in safety and +; mission critical applications that require provable dependability. +; +; 1 tab == 4 spaces! +;*/ + + .global _vRegTest1Implementation + .global _vRegTest2Implementation + + .extern _ulRegTest1LoopCounter + .extern _ulRegTest2LoopCounter + + .text + + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest1Implementation: + + ; Put a known value in each register. + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ; Loop, checking each itteration that each register still contains the + ; expected value. +TestLoop1: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest1LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register. + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ; Restore the clobbered registers. + POPM R14-R15 + + ; Now compare each register to ensure it still contains the value that was + ; set before this loop was entered. + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop1 + +RegTest1Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; causing the check task to indicate the error. + BRA RegTest1Error +;/*-----------------------------------------------------------*/ + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest2Implementation: + + ; Put a known value in each register. + MOV.L #10, R1 + MOV.L #20, R2 + MOV.L #30, R3 + MOV.L #40, R4 + MOV.L #50, R5 + MOV.L #60, R6 + MOV.L #70, R7 + MOV.L #80, R8 + MOV.L #90, R9 + MOV.L #100, R10 + MOV.L #110, R11 + MOV.L #120, R12 + MOV.L #130, R13 + MOV.L #140, R14 + MOV.L #150, R15 + + ; Loop, checking on each itteration that each register still contains the + ; expected value. +TestLoop2: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest2LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Restore the clobbered registers. + POPM R14-R15 + + CMP #10, R1 + BNE RegTest2Error + CMP #20, R2 + BNE RegTest2Error + CMP #30, R3 + BNE RegTest2Error + CMP #40, R4 + BNE RegTest2Error + CMP #50, R5 + BNE RegTest2Error + CMP #60, R6 + BNE RegTest2Error + CMP #70, R7 + BNE RegTest2Error + CMP #80, R8 + BNE RegTest2Error + CMP #90, R9 + BNE RegTest2Error + CMP #100, R10 + BNE RegTest2Error + CMP #110, R11 + BNE RegTest2Error + CMP #120, R12 + BNE RegTest2Error + CMP #130, R13 + BNE RegTest2Error + CMP #140, R14 + BNE RegTest2Error + CMP #150, R15 + BNE RegTest2Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop2 + +RegTest2Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; - causing the check task to indicate the error. + BRA RegTest2Error + + .END diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s new file mode 100644 index 000000000..b5e790f4d --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s @@ -0,0 +1,269 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + PUBLIC _vRegTest1Implementation + PUBLIC _vRegTest2Implementation + + EXTERN _ulRegTest1CycleCount + EXTERN _ulRegTest2CycleCount + + RSEG CODE:CODE(4) + +_vRegTest1Implementation: + + /* Set each register to a known value. */ + MOV.L #0x33333333, R15 + MVTACHI R15 + MOV.L #0x44444444, R15 + MVTACLO R15 + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + /* Loop, checking each iteration that each register still contains the + expected value. */ + TestLoop1: + + /* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + /* Increment the loop counter to show this task is still getting CPU + time. */ + MOV.L #_ulRegTest1CycleCount, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + /* Yield to extend the text coverage. Set the bit in the ITU SWINTR + register. */ + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + /* Check the accumulator value. */ + MVFACHI R15 + CMP #0x33333333, R15 + BNE RegTest2Error + MVFACMI R15 + CMP #0x33334444, R15 + BNE RegTest2Error + + /* Restore the clobbered registers. */ + POPM R14-R15 + + /* Now compare each register to ensure it still contains the value that + was set before this loop was entered. */ + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + /* All comparisons passed, start a new iteration of this loop. */ + BRA TestLoop1 + + /* A compare failed, just loop here so the loop counter stops + incrementing causing the check timer to indicate the error. */ + RegTest1Error: + BRA RegTest1Error + +/*-----------------------------------------------------------*/ + +_vRegTest2Implementation: + + /* Set each register to a known value. */ + MOV.L #0x11111111, R15 + MVTACHI R15 + MOV.L #0x22222222, R15 + MVTACLO R15 + MOV.L #100, R1 + MOV.L #200, R2 + MOV.L #300, R3 + MOV.L #400, R4 + MOV.L #500, R5 + MOV.L #600, R6 + MOV.L #700, R7 + MOV.L #800, R8 + MOV.L #900, R9 + MOV.L #1000, R10 + MOV.L #1001, R11 + MOV.L #1002, R12 + MOV.L #1003, R13 + MOV.L #1004, R14 + MOV.L #1005, R15 + + /* Loop, checking each iteration that each register still contains the + expected value. */ + TestLoop2: + + /* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + /* Increment the loop counter to show this task is still getting CPU + time. */ + MOV.L #_ulRegTest2CycleCount, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + /* Check the accumulator value. */ + MVFACHI R15 + CMP #0x11111111, R15 + BNE RegTest2Error + MVFACMI R15 + CMP #0x11112222, R15 + BNE RegTest2Error + + /* Restore the clobbered registers. */ + POPM R14-R15 + + /* Now compare each register to ensure it still contains the value that + was set before this loop was entered. */ + CMP #100, R1 + BNE RegTest2Error + CMP #200, R2 + BNE RegTest2Error + CMP #300, R3 + BNE RegTest2Error + CMP #400, R4 + BNE RegTest2Error + CMP #500, R5 + BNE RegTest2Error + CMP #600, R6 + BNE RegTest2Error + CMP #700, R7 + BNE RegTest2Error + CMP #800, R8 + BNE RegTest2Error + CMP #900, R9 + BNE RegTest2Error + CMP #1000, R10 + BNE RegTest2Error + CMP #1001, R11 + BNE RegTest2Error + CMP #1002, R12 + BNE RegTest2Error + CMP #1003, R13 + BNE RegTest2Error + CMP #1004, R14 + BNE RegTest2Error + CMP #1005, R15 + BNE RegTest2Error + + /* All comparisons passed, start a new iteration of this loop. */ + BRA TestLoop2 + + /* A compare failed, just loop here so the loop counter stops + incrementing causing the check timer to indicate the error. */ + RegTest2Error: + BRA RegTest2Error + +/*-----------------------------------------------------------*/ + + END + diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h new file mode 100644 index 000000000..1516a0753 --- /dev/null +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h @@ -0,0 +1,86 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef PRIORITY_DEFINITIONS_H +#define PRIORITY_DEFINITIONS_H + +#ifndef __IASMRX__ + #error This file is only intended to be included from the FreeRTOS IAR port layer assembly file. +#endif + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#endif /* PRIORITY_DEFINITIONS_H */ diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h index 370d54947..0de90f97e 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h @@ -2,15 +2,15 @@ * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. +* applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * @@ -75,7 +75,7 @@ typedef enum { Typedef definitions ***********************************************************************************************************************/ #ifndef __TYPEDEF__ - #ifndef _STD_USING_INT_TYPES + #if !defined( _STD_USING_INT_TYPES ) && !defined( _STDINT ) #define _SYS_INT_TYPES_H #ifndef _STD_USING_BIT_TYPES #ifndef __int8_t_defined diff --git a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/main.c b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/main.c index 4e39c6d07..9c0497643 100644 --- a/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/main.c +++ b/FreeRTOS/Demo/RX113-RSK_GCC_e2studio_IAR/src/main.c @@ -95,11 +95,10 @@ #include #include "r_cg_macrodriver.h" #include "r_cg_sci.h" -#include "r_rsk_async.h" /* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 /*-----------------------------------------------------------*/ @@ -253,6 +252,26 @@ const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500 /* Reneable register protection. */ SYSTEM.PRCR.WORD = ulDisableRegisterWrite; } +/*-----------------------------------------------------------*/ + +#ifdef __ICCRX__ + + #include + + /* Called from the C start up code when compiled with IAR. */ + #pragma diag_suppress = Pm011 + int __low_level_init(void) + #pragma diag_default = Pm011 + { + extern void R_Systeminit( void ); + + __disable_interrupt(); + R_Systeminit(); + + return (int)(1U); + } + +#endif /* __ICCRX__ */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.HardwareDebuglinker b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.HardwareDebuglinker new file mode 100644 index 000000000..8174ece4b --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.HardwareDebuglinker @@ -0,0 +1,148 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.cproject b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.cproject new file mode 100644 index 000000000..8f22596ce --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.cproject @@ -0,0 +1,161 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.info b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.info new file mode 100644 index 000000000..209c49b60 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.info @@ -0,0 +1,7 @@ +TOOL_CHAIN=KPIT GNURX-ELF Toolchain +VERSION=v15.01 +TC_INSTALL=C:\Program Files (x86)\KPIT\GNURXv15.01-ELF\rx-elf\rx-elf\ +GCC_STRING=4.8-GNURX_v15.01 +VERSION_IDE= +E2STUDIO_VERSION=4.0.2.008 +ACTIVE_CONFIGURATION=HardwareDebug \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.project b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.project new file mode 100644 index 000000000..7708d21e5 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.project @@ -0,0 +1,232 @@ + + + RTOSDemo + + + + + + com.renesas.cdt.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.renesas.cdt.core.kpitcnature + com.renesas.cdt.core.kpitccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Main_Full/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/Main_Full/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1442956878652 + src/FreeRTOS_Source + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-croutine.c + + + + 1442956966430 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1442956966454 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1442958159158 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1442958159162 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1442958159166 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1442958159170 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-death.c + + + + 1442958159175 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1442958159180 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1442958159185 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1442958159190 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1442958159195 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 1442958159200 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1442958159205 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1442958159209 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1442958159214 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1442958159219 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1442958159224 + src/Main_Full/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TimerDemo.c + + + + 1442957000626 + src/FreeRTOS_Source/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-RX600v2 + + + + 1442956924089 + src/FreeRTOS_Source/portable/MemMang + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-heap_4.c + + + + + + FREERTOS_ROOT + $%7BPARENT-3-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgproject.cgp b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgproject.cgp new file mode 100644 index 000000000..e35cf4b0a --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/CodeGenerator/cgproject.cgp @@ -0,0 +1,184968 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/Dependency_Scan_Preferences.prefs b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/Dependency_Scan_Preferences.prefs new file mode 100644 index 000000000..c52c797ff --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/Dependency_Scan_Preferences.prefs @@ -0,0 +1,4 @@ +Build\ project\ excluding\ the\ dependencies=false +Re-generate\ and\ use\ dependencies\ during\ project\ build=true +Use\ existing\ dependencies\ during\ project\ build=false +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/Project_Generation_Prefrences.prefs b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/Project_Generation_Prefrences.prefs new file mode 100644 index 000000000..fb8addeff --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/Project_Generation_Prefrences.prefs @@ -0,0 +1,24 @@ +Library\ Generator\ Command=rx-elf-libgen +com.renesas.cdt.core.Assembler.option.includeFileDirectories="${workspace_loc\:/${ProjName}}/src"; +com.renesas.cdt.core.Compiler.option.includeFileDir.724701468="${TCINSTALL}/rx-elf/optlibinc"; +com.renesas.cdt.core.LibraryGenerator.option.ctype=false +com.renesas.cdt.core.LibraryGenerator.option.libraryType=Project-Built +com.renesas.cdt.core.LibraryGenerator.option.math=false +com.renesas.cdt.core.LibraryGenerator.option.selectLibrary=Optimized +com.renesas.cdt.core.LibraryGenerator.option.stdio=true +com.renesas.cdt.core.LibraryGenerator.option.stdlib=true +com.renesas.cdt.core.LibraryGenerator.option.string=true +com.renesas.cdt.core.Linker.option.userDefinedOptions=; +com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType=RX200 +com.renesas.cdt.rx.HardwareDebug.Compiler.option.cpuType.2093890278=RX200 +com.renesas.cdt.rx.HardwareDebug.Compiler.option.dataEndian=Little-endian data +com.renesas.cdt.rx.HardwareDebug.Compiler.option.disableFPUInstructions=false +com.renesas.cdt.rx.HardwareDebug.Compiler.option.genCodeForRX610=false +com.renesas.cdt.rx.HardwareDebug.Compiler.option.genCodeForRX64M=true +com.renesas.cdt.rx.HardwareDebug.Compiler.option.generateRXas100output=false +com.renesas.cdt.rx.HardwareDebug.Compiler.option.macroDefines=__RX_LITTLE_ENDIAN__\=1; +com.renesas.cdt.rx.HardwareDebug.Compiler.option.make64bitDouble=false +com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveLibraryFiles=${BuildArtifactFileBaseName};gcc; +com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveSearchDirectories="${CONFIGDIR}";"${TCINSTALL}/lib/gcc/rx-elf/${GCC_VERSION}"; +com.renesas.cdt.rx.HardwareDebug.Linker.option.archiveSearchDirectories.1977851385="${CONFIGDIR}";"${TCINSTALL}/lib/gcc/rx-elf/${GCC_VERSION}"; +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/language.settings.xml b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/language.settings.xml new file mode 100644 index 000000000..3ab9b783c --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/.settings/language.settings.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..34d053165 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/RTOSDemo HardwareDebug.launch @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/custom.bat b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/custom.bat new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/main.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/main.c new file mode 100644 index 000000000..56ce5a2c9 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/main.c @@ -0,0 +1,5 @@ + +int main( void ) +{ + return 0; +} diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/makefile.init b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/makefile.init new file mode 100644 index 000000000..0835091e2 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/makefile.init @@ -0,0 +1,5 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +PATH := $(PATH):C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\bin;C:\PROGRA~2\KPIT\GNURXV~1.01-\rx-elf\rx-elf\libexec\gcc\rx-elf\4.8-GNURX_v15.01 \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..0a919d156 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,230 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { +//_RB_ LED0 = !LED0; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h new file mode 100644 index 000000000..f0c3446bf --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Renesas hardware definition header. */ +#include "iodefine.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( 52000000UL ) /*_RB_ guess*/ +#define configPERIPHERAL_CLOCK_HZ ( 26000000UL ) /*_RB_ guess*/ +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configMAX_PRIORITIES ( 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* The peripheral used to generate the tick interrupt is configured as part of +the application code. This constant should be set to the vector number of the +peripheral chosen. As supplied this is CMT0. */ +#define configTICK_VECTOR _CMT0_CMI0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +void vAssertCalled( void ); +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Override some of the priorities set in the common demo tasks. This is +required to ensure flase positive timing errors are not reported. */ +#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) +#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 ) +#define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 3 ) + + +/*----------------------------------------------------------- + * Ethernet configuration. + *-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x12 +#define configMAC_ADDR2 0x13 +#define configMAC_ADDR3 0x10 +#define configMAC_ADDR4 0x15 +#define configMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define configIP_ADDR0 192 +#define configIP_ADDR1 168 +#define configIP_ADDR2 0 +#define configIP_ADDR3 200 + +/* Netmask configuration. */ +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.c new file mode 100644 index 000000000..5fc16a555 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.c @@ -0,0 +1,187 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file contains the non-portable and therefore RX62N specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2111UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + /* Give write access. */ + SYSTEM.PRCR.WORD = 0xa502; + + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Set interrupt priority and enable. */ + IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IR( TMR0, CMIA0 ) = 0U; + IEN( TMR0, CMIA0 ) = 1U; + + /* Do the same for TMR2, but to vector 129. */ + IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + IR( TMR2, CMIA2 ) = 0U; + IEN( TMR2, CMIA2 ) = 1U; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +#ifdef __GNUC__ + + void vIntQTimerISR0( void ) __attribute__ ((interrupt)); + void vIntQTimerISR1( void ) __attribute__ ((interrupt)); + + void vIntQTimerISR0( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xFirstTimerHandler() ); + } + /*-----------------------------------------------------------*/ + + void vIntQTimerISR1( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xSecondTimerHandler() ); + } + +#endif /* __GNUC__ */ + +#ifdef __ICCRX__ + +#pragma vector = VECT_TMR0_CMIA0 +__interrupt void vT0_1InterruptHandler( void ) +{ + __enable_interrupt(); + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +#pragma vector = VECT_TMR2_CMIA2 +__interrupt void vT2_3InterruptHandler( void ) +{ + __enable_interrupt(); + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} + +#endif /* __ICCRX__ */ + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.h new file mode 100644 index 000000000..fcf9f8c1f --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/RegTest_GCC.S b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/RegTest_GCC.S new file mode 100644 index 000000000..0d8d1e4cf --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/RegTest_GCC.S @@ -0,0 +1,235 @@ +;/* +; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. +; All rights reserved +; +; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. +; +; *************************************************************************** +; * * +; * FreeRTOS provides completely free yet professionally developed, * +; * robust, strictly quality controlled, supported, and cross * +; * platform software that has become a de facto standard. * +; * * +; * Help yourself get started quickly and support the FreeRTOS * +; * project by purchasing a FreeRTOS tutorial book, reference * +; * manual, or both from: http://www.FreeRTOS.org/Documentation * +; * * +; * Thank you! * +; * * +; *************************************************************************** +; +; This file is part of the FreeRTOS distribution. +; +; FreeRTOS is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License (version 2) as published by the +; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. +; +; >>! NOTE: The modification to the GPL is included to allow you to distribute +; >>! a combined work that includes FreeRTOS without being obliged to provide +; >>! the source code for proprietary components outside of the FreeRTOS +; >>! kernel. +; +; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +; FOR A PARTICULAR PURPOSE. Full license text is available from the following +; link: http://www.freertos.org/a00114.html +; +; 1 tab == 4 spaces! +; +; *************************************************************************** +; * * +; * Having a problem? Start by reading the FAQ "My application does * +; * not run, what could be wrong?" * +; * * +; * http://www.FreeRTOS.org/FAQHelp.html * +; * * +; *************************************************************************** +; +; http://www.FreeRTOS.org - Documentation, books, training, latest versions, +; license and Real Time Engineers Ltd. contact details.; +; +; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, +; including FreeRTOS+Trace - an indispensable productivity tool, a DOS +; compatible FAT file system, and our tiny thread aware UDP/IP stack. +; +; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High +; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS +; licenses offer ticketed support, indemnification and middleware. +; +; http://www.SafeRTOS.com - High Integrity Systems also provide a safety +; engineered and independently SIL3 certified version for use in safety and +; mission critical applications that require provable dependability. +; +; 1 tab == 4 spaces! +;*/ + + .global _vRegTest1Implementation + .global _vRegTest2Implementation + + .extern _ulRegTest1LoopCounter + .extern _ulRegTest2LoopCounter + + .text + + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest1Implementation: + + ; Put a known value in each register. + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ; Loop, checking each itteration that each register still contains the + ; expected value. +TestLoop1: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest1LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register. + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ; Restore the clobbered registers. + POPM R14-R15 + + ; Now compare each register to ensure it still contains the value that was + ; set before this loop was entered. + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop1 + +RegTest1Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; causing the check task to indicate the error. + BRA RegTest1Error +;/*-----------------------------------------------------------*/ + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest2Implementation: + + ; Put a known value in each register. + MOV.L #10, R1 + MOV.L #20, R2 + MOV.L #30, R3 + MOV.L #40, R4 + MOV.L #50, R5 + MOV.L #60, R6 + MOV.L #70, R7 + MOV.L #80, R8 + MOV.L #90, R9 + MOV.L #100, R10 + MOV.L #110, R11 + MOV.L #120, R12 + MOV.L #130, R13 + MOV.L #140, R14 + MOV.L #150, R15 + + ; Loop, checking on each itteration that each register still contains the + ; expected value. +TestLoop2: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest2LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Restore the clobbered registers. + POPM R14-R15 + + CMP #10, R1 + BNE RegTest2Error + CMP #20, R2 + BNE RegTest2Error + CMP #30, R3 + BNE RegTest2Error + CMP #40, R4 + BNE RegTest2Error + CMP #50, R5 + BNE RegTest2Error + CMP #60, R6 + BNE RegTest2Error + CMP #70, R7 + BNE RegTest2Error + CMP #80, R8 + BNE RegTest2Error + CMP #90, R9 + BNE RegTest2Error + CMP #100, R10 + BNE RegTest2Error + CMP #110, R11 + BNE RegTest2Error + CMP #120, R12 + BNE RegTest2Error + CMP #130, R13 + BNE RegTest2Error + CMP #140, R14 + BNE RegTest2Error + CMP #150, R15 + BNE RegTest2Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop2 + +RegTest2Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; - causing the check task to indicate the error. + BRA RegTest2Error + + .END diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/main_full.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/main_full.c new file mode 100644 index 000000000..8aec86bc7 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Main_Full/main_full.c @@ -0,0 +1,499 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the registers, as described at the top of this file. The nature of these + * files necessitates that they are written in assembly, but the entry points + * are kept in the C file for the convenience of checking the task parameter. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); +void vRegTest1Implementation( void ); +void vRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/* String for display in the web server. It is set to an error message if the +check task detects an error. */ +const char *pcStatusMessage = "All tasks running without error"; +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ +//_RB_ LED0 = !LED0; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + pcStatusMessage = "Error found in at least one task."; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + vRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + vRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.c new file mode 100644 index 000000000..42c93041f --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.c @@ -0,0 +1,554 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : interrupt_handlers.c */ +/* DESCRIPTION : Interrupt Handler */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/************************************************************************/ +/* File Version: V1.00 */ +/* History : 0.50 (2014-09-18) [Hardware Manual Revision : 0.50] */ +/* : 1.00 (2015-05-18) [Hardware Manual Revision : 1.00] */ +/* Date Modified: 21/07/2015 */ +/************************************************************************/ + +#include "interrupt_handlers.h" + +// INT_Exception(Supervisor Instruction) +void INT_Excep_SuperVisorInst(void){/* brk(); */} + +// INT_Exception(Access Instruction) +void INT_Excep_AccessInst(void){/* brk(); */} + +// INT_Exception(Undefined Instruction) +void INT_Excep_UndefinedInst(void){/* brk(); */} + +// INT_Exception(Floating Point) +void INT_Excep_FloatingPoint(void){/* brk(); */} + +// INT_NMI +void INT_NonMaskableInterrupt(void){/* brk(); */} + +// INT_Dummy +void INT_Dummy(void){/* brk(); */} + +// BRK +void INT_Excep_BRK(void){ /* wait(); */ } + +// BSC BUSERR +void INT_Excep_BSC_BUSERR(void){/* brk(); */} + +// FCU FRDYI +void INT_Excep_FCU_FRDYI(void){/* brk(); */} + +// ICU SWINT +void INT_Excep_ICU_SWINT(void){/* brk(); */} + +// CMT0 CMI0 +void INT_Excep_CMT0_CMI0(void){/* brk(); */} + +// CMT1 CMI1 +void INT_Excep_CMT1_CMI1(void){/* brk(); */} + +// CMT2 CMI2 +void INT_Excep_CMT2_CMI2(void){/* brk(); */} + +// CMT3 CMI3 +void INT_Excep_CMT3_CMI3(void){/* brk(); */} + +// CAC FERRF +void INT_Excep_CAC_FERRF(void){/* brk(); */} + +// CAC MENDF +void INT_Excep_CAC_MENDF(void){/* brk(); */} + +// CAC OVFF +void INT_Excep_CAC_OVFF(void){/* brk(); */} + +// USB0 D0FIFO0 +void INT_Excep_USB0_D0FIFO0(void){/* brk(); */} + +// USB0 D1FIFO0 +void INT_Excep_USB0_D1FIFO0(void){/* brk(); */} + +// USB0 USBI0 +void INT_Excep_USB0_USBI0(void){/* brk(); */} + +// SDHI SBFAI +void INT_Excep_SDHI_SBFAI(void){/* brk(); */} + +// SDHI CDETI +void INT_Excep_SDHI_CDETI(void){/* brk(); */} + +// SDHI CACI +void INT_Excep_SDHI_CACI(void){/* brk(); */} + +// SDHI SDACI +void INT_Excep_SDHI_SDACI(void){/* brk(); */} + +// RSPI0 SPEI0 +void INT_Excep_RSPI0_SPEI0(void){/* brk(); */} + +// RSPI0 SPRI0 +void INT_Excep_RSPI0_SPRI0(void){/* brk(); */} + +// RSPI0 SPTI0 +void INT_Excep_RSPI0_SPTI0(void){/* brk(); */} + +// RSPI0 SPII0 +void INT_Excep_RSPI0_SPII0(void){/* brk(); */} + +// RSCAN COMFRXINT +void INT_Excep_RSCAN_COMFRXINT(void){/* brk(); */} + +// RSCAN RXFINT +void INT_Excep_RSCAN_RXFINT(void){/* brk(); */} + +// RSCAN TXINT +void INT_Excep_RSCAN_TXINT(void){/* brk(); */} + +// RSCAN CHERRINT +void INT_Excep_RSCAN_CHERRINT(void){/* brk(); */} + +// RSCAN GLERRINT +void INT_Excep_RSCAN_GLERRINT(void){/* brk(); */} + +// DOC DOPCF +void INT_Excep_DOC_DOPCF(void){/* brk(); */} + +// CMPB CMPB0 +void INT_Excep_CMPB_CMPB0(void){/* brk(); */} + +// CMPB CMPB1 +void INT_Excep_CMPB_CMPB1(void){/* brk(); */} + +// CTSU CTSUWR +void INT_Excep_CTSU_CTSUWR(void){/* brk(); */} + +// CTSU CTSURD +void INT_Excep_CTSU_CTSURD(void){/* brk(); */} + +// CTSU CTSUFN +void INT_Excep_CTSU_CTSUFN(void){/* brk(); */} + +// RTC CUP +void INT_Excep_RTC_CUP(void){/* brk(); */} + +// ICU IRQ0 +void INT_Excep_ICU_IRQ0(void){/* brk(); */} + +// ICU IRQ1 +void INT_Excep_ICU_IRQ1(void){/* brk(); */} + +// ICU IRQ2 +void INT_Excep_ICU_IRQ2(void){/* brk(); */} + +// ICU IRQ3 +void INT_Excep_ICU_IRQ3(void){/* brk(); */} + +// ICU IRQ4 +void INT_Excep_ICU_IRQ4(void){/* brk(); */} + +// ICU IRQ5 +void INT_Excep_ICU_IRQ5(void){/* brk(); */} + +// ICU IRQ6 +void INT_Excep_ICU_IRQ6(void){/* brk(); */} + +// ICU IRQ7 +void INT_Excep_ICU_IRQ7(void){/* brk(); */} + +// ELC ELSR8I +void INT_Excep_ELC_ELSR8I(void){/* brk(); */} + +// LVD LVD1 +void INT_Excep_LVD_LVD1(void){/* brk(); */} + +// LVD LVD2 +void INT_Excep_LVD_LVD2(void){/* brk(); */} + +// CMPA CMPA1 +//void INT_Excep_CMPA_CMPA1(void){/* brk(); */} + +// CMPA CMPA2 +//void INT_Excep_CMPA_CMPA2(void){/* brk(); */} + +// USB0 USBR0 +void INT_Excep_USB0_USBR0(void){/* brk(); */} + +// VBATT VBTLVDI +void INT_Excep_VBATT_VBTLVDI(void){/* brk(); */} + +// RTC ALM +void INT_Excep_RTC_ALM(void){/* brk(); */} + +// RTC PRD +void INT_Excep_RTC_PRD(void){/* brk(); */} + +// S12AD S12ADI0 +void INT_Excep_S12AD_S12ADI0(void){/* brk(); */} + +// S12AD GBADI +void INT_Excep_S12AD_GBADI(void){/* brk(); */} + +// CMPB1 CMPB2 +void INT_Excep_CMPB1_CMPB2(void){/* brk(); */} + +// CMPB1 CMPB3 +void INT_Excep_CMPB1_CMPB3(void){/* brk(); */} + +// ELC ELSR18I +void INT_Excep_ELC_ELSR18I(void){/* brk(); */} + +// ELC ELSR19I +void INT_Excep_ELC_ELSR19I(void){/* brk(); */} + +// SSI0 SSIF0 +void INT_Excep_SSI0_SSIF0(void){/* brk(); */} + +// SSI0 SSIRXI0 +void INT_Excep_SSI0_SSIRXI0(void){/* brk(); */} + +// SSI0 SSITXI0 +void INT_Excep_SSI0_SSITXI0(void){/* brk(); */} + +// SECURITY RD +void INT_Excep_SECURITY_RD(void){/* brk(); */} + +// SECURITY WR +void INT_Excep_SECURITY_WR(void){/* brk(); */} + +// SECURITY ERR +void INT_Excep_SECURITY_ERR(void){/* brk(); */} + +// MTU0 TGIA0 +void INT_Excep_MTU0_TGIA0(void){/* brk(); */} + +// MTU0 TGIB0 +void INT_Excep_MTU0_TGIB0(void){/* brk(); */} + +// MTU0 TGIC0 +void INT_Excep_MTU0_TGIC0(void){/* brk(); */} + +// MTU0 TGID0 +void INT_Excep_MTU0_TGID0(void){/* brk(); */} + +// MTU0 TCIV0 +void INT_Excep_MTU0_TCIV0(void){/* brk(); */} + +// MTU0 TGIE0 +void INT_Excep_MTU0_TGIE0(void){/* brk(); */} + +// MTU0 TGIF0 +void INT_Excep_MTU0_TGIF0(void){/* brk(); */} + +// MTU1 TGIA1 +void INT_Excep_MTU1_TGIA1(void){/* brk(); */} + +// MTU1 TGIB1 +void INT_Excep_MTU1_TGIB1(void){/* brk(); */} + +// MTU1 TCIV1 +void INT_Excep_MTU1_TCIV1(void){/* brk(); */} + +// MTU1 TCIU1 +void INT_Excep_MTU1_TCIU1(void){/* brk(); */} + +// MTU2 TGIA2 +void INT_Excep_MTU2_TGIA2(void){/* brk(); */} + +// MTU2 TGIB2 +void INT_Excep_MTU2_TGIB2(void){/* brk(); */} + +// MTU2 TCIV2 +void INT_Excep_MTU2_TCIV2(void){/* brk(); */} + +// MTU2 TCIU2 +void INT_Excep_MTU2_TCIU2(void){/* brk(); */} + +// MTU3 TGIA3 +void INT_Excep_MTU3_TGIA3(void){/* brk(); */} + +// MTU3 TGIB3 +void INT_Excep_MTU3_TGIB3(void){/* brk(); */} + +// MTU3 TGIC3 +void INT_Excep_MTU3_TGIC3(void){/* brk(); */} + +// MTU3 TGID3 +void INT_Excep_MTU3_TGID3(void){/* brk(); */} + +// MTU3 TCIV3 +void INT_Excep_MTU3_TCIV3(void){/* brk(); */} + +// MTU4 TGIA4 +void INT_Excep_MTU4_TGIA4(void){/* brk(); */} + +// MTU4 TGIB4 +void INT_Excep_MTU4_TGIB4(void){/* brk(); */} + +// MTU4 TGIC4 +void INT_Excep_MTU4_TGIC4(void){/* brk(); */} + +// MTU4 TGID4 +void INT_Excep_MTU4_TGID4(void){/* brk(); */} + +// MTU4 TCIV4 +void INT_Excep_MTU4_TCIV4(void){/* brk(); */} + +// MTU5 TGIU5 +void INT_Excep_MTU5_TGIU5(void){/* brk(); */} + +// MTU5 TGIV5 +void INT_Excep_MTU5_TGIV5(void){/* brk(); */} + +// MTU5 TGIW5 +void INT_Excep_MTU5_TGIW5(void){/* brk(); */} + +// TPU0 TGI0A +void INT_Excep_TPU0_TGI0A(void){/* brk(); */} + +// TPU0 TGI0B +void INT_Excep_TPU0_TGI0B(void){/* brk(); */} + +// TPU0 TGI0C +void INT_Excep_TPU0_TGI0C(void){/* brk(); */} + +// TPU0 TGI0D +void INT_Excep_TPU0_TGI0D(void){/* brk(); */} + +// TPU0 TCI0V +void INT_Excep_TPU0_TCI0V(void){/* brk(); */} + +// TPU1 TGI1A +void INT_Excep_TPU1_TGI1A(void){/* brk(); */} + +// TPU1 TGI1B +void INT_Excep_TPU1_TGI1B(void){/* brk(); */} + +// TPU1 TCI1V +void INT_Excep_TPU1_TCI1V(void){/* brk(); */} + +// TPU1 TCI1U +void INT_Excep_TPU1_TCI1U(void){/* brk(); */} + +// TPU2 TGI2A +void INT_Excep_TPU2_TGI2A(void){/* brk(); */} + +// TPU2 TGI2B +void INT_Excep_TPU2_TGI2B(void){/* brk(); */} + +// TPU2 TCI2V +void INT_Excep_TPU2_TCI2V(void){/* brk(); */} + +// TPU2 TCI2U +void INT_Excep_TPU2_TCI2U(void){/* brk(); */} + +// TPU3 TGI3A +void INT_Excep_TPU3_TGI3A(void){/* brk(); */} + +// TPU3 TGI3B +void INT_Excep_TPU3_TGI3B(void){/* brk(); */} + +// TPU3 TGI3C +void INT_Excep_TPU3_TGI3C(void){/* brk(); */} + +// TPU3 TGI3D +void INT_Excep_TPU3_TGI3D(void){/* brk(); */} + +// TPU3 TCI3V +void INT_Excep_TPU3_TCI3V(void){/* brk(); */} + +// TPU4 TGI4A +void INT_Excep_TPU4_TGI4A(void){/* brk(); */} + +// TPU4 TGI4B +void INT_Excep_TPU4_TGI4B(void){/* brk(); */} + +// TPU4 TCI4V +void INT_Excep_TPU4_TCI4V(void){/* brk(); */} + +// TPU4 TCI4U +void INT_Excep_TPU4_TCI4U(void){/* brk(); */} + +// TPU5 TGI5A +void INT_Excep_TPU5_TGI5A(void){/* brk(); */} + +// TPU5 TGI5B +void INT_Excep_TPU5_TGI5B(void){/* brk(); */} + +// TPU5 TCI5V +void INT_Excep_TPU5_TCI5V(void){/* brk(); */} + +// TPU5 TCI5U +void INT_Excep_TPU5_TCI5U(void){/* brk(); */} + +// POE OEI1 +void INT_Excep_POE_OEI1(void){/* brk(); */} + +// POE OEI2 +void INT_Excep_POE_OEI2(void){/* brk(); */} + +// TMR0 CMIA0 +void INT_Excep_TMR0_CMIA0(void){/* brk(); */} + +// TMR0 CMIB0 +void INT_Excep_TMR0_CMIB0(void){/* brk(); */} + +// TMR0 OVI0 +void INT_Excep_TMR0_OVI0(void){/* brk(); */} + +// TMR1 CMIA1 +void INT_Excep_TMR1_CMIA1(void){/* brk(); */} + +// TMR1 CMIB1 +void INT_Excep_TMR1_CMIB1(void){/* brk(); */} + +// TMR1 OVI1 +void INT_Excep_TMR1_OVI1(void){/* brk(); */} + +// TMR2 CMIA2 +void INT_Excep_TMR2_CMIA2(void){/* brk(); */} + +// TMR2 CMIB2 +void INT_Excep_TMR2_CMIB2(void){/* brk(); */} + +// TMR2 OVI2 +void INT_Excep_TMR2_OVI2(void){/* brk(); */} + +// TMR3 CMIA3 +void INT_Excep_TMR3_CMIA3(void){/* brk(); */} + +// TMR3 CMIB3 +void INT_Excep_TMR3_CMIB3(void){/* brk(); */} + +// TMR3 OVI3 +void INT_Excep_TMR3_OVI3(void){/* brk(); */} + +// DMAC DMAC0I +void INT_Excep_DMAC_DMAC0I(void){/* brk(); */} + +// DMAC DMAC1I +void INT_Excep_DMAC_DMAC1I(void){/* brk(); */} + +// DMAC DMAC2I +void INT_Excep_DMAC_DMAC2I(void){/* brk(); */} + +// DMAC DMAC3I +void INT_Excep_DMAC_DMAC3I(void){/* brk(); */} + +// SCI0 ERI0 +void INT_Excep_SCI0_ERI0(void){/* brk(); */} + +// SCI0 RXI0 +void INT_Excep_SCI0_RXI0(void){/* brk(); */} + +// SCI0 TXI0 +void INT_Excep_SCI0_TXI0(void){/* brk(); */} + +// SCI0 TEI0 +void INT_Excep_SCI0_TEI0(void){/* brk(); */} + +// SCI1 ERI1 +void INT_Excep_SCI1_ERI1(void){/* brk(); */} + +// SCI1 RXI1 +void INT_Excep_SCI1_RXI1(void){/* brk(); */} + +// SCI1 TXI1 +void INT_Excep_SCI1_TXI1(void){/* brk(); */} + +// SCI1 TEI1 +void INT_Excep_SCI1_TEI1(void){/* brk(); */} + +// SCI5 ERI5 +void INT_Excep_SCI5_ERI5(void){/* brk(); */} + +// SCI5 RXI5 +void INT_Excep_SCI5_RXI5(void){/* brk(); */} + +// SCI5 TXI5 +void INT_Excep_SCI5_TXI5(void){/* brk(); */} + +// SCI5 TEI5 +void INT_Excep_SCI5_TEI5(void){/* brk(); */} + +// SCI6 ERI6 +void INT_Excep_SCI6_ERI6(void){/* brk(); */} + +// SCI6 RXI6 +void INT_Excep_SCI6_RXI6(void){/* brk(); */} + +// SCI6 TXI6 +void INT_Excep_SCI6_TXI6(void){/* brk(); */} + +// SCI6 TEI6 +void INT_Excep_SCI6_TEI6(void){/* brk(); */} + +// SCI8 ERI8 +void INT_Excep_SCI8_ERI8(void){/* brk(); */} + +// SCI8 RXI8 +void INT_Excep_SCI8_RXI8(void){/* brk(); */} + +// SCI8 TXI8 +void INT_Excep_SCI8_TXI8(void){/* brk(); */} + +// SCI8 TEI8 +void INT_Excep_SCI8_TEI8(void){/* brk(); */} + +// SCI9 ERI9 +void INT_Excep_SCI9_ERI9(void){/* brk(); */} + +// SCI9 RXI9 +void INT_Excep_SCI9_RXI9(void){/* brk(); */} + +// SCI9 TXI9 +void INT_Excep_SCI9_TXI9(void){/* brk(); */} + +// SCI9 TEI9 +void INT_Excep_SCI9_TEI9(void){/* brk(); */} + +// SCI12 ERI12 +void INT_Excep_SCI12_ERI12(void){/* brk(); */} + +// SCI12 RXI12 +void INT_Excep_SCI12_RXI12(void){/* brk(); */} + +// SCI12 TXI12 +void INT_Excep_SCI12_TXI12(void){/* brk(); */} + +// SCI12 TEI12 +void INT_Excep_SCI12_TEI12(void){/* brk(); */} + +// SCI12 SCIX0 +void INT_Excep_SCI12_SCIX0(void){/* brk(); */} + +// SCI12 SCIX1 +void INT_Excep_SCI12_SCIX1(void){/* brk(); */} + +// SCI12 SCIX2 +void INT_Excep_SCI12_SCIX2(void){/* brk(); */} + +// SCI12 SCIX3 +void INT_Excep_SCI12_SCIX3(void){/* brk(); */} + +// RIIC0 EEI0 +void INT_Excep_RIIC0_EEI0(void){/* brk(); */} + +// RIIC0 RXI0 +void INT_Excep_RIIC0_RXI0(void){/* brk(); */} + +// RIIC0 TXI0 +void INT_Excep_RIIC0_TXI0(void){/* brk(); */} + +// RIIC0 TEI0 +void INT_Excep_RIIC0_TEI0(void){/* brk(); */} diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.h new file mode 100644 index 000000000..ae7bda441 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/interrupt_handlers.h @@ -0,0 +1,839 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : interrupt_handlers.h */ +/* DESCRIPTION : Interrupt Handler Declarations */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/************************************************************************/ +/* File Version : V1.00 */ +/* History : 0.50 (2014-09-18) [Hardware Manual Revision : 0.50] */ +/* : 1.00 (2015-05-18) [Hardware Manual Revision : 1.00] */ +/* Date Modified: 21/07/2015 */ +/************************************************************************/ + +#ifndef INTERRUPT_HANDLERS_H +#define INTERRUPT_HANDLERS_H + +// INT_Exception(Supervisor Instruction) + +void INT_Excep_SuperVisorInst(void) __attribute__ ((interrupt)); + +// INT_Exception(Access Instruction) + +void INT_Excep_AccessInst(void) __attribute__ ((interrupt)); + +// INT_Exception(Undefined Instruction) + +void INT_Excep_UndefinedInst(void) __attribute__ ((interrupt)); + +// INT_Exception(Floating Point) + +void INT_Excep_FloatingPoint(void) __attribute__ ((interrupt)); + +// INT_NMI + +void INT_NonMaskableInterrupt(void) __attribute__ ((interrupt)); + +// INT_Dummy + +void INT_Dummy(void) __attribute__ ((interrupt)); + +// BRK + +void INT_Excep_BRK(void) __attribute__ ((interrupt)); + +// vector 1 reserved +// vector 2 reserved +// vector 3 reserved +// vector 4 reserved +// vector 5 reserved +// vector 6 reserved +// vector 7 reserved +// vector 8 reserved +// vector 9 reserved +// vector 10 reserved +// vector 11 reserved +// vector 12 reserved +// vector 13 reserved +// vector 14 reserved +// vector 15 reserved + +// BSC BUSERR + +void INT_Excep_BSC_BUSERR(void) __attribute__ ((interrupt)); + +// vector 17 reserved +// vector 18 reserved +// vector 19 reserved +// vector 20 reserved +// vector 21 reserved +// vector 22 reserved + +// FCU FRDYI + +void INT_Excep_FCU_FRDYI(void) __attribute__ ((interrupt)); + +// vector 24 reserved +// vector 25 reserved +// vector 26 reserved + +// ICU SWINT + +void INT_Excep_ICU_SWINT(void) __attribute__ ((interrupt)); + +// CMT0 CMI0 + +void INT_Excep_CMT0_CMI0(void) __attribute__ ((interrupt)); + +// CMT1 CMI1 + +void INT_Excep_CMT1_CMI1(void) __attribute__ ((interrupt)); + +// CMT2 CMI2 + +void INT_Excep_CMT2_CMI2(void) __attribute__ ((interrupt)); + +// CMT3 CMI3 + +void INT_Excep_CMT3_CMI3(void) __attribute__ ((interrupt)); + +// CAC FERRF + +void INT_Excep_CAC_FERRF(void) __attribute__ ((interrupt)); + +// CAC MENDF + +void INT_Excep_CAC_MENDF(void) __attribute__ ((interrupt)); + +// CAC OVFF + +void INT_Excep_CAC_OVFF(void) __attribute__ ((interrupt)); + +// vector 35 reserved + +// USB0 D0FIFO0 + +void INT_Excep_USB0_D0FIFO0(void) __attribute__ ((interrupt)); + +// USB0 D1FIFO0 + +void INT_Excep_USB0_D1FIFO0(void) __attribute__ ((interrupt)); + +// USB0 USBI0 + +void INT_Excep_USB0_USBI0(void) __attribute__ ((interrupt)); + +// vector 39 reserved + +// SDHI SBFAI + +void INT_Excep_SDHI_SBFAI(void) __attribute__ ((interrupt)); + +// SDHI CDETI + +void INT_Excep_SDHI_CDETI(void) __attribute__ ((interrupt)); + +// SDHI CACI + +void INT_Excep_SDHI_CACI(void) __attribute__ ((interrupt)); + +// SDHI SDACI + +void INT_Excep_SDHI_SDACI(void) __attribute__ ((interrupt)); + +// RSPI0 SPEI0 + +void INT_Excep_RSPI0_SPEI0(void) __attribute__ ((interrupt)); + +// RSPI0 SPRI0 + +void INT_Excep_RSPI0_SPRI0(void) __attribute__ ((interrupt)); + +// RSPI0 SPTI0 + +void INT_Excep_RSPI0_SPTI0(void) __attribute__ ((interrupt)); + +// RSPI0 SPII0 + +void INT_Excep_RSPI0_SPII0(void) __attribute__ ((interrupt)); + +// vector 48 reserved +// vector 49 reserved +// vector 50 reserved +// vector 51 reserved + +// RSCAN COMFRXINT + +void INT_Excep_RSCAN_COMFRXINT(void) __attribute__ ((interrupt)); + +// RSCAN RXFINT + +void INT_Excep_RSCAN_RXFINT(void) __attribute__ ((interrupt)); + +// RSCAN TXINT + +void INT_Excep_RSCAN_TXINT(void) __attribute__ ((interrupt)); + +// RSCAN CHERRINT + +void INT_Excep_RSCAN_CHERRINT(void) __attribute__ ((interrupt)); + +// RSCAN GLERRINT + +void INT_Excep_RSCAN_GLERRINT(void) __attribute__ ((interrupt)); + +// DOC DOPCF + +void INT_Excep_DOC_DOPCF(void) __attribute__ ((interrupt)); + +// CMPB CMPB0 + +void INT_Excep_CMPB_CMPB0(void) __attribute__ ((interrupt)); + +// CMPB CMPB1 + +void INT_Excep_CMPB_CMPB1(void) __attribute__ ((interrupt)); + +// CTSU CTSUWR + +void INT_Excep_CTSU_CTSUWR(void) __attribute__ ((interrupt)); + +// CTSU CTSURD + +void INT_Excep_CTSU_CTSURD(void) __attribute__ ((interrupt)); + +// CTSU CTSUFN + +void INT_Excep_CTSU_CTSUFN(void) __attribute__ ((interrupt)); + +// RTC CUP + +void INT_Excep_RTC_CUP(void) __attribute__ ((interrupt)); + +// ICU IRQ0 + +void INT_Excep_ICU_IRQ0(void) __attribute__ ((interrupt)); + +// ICU IRQ1 + +void INT_Excep_ICU_IRQ1(void) __attribute__ ((interrupt)); + +// ICU IRQ2 + +void INT_Excep_ICU_IRQ2(void) __attribute__ ((interrupt)); + +// ICU IRQ3 + +void INT_Excep_ICU_IRQ3(void) __attribute__ ((interrupt)); + +// ICU IRQ4 + +void INT_Excep_ICU_IRQ4(void) __attribute__ ((interrupt)); + +// ICU IRQ5 + +void INT_Excep_ICU_IRQ5(void) __attribute__ ((interrupt)); + +// ICU IRQ6 + +void INT_Excep_ICU_IRQ6(void) __attribute__ ((interrupt)); + +// ICU IRQ7 + +void INT_Excep_ICU_IRQ7(void) __attribute__ ((interrupt)); + +// vector 72 reserved +// vector 73 reserved +// vector 74 reserved +// vector 75 reserved +// vector 76 reserved +// vector 77 reserved +// vector 78 reserved +// vector 79 reserved + +// ELC ELSR8I + +void INT_Excep_ELC_ELSR8I(void) __attribute__ ((interrupt)); + +// vector 81 reserved +// vector 82 reserved +// vector 83 reserved +// vector 84 reserved +// vector 85 reserved +// vector 86 reserved +// vector 87 reserved + +// LVD LVD1 + +void INT_Excep_LVD_LVD1(void) __attribute__ ((interrupt)); + +// LVD LVD2 + +void INT_Excep_LVD_LVD2(void) __attribute__ ((interrupt)); + +// CMPA CMPA1 + +//void INT_Excep_CMPA_CMPA1(void) __attribute__ ((interrupt)); + +// CMPA CMPA2 + +//void INT_Excep_CMPA_CMPA2(void) __attribute__ ((interrupt)); + +// USB0 USBR0 + +void INT_Excep_USB0_USBR0(void) __attribute__ ((interrupt)); + +// VBATT VBTLVDI + +void INT_Excep_VBATT_VBTLVDI(void) __attribute__ ((interrupt)); + +// RTC ALM + +void INT_Excep_RTC_ALM(void) __attribute__ ((interrupt)); + +// RTC PRD + +void INT_Excep_RTC_PRD(void) __attribute__ ((interrupt)); + +// vector 94 reserved +// vector 95 reserved +// vector 96 reserved +// vector 97 reserved +// vector 98 reserved +// vector 99 reserved +// vector 100 reserved +// vector 101 reserved + +// S12AD S12ADI0 + +void INT_Excep_S12AD_S12ADI0(void) __attribute__ ((interrupt)); + +// S12AD GBADI + +void INT_Excep_S12AD_GBADI(void) __attribute__ ((interrupt)); + +// CMPB1 CMPB2 + +void INT_Excep_CMPB1_CMPB2(void) __attribute__ ((interrupt)); + +// CMPB1 CMPB3 + +void INT_Excep_CMPB1_CMPB3(void) __attribute__ ((interrupt)); + +// ELC ELSR18I + +void INT_Excep_ELC_ELSR18I(void) __attribute__ ((interrupt)); + +// ELC ELSR19I + +void INT_Excep_ELC_ELSR19I(void) __attribute__ ((interrupt)); + +// SSI0 SSIF0 + +void INT_Excep_SSI0_SSIF0(void) __attribute__ ((interrupt)); + +// SSI0 SSIRXI0 + +void INT_Excep_SSI0_SSIRXI0(void) __attribute__ ((interrupt)); + +// SSI0 SSITXI0 + +void INT_Excep_SSI0_SSITXI0(void) __attribute__ ((interrupt)); + +// SECURITY RD + +void INT_Excep_SECURITY_RD(void) __attribute__ ((interrupt)); + +// SECURITY WR + +void INT_Excep_SECURITY_WR(void) __attribute__ ((interrupt)); + +// SECURITY ERR + +void INT_Excep_SECURITY_ERR(void) __attribute__ ((interrupt)); + +// MTU0 TGIA0 + +void INT_Excep_MTU0_TGIA0(void) __attribute__ ((interrupt)); + +// MTU0 TGIB0 + +void INT_Excep_MTU0_TGIB0(void) __attribute__ ((interrupt)); + +// MTU0 TGIC0 + +void INT_Excep_MTU0_TGIC0(void) __attribute__ ((interrupt)); + +// MTU0 TGID0 + +void INT_Excep_MTU0_TGID0(void) __attribute__ ((interrupt)); + +// MTU0 TCIV0 + +void INT_Excep_MTU0_TCIV0(void) __attribute__ ((interrupt)); + +// MTU0 TGIE0 + +void INT_Excep_MTU0_TGIE0(void) __attribute__ ((interrupt)); + +// MTU0 TGIF0 + +void INT_Excep_MTU0_TGIF0(void) __attribute__ ((interrupt)); + +// MTU1 TGIA1 + +void INT_Excep_MTU1_TGIA1(void) __attribute__ ((interrupt)); + +// MTU1 TGIB1 + +void INT_Excep_MTU1_TGIB1(void) __attribute__ ((interrupt)); + +// MTU1 TCIV1 + +void INT_Excep_MTU1_TCIV1(void) __attribute__ ((interrupt)); + +// MTU1 TCIU1 + +void INT_Excep_MTU1_TCIU1(void) __attribute__ ((interrupt)); + +// MTU2 TGIA2 + +void INT_Excep_MTU2_TGIA2(void) __attribute__ ((interrupt)); + +// MTU2 TGIB2 + +void INT_Excep_MTU2_TGIB2(void) __attribute__ ((interrupt)); + +// MTU2 TCIV2 + +void INT_Excep_MTU2_TCIV2(void) __attribute__ ((interrupt)); + +// MTU2 TCIU2 + +void INT_Excep_MTU2_TCIU2(void) __attribute__ ((interrupt)); + +// MTU3 TGIA3 + +void INT_Excep_MTU3_TGIA3(void) __attribute__ ((interrupt)); + +// MTU3 TGIB3 + +void INT_Excep_MTU3_TGIB3(void) __attribute__ ((interrupt)); + +// MTU3 TGIC3 + +void INT_Excep_MTU3_TGIC3(void) __attribute__ ((interrupt)); + +// MTU3 TGID3 + +void INT_Excep_MTU3_TGID3(void) __attribute__ ((interrupt)); + +// MTU3 TCIV3 + +void INT_Excep_MTU3_TCIV3(void) __attribute__ ((interrupt)); + +// MTU4 TGIA4 + +void INT_Excep_MTU4_TGIA4(void) __attribute__ ((interrupt)); + +// MTU4 TGIB4 + +void INT_Excep_MTU4_TGIB4(void) __attribute__ ((interrupt)); + +// MTU4 TGIC4 + +void INT_Excep_MTU4_TGIC4(void) __attribute__ ((interrupt)); + +// MTU4 TGID4 + +void INT_Excep_MTU4_TGID4(void) __attribute__ ((interrupt)); + +// MTU4 TCIV4 + +void INT_Excep_MTU4_TCIV4(void) __attribute__ ((interrupt)); + +// MTU5 TGIU5 + +void INT_Excep_MTU5_TGIU5(void) __attribute__ ((interrupt)); + +// MTU5 TGIV5 + +void INT_Excep_MTU5_TGIV5(void) __attribute__ ((interrupt)); + +// MTU5 TGIW5 + +void INT_Excep_MTU5_TGIW5(void) __attribute__ ((interrupt)); + +// TPU0 TGI0A + +void INT_Excep_TPU0_TGI0A(void) __attribute__ ((interrupt)); + +// TPU0 TGI0B + +void INT_Excep_TPU0_TGI0B(void) __attribute__ ((interrupt)); + +// TPU0 TGI0C + +void INT_Excep_TPU0_TGI0C(void) __attribute__ ((interrupt)); + +// TPU0 TGI0D + +void INT_Excep_TPU0_TGI0D(void) __attribute__ ((interrupt)); + +// TPU0 TCI0V + +void INT_Excep_TPU0_TCI0V(void) __attribute__ ((interrupt)); + +// TPU1 TGI1A + +void INT_Excep_TPU1_TGI1A(void) __attribute__ ((interrupt)); + +// TPU1 TGI1B + +void INT_Excep_TPU1_TGI1B(void) __attribute__ ((interrupt)); + +// TPU1 TCI1V + +void INT_Excep_TPU1_TCI1V(void) __attribute__ ((interrupt)); + +// TPU1 TCI1U + +void INT_Excep_TPU1_TCI1U(void) __attribute__ ((interrupt)); + +// TPU2 TGI2A + +void INT_Excep_TPU2_TGI2A(void) __attribute__ ((interrupt)); + +// TPU2 TGI2B + +void INT_Excep_TPU2_TGI2B(void) __attribute__ ((interrupt)); + +// TPU2 TCI2V + +void INT_Excep_TPU2_TCI2V(void) __attribute__ ((interrupt)); + +// TPU2 TCI2U + +void INT_Excep_TPU2_TCI2U(void) __attribute__ ((interrupt)); + +// TPU3 TGI3A + +void INT_Excep_TPU3_TGI3A(void) __attribute__ ((interrupt)); + +// TPU3 TGI3B + +void INT_Excep_TPU3_TGI3B(void) __attribute__ ((interrupt)); + +// TPU3 TGI3C + +void INT_Excep_TPU3_TGI3C(void) __attribute__ ((interrupt)); + +// TPU3 TGI3D + +void INT_Excep_TPU3_TGI3D(void) __attribute__ ((interrupt)); + +// TPU3 TCI3V + +void INT_Excep_TPU3_TCI3V(void) __attribute__ ((interrupt)); + +// TPU4 TGI4A + +void INT_Excep_TPU4_TGI4A(void) __attribute__ ((interrupt)); + +// TPU4 TGI4B + +void INT_Excep_TPU4_TGI4B(void) __attribute__ ((interrupt)); + +// TPU4 TCI4V + +void INT_Excep_TPU4_TCI4V(void) __attribute__ ((interrupt)); + +// TPU4 TCI4U + +void INT_Excep_TPU4_TCI4U(void) __attribute__ ((interrupt)); + +// TPU5 TGI5A + +void INT_Excep_TPU5_TGI5A(void) __attribute__ ((interrupt)); + +// TPU5 TGI5B + +void INT_Excep_TPU5_TGI5B(void) __attribute__ ((interrupt)); + +// TPU5 TCI5V + +void INT_Excep_TPU5_TCI5V(void) __attribute__ ((interrupt)); + +// TPU5 TCI5U + +void INT_Excep_TPU5_TCI5U(void) __attribute__ ((interrupt)); + +// vector 168 reserved +// vector 169 reserved + +// POE OEI1 + +void INT_Excep_POE_OEI1(void) __attribute__ ((interrupt)); + +// POE OEI2 + +void INT_Excep_POE_OEI2(void) __attribute__ ((interrupt)); + +// vector 172 reserved +// vector 173 reserved + +// TMR0 CMIA0 + +void INT_Excep_TMR0_CMIA0(void) __attribute__ ((interrupt)); + +// TMR0 CMIB0 + +void INT_Excep_TMR0_CMIB0(void) __attribute__ ((interrupt)); + +// TMR0 OVI0 + +void INT_Excep_TMR0_OVI0(void) __attribute__ ((interrupt)); + +// TMR1 CMIA1 + +void INT_Excep_TMR1_CMIA1(void) __attribute__ ((interrupt)); + +// TMR1 CMIB1 + +void INT_Excep_TMR1_CMIB1(void) __attribute__ ((interrupt)); + +// TMR1 OVI1 + +void INT_Excep_TMR1_OVI1(void) __attribute__ ((interrupt)); + +// TMR2 CMIA2 + +void INT_Excep_TMR2_CMIA2(void) __attribute__ ((interrupt)); + +// TMR2 CMIB2 + +void INT_Excep_TMR2_CMIB2(void) __attribute__ ((interrupt)); + +// TMR2 OVI2 + +void INT_Excep_TMR2_OVI2(void) __attribute__ ((interrupt)); + +// TMR3 CMIA3 + +void INT_Excep_TMR3_CMIA3(void) __attribute__ ((interrupt)); + +// TMR3 CMIB3 + +void INT_Excep_TMR3_CMIB3(void) __attribute__ ((interrupt)); + +// TMR3 OVI3 + +void INT_Excep_TMR3_OVI3(void) __attribute__ ((interrupt)); + +// vector 186 reserved +// vector 187 reserved +// vector 188 reserved +// vector 189 reserved +// vector 190 reserved +// vector 191 reserved +// vector 192 reserved +// vector 193 reserved +// vector 194 reserved +// vector 195 reserved +// vector 196 reserved +// vector 197 reserved + +// DMAC DMAC0I + +void INT_Excep_DMAC_DMAC0I(void) __attribute__ ((interrupt)); + +// DMAC DMAC1I + +void INT_Excep_DMAC_DMAC1I(void) __attribute__ ((interrupt)); + +// DMAC DMAC2I + +void INT_Excep_DMAC_DMAC2I(void) __attribute__ ((interrupt)); + +// DMAC DMAC3I + +void INT_Excep_DMAC_DMAC3I(void) __attribute__ ((interrupt)); + +// vector 202 reserved +// vector 203 reserved +// vector 204 reserved +// vector 205 reserved +// vector 206 reserved +// vector 207 reserved +// vector 208 reserved +// vector 209 reserved +// vector 210 reserved +// vector 211 reserved +// vector 212 reserved +// vector 213 reserved + +// SCI0 ERI0 + +void INT_Excep_SCI0_ERI0(void) __attribute__ ((interrupt)); + +// SCI0 RXI0 + +void INT_Excep_SCI0_RXI0(void) __attribute__ ((interrupt)); + +// SCI0 TXI0 + +void INT_Excep_SCI0_TXI0(void) __attribute__ ((interrupt)); + +// SCI0 TEI0 + +void INT_Excep_SCI0_TEI0(void) __attribute__ ((interrupt)); + +// SCI1 ERI1 + +void INT_Excep_SCI1_ERI1(void) __attribute__ ((interrupt)); + +// SCI1 RXI1 + +void INT_Excep_SCI1_RXI1(void) __attribute__ ((interrupt)); + +// SCI1 TXI1 + +void INT_Excep_SCI1_TXI1(void) __attribute__ ((interrupt)); + +// SCI1 TEI1 + +void INT_Excep_SCI1_TEI1(void) __attribute__ ((interrupt)); + +// SCI5 ERI5 + +void INT_Excep_SCI5_ERI5(void) __attribute__ ((interrupt)); + +// SCI5 RXI5 + +void INT_Excep_SCI5_RXI5(void) __attribute__ ((interrupt)); + +// SCI5 TXI5 + +void INT_Excep_SCI5_TXI5(void) __attribute__ ((interrupt)); + +// SCI5 TEI5 + +void INT_Excep_SCI5_TEI5(void) __attribute__ ((interrupt)); + +// SCI6 ERI6 + +void INT_Excep_SCI6_ERI6(void) __attribute__ ((interrupt)); + +// SCI6 RXI6 + +void INT_Excep_SCI6_RXI6(void) __attribute__ ((interrupt)); + +// SCI6 TXI6 + +void INT_Excep_SCI6_TXI6(void) __attribute__ ((interrupt)); + +// SCI6 TEI6 + +void INT_Excep_SCI6_TEI6(void) __attribute__ ((interrupt)); + +// SCI8 ERI8 + +void INT_Excep_SCI8_ERI8(void) __attribute__ ((interrupt)); + +// SCI8 RXI8 + +void INT_Excep_SCI8_RXI8(void) __attribute__ ((interrupt)); + +// SCI8 TXI8 + +void INT_Excep_SCI8_TXI8(void) __attribute__ ((interrupt)); + +// SCI8 TEI8 + +void INT_Excep_SCI8_TEI8(void) __attribute__ ((interrupt)); + +// SCI9 ERI9 + +void INT_Excep_SCI9_ERI9(void) __attribute__ ((interrupt)); + +// SCI9 RXI9 + +void INT_Excep_SCI9_RXI9(void) __attribute__ ((interrupt)); + +// SCI9 TXI9 + +void INT_Excep_SCI9_TXI9(void) __attribute__ ((interrupt)); + +// SCI9 TEI9 + +void INT_Excep_SCI9_TEI9(void) __attribute__ ((interrupt)); + +// SCI12 ERI12 + +void INT_Excep_SCI12_ERI12(void) __attribute__ ((interrupt)); + +// SCI12 RXI12 + +void INT_Excep_SCI12_RXI12(void) __attribute__ ((interrupt)); + +// SCI12 TXI12 + +void INT_Excep_SCI12_TXI12(void) __attribute__ ((interrupt)); + +// SCI12 TEI12 + +void INT_Excep_SCI12_TEI12(void) __attribute__ ((interrupt)); + +// SCI12 SCIX0 + +void INT_Excep_SCI12_SCIX0(void) __attribute__ ((interrupt)); + +// SCI12 SCIX1 + +void INT_Excep_SCI12_SCIX1(void) __attribute__ ((interrupt)); + +// SCI12 SCIX2 + +void INT_Excep_SCI12_SCIX2(void) __attribute__ ((interrupt)); + +// SCI12 SCIX3 + +void INT_Excep_SCI12_SCIX3(void) __attribute__ ((interrupt)); + +// RIIC0 EEI0 + +void INT_Excep_RIIC0_EEI0(void) __attribute__ ((interrupt)); + +// RIIC0 RXI0 + +void INT_Excep_RIIC0_RXI0(void) __attribute__ ((interrupt)); + +// RIIC0 TXI0 + +void INT_Excep_RIIC0_TXI0(void) __attribute__ ((interrupt)); + +// RIIC0 TEI0 + +void INT_Excep_RIIC0_TEI0(void) __attribute__ ((interrupt)); + +// vector 250 reserved +// vector 251 reserved +// vector 252 reserved +// vector 253 reserved +// vector 254 reserved +// vector 255 reserved + +//;<> +//;Power On Reset PC +extern void PowerON_Reset(void) __attribute__ ((interrupt)); +//;<> +#endif diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/typedefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/typedefine.h new file mode 100644 index 000000000..5aa146beb --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/typedefine.h @@ -0,0 +1,28 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : typedefine.h */ +/* DESCRIPTION : Aliases of Integer Type */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + +/************************************************************************/ +/* File Version: V1.00 */ +/* Date Generated: 08/07/2013 */ +/************************************************************************/ + +typedef signed char _SBYTE; +typedef unsigned char _UBYTE; +typedef signed short _SWORD; +typedef unsigned short _UWORD; +typedef signed int _SINT; +typedef unsigned int _UINT; +typedef signed long _SDWORD; +typedef unsigned long _UDWORD; +typedef signed long long _SQWORD; +typedef unsigned long long _UQWORD; diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/vector_table.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/vector_table.c new file mode 100644 index 000000000..01520e4ba --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/Renesas_Code/vector_table.c @@ -0,0 +1,632 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : vector_table.c */ +/* DESCRIPTION : Vector Table */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/************************************************************************/ +/* File Version : V1.00 */ +/* History: 0.50 (2014-09-05) [Hardware Manual Revision : 0.50] */ +/* 0.51 (2014-10-01) [Hardware Manual Revision : 0.50] */ +/* Date Modified: 03/07/2015 */ +/************************************************************************/ + + +#include "interrupt_handlers.h" + +typedef void (*fp) (void); +extern void PowerON_Reset (void); +extern void stack (void); +extern void vTickISR( void ); +extern void vSoftwareInterruptISR( void ); +extern void vIntQTimerISR0( void ); +extern void vIntQTimerISR1( void ); + + +#define EXVECT_SECT __attribute__ ((section (".exvectors"))) + +const void *ExceptVectors[] EXVECT_SECT = { +//;0xffffff80 MDES Endian Select Register +#ifdef __RX_LITTLE_ENDIAN__ +(fp)0xffffffff, +#endif +#ifdef __RX_BIG_ENDIAN__ +(fp)0xfffffff8, +#endif +//;0xffffff84 Reserved + (fp)0, +//;0xffffff88 OFS1 Option byte setting + (fp)0xFFFFFFFF, +//;0xffffff8C OFS0 + (fp)0xFFFFFFFF, +//;0xffffff90 Reserved + (fp)0, +//;0xffffff94 Reserved + (fp)0, +//;0xffffff98 Reserved + (fp)0, +//;0xffffff9C Reserved + (fp)0, +//;0xffffffA0 Reserved + (fp)0xFFFFFFFF, +//;0xffffffA4 Reserved + (fp)0xFFFFFFFF, +//;0xffffffA8 Reserved + (fp)0xFFFFFFFF, +//;0xffffffAC Reserved + (fp)0xFFFFFFFF, +//;0xffffffB0 Reserved + (fp)0, +//;0xffffffB4 Reserved + (fp)0, +//;0xffffffB8 Reserved + (fp)0, +//;0xffffffBC Reserved + (fp)0, +//;0xffffffC0 Reserved + (fp)0, +//;0xffffffC4 Reserved + (fp)0, +//;0xffffffC8 Reserved + (fp)0, +//;0xffffffCC Reserved + (fp)0, +//;0xffffffd0 Exception(Supervisor Instruction) + INT_Excep_SuperVisorInst, +//;0xffffffd4 Exception(Access Instruction) + INT_Excep_AccessInst, +//;0xffffffd8 Reserved + (fp)0, +//;0xffffffdc Exception(Undefined Instruction) + INT_Excep_UndefinedInst, +//;0xffffffe0 Reserved + (fp)0, +//;0xffffffe4 Exception(Floating Point) + INT_Excep_FloatingPoint, +//;0xffffffe8 Reserved + (fp)0, +//;0xffffffec Reserved + (fp)0, +//;0xfffffff0 Reserved + (fp)0, +//;0xfffffff4 Reserved + (fp)0, +//;0xfffffff8 NMI + INT_NonMaskableInterrupt, +}; + +#define FVECT_SECT __attribute__ ((section (".fvectors"))) + +const void *HardwareVectors[] FVECT_SECT = { +//;0xfffffffc RESET +//;<> +//;Power On Reset PC + /*(void*)*/ PowerON_Reset +//;<> +}; + +#define RVECT_SECT __attribute__ ((section (".rvectors"))) + +const fp RelocatableVectors[] RVECT_SECT = { +//;0x0000 Reserved + (fp)0, +//;0x0004 Reserved + (fp)0, +//;0x0008 Reserved + (fp)0, +//;0x000C Reserved + (fp)0, +//;0x0010 Reserved + (fp)0, +//;0x0014 Reserved + (fp)0, +//;0x0018 Reserved + (fp)0, +//;0x001C Reserved + (fp)0, +//;0x0020 Reserved + (fp)0, +//;0x0024 Reserved + (fp)0, +//;0x0028 Reserved + (fp)0, +//;0x002C Reserved + (fp)0, +//;0x0030 Reserved + (fp)0, +//;0x0034 Reserved + (fp)0, +//;0x0038 Reserved + (fp)0, +//;0x003C Reserved + (fp)0, +//;0x0040 BSC_BUSERR + (fp)INT_Excep_BSC_BUSERR, +//;0x0044 Reserved + (fp)0, +//;0x0048 Reserved + (fp)0, +//;0x004C Reserved + (fp)0, +//;0x0050 Reserved + (fp)0, +//;0x0054 Reserved + (fp)0, +//;0x0058 Reserved + (fp)0, +//;0x005C FCU_FRDYI + (fp)INT_Excep_FCU_FRDYI, +//;0x0060 Reserved + (fp)0, +//;0x0064 Reserved + (fp)0, +//;0x0068 Reserved + (fp)0, +//;0x006C ICU_SWINT + (fp)vSoftwareInterruptISR, +//;0x0070 CMT0_CMI0 + (fp)vTickISR, +//;0x0074 CMT1_CMI1 + (fp)INT_Excep_CMT1_CMI1, +//;0x0078 CMT2_CMI2 + (fp)INT_Excep_CMT2_CMI2, +//;0x007C CMT3_CMI3 + (fp)INT_Excep_CMT3_CMI3, +//;0x0080 CAC_FERRF + (fp)INT_Excep_CAC_FERRF, +//;0x0084 CAC_MENDF + (fp)INT_Excep_CAC_MENDF, +//;0x0088 CAC_OVFF + (fp)INT_Excep_CAC_OVFF, +//;0x008C Reserved + (fp)0, +//;0x0090 USB0_D0FIFO0 + (fp)INT_Excep_USB0_D0FIFO0, +//;0x0094 USB0_D1FIFO0 + (fp)INT_Excep_USB0_D1FIFO0, +//;0x0098 USB0_USBI0 + (fp)INT_Excep_USB0_USBI0, +//;0x009C Reserved + (fp)0, +//;0x00A0 SDHI_SBFAI + (fp)INT_Excep_SDHI_SBFAI, +//;0x00A4 SDHI_CDETI + (fp)INT_Excep_SDHI_CDETI, +//;0x00A8 SDHI_CACI + (fp)INT_Excep_SDHI_CACI, +//;0x00AC SDHI_SDACI + (fp)INT_Excep_SDHI_SDACI, +//;0x00B0 RSPI0_SPEI0 + (fp)INT_Excep_RSPI0_SPEI0, +//;0x00B4 RSPI0_SPRI0 + (fp)INT_Excep_RSPI0_SPRI0, +//;0x00B8 RSPI0_SPTI0 + (fp)INT_Excep_RSPI0_SPTI0, +//;0x00BC RSPI0_SPII0 + (fp)INT_Excep_RSPI0_SPII0, +//;0x00C0 Reserved + (fp)0, +//;0x00C4 Reserved + (fp)0, +//;0x00C8 Reserved + (fp)0, +//;0x00CC Reserved + (fp)0, +//;0x00D0 CAN_COMFRXINT + (fp)INT_Excep_RSCAN_COMFRXINT, +//;0x00D4 CAN_RXFINT + (fp)INT_Excep_RSCAN_RXFINT, +//;0x00D8 CAN_TXINT + (fp)INT_Excep_RSCAN_TXINT, +//;0x00DC CAN_CHERRINT + (fp)INT_Excep_RSCAN_CHERRINT, +//;0x00E0 CAN_GLERRINT + (fp)INT_Excep_RSCAN_GLERRINT, +//;0x00E4 DOC_DOPCF + (fp)INT_Excep_DOC_DOPCF, +//;0x00E8 CMPB_CMPB0 + (fp)INT_Excep_CMPB_CMPB0, +//;0x00EC CMPB_CMPB1 + (fp)INT_Excep_CMPB_CMPB1, +//;0x00F0 CTSU_CTSUWR + (fp)INT_Excep_CTSU_CTSUWR, +//;0x00F4 CTSU_CTSURD + (fp)INT_Excep_CTSU_CTSURD, +//;0x00F8 CTSU_CTSUFN + (fp)INT_Excep_CTSU_CTSUFN, +//;0x00FC RTC_CUP + (fp)INT_Excep_RTC_CUP, +//;0x0100 ICU_IRQ0 + (fp)INT_Excep_ICU_IRQ0, +//;0x0104 ICU_IRQ1 + (fp)INT_Excep_ICU_IRQ1, +//;0x0108 ICU_IRQ2 + (fp)INT_Excep_ICU_IRQ2, +//;0x010C ICU_IRQ3 + (fp)INT_Excep_ICU_IRQ3, +//;0x0110 ICU_IRQ4 + (fp)INT_Excep_ICU_IRQ4, +//;0x0114 ICU_IRQ5 + (fp)INT_Excep_ICU_IRQ5, +//;0x0118 ICU_IRQ6 + (fp)INT_Excep_ICU_IRQ6, +//;0x011C ICU_IRQ7 + (fp)INT_Excep_ICU_IRQ7, +//;0x0120 Reserved + (fp)0, +//;0x0124 Reserved + (fp)0, +//;0x0128 Reserved + (fp)0, +//;0x012C Reserved + (fp)0, +//;0x0130 Reserved + (fp)0, +//;0x0134 Reserved + (fp)0, +//;0x0138 Reserved + (fp)0, +//;0x013C Reserved + (fp)0, +//;0x0140 ELC_ELSR8I + (fp)INT_Excep_ELC_ELSR8I, +//;0x0144 Reserved + (fp)0, +//;0x0148 Reserved + (fp)0, +//;0x014C Reserved + (fp)0, +//;0x0150 Reserved + (fp)0, +//;0x0154 Reserved + (fp)0, +//;0x0158 Reserved + (fp)0, +//;0x015C Reserved + (fp)0, +//;0x0160 LVD/CMPA_LVD1/CMPA1 + (fp)INT_Excep_LVD_LVD1, +//;0x0164 LVD/CMPA_LVD2/CMPA2 + (fp)INT_Excep_LVD_LVD2, +//;0x0168 USB0_USBR0 + (fp)INT_Excep_USB0_USBR0, +//;0x016C VBATT_VBTLVDI + (fp)INT_Excep_VBATT_VBTLVDI, +//;0x0170 RTC_ALM + (fp)INT_Excep_RTC_ALM, +//;0x0174 RTC_PRD + (fp)INT_Excep_RTC_PRD, +//;0x0178 Reserved + (fp)0, +//;0x017C Reserved + (fp)0, +//;0x0180 Reserved + (fp)0, +//;0x0184 Reserved + (fp)0, +//;0x0188 Reserved + (fp)0, +//;0x018C Reserved + (fp)0, +//;0x0190 Reserved + (fp)0, +//;0x0194 Reserved + (fp)0, +//;0x0198 S12AD_S12ADI0 + (fp)INT_Excep_S12AD_S12ADI0, +//;0x019C S12AD_GBADI + (fp)INT_Excep_S12AD_GBADI, +//;0x01A0 CMPB1_CMPB2 + (fp)INT_Excep_CMPB1_CMPB2, +//;0x01A4 CMPB1_CMPB3 + (fp)INT_Excep_CMPB1_CMPB3, +//;0x01A8 ELC_ELSR18I + (fp)INT_Excep_ELC_ELSR18I, +//;0x01AC ELC_ELSR19I + (fp)INT_Excep_ELC_ELSR19I, +//;0x01B0 SSI0_SSIF0 + (fp)INT_Excep_SSI0_SSIF0, +//;0x01B4 SSI0_SSIRXI0 + (fp)INT_Excep_SSI0_SSIRXI0, +//;0x01B8 SSI0_SSITXI0 + (fp)INT_Excep_SSI0_SSITXI0, +//;0x01BC Secure_RD + (fp)INT_Excep_SECURITY_RD, +//;0x01C0 Secure_WR + (fp)INT_Excep_SECURITY_WR, +//;0x01C4 Secure_Error + (fp)INT_Excep_SECURITY_ERR, +//;0x01C8 MTU0_TGIA0 + (fp)INT_Excep_MTU0_TGIA0, +//;0x01CC MTU0_TGIB0 + (fp)INT_Excep_MTU0_TGIB0, +//;0x01D0 MTU0_TGIC0 + (fp)INT_Excep_MTU0_TGIC0, +//;0x01D4 MTU0_TGID0 + (fp)INT_Excep_MTU0_TGID0, +//;0x01D8 MTU0_TCIV0 + (fp)INT_Excep_MTU0_TCIV0, +//;0x01DC MTU0_TGIE0 + (fp)INT_Excep_MTU0_TGIE0, +//;0x01E0 MTU0_TGIF0 + (fp)INT_Excep_MTU0_TGIF0, +//;0x01E4 MTU1_TGIA1 + (fp)INT_Excep_MTU1_TGIA1, +//;0x01E8 MTU1_TGIB1 + (fp)INT_Excep_MTU1_TGIB1, +//;0x01EC MTU1_TCIV1 + (fp)INT_Excep_MTU1_TCIV1, +//;0x01F0 MTU1_TCIU1 + (fp)INT_Excep_MTU1_TCIU1, +//;0x01F4 MTU2_TGIA2 + (fp)INT_Excep_MTU2_TGIA2, +//;0x01F8 MTU2_TGIB2 + (fp)INT_Excep_MTU2_TGIB2, +//;0x01FC MTU2_TCIV2 + (fp)INT_Excep_MTU2_TCIV2, +//;0x0200 MTU2_TCIU2 + (fp)INT_Excep_MTU2_TCIU2, +//;0x0204 MTU3_TGIA3 + (fp)INT_Excep_MTU3_TGIA3, +//;0x0208 MTU3_TGIB3 + (fp)INT_Excep_MTU3_TGIB3, +//;0x020C MTU3_TGIC3 + (fp)INT_Excep_MTU3_TGIC3, +//;0x0210 MTU3_TGID3 + (fp)INT_Excep_MTU3_TGID3, +//;0x0214 MTU3_TCIV3 + (fp)INT_Excep_MTU3_TCIV3, +//;0x0218 MTU4_TGIA4 + (fp)INT_Excep_MTU4_TGIA4, +//;0x021C MTU4_TGIB4 + (fp)INT_Excep_MTU4_TGIB4, +//;0x0220 MTU4_TGIC4 + (fp)INT_Excep_MTU4_TGIC4, +//;0x0224 MTU4_TGID4 + (fp)INT_Excep_MTU4_TGID4, +//;0x0228 MTU4_TCIV4 + (fp)INT_Excep_MTU4_TCIV4, +//;0x022C MTU5_TGIU5 + (fp)INT_Excep_MTU5_TGIU5, +//;0x0230 MTU5_TGIV5 + (fp)INT_Excep_MTU5_TGIV5, +//;0x0234 MTU5_TGIW5 + (fp)INT_Excep_MTU5_TGIW5, +//;0x0238 TPU0_TGI0A + (fp)INT_Excep_TPU0_TGI0A, +//;0x023C TPU0_TGI0B + (fp)INT_Excep_TPU0_TGI0B, +//;0x0240 TPU0_TGI0C + (fp)INT_Excep_TPU0_TGI0C, +//;0x0244 TPU0_TGI0D + (fp)INT_Excep_TPU0_TGI0D, +//;0x0248 TPU0_TCI0V + (fp)INT_Excep_TPU0_TCI0V, +//;0x024C TPU1_TGI1A + (fp)INT_Excep_TPU1_TGI1A, +//;0x0250 TPU1_TGI1B + (fp)INT_Excep_TPU1_TGI1B, +//;0x0254 TPU1_TCI1V + (fp)INT_Excep_TPU1_TCI1V, +//;0x0258 TPU1_TCI1U + (fp)INT_Excep_TPU1_TCI1U, +//;0x025C TPU2_TGI2A + (fp)INT_Excep_TPU2_TGI2A, +//;0x0260 TPU2_TGI2B + (fp)INT_Excep_TPU2_TGI2B, +//;0x0264 TPU2_TCI2V + (fp)INT_Excep_TPU2_TCI2V, +//;0x0268 TPU2_TCI2U + (fp)INT_Excep_TPU2_TCI2U, +//;0x026C TPU3_TGI3A + (fp)INT_Excep_TPU3_TGI3A, +//;0x0270 TPU3_TGI3B + (fp)INT_Excep_TPU3_TGI3B, +//;0x0274 TPU3_TGI3C + (fp)INT_Excep_TPU3_TGI3C, +//;0x0278 TPU3_TGI3D + (fp)INT_Excep_TPU3_TGI3D, +//;0x027C TPU3_TCI3V + (fp)INT_Excep_TPU3_TCI3V, +//;0x0280 TPU4_TGI4A + (fp)INT_Excep_TPU4_TGI4A, +//;0x0284 TPU4_TGI4B + (fp)INT_Excep_TPU4_TGI4B, +//;0x0288 TPU4_TCI4V + (fp)INT_Excep_TPU4_TCI4V, +//;0x028C TPU4_TCI4U + (fp)INT_Excep_TPU4_TCI4U, +//;0x0290 TPU5_TGI5A + (fp)INT_Excep_TPU5_TGI5A, +//;0x0294 TPU5_TGI5B + (fp)INT_Excep_TPU5_TGI5B, +//;0x0298 TPU5_TCI5V + (fp)INT_Excep_TPU5_TCI5V, +//;0x029C TPU5_TCI5U + (fp)INT_Excep_TPU5_TCI5U, +//;0x02A0 Reserved + (fp)0, +//;0x02A4 Reserved + (fp)0, +//;0x02A8 POE_OEI1 + (fp)INT_Excep_POE_OEI1, +//;0x02AC POE_OEI2 + (fp)INT_Excep_POE_OEI2, +//;0x02B0 Reserved + (fp)0, +//;0x02B4 Reserved + (fp)0, +//;0x02B8 TMR0_CMIA0 + (fp)vIntQTimerISR0, +//;0x02BC TMR0_CMIB0 + (fp)INT_Excep_TMR0_CMIB0, +//;0x02C0 TMR0_OVI0 + (fp)INT_Excep_TMR0_OVI0, +//;0x02C4 TMR1_CMIA1 + (fp)INT_Excep_TMR1_CMIA1, +//;0x02C8 TMR1_CMIB1 + (fp)INT_Excep_TMR1_CMIB1, +//;0x02CC TMR1_OVI1 + (fp)INT_Excep_TMR1_OVI1, +//;0x02D0 TMR2_CMIA2 + (fp)vIntQTimerISR1, +//;0x02D4 TMR2_CMIB2 + (fp)INT_Excep_TMR2_CMIB2, +//;0x02D8 TMR2_OVI2 + (fp)INT_Excep_TMR2_OVI2, +//;0x02DC TMR3_CMIA3 + (fp)INT_Excep_TMR3_CMIA3, +//;0x02E0 TMR3_CMIB3 + (fp)INT_Excep_TMR3_CMIB3, +//;0x02E4 TMR3_OVI3 + (fp)INT_Excep_TMR3_OVI3, +//;0x02E8 Reserved + (fp)0, +//;0x02EC Reserved + (fp)0, +//;0x02F0 Reserved + (fp)0, +//;0x02F4 Reserved + (fp)0, +//;0x02F8 Reserved + (fp)0, +//;0x02FC Reserved + (fp)0, +//;0x0300 Reserved + (fp)0, +//;0x0304 Reserved + (fp)0, +//;0x0308 Reserved + (fp)0, +//;0x030C Reserved + (fp)0, +//;0x0310 Reserved + (fp)0, +//;0x0314 Reserved + (fp)0, +//;0x0318 DMAC_DMAC0I + (fp)INT_Excep_DMAC_DMAC0I, +//;0x031C DMAC_DMAC1I + (fp)INT_Excep_DMAC_DMAC1I, +//;0x0320 DMAC_DMAC2I + (fp)INT_Excep_DMAC_DMAC2I, +//;0x0324 DMAC_DMAC3I + (fp)INT_Excep_DMAC_DMAC3I, +//;0x0328 Reserved + (fp)0, +//;0x032C Reserved + (fp)0, +//;0x0330 Reserved + (fp)0, +//;0x0334 Reserved + (fp)0, +//;0x0338 Reserved + (fp)0, +//;0x033C Reserved + (fp)0, +//;0x0340 Reserved + (fp)0, +//;0x0344 Reserved + (fp)0, +//;0x0348 Reserved + (fp)0, +//;0x034C Reserved + (fp)0, +//;0x0350 Reserved + (fp)0, +//;0x0354 Reserved + (fp)0, +//;0x0358 SCI0_ERI0 + (fp)INT_Excep_SCI0_ERI0, +//;0x035C SCI0_RXI0 + (fp)INT_Excep_SCI0_RXI0, +//;0x0360 SCI0_TXI0 + (fp)INT_Excep_SCI0_TXI0, +//;0x0364 SCI0_TEI0 + (fp)INT_Excep_SCI0_TEI0, +//;0x0368 SCI1_ERI1 + (fp)INT_Excep_SCI1_ERI1, +//;0x036C SCI1_RXI1 + (fp)INT_Excep_SCI1_RXI1, +//;0x0370 SCI1_TXI1 + (fp)INT_Excep_SCI1_TXI1, +//;0x0374 SCI1_TEI1 + (fp)INT_Excep_SCI1_TEI1, +//;0x0378 SCI5_ERI5 + (fp)INT_Excep_SCI5_ERI5, +//;0x037C SCI5_RXI5 + (fp)INT_Excep_SCI5_RXI5, +//;0x0380 SCI5_TXI5 + (fp)INT_Excep_SCI5_TXI5, +//;0x0384 SCI5_TEI5 + (fp)INT_Excep_SCI5_TEI5, +//;0x0388 SCI6_ERI6 + (fp)INT_Excep_SCI6_ERI6, +//;0x038C SCI6_RXI6 + (fp)INT_Excep_SCI6_RXI6, +//;0x0390 SCI6_TXI6 + (fp)INT_Excep_SCI6_TXI6, +//;0x0394 SCI6_TEI6 + (fp)INT_Excep_SCI6_TEI6, +//;0x0398 SCI8_ERI8 + (fp)INT_Excep_SCI8_ERI8, +//;0x039C SCI8_RXI8 + (fp)INT_Excep_SCI8_RXI8, +//;0x03A0 SCI8_TXI8 + (fp)INT_Excep_SCI8_TXI8, +//;0x03A4 SCI8_TEI8 + (fp)INT_Excep_SCI8_TEI8, +//;0x03A8 SCI9_ERI9 + (fp)INT_Excep_SCI9_ERI9, +//;0x03AC SCI9_RXI9 + (fp)INT_Excep_SCI9_RXI9, +//;0x03B0 SCI9_TXI9 + (fp)INT_Excep_SCI9_TXI9, +//;0x03B4 SCI9_TEI9 + (fp)INT_Excep_SCI9_TEI9, +//;0x03B8 SCI12_ERI12 + (fp)INT_Excep_SCI12_ERI12, +//;0x03BC SCI12_RXI12 + (fp)INT_Excep_SCI12_RXI12, +//;0x03C0 SCI12_TXI12 + (fp)INT_Excep_SCI12_TXI12, +//;0x03C4 SCI12_TEI12 + (fp)INT_Excep_SCI12_TEI12, +//;0x03C8 SCI12_SCIX0 + (fp)INT_Excep_SCI12_SCIX0, +//;0x03CC SCI12_SCIX1 + (fp)INT_Excep_SCI12_SCIX1, +//;0x03D0 SCI12_SCIX2 + (fp)INT_Excep_SCI12_SCIX2, +//;0x03D4 SCI12_SCIX3 + (fp)INT_Excep_SCI12_SCIX3, +//;0x03D8 RIIC0_EEI0 + (fp)INT_Excep_RIIC0_EEI0, +//;0x03DC RIIC0_RXI0 + (fp)INT_Excep_RIIC0_RXI0, +//;0x03E0 RIIC0_TXI0 + (fp)INT_Excep_RIIC0_TXI0, +//;0x03E4 RIIC0_TEI0 + (fp)INT_Excep_RIIC0_TEI0, +//;0x03E8 Reserved + (fp)0, +//;0x03EC Reserved + (fp)0, +//;0x03F0 Reserved + (fp)0, +//;0x03F4 Reserved + (fp)0, +//;0x03F8 Reserved + (fp)0, +//;0x03FC Reserved + (fp)0, +}; diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c new file mode 100644 index 000000000..1e082fac8 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.c @@ -0,0 +1,115 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Create(void) +{ + uint32_t sckcr_dummy; + volatile uint32_t memorywaitcycle; + + /* Set main clock control registers */ + SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _00_CGC_MAINOSC_UNDER10M; + SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768; + + /* Set main clock operation */ + SYSTEM.MOSCCR.BIT.MOSTP = 0U; + + /* Wait for main clock oscillator wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF); + + /* Set system clock */ + sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000100_CGC_PCLKB_DIV_2 | _00001000_CGC_PCLKA_DIV_2 | + _00010000_CGC_BCLK_DIV_2 | _00000000_CGC_ICLK_DIV_1 | _10000000_CGC_FCLK_DIV_2; + SYSTEM.SCKCR.LONG = sckcr_dummy; + + while (SYSTEM.SCKCR.LONG != sckcr_dummy); + + /* Set PLL circuit */ + SYSTEM.PLLCR.WORD = _0000_CGC_PLL_FREQ_DIV_1 | _0C00_CGC_PLL_FREQ_MUL_6_5; + SYSTEM.PLLCR2.BIT.PLLEN = 0U; + + /* Wait for PLL wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF); + + /* Disable sub-clock */ + SYSTEM.SOSCCR.BIT.SOSTP = 1U; + + /* Wait for the register modification to complete */ + while (1U != SYSTEM.SOSCCR.BIT.SOSTP); + + /* Disable sub-clock */ + RTC.RCR3.BIT.RTCEN = 0U; + + /* Wait for the register modification to complete */ + while (0U != RTC.RCR3.BIT.RTCEN); + + /* Set BCLK */ + SYSTEM.SCKCR.BIT.PSTOP1 = 1U; + + /* Set memory wait cycle setting register */ + SYSTEM.MEMWAIT.BIT.MEMWAIT = 1U; + memorywaitcycle = SYSTEM.MEMWAIT.BYTE; + memorywaitcycle++; + + /* Set clock source */ + SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL; + + while (SYSTEM.SCKCR3.WORD != _0400_CGC_CLOCKSOURCE_PLL); + + /* Set LOCO */ + SYSTEM.LOCOCR.BIT.LCSTP = 1U; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h new file mode 100644 index 000000000..7732241d2 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc.h @@ -0,0 +1,227 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef CGC_H +#define CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + System Clock Control Register (SCKCR) +*/ +/* Peripheral Module Clock D (PCLKD) */ +#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */ +#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */ +#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */ +#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */ +#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */ +#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */ +#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */ +/* Peripheral Module Clock B (PCLKB) */ +#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */ +#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */ +#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */ +#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */ +#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */ +#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */ +#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */ +/* Peripheral Module Clock A (PCLKA) */ +#define _00000000_CGC_PCLKA_DIV_1 (0x00000000UL) /* x1 */ +#define _00001000_CGC_PCLKA_DIV_2 (0x00001000UL) /* x1/2 */ +#define _00002000_CGC_PCLKA_DIV_4 (0x00002000UL) /* x1/4 */ +#define _00003000_CGC_PCLKA_DIV_8 (0x00003000UL) /* x1/8 */ +#define _00004000_CGC_PCLKA_DIV_16 (0x00004000UL) /* x1/16 */ +#define _00005000_CGC_PCLKA_DIV_32 (0x00005000UL) /* x1/32 */ +#define _00006000_CGC_PCLKA_DIV_64 (0x00006000UL) /* x1/64 */ +/* External Bus Clock (BCLK) */ +#define _00000000_CGC_BCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _00010000_CGC_BCLK_DIV_2 (0x00010000UL) /* x1/2 */ +#define _00020000_CGC_BCLK_DIV_4 (0x00020000UL) /* x1/4 */ +#define _00030000_CGC_BCLK_DIV_8 (0x00030000UL) /* x1/8 */ +#define _00040000_CGC_BCLK_DIV_16 (0x00040000UL) /* x1/16 */ +#define _00050000_CGC_BCLK_DIV_32 (0x00050000UL) /* x1/32 */ +#define _00060000_CGC_BCLK_DIV_64 (0x00060000UL) /* x1/64 */ +/* System Clock (ICLK) */ +#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */ +#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */ +#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */ +#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */ +#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */ +#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */ +#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */ +/* System Clock (FCLK) */ +#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */ +#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */ +#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */ +#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */ +#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */ +#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */ + +/* + System Clock Control Register 3 (SCKCR3) +*/ +#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */ + +/* + PLL Control Register (PLLCR) +*/ +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */ +/* Frequency Multiplication Factor Select (STC[5:0]) */ +#define _0700_CGC_PLL_FREQ_MUL_4_0 (0x0700U) /* x4 */ +#define _0800_CGC_PLL_FREQ_MUL_4_5 (0x0800U) /* x4.5 */ +#define _0900_CGC_PLL_FREQ_MUL_5_0 (0x0900U) /* x5 */ +#define _0A00_CGC_PLL_FREQ_MUL_5_5 (0x0A00U) /* x5.5 */ +#define _0B00_CGC_PLL_FREQ_MUL_6_0 (0x0B00U) /* x6 */ +#define _0C00_CGC_PLL_FREQ_MUL_6_5 (0x0C00U) /* x6.5 */ +#define _0D00_CGC_PLL_FREQ_MUL_7_0 (0x0D00U) /* x7 */ +#define _0E00_CGC_PLL_FREQ_MUL_7_5 (0x0E00U) /* x7.5 */ +#define _0F00_CGC_PLL_FREQ_MUL_8_0 (0x0F00U) /* x8 */ +#define _1000_CGC_PLL_FREQ_MUL_8_5 (0x1000U) /* x8.5 */ +#define _1100_CGC_PLL_FREQ_MUL_9_0 (0x1100U) /* x9 */ +#define _1200_CGC_PLL_FREQ_MUL_9_5 (0x1200U) /* x9.5 */ +#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10 */ +#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11 */ +#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* 11.5 */ +#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12 */ +#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13 */ +#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +/* + USB-dedicated PLL Control Register (UPLLCR) +*/ +/* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */ +#define _0000_CGC_UPLL_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_UPLL_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_UPLL_DIV_4 (0x0002U) /* x1/4 */ +/* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */ +#define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */ +#define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */ +/* Frequency Multiplication Factor Select (USTC[5:0]) */ +#define _0700_CGC_UPLL_MUL_4 (0x0700U) /* x4 */ +#define _0B00_CGC_UPLL_MUL_6 (0x0B00U) /* x6 */ +#define _0F00_CGC_UPLL_MUL_8 (0x0F00U) /* x8 */ +#define _1700_CGC_UPLL_MUL_12 (0x1700U) /* x12 */ + +/* + High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) +*/ +/* HOCO Frequency Setting (HCFRQ[1:0]) */ +#define _00_CGC_HOCO_CLK_32 (0x00U) /* 32 MHz */ +#define _03_CGC_HOCO_CLK_54 (0x03U) /* 54 MHz */ + +/* + Oscillation Stop Detection Control Register (OSTDCR) +*/ +/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */ +#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */ +#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */ +/* Oscillation Stop Detection Function Enable (OSTDE) */ +#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */ +#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */ + +/* + Main Clock Oscillator Wait Control Register (MOSCWTCR) +*/ +/* Main Clock Oscillator Wait Time (MSTS[4:0]) */ +#define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */ +#define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */ +#define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */ +#define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */ +#define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */ +#define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */ +#define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */ +#define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */ + +/* + Clock Output Control Register (CKOCR) +*/ +/* Clock Output Source Select (CKOSEL[2:0]) */ +#define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLKOUT_PLLCLK (0x0400U) /* PLL clock oscillator */ +/* Clock Output Division Ratio Select (CKODIV[2:0]) */ +#define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */ +#define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */ +#define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */ +#define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */ +#define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */ +/* Clock Output Control (CKOSTP) */ +#define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */ +#define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */ + +/* + Main Clock Oscillator Forced Oscillation Control Register (MOFCR) +*/ +/* Main Oscillator Drive Capability Switch (MODRV21) */ +#define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */ +#define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */ +/* Main Clock Oscillator Switch (MOSEL) */ +#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */ + +/* + Low-power timer control register 1 (LPTCR1) +*/ +/* Low-Power Timer Clock Division Ratio Select (LPCNTPSSEL[2:0]) */ +#define _01_CGC_LPT_CLK_DIV_2 (0x01U) /* x1/2 */ +#define _02_CGC_LPT_CLK_DIV_4 (0x02U) /* x1/4 */ +#define _03_CGC_LPT_CLK_DIV_8 (0x03U) /* x1/8 */ +#define _04_CGC_LPT_CLK_DIV_16 (0x04U) /* x1/16 */ +#define _05_CGC_LPT_CLK_DIV_32 (0x05U) /* x1/32 */ +/* Low-Power Timer Clock Source Select (LPCNTCKSEL) */ +#define _00_CGC_LPT_SOURCE_SUB (0x00U) /* Sub-clock */ +#define _10_CGC_LPT_SOURCE_IWDT (0x10U) /* IWDT-dedicated on-chip */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c new file mode 100644 index 000000000..611001e2a --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_cgc_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc_user.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c new file mode 100644 index 000000000..f1bd64fd1 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_hardware_setup.c @@ -0,0 +1,92 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_hardware_setup.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements system initializing function. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +int HardwareSetup(void); +void R_Systeminit(void); + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every macro. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_Systeminit(void) +{ + /* Enable writing to registers related to operating modes, LPC, LPT, LVD, CGC and software reset */ + SYSTEM.PRCR.WORD = 0xA50FU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + /* Set peripheral settings */ + R_CGC_Create(); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.WORD = 0xA500U; +} +/*********************************************************************************************************************** +* Function Name: HardwareSetup +* Description : This function initializes hardware setting. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +int HardwareSetup(void) +{ + R_Systeminit(); + + return (1U); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_interrupt_handlers.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_interrupt_handlers.h new file mode 100644 index 000000000..c306c8b2e --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_interrupt_handlers.h @@ -0,0 +1,72 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_interrupt_handlers.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file declares interrupt handlers. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef INTERRUPT_HANDLERS_H +#define INTERRUPT_HANDLERS_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +/* Undefined */ +void r_undefined_exception(void) __attribute__ ((interrupt)); + +/* Access Exception */ +void r_access_exception(void) __attribute__ ((interrupt)); + +/* Privileged Instruction Exception */ +void r_privileged_exception(void) __attribute__ ((interrupt)); + +/* Floating Point Exception */ +void r_floatingpoint_exception(void) __attribute__ ((interrupt)); + +/* NMI */ +void r_nmi_exception(void) __attribute__ ((interrupt)); + +/* BRK */ +void r_brk_exception(void) __attribute__ ((interrupt)); + +/* Hardware Vectors */ +void PowerON_Reset(void) __attribute__ ((interrupt)); + +/* Idle Vectors */ +void r_undefined_exception(void) __attribute__ ((interrupt)); +void r_reserved_exception(void) __attribute__ ((interrupt)); + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h new file mode 100644 index 000000000..e8e55270d --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h @@ -0,0 +1,98 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements general head file. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef STATUS_H +#define STATUS_H +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "../iodefine.h" +#include "r_cg_interrupt_handlers.h" + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + + +#define nop() asm("nop;") +#define brk() asm("brk;") +#define wait() asm("wait;") + +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + #ifndef _STDINT_H + typedef signed char int8_t; + typedef unsigned char uint8_t; + typedef signed short int16_t; + typedef unsigned short uint16_t; + typedef signed long int32_t; + typedef unsigned long uint32_t; + + typedef signed char int_least8_t; + typedef signed short int_least16_t; + typedef signed long int_least32_t; + typedef unsigned char uint_least8_t; + typedef unsigned short uint_least16_t; + typedef unsigned long uint_least32_t; + #endif + + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_main.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_main.c new file mode 100644 index 000000000..4807a41f7 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_main.c @@ -0,0 +1,90 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_main.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements main function. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +void R_MAIN_UserInit(void); +/*********************************************************************************************************************** +* Function Name: main +* Description : This function implements main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void main(void) +{ + R_MAIN_UserInit(); + /* Start user code. Do not edit comment generated here */ + while (1U) + { + ; + } + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: R_MAIN_UserInit +* Description : This function adds user code before implementing main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_MAIN_UserInit(void) +{ + /* Start user code. Do not edit comment generated here */ + uint16_t protect_dummy = (uint16_t)(SYSTEM.PRCR.WORD & 0x000FU); + + /* Disable protect bit */ + SYSTEM.PRCR.WORD = 0xA50FU; + + SYSTEM.VBATTCR.BYTE = 0x81U; + + /* Restore the previous state of the protect register */ + SYSTEM.PRCR.WORD = (uint16_t)(0xA500U | protect_dummy); + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_reset_program.asm b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_reset_program.asm new file mode 100644 index 000000000..197bc41ce --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_reset_program.asm @@ -0,0 +1,195 @@ +;;/********************************************************************************************************************* +;;* DISCLAIMER +;;* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +;;* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +;;* applicable laws, including copyright laws. +;;* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +;;* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +;;* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +;;* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +;;* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +;;* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +;;* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +;;* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +;;* following link: +;;* http://www.renesas.com/disclaimer +;;* +;;* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +;;*********************************************************************************************************************/ +;;/* +;;********************************************************************************************************************** +;;* File Name : r_cg_reset_program.asm +;;* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +;;* Device(s) : R5F52318AxFP +;;* Tool-Chain : GCCRX +;;* Description : This is start up file for RX. +;;* Creation Date: 23/09/2015 +;;********************************************************************************************************************** +;;*/ + +;;reset_program.asm + + .list + .section .text + .global _PowerON_Reset ;;global Start routine + + .extern _HardwareSetup ;;external Sub-routine to initialise Hardware + .extern _data + .extern _mdata + .extern _ebss + .extern _bss + .extern _edata + .extern _main + .extern _ustack + .extern _istack + .extern _rvectors + .extern _exit + + +_PowerON_Reset : +;;initialise user stack pointer + mvtc #_ustack,USP + +;;initialise interrupt stack pointer + mvtc #_istack,ISP + +#ifdef __RXv2__ +;; setup exception vector + mvtc #_ExceptVectors, extb ;;EXCEPTION VECTOR ADDRESS +#endif +;;setup intb + mvtc #_rvectors_start, intb ;;INTERRUPT VECTOR ADDRESS definition + +;;setup FPSW + mvtc #100h, fpsw + +;;load data section from ROM to RAM + + mov #_mdata,r2 ;;src ROM address of data section in R2 + mov #_data,r1 ;;dest start RAM address of data section in R1 + mov #_edata,r3 ;;end RAM address of data section in R3 + sub r1,r3 ;;size of data section in R3 (R3=R3-R1) + smovf ;;block copy R3 bytes from R2 to R1 + +;;bss initialisation : zero out bss + + mov #00h,r2 ;;load R2 reg with zero + mov #_ebss, r3 ;;store the end address of bss in R3 + mov #_bss, r1 ;;store the start address of bss in R1 + sub r1,r3 ;;ize of bss section in R3 (R3=R3-R1) + sstr.b +;;call the hardware initialiser + bsr.a _HardwareSetup + nop + +;;setup PSW + mvtc #10000h, psw ;;Set Ubit & Ibit for PSW + +;;change PSW PM to user-mode + MVFC PSW,R1 +;;DO NOT CHANGE TO USER MODE OR #00100000h,R1 + PUSH.L R1 + MVFC PC,R1 + ADD #10,R1 + PUSH.L R1 + RTE + NOP + NOP +#ifdef CPPAPP + bsr.a __rx_init +#endif +;;start user program + bsr.a _main + bsr.a _exit + +#ifdef CPPAPP + .global _rx_run_preinit_array + .type _rx_run_preinit_array,@function +_rx_run_preinit_array: + mov #__preinit_array_start,r1 + mov #__preinit_array_end,r2 + bra.a _rx_run_inilist + + .global _rx_run_init_array + .type _rx_run_init_array,@function +_rx_run_init_array: + mov #__init_array_start,r1 + mov #__init_array_end,r2 + mov #4, r3 + bra.a _rx_run_inilist + + .global _rx_run_fini_array + .type _rx_run_fini_array,@function +_rx_run_fini_array: + mov #__fini_array_start,r2 + mov #__fini_array_end,r1 + mov #-4, r3 + ;;fall through + +_rx_run_inilist: +next_inilist: + cmp r1,r2 + beq.b done_inilist + mov.l [r1],r4 + cmp #-1, r4 + beq.b skip_inilist + cmp #0, r4 + beq.b skip_inilist + pushm r1-r3 + jsr r4 + popm r1-r3 +skip_inilist: + add r3,r1 + bra.b next_inilist +done_inilist: + rts + + .section .init,"ax" + .balign 4 + + .global __rx_init +__rx_init: + + .section .fini,"ax" + .balign 4 + + .global __rx_fini +__rx_fini: + bsr.a _rx_run_fini_array + + .section .sdata + .balign 4 + .global __gp + .weak __gp +__gp: + + .section .data + .global ___dso_handle + .weak ___dso_handle +___dso_handle: + .long 0 + + .section .init,"ax" + bsr.a _rx_run_preinit_array + bsr.a _rx_run_init_array + rts + + .global __rx_init_end +__rx_init_end: + + .section .fini,"ax" + + rts + .global __rx_fini_end +__rx_fini_end: + +#endif + +;;call to exit +_exit: + bra _loop_here +_loop_here: + bra _loop_here + + .text + .end diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h new file mode 100644 index 000000000..02e722de2 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_userdefine.h @@ -0,0 +1,37 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file includes user definition. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef _USER_DEF_H +#define _USER_DEF_H + +/*********************************************************************************************************************** +User definitions +***********************************************************************************************************************/ + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_vector_table.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_vector_table.c new file mode 100644 index 000000000..0218fd306 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/cg_src/r_cg_vector_table.c @@ -0,0 +1,467 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_vector_table.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : GCCRX +* Description : This file implements interrupt vector. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +typedef void (*fp) (void); +extern void PowerON_Reset (void); +extern void stack (void); + +#define OFS0_VAL 0xFFFFFFFFUL +#define OFS1_VAL 0xFFFFFFFFUL +#define EXVECT_SECT __attribute__ ((section (".exvectors"))) + +const void *ExceptVectors[] EXVECT_SECT = { +/* Start user code for adding. Do not edit comment generated here */ + /* 0xffffff80 MDE register */ +#ifdef __RX_BIG_ENDIAN__ + /* Big endian */ + (fp)0xfffffff8, +#else + /* Little endian */ + (fp)0xffffffff, +#endif + /* 0xffffff84 Reserved */ + r_reserved_exception, + /* 0xffffff88 OFS1 register */ + (fp) OFS1_VAL, + /* 0xffffff8c OFS0 register */ + (fp) OFS0_VAL, + /* 0xffffff90 Reserved */ + r_reserved_exception, + /* 0xffffff94 Reserved */ + r_reserved_exception, + /* 0xffffff98 Reserved */ + r_reserved_exception, + /* 0xffffff9c Reserved */ + r_reserved_exception, + /* 0xffffffa0 ID */ + (fp)0xffffffff, + /* 0xffffffa4 ID */ + (fp)0xffffffff, + /* 0xffffffa8 ID */ + (fp)0xffffffff, + /* 0xffffffac ID */ + (fp)0xffffffff, + /* 0xffffffb0 Reserved */ + r_reserved_exception, + /* 0xffffffb4 Reserved */ + r_reserved_exception, + /* 0xffffffb8 Reserved */ + r_reserved_exception, + /* 0xffffffbc Reserved */ + r_reserved_exception, + /* 0xffffffc0 Reserved */ + r_reserved_exception, + /* 0xffffffc4 Reserved */ + r_reserved_exception, + /* 0xffffffc8 Reserved */ + r_reserved_exception, + /* 0xffffffcc Reserved */ + r_reserved_exception, + /* 0xffffffd0 Exception(Supervisor Instruction) */ + r_privileged_exception, + /* 0xffffffd4 Exception(Access Instruction) */ + r_access_exception, + /* 0xffffffd8 Reserved */ + r_undefined_exception, + /* 0xffffffdc Exception(Undefined Instruction) */ + r_undefined_exception, + /* 0xffffffe0 Reserved */ + r_undefined_exception, + /* 0xffffffe4 Exception(Floating Point) */ + r_floatingpoint_exception, + /* 0xffffffe8 Reserved */ + r_undefined_exception, + /* 0xffffffec Reserved */ + r_undefined_exception, + /* 0xfffffff0 Reserved */ + r_undefined_exception, + /* 0xfffffff4 Reserved */ + r_undefined_exception, + /* 0xfffffff8 NMI */ + r_nmi_exception +/* End user code. Do not edit comment generated here */ +}; + +#define FVECT_SECT __attribute__ ((section (".fvectors"))) +const void *HardwareVectors[] FVECT_SECT = { + /* 0xfffffffc RESET */ + /* <> */ + /* Power On Reset PC */ + PowerON_Reset + /* <> */ +}; + +#define RVECT_SECT __attribute__ ((section (".rvectors"))) + +const fp RelocatableVectors[] RVECT_SECT = { + /* 0x0000 Reserved */ + (fp)r_reserved_exception, + /* 0x0004 Reserved */ + (fp)r_reserved_exception, + /* 0x0008 Reserved */ + (fp)r_reserved_exception, + /* 0x000C Reserved */ + (fp)r_reserved_exception, + /* 0x0010 Reserved */ + (fp)r_reserved_exception, + /* 0x0014 Reserved */ + (fp)r_reserved_exception, + /* 0x0018 Reserved */ + (fp)r_reserved_exception, + /* 0x001C Reserved */ + (fp)r_reserved_exception, + /* 0x0020 Reserved */ + (fp)r_reserved_exception, + /* 0x0024 Reserved */ + (fp)r_reserved_exception, + /* 0x0028 Reserved */ + (fp)r_reserved_exception, + /* 0x002C Reserved */ + (fp)r_reserved_exception, + /* 0x0030 Reserved */ + (fp)r_reserved_exception, + /* 0x0034 Reserved */ + (fp)r_reserved_exception, + /* 0x0038 Reserved */ + (fp)r_reserved_exception, + /* 0x003C Reserved */ + (fp)r_reserved_exception, + /* 0x0040 BSC BUSERR */ + (fp)r_undefined_exception, + /* 0x0044 Reserved */ + (fp)r_reserved_exception, + /* 0x0048 Reserved */ + (fp)r_undefined_exception, + /* 0x004C Reserved */ + (fp)r_reserved_exception, + /* 0x0050 Reserved */ + (fp)r_reserved_exception, + /* 0x0054 Reserved */ + (fp)r_undefined_exception, + /* 0x0058 Reserved */ + (fp)r_reserved_exception, + /* 0x005C Reserved */ + (fp)r_undefined_exception, + /* 0x0060 Reserved */ + (fp)r_reserved_exception, + /* 0x0064 Reserved */ + (fp)r_reserved_exception, + /* 0x0068 ICU SWINT2 */ + (fp)r_undefined_exception, + /* 0x006C ICU SWINT */ + (fp)r_undefined_exception, + /* 0x0070 CMT0 */ + (fp)r_undefined_exception, + /* 0x0074 CMT1 */ + (fp)r_undefined_exception, + /* 0x0078 CMTW0 */ + (fp)r_undefined_exception, + /* 0x007C CMTW1 */ + (fp)r_undefined_exception, + /* 0x0080 USBA D0FIFO2 */ + (fp)r_undefined_exception, + /* 0x0084 USBA D1FIFO2 */ + (fp)r_undefined_exception, + /* 0x0088 USB0 D0FIFO0 */ + (fp)r_undefined_exception, + /* 0x008C USB0 D0FIFO0 */ + (fp)r_undefined_exception, + /* 0x0090 Reserved */ + (fp)r_reserved_exception, + /* 0x0094 Reserved */ + (fp)r_reserved_exception, + /* 0x0098 RSPI0 SPRI0 */ + (fp)r_undefined_exception, + /* 0x009C RSPI0 SPTI0 */ + (fp)r_undefined_exception, + /* 0x00A0 RSPI1 SPRI1 */ + (fp)r_undefined_exception, + /* 0x00A4 RSPI1 SPTI1 */ + (fp)r_undefined_exception, + /* 0x00A8 QSPI SPRI */ + (fp)r_undefined_exception, + /* 0x00AC QSPI SPTI */ + (fp)r_undefined_exception, + /* 0x00B0 SDHI SBFAI */ + (fp)r_undefined_exception, + /* 0x00B4 MMC MBFAI */ + (fp)r_undefined_exception, + /* 0x00B8 SSI0 SSITX0 */ + (fp)r_undefined_exception, + /* 0x00BC SSI0 SSIRX0 */ + (fp)r_undefined_exception, + /* 0x00C0 SSI1 SSIRTI1 */ + (fp)r_undefined_exception, + /* 0x00C4 Reserved */ + (fp)r_reserved_exception, + /* 0x00C8 SRC IDEI */ + (fp)r_undefined_exception, + /* 0x00CC SRC ODFI */ + (fp)r_undefined_exception, + /* 0x00E0 Reserved */ + (fp)r_reserved_exception, + /* 0x00E4 Reserved */ + (fp)r_reserved_exception, + /* 0x00E8 SCI0 RXI0 */ + (fp)r_undefined_exception, + /* 0x00EC SCI0 TXI0 */ + (fp)r_undefined_exception, + /* 0x00F0 SCI1 RXI1 */ + (fp)r_undefined_exception, + /* 0x00F4 SCI1 TXI1 */ + (fp)r_undefined_exception, + /* 0x00F8 SCI2 RXI2 */ + (fp)r_undefined_exception, + /* 0x00FC SCI2 TXI2 */ + (fp)r_undefined_exception, + /* 0x0100 ICU IRQ0 */ + (fp)r_undefined_exception, + /* 0x0104 ICU IRQ1 */ + (fp)r_undefined_exception, + /* 0x0108 ICU IRQ2 */ + (fp)r_undefined_exception, + /* 0x010C ICU IRQ3 */ + (fp)r_undefined_exception, + /* 0x0110 ICU IRQ4 */ + (fp)r_undefined_exception, + /* 0x0114 ICU IRQ5 */ + (fp)r_undefined_exception, + /* 0x0118 ICU IRQ6 */ + (fp)r_undefined_exception, + /* 0x011C ICU IRQ7 */ + (fp)r_undefined_exception, + /* 0x0120 ICU IRQ8 */ + (fp)r_undefined_exception, + /* 0x0124 ICU IRQ9 */ + (fp)r_undefined_exception, + /* 0x0128 ICU IRQ10 */ + (fp)r_undefined_exception, + /* 0x012C ICU IRQ11 */ + (fp)r_undefined_exception, + /* 0x0130 ICU IRQ12 */ + (fp)r_undefined_exception, + /* 0x0134 ICU IRQ13 */ + (fp)r_undefined_exception, + /* 0x0138 ICU IRQ14 */ + (fp)r_undefined_exception, + /* 0x013C ICU IRQ15 */ + (fp)r_undefined_exception, + /* 0x0140 SCI3 RXI3 */ + (fp)r_undefined_exception, + /* 0x0144 SCI3 TXI3 */ + (fp)r_undefined_exception, + /* 0x0148 SCI4 RXI4 */ + (fp)r_undefined_exception, + /* 0x014C SCI4 TXI4 */ + (fp)r_undefined_exception, + /* 0x0150 SCI5 RXI5 */ + (fp)r_undefined_exception, + /* 0x0154 SCI5 TXI5 */ + (fp)r_undefined_exception, + /* 0x0158 SCI6 RXI6 */ + (fp)r_undefined_exception, + /* 0x015C SCI6 TXI6 */ + (fp)r_undefined_exception, + /* 0x0160 LVD LVD1 */ + (fp)r_undefined_exception, + /* 0x0164 LVD LVD2 */ + (fp)r_undefined_exception, + /* 0x0168 USB0 USBR0 */ + (fp)r_undefined_exception, + /* 0x016C Reserved */ + (fp)r_reserved_exception, + /* 0x0170 RTC ALM */ + (fp)r_undefined_exception, + /* 0x0174 RTC PRD */ + (fp)r_undefined_exception, + /* 0x0178 USBA USBHSR */ + (fp)r_undefined_exception, + /* 0x0184 PDC PCDFI */ + (fp)r_undefined_exception, + /* 0x0188 SCI7 RXI7 */ + (fp)r_undefined_exception, + /* 0x018C SCI7 TXI7 */ + (fp)r_undefined_exception, + /* 0x0190 SCIFA8 RXIF8 */ + (fp)r_undefined_exception, + /* 0x0194 SCIF8 TXIF8 */ + (fp)r_undefined_exception, + /* 0x0198 SCIF9 RXIF9 */ + (fp)r_undefined_exception, + /* 0x019C SCIF9 TXIF9 */ + (fp)r_undefined_exception, + /* 0x01A0 SCIF10 RXIF10 */ + (fp)r_undefined_exception, + /* 0x01A4 SCIF10 TXIF10 */ + (fp)r_undefined_exception, + /* 0x01A8 ICU GROUP_BE0 */ + (fp)r_undefined_exception, + /* 0x01AC Reserved */ + (fp)r_reserved_exception, + /* 0x01B0 Reserved */ + (fp)r_reserved_exception, + /* 0x01B4 Reserved */ + (fp)r_reserved_exception, + /* 0x01B8 ICU GROUP_BL0 */ + (fp)r_undefined_exception, + /* 0x01BC ICU GROUP_BL1 */ + (fp)r_undefined_exception, + /* 0x01C0 ICU GROUP_AL0 */ + (fp)r_undefined_exception, + /* 0x01C4 ICU GROUP_AL1 */ + (fp)r_undefined_exception, + /* 0x01C8 SCIF11 RXIF11 */ + (fp)r_undefined_exception, + /* 0x01CC SCIF11 TXIF11 */ + (fp)r_undefined_exception, + /* 0x01D0 SCI12 RXI12 */ + (fp)r_undefined_exception, + /* 0x01D4 SCI12 TXI12 */ + (fp)r_undefined_exception, + /* 0x01D8 Reserved */ + (fp)r_reserved_exception, + /* 0x01DC Reserved */ + (fp)r_reserved_exception, + /* 0x01F4 OST OST */ + (fp)r_undefined_exception, + /* 0x01F8 EXDMAC EXDMAC0I */ + (fp)r_undefined_exception, + /* 0x01FC EXDMAC EXDMAC1I */ + (fp)r_undefined_exception, + /* 0x0318 DMAC DMAC0I */ + (fp)r_undefined_exception, + /* 0x031C DMAC DMAC1I */ + (fp)r_undefined_exception, + /* 0x0320 DMAC DMAC2I */ + (fp)r_undefined_exception, + /* 0x0324 DMAC DMAC3I */ + (fp)r_undefined_exception, + /* 0x03D8 RIIC0 EEI0 */ + (fp)r_undefined_exception, + /* 0x03DC RIIC0 RXI0 */ + (fp)r_undefined_exception, + /* 0x03E0 RIIC0 TXI0 */ + (fp)r_undefined_exception, + /* 0x03E4 RIIC0 TEI0 */ + (fp)r_undefined_exception, + +}; + +/*********************************************************************************************************************** +* Function Name: r_undefined_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_undefined_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_reserved_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_reserved_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_nmi_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_nmi_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_brk_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_brk_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_privileged_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_privileged_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_access_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_access_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_floatingpoint_exception +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_floatingpoint_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/iodefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/iodefine.h new file mode 100644 index 000000000..ded747368 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/iodefine.h @@ -0,0 +1,22195 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : iodefine.h */ +/* DESCRIPTION : Definition of I/O Registers */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/********************************************************************************* +* +* Device : RX/RX200/RX231 +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register. +* +* History : 0.5A (2014-09-18) [Hardware Manual Revision : 0.50] +* : 1.0A (2015-05-18) [Hardware Manual Revision : 1.00] +* : 1.0C (2015-07-21) [Hardware Manual Revision : 1.00] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2015 (2014) Renesas Electronics Corporation. +* +*********************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX231 */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(MTU0,TGIA0) = 0; expands to : */ +/* ICU.IR[114].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(MTU1,TGIA1) = 2; expands to : */ +/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */ +/* ICU.IPR[121].BIT.IPR = 2; */ +/* */ +/* IPR(SCI0,ERI0) = 3; expands to : */ +/* IPR(SCI0, ) = 3; // SCI0 uses single IPR for all sources. */ +/* ICU.IPR[214].BIT.IPR = 3; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */ +/* #pragma interrupt INT_TPU0_TGI0A(vect=VECT(TPU0,TGI0A)) expands to : */ +/* #pragma interrupt INT_TPU0_TGI0A(vect=142) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(TPU4) = 0; // TPU,TPU0,TPU1,TPU2,TPU3,TPU4,TPU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA13 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX231IODEFINE_HEADER__ +#define __RX231IODEFINE_HEADER__ + +#pragma pack(4) + +struct st_bsc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char STSCLR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char STSCLR : 1; +#endif + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IGAEN : 1; + unsigned char TOEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TOEN : 1; + unsigned char IGAEN : 1; +#endif + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IA : 1; + unsigned char TO : 1; + unsigned char : 2; + unsigned char MST : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MST : 3; + unsigned char : 2; + unsigned char TO : 1; + unsigned char IA : 1; +#endif + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 3; + unsigned short ADDR : 13; +#else + unsigned short ADDR : 13; + unsigned short : 3; +#endif + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BPRA : 2; + unsigned short BPRO : 2; + unsigned short BPIB : 2; + unsigned short BPGB : 2; + unsigned short BPHB : 2; + unsigned short BPFB : 2; + unsigned short BPEB : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short BPEB : 2; + unsigned short BPFB : 2; + unsigned short BPHB : 2; + unsigned short BPGB : 2; + unsigned short BPIB : 2; + unsigned short BPRO : 2; + unsigned short BPRA : 2; +#endif + } BIT; + } BUSPRI; + char wk4[7408]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS0WCR2; + char wk5[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS1WCR2; + char wk6[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS2WCR2; + char wk7[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif + } BIT; + } CS3WCR2; + char wk8[1990]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS0CR; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS0REC; + char wk10[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS1CR; + char wk11[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS1REC; + char wk12[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS2CR; + char wk13[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS2REC; + char wk14[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif + } BIT; + } CS3CR; + char wk15[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif + } BIT; + } CS3REC; + char wk16[68]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RCVEN0 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM7 : 1; +#else + unsigned short RCVENM7 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN0 : 1; +#endif + } BIT; + } CSRECEN; +}; + +struct st_cac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CFME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CFME : 1; +#endif + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CACREFE : 1; + unsigned char FMCS : 3; + unsigned char TCSS : 2; + unsigned char EDGES : 2; +#else + unsigned char EDGES : 2; + unsigned char TCSS : 2; + unsigned char FMCS : 3; + unsigned char CACREFE : 1; +#endif + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RPS : 1; + unsigned char RSCS : 3; + unsigned char RCDS : 2; + unsigned char DFS : 2; +#else + unsigned char DFS : 2; + unsigned char RCDS : 2; + unsigned char RSCS : 3; + unsigned char RPS : 1; +#endif + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRIE : 1; + unsigned char MENDIE : 1; + unsigned char OVFIE : 1; + unsigned char : 1; + unsigned char FERRFCL : 1; + unsigned char MENDFCL : 1; + unsigned char OVFFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char OVFFCL : 1; + unsigned char MENDFCL : 1; + unsigned char FERRFCL : 1; + unsigned char : 1; + unsigned char OVFIE : 1; + unsigned char MENDIE : 1; + unsigned char FERRIE : 1; +#endif + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRF : 1; + unsigned char MENDF : 1; + unsigned char OVFF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char OVFF : 1; + unsigned char MENDF : 1; + unsigned char FERRF : 1; +#endif + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +}; + +struct st_rscan { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TPRI : 1; + unsigned short DCE : 1; + unsigned short DRE : 1; + unsigned short MME : 1; + unsigned short DCS : 1; + unsigned short : 3; + unsigned short TSP : 4; + unsigned short TSSS : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short TSSS : 1; + unsigned short TSP : 4; + unsigned short : 3; + unsigned short DCS : 1; + unsigned short MME : 1; + unsigned short DRE : 1; + unsigned short DCE : 1; + unsigned short TPRI : 1; +#endif + } BIT; + } GCFGL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITRCP : 16; +#else + unsigned short ITRCP : 16; +#endif + } BIT; + } GCFGH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GMDC : 2; + unsigned short GSLPR : 1; + unsigned short : 5; + unsigned short DEIE : 1; + unsigned short MEIE : 1; + unsigned short THLEIE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short THLEIE : 1; + unsigned short MEIE : 1; + unsigned short DEIE : 1; + unsigned short : 5; + unsigned short GSLPR : 1; + unsigned short GMDC : 2; +#endif + } BIT; + } GCTRL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSRST : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short TSRST : 1; +#endif + } BIT; + } GCTRH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GRSTSTS : 1; + unsigned short GHLTSTS : 1; + unsigned short GSLPSTS : 1; + unsigned short GRAMINIT : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short GRAMINIT : 1; + unsigned short GSLPSTS : 1; + unsigned short GHLTSTS : 1; + unsigned short GRSTSTS : 1; +#endif + } BIT; + } GSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DEF : 1; + unsigned char MES : 1; + unsigned char THLES : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char THLES : 1; + unsigned char MES : 1; + unsigned char DEF : 1; +#endif + } BIT; + } GERFLL; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TS : 16; +#else + unsigned short TS : 16; +#endif + } BIT; + } GTSC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RNC0 : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short RNC0 : 5; +#endif + } BIT; + } GAFLCFG; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short NRXMB : 5; + unsigned short : 11; +#else + unsigned short : 11; + unsigned short NRXMB : 5; +#endif + } BIT; + } RMNB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMNS : 16; +#else + unsigned short RMNS : 16; +#endif + } BIT; + } RMND0; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFE : 1; + unsigned short RFIE : 1; + unsigned short : 6; + unsigned short RFDC : 3; + unsigned short : 1; + unsigned short RFIM : 1; + unsigned short RFIGCV : 3; +#else + unsigned short RFIGCV : 3; + unsigned short RFIM : 1; + unsigned short : 1; + unsigned short RFDC : 3; + unsigned short : 6; + unsigned short RFIE : 1; + unsigned short RFE : 1; +#endif + } BIT; + } RFCC0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFE : 1; + unsigned short RFIE : 1; + unsigned short : 6; + unsigned short RFDC : 3; + unsigned short : 1; + unsigned short RFIM : 1; + unsigned short RFIGCV : 3; +#else + unsigned short RFIGCV : 3; + unsigned short RFIM : 1; + unsigned short : 1; + unsigned short RFDC : 3; + unsigned short : 6; + unsigned short RFIE : 1; + unsigned short RFE : 1; +#endif + } BIT; + } RFCC1; + char wk2[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFEMP : 1; + unsigned short RFFLL : 1; + unsigned short RFMLT : 1; + unsigned short RFIF : 1; + unsigned short : 4; + unsigned short RFMC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RFMC : 6; + unsigned short : 4; + unsigned short RFIF : 1; + unsigned short RFMLT : 1; + unsigned short RFFLL : 1; + unsigned short RFEMP : 1; +#endif + } BIT; + } RFSTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFEMP : 1; + unsigned short RFFLL : 1; + unsigned short RFMLT : 1; + unsigned short RFIF : 1; + unsigned short : 4; + unsigned short RFMC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RFMC : 6; + unsigned short : 4; + unsigned short RFIF : 1; + unsigned short RFMLT : 1; + unsigned short RFFLL : 1; + unsigned short RFEMP : 1; +#endif + } BIT; + } RFSTS1; + char wk3[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short RFPC : 8; +#endif + } BIT; + } RFPCTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short RFPC : 8; +#endif + } BIT; + } RFPCTR1; + char wk4[20]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RF0MLT : 1; + unsigned char RF1MLT : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RF1MLT : 1; + unsigned char RF0MLT : 1; +#endif + } BIT; + } RFMSTS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RF0IF : 1; + unsigned char RF1IF : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char RF1IF : 1; + unsigned char RF0IF : 1; +#endif + } BIT; + } RFISTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0IF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CF0IF : 1; +#endif + } BIT; + } CFISTS; + char wk6[36]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSIF0 : 1; + unsigned short TAIF0 : 1; + unsigned short CFTIF0 : 1; + unsigned short THIF0 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short THIF0 : 1; + unsigned short CFTIF0 : 1; + unsigned short TAIF0 : 1; + unsigned short TSIF0 : 1; +#endif + } BIT; + } GTINTSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RPAGE : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RPAGE : 1; +#endif + } BIT; + } GRWCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short RTMPS : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short RTMPS : 3; + unsigned short : 8; +#endif + } BIT; + } GTSTCFG; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char RTME : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char RTME : 1; + unsigned char : 2; +#endif + } BIT; + } GTSTCTRL; + char wk7[5]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LOCK : 16; +#else + unsigned short LOCK : 16; +#endif + } BIT; + } GLOCKK; + char wk8[10]; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR0; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF00; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF20; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF30; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR1; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF01; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF21; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF31; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR2; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF02; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF12; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF22; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF32; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR3; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF03; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF13; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF23; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF33; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR4; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF04; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF14; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF24; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF34; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR5; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF05; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF15; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF25; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF35; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR6; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF06; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF16; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF26; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF36; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR7; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF07; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF17; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF27; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF37; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR8; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF08; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF18; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF28; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF38; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR9; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF09; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF19; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF29; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF39; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR10; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF010; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF110; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF210; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF310; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 16; +#else + unsigned short GAFLID : 16; +#endif + } BIT; + } GAFLIDL15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLID : 13; + unsigned short GAFLLB : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLIDE : 1; +#else + unsigned short GAFLIDE : 1; + unsigned short GAFLRTR : 1; + unsigned short GAFLLB : 1; + unsigned short GAFLID : 13; +#endif + } BIT; + } GAFLIDH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR11; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 16; +#else + unsigned short GAFLIDM : 16; +#endif + } BIT; + } GAFLML15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF011; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLIDM : 13; + unsigned short : 1; + unsigned short GAFLRTRM : 1; + unsigned short GAFLIDEM : 1; +#else + unsigned short GAFLIDEM : 1; + unsigned short GAFLRTRM : 1; + unsigned short : 1; + unsigned short GAFLIDM : 13; +#endif + } BIT; + } GAFLMH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF111; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLFDP0 : 1; + unsigned short GAFLFDP1 : 1; + unsigned short : 2; + unsigned short GAFLFDP4 : 1; + unsigned short : 3; + unsigned short GAFLRMDP : 7; + unsigned short GAFLRMV : 1; +#else + unsigned short GAFLRMV : 1; + unsigned short GAFLRMDP : 7; + unsigned short : 3; + unsigned short GAFLFDP4 : 1; + unsigned short : 2; + unsigned short GAFLFDP1 : 1; + unsigned short GAFLFDP0 : 1; +#endif + } BIT; + } GAFLPL15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF211; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short GAFLPTR : 12; + unsigned short GAFLDLC : 4; +#else + unsigned short GAFLDLC : 4; + unsigned short GAFLPTR : 12; +#endif + } BIT; + } GAFLPH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF311; + }; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF012; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF112; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF212; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF312; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF013; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF113; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF213; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF313; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF014; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF114; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF214; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF314; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 16; +#else + unsigned short RMID : 16; +#endif + } BIT; + } RMIDL15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMID : 13; + unsigned short : 1; + unsigned short RMRTR : 1; + unsigned short RMIDE : 1; +#else + unsigned short RMIDE : 1; + unsigned short RMRTR : 1; + unsigned short : 1; + unsigned short RMID : 13; +#endif + } BIT; + } RMIDH15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMTS : 16; +#else + unsigned short RMTS : 16; +#endif + } BIT; + } RMTS15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMPTR : 12; + unsigned short RMDLC : 4; +#else + unsigned short RMDLC : 4; + unsigned short RMPTR : 12; +#endif + } BIT; + } RMPTR15; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB0 : 8; + unsigned short RMDB1 : 8; +#else + unsigned short RMDB1 : 8; + unsigned short RMDB0 : 8; +#endif + } BIT; + } RMDF015; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB2 : 8; + unsigned short RMDB3 : 8; +#else + unsigned short RMDB3 : 8; + unsigned short RMDB2 : 8; +#endif + } BIT; + } RMDF115; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB4 : 8; + unsigned short RMDB5 : 8; +#else + unsigned short RMDB5 : 8; + unsigned short RMDB4 : 8; +#endif + } BIT; + } RMDF215; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RMDB6 : 8; + unsigned short RMDB7 : 8; +#else + unsigned short RMDB7 : 8; + unsigned short RMDB6 : 8; +#endif + } BIT; + } RMDF315; + char wk9[224]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC7; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC8; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC9; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC14; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC15; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 16; +#else + unsigned short RFID : 16; +#endif + } BIT; + } RFIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC16; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 13; + unsigned short : 1; + unsigned short RFRTR : 1; + unsigned short RFIDE : 1; +#else + unsigned short RFIDE : 1; + unsigned short RFRTR : 1; + unsigned short : 1; + unsigned short RFID : 13; +#endif + } BIT; + } RFIDH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC17; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFTS : 16; +#else + unsigned short RFTS : 16; +#endif + } BIT; + } RFTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC18; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPTR : 12; + unsigned short RFDLC : 4; +#else + unsigned short RFDLC : 4; + unsigned short RFPTR : 12; +#endif + } BIT; + } RFPTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC19; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB0 : 8; + unsigned short RFDB1 : 8; +#else + unsigned short RFDB1 : 8; + unsigned short RFDB0 : 8; +#endif + } BIT; + } RFDF00; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC20; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB2 : 8; + unsigned short RFDB3 : 8; +#else + unsigned short RFDB3 : 8; + unsigned short RFDB2 : 8; +#endif + } BIT; + } RFDF10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC21; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB4 : 8; + unsigned short RFDB5 : 8; +#else + unsigned short RFDB5 : 8; + unsigned short RFDB4 : 8; +#endif + } BIT; + } RFDF20; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC22; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB6 : 8; + unsigned short RFDB7 : 8; +#else + unsigned short RFDB7 : 8; + unsigned short RFDB6 : 8; +#endif + } BIT; + } RFDF30; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC23; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 16; +#else + unsigned short RFID : 16; +#endif + } BIT; + } RFIDL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC24; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFID : 13; + unsigned short : 1; + unsigned short RFRTR : 1; + unsigned short RFIDE : 1; +#else + unsigned short RFIDE : 1; + unsigned short RFRTR : 1; + unsigned short : 1; + unsigned short RFID : 13; +#endif + } BIT; + } RFIDH1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC25; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFTS : 16; +#else + unsigned short RFTS : 16; +#endif + } BIT; + } RFTS1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC26; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFPTR : 12; + unsigned short RFDLC : 4; +#else + unsigned short RFDLC : 4; + unsigned short RFPTR : 12; +#endif + } BIT; + } RFPTR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC27; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB0 : 8; + unsigned short RFDB1 : 8; +#else + unsigned short RFDB1 : 8; + unsigned short RFDB0 : 8; +#endif + } BIT; + } RFDF01; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC28; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB2 : 8; + unsigned short RFDB3 : 8; +#else + unsigned short RFDB3 : 8; + unsigned short RFDB2 : 8; +#endif + } BIT; + } RFDF11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC29; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB4 : 8; + unsigned short RFDB5 : 8; +#else + unsigned short RFDB5 : 8; + unsigned short RFDB4 : 8; +#endif + } BIT; + } RFDF21; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC30; + }; + union { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFDB6 : 8; + unsigned short RFDB7 : 8; +#else + unsigned short RFDB7 : 8; + unsigned short RFDB6 : 8; +#endif + } BIT; + } RFDF31; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC31; + }; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC32; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC33; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC34; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC35; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC36; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC37; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC38; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC39; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC40; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC41; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC42; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC43; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC44; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC45; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC46; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC47; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC48; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC49; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC50; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC51; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC52; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC53; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC54; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC55; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC56; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC57; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC58; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC59; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC60; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC61; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC62; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC63; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC64; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC65; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC66; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC67; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC68; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC69; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC70; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC71; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC72; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC73; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC74; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC75; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC76; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC77; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC78; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC79; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC80; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC81; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC82; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC83; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC84; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC85; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC86; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC87; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC88; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC89; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC90; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC91; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC92; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC93; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC94; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC95; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC96; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC97; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC98; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC99; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC100; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC101; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC102; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC103; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC104; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC105; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC106; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC107; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC108; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC109; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC110; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC111; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC112; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC113; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC114; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC115; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC116; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC117; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC118; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC119; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC120; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC121; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC122; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC123; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC124; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC125; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC126; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDTA : 16; +#else + unsigned short RDTA : 16; +#endif + } BIT; + } RPGACC127; +}; + +struct st_rscan0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BRP : 10; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short BRP : 10; +#endif + } BIT; + } CFGL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSEG1 : 4; + unsigned short TSEG2 : 3; + unsigned short : 1; + unsigned short SJW : 2; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short SJW : 2; + unsigned short : 1; + unsigned short TSEG2 : 3; + unsigned short TSEG1 : 4; +#endif + } BIT; + } CFGH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CHMDC : 2; + unsigned short CSLPR : 1; + unsigned short RTBO : 1; + unsigned short : 4; + unsigned short BEIE : 1; + unsigned short EWIE : 1; + unsigned short EPIE : 1; + unsigned short BOEIE : 1; + unsigned short BORIE : 1; + unsigned short OLIE : 1; + unsigned short BLIE : 1; + unsigned short ALIE : 1; +#else + unsigned short ALIE : 1; + unsigned short BLIE : 1; + unsigned short OLIE : 1; + unsigned short BORIE : 1; + unsigned short BOEIE : 1; + unsigned short EPIE : 1; + unsigned short EWIE : 1; + unsigned short BEIE : 1; + unsigned short : 4; + unsigned short RTBO : 1; + unsigned short CSLPR : 1; + unsigned short CHMDC : 2; +#endif + } BIT; + } CTRL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TAIE : 1; + unsigned short : 4; + unsigned short BOM : 2; + unsigned short ERRD : 1; + unsigned short CTME : 1; + unsigned short CTMS : 2; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CTMS : 2; + unsigned short CTME : 1; + unsigned short ERRD : 1; + unsigned short BOM : 2; + unsigned short : 4; + unsigned short TAIE : 1; +#endif + } BIT; + } CTRH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CRSTSTS : 1; + unsigned short CHLTSTS : 1; + unsigned short CSLPSTS : 1; + unsigned short EPSTS : 1; + unsigned short BOSTS : 1; + unsigned short TRMSTS : 1; + unsigned short RECSTS : 1; + unsigned short COMSTS : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short COMSTS : 1; + unsigned short RECSTS : 1; + unsigned short TRMSTS : 1; + unsigned short BOSTS : 1; + unsigned short EPSTS : 1; + unsigned short CSLPSTS : 1; + unsigned short CHLTSTS : 1; + unsigned short CRSTSTS : 1; +#endif + } BIT; + } STSL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short REC : 8; + unsigned short TEC : 8; +#else + unsigned short TEC : 8; + unsigned short REC : 8; +#endif + } BIT; + } STSH; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BEF : 1; + unsigned short EWF : 1; + unsigned short EPF : 1; + unsigned short BOEF : 1; + unsigned short BORF : 1; + unsigned short OVLF : 1; + unsigned short BLF : 1; + unsigned short ALF : 1; + unsigned short SERR : 1; + unsigned short FERR : 1; + unsigned short AERR : 1; + unsigned short CERR : 1; + unsigned short B1ERR : 1; + unsigned short B0ERR : 1; + unsigned short ADERR : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short ADERR : 1; + unsigned short B0ERR : 1; + unsigned short B1ERR : 1; + unsigned short CERR : 1; + unsigned short AERR : 1; + unsigned short FERR : 1; + unsigned short SERR : 1; + unsigned short ALF : 1; + unsigned short BLF : 1; + unsigned short OVLF : 1; + unsigned short BORF : 1; + unsigned short BOEF : 1; + unsigned short EPF : 1; + unsigned short EWF : 1; + unsigned short BEF : 1; +#endif + } BIT; + } ERFLL; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CRCREG : 15; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short CRCREG : 15; +#endif + } BIT; + } ERFLH; + char wk0[64]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFE : 1; + unsigned short CFRXIE : 1; + unsigned short CFTXIE : 1; + unsigned short : 5; + unsigned short CFDC : 3; + unsigned short : 1; + unsigned short CFIM : 1; + unsigned short CFIGCV : 3; +#else + unsigned short CFIGCV : 3; + unsigned short CFIM : 1; + unsigned short : 1; + unsigned short CFDC : 3; + unsigned short : 5; + unsigned short CFTXIE : 1; + unsigned short CFRXIE : 1; + unsigned short CFE : 1; +#endif + } BIT; + } CFCCL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFM : 2; + unsigned short CFITSS : 1; + unsigned short CFITR : 1; + unsigned short CFTML : 2; + unsigned short : 2; + unsigned short CFITT : 8; +#else + unsigned short CFITT : 8; + unsigned short : 2; + unsigned short CFTML : 2; + unsigned short CFITR : 1; + unsigned short CFITSS : 1; + unsigned short CFM : 2; +#endif + } BIT; + } CFCCH0; + char wk1[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFEMP : 1; + unsigned short CFFLL : 1; + unsigned short CFMLT : 1; + unsigned short CFRXIF : 1; + unsigned short CFTXIF : 1; + unsigned short : 3; + unsigned short CFMC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short CFMC : 6; + unsigned short : 3; + unsigned short CFTXIF : 1; + unsigned short CFRXIF : 1; + unsigned short CFMLT : 1; + unsigned short CFFLL : 1; + unsigned short CFEMP : 1; +#endif + } BIT; + } CFSTS0; + char wk2[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CFPC : 8; +#endif + } BIT; + } CFPCTR0; + char wk3[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0MLT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CF0MLT : 1; +#endif + } BIT; + } CFMSTS; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTR : 1; + unsigned char TMTAR : 1; + unsigned char TMOM : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TMOM : 1; + unsigned char TMTAR : 1; + unsigned char TMTR : 1; +#endif + } BIT; + } TMC3; + char wk5[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMTSTS : 1; + unsigned char TMTRF : 2; + unsigned char TMTRM : 1; + unsigned char TMTARM : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char TMTARM : 1; + unsigned char TMTRM : 1; + unsigned char TMTRF : 2; + unsigned char TMTSTS : 1; +#endif + } BIT; + } TMSTS3; + char wk6[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMTRSTS0 : 1; + unsigned short TMTRSTS1 : 1; + unsigned short TMTRSTS2 : 1; + unsigned short TMTRSTS3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMTRSTS3 : 1; + unsigned short TMTRSTS2 : 1; + unsigned short TMTRSTS1 : 1; + unsigned short TMTRSTS0 : 1; +#endif + } BIT; + } TMTRSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMTCSTS0 : 1; + unsigned short TMTCSTS1 : 1; + unsigned short TMTCSTS2 : 1; + unsigned short TMTCSTS3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMTCSTS3 : 1; + unsigned short TMTCSTS2 : 1; + unsigned short TMTCSTS1 : 1; + unsigned short TMTCSTS0 : 1; +#endif + } BIT; + } TMTCSTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMTASTS0 : 1; + unsigned short TMTASTS1 : 1; + unsigned short TMTASTS2 : 1; + unsigned short TMTASTS3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMTASTS3 : 1; + unsigned short TMTASTS2 : 1; + unsigned short TMTASTS1 : 1; + unsigned short TMTASTS0 : 1; +#endif + } BIT; + } TMTASTS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMIE0 : 1; + unsigned short TMIE1 : 1; + unsigned short TMIE2 : 1; + unsigned short TMIE3 : 1; + unsigned short : 12; +#else + unsigned short : 12; + unsigned short TMIE3 : 1; + unsigned short TMIE2 : 1; + unsigned short TMIE1 : 1; + unsigned short TMIE0 : 1; +#endif + } BIT; + } TMIEC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short THLE : 1; + unsigned short : 7; + unsigned short THLIE : 1; + unsigned short THLIM : 1; + unsigned short THLDTE : 1; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short THLDTE : 1; + unsigned short THLIM : 1; + unsigned short THLIE : 1; + unsigned short : 7; + unsigned short THLE : 1; +#endif + } BIT; + } THLCC0; + char wk7[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short THLEMP : 1; + unsigned short THLFLL : 1; + unsigned short THLELT : 1; + unsigned short THLIF : 1; + unsigned short : 4; + unsigned short THLMC : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short THLMC : 4; + unsigned short : 4; + unsigned short THLIF : 1; + unsigned short THLELT : 1; + unsigned short THLFLL : 1; + unsigned short THLEMP : 1; +#endif + } BIT; + } THLSTS0; + char wk8[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short THLPC : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short THLPC : 8; +#endif + } BIT; + } THLPCTR0; + char wk9[602]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFID : 16; +#else + unsigned short CFID : 16; +#endif + } BIT; + } CFIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFID : 13; + unsigned short THLEN : 1; + unsigned short CFRTR : 1; + unsigned short CFIDE : 1; +#else + unsigned short CFIDE : 1; + unsigned short CFRTR : 1; + unsigned short THLEN : 1; + unsigned short CFID : 13; +#endif + } BIT; + } CFIDH0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFTS : 16; +#else + unsigned short CFTS : 16; +#endif + } BIT; + } CFTS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFPTR : 12; + unsigned short CFDLC : 4; +#else + unsigned short CFDLC : 4; + unsigned short CFPTR : 12; +#endif + } BIT; + } CFPTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB0 : 8; + unsigned short CFDB1 : 8; +#else + unsigned short CFDB1 : 8; + unsigned short CFDB0 : 8; +#endif + } BIT; + } CFDF00; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB2 : 8; + unsigned short CFDB3 : 8; +#else + unsigned short CFDB3 : 8; + unsigned short CFDB2 : 8; +#endif + } BIT; + } CFDF10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB4 : 8; + unsigned short CFDB5 : 8; +#else + unsigned short CFDB5 : 8; + unsigned short CFDB4 : 8; +#endif + } BIT; + } CFDF20; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CFDB6 : 8; + unsigned short CFDB7 : 8; +#else + unsigned short CFDB7 : 8; + unsigned short CFDB6 : 8; +#endif + } BIT; + } CFDF30; + char wk10[16]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH0; + char wk11[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF00; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF10; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF20; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF30; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH1; + char wk12[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF01; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF11; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF21; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF31; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH2; + char wk13[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF02; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF12; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF22; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF32; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 16; +#else + unsigned short TMID : 16; +#endif + } BIT; + } TMIDL3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMID : 13; + unsigned short THLEN : 1; + unsigned short TMRTR : 1; + unsigned short TMIDE : 1; +#else + unsigned short TMIDE : 1; + unsigned short TMRTR : 1; + unsigned short THLEN : 1; + unsigned short TMID : 13; +#endif + } BIT; + } TMIDH3; + char wk14[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMPTR : 8; + unsigned short : 4; + unsigned short TMDLC : 4; +#else + unsigned short TMDLC : 4; + unsigned short : 4; + unsigned short TMPTR : 8; +#endif + } BIT; + } TMPTR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB0 : 8; + unsigned short TMDB1 : 8; +#else + unsigned short TMDB1 : 8; + unsigned short TMDB0 : 8; +#endif + } BIT; + } TMDF03; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB2 : 8; + unsigned short TMDB3 : 8; +#else + unsigned short TMDB3 : 8; + unsigned short TMDB2 : 8; +#endif + } BIT; + } TMDF13; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB4 : 8; + unsigned short TMDB5 : 8; +#else + unsigned short TMDB5 : 8; + unsigned short TMDB4 : 8; +#endif + } BIT; + } TMDF23; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TMDB6 : 8; + unsigned short TMDB7 : 8; +#else + unsigned short TMDB7 : 8; + unsigned short TMDB6 : 8; +#endif + } BIT; + } TMDF33; + char wk15[64]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BT : 2; + unsigned short : 1; + unsigned short BN : 2; + unsigned short : 3; + unsigned short TID : 8; +#else + unsigned short TID : 8; + unsigned short : 3; + unsigned short BN : 2; + unsigned short : 1; + unsigned short BT : 2; +#endif + } BIT; + } THLACC0; +}; + +struct st_cmpb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0INI : 1; + unsigned char : 3; + unsigned char CPB1INI : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1INI : 1; + unsigned char : 3; + unsigned char CPB0INI : 1; +#endif + } BIT; + } CPBCNT1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0WCP : 1; + unsigned char : 3; + unsigned char CPB1WCP : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1WCP : 1; + unsigned char : 3; + unsigned char CPB0WCP : 1; +#endif + } BIT; + } CPBCNT2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CPB0OUT : 1; + unsigned char : 3; + unsigned char CPB1OUT : 1; +#else + unsigned char CPB1OUT : 1; + unsigned char : 3; + unsigned char CPB0OUT : 1; + unsigned char : 3; +#endif + } BIT; + } CPBFLG; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0INTEN : 1; + unsigned char CPB0INTEG : 1; + unsigned char CPB0INTPL : 1; + unsigned char : 1; + unsigned char CPB1INTEN : 1; + unsigned char CPB1INTEG : 1; + unsigned char CPB1INTPL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CPB1INTPL : 1; + unsigned char CPB1INTEG : 1; + unsigned char CPB1INTEN : 1; + unsigned char : 1; + unsigned char CPB0INTPL : 1; + unsigned char CPB0INTEG : 1; + unsigned char CPB0INTEN : 1; +#endif + } BIT; + } CPBINT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0FEN : 1; + unsigned char : 1; + unsigned char CPB0F : 2; + unsigned char CPB1FEN : 1; + unsigned char : 1; + unsigned char CPB1F : 2; +#else + unsigned char CPB1F : 2; + unsigned char : 1; + unsigned char CPB1FEN : 1; + unsigned char CPB0F : 2; + unsigned char : 1; + unsigned char CPB0FEN : 1; +#endif + } BIT; + } CPBF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPBSPDMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CPBSPDMD : 1; +#endif + } BIT; + } CPBMD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0VRF : 1; + unsigned char : 3; + unsigned char CPB1VRF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB1VRF : 1; + unsigned char : 3; + unsigned char CPB0VRF : 1; +#endif + } BIT; + } CPBREF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB0OE : 1; + unsigned char CPB0OP : 1; + unsigned char : 2; + unsigned char CPB1OE : 1; + unsigned char CPB1OP : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CPB1OP : 1; + unsigned char CPB1OE : 1; + unsigned char : 2; + unsigned char CPB0OP : 1; + unsigned char CPB0OE : 1; +#endif + } BIT; + } CPBOCR; + char wk0[24]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2INI : 1; + unsigned char : 3; + unsigned char CPB3INI : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB3INI : 1; + unsigned char : 3; + unsigned char CPB2INI : 1; +#endif + } BIT; + } CPB1CNT1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2WCP : 1; + unsigned char : 3; + unsigned char CPB3WCP : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB3WCP : 1; + unsigned char : 3; + unsigned char CPB2WCP : 1; +#endif + } BIT; + } CPB1CNT2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CPB2OUT : 1; + unsigned char : 3; + unsigned char CPB3OUT : 1; +#else + unsigned char CPB3OUT : 1; + unsigned char : 3; + unsigned char CPB2OUT : 1; + unsigned char : 3; +#endif + } BIT; + } CPB1FLG; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2INTEN : 1; + unsigned char CPB2INTEG : 1; + unsigned char CPB2INTPL : 1; + unsigned char : 1; + unsigned char CPB3INTEN : 1; + unsigned char CPB3INTEG : 1; + unsigned char CPB3INTPL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CPB3INTPL : 1; + unsigned char CPB3INTEG : 1; + unsigned char CPB3INTEN : 1; + unsigned char : 1; + unsigned char CPB2INTPL : 1; + unsigned char CPB2INTEG : 1; + unsigned char CPB2INTEN : 1; +#endif + } BIT; + } CPB1INT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2FEN : 1; + unsigned char : 1; + unsigned char CPB2F : 2; + unsigned char CPB3FEN : 1; + unsigned char : 1; + unsigned char CPB3F : 2; +#else + unsigned char CPB3F : 2; + unsigned char : 1; + unsigned char CPB3FEN : 1; + unsigned char CPB2F : 2; + unsigned char : 1; + unsigned char CPB2FEN : 1; +#endif + } BIT; + } CPB1F; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB1SPDMD : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CPB1SPDMD : 1; +#endif + } BIT; + } CPB1MD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2VRF : 1; + unsigned char : 3; + unsigned char CPB3VRF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CPB3VRF : 1; + unsigned char : 3; + unsigned char CPB2VRF : 1; +#endif + } BIT; + } CPB1REF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CPB2OE : 1; + unsigned char CPB2OP : 1; + unsigned char : 2; + unsigned char CPB3OE : 1; + unsigned char CPB3OP : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CPB3OP : 1; + unsigned char CPB3OE : 1; + unsigned char : 2; + unsigned char CPB2OP : 1; + unsigned char CPB2OE : 1; +#endif + } BIT; + } CPB1OCR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR0 : 1; + unsigned short STR1 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR1 : 1; + unsigned short STR0 : 1; +#endif + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR2 : 1; + unsigned short STR3 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR3 : 1; + unsigned short STR2 : 1; +#endif + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 4; + unsigned short CMIE : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMIE : 1; + unsigned short : 4; + unsigned short CKS : 2; +#endif + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char GPS : 2; + unsigned char LMS : 1; + unsigned char : 4; + unsigned char DORCLR : 1; +#else + unsigned char DORCLR : 1; + unsigned char : 4; + unsigned char LMS : 1; + unsigned char GPS : 2; +#endif + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_ctsu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSTRT : 1; + unsigned char CTSUCAP : 1; + unsigned char CTSUSNZ : 1; + unsigned char : 1; + unsigned char CTSUINIT : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CTSUINIT : 1; + unsigned char : 1; + unsigned char CTSUSNZ : 1; + unsigned char CTSUCAP : 1; + unsigned char CTSUSTRT : 1; +#endif + } BIT; + } CTSUCR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUPON : 1; + unsigned char CTSUCSW : 1; + unsigned char CTSUATUNE0 : 1; + unsigned char CTSUATUNE1 : 1; + unsigned char CTSUCLK : 2; + unsigned char CTSUMD : 2; +#else + unsigned char CTSUMD : 2; + unsigned char CTSUCLK : 2; + unsigned char CTSUATUNE1 : 1; + unsigned char CTSUATUNE0 : 1; + unsigned char CTSUCSW : 1; + unsigned char CTSUPON : 1; +#endif + } BIT; + } CTSUCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUPRRATIO : 4; + unsigned char CTSUPRMODE : 2; + unsigned char CTSUSOFF : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CTSUSOFF : 1; + unsigned char CTSUPRMODE : 2; + unsigned char CTSUPRRATIO : 4; +#endif + } BIT; + } CTSUSDPRS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSST : 8; +#else + unsigned char CTSUSST : 8; +#endif + } BIT; + } CTSUSST; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUMCH0 : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CTSUMCH0 : 6; +#endif + } BIT; + } CTSUMCH0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUMCH1 : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CTSUMCH1 : 6; +#endif + } BIT; + } CTSUMCH1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC00 : 1; + unsigned char CTSUCHAC01 : 1; + unsigned char CTSUCHAC02 : 1; + unsigned char CTSUCHAC03 : 1; + unsigned char CTSUCHAC04 : 1; + unsigned char CTSUCHAC05 : 1; + unsigned char CTSUCHAC06 : 1; + unsigned char CTSUCHAC07 : 1; +#else + unsigned char CTSUCHAC07 : 1; + unsigned char CTSUCHAC06 : 1; + unsigned char CTSUCHAC05 : 1; + unsigned char CTSUCHAC04 : 1; + unsigned char CTSUCHAC03 : 1; + unsigned char CTSUCHAC02 : 1; + unsigned char CTSUCHAC01 : 1; + unsigned char CTSUCHAC00 : 1; +#endif + } BIT; + } CTSUCHAC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC10 : 1; + unsigned char CTSUCHAC11 : 1; + unsigned char CTSUCHAC12 : 1; + unsigned char CTSUCHAC13 : 1; + unsigned char CTSUCHAC14 : 1; + unsigned char CTSUCHAC15 : 1; + unsigned char CTSUCHAC16 : 1; + unsigned char CTSUCHAC17 : 1; +#else + unsigned char CTSUCHAC17 : 1; + unsigned char CTSUCHAC16 : 1; + unsigned char CTSUCHAC15 : 1; + unsigned char CTSUCHAC14 : 1; + unsigned char CTSUCHAC13 : 1; + unsigned char CTSUCHAC12 : 1; + unsigned char CTSUCHAC11 : 1; + unsigned char CTSUCHAC10 : 1; +#endif + } BIT; + } CTSUCHAC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC20 : 1; + unsigned char CTSUCHAC21 : 1; + unsigned char CTSUCHAC22 : 1; + unsigned char CTSUCHAC23 : 1; + unsigned char CTSUCHAC24 : 1; + unsigned char CTSUCHAC25 : 1; + unsigned char CTSUCHAC26 : 1; + unsigned char CTSUCHAC27 : 1; +#else + unsigned char CTSUCHAC27 : 1; + unsigned char CTSUCHAC26 : 1; + unsigned char CTSUCHAC25 : 1; + unsigned char CTSUCHAC24 : 1; + unsigned char CTSUCHAC23 : 1; + unsigned char CTSUCHAC22 : 1; + unsigned char CTSUCHAC21 : 1; + unsigned char CTSUCHAC20 : 1; +#endif + } BIT; + } CTSUCHAC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC30 : 1; + unsigned char CTSUCHAC31 : 1; + unsigned char CTSUCHAC32 : 1; + unsigned char CTSUCHAC33 : 1; + unsigned char CTSUCHAC34 : 1; + unsigned char CTSUCHAC35 : 1; + unsigned char CTSUCHAC36 : 1; + unsigned char CTSUCHAC37 : 1; +#else + unsigned char CTSUCHAC37 : 1; + unsigned char CTSUCHAC36 : 1; + unsigned char CTSUCHAC35 : 1; + unsigned char CTSUCHAC34 : 1; + unsigned char CTSUCHAC33 : 1; + unsigned char CTSUCHAC32 : 1; + unsigned char CTSUCHAC31 : 1; + unsigned char CTSUCHAC30 : 1; +#endif + } BIT; + } CTSUCHAC3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHAC40 : 1; + unsigned char CTSUCHAC41 : 1; + unsigned char CTSUCHAC42 : 1; + unsigned char CTSUCHAC43 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CTSUCHAC43 : 1; + unsigned char CTSUCHAC42 : 1; + unsigned char CTSUCHAC41 : 1; + unsigned char CTSUCHAC40 : 1; +#endif + } BIT; + } CTSUCHAC4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC00 : 1; + unsigned char CTSUCHTRC01 : 1; + unsigned char CTSUCHTRC02 : 1; + unsigned char CTSUCHTRC03 : 1; + unsigned char CTSUCHTRC04 : 1; + unsigned char CTSUCHTRC05 : 1; + unsigned char CTSUCHTRC06 : 1; + unsigned char CTSUCHTRC07 : 1; +#else + unsigned char CTSUCHTRC07 : 1; + unsigned char CTSUCHTRC06 : 1; + unsigned char CTSUCHTRC05 : 1; + unsigned char CTSUCHTRC04 : 1; + unsigned char CTSUCHTRC03 : 1; + unsigned char CTSUCHTRC02 : 1; + unsigned char CTSUCHTRC01 : 1; + unsigned char CTSUCHTRC00 : 1; +#endif + } BIT; + } CTSUCHTRC0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC10 : 1; + unsigned char CTSUCHTRC11 : 1; + unsigned char CTSUCHTRC12 : 1; + unsigned char CTSUCHTRC13 : 1; + unsigned char CTSUCHTRC14 : 1; + unsigned char CTSUCHTRC15 : 1; + unsigned char CTSUCHTRC16 : 1; + unsigned char CTSUCHTRC17 : 1; +#else + unsigned char CTSUCHTRC17 : 1; + unsigned char CTSUCHTRC16 : 1; + unsigned char CTSUCHTRC15 : 1; + unsigned char CTSUCHTRC14 : 1; + unsigned char CTSUCHTRC13 : 1; + unsigned char CTSUCHTRC12 : 1; + unsigned char CTSUCHTRC11 : 1; + unsigned char CTSUCHTRC10 : 1; +#endif + } BIT; + } CTSUCHTRC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC20 : 1; + unsigned char CTSUCHTRC21 : 1; + unsigned char CTSUCHTRC22 : 1; + unsigned char CTSUCHTRC23 : 1; + unsigned char CTSUCHTRC24 : 1; + unsigned char CTSUCHTRC25 : 1; + unsigned char CTSUCHTRC26 : 1; + unsigned char CTSUCHTRC27 : 1; +#else + unsigned char CTSUCHTRC27 : 1; + unsigned char CTSUCHTRC26 : 1; + unsigned char CTSUCHTRC25 : 1; + unsigned char CTSUCHTRC24 : 1; + unsigned char CTSUCHTRC23 : 1; + unsigned char CTSUCHTRC22 : 1; + unsigned char CTSUCHTRC21 : 1; + unsigned char CTSUCHTRC20 : 1; +#endif + } BIT; + } CTSUCHTRC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC30 : 1; + unsigned char CTSUCHTRC31 : 1; + unsigned char CTSUCHTRC32 : 1; + unsigned char CTSUCHTRC33 : 1; + unsigned char CTSUCHTRC34 : 1; + unsigned char CTSUCHTRC35 : 1; + unsigned char CTSUCHTRC36 : 1; + unsigned char CTSUCHTRC37 : 1; +#else + unsigned char CTSUCHTRC37 : 1; + unsigned char CTSUCHTRC36 : 1; + unsigned char CTSUCHTRC35 : 1; + unsigned char CTSUCHTRC34 : 1; + unsigned char CTSUCHTRC33 : 1; + unsigned char CTSUCHTRC32 : 1; + unsigned char CTSUCHTRC31 : 1; + unsigned char CTSUCHTRC30 : 1; +#endif + } BIT; + } CTSUCHTRC3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUCHTRC40 : 1; + unsigned char CTSUCHTRC41 : 1; + unsigned char CTSUCHTRC42 : 1; + unsigned char CTSUCHTRC43 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char CTSUCHTRC43 : 1; + unsigned char CTSUCHTRC42 : 1; + unsigned char CTSUCHTRC41 : 1; + unsigned char CTSUCHTRC40 : 1; +#endif + } BIT; + } CTSUCHTRC4; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSSMOD : 2; + unsigned char : 2; + unsigned char CTSUSSCNT : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CTSUSSCNT : 2; + unsigned char : 2; + unsigned char CTSUSSMOD : 2; +#endif + } BIT; + } CTSUDCLKC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CTSUSTC : 3; + unsigned char : 1; + unsigned char CTSUDTSR : 1; + unsigned char CTSUSOVF : 1; + unsigned char CTSUROVF : 1; + unsigned char CTSUPS : 1; +#else + unsigned char CTSUPS : 1; + unsigned char CTSUROVF : 1; + unsigned char CTSUSOVF : 1; + unsigned char CTSUDTSR : 1; + unsigned char : 1; + unsigned char CTSUSTC : 3; +#endif + } BIT; + } CTSUST; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CTSUSSDIV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short CTSUSSDIV : 4; + unsigned short : 8; +#endif + } BIT; + } CTSUSSC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSUSO : 10; + unsigned short CTSUSNUM : 6; +#else + unsigned short CTSUSNUM : 6; + unsigned short CTSUSO : 10; +#endif + } BIT; + } CTSUSO0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSURICOA : 8; + unsigned short CTSUSDPA : 5; + unsigned short CTSUICOG : 2; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short CTSUICOG : 2; + unsigned short CTSUSDPA : 5; + unsigned short CTSURICOA : 8; +#endif + } BIT; + } CTSUSO1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSUSC : 16; +#else + unsigned short CTSUSC : 16; +#endif + } BIT; + } CTSUSC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CTSURC : 16; +#else + unsigned short CTSURC : 16; +#endif + } BIT; + } CTSURC; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short CTSUICOMP : 1; +#else + unsigned short CTSUICOMP : 1; + unsigned short : 15; +#endif + } BIT; + } CTSUERRS; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char DAOE0 : 1; + unsigned char DAOE1 : 1; +#else + unsigned char DAOE1 : 1; + unsigned char DAOE0 : 1; + unsigned char : 6; +#endif + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DPSEL : 1; +#else + unsigned char DPSEL : 1; + unsigned char : 7; +#endif + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char DAADST : 1; +#else + unsigned char DAADST : 1; + unsigned char : 7; +#endif + } BIT; + } DAADSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char REF : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char REF : 3; +#endif + } BIT; + } DAVREFCR; +}; + +struct st_dmac { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DMST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DMST : 1; +#endif + } BIT; + } DMAST; +}; + +struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif + } BIT; + } DMCSL; +}; + +struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DCTG : 2; + unsigned short : 6; + unsigned short SZ : 2; + unsigned short : 2; + unsigned short DTS : 2; + unsigned short MD : 2; +#else + unsigned short MD : 2; + unsigned short DTS : 2; + unsigned short : 2; + unsigned short SZ : 2; + unsigned short : 6; + unsigned short DCTG : 2; +#endif + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DARIE : 1; + unsigned char SARIE : 1; + unsigned char RPTIE : 1; + unsigned char ESIE : 1; + unsigned char DTIE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char DTIE : 1; + unsigned char ESIE : 1; + unsigned char RPTIE : 1; + unsigned char SARIE : 1; + unsigned char DARIE : 1; +#endif + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DARA : 5; + unsigned short : 1; + unsigned short DM : 2; + unsigned short SARA : 5; + unsigned short : 1; + unsigned short SM : 2; +#else + unsigned short SM : 2; + unsigned short : 1; + unsigned short SARA : 5; + unsigned short DM : 2; + unsigned short : 1; + unsigned short DARA : 5; +#endif + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTE : 1; +#endif + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWREQ : 1; + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char CLRS : 1; + unsigned char : 3; + unsigned char SWREQ : 1; +#endif + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESIF : 1; + unsigned char : 3; + unsigned char DTIF : 1; + unsigned char : 2; + unsigned char ACT : 1; +#else + unsigned char ACT : 1; + unsigned char : 2; + unsigned char DTIF : 1; + unsigned char : 3; + unsigned char ESIF : 1; +#endif + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DISEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DISEL : 1; +#endif + } BIT; + } DMCSL; +}; + +struct st_doc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OMS : 2; + unsigned char DCSEL : 1; + unsigned char : 1; + unsigned char DOPCIE : 1; + unsigned char DOPCF : 1; + unsigned char DOPCFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DOPCFCL : 1; + unsigned char DOPCF : 1; + unsigned char DOPCIE : 1; + unsigned char : 1; + unsigned char DCSEL : 1; + unsigned char OMS : 2; +#endif + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char RRS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char RRS : 1; + unsigned char : 4; +#endif + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SHORT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SHORT : 1; +#endif + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCST : 1; +#endif + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VECN : 8; + unsigned short : 7; + unsigned short ACT : 1; +#else + unsigned short ACT : 1; + unsigned short : 7; + unsigned short VECN : 8; +#endif + } BIT; + } DTCSTS; +}; + +struct st_elc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ELCON : 1; +#else + unsigned char ELCON : 1; + unsigned char : 7; +#endif + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELS : 8; +#else + unsigned char ELS : 8; +#endif + } BIT; + } ELSR[30]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char MTU1MD : 2; + unsigned char MTU2MD : 2; + unsigned char MTU3MD : 2; +#else + unsigned char MTU3MD : 2; + unsigned char MTU2MD : 2; + unsigned char MTU1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MTU4MD : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MTU4MD : 2; +#endif + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char CMT1MD : 2; + unsigned char LPTMD : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LPTMD : 2; + unsigned char CMT1MD : 2; + unsigned char : 2; +#endif + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMR0MD : 2; + unsigned char : 2; + unsigned char TMR2MD : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char TMR2MD : 2; + unsigned char : 2; + unsigned char TMR0MD : 2; +#endif + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGR0 : 1; + unsigned char PGR1 : 1; + unsigned char PGR2 : 1; + unsigned char PGR3 : 1; + unsigned char PGR4 : 1; + unsigned char PGR5 : 1; + unsigned char PGR6 : 1; + unsigned char PGR7 : 1; +#else + unsigned char PGR7 : 1; + unsigned char PGR6 : 1; + unsigned char PGR5 : 1; + unsigned char PGR4 : 1; + unsigned char PGR3 : 1; + unsigned char PGR2 : 1; + unsigned char PGR1 : 1; + unsigned char PGR0 : 1; +#endif + } BIT; + } PGR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PGCI : 2; + unsigned char PGCOVE : 1; + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PGCO : 3; + unsigned char : 1; + unsigned char PGCOVE : 1; + unsigned char PGCI : 2; +#endif + } BIT; + } PGC2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PDBF0 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF7 : 1; +#else + unsigned char PDBF7 : 1; + unsigned char PDBF6 : 1; + unsigned char PDBF5 : 1; + unsigned char PDBF4 : 1; + unsigned char PDBF3 : 1; + unsigned char PDBF2 : 1; + unsigned char PDBF1 : 1; + unsigned char PDBF0 : 1; +#endif + } BIT; + } PDBF2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSB : 3; + unsigned char PSP : 2; + unsigned char PSM : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSM : 2; + unsigned char PSP : 2; + unsigned char PSB : 3; +#endif + } BIT; + } PEL3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEG : 1; + unsigned char : 5; + unsigned char WE : 1; + unsigned char WI : 1; +#else + unsigned char WI : 1; + unsigned char WE : 1; + unsigned char : 5; + unsigned char SEG : 1; +#endif + } BIT; + } ELSEGR; +}; + +struct st_flash { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DFLEN : 1; +#endif + } BIT; + } DFLCTL; + char wk0[111]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char FMS0 : 1; + unsigned char : 1; + unsigned char RPDIS : 1; + unsigned char FMS1 : 1; + unsigned char : 1; + unsigned char LVPE : 1; + unsigned char FMS2 : 1; +#else + unsigned char FMS2 : 1; + unsigned char LVPE : 1; + unsigned char : 1; + unsigned char FMS1 : 1; + unsigned char RPDIS : 1; + unsigned char : 1; + unsigned char FMS0 : 1; + unsigned char : 1; +#endif + } BIT; + } FPMCR; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EXS : 1; +#endif + } BIT; + } FASR; + char wk2[3]; + unsigned short FSARL; + char wk3[6]; + unsigned short FSARH; + char wk4[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD : 4; + unsigned char : 2; + unsigned char STOP : 1; + unsigned char OPST : 1; +#else + unsigned char OPST : 1; + unsigned char STOP : 1; + unsigned char : 2; + unsigned char CMD : 4; +#endif + } BIT; + } FCR; + char wk5[3]; + unsigned short FEARL; + char wk6[6]; + unsigned short FEARH; + char wk7[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FRESET : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char FRESET : 1; +#endif + } BIT; + } FRESETR; + char wk8[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char FRDY : 1; + unsigned char EXRDY : 1; +#else + unsigned char EXRDY : 1; + unsigned char FRDY : 1; + unsigned char : 6; +#endif + } BIT; + } FSTATR1; + char wk9[3]; + unsigned short FWB0; + char wk10[6]; + unsigned short FWB1; + char wk11[6]; + unsigned short FWB2; + char wk12[2]; + unsigned short FWB3; + char wk13[58]; + unsigned char FPR; + char wk14[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PERR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PERR : 1; +#endif + } BIT; + } FPSR; + char wk15[59]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short SASMF : 1; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short SASMF : 1; + unsigned short : 8; +#endif + } BIT; + } FSCMR; + char wk16[6]; + unsigned short FAWSMR; + char wk17[6]; + unsigned short FAWEMR; + char wk18[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PCKA : 5; + unsigned char : 1; + unsigned char SAS : 2; +#else + unsigned char SAS : 2; + unsigned char : 1; + unsigned char PCKA : 5; +#endif + } BIT; + } FISR; + char wk19[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMD : 3; + unsigned char : 4; + unsigned char OPST : 1; +#else + unsigned char OPST : 1; + unsigned char : 4; + unsigned char CMD : 3; +#endif + } BIT; + } FEXCR; + char wk20[3]; + unsigned short FEAML; + char wk21[6]; + unsigned short FEAMH; + char wk22[6]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ERERR : 1; + unsigned char PRGERR : 1; + unsigned char : 1; + unsigned char BCERR : 1; + unsigned char ILGLERR : 1; + unsigned char EILGLERR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char EILGLERR : 1; + unsigned char ILGLERR : 1; + unsigned char BCERR : 1; + unsigned char : 1; + unsigned char PRGERR : 1; + unsigned char ERERR : 1; +#endif + } BIT; + } FSTATR0; + char wk23[15809]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FENTRY0 : 1; + unsigned short : 6; + unsigned short FENTRYD : 1; + unsigned short FEKEY : 8; +#else + unsigned short FEKEY : 8; + unsigned short FENTRYD : 1; + unsigned short : 6; + unsigned short FENTRY0 : 1; +#endif + } BIT; + } FENTRYR; +}; + +struct st_flashconst { + unsigned long UIDR0; + unsigned long UIDR1; + unsigned long UIDR2; + unsigned long UIDR3; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IR : 1; +#endif + } BIT; + } IR[254]; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCE : 1; +#endif + } BIT; + } DTCER[253]; + char wk1[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IEN0 : 1; + unsigned char IEN1 : 1; + unsigned char IEN2 : 1; + unsigned char IEN3 : 1; + unsigned char IEN4 : 1; + unsigned char IEN5 : 1; + unsigned char IEN6 : 1; + unsigned char IEN7 : 1; +#else + unsigned char IEN7 : 1; + unsigned char IEN6 : 1; + unsigned char IEN5 : 1; + unsigned char IEN4 : 1; + unsigned char IEN3 : 1; + unsigned char IEN2 : 1; + unsigned char IEN1 : 1; + unsigned char IEN0 : 1; +#endif + } BIT; + } IER[32]; + char wk2[192]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT : 1; +#endif + } BIT; + } SWINTR; + char wk3[15]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FVCT : 8; + unsigned short : 7; + unsigned short FIEN : 1; +#else + unsigned short FIEN : 1; + unsigned short : 7; + unsigned short FVCT : 8; +#endif + } BIT; + } FIR; + char wk4[14]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IPR : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IPR : 4; +#endif + } BIT; + } IPR[251]; + char wk5[5]; + unsigned char DMRSR0; + char wk6[3]; + unsigned char DMRSR1; + char wk7[3]; + unsigned char DMRSR2; + char wk8[3]; + unsigned char DMRSR3; + char wk9[243]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRQMD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IRQMD : 2; + unsigned char : 2; +#endif + } BIT; + } IRQCR[8]; + char wk10[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN0 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN7 : 1; +#else + unsigned char FLTEN7 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN0 : 1; +#endif + } BIT; + } IRQFLTE0; + char wk11[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL0 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL7 : 2; +#else + unsigned short FCLKSEL7 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL0 : 2; +#endif + } BIT; + } IRQFLTC0; + char wk12[106]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIST : 1; + unsigned char OSTST : 1; + unsigned char WDTST : 1; + unsigned char IWDTST : 1; + unsigned char LVD1ST : 1; + unsigned char LVD2ST : 1; + unsigned char VBATST : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char VBATST : 1; + unsigned char LVD2ST : 1; + unsigned char LVD1ST : 1; + unsigned char IWDTST : 1; + unsigned char WDTST : 1; + unsigned char OSTST : 1; + unsigned char NMIST : 1; +#endif + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIEN : 1; + unsigned char OSTEN : 1; + unsigned char WDTEN : 1; + unsigned char IWDTEN : 1; + unsigned char LVD1EN : 1; + unsigned char LVD2EN : 1; + unsigned char VBATEN : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char VBATEN : 1; + unsigned char LVD2EN : 1; + unsigned char LVD1EN : 1; + unsigned char IWDTEN : 1; + unsigned char WDTEN : 1; + unsigned char OSTEN : 1; + unsigned char NMIEN : 1; +#endif + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMICLR : 1; + unsigned char OSTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char IWDTCLR : 1; + unsigned char LVD1CLR : 1; + unsigned char LVD2CLR : 1; + unsigned char VBATCLR : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char VBATCLR : 1; + unsigned char LVD2CLR : 1; + unsigned char LVD1CLR : 1; + unsigned char IWDTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char OSTCLR : 1; + unsigned char NMICLR : 1; +#endif + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char NMIMD : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NMIMD : 1; + unsigned char : 3; +#endif + } BIT; + } NMICR; + char wk13[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFLTEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char NFLTEN : 1; +#endif + } BIT; + } NMIFLTE; + char wk14[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCLKSEL : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char NFCLKSEL : 2; +#endif + } BIT; + } NMIFLTC; +}; + +struct st_irda { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRRXINV : 1; + unsigned char IRTXINV : 1; + unsigned char IRCKS : 3; + unsigned char IRE : 1; +#else + unsigned char IRE : 1; + unsigned char IRCKS : 3; + unsigned char IRTXINV : 1; + unsigned char IRRXINV : 1; + unsigned char : 2; +#endif + } BIT; + } IRCR; +}; + +struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char SLCSTP : 1; +#else + unsigned char SLCSTP : 1; + unsigned char : 7; +#endif + } BIT; + } IWDTCSTPR; +}; + +struct st_lpt { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTPSSEL : 3; + unsigned char : 1; + unsigned char LPCNTCKSEL : 1; + unsigned char : 1; + unsigned char LPCMRE0 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LPCMRE0 : 1; + unsigned char : 1; + unsigned char LPCNTCKSEL : 1; + unsigned char : 1; + unsigned char LPCNTPSSEL : 3; +#endif + } BIT; + } LPTCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LPCNTSTP : 1; +#endif + } BIT; + } LPTCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LPCNTEN : 1; + unsigned char LPCNTRST : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LPCNTRST : 1; + unsigned char LPCNTEN : 1; +#endif + } BIT; + } LPTCR3; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LPCNTPRD : 16; +#else + unsigned short LPCNTPRD : 16; +#endif + } BIT; + } LPTPRD; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LPCMR0 : 16; +#else + unsigned short LPCMR0 : 16; +#endif + } BIT; + } LPCMR0; + char wk2[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 15; + unsigned short LPWKUPEN : 1; +#else + unsigned short LPWKUPEN : 1; + unsigned short : 15; +#endif + } BIT; + } LPWUCR; +}; + +struct st_mpc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS0E : 1; + unsigned char CS1E : 1; + unsigned char CS2E : 1; + unsigned char CS3E : 1; + unsigned char CS4E : 1; + unsigned char CS5E : 1; + unsigned char CS6E : 1; + unsigned char CS7E : 1; +#else + unsigned char CS7E : 1; + unsigned char CS6E : 1; + unsigned char CS5E : 1; + unsigned char CS4E : 1; + unsigned char CS3E : 1; + unsigned char CS2E : 1; + unsigned char CS1E : 1; + unsigned char CS0E : 1; +#endif + } BIT; + } PFCSE; + char wk0[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A8E : 1; + unsigned char A9E : 1; + unsigned char A10E : 1; + unsigned char A11E : 1; + unsigned char A12E : 1; + unsigned char A13E : 1; + unsigned char A14E : 1; + unsigned char A15E : 1; +#else + unsigned char A15E : 1; + unsigned char A14E : 1; + unsigned char A13E : 1; + unsigned char A12E : 1; + unsigned char A11E : 1; + unsigned char A10E : 1; + unsigned char A9E : 1; + unsigned char A8E : 1; +#endif + } BIT; + } PFAOE0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A16E : 1; + unsigned char A17E : 1; + unsigned char A18E : 1; + unsigned char A19E : 1; + unsigned char A20E : 1; + unsigned char A21E : 1; + unsigned char A22E : 1; + unsigned char A23E : 1; +#else + unsigned char A23E : 1; + unsigned char A22E : 1; + unsigned char A21E : 1; + unsigned char A20E : 1; + unsigned char A19E : 1; + unsigned char A18E : 1; + unsigned char A17E : 1; + unsigned char A16E : 1; +#endif + } BIT; + } PFAOE1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADRLE : 1; + unsigned char : 3; + unsigned char DHE : 1; + unsigned char : 1; + unsigned char WR1BC1E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char WR1BC1E : 1; + unsigned char : 1; + unsigned char DHE : 1; + unsigned char : 3; + unsigned char ADRLE : 1; +#endif + } BIT; + } PFBCR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WAITS : 2; + unsigned char ALEOE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char ALEOE : 1; + unsigned char WAITS : 2; +#endif + } BIT; + } PFBCR1; + char wk1[23]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PFSWE : 1; + unsigned char B0WI : 1; +#else + unsigned char B0WI : 1; + unsigned char PFSWE : 1; + unsigned char : 6; +#endif + } BIT; + } PWPR; + char wk2[35]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } P03PFS; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } P05PFS; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P07PFS; + char wk5[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P33PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } P34PFS; + char wk6[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 7; +#endif + } BIT; + } P47PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P52PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P53PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } P56PFS; + char wk7[33]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 2; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 2; + unsigned char PSEL : 5; +#endif + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PE7PFS; + char wk8[16]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PH0PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH1PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 1; + unsigned char PSEL : 5; +#endif + } BIT; + } PH2PFS; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PH3PFS; + char wk9[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PSEL : 5; +#endif + } BIT; + } PJ3PFS; +}; + +struct st_mpu { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE0; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE3; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE4; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE5; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE6; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long RSPN : 28; +#else + unsigned long RSPN : 28; + unsigned long : 4; +#endif + } BIT; + } RSPAGE7; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long V : 1; + unsigned long UAC : 3; + unsigned long REPN : 28; +#else + unsigned long REPN : 28; + unsigned long UAC : 3; + unsigned long V : 1; +#endif + } BIT; + } REPAGE7; + char wk0[192]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MPEN : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long MPEN : 1; +#endif + } BIT; + } MPEN; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UBAC : 3; + unsigned long : 28; +#else + unsigned long : 28; + unsigned long UBAC : 3; + unsigned long : 1; +#endif + } BIT; + } MPBAC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLR : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long CLR : 1; +#endif + } BIT; + } MPECLR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IMPER : 1; + unsigned long DMPER : 1; + unsigned long DRW : 1; + unsigned long : 29; +#else + unsigned long : 29; + unsigned long DRW : 1; + unsigned long DMPER : 1; + unsigned long IMPER : 1; +#endif + } BIT; + } MPESTS; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long DEA : 32; +#else + unsigned long DEA : 32; +#endif + } BIT; + } MPDEA; + char wk2[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SA : 32; +#else + unsigned long SA : 32; +#endif + } BIT; + } MPSA; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short S : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short S : 1; +#endif + } BIT; + } MPOPS; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short INV : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short INV : 1; +#endif + } BIT; + } MPOPI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACI : 3; + unsigned long : 12; + unsigned long HITI : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITI : 8; + unsigned long : 12; + unsigned long UHACI : 3; + unsigned long : 1; +#endif + } BIT; + } MHITI; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long UHACD : 3; + unsigned long : 12; + unsigned long HITD : 8; + unsigned long : 8; +#else + unsigned long : 8; + unsigned long HITD : 8; + unsigned long : 12; + unsigned long UHACD : 3; + unsigned long : 1; +#endif + } BIT; + } MHITD; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OE3B : 1; + unsigned char OE4A : 1; + unsigned char OE4B : 1; + unsigned char OE3D : 1; + unsigned char OE4C : 1; + unsigned char OE4D : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OE4D : 1; + unsigned char OE4C : 1; + unsigned char OE3D : 1; + unsigned char OE4B : 1; + unsigned char OE4A : 1; + unsigned char OE3B : 1; +#endif + } BIT; + } TOER; + char wk0[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UF : 1; + unsigned char VF : 1; + unsigned char WF : 1; + unsigned char FB : 1; + unsigned char P : 1; + unsigned char N : 1; + unsigned char BDC : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BDC : 1; + unsigned char N : 1; + unsigned char P : 1; + unsigned char FB : 1; + unsigned char WF : 1; + unsigned char VF : 1; + unsigned char UF : 1; +#endif + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLSP : 1; + unsigned char OLSN : 1; + unsigned char TOCS : 1; + unsigned char TOCL : 1; + unsigned char : 2; + unsigned char PSYE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PSYE : 1; + unsigned char : 2; + unsigned char TOCL : 1; + unsigned char TOCS : 1; + unsigned char OLSN : 1; + unsigned char OLSP : 1; +#endif + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char BF : 2; +#else + unsigned char BF : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOCR2; + char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + char wk3[12]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCOR : 3; + unsigned char T4VEN : 1; + unsigned char T3ACOR : 3; + unsigned char T3AEN : 1; +#else + unsigned char T3AEN : 1; + unsigned char T3ACOR : 3; + unsigned char T4VEN : 1; + unsigned char T4VCOR : 3; +#endif + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char T4VCNT : 3; + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char T3ACNT : 3; + unsigned char : 1; + unsigned char T4VCNT : 3; +#endif + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BTE : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char BTE : 2; +#endif + } BIT; + } TBTER; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TDER : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TDER : 1; +#endif + } BIT; + } TDER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OLS1P : 1; + unsigned char OLS1N : 1; + unsigned char OLS2P : 1; + unsigned char OLS2N : 1; + unsigned char OLS3P : 1; + unsigned char OLS3N : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char OLS3N : 1; + unsigned char OLS3P : 1; + unsigned char OLS2N : 1; + unsigned char OLS2P : 1; + unsigned char OLS1N : 1; + unsigned char OLS1P : 1; +#endif + } BIT; + } TOLBR; + char wk6[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WRE : 1; + unsigned char : 6; + unsigned char CCE : 1; +#else + unsigned char CCE : 1; + unsigned char : 6; + unsigned char WRE : 1; +#endif + } BIT; + } TWCR; + char wk7[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char : 3; + unsigned char CST3 : 1; + unsigned char CST4 : 1; +#else + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char : 3; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char : 3; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; +#else + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char : 3; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYR; + char wk8[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RWE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RWE : 1; +#endif + } BIT; + } TRWER; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[111]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char BFE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char BFE : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk1[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEE : 1; + unsigned char TGIEF : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TGIEF : 1; + unsigned char TGIEE : 1; +#endif + } BIT; + } TIER2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; +}; + +struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[238]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char I1AE : 1; + unsigned char I1BE : 1; + unsigned char I2AE : 1; + unsigned char I2BE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char I2BE : 1; + unsigned char I2AE : 1; + unsigned char I1BE : 1; + unsigned char I1AE : 1; +#endif + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[365]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 2; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char CCLR : 2; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 2; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 2; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk8[90]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; +}; + +struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + char wk2[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char : 1; + unsigned char TTGE2 : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char TTGE2 : 1; + unsigned char : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 7; +#endif + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TTSA : 1; + unsigned char TTSB : 1; + unsigned char TTSE : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TTSE : 1; + unsigned char TTSB : 1; + unsigned char TTSA : 1; +#endif + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ITB4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITA3AE : 1; + unsigned short DT4BE : 1; + unsigned short UT4BE : 1; + unsigned short DT4AE : 1; + unsigned short UT4AE : 1; + unsigned short : 6; + unsigned short BF : 2; +#else + unsigned short BF : 2; + unsigned short : 6; + unsigned short UT4AE : 1; + unsigned short DT4AE : 1; + unsigned short UT4BE : 1; + unsigned short DT4BE : 1; + unsigned short ITA3AE : 1; + unsigned short ITA4VE : 1; + unsigned short ITB3AE : 1; + unsigned short ITB4VE : 1; +#endif + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[72]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; +}; + +struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFUEN : 1; + unsigned char NFVEN : 1; + unsigned char NFWEN : 1; + unsigned char : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char : 1; + unsigned char NFWEN : 1; + unsigned char NFVEN : 1; + unsigned char NFUEN : 1; +#endif + } BIT; + } NFCR; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRU; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORU; + char wk3[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRV; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORV; + char wk5[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TPSC : 2; +#endif + } BIT; + } TCRW; + char wk6[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char IOC : 5; +#endif + } BIT; + } TIORW; + char wk7[11]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIE5W : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char TGIE5U : 1; + unsigned char TGIE5V : 1; + unsigned char TGIE5W : 1; +#endif + } BIT; + } TIER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CSTW5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTU5 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CSTU5 : 1; + unsigned char CSTV5 : 1; + unsigned char CSTW5 : 1; +#endif + } BIT; + } TSTR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCLR5W : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5U : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char CMPCLR5U : 1; + unsigned char CMPCLR5V : 1; + unsigned char CMPCLR5W : 1; +#endif + } BIT; + } TCNTCMPCLR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE0M : 2; + unsigned short POE1M : 2; + unsigned short POE2M : 2; + unsigned short POE3M : 2; + unsigned short PIE1 : 1; + unsigned short : 3; + unsigned short POE0F : 1; + unsigned short POE1F : 1; + unsigned short POE2F : 1; + unsigned short POE3F : 1; +#else + unsigned short POE3F : 1; + unsigned short POE2F : 1; + unsigned short POE1F : 1; + unsigned short POE0F : 1; + unsigned short : 3; + unsigned short PIE1 : 1; + unsigned short POE3M : 2; + unsigned short POE2M : 2; + unsigned short POE1M : 2; + unsigned short POE0M : 2; +#endif + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short OIE1 : 1; + unsigned short OCE1 : 1; + unsigned short : 5; + unsigned short OSF1 : 1; +#else + unsigned short OSF1 : 1; + unsigned short : 5; + unsigned short OCE1 : 1; + unsigned short OIE1 : 1; + unsigned short : 8; +#endif + } BIT; + } OCSR1; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short POE8M : 2; + unsigned short : 6; + unsigned short PIE2 : 1; + unsigned short POE8E : 1; + unsigned short : 2; + unsigned short POE8F : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short POE8F : 1; + unsigned short : 2; + unsigned short POE8E : 1; + unsigned short PIE2 : 1; + unsigned short : 6; + unsigned short POE8M : 2; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CH34HIZ : 1; + unsigned char CH0HIZ : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CH0HIZ : 1; + unsigned char CH34HIZ : 1; +#endif + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PE0ZE : 1; + unsigned char PE1ZE : 1; + unsigned char PE2ZE : 1; + unsigned char PE3ZE : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char PE3ZE : 1; + unsigned char PE2ZE : 1; + unsigned char PE1ZE : 1; + unsigned char PE0ZE : 1; +#endif + } BIT; + } POECR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char P3CZEA : 1; + unsigned char P2CZEA : 1; + unsigned char P1CZEA : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char P1CZEA : 1; + unsigned char P2CZEA : 1; + unsigned char P3CZEA : 1; + unsigned char : 4; +#endif + } BIT; + } POECR2; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 1; + unsigned short : 8; + unsigned short OSTSTE : 1; + unsigned short : 2; + unsigned short OSTSTF : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short OSTSTF : 1; + unsigned short : 2; + unsigned short OSTSTE : 1; + unsigned short : 8; + unsigned short : 1; +#endif + } BIT; + } ICSR3; +}; + +struct st_port { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL0 : 1; + unsigned char PSEL1 : 1; + unsigned char : 1; + unsigned char PSEL3 : 1; + unsigned char : 1; + unsigned char PSEL5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL5 : 1; + unsigned char : 1; + unsigned char PSEL3 : 1; + unsigned char : 1; + unsigned char PSEL1 : 1; + unsigned char PSEL0 : 1; +#endif + } BIT; + } PSRB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PSEL6 : 1; + unsigned char PSEL7 : 1; +#else + unsigned char PSEL7 : 1; + unsigned char PSEL6 : 1; + unsigned char : 6; +#endif + } BIT; + } PSRA; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PCR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 4; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif + } BIT; + } DSCR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk4[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B0 : 1; +#endif + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_porth { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } PCR; + char wk4[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char B0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char B0 : 1; +#endif + } BIT; + } DSCR; +}; + +struct st_portj { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } ODR0; + char wk4[45]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char B3 : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char B3 : 1; + unsigned char : 3; +#endif + } BIT; + } DSCR; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDAI : 1; + unsigned char SCLI : 1; + unsigned char SDAO : 1; + unsigned char SCLO : 1; + unsigned char SOWP : 1; + unsigned char CLO : 1; + unsigned char IICRST : 1; + unsigned char ICE : 1; +#else + unsigned char ICE : 1; + unsigned char IICRST : 1; + unsigned char CLO : 1; + unsigned char SOWP : 1; + unsigned char SCLO : 1; + unsigned char SDAO : 1; + unsigned char SCLI : 1; + unsigned char SDAI : 1; +#endif + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char ST : 1; + unsigned char RS : 1; + unsigned char SP : 1; + unsigned char : 1; + unsigned char TRS : 1; + unsigned char MST : 1; + unsigned char BBSY : 1; +#else + unsigned char BBSY : 1; + unsigned char MST : 1; + unsigned char TRS : 1; + unsigned char : 1; + unsigned char SP : 1; + unsigned char RS : 1; + unsigned char ST : 1; + unsigned char : 1; +#endif + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BC : 3; + unsigned char BCWP : 1; + unsigned char CKS : 3; + unsigned char MTWP : 1; +#else + unsigned char MTWP : 1; + unsigned char CKS : 3; + unsigned char BCWP : 1; + unsigned char BC : 3; +#endif + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOS : 1; + unsigned char TMOL : 1; + unsigned char TMOH : 1; + unsigned char : 1; + unsigned char SDDL : 3; + unsigned char DLCS : 1; +#else + unsigned char DLCS : 1; + unsigned char SDDL : 3; + unsigned char : 1; + unsigned char TMOH : 1; + unsigned char TMOL : 1; + unsigned char TMOS : 1; +#endif + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NF : 2; + unsigned char ACKBR : 1; + unsigned char ACKBT : 1; + unsigned char ACKWP : 1; + unsigned char RDRFS : 1; + unsigned char WAIT : 1; + unsigned char SMBS : 1; +#else + unsigned char SMBS : 1; + unsigned char WAIT : 1; + unsigned char RDRFS : 1; + unsigned char ACKWP : 1; + unsigned char ACKBT : 1; + unsigned char ACKBR : 1; + unsigned char NF : 2; +#endif + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOE : 1; + unsigned char MALE : 1; + unsigned char NALE : 1; + unsigned char SALE : 1; + unsigned char NACKE : 1; + unsigned char NFE : 1; + unsigned char SCLE : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SCLE : 1; + unsigned char NFE : 1; + unsigned char NACKE : 1; + unsigned char SALE : 1; + unsigned char NALE : 1; + unsigned char MALE : 1; + unsigned char TMOE : 1; +#endif + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SAR0E : 1; + unsigned char SAR1E : 1; + unsigned char SAR2E : 1; + unsigned char GCAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char HOAE : 1; +#else + unsigned char HOAE : 1; + unsigned char : 1; + unsigned char DIDE : 1; + unsigned char : 1; + unsigned char GCAE : 1; + unsigned char SAR2E : 1; + unsigned char SAR1E : 1; + unsigned char SAR0E : 1; +#endif + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOIE : 1; + unsigned char ALIE : 1; + unsigned char STIE : 1; + unsigned char SPIE : 1; + unsigned char NAKIE : 1; + unsigned char RIE : 1; + unsigned char TEIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char TEIE : 1; + unsigned char RIE : 1; + unsigned char NAKIE : 1; + unsigned char SPIE : 1; + unsigned char STIE : 1; + unsigned char ALIE : 1; + unsigned char TMOIE : 1; +#endif + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AAS0 : 1; + unsigned char AAS1 : 1; + unsigned char AAS2 : 1; + unsigned char GCA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char HOA : 1; +#else + unsigned char HOA : 1; + unsigned char : 1; + unsigned char DID : 1; + unsigned char : 1; + unsigned char GCA : 1; + unsigned char AAS2 : 1; + unsigned char AAS1 : 1; + unsigned char AAS0 : 1; +#endif + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TMOF : 1; + unsigned char AL : 1; + unsigned char START : 1; + unsigned char STOP : 1; + unsigned char NACKF : 1; + unsigned char RDRF : 1; + unsigned char TEND : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char TEND : 1; + unsigned char RDRF : 1; + unsigned char NACKF : 1; + unsigned char STOP : 1; + unsigned char START : 1; + unsigned char AL : 1; + unsigned char TMOF : 1; +#endif + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SVA0 : 1; + unsigned char SVA : 7; +#else + unsigned char SVA : 7; + unsigned char SVA0 : 1; +#endif + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FS : 1; + unsigned char SVA : 2; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SVA : 2; + unsigned char FS : 1; +#endif + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRL : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRL : 5; +#endif + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BRH : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char BRH : 5; +#endif + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPMS : 1; + unsigned char TXMD : 1; + unsigned char MODFEN : 1; + unsigned char MSTR : 1; + unsigned char SPEIE : 1; + unsigned char SPTIE : 1; + unsigned char SPE : 1; + unsigned char SPRIE : 1; +#else + unsigned char SPRIE : 1; + unsigned char SPE : 1; + unsigned char SPTIE : 1; + unsigned char SPEIE : 1; + unsigned char MSTR : 1; + unsigned char MODFEN : 1; + unsigned char TXMD : 1; + unsigned char SPMS : 1; +#endif + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSL0P : 1; + unsigned char SSL1P : 1; + unsigned char SSL2P : 1; + unsigned char SSL3P : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char SSL3P : 1; + unsigned char SSL2P : 1; + unsigned char SSL1P : 1; + unsigned char SSL0P : 1; +#endif + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPLP : 1; + unsigned char SPLP2 : 1; + unsigned char : 2; + unsigned char MOIFV : 1; + unsigned char MOIFE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MOIFE : 1; + unsigned char MOIFV : 1; + unsigned char : 2; + unsigned char SPLP2 : 1; + unsigned char SPLP : 1; +#endif + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OVRF : 1; + unsigned char IDLNF : 1; + unsigned char MODF : 1; + unsigned char PERF : 1; + unsigned char : 1; + unsigned char SPTEF : 1; + unsigned char : 1; + unsigned char SPRF : 1; +#else + unsigned char SPRF : 1; + unsigned char : 1; + unsigned char SPTEF : 1; + unsigned char : 1; + unsigned char PERF : 1; + unsigned char MODF : 1; + unsigned char IDLNF : 1; + unsigned char OVRF : 1; +#endif + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPSLN : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPSLN : 3; +#endif + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPCP : 3; + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SPECM : 3; + unsigned char : 1; + unsigned char SPCP : 3; +#endif + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPFC : 2; + unsigned char : 2; + unsigned char SPRDTD : 1; + unsigned char SPLW : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char SPLW : 1; + unsigned char SPRDTD : 1; + unsigned char : 2; + unsigned char SPFC : 2; +#endif + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SCKDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SCKDL : 3; +#endif + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SLNDL : 3; +#endif + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPNDL : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPNDL : 3; +#endif + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SPPE : 1; + unsigned char SPOE : 1; + unsigned char SPIIE : 1; + unsigned char PTE : 1; + unsigned char SCKASE : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SCKASE : 1; + unsigned char PTE : 1; + unsigned char SPIIE : 1; + unsigned char SPOE : 1; + unsigned char SPPE : 1; +#endif + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CPHA : 1; + unsigned short CPOL : 1; + unsigned short BRDV : 2; + unsigned short SSLA : 3; + unsigned short SSLKP : 1; + unsigned short SPB : 4; + unsigned short LSBF : 1; + unsigned short SPNDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SCKDEN : 1; +#else + unsigned short SCKDEN : 1; + unsigned short SLNDEN : 1; + unsigned short SPNDEN : 1; + unsigned short LSBF : 1; + unsigned short SPB : 4; + unsigned short SSLKP : 1; + unsigned short SSLA : 3; + unsigned short BRDV : 2; + unsigned short CPOL : 1; + unsigned short CPHA : 1; +#endif + } BIT; + } SPCMD7; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char F64HZ : 1; + unsigned char F32HZ : 1; + unsigned char F16HZ : 1; + unsigned char F8HZ : 1; + unsigned char F4HZ : 1; + unsigned char F2HZ : 1; + unsigned char F1HZ : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char F1HZ : 1; + unsigned char F2HZ : 1; + unsigned char F4HZ : 1; + unsigned char F8HZ : 1; + unsigned char F16HZ : 1; + unsigned char F32HZ : 1; + unsigned char F64HZ : 1; +#endif + } BIT; + } R64CNT; + char wk0[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCNT; + unsigned char BCNT0; + }; + char wk1[1]; + union { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCNT; + unsigned char BCNT1; + }; + char wk2[1]; + union { + unsigned char BCNT2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCNT; + }; + char wk3[1]; + union { + unsigned char BCNT3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKCNT; + }; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRCNT; + union { + unsigned char BCNT0AR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECAR; + }; + char wk7[1]; + union { + unsigned char BCNT1AR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINAR; + }; + char wk8[1]; + union { + unsigned char BCNT2AR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRAR; + }; + char wk9[1]; + union { + unsigned char BCNT3AR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 4; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 4; + unsigned char DAYW : 3; +#endif + } BIT; + } RWKAR; + }; + char wk10[1]; + union { + unsigned char BCNT0AER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 1; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYAR; + }; + char wk11[1]; + union { + unsigned char BCNT1AER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 2; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 2; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONAR; + }; + char wk12[1]; + union { + unsigned short BCNT2AER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif + } BIT; + } RYRAR; + }; + union { + unsigned char BCNT3AER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 7; +#endif + } BIT; + } RYRAREN; + }; + char wk13[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AIE : 1; + unsigned char CIE : 1; + unsigned char PIE : 1; + unsigned char RTCOS : 1; + unsigned char PES : 4; +#else + unsigned char PES : 4; + unsigned char RTCOS : 1; + unsigned char PIE : 1; + unsigned char CIE : 1; + unsigned char AIE : 1; +#endif + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char START : 1; + unsigned char RESET : 1; + unsigned char ADJ30 : 1; + unsigned char RTCOE : 1; + unsigned char AADJE : 1; + unsigned char AADJP : 1; + unsigned char HR24 : 1; + unsigned char CNTMD : 1; +#else + unsigned char CNTMD : 1; + unsigned char HR24 : 1; + unsigned char AADJP : 1; + unsigned char AADJE : 1; + unsigned char RTCOE : 1; + unsigned char ADJ30 : 1; + unsigned char RESET : 1; + unsigned char START : 1; +#endif + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RTCEN : 1; + unsigned char RTCDV : 3; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char RTCDV : 3; + unsigned char RTCEN : 1; +#endif + } BIT; + } RCR3; + char wk16[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADJ : 6; + unsigned char PMADJ : 2; +#else + unsigned char PMADJ : 2; + unsigned char ADJ : 6; +#endif + } BIT; + } RADJ; + char wk17[17]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR0; + char wk18[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR1; + char wk19[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif + } BIT; + } RTCCR2; + char wk20[13]; + union { + unsigned char BCNT0CP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP0; + }; + char wk21[1]; + union { + unsigned char BCNT1CP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP0; + }; + char wk22[1]; + union { + unsigned char BCNT2CP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP0; + }; + char wk23[3]; + union { + unsigned char BCNT3CP0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP0; + }; + char wk24[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP0; + char wk25[5]; + union { + unsigned char BCNT0CP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP1; + }; + char wk26[1]; + union { + unsigned char BCNT1CP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP1; + }; + char wk27[1]; + union { + unsigned char BCNT2CP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP1; + }; + char wk28[3]; + union { + unsigned char BCNT3CP1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP1; + }; + char wk29[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP1; + char wk30[5]; + union { + unsigned char BCNT0CP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif + } BIT; + } RSECCP2; + }; + char wk31[1]; + union { + unsigned char BCNT1CP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif + } BIT; + } RMINCP2; + }; + char wk32[1]; + union { + unsigned char BCNT2CP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif + } BIT; + } RHRCP2; + }; + char wk33[3]; + union { + unsigned char BCNT3CP2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif + } BIT; + } RDAYCP2; + }; + char wk34[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif + } BIT; + } RMONCP2; +}; + +struct st_s12ad { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DBLANS : 5; + unsigned short : 1; + unsigned short GBADIE : 1; + unsigned short DBLE : 1; + unsigned short EXTRG : 1; + unsigned short TRGE : 1; + unsigned short ADHSC : 1; + unsigned short : 1; + unsigned short ADIE : 1; + unsigned short ADCS : 2; + unsigned short ADST : 1; +#else + unsigned short ADST : 1; + unsigned short ADCS : 2; + unsigned short ADIE : 1; + unsigned short : 1; + unsigned short ADHSC : 1; + unsigned short TRGE : 1; + unsigned short EXTRG : 1; + unsigned short DBLE : 1; + unsigned short GBADIE : 1; + unsigned short : 1; + unsigned short DBLANS : 5; +#endif + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA000 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSA007 : 1; + unsigned short ANSA006 : 1; + unsigned short ANSA005 : 1; + unsigned short ANSA004 : 1; + unsigned short ANSA003 : 1; + unsigned short ANSA002 : 1; + unsigned short ANSA001 : 1; + unsigned short ANSA000 : 1; +#endif + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSA100 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA104 : 1; + unsigned short ANSA105 : 1; + unsigned short ANSA106 : 1; + unsigned short ANSA107 : 1; + unsigned short ANSA108 : 1; + unsigned short ANSA109 : 1; + unsigned short ANSA110 : 1; + unsigned short ANSA111 : 1; + unsigned short ANSA112 : 1; + unsigned short ANSA113 : 1; + unsigned short ANSA114 : 1; + unsigned short ANSA115 : 1; +#else + unsigned short ANSA115 : 1; + unsigned short ANSA114 : 1; + unsigned short ANSA113 : 1; + unsigned short ANSA112 : 1; + unsigned short ANSA111 : 1; + unsigned short ANSA110 : 1; + unsigned short ANSA109 : 1; + unsigned short ANSA108 : 1; + unsigned short ANSA107 : 1; + unsigned short ANSA106 : 1; + unsigned short ANSA105 : 1; + unsigned short ANSA104 : 1; + unsigned short ANSA103 : 1; + unsigned short ANSA102 : 1; + unsigned short ANSA101 : 1; + unsigned short ANSA100 : 1; +#endif + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS000 : 1; + unsigned short ADS001 : 1; + unsigned short ADS002 : 1; + unsigned short ADS003 : 1; + unsigned short ADS004 : 1; + unsigned short ADS005 : 1; + unsigned short ADS006 : 1; + unsigned short ADS007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ADS007 : 1; + unsigned short ADS006 : 1; + unsigned short ADS005 : 1; + unsigned short ADS004 : 1; + unsigned short ADS003 : 1; + unsigned short ADS002 : 1; + unsigned short ADS001 : 1; + unsigned short ADS000 : 1; +#endif + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ADS100 : 1; + unsigned short ADS101 : 1; + unsigned short ADS102 : 1; + unsigned short ADS103 : 1; + unsigned short ADS104 : 1; + unsigned short ADS105 : 1; + unsigned short ADS106 : 1; + unsigned short ADS107 : 1; + unsigned short ADS108 : 1; + unsigned short ADS109 : 1; + unsigned short ADS110 : 1; + unsigned short ADS111 : 1; + unsigned short ADS112 : 1; + unsigned short ADS113 : 1; + unsigned short ADS114 : 1; + unsigned short ADS115 : 1; +#else + unsigned short ADS115 : 1; + unsigned short ADS114 : 1; + unsigned short ADS113 : 1; + unsigned short ADS112 : 1; + unsigned short ADS111 : 1; + unsigned short ADS110 : 1; + unsigned short ADS109 : 1; + unsigned short ADS108 : 1; + unsigned short ADS107 : 1; + unsigned short ADS106 : 1; + unsigned short ADS105 : 1; + unsigned short ADS104 : 1; + unsigned short ADS103 : 1; + unsigned short ADS102 : 1; + unsigned short ADS101 : 1; + unsigned short ADS100 : 1; +#endif + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADC : 3; + unsigned char : 4; + unsigned char AVEE : 1; +#else + unsigned char AVEE : 1; + unsigned char : 4; + unsigned char ADC : 3; +#endif + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 5; + unsigned short ACE : 1; + unsigned short : 2; + unsigned short DIAGVAL : 2; + unsigned short DIAGLD : 1; + unsigned short DIAGM : 1; + unsigned short : 3; + unsigned short ADRFMT : 1; +#else + unsigned short ADRFMT : 1; + unsigned short : 3; + unsigned short DIAGM : 1; + unsigned short DIAGLD : 1; + unsigned short DIAGVAL : 2; + unsigned short : 2; + unsigned short ACE : 1; + unsigned short : 5; +#endif + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TRSB : 6; + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short TRSA : 6; + unsigned short : 2; + unsigned short TRSB : 6; +#endif + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TSSAD : 1; + unsigned short OCSAD : 1; + unsigned short : 6; + unsigned short TSSA : 1; + unsigned short OCSA : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short OCSA : 1; + unsigned short TSSA : 1; + unsigned short : 6; + unsigned short OCSAD : 1; + unsigned short TSSAD : 1; +#endif + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB000 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ANSB007 : 1; + unsigned short ANSB006 : 1; + unsigned short ANSB005 : 1; + unsigned short ANSB004 : 1; + unsigned short ANSB003 : 1; + unsigned short ANSB002 : 1; + unsigned short ANSB001 : 1; + unsigned short ANSB000 : 1; +#endif + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ANSB100 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB104 : 1; + unsigned short ANSB105 : 1; + unsigned short ANSB106 : 1; + unsigned short ANSB107 : 1; + unsigned short ANSB108 : 1; + unsigned short ANSB109 : 1; + unsigned short ANSB110 : 1; + unsigned short ANSB111 : 1; + unsigned short ANSB112 : 1; + unsigned short ANSB113 : 1; + unsigned short ANSB114 : 1; + unsigned short ANSB115 : 1; +#else + unsigned short ANSB115 : 1; + unsigned short ANSB114 : 1; + unsigned short ANSB113 : 1; + unsigned short ANSB112 : 1; + unsigned short ANSB111 : 1; + unsigned short ANSB110 : 1; + unsigned short ANSB109 : 1; + unsigned short ANSB108 : 1; + unsigned short ANSB107 : 1; + unsigned short ANSB106 : 1; + unsigned short ANSB105 : 1; + unsigned short ANSB104 : 1; + unsigned short ANSB103 : 1; + unsigned short ANSB102 : 1; + unsigned short ANSB101 : 1; + unsigned short ANSB100 : 1; +#endif + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#else + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#endif + } RIGHT; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short DIAGST : 2; + unsigned short : 2; + unsigned short AD : 12; +#else + unsigned short AD : 12; + unsigned short : 2; + unsigned short DIAGST : 2; +#endif + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk2[16]; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + unsigned short ADDR21; + unsigned short ADDR22; + unsigned short ADDR23; + unsigned short ADDR24; + unsigned short ADDR25; + unsigned short ADDR26; + unsigned short ADDR27; + unsigned short ADDR28; + unsigned short ADDR29; + unsigned short ADDR30; + unsigned short ADDR31; + char wk4[26]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADNDIS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ADNDIS : 5; +#endif + } BIT; + } ADDISCR; + char wk5[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ELCC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char ELCC : 2; +#endif + } BIT; + } ADELCCR; + char wk6[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PGS : 1; + unsigned short GBRSCN : 1; + unsigned short : 13; + unsigned short GBRP : 1; +#else + unsigned short GBRP : 1; + unsigned short : 13; + unsigned short GBRSCN : 1; + unsigned short PGS : 1; +#endif + } BIT; + } ADGSPCR; + char wk7[8]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HVSEL : 2; + unsigned char : 2; + unsigned char LVSEL : 1; + unsigned char : 2; + unsigned char ADSLP : 1; +#else + unsigned char ADSLP : 1; + unsigned char : 2; + unsigned char LVSEL : 1; + unsigned char : 2; + unsigned char HVSEL : 2; +#endif + } BIT; + } ADHVREFCNT; + char wk8[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MONCOMB : 1; + unsigned char : 3; + unsigned char MONCMPA : 1; + unsigned char MONCMPB : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char MONCMPB : 1; + unsigned char MONCMPA : 1; + unsigned char : 3; + unsigned char MONCOMB : 1; +#endif + } BIT; + } ADWINMON; + char wk9[3]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPAB : 2; + unsigned short : 7; + unsigned short CMPBE : 1; + unsigned short : 1; + unsigned short CMPAE : 1; + unsigned short : 2; + unsigned short WCMPE : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short WCMPE : 1; + unsigned short : 2; + unsigned short CMPAE : 1; + unsigned short : 1; + unsigned short CMPBE : 1; + unsigned short : 7; + unsigned short CMPAB : 2; +#endif + } BIT; + } ADCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPTSA : 1; + unsigned char CMPOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPOCA : 1; + unsigned char CMPTSA : 1; +#endif + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPLTSA : 1; + unsigned char CMPLOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPLOCA : 1; + unsigned char CMPLTSA : 1; +#endif + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA000 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPCHA007 : 1; + unsigned short CMPCHA006 : 1; + unsigned short CMPCHA005 : 1; + unsigned short CMPCHA004 : 1; + unsigned short CMPCHA003 : 1; + unsigned short CMPCHA002 : 1; + unsigned short CMPCHA001 : 1; + unsigned short CMPCHA000 : 1; +#endif + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPCHA100 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA104 : 1; + unsigned short CMPCHA105 : 1; + unsigned short CMPCHA106 : 1; + unsigned short CMPCHA107 : 1; + unsigned short CMPCHA108 : 1; + unsigned short CMPCHA109 : 1; + unsigned short CMPCHA110 : 1; + unsigned short CMPCHA111 : 1; + unsigned short CMPCHA112 : 1; + unsigned short CMPCHA113 : 1; + unsigned short CMPCHA114 : 1; + unsigned short CMPCHA115 : 1; +#else + unsigned short CMPCHA115 : 1; + unsigned short CMPCHA114 : 1; + unsigned short CMPCHA113 : 1; + unsigned short CMPCHA112 : 1; + unsigned short CMPCHA111 : 1; + unsigned short CMPCHA110 : 1; + unsigned short CMPCHA109 : 1; + unsigned short CMPCHA108 : 1; + unsigned short CMPCHA107 : 1; + unsigned short CMPCHA106 : 1; + unsigned short CMPCHA105 : 1; + unsigned short CMPCHA104 : 1; + unsigned short CMPCHA103 : 1; + unsigned short CMPCHA102 : 1; + unsigned short CMPCHA101 : 1; + unsigned short CMPCHA100 : 1; +#endif + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA000 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPLCHA007 : 1; + unsigned short CMPLCHA006 : 1; + unsigned short CMPLCHA005 : 1; + unsigned short CMPLCHA004 : 1; + unsigned short CMPLCHA003 : 1; + unsigned short CMPLCHA002 : 1; + unsigned short CMPLCHA001 : 1; + unsigned short CMPLCHA000 : 1; +#endif + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPLCHA100 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA104 : 1; + unsigned short CMPLCHA105 : 1; + unsigned short CMPLCHA106 : 1; + unsigned short CMPLCHA107 : 1; + unsigned short CMPLCHA108 : 1; + unsigned short CMPLCHA109 : 1; + unsigned short CMPLCHA110 : 1; + unsigned short CMPLCHA111 : 1; + unsigned short CMPLCHA112 : 1; + unsigned short CMPLCHA113 : 1; + unsigned short CMPLCHA114 : 1; + unsigned short CMPLCHA115 : 1; +#else + unsigned short CMPLCHA115 : 1; + unsigned short CMPLCHA114 : 1; + unsigned short CMPLCHA113 : 1; + unsigned short CMPLCHA112 : 1; + unsigned short CMPLCHA111 : 1; + unsigned short CMPLCHA110 : 1; + unsigned short CMPLCHA109 : 1; + unsigned short CMPLCHA108 : 1; + unsigned short CMPLCHA107 : 1; + unsigned short CMPLCHA106 : 1; + unsigned short CMPLCHA105 : 1; + unsigned short CMPLCHA104 : 1; + unsigned short CMPLCHA103 : 1; + unsigned short CMPLCHA102 : 1; + unsigned short CMPLCHA101 : 1; + unsigned short CMPLCHA100 : 1; +#endif + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA000 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA007 : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short CMPSTCHA007 : 1; + unsigned short CMPSTCHA006 : 1; + unsigned short CMPSTCHA005 : 1; + unsigned short CMPSTCHA004 : 1; + unsigned short CMPSTCHA003 : 1; + unsigned short CMPSTCHA002 : 1; + unsigned short CMPSTCHA001 : 1; + unsigned short CMPSTCHA000 : 1; +#endif + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPSTCHA100 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA104 : 1; + unsigned short CMPSTCHA105 : 1; + unsigned short CMPSTCHA106 : 1; + unsigned short CMPSTCHA107 : 1; + unsigned short CMPSTCHA108 : 1; + unsigned short CMPSTCHA109 : 1; + unsigned short CMPSTCHA110 : 1; + unsigned short CMPSTCHA111 : 1; + unsigned short CMPSTCHA112 : 1; + unsigned short CMPSTCHA113 : 1; + unsigned short CMPSTCHA114 : 1; + unsigned short CMPSTCHA115 : 1; +#else + unsigned short CMPSTCHA115 : 1; + unsigned short CMPSTCHA114 : 1; + unsigned short CMPSTCHA113 : 1; + unsigned short CMPSTCHA112 : 1; + unsigned short CMPSTCHA111 : 1; + unsigned short CMPSTCHA110 : 1; + unsigned short CMPSTCHA109 : 1; + unsigned short CMPSTCHA108 : 1; + unsigned short CMPSTCHA107 : 1; + unsigned short CMPSTCHA106 : 1; + unsigned short CMPSTCHA105 : 1; + unsigned short CMPSTCHA104 : 1; + unsigned short CMPSTCHA103 : 1; + unsigned short CMPSTCHA102 : 1; + unsigned short CMPSTCHA101 : 1; + unsigned short CMPSTCHA100 : 1; +#endif + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTTSA : 1; + unsigned char CMPSTOCA : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char CMPSTOCA : 1; + unsigned char CMPSTTSA : 1; +#endif + } BIT; + } ADCMPSER; + char wk10[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPCHB : 6; + unsigned char : 1; + unsigned char CMPLB : 1; +#else + unsigned char CMPLB : 1; + unsigned char : 1; + unsigned char CMPCHB : 6; +#endif + } BIT; + } ADCMPBNSR; + char wk11[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CMPSTB : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CMPSTB : 1; +#endif + } BIT; + } ADCMPBSR; + char wk12[3]; + unsigned short ADBUF0; + unsigned short ADBUF1; + unsigned short ADBUF2; + unsigned short ADBUF3; + unsigned short ADBUF4; + unsigned short ADBUF5; + unsigned short ADBUF6; + unsigned short ADBUF7; + unsigned short ADBUF8; + unsigned short ADBUF9; + unsigned short ADBUF10; + unsigned short ADBUF11; + unsigned short ADBUF12; + unsigned short ADBUF13; + unsigned short ADBUF14; + unsigned short ADBUF15; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BUFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BUFEN : 1; +#endif + } BIT; + } ADBUFEN; + char wk13[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BUFPTR : 4; + unsigned char PTROVF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PTROVF : 1; + unsigned char BUFPTR : 4; +#endif + } BIT; + } ADBUFPTR; + char wk14[10]; + unsigned char ADSSTRL; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; +}; + +struct st_sci0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_sci12 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ESME : 1; +#endif + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SFSF : 1; + unsigned char RXDSF : 1; + unsigned char BRME : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char BRME : 1; + unsigned char RXDSF : 1; + unsigned char SFSF : 1; + unsigned char : 1; +#endif + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFE : 1; + unsigned char CF0RE : 1; + unsigned char CF1DS : 2; + unsigned char PIBE : 1; + unsigned char PIBS : 3; +#else + unsigned char PIBS : 3; + unsigned char PIBE : 1; + unsigned char CF1DS : 2; + unsigned char CF0RE : 1; + unsigned char BFE : 1; +#endif + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFCS : 3; + unsigned char : 1; + unsigned char BCCS : 2; + unsigned char RTS : 2; +#else + unsigned char RTS : 2; + unsigned char BCCS : 2; + unsigned char : 1; + unsigned char DFCS : 3; +#endif + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SDST : 1; +#endif + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXDXPS : 1; + unsigned char RXDXPS : 1; + unsigned char : 2; + unsigned char SHARPS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SHARPS : 1; + unsigned char : 2; + unsigned char RXDXPS : 1; + unsigned char TXDXPS : 1; +#endif + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDIE : 1; + unsigned char CF0MIE : 1; + unsigned char CF1MIE : 1; + unsigned char PIBDIE : 1; + unsigned char BCDIE : 1; + unsigned char AEDIE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDIE : 1; + unsigned char BCDIE : 1; + unsigned char PIBDIE : 1; + unsigned char CF1MIE : 1; + unsigned char CF0MIE : 1; + unsigned char BFDIE : 1; +#endif + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDF : 1; + unsigned char CF0MF : 1; + unsigned char CF1MF : 1; + unsigned char PIBDF : 1; + unsigned char BCDF : 1; + unsigned char AEDF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDF : 1; + unsigned char BCDF : 1; + unsigned char PIBDF : 1; + unsigned char CF1MF : 1; + unsigned char CF0MF : 1; + unsigned char BFDF : 1; +#endif + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDCL : 1; + unsigned char CF0MCL : 1; + unsigned char CF1MCL : 1; + unsigned char PIBDCL : 1; + unsigned char BCDCL : 1; + unsigned char AEDCL : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDCL : 1; + unsigned char BCDCL : 1; + unsigned char PIBDCL : 1; + unsigned char CF1MCL : 1; + unsigned char CF0MCL : 1; + unsigned char BFDCL : 1; +#endif + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0CE0 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE7 : 1; +#else + unsigned char CF0CE7 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE0 : 1; +#endif + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF1CE0 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE7 : 1; +#else + unsigned char CF1CE7 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE0 : 1; +#endif + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCST : 1; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TOMS : 2; + unsigned char : 1; + unsigned char TWRC : 1; + unsigned char TCSS : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char TCSS : 3; + unsigned char TWRC : 1; + unsigned char : 1; + unsigned char TOMS : 2; +#endif + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +}; + +struct st_sdhi { + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long CMD12AT:2; +// unsigned long TRSTP:1; +// unsigned long CMDRW:1; +// unsigned long CMDTP:1; +// unsigned long RSPTP:3; +// unsigned long ACMD:2; +// unsigned long CMDIDX:6; +// } BIT; + } SDCMD; + char wk0[4]; + unsigned long SDARG; + char wk1[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long STP : 1; + unsigned long : 7; + unsigned long SDBLKCNTEN : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long SDBLKCNTEN : 1; + unsigned long : 7; + unsigned long STP : 1; +#endif + } BIT; + } SDSTOP; + unsigned long SDBLKCNT; + unsigned long SDRSP10; + char wk2[4]; + unsigned long SDRSP32; + char wk3[4]; + unsigned long SDRSP54; + char wk4[4]; + unsigned long SDRSP76; + char wk5[4]; + union { + unsigned long LONG; +// struct { +// unsigned long :21; +// unsigned long SDD3MON:1; +// unsigned long SDD3IN:1; +// unsigned long SDD3RM:1; +// unsigned long SDWPMON:1; +// unsigned long :1; +// unsigned long SDCDMON:1; +// unsigned long SDCDIN:1; +// unsigned long SDCDRM:1; +// unsigned long ACEND:1; +// unsigned long :1; +// unsigned long RSPEND:1; +// } BIT; + } SDSTS1; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long ILA:1; +// unsigned long CBSY:1; +// unsigned long SDCLKCREN:1; +// unsigned long :3; +// unsigned long BWE:1; +// unsigned long BRE:1; +// unsigned long SDD0MON:1; +// unsigned long RSPTO:1; +// unsigned long ILR:1; +// unsigned long ILW:1; +// unsigned long DTO:1; +// unsigned long ENDE:1; +// unsigned long CRCE:1; +// unsigned long CMDE:1; +// } BIT; + } SDSTS2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPENDM : 1; + unsigned long : 1; + unsigned long ACENDM : 1; + unsigned long SDCDRMM : 1; + unsigned long SDCDINM : 1; + unsigned long : 3; + unsigned long SDD3RMM : 1; + unsigned long SDD3INM : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long SDD3INM : 1; + unsigned long SDD3RMM : 1; + unsigned long : 3; + unsigned long SDCDINM : 1; + unsigned long SDCDRMM : 1; + unsigned long ACENDM : 1; + unsigned long : 1; + unsigned long RSPENDM : 1; +#endif + } BIT; + } SDIMSK1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMDEM : 1; + unsigned long CRCEM : 1; + unsigned long ENDEM : 1; + unsigned long DTTOM : 1; + unsigned long ILWM : 1; + unsigned long ILRM : 1; + unsigned long RSPTOM : 1; + unsigned long : 1; + unsigned long BREM : 1; + unsigned long BWEM : 1; + unsigned long : 5; + unsigned long ILAM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long ILAM : 1; + unsigned long : 5; + unsigned long BWEM : 1; + unsigned long BREM : 1; + unsigned long : 1; + unsigned long RSPTOM : 1; + unsigned long ILRM : 1; + unsigned long ILWM : 1; + unsigned long DTTOM : 1; + unsigned long ENDEM : 1; + unsigned long CRCEM : 1; + unsigned long CMDEM : 1; +#endif + } BIT; + } SDIMSK2; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLKSEL : 8; + unsigned long CLKEN : 1; + unsigned long CLKCTRLEN : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long CLKCTRLEN : 1; + unsigned long CLKEN : 1; + unsigned long CLKSEL : 8; +#endif + } BIT; + } SDCLKCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long LEN : 10; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long LEN : 10; +#endif + } BIT; + } SDSIZE; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CTOP : 4; + unsigned long TOP : 4; + unsigned long : 7; + unsigned long WIDTH : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long WIDTH : 1; + unsigned long : 7; + unsigned long TOP : 4; + unsigned long CTOP : 4; +#endif + } BIT; + } SDOPT; + char wk6[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CMDE0 : 1; + unsigned long CMDE1 : 1; + unsigned long RSPLENE0 : 1; + unsigned long RSPLENE1 : 1; + unsigned long RDLENE : 1; + unsigned long CRCLENE : 1; + unsigned long : 2; + unsigned long RSPCRCE0 : 1; + unsigned long RSPCRCE1 : 1; + unsigned long RDCRCE : 1; + unsigned long CRCTKE : 1; + unsigned long CRCTK : 3; + unsigned long : 17; +#else + unsigned long : 17; + unsigned long CRCTK : 3; + unsigned long CRCTKE : 1; + unsigned long RDCRCE : 1; + unsigned long RSPCRCE1 : 1; + unsigned long RSPCRCE0 : 1; + unsigned long : 2; + unsigned long CRCLENE : 1; + unsigned long RDLENE : 1; + unsigned long RSPLENE1 : 1; + unsigned long RSPLENE0 : 1; + unsigned long CMDE1 : 1; + unsigned long CMDE0 : 1; +#endif + } BIT; + } SDERSTS1; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RSPTO0 : 1; + unsigned long RSPTO1 : 1; + unsigned long BSYTO0 : 1; + unsigned long BSYTO1 : 1; + unsigned long RDTO : 1; + unsigned long CRCTO : 1; + unsigned long CRCBSYTO : 1; + unsigned long : 25; +#else + unsigned long : 25; + unsigned long CRCBSYTO : 1; + unsigned long CRCTO : 1; + unsigned long RDTO : 1; + unsigned long BSYTO1 : 1; + unsigned long BSYTO0 : 1; + unsigned long RSPTO1 : 1; + unsigned long RSPTO0 : 1; +#endif + } BIT; + } SDERSTS2; + unsigned long SDBUFR; + char wk7[4]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long INTEN : 1; + unsigned long : 1; + unsigned long RWREQ : 1; + unsigned long : 5; + unsigned long IOABT : 1; + unsigned long C52PUB : 1; + unsigned long : 22; +#else + unsigned long : 22; + unsigned long C52PUB : 1; + unsigned long IOABT : 1; + unsigned long : 5; + unsigned long RWREQ : 1; + unsigned long : 1; + unsigned long INTEN : 1; +#endif + } BIT; + } SDIOMD; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long EXWT:1; +// unsigned long EXPUB52:1; +// unsigned long :13; +// unsigned long IOIRQ:1; +// } BIT; + } SDIOSTS; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IOIRQM : 1; + unsigned long : 13; + unsigned long EXPUB52M : 1; + unsigned long EXWTM : 1; + unsigned long : 16; +#else + unsigned long : 16; + unsigned long EXWTM : 1; + unsigned long EXPUB52M : 1; + unsigned long : 13; + unsigned long IOIRQM : 1; +#endif + } BIT; + } SDIOIMSK; + char wk8[316]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 1; + unsigned long DMAEN : 1; + unsigned long : 30; +#else + unsigned long : 30; + unsigned long DMAEN : 1; + unsigned long : 1; +#endif + } BIT; + } SDDMAEN; + char wk9[12]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long SDRST : 1; + unsigned long : 31; +#else + unsigned long : 31; + unsigned long SDRST : 1; +#endif + } BIT; + } SDRST; + char wk10[28]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 6; + unsigned long BWSWP : 1; + unsigned long BRSWP : 1; + unsigned long : 24; +#else + unsigned long : 24; + unsigned long BRSWP : 1; + unsigned long BWSWP : 1; + unsigned long : 6; +#endif + } BIT; + } SDSWAP; +}; + +struct st_smci { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char BCP : 2; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char BLK : 1; + unsigned char GM : 1; +#else + unsigned char GM : 1; + unsigned char BLK : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char BCP : 2; + unsigned char CKS : 2; +#endif + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char ERS : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char ERS : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif + } BIT; + } SCMR; + char wk0[7]; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_ssi { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long REN : 1; + unsigned long TEN : 1; + unsigned long : 1; + unsigned long MUEN : 1; + unsigned long CKDV : 4; + unsigned long DEL : 1; + unsigned long PDTA : 1; + unsigned long SDTA : 1; + unsigned long SPDP : 1; + unsigned long SWSP : 1; + unsigned long SCKP : 1; + unsigned long SWSD : 1; + unsigned long SCKD : 1; + unsigned long SWL : 3; + unsigned long DWL : 3; + unsigned long CHNL : 2; + unsigned long : 1; + unsigned long IIEN : 1; + unsigned long ROIEN : 1; + unsigned long RUIEN : 1; + unsigned long TOIEN : 1; + unsigned long TUIEN : 1; + unsigned long CKS : 1; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CKS : 1; + unsigned long TUIEN : 1; + unsigned long TOIEN : 1; + unsigned long RUIEN : 1; + unsigned long ROIEN : 1; + unsigned long IIEN : 1; + unsigned long : 1; + unsigned long CHNL : 2; + unsigned long DWL : 3; + unsigned long SWL : 3; + unsigned long SCKD : 1; + unsigned long SWSD : 1; + unsigned long SCKP : 1; + unsigned long SWSP : 1; + unsigned long SPDP : 1; + unsigned long SDTA : 1; + unsigned long PDTA : 1; + unsigned long DEL : 1; + unsigned long CKDV : 4; + unsigned long MUEN : 1; + unsigned long : 1; + unsigned long TEN : 1; + unsigned long REN : 1; +#endif + } BIT; + } SSICR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IDST : 1; + unsigned long RSWNO : 1; + unsigned long RCHNO : 2; + unsigned long TSWNO : 1; + unsigned long TCHNO : 2; + unsigned long : 18; + unsigned long IIRQ : 1; + unsigned long ROIRQ : 1; + unsigned long RUIRQ : 1; + unsigned long TOIRQ : 1; + unsigned long TUIRQ : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long TUIRQ : 1; + unsigned long TOIRQ : 1; + unsigned long RUIRQ : 1; + unsigned long ROIRQ : 1; + unsigned long IIRQ : 1; + unsigned long : 18; + unsigned long TCHNO : 2; + unsigned long TSWNO : 1; + unsigned long RCHNO : 2; + unsigned long RSWNO : 1; + unsigned long IDST : 1; +#endif + } BIT; + } SSISR; + char wk0[8]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RFRST : 1; + unsigned long TFRST : 1; + unsigned long RIE : 1; + unsigned long TIE : 1; + unsigned long RTRG : 2; + unsigned long TTRG : 2; + unsigned long : 8; + unsigned long SSIRST : 1; + unsigned long : 14; + unsigned long AUCKE : 1; +#else + unsigned long AUCKE : 1; + unsigned long : 14; + unsigned long SSIRST : 1; + unsigned long : 8; + unsigned long TTRG : 2; + unsigned long RTRG : 2; + unsigned long TIE : 1; + unsigned long RIE : 1; + unsigned long TFRST : 1; + unsigned long RFRST : 1; +#endif + } BIT; + } SSIFCR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long RDF : 1; + unsigned long : 7; + unsigned long RDC : 4; + unsigned long : 4; + unsigned long TDE : 1; + unsigned long : 7; + unsigned long TDC : 4; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long TDC : 4; + unsigned long : 7; + unsigned long TDE : 1; + unsigned long : 4; + unsigned long RDC : 4; + unsigned long : 7; + unsigned long RDF : 1; +#endif + } BIT; + } SSIFSR; + unsigned long SSIFTDR; + unsigned long SSIFRDR; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 8; + unsigned long CONT : 1; + unsigned long : 23; +#else + unsigned long : 23; + unsigned long CONT : 1; + unsigned long : 8; +#endif + } BIT; + } SSITDMR; +}; + +struct st_system { + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short MD : 1; +#endif + } BIT; + } MDMONR; + char wk0[4]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ROME : 1; + unsigned short EXBE : 1; + unsigned short : 6; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 6; + unsigned short EXBE : 1; + unsigned short ROME : 1; +#endif + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RAME : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RAME : 1; +#endif + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 14; + unsigned short OPE : 1; + unsigned short SSBY : 1; +#else + unsigned short SSBY : 1; + unsigned short OPE : 1; + unsigned short : 14; +#endif + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 4; + unsigned long MSTPA4 : 1; + unsigned long MSTPA5 : 1; + unsigned long : 3; + unsigned long MSTPA9 : 1; + unsigned long : 3; + unsigned long MSTPA13 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA15 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA19 : 1; + unsigned long : 8; + unsigned long MSTPA28 : 1; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long MSTPA28 : 1; + unsigned long : 8; + unsigned long MSTPA19 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA13 : 1; + unsigned long : 3; + unsigned long MSTPA9 : 1; + unsigned long : 3; + unsigned long MSTPA5 : 1; + unsigned long MSTPA4 : 1; + unsigned long : 4; +#endif + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPB0 : 1; + unsigned long : 3; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 2; + unsigned long MSTPB9 : 1; + unsigned long MSTPB10 : 1; + unsigned long : 6; + unsigned long MSTPB17 : 1; + unsigned long : 1; + unsigned long MSTPB19 : 1; + unsigned long : 1; + unsigned long MSTPB21 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB26 : 1; + unsigned long : 3; + unsigned long MSTPB30 : 1; + unsigned long MSTPB31 : 1; +#else + unsigned long MSTPB31 : 1; + unsigned long MSTPB30 : 1; + unsigned long : 3; + unsigned long MSTPB26 : 1; + unsigned long MSTPB25 : 1; + unsigned long : 1; + unsigned long MSTPB23 : 1; + unsigned long : 1; + unsigned long MSTPB21 : 1; + unsigned long : 1; + unsigned long MSTPB19 : 1; + unsigned long : 1; + unsigned long MSTPB17 : 1; + unsigned long : 6; + unsigned long MSTPB10 : 1; + unsigned long MSTPB9 : 1; + unsigned long : 2; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 3; + unsigned long MSTPB0 : 1; +#endif + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPC0 : 1; + unsigned long MSTPC1 : 1; + unsigned long : 17; + unsigned long MSTPC19 : 1; + unsigned long MSTPC20 : 1; + unsigned long : 5; + unsigned long MSTPC26 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC29 : 1; + unsigned long MSTPC30 : 1; + unsigned long DSLPE : 1; +#else + unsigned long DSLPE : 1; + unsigned long MSTPC30 : 1; + unsigned long MSTPC29 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC26 : 1; + unsigned long : 5; + unsigned long MSTPC20 : 1; + unsigned long MSTPC19 : 1; + unsigned long : 17; + unsigned long MSTPC1 : 1; + unsigned long MSTPC0 : 1; +#endif + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 10; + unsigned long MSTPD10 : 1; + unsigned long : 4; + unsigned long MSTPD15 : 1; + unsigned long : 3; + unsigned long MSTPD19 : 1; + unsigned long : 11; + unsigned long MSTPD31 : 1; +#else + unsigned long MSTPD31 : 1; + unsigned long : 11; + unsigned long MSTPD19 : 1; + unsigned long : 3; + unsigned long MSTPD15 : 1; + unsigned long : 4; + unsigned long MSTPD10 : 1; + unsigned long : 10; +#endif + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKD : 4; + unsigned long : 4; + unsigned long PCKB : 4; + unsigned long PCKA : 4; + unsigned long BCK : 4; + unsigned long : 3; + unsigned long PSTOP1 : 1; + unsigned long ICK : 4; + unsigned long FCK : 4; +#else + unsigned long FCK : 4; + unsigned long ICK : 4; + unsigned long PSTOP1 : 1; + unsigned long : 3; + unsigned long BCK : 4; + unsigned long PCKA : 4; + unsigned long PCKB : 4; + unsigned long : 4; + unsigned long PCKD : 4; +#endif + } BIT; + } SCKCR; + char wk3[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKSEL : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CKSEL : 3; + unsigned short : 8; +#endif + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PLIDIV : 2; + unsigned short : 6; + unsigned short STC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short STC : 6; + unsigned short : 6; + unsigned short PLIDIV : 2; +#endif + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PLLEN : 1; +#endif + } BIT; + } PLLCR2; + char wk4[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short UPLIDIV : 2; + unsigned short : 2; + unsigned short UCKUPLLSEL : 1; + unsigned short : 3; + unsigned short USTC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short USTC : 6; + unsigned short : 3; + unsigned short UCKUPLLSEL : 1; + unsigned short : 2; + unsigned short UPLIDIV : 2; +#endif + } BIT; + } UPLLCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char UPLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char UPLLEN : 1; +#endif + } BIT; + } UPLLCR2; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCLKDIV : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCLKDIV : 1; +#endif + } BIT; + } BCKCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MEMWAIT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MEMWAIT : 1; +#endif + } BIT; + } MEMWAIT; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MOSTP : 1; +#endif + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SOSTP : 1; +#endif + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LCSTP : 1; +#endif + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ILCSTP : 1; +#endif + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HCSTP : 1; +#endif + } BIT; + } HOCOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCFRQ : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char HCFRQ : 2; +#endif + } BIT; + } HOCOCR2; + char wk6[4]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOOVF : 1; + unsigned char : 1; + unsigned char PLOVF : 1; + unsigned char HCOVF : 1; + unsigned char : 1; + unsigned char UPLOVF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char UPLOVF : 1; + unsigned char : 1; + unsigned char HCOVF : 1; + unsigned char PLOVF : 1; + unsigned char : 1; + unsigned char MOOVF : 1; +#endif + } BIT; + } OSCOVFSR; + char wk7[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKOSEL : 4; + unsigned short CKODIV : 3; + unsigned short CKOSTP : 1; +#else + unsigned short CKOSTP : 1; + unsigned short CKODIV : 3; + unsigned short CKOSEL : 4; + unsigned short : 8; +#endif + } BIT; + } CKOCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDIE : 1; + unsigned char : 6; + unsigned char OSTDE : 1; +#else + unsigned char OSTDE : 1; + unsigned char : 6; + unsigned char OSTDIE : 1; +#endif + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char OSTDF : 1; +#endif + } BIT; + } OSTDSR; + char wk8[30]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LOCOTRD : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char LOCOTRD : 5; +#endif + } BIT; + } LOCOTRR; + char wk9[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILOCOTRD : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ILOCOTRD : 5; +#endif + } BIT; + } ILOCOTRR; + char wk10[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOCOTRD : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char HOCOTRD : 6; +#endif + } BIT; + } HOCOTRR0; + char wk11[2]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOCOTRD : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char HOCOTRD : 6; +#endif + } BIT; + } HOCOTRR3; + char wk12[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OPCM : 3; + unsigned char : 1; + unsigned char OPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char OPCMTSF : 1; + unsigned char : 1; + unsigned char OPCM : 3; +#endif + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RSTCKSEL : 3; + unsigned char : 4; + unsigned char RSTCKEN : 1; +#else + unsigned char RSTCKEN : 1; + unsigned char : 4; + unsigned char RSTCKSEL : 3; +#endif + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MSTS : 5; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MSTS : 5; +#endif + } BIT; + } MOSCWTCR; + char wk13[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOPCM : 1; + unsigned char : 3; + unsigned char SOPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SOPCMTSF : 1; + unsigned char : 3; + unsigned char SOPCM : 1; +#endif + } BIT; + } SOPCCR; + char wk14[21]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IWDTRF : 1; + unsigned char WDTRF : 1; + unsigned char SWRF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SWRF : 1; + unsigned char WDTRF : 1; + unsigned char IWDTRF : 1; +#endif + } BIT; + } RSTSR2; + char wk15[1]; + unsigned short SWRR; + char wk16[28]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1IDTSEL : 2; + unsigned char LVD1IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD1IRQSEL : 1; + unsigned char LVD1IDTSEL : 2; +#endif + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1DET : 1; + unsigned char LVD1MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD1MON : 1; + unsigned char LVD1DET : 1; +#endif + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2IDTSEL : 2; + unsigned char LVD2IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD2IRQSEL : 1; + unsigned char LVD2IDTSEL : 2; +#endif + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2DET : 1; + unsigned char LVD2MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD2MON : 1; + unsigned char LVD2DET : 1; +#endif + } BIT; + } LVD2SR; + char wk17[794]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PRC0 : 1; + unsigned short PRC1 : 1; + unsigned short PRC2 : 1; + unsigned short PRC3 : 1; + unsigned short : 4; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 4; + unsigned short PRC3 : 1; + unsigned short PRC2 : 1; + unsigned short PRC1 : 1; + unsigned short PRC0 : 1; +#endif + } BIT; + } PRCR; + char wk18[48784]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PORF : 1; + unsigned char LVD0RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD2RF : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char LVD2RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD0RF : 1; + unsigned char PORF : 1; +#endif + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CWSF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CWSF : 1; +#endif + } BIT; + } RSTSR1; + char wk19[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char MODRV21 : 1; + unsigned char MOSEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MOSEL : 1; + unsigned char MODRV21 : 1; + unsigned char : 5; +#endif + } BIT; + } MOFCR; + char wk20[3]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char EXVCCINP2 : 1; + unsigned char : 1; + unsigned char LVD1E : 1; + unsigned char LVD2E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LVD2E : 1; + unsigned char LVD1E : 1; + unsigned char : 1; + unsigned char EXVCCINP2 : 1; + unsigned char : 3; +#endif + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1LVL : 4; + unsigned char LVD2LVL : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2LVL : 2; + unsigned char LVD1LVL : 4; +#endif + } BIT; + } LVDLVLR; + char wk21[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1RIE : 1; + unsigned char : 1; + unsigned char LVD1CMPE : 1; + unsigned char : 3; + unsigned char LVD1RI : 1; + unsigned char LVD1RN : 1; +#else + unsigned char LVD1RN : 1; + unsigned char LVD1RI : 1; + unsigned char : 3; + unsigned char LVD1CMPE : 1; + unsigned char : 1; + unsigned char LVD1RIE : 1; +#endif + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2RIE : 1; + unsigned char : 1; + unsigned char LVD2CMPE : 1; + unsigned char : 3; + unsigned char LVD2RI : 1; + unsigned char LVD2RN : 1; +#else + unsigned char LVD2RN : 1; + unsigned char LVD2RI : 1; + unsigned char : 3; + unsigned char LVD2CMPE : 1; + unsigned char : 1; + unsigned char LVD2RIE : 1; +#endif + } BIT; + } LVD2CR0; + char wk22[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char VBATTDIS : 1; + unsigned char : 3; + unsigned char VBTLVDEN : 1; + unsigned char : 1; + unsigned char VBTLVDLVL : 2; +#else + unsigned char VBTLVDLVL : 2; + unsigned char : 1; + unsigned char VBTLVDEN : 1; + unsigned char : 3; + unsigned char VBATTDIS : 1; +#endif + } BIT; + } VBATTCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char VBATRLVDETF : 1; + unsigned char VBTLVDMON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char VBTLVDMON : 1; + unsigned char VBATRLVDETF : 1; +#endif + } BIT; + } VBATTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char VBTLVDIE : 1; + unsigned char VBTLVDISEL : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char VBTLVDISEL : 1; + unsigned char VBTLVDIE : 1; +#endif + } BIT; + } VBTLVDICR; +}; + +struct st_tempsconst { + union { + unsigned long LONG; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long : 16; + unsigned long TSCD : 12; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long TSCD : 12; + unsigned long : 16; +#endif + } BIT; + } TSCDR; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCS : 1; +#endif + } BIT; + } TCSTR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char CCLR : 2; + unsigned char OVIE : 1; + unsigned char CMIEA : 1; + unsigned char CMIEB : 1; +#else + unsigned char CMIEB : 1; + unsigned char CMIEA : 1; + unsigned char OVIE : 1; + unsigned char CCLR : 2; + unsigned char : 3; +#endif + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSA : 2; + unsigned char OSB : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char OSB : 2; + unsigned char OSA : 2; +#endif + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 3; + unsigned char CSS : 2; + unsigned char : 2; + unsigned char TMRIS : 1; +#else + unsigned char TMRIS : 1; + unsigned char : 2; + unsigned char CSS : 2; + unsigned char CKS : 3; +#endif + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_tpu { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CST0 : 1; + unsigned char CST1 : 1; + unsigned char CST2 : 1; + unsigned char CST3 : 1; + unsigned char CST4 : 1; + unsigned char CST5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char CST5 : 1; + unsigned char CST4 : 1; + unsigned char CST3 : 1; + unsigned char CST2 : 1; + unsigned char CST1 : 1; + unsigned char CST0 : 1; +#endif + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SYNC0 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC3 : 1; + unsigned char SYNC4 : 1; + unsigned char SYNC5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char SYNC5 : 1; + unsigned char SYNC4 : 1; + unsigned char SYNC3 : 1; + unsigned char SYNC2 : 1; + unsigned char SYNC1 : 1; + unsigned char SYNC0 : 1; +#endif + } BIT; + } TSYR; +}; + +struct st_tpu0 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[7]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[22]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu2 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[37]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu3 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[52]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOC : 4; + unsigned char IOD : 4; +#else + unsigned char IOD : 4; + unsigned char IOC : 4; +#endif + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu4 { + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk0[67]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFAEN : 1; + unsigned char NFBEN : 1; + unsigned char NFCEN : 1; + unsigned char NFDEN : 1; + unsigned char NFCS : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char NFCS : 2; + unsigned char NFDEN : 1; + unsigned char NFCEN : 1; + unsigned char NFBEN : 1; + unsigned char NFAEN : 1; +#endif + } BIT; + } NFCR; + char wk1[82]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TPSC : 3; + unsigned char CKEG : 2; + unsigned char CCLR : 3; +#else + unsigned char CCLR : 3; + unsigned char CKEG : 2; + unsigned char TPSC : 3; +#endif + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MD : 4; + unsigned char BFA : 1; + unsigned char BFB : 1; + unsigned char ICSELB : 1; + unsigned char ICSELD : 1; +#else + unsigned char ICSELD : 1; + unsigned char ICSELB : 1; + unsigned char BFB : 1; + unsigned char BFA : 1; + unsigned char MD : 4; +#endif + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IOA : 4; + unsigned char IOB : 4; +#else + unsigned char IOB : 4; + unsigned char IOA : 4; +#endif + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGIEA : 1; + unsigned char TGIEB : 1; + unsigned char TGIEC : 1; + unsigned char TGIED : 1; + unsigned char TCIEV : 1; + unsigned char TCIEU : 1; + unsigned char : 1; + unsigned char TTGE : 1; +#else + unsigned char TTGE : 1; + unsigned char : 1; + unsigned char TCIEU : 1; + unsigned char TCIEV : 1; + unsigned char TGIED : 1; + unsigned char TGIEC : 1; + unsigned char TGIEB : 1; + unsigned char TGIEA : 1; +#endif + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TGFA : 1; + unsigned char TGFB : 1; + unsigned char TGFC : 1; + unsigned char TGFD : 1; + unsigned char TCFV : 1; + unsigned char TCFU : 1; + unsigned char : 1; + unsigned char TCFD : 1; +#else + unsigned char TCFD : 1; + unsigned char : 1; + unsigned char TCFU : 1; + unsigned char TCFV : 1; + unsigned char TGFD : 1; + unsigned char TGFC : 1; + unsigned char TGFB : 1; + unsigned char TGFA : 1; +#endif + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_usb0 { + union { + unsigned short WORD; +// struct { +// unsigned short :5; +// unsigned short SCKE:1; +// unsigned short :1; +// unsigned short CNEN:1; +// unsigned short :1; +// unsigned short DCFM:1; +// unsigned short DRPD:1; +// unsigned short DPRPU:1; +// unsigned short DMRPU:1; +// unsigned short :2; +// unsigned short USBE:1; +// } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short LNST : 2; + unsigned short IDMON : 1; + unsigned short : 3; + unsigned short HTACT : 1; + unsigned short : 7; + unsigned short OVCMON : 2; +#else + unsigned short OVCMON : 2; + unsigned short : 7; + unsigned short HTACT : 1; + unsigned short : 3; + unsigned short IDMON : 1; + unsigned short LNST : 2; +#endif + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :4; +// unsigned short HNPBTOA:1; +// unsigned short EXICEN:1; +// unsigned short VBUSEN:1; +// unsigned short WKUP:1; +// unsigned short RWUPE:1; +// unsigned short USBRST:1; +// unsigned short RESUME:1; +// unsigned short UACT:1; +// unsigned short :1; +// unsigned short RHST:3; +// } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short :3; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :2; +// unsigned short ISEL:1; +// unsigned short :1; +// unsigned short CURPIPE:4; +// } BIT; + } CFIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short VBSE:1; +// unsigned short RSME:1; +// unsigned short SOFE:1; +// unsigned short DVSE:1; +// unsigned short CTRE:1; +// unsigned short BEMPE:1; +// unsigned short NRDYE:1; +// unsigned short BRDYE:1; +// unsigned short :8; +// } BIT; + } INTENB0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCRE:1; +// unsigned short BCHGE:1; +// unsigned short :1; +// unsigned short DTCHE:1; +// unsigned short ATTCHE:1; +// unsigned short :4; +// unsigned short EOFERRE:1; +// unsigned short SIGNE:1; +// unsigned short SACKE:1; +// unsigned short :3; +// unsigned short PDDETINTE0:1; +// } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE9BRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BRDYE : 1; + unsigned short PIPE8BRDYE : 1; + unsigned short PIPE7BRDYE : 1; + unsigned short PIPE6BRDYE : 1; + unsigned short PIPE5BRDYE : 1; + unsigned short PIPE4BRDYE : 1; + unsigned short PIPE3BRDYE : 1; + unsigned short PIPE2BRDYE : 1; + unsigned short PIPE1BRDYE : 1; + unsigned short PIPE0BRDYE : 1; +#endif + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE9NRDYE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9NRDYE : 1; + unsigned short PIPE8NRDYE : 1; + unsigned short PIPE7NRDYE : 1; + unsigned short PIPE6NRDYE : 1; + unsigned short PIPE5NRDYE : 1; + unsigned short PIPE4NRDYE : 1; + unsigned short PIPE3NRDYE : 1; + unsigned short PIPE2NRDYE : 1; + unsigned short PIPE1NRDYE : 1; + unsigned short PIPE0NRDYE : 1; +#endif + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PIPE0BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE9BEMPE : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PIPE9BEMPE : 1; + unsigned short PIPE8BEMPE : 1; + unsigned short PIPE7BEMPE : 1; + unsigned short PIPE6BEMPE : 1; + unsigned short PIPE5BEMPE : 1; + unsigned short PIPE4BEMPE : 1; + unsigned short PIPE3BEMPE : 1; + unsigned short PIPE2BEMPE : 1; + unsigned short PIPE1BEMPE : 1; + unsigned short PIPE0BEMPE : 1; +#endif + } BIT; + } BEMPENB; + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short TRNENSEL:1; +// unsigned short :1; +// unsigned short BRDYM:1; +// unsigned short :1; +// unsigned short EDGESTS:1; +// unsigned short :4; +// } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; +// struct { +// unsigned short VBINT:1; +// unsigned short RESM:1; +// unsigned short SOFR:1; +// unsigned short DVST:1; +// unsigned short CTRT:1; +// unsigned short BEMP:1; +// unsigned short NRDY:1; +// unsigned short BRDY:1; +// unsigned short VBSTS:1; +// unsigned short DVSQ:3; +// unsigned short VALID:1; +// unsigned short CTSQ:3; +// } BIT; + } INTSTS0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCR:1; +// unsigned short BCHG:1; +// unsigned short :1; +// unsigned short DTCH:1; +// unsigned short ATTCH:1; +// unsigned short :4; +// unsigned short EOFERR:1; +// unsigned short SIGN:1; +// unsigned short SACK:1; +// unsigned short :3; +// unsigned short PDDETINT0:1; +// } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BRDY:1; +// unsigned short PIPE8BRDY:1; +// unsigned short PIPE7BRDY:1; +// unsigned short PIPE6BRDY:1; +// unsigned short PIPE5BRDY:1; +// unsigned short PIPE4BRDY:1; +// unsigned short PIPE3BRDY:1; +// unsigned short PIPE2BRDY:1; +// unsigned short PIPE1BRDY:1; +// unsigned short PIPE0BRDY:1; +// } BIT; + } BRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9NRDY:1; +// unsigned short PIPE8NRDY:1; +// unsigned short PIPE7NRDY:1; +// unsigned short PIPE6NRDY:1; +// unsigned short PIPE5NRDY:1; +// unsigned short PIPE4NRDY:1; +// unsigned short PIPE3NRDY:1; +// unsigned short PIPE2NRDY:1; +// unsigned short PIPE1NRDY:1; +// unsigned short PIPE0NRDY:1; +// } BIT; + } NRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BEMP:1; +// unsigned short PIPE8BEMP:1; +// unsigned short PIPE7BEMP:1; +// unsigned short PIPE6BEMP:1; +// unsigned short PIPE5BEMP:1; +// unsigned short PIPE4BEMP:1; +// unsigned short PIPE3BEMP:1; +// unsigned short PIPE2BEMP:1; +// unsigned short PIPE1BEMP:1; +// unsigned short PIPE0BEMP:1; +// } BIT; + } BEMPSTS; + union { + unsigned short WORD; +// struct { +// unsigned short OVRN:1; +// unsigned short CRCE:1; +// unsigned short :3; +// unsigned short FRNM:11; +// } BIT; + } FRMNUM; + char wk10[6]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BMREQUESTTYPE : 8; + unsigned short BREQUEST : 8; +#else + unsigned short BREQUEST : 8; + unsigned short BMREQUESTTYPE : 8; +#endif + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short :4; +// } BIT; + } DCPCFG; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :5; +// unsigned short MXPS:7; +// } BIT; + } DCPMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short SUREQ:1; +// unsigned short :2; +// unsigned short SUREQCLR:1; +// unsigned short :2; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :2; +// unsigned short CCPL:1; +// unsigned short PID:2; +// } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short PIPESEL:4; +// } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; +// struct { +// unsigned short TYPE:2; +// unsigned short :3; +// unsigned short BFRE:1; +// unsigned short DBLB:1; +// unsigned short :1; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short EPNUM:4; +// } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :3; +// unsigned short MXPS:9; +// } BIT; + } PIPEMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short :3; +// unsigned short IFIS:1; +// unsigned short :9; +// unsigned short IITV:3; +// } BIT; + } PIPEPERI; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE1CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE2CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE3CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE4CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE5CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE6CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE7CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE8CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[12]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RPDME0 : 1; + unsigned short IDPSRCE0 : 1; + unsigned short IDMSINKE0 : 1; + unsigned short VDPSRCE0 : 1; + unsigned short IDPSINKE0 : 1; + unsigned short VDMSRCE0 : 1; + unsigned short : 1; + unsigned short BATCHGE0 : 1; + unsigned short CHGDETSTS0 : 1; + unsigned short PDDETSTS0 : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short PDDETSTS0 : 1; + unsigned short CHGDETSTS0 : 1; + unsigned short BATCHGE0 : 1; + unsigned short : 1; + unsigned short VDMSRCE0 : 1; + unsigned short IDPSINKE0 : 1; + unsigned short VDPSRCE0 : 1; + unsigned short IDMSINKE0 : 1; + unsigned short IDPSRCE0 : 1; + unsigned short RPDME0 : 1; +#endif + } BIT; + } USBBCCTRL0; + char wk16[26]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short VDDUSBE : 1; + unsigned short : 6; + unsigned short VDCEN : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short VDCEN : 1; + unsigned short : 6; + unsigned short VDDUSBE : 1; +#endif + } BIT; + } USBMC; + char wk17[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD0; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD1; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD2; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD3; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD4; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD5; +}; + +struct st_wdt { + unsigned char WDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TOPS : 2; + unsigned short : 2; + unsigned short CKS : 4; + unsigned short RPES : 2; + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short RPSS : 2; + unsigned short : 2; + unsigned short RPES : 2; + unsigned short CKS : 4; + unsigned short : 2; + unsigned short TOPS : 2; +#endif + } BIT; + } WDTCR; + union { + unsigned short WORD; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CNTVAL : 14; + unsigned short UNDFF : 1; + unsigned short REFEF : 1; +#else + unsigned short REFEF : 1; + unsigned short UNDFF : 1; + unsigned short CNTVAL : 14; +#endif + } BIT; + } WDTSR; + union { + unsigned char BYTE; + struct { + +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char RSTIRQS : 1; +#else + unsigned char RSTIRQS : 1; + unsigned char : 7; +#endif + } BIT; + } WDTRCR; +}; + +enum enum_ir { +IR_BSC_BUSERR=16,IR_FCU_FRDYI=23, +IR_ICU_SWINT=27, +IR_CMT0_CMI0,IR_CMT1_CMI1, +IR_CMT2_CMI2,IR_CMT3_CMI3, +IR_CAC_FERRF,IR_CAC_MENDF,IR_CAC_OVFF, +IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0, +IR_SDHI_SBFAI=40,IR_SDHI_CDETI,IR_SDHI_CACI,IR_SDHI_SDACI, +IR_RSPI0_SPEI0,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_RSCAN_COMFRXINT=52,IR_RSCAN_RXFINT,IR_RSCAN_TXINT,IR_RSCAN_CHERRINT,IR_RSCAN_GLERRINT, +IR_DOC_DOPCF, +IR_CMPB_CMPB0,IR_CMPB_CMPB1, +IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN, +IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ELC_ELSR8I=80, +IR_LVD_LVD1=88,IR_LVD_LVD2, +IR_CMPA_CMPA1=88,IR_CMPA_CMPA2, +IR_USB0_USBR0, +IR_VBATT_VBTLVDI, +IR_RTC_ALM,IR_RTC_PRD, +IR_S12AD_S12ADI0=102,IR_S12AD_GBADI, +IR_CMPB1_CMPB2,IR_CMPB1_CMPB3, +IR_ELC_ELSR18I,IR_ELC_ELSR19I, +IR_SSI0_SSIF0,IR_SSI0_SSIRXI0,IR_SSI0_SSITXI0, +IR_SECURITY_RD,IR_SECURITY_WR,IR_SECURITY_ERR, +IR_MTU0_TGIA0,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_TPU0_TGI0A,IR_TPU0_TGI0B,IR_TPU0_TGI0C,IR_TPU0_TGI0D,IR_TPU0_TCI0V, +IR_TPU1_TGI1A,IR_TPU1_TGI1B,IR_TPU1_TCI1V,IR_TPU1_TCI1U, +IR_TPU2_TGI2A,IR_TPU2_TGI2B,IR_TPU2_TCI2V,IR_TPU2_TCI2U, +IR_TPU3_TGI3A,IR_TPU3_TGI3B,IR_TPU3_TGI3C,IR_TPU3_TGI3D,IR_TPU3_TCI3V, +IR_TPU4_TGI4A,IR_TPU4_TGI4B,IR_TPU4_TCI4V,IR_TPU4_TCI4U, +IR_TPU5_TGI5A,IR_TPU5_TGI5B,IR_TPU5_TCI5V,IR_TPU5_TCI5U, +IR_POE_OEI1=170,IR_POE_OEI2, +IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_DMAC_DMAC0I=198,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I, +IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8, +IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9, +IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3, +IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0 +}; + +enum enum_dtce { +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0,DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2,DTCE_CMT3_CMI3, +DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0, +DTCE_SDHI_SBFAI=40, +DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0, +DTCE_RSCAN_COMFRXINT=52, +DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1, +DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD, +DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI, +DTCE_CMPB1_CMPB2,DTCE_CMPB1_CMPB3, +DTCE_ELC_ELSR18I,DTCE_ELC_ELSR19I, +DTCE_SSI0_SSIRXI0=109,DTCE_SSI0_SSITXI0, +DTCE_SECURITY_RD,DTCE_SECURITY_WR, +DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0, +DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1, +DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2, +DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3, +DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_TPU0_TGI0A,DTCE_TPU0_TGI0B,DTCE_TPU0_TGI0C,DTCE_TPU0_TGI0D, +DTCE_TPU1_TGI1A=147,DTCE_TPU1_TGI1B, +DTCE_TPU2_TGI2A=151,DTCE_TPU2_TGI2B, +DTCE_TPU3_TGI3A=155,DTCE_TPU3_TGI3B,DTCE_TPU3_TGI3C,DTCE_TPU3_TGI3D, +DTCE_TPU4_TGI4A=160,DTCE_TPU4_TGI4B, +DTCE_TPU5_TGI5A=164,DTCE_TPU5_TGI5B, +DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0, +DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1, +DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2, +DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3, +DTCE_DMAC_DMAC0I=198,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1, +DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6, +DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9, +DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12, +DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03,IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03,IER_CMT3_CMI3=0x03, +IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04, +IER_SDHI_SBFAI=0x05,IER_SDHI_CDETI=0x05,IER_SDHI_CACI=0x05,IER_SDHI_SDACI=0x05, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_RSCAN_COMFRXINT=0x06,IER_RSCAN_RXFINT=0x06,IER_RSCAN_TXINT=0x06,IER_RSCAN_CHERRINT=0x06,IER_RSCAN_GLERRINT=0x07, +IER_DOC_DOPCF=0x07, +IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07, +IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07, +IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ELC_ELSR8I=0x0A, +IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B, +IER_CMPA_CMPA1=0x0B,IER_CMPA_CMPA2=0x0B, +IER_USB0_USBR0=0x0B, +IER_VBATT_VBTLVDI=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C, +IER_CMPB1_CMPB2=0x0D,IER_CMPB1_CMPB3=0x0D, +IER_ELC_ELSR18I=0x0D,IER_ELC_ELSR19I=0x0D, +IER_SSI0_SSIF0=0x0D,IER_SSI0_SSIRXI0=0x0D,IER_SSI0_SSITXI0=0x0D, +IER_SECURITY_RD=0x0D,IER_SECURITY_WR=0x0E,IER_SECURITY_ERR=0x0E, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11, +IER_TPU0_TGI0A=0x11,IER_TPU0_TGI0B=0x11,IER_TPU0_TGI0C=0x12,IER_TPU0_TGI0D=0x12,IER_TPU0_TCI0V=0x12, +IER_TPU1_TGI1A=0x12,IER_TPU1_TGI1B=0x12,IER_TPU1_TCI1V=0x12,IER_TPU1_TCI1U=0x12, +IER_TPU2_TGI2A=0x12,IER_TPU2_TGI2B=0x13,IER_TPU2_TCI2V=0x13,IER_TPU2_TCI2U=0x13, +IER_TPU3_TGI3A=0x13,IER_TPU3_TGI3B=0x13,IER_TPU3_TGI3C=0x13,IER_TPU3_TGI3D=0x13,IER_TPU3_TCI3V=0x13, +IER_TPU4_TGI4A=0x14,IER_TPU4_TGI4B=0x14,IER_TPU4_TCI4V=0x14,IER_TPU4_TCI4U=0x14, +IER_TPU5_TGI5A=0x14,IER_TPU5_TGI5B=0x14,IER_TPU5_TCI5V=0x14,IER_TPU5_TCI5U=0x14, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_DMAC_DMAC0I=0x18,IER_DMAC_DMAC1I=0x18,IER_DMAC_DMAC2I=0x19,IER_DMAC_DMAC3I=0x19, +IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C, +IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C, +IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D, +IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D, +IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E, +IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_FCU_FRDYI=2, +IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4,IPR_CMT1_CMI1=5, +IPR_CMT2_CMI2=6,IPR_CMT3_CMI3=7, +IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34, +IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38, +IPR_SDHI_SBFAI=40,IPR_SDHI_CDETI=41,IPR_SDHI_CACI=42,IPR_SDHI_SDACI=43, +IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44, +IPR_RSCAN_COMFRXINT=52,IPR_RSCAN_RXFINT=53,IPR_RSCAN_TXINT=54,IPR_RSCAN_CHERRINT=55,IPR_RSCAN_GLERRINT=56, +IPR_DOC_DOPCF=57, +IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59, +IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60, +IPR_RTC_CUP=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_ELC_ELSR8I=80, +IPR_LVD_LVD1=88,IPR_LVD_LVD2=89, +IPR_CMPA_CMPA1=88,IPR_CMPA_CMPA2=89, +IPR_USB0_USBR0=90, +IPR_VBATT_VBTLVDI=91, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103, +IPR_CMPB1_CMPB2=104,IPR_CMPB1_CMPB3=105, +IPR_ELC_ELSR18I=106,IPR_ELC_ELSR19I=107, +IPR_SSI0_SSIF0=108,IPR_SSI0_SSIRXI0=108,IPR_SSI0_SSITXI0=108, +IPR_SECURITY_RD=111,IPR_SECURITY_WR=111,IPR_SECURITY_ERR=113, +IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118, +IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123, +IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127, +IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133, +IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138, +IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139, +IPR_TPU0_TGI0A=142,IPR_TPU0_TGI0B=142,IPR_TPU0_TGI0C=142,IPR_TPU0_TGI0D=142,IPR_TPU0_TCI0V=146, +IPR_TPU1_TGI1A=147,IPR_TPU1_TGI1B=147,IPR_TPU1_TCI1V=149,IPR_TPU1_TCI1U=149, +IPR_TPU2_TGI2A=151,IPR_TPU2_TGI2B=151,IPR_TPU2_TCI2V=153,IPR_TPU2_TCI2U=153, +IPR_TPU3_TGI3A=155,IPR_TPU3_TGI3B=155,IPR_TPU3_TGI3C=155,IPR_TPU3_TGI3D=155,IPR_TPU3_TCI3V=159, +IPR_TPU4_TGI4A=160,IPR_TPU4_TGI4B=160,IPR_TPU4_TCI4V=162,IPR_TPU4_TCI4U=162, +IPR_TPU5_TGI5A=164,IPR_TPU5_TGI5B=164,IPR_TPU5_TCI5V=166,IPR_TPU5_TCI5U=166, +IPR_POE_OEI1=170,IPR_POE_OEI2=171, +IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174, +IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177, +IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180, +IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183, +IPR_DMAC_DMAC0I=198,IPR_DMAC_DMAC1I=199,IPR_DMAC_DMAC2I=200,IPR_DMAC_DMAC3I=201, +IPR_SCI0_ERI0=214,IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214, +IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218, +IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222, +IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226, +IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230, +IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234, +IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245, +IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249, +IPR_BSC_=0, +IPR_FCU_=2, +IPR_RSPI0_=44, +IPR_DOC_=57, +IPR_VBATT_=91, +IPR_MTU1_TGI=121, +IPR_MTU1_TCI=123, +IPR_MTU2_TGI=125, +IPR_MTU2_TCI=127, +IPR_MTU3_TGI=129, +IPR_MTU4_TGI=134, +IPR_MTU5_=139, +IPR_MTU5_TGI=139, +IPR_TPU0_TGI=142, +IPR_TPU1_TGI=147, +IPR_TPU1_TCI=149, +IPR_TPU2_TGI=151, +IPR_TPU2_TCI=153, +IPR_TPU3_TGI=155, +IPR_TPU4_TGI=160, +IPR_TPU4_TCI=162, +IPR_TPU5_TGI=164, +IPR_TPU5_TCI=166, +IPR_TMR0_=174, +IPR_TMR1_=177, +IPR_TMR2_=180, +IPR_TMR3_=183, +IPR_SCI0_=214, +IPR_SCI1_=218, +IPR_SCI5_=222, +IPR_SCI6_=226, +IPR_SCI8_=230, +IPR_SCI9_=234 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_CAC_FERRF IEN0 +#define IEN_CAC_MENDF IEN1 +#define IEN_CAC_OVFF IEN2 +#define IEN_USB0_D0FIFO0 IEN4 +#define IEN_USB0_D1FIFO0 IEN5 +#define IEN_USB0_USBI0 IEN6 +#define IEN_SDHI_SBFAI IEN0 +#define IEN_SDHI_CDETI IEN1 +#define IEN_SDHI_CACI IEN2 +#define IEN_SDHI_SDACI IEN3 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_RSCAN_COMFRXINT IEN4 +#define IEN_RSCAN_RXFINT IEN5 +#define IEN_RSCAN_TXINT IEN6 +#define IEN_RSCAN_CHERRINT IEN7 +#define IEN_RSCAN_GLERRINT IEN0 +#define IEN_DOC_DOPCF IEN1 +#define IEN_CMPB_CMPB0 IEN2 +#define IEN_CMPB_CMPB1 IEN3 +#define IEN_CTSU_CTSUWR IEN4 +#define IEN_CTSU_CTSURD IEN5 +#define IEN_CTSU_CTSUFN IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ELC_ELSR8I IEN0 +#define IEN_LVD_LVD1 IEN0 +#define IEN_LVD_LVD2 IEN1 +#define IEN_CMPA_CMPA1 IEN0 +#define IEN_CMPA_CMPA2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_VBATT_VBTLVDI IEN3 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_S12AD_S12ADI0 IEN6 +#define IEN_S12AD_GBADI IEN7 +#define IEN_CMPB1_CMPB2 IEN0 +#define IEN_CMPB1_CMPB3 IEN1 +#define IEN_ELC_ELSR18I IEN2 +#define IEN_ELC_ELSR19I IEN3 +#define IEN_SSI0_SSIF0 IEN4 +#define IEN_SSI0_SSIRXI0 IEN5 +#define IEN_SSI0_SSITXI0 IEN6 +#define IEN_SECURITY_RD IEN7 +#define IEN_SECURITY_WR IEN0 +#define IEN_SECURITY_ERR IEN1 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN5 +#define IEN_TPU0_TGI0A IEN6 +#define IEN_TPU0_TGI0B IEN7 +#define IEN_TPU0_TGI0C IEN0 +#define IEN_TPU0_TGI0D IEN1 +#define IEN_TPU0_TCI0V IEN2 +#define IEN_TPU1_TGI1A IEN3 +#define IEN_TPU1_TGI1B IEN4 +#define IEN_TPU1_TCI1V IEN5 +#define IEN_TPU1_TCI1U IEN6 +#define IEN_TPU2_TGI2A IEN7 +#define IEN_TPU2_TGI2B IEN0 +#define IEN_TPU2_TCI2V IEN1 +#define IEN_TPU2_TCI2U IEN2 +#define IEN_TPU3_TGI3A IEN3 +#define IEN_TPU3_TGI3B IEN4 +#define IEN_TPU3_TGI3C IEN5 +#define IEN_TPU3_TGI3D IEN6 +#define IEN_TPU3_TCI3V IEN7 +#define IEN_TPU4_TGI4A IEN0 +#define IEN_TPU4_TGI4B IEN1 +#define IEN_TPU4_TCI4V IEN2 +#define IEN_TPU4_TCI4U IEN3 +#define IEN_TPU5_TGI5A IEN4 +#define IEN_TPU5_TGI5B IEN5 +#define IEN_TPU5_TCI5V IEN6 +#define IEN_TPU5_TCI5U IEN7 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_DMAC_DMAC0I IEN6 +#define IEN_DMAC_DMAC1I IEN7 +#define IEN_DMAC_DMAC2I IEN0 +#define IEN_DMAC_DMAC3I IEN1 +#define IEN_SCI0_ERI0 IEN6 +#define IEN_SCI0_RXI0 IEN7 +#define IEN_SCI0_TXI0 IEN0 +#define IEN_SCI0_TEI0 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI5_ERI5 IEN6 +#define IEN_SCI5_RXI5 IEN7 +#define IEN_SCI5_TXI5 IEN0 +#define IEN_SCI5_TEI5 IEN1 +#define IEN_SCI6_ERI6 IEN2 +#define IEN_SCI6_RXI6 IEN3 +#define IEN_SCI6_TXI6 IEN4 +#define IEN_SCI6_TEI6 IEN5 +#define IEN_SCI8_ERI8 IEN6 +#define IEN_SCI8_RXI8 IEN7 +#define IEN_SCI8_TXI8 IEN0 +#define IEN_SCI8_TEI8 IEN1 +#define IEN_SCI9_ERI9 IEN2 +#define IEN_SCI9_RXI9 IEN3 +#define IEN_SCI9_TXI9 IEN4 +#define IEN_SCI9_TEI9 IEN5 +#define IEN_SCI12_ERI12 IEN6 +#define IEN_SCI12_RXI12 IEN7 +#define IEN_SCI12_TXI12 IEN0 +#define IEN_SCI12_TEI12 IEN1 +#define IEN_SCI12_SCIX0 IEN2 +#define IEN_SCI12_SCIX1 IEN3 +#define IEN_SCI12_SCIX2 IEN4 +#define IEN_SCI12_SCIX3 IEN5 +#define IEN_RIIC0_EEI0 IEN6 +#define IEN_RIIC0_RXI0 IEN7 +#define IEN_RIIC0_TXI0 IEN0 +#define IEN_RIIC0_TEI0 IEN1 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_CAC_FERRF 32 +#define VECT_CAC_MENDF 33 +#define VECT_CAC_OVFF 34 +#define VECT_USB0_D0FIFO0 36 +#define VECT_USB0_D1FIFO0 37 +#define VECT_USB0_USBI0 38 +#define VECT_SDHI_SBFAI 40 +#define VECT_SDHI_CDETI 41 +#define VECT_SDHI_CACI 42 +#define VECT_SDHI_SDACI 43 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_RSCAN_COMFRXINT 52 +#define VECT_RSCAN_RXFINT 53 +#define VECT_RSCAN_TXINT 54 +#define VECT_RSCAN_CHERRINT 55 +#define VECT_RSCAN_GLERRINT 56 +#define VECT_DOC_DOPCF 57 +#define VECT_CMPB_CMPB0 58 +#define VECT_CMPB_CMPB1 59 +#define VECT_CTSU_CTSUWR 60 +#define VECT_CTSU_CTSURD 61 +#define VECT_CTSU_CTSUFN 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ELC_ELSR8I 80 +#define VECT_LVD_LVD1 88 +#define VECT_LVD_LVD2 89 +#define VECT_CMPA_CMPA1 88 +#define VECT_CMPA_CMPA2 89 +#define VECT_USB0_USBR0 90 +#define VECT_VBATT_VBTLVDI 91 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_S12AD_S12ADI0 102 +#define VECT_S12AD_GBADI 103 +#define VECT_CMPB1_CMPB2 104 +#define VECT_CMPB1_CMPB3 105 +#define VECT_ELC_ELSR18I 106 +#define VECT_ELC_ELSR19I 107 +#define VECT_SSI0_SSIF0 108 +#define VECT_SSI0_SSIRXI0 109 +#define VECT_SSI0_SSITXI0 110 +#define VECT_SECURITY_RD 111 +#define VECT_SECURITY_WR 112 +#define VECT_SECURITY_ERR 113 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_TPU0_TGI0A 142 +#define VECT_TPU0_TGI0B 143 +#define VECT_TPU0_TGI0C 144 +#define VECT_TPU0_TGI0D 145 +#define VECT_TPU0_TCI0V 146 +#define VECT_TPU1_TGI1A 147 +#define VECT_TPU1_TGI1B 148 +#define VECT_TPU1_TCI1V 149 +#define VECT_TPU1_TCI1U 150 +#define VECT_TPU2_TGI2A 151 +#define VECT_TPU2_TGI2B 152 +#define VECT_TPU2_TCI2V 153 +#define VECT_TPU2_TCI2U 154 +#define VECT_TPU3_TGI3A 155 +#define VECT_TPU3_TGI3B 156 +#define VECT_TPU3_TGI3C 157 +#define VECT_TPU3_TGI3D 158 +#define VECT_TPU3_TCI3V 159 +#define VECT_TPU4_TGI4A 160 +#define VECT_TPU4_TGI4B 161 +#define VECT_TPU4_TCI4V 162 +#define VECT_TPU4_TCI4U 163 +#define VECT_TPU5_TGI5A 164 +#define VECT_TPU5_TGI5B 165 +#define VECT_TPU5_TCI5V 166 +#define VECT_TPU5_TCI5U 167 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_DMAC_DMAC0I 198 +#define VECT_DMAC_DMAC1I 199 +#define VECT_DMAC_DMAC2I 200 +#define VECT_DMAC_DMAC3I 201 +#define VECT_SCI0_ERI0 214 +#define VECT_SCI0_RXI0 215 +#define VECT_SCI0_TXI0 216 +#define VECT_SCI0_TEI0 217 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI5_ERI5 222 +#define VECT_SCI5_RXI5 223 +#define VECT_SCI5_TXI5 224 +#define VECT_SCI5_TEI5 225 +#define VECT_SCI6_ERI6 226 +#define VECT_SCI6_RXI6 227 +#define VECT_SCI6_TXI6 228 +#define VECT_SCI6_TEI6 229 +#define VECT_SCI8_ERI8 230 +#define VECT_SCI8_RXI8 231 +#define VECT_SCI8_TXI8 232 +#define VECT_SCI8_TEI8 233 +#define VECT_SCI9_ERI9 234 +#define VECT_SCI9_RXI9 235 +#define VECT_SCI9_TXI9 236 +#define VECT_SCI9_TEI9 237 +#define VECT_SCI12_ERI12 238 +#define VECT_SCI12_RXI12 239 +#define VECT_SCI12_TXI12 240 +#define VECT_SCI12_TEI12 241 +#define VECT_SCI12_SCIX0 242 +#define VECT_SCI12_SCIX1 243 +#define VECT_SCI12_SCIX2 244 +#define VECT_SCI12_SCIX3 245 +#define VECT_RIIC0_EEI0 246 +#define VECT_RIIC0_RXI0 247 +#define VECT_RIIC0_TXI0 248 +#define VECT_RIIC0_TEI0 249 + +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_RSCAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_IRDA SYSTEM.MSTPCRC.BIT.MSTPC20 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_SDHI SYSTEM.MSTPCRD.BIT.MSTPD19 +#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15 +#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define BSC (*(volatile struct st_bsc *)0x81300) +#define CAC (*(volatile struct st_cac *)0x8B000) +#define CMPB (*(volatile struct st_cmpb *)0x8C580) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 *)0x88018) +#define CRC (*(volatile struct st_crc *)0x88280) +#define CTSU (*(volatile struct st_ctsu *)0xA0900) +#define DA (*(volatile struct st_da *)0x88040) +#define DMAC (*(volatile struct st_dmac *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 *)0x820C0) +#define DOC (*(volatile struct st_doc *)0x8B080) +#define DTC (*(volatile struct st_dtc *)0x82400) +#define ELC (*(volatile struct st_elc *)0x8B100) +#define FLASH (*(volatile struct st_flash *)0x7FC090) +#define FLASHCONST (*(volatile struct st_flashconst *)0x7FC350) +#define ICU (*(volatile struct st_icu *)0x87000) +#define IRDA (*(volatile struct st_irda *)0x88410) +#define IWDT (*(volatile struct st_iwdt *)0x88030) +#define LPT (*(volatile struct st_lpt *)0x800B0) +#define MPC (*(volatile struct st_mpc *)0x8C100) +#define MPU (*(volatile struct st_mpu *)0x86400) +#define MTU (*(volatile struct st_mtu *)0xD0A0A) +#define MTU0 (*(volatile struct st_mtu0 *)0xD0A90) +#define MTU1 (*(volatile struct st_mtu1 *)0xD0A90) +#define MTU2 (*(volatile struct st_mtu2 *)0xD0A92) +#define MTU3 (*(volatile struct st_mtu3 *)0xD0A00) +#define MTU4 (*(volatile struct st_mtu4 *)0xD0A00) +#define MTU5 (*(volatile struct st_mtu5 *)0xD0A94) +#define POE (*(volatile struct st_poe *)0x88900) +#define PORT (*(volatile struct st_port *)0x8C120) +#define PORT0 (*(volatile struct st_port0 *)0x8C000) +#define PORT1 (*(volatile struct st_port1 *)0x8C001) +#define PORT2 (*(volatile struct st_port2 *)0x8C002) +#define PORT3 (*(volatile struct st_port3 *)0x8C003) +#define PORT4 (*(volatile struct st_port4 *)0x8C004) +#define PORT5 (*(volatile struct st_port5 *)0x8C005) +#define PORTA (*(volatile struct st_porta *)0x8C00A) +#define PORTB (*(volatile struct st_portb *)0x8C00B) +#define PORTC (*(volatile struct st_portc *)0x8C00C) +#define PORTD (*(volatile struct st_portd *)0x8C00D) +#define PORTE (*(volatile struct st_porte *)0x8C00E) +#define PORTH (*(volatile struct st_porth *)0x8C011) +#define PORTJ (*(volatile struct st_portj *)0x8C012) +#define RIIC0 (*(volatile struct st_riic *)0x88300) +#define RSCAN (*(volatile struct st_rscan *)0xA8322) +#define RSCAN0 (*(volatile struct st_rscan0 *)0xA8300) +#define RSPI0 (*(volatile struct st_rspi *)0x88380) +#define RTC (*(volatile struct st_rtc *)0x8C400) +#define S12AD (*(volatile struct st_s12ad *)0x89000) +#define SCI0 (*(volatile struct st_sci0 *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 *)0x8A020) +#define SCI5 (*(volatile struct st_sci0 *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 *)0x8A0C0) +#define SCI8 (*(volatile struct st_sci0 *)0x8A100) +#define SCI9 (*(volatile struct st_sci0 *)0x8A120) +#define SCI12 (*(volatile struct st_sci12 *)0x8B300) +#define SDHI (*(volatile struct st_sdhi *)0x8AC00) +#define SMCI0 (*(volatile struct st_smci *)0x8A000) +#define SMCI1 (*(volatile struct st_smci *)0x8A020) +#define SMCI2 (*(volatile struct st_smci *)0x8A040) +#define SMCI3 (*(volatile struct st_smci *)0x8A060) +#define SMCI4 (*(volatile struct st_smci *)0x8A080) +#define SMCI5 (*(volatile struct st_smci *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci *)0x8A0C0) +#define SMCI7 (*(volatile struct st_smci *)0x8A0E0) +#define SMCI8 (*(volatile struct st_smci *)0x8A100) +#define SMCI9 (*(volatile struct st_smci *)0x8A120) +#define SMCI10 (*(volatile struct st_smci *)0x8A140) +#define SMCI11 (*(volatile struct st_smci *)0x8A150) +#define SMCI12 (*(volatile struct st_smci *)0x8B300) +#define SSI0 (*(volatile struct st_ssi *)0x8A500) +#define SYSTEM (*(volatile struct st_system *)0x80000) +#define TEMPSCONST (*(volatile struct st_tempsconst *)0x7FC0A0) +#define TMR0 (*(volatile struct st_tmr0 *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 *)0x88214) +#define TPU (*(volatile struct st_tpu *)0x88100) +#define TPU0 (*(volatile struct st_tpu0 *)0x88108) +#define TPU1 (*(volatile struct st_tpu1 *)0x88108) +#define TPU2 (*(volatile struct st_tpu2 *)0x8810A) +#define TPU3 (*(volatile struct st_tpu3 *)0x8810A) +#define TPU4 (*(volatile struct st_tpu4 *)0x8810C) +#define TPU5 (*(volatile struct st_tpu5 *)0x8810C) +#define USB0 (*(volatile struct st_usb0 *)0xA0000) +#define WDT (*(volatile struct st_wdt *)0x88020) + +#pragma pack() +#endif + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/main.c b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/main.c new file mode 100644 index 000000000..409c03775 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_GCC_e2studio_IAR/src/main.c @@ -0,0 +1,251 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup, standard FreeRTOS hook functions, and the ISR hander called + * by the RTOS after interrupt entry (including nesting) has been taken care of. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +/* Start user code. Do not edit comment generated here */ +uint16_t usProtectDummy = ( uint16_t ) ( SYSTEM.PRCR.WORD & 0x000FU ); + + /* Disable protect bit */ + SYSTEM.PRCR.WORD = 0xA50FU; + + SYSTEM.VBATTCR.BYTE = 0x81U; + + /* Restore the previous state of the protect register */ + SYSTEM.PRCR.WORD = ( uint16_t )( 0xA500U | usProtectDummy ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* The RX port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. */ +void vApplicationSetupTimerInterrupt( void ) +{ +const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL; + + /* Disable register write protection. */ + SYSTEM.PRCR.WORD = ulEnableRegisterWrite; + + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; + + /* Reneable register protection. */ + SYSTEM.PRCR.WORD = ulDisableRegisterWrite; +} + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.HardwareDebuglinker b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.HardwareDebuglinker new file mode 100644 index 000000000..9eb2fea9d --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.HardwareDebuglinker @@ -0,0 +1,35 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.cproject b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.cproject new file mode 100644 index 000000000..5b2301311 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.cproject @@ -0,0 +1,157 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.info b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.info new file mode 100644 index 000000000..7a5b86fda --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.info @@ -0,0 +1,6 @@ +TOOL_CHAIN=Renesas RXC Toolchain +VERSION=v2.03.00 +TC_INSTALL=C:\devtools\Renesas\RX\2_3_0\ +VERSION_IDE= +E2STUDIO_VERSION=4.0.2.008 +ACTIVE_CONFIGURATION=HardwareDebug \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.project b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.project new file mode 100644 index 000000000..2d5073011 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.project @@ -0,0 +1,232 @@ + + + RTOSDemo + + + + + + com.renesas.cdt.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.renesas.cdt.core.kpitcnature + com.renesas.cdt.core.kpitccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1442942249601 + src/FreeRTOS_Source + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-croutine.c + + + + 1442942274534 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1442942274544 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-Renesas + + + + 1442947187801 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-BlockQ.c + + + + 1442947187811 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1442947187821 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1442947187821 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-death.c + + + + 1442947187831 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1442947187831 + src/Full_Demo/Standard_Demo_Tasks + 5 + + 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b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/CodeGenerator/cgprojectDatas.datas @@ -0,0 +1,3 @@ +# +#Tue Sep 22 17:05:11 BST 2015 +CGExist=true diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Dependency_Scan_Preferences.prefs b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Dependency_Scan_Preferences.prefs new file mode 100644 index 000000000..c52c797ff --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Dependency_Scan_Preferences.prefs @@ -0,0 +1,4 @@ +Build\ project\ excluding\ the\ dependencies=false +Re-generate\ and\ use\ dependencies\ during\ project\ build=true +Use\ existing\ dependencies\ during\ project\ build=false +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Project_Generation_Prefrences.prefs b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Project_Generation_Prefrences.prefs new file mode 100644 index 000000000..fa4334b2e --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/.settings/Project_Generation_Prefrences.prefs @@ -0,0 +1,54 @@ +com.renesas.cdt.renesas.Assembler.option.userDefine=-nologo;;; +com.renesas.cdt.renesas.Compiler.option.C=com.renesas.cdt.renesas.Compiler.option.C89 +com.renesas.cdt.renesas.Compiler.option.UserDef=-nologo; +com.renesas.cdt.renesas.Compiler.option.defines=__RX; +com.renesas.cdt.renesas.Compiler.option.incFileDirectories="${TCINSTALL}/include"; +com.renesas.cdt.renesas.Configurator.option.cfgPath="" +com.renesas.cdt.renesas.Configurator.option.rtosName=None +com.renesas.cdt.renesas.Configurator.option.rtosPath="" +com.renesas.cdt.renesas.Configurator.option.rtosVersion=None +com.renesas.cdt.renesas.Linker.option.rom=D\=R;D_1\=R_1;D_2\=R_2; +com.renesas.cdt.renesas.Linker.option.typeOfOutputFileOption=Stype via absolute +com.renesas.cdt.renesas.StandardLibrary.option.complexC99=false +com.renesas.cdt.renesas.StandardLibrary.option.ctypec89=false +com.renesas.cdt.renesas.StandardLibrary.option.fenvC99=false +com.renesas.cdt.renesas.StandardLibrary.option.inttypesC99=false +com.renesas.cdt.renesas.StandardLibrary.option.libConfiguration=C(C89) +com.renesas.cdt.renesas.StandardLibrary.option.mathc89=false +com.renesas.cdt.renesas.StandardLibrary.option.mathfc89=false +com.renesas.cdt.renesas.StandardLibrary.option.mode=com.renesas.cdt.renesas.StandardLibrary.option.buildOnlyWhenOptionsChanged +com.renesas.cdt.renesas.StandardLibrary.option.runtime=true +com.renesas.cdt.renesas.StandardLibrary.option.rxccomplexCPP=false +com.renesas.cdt.renesas.StandardLibrary.option.rxciosCPP=false +com.renesas.cdt.renesas.StandardLibrary.option.rxcnewCPP=false +com.renesas.cdt.renesas.StandardLibrary.option.rxcstringCPP=false +com.renesas.cdt.renesas.StandardLibrary.option.stdargc89=false +com.renesas.cdt.renesas.StandardLibrary.option.stdioc89=false +com.renesas.cdt.renesas.StandardLibrary.option.stdlibc89=true +com.renesas.cdt.renesas.StandardLibrary.option.stringc89=true +com.renesas.cdt.renesas.StandardLibrary.option.wcharC99=false +com.renesas.cdt.renesas.StandardLibrary.option.wctypeC99=false +com.renesas.cdt.rxc.HardwareDebug.Assembler.option.endian=Little-endian data +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.RAM=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.ROM=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.address=00000000 +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.addressRegister=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.allocLowerBit=Lower bit +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.cpuType=RX200 +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.denormalized=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.endian=Little-endian data +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.enumSize=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.packStructures=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.patchCode=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.precisionDouble=Single precision +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.registerFastInterrupt=None +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.replaceFromIntWithShort=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.roundTo=Nearest +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.saveacc=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signBitField=unsigned +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.signChar=unsigned +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.useDynamic=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.useTry=false +com.renesas.cdt.rxc.HardwareDebug.Compiler.option.widthDivergence=24 bit +com.renesas.cdt.rxc.HardwareDebug.StandardLibrary.option.endian=Little-endian data +eclipse.preferences.version=1 diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch new file mode 100644 index 000000000..62208bac8 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/RTOSDemo HardwareDebug.launch @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/custom.bat b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/custom.bat new file mode 100644 index 000000000..e69de29bb diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/makefile.init b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/makefile.init new file mode 100644 index 000000000..6e9134b91 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/makefile.init @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +export INC_RX=C:\devtools\Renesas\RX\2_3_0\include +export RXC_LIB=C:\devtools\Renesas\RX\2_3_0\bin +export BIN_RX=C:\devtools\Renesas\RX\2_3_0\bin +PATH := $(PATH):C:\devtools\Renesas\RX\2_3_0\bin \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..0a919d156 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,230 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { +//_RB_ LED0 = !LED0; + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/FreeRTOSConfig.h new file mode 100644 index 000000000..ff23b62c2 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/FreeRTOSConfig.h @@ -0,0 +1,182 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/* Renesas hardware definition header. */ +#include "iodefine.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( 52000000UL ) /*_RB_ guess*/ +#define configPERIPHERAL_CLOCK_HZ ( 26000000UL ) /*_RB_ guess*/ +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 12 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_CO_ROUTINES 0 +#define configUSE_MUTEXES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 0 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_QUEUE_SETS 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configMAX_PRIORITIES ( 7 ) +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* The peripheral used to generate the tick interrupt is configured as part of +the application code. This constant should be set to the vector number of the +peripheral chosen. As supplied this is CMT0. */ +#define configTICK_VECTOR _CMT0_CMI0 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +void vAssertCalled( void ); +#define configASSERT( x ) if( ( x ) == 0 ) { brk(); taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Override some of the priorities set in the common demo tasks. This is +required to ensure false positive timing errors are not reported. */ +#define bktPRIMARY_PRIORITY ( configMAX_PRIORITIES - 3 ) +#define bktSECONDARY_PRIORITY ( configMAX_PRIORITIES - 4 ) +#define intqHIGHER_PRIORITY ( configMAX_PRIORITIES - 3 ) + + +/*----------------------------------------------------------- + * Ethernet configuration. + *-----------------------------------------------------------*/ + +/* MAC address configuration. */ +#define configMAC_ADDR0 0x00 +#define configMAC_ADDR1 0x12 +#define configMAC_ADDR2 0x13 +#define configMAC_ADDR3 0x10 +#define configMAC_ADDR4 0x15 +#define configMAC_ADDR5 0x11 + +/* IP address configuration. */ +#define configIP_ADDR0 192 +#define configIP_ADDR1 168 +#define configIP_ADDR2 0 +#define configIP_ADDR3 200 + +/* Netmask configuration. */ +#define configNET_MASK0 255 +#define configNET_MASK1 255 +#define configNET_MASK2 255 +#define configNET_MASK3 0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..e7dffe6e3 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.c @@ -0,0 +1,162 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file contains the non-portable and therefore RX62N specific parts of + * the IntQueue standard demo task - namely the configuration of the timers + * that generate the interrupts and the interrupt entry points. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Hardware specifics. */ +#include "iodefine.h" + +#define tmrTIMER_0_1_FREQUENCY ( 2000UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2407UL ) + +void vInitialiseTimerForIntQueueTest( void ) +{ + /* Ensure interrupts do not start until full configuration is complete. */ + portENTER_CRITICAL(); + { + SYSTEM.PRCR.WORD = 0xa502; + + /* Cascade two 8bit timer channels to generate the interrupts. + 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are + utilised for this test. */ + + /* Enable the timers. */ + SYSTEM.MSTPCRA.BIT.MSTPA5 = 0; + SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; + + /* Enable compare match A interrupt request. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Clear the timer on compare match A. */ + TMR0.TCR.BIT.CCLR = 1; + TMR2.TCR.BIT.CCLR = 1; + + /* Set the compare match value. */ + TMR01.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + TMR23.TCORA = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / tmrTIMER_0_1_FREQUENCY ) -1 ) / 8 ); + + /* 16 bit operation ( count from timer 1,2 ). */ + TMR0.TCCR.BIT.CSS = 3; + TMR2.TCCR.BIT.CSS = 3; + + /* Use PCLK as the input. */ + TMR1.TCCR.BIT.CSS = 1; + TMR3.TCCR.BIT.CSS = 1; + + /* Divide PCLK by 8. */ + TMR1.TCCR.BIT.CKS = 2; + TMR3.TCCR.BIT.CKS = 2; + + /* Enable TMR 0, 2 interrupts. */ + TMR0.TCR.BIT.CMIEA = 1; + TMR2.TCR.BIT.CMIEA = 1; + + /* Set interrupt priority and enable. */ + IPR( TMR0, CMIA0 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + IR( TMR0, CMIA0 ) = 0U; + IEN( TMR0, CMIA0 ) = 1U; + + /* Do the same for TMR2, but to vector 129. */ + IPR( TMR2, CMIA2 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + IR( TMR2, CMIA2 ) = 0U; + IEN( TMR2, CMIA2 ) = 1U; + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +#pragma interrupt r_tmr_cmia0_interrupt(vect=VECT(TMR0,CMIA0)) +void r_tmr_cmia0_interrupt( void ) +{ + portYIELD_FROM_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +#pragma interrupt r_tmr_cmia2_interrupt(vect=VECT(TMR2,CMIA2)) +void r_tmr_cmia2_interrupt( void ) +{ + portYIELD_FROM_ISR( xSecondTimerHandler() ); +} + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..fcf9f8c1f --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/main_full.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/main_full.c new file mode 100644 index 000000000..4df406c7f --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Full_Demo/main_full.c @@ -0,0 +1,668 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to + * select between the two. See the notes on using + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY in main.c. This file implements the + * comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 3UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_1_PARAMETER ( ( void * ) 0x12121212UL ) +#define mainREG_TEST_2_PARAMETER ( ( void * ) 0x12345678UL ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Entry point for the comprehensive demo (as opposed to the simple blinky + * demo). + */ +void main_full( void ); + +/* + * The full demo includes some functionality called from the tick hook. + */ +void vFullDemoTickHook( void ); + + /* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the registers, as described at the top of this file. The nature of these + * files necessitates that they are written in assembly, but the entry points + * are kept in the C file for the convenience of checking the task parameter. + */ +static void prvRegTest1Task( void *pvParameters ); +static void prvRegTest2Task( void *pvParameters ); +static void prvRegTest1Implementation( void ); +static void prvRegTest2Implementation( void ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/* String for display in the web server. It is set to an error message if the +check task detects an error. */ +const char *pcStatusMessage = "All tasks running without error"; +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTest1Task, "RegTst1", configMINIMAL_STACK_SIZE, mainREG_TEST_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTest2Task, "RegTst2", configMINIMAL_STACK_SIZE, mainREG_TEST_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) mainNO_ERROR_CHECK_TASK_PERIOD ) != pdPASS ) + { + ulErrorFound |= 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ +//_RB_ LED0 = !LED0; + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + pcStatusMessage = "Error found in at least one task."; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = ( 35 / portTICK_PERIOD_MS ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + nop(); + + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Use task notifications from an interrupt. */ + xNotifyTaskFromISR(); + + /* Use mutexes from interrupts. */ + vInterruptSemaphorePeriodicTest(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest1Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_1_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest1Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +static void prvRegTest2Task( void *pvParameters ) +{ + if( pvParameters != mainREG_TEST_2_PARAMETER ) + { + /* The parameter did not contain the expected value. */ + for( ;; ) + { + /* Stop the tick interrupt so its obvious something has gone wrong. */ + taskDISABLE_INTERRUPTS(); + } + } + + /* This is an inline asm function that never returns. */ + prvRegTest2Implementation(); +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest1Implementation +static void prvRegTest1Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ; Loop, checking each itteration that each register still contains the + ; expected value. +TestLoop1: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest1LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Yield to extend the text coverage. Set the bit in the ITU SWINTR register. + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ; Restore the clobbered registers. + POPM R14-R15 + + ; Now compare each register to ensure it still contains the value that was + ; set before this loop was entered. + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop1 + +RegTest1Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; causing the check task to indicate the error. + BRA RegTest1Error +} +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of this file. */ +#pragma inline_asm prvRegTest2Implementation +static void prvRegTest2Implementation( void ) +{ + ; Put a known value in each register. + MOV.L #10, R1 + MOV.L #20, R2 + MOV.L #30, R3 + MOV.L #40, R4 + MOV.L #50, R5 + MOV.L #60, R6 + MOV.L #70, R7 + MOV.L #80, R8 + MOV.L #90, R9 + MOV.L #100, R10 + MOV.L #110, R11 + MOV.L #120, R12 + MOV.L #130, R13 + MOV.L #140, R14 + MOV.L #150, R15 + + ; Loop, checking on each itteration that each register still contains the + ; expected value. +TestLoop2: + + ; Push the registers that are going to get clobbered. + PUSHM R14-R15 + + ; Increment the loop counter to show this task is still getting CPU time. + MOV.L #_ulRegTest2LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ; Restore the clobbered registers. + POPM R14-R15 + + CMP #10, R1 + BNE RegTest2Error + CMP #20, R2 + BNE RegTest2Error + CMP #30, R3 + BNE RegTest2Error + CMP #40, R4 + BNE RegTest2Error + CMP #50, R5 + BNE RegTest2Error + CMP #60, R6 + BNE RegTest2Error + CMP #70, R7 + BNE RegTest2Error + CMP #80, R8 + BNE RegTest2Error + CMP #90, R9 + BNE RegTest2Error + CMP #100, R10 + BNE RegTest2Error + CMP #110, R11 + BNE RegTest2Error + CMP #120, R12 + BNE RegTest2Error + CMP #130, R13 + BNE RegTest2Error + CMP #140, R14 + BNE RegTest2Error + CMP #150, R15 + BNE RegTest2Error + + ; All comparisons passed, start a new itteratio of this loop. + BRA TestLoop2 + +RegTest2Error: + ; A compare failed, just loop here so the loop counter stops incrementing + ; - causing the check task to indicate the error. + BRA RegTest2Error +} +/*-----------------------------------------------------------*/ + + + + diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/stacksct.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/stacksct.h new file mode 100644 index 000000000..3c08dcb1d --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/stacksct.h @@ -0,0 +1,13 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : stacksct.h */ +/* DESCRIPTION : Setting of Stack area */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ +#pragma stacksize su=0x300 +#pragma stacksize si=0x300 \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/typedefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/typedefine.h new file mode 100644 index 000000000..c50b4f754 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/typedefine.h @@ -0,0 +1,42 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : typedefine.h */ +/* DESCRIPTION : Aliases of Integer Type */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/********************************************************************* +* +* Device : RX +* +* File Name : typedefine.h +* +* Abstract : Aliases of Integer Type. +* +* History : 1.00 (2009-08-07) +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2009 Renesas Electronics Corporation. +* and Renesas Solutions Corporation. All rights reserved. +* +*********************************************************************/ + +typedef signed char _SBYTE; +typedef unsigned char _UBYTE; +typedef signed short _SWORD; +typedef unsigned short _UWORD; +typedef signed int _SINT; +typedef unsigned int _UINT; +typedef signed long _SDWORD; +typedef unsigned long _UDWORD; +typedef signed long long _SQWORD; +typedef unsigned long long _UQWORD; diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/vect.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/vect.h new file mode 100644 index 000000000..c761e6d0d --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/Renesas_Code/vect.h @@ -0,0 +1,849 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : vect.h */ +/* DESCRIPTION : Definition of vector */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/************************************************************************ +* +* Device : RX/RX200/RX231 +* +* File Name : vect.h +* +* Abstract : Definition of Vector. +* +* History : 0.50 (2014-09-18) [Hardware Manual Revision : 0.50] +* : 1.00 (2015-05-18) [Hardware Manual Revision : 1.00] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2015 (2014) Renesas Electronics Corporation. +* +************************************************************************/ + +// Exception(Supervisor Instruction) +#pragma interrupt (Excep_SuperVisorInst) +void Excep_SuperVisorInst(void); + +// Exception(Access Instruction) +#pragma interrupt (Excep_AccessInst) +void Excep_AccessInst(void); + +// Exception(Undefined Instruction) +#pragma interrupt (Excep_UndefinedInst) +void Excep_UndefinedInst(void); + +// Exception(Floating Point) +#pragma interrupt (Excep_FloatingPoint) +void Excep_FloatingPoint(void); + +// NMI +#pragma interrupt (NonMaskableInterrupt) +void NonMaskableInterrupt(void); + +// Dummy +#pragma interrupt (Dummy) +void Dummy(void); + +// BRK +#pragma interrupt (Excep_BRK(vect=0)) +void Excep_BRK(void); + +// vector 1 reserved +// vector 2 reserved +// vector 3 reserved +// vector 4 reserved +// vector 5 reserved +// vector 6 reserved +// vector 7 reserved +// vector 8 reserved +// vector 9 reserved +// vector 10 reserved +// vector 11 reserved +// vector 12 reserved +// vector 13 reserved +// vector 14 reserved +// vector 15 reserved + +// BSC BUSERR +#pragma interrupt (Excep_BSC_BUSERR(vect=16)) +void Excep_BSC_BUSERR(void); + +// vector 17 reserved +// vector 18 reserved +// vector 19 reserved +// vector 20 reserved +// vector 21 reserved +// vector 22 reserved + +// FCU FRDYI +#pragma interrupt (Excep_FCU_FRDYI(vect=23)) +void Excep_FCU_FRDYI(void); + +// vector 24 reserved +// vector 25 reserved +// vector 26 reserved + +// ICU SWINT +// FreeRTOS installs its own software interrupt. +//#pragma interrupt (Excep_ICU_SWINT(vect=27)) +//void Excep_ICU_SWINT(void); + +// CMT0 CMI0 +// By default FreeRTOS uses CMT0 to generate the tick interrupt. +//#pragma interrupt (Excep_CMT0_CMI0(vect=28)) +//void Excep_CMT0_CMI0(void); + +// CMT1 CMI1 +#pragma interrupt (Excep_CMT1_CMI1(vect=29)) +void Excep_CMT1_CMI1(void); + +// CMT2 CMI2 +#pragma interrupt (Excep_CMT2_CMI2(vect=30)) +void Excep_CMT2_CMI2(void); + +// CMT3 CMI3 +#pragma interrupt (Excep_CMT3_CMI3(vect=31)) +void Excep_CMT3_CMI3(void); + +// CAC FERRF +#pragma interrupt (Excep_CAC_FERRF(vect=32)) +void Excep_CAC_FERRF(void); + +// CAC MENDF +#pragma interrupt (Excep_CAC_MENDF(vect=33)) +void Excep_CAC_MENDF(void); + +// CAC OVFF +#pragma interrupt (Excep_CAC_OVFF(vect=34)) +void Excep_CAC_OVFF(void); + +// vector 35 reserved + +// USB0 D0FIFO0 +#pragma interrupt (Excep_USB0_D0FIFO0(vect=36)) +void Excep_USB0_D0FIFO0(void); + +// USB0 D1FIFO0 +#pragma interrupt (Excep_USB0_D1FIFO0(vect=37)) +void Excep_USB0_D1FIFO0(void); + +// USB0 USBI0 +#pragma interrupt (Excep_USB0_USBI0(vect=38)) +void Excep_USB0_USBI0(void); + +// vector 39 reserved + +// SDHI SBFAI +#pragma interrupt (Excep_SDHI_SBFAI(vect=40)) +void Excep_SDHI_SBFAI(void); + +// SDHI CDETI +#pragma interrupt (Excep_SDHI_CDETI(vect=41)) +void Excep_SDHI_CDETI(void); + +// SDHI CACI +#pragma interrupt (Excep_SDHI_CACI(vect=42)) +void Excep_SDHI_CACI(void); + +// SDHI SDACI +#pragma interrupt (Excep_SDHI_SDACI(vect=43)) +void Excep_SDHI_SDACI(void); + +// RSPI0 SPEI0 +#pragma interrupt (Excep_RSPI0_SPEI0(vect=44)) +void Excep_RSPI0_SPEI0(void); + +// RSPI0 SPRI0 +#pragma interrupt (Excep_RSPI0_SPRI0(vect=45)) +void Excep_RSPI0_SPRI0(void); + +// RSPI0 SPTI0 +#pragma interrupt (Excep_RSPI0_SPTI0(vect=46)) +void Excep_RSPI0_SPTI0(void); + +// RSPI0 SPII0 +#pragma interrupt (Excep_RSPI0_SPII0(vect=47)) +void Excep_RSPI0_SPII0(void); + +// vector 48 reserved +// vector 49 reserved +// vector 50 reserved +// vector 51 reserved + +// RSCAN COMFRXINT +#pragma interrupt (Excep_RSCAN_COMFRXINT(vect=52)) +void Excep_RSCAN_COMFRXINT(void); + +// RSCAN RXFINT +#pragma interrupt (Excep_RSCAN_RXFINT(vect=53)) +void Excep_RSCAN_RXFINT(void); + +// RSCAN TXINT +#pragma interrupt (Excep_RSCAN_TXINT(vect=54)) +void Excep_RSCAN_TXINT(void); + +// RSCAN CHERRINT +#pragma interrupt (Excep_RSCAN_CHERRINT(vect=55)) +void Excep_RSCAN_CHERRINT(void); + +// RSCAN GLERRINT +#pragma interrupt (Excep_RSCAN_GLERRINT(vect=56)) +void Excep_RSCAN_GLERRINT(void); + +// DOC DOPCF +#pragma interrupt (Excep_DOC_DOPCF(vect=57)) +void Excep_DOC_DOPCF(void); + +// CMPB CMPB0 +#pragma interrupt (Excep_CMPB_CMPB0(vect=58)) +void Excep_CMPB_CMPB0(void); + +// CMPB CMPB1 +#pragma interrupt (Excep_CMPB_CMPB1(vect=59)) +void Excep_CMPB_CMPB1(void); + +// CTSU CTSUWR +#pragma interrupt (Excep_CTSU_CTSUWR(vect=60)) +void Excep_CTSU_CTSUWR(void); + +// CTSU CTSURD +#pragma interrupt (Excep_CTSU_CTSURD(vect=61)) +void Excep_CTSU_CTSURD(void); + +// CTSU CTSUFN +#pragma interrupt (Excep_CTSU_CTSUFN(vect=62)) +void Excep_CTSU_CTSUFN(void); + +// RTC CUP +#pragma interrupt (Excep_RTC_CUP(vect=63)) +void Excep_RTC_CUP(void); + +// ICU IRQ0 +#pragma interrupt (Excep_ICU_IRQ0(vect=64)) +void Excep_ICU_IRQ0(void); + +// ICU IRQ1 +#pragma interrupt (Excep_ICU_IRQ1(vect=65)) +void Excep_ICU_IRQ1(void); + +// ICU IRQ2 +#pragma interrupt (Excep_ICU_IRQ2(vect=66)) +void Excep_ICU_IRQ2(void); + +// ICU IRQ3 +#pragma interrupt (Excep_ICU_IRQ3(vect=67)) +void Excep_ICU_IRQ3(void); + +// ICU IRQ4 +#pragma interrupt (Excep_ICU_IRQ4(vect=68)) +void Excep_ICU_IRQ4(void); + +// ICU IRQ5 +#pragma interrupt (Excep_ICU_IRQ5(vect=69)) +void Excep_ICU_IRQ5(void); + +// ICU IRQ6 +#pragma interrupt (Excep_ICU_IRQ6(vect=70)) +void Excep_ICU_IRQ6(void); + +// ICU IRQ7 +#pragma interrupt (Excep_ICU_IRQ7(vect=71)) +void Excep_ICU_IRQ7(void); + +// vector 72 reserved +// vector 73 reserved +// vector 74 reserved +// vector 75 reserved +// vector 76 reserved +// vector 77 reserved +// vector 78 reserved +// vector 79 reserved + +// ELC ELSR8I +#pragma interrupt (Excep_ELC_ELSR8I(vect=80)) +void Excep_ELC_ELSR8I(void); + +// vector 81 reserved +// vector 82 reserved +// vector 83 reserved +// vector 84 reserved +// vector 85 reserved +// vector 86 reserved +// vector 87 reserved + +// LVD LVD1 +#pragma interrupt (Excep_LVD_LVD1(vect=88)) +void Excep_LVD_LVD1(void); + +// LVD LVD2 +#pragma interrupt (Excep_LVD_LVD2(vect=89)) +void Excep_LVD_LVD2(void); + +// CMPA CMPA1 +//#pragma interrupt (Excep_CMPA_CMPA1(vect=88)) +//void Excep_CMPA_CMPA1(void); + +// CMPA CMPA2 +//#pragma interrupt (Excep_CMPA_CMPA2(vect=89)) +//void Excep_CMPA_CMPA2(void); + +// USB0 USBR0 +#pragma interrupt (Excep_USB0_USBR0(vect=90)) +void Excep_USB0_USBR0(void); + +// VBATT VBTLVDI +#pragma interrupt (Excep_VBATT_VBTLVDI(vect=91)) +void Excep_VBATT_VBTLVDI(void); + +// RTC ALM +#pragma interrupt (Excep_RTC_ALM(vect=92)) +void Excep_RTC_ALM(void); + +// RTC PRD +#pragma interrupt (Excep_RTC_PRD(vect=93)) +void Excep_RTC_PRD(void); + +// vector 94 reserved +// vector 95 reserved +// vector 96 reserved +// vector 97 reserved +// vector 98 reserved +// vector 99 reserved +// vector 100 reserved +// vector 101 reserved + +// S12AD S12ADI0 +#pragma interrupt (Excep_S12AD_S12ADI0(vect=102)) +void Excep_S12AD_S12ADI0(void); + +// S12AD GBADI +#pragma interrupt (Excep_S12AD_GBADI(vect=103)) +void Excep_S12AD_GBADI(void); + +// CMPB1 CMPB2 +#pragma interrupt (Excep_CMPB1_CMPB2(vect=104)) +void Excep_CMPB1_CMPB2(void); + +// CMPB1 CMPB3 +#pragma interrupt (Excep_CMPB1_CMPB3(vect=105)) +void Excep_CMPB1_CMPB3(void); + +// ELC ELSR18I +#pragma interrupt (Excep_ELC_ELSR18I(vect=106)) +void Excep_ELC_ELSR18I(void); + +// ELC ELSR19I +#pragma interrupt (Excep_ELC_ELSR19I(vect=107)) +void Excep_ELC_ELSR19I(void); + +// SSI0 SSIF0 +#pragma interrupt (Excep_SSI0_SSIF0(vect=108)) +void Excep_SSI0_SSIF0(void); + +// SSI0 SSIRXI0 +#pragma interrupt (Excep_SSI0_SSIRXI0(vect=109)) +void Excep_SSI0_SSIRXI0(void); + +// SSI0 SSITXI0 +#pragma interrupt (Excep_SSI0_SSITXI0(vect=110)) +void Excep_SSI0_SSITXI0(void); + +// SECURITY RD +#pragma interrupt (Excep_SECURITY_RD(vect=111)) +void Excep_SECURITY_RD(void); + +// SECURITY WR +#pragma interrupt (Excep_SECURITY_WR(vect=112)) +void Excep_SECURITY_WR(void); + +// SECURITY ERR +#pragma interrupt (Excep_SECURITY_ERR(vect=113)) +void Excep_SECURITY_ERR(void); + +// MTU0 TGIA0 +#pragma interrupt (Excep_MTU0_TGIA0(vect=114)) +void Excep_MTU0_TGIA0(void); + +// MTU0 TGIB0 +#pragma interrupt (Excep_MTU0_TGIB0(vect=115)) +void Excep_MTU0_TGIB0(void); + +// MTU0 TGIC0 +#pragma interrupt (Excep_MTU0_TGIC0(vect=116)) +void Excep_MTU0_TGIC0(void); + +// MTU0 TGID0 +#pragma interrupt (Excep_MTU0_TGID0(vect=117)) +void Excep_MTU0_TGID0(void); + +// MTU0 TCIV0 +#pragma interrupt (Excep_MTU0_TCIV0(vect=118)) +void Excep_MTU0_TCIV0(void); + +// MTU0 TGIE0 +#pragma interrupt (Excep_MTU0_TGIE0(vect=119)) +void Excep_MTU0_TGIE0(void); + +// MTU0 TGIF0 +#pragma interrupt (Excep_MTU0_TGIF0(vect=120)) +void Excep_MTU0_TGIF0(void); + +// MTU1 TGIA1 +#pragma interrupt (Excep_MTU1_TGIA1(vect=121)) +void Excep_MTU1_TGIA1(void); + +// MTU1 TGIB1 +#pragma interrupt (Excep_MTU1_TGIB1(vect=122)) +void Excep_MTU1_TGIB1(void); + +// MTU1 TCIV1 +#pragma interrupt (Excep_MTU1_TCIV1(vect=123)) +void Excep_MTU1_TCIV1(void); + +// MTU1 TCIU1 +#pragma interrupt (Excep_MTU1_TCIU1(vect=124)) +void Excep_MTU1_TCIU1(void); + +// MTU2 TGIA2 +#pragma interrupt (Excep_MTU2_TGIA2(vect=125)) +void Excep_MTU2_TGIA2(void); + +// MTU2 TGIB2 +#pragma interrupt (Excep_MTU2_TGIB2(vect=126)) +void Excep_MTU2_TGIB2(void); + +// MTU2 TCIV2 +#pragma interrupt (Excep_MTU2_TCIV2(vect=127)) +void Excep_MTU2_TCIV2(void); + +// MTU2 TCIU2 +#pragma interrupt (Excep_MTU2_TCIU2(vect=128)) +void Excep_MTU2_TCIU2(void); + +// MTU3 TGIA3 +#pragma interrupt (Excep_MTU3_TGIA3(vect=129)) +void Excep_MTU3_TGIA3(void); + +// MTU3 TGIB3 +#pragma interrupt (Excep_MTU3_TGIB3(vect=130)) +void Excep_MTU3_TGIB3(void); + +// MTU3 TGIC3 +#pragma interrupt (Excep_MTU3_TGIC3(vect=131)) +void Excep_MTU3_TGIC3(void); + +// MTU3 TGID3 +#pragma interrupt (Excep_MTU3_TGID3(vect=132)) +void Excep_MTU3_TGID3(void); + +// MTU3 TCIV3 +#pragma interrupt (Excep_MTU3_TCIV3(vect=133)) +void Excep_MTU3_TCIV3(void); + +// MTU4 TGIA4 +#pragma interrupt (Excep_MTU4_TGIA4(vect=134)) +void Excep_MTU4_TGIA4(void); + +// MTU4 TGIB4 +#pragma interrupt (Excep_MTU4_TGIB4(vect=135)) +void Excep_MTU4_TGIB4(void); + +// MTU4 TGIC4 +#pragma interrupt (Excep_MTU4_TGIC4(vect=136)) +void Excep_MTU4_TGIC4(void); + +// MTU4 TGID4 +#pragma interrupt (Excep_MTU4_TGID4(vect=137)) +void Excep_MTU4_TGID4(void); + +// MTU4 TCIV4 +#pragma interrupt (Excep_MTU4_TCIV4(vect=138)) +void Excep_MTU4_TCIV4(void); + +// MTU5 TGIU5 +#pragma interrupt (Excep_MTU5_TGIU5(vect=139)) +void Excep_MTU5_TGIU5(void); + +// MTU5 TGIV5 +#pragma interrupt (Excep_MTU5_TGIV5(vect=140)) +void Excep_MTU5_TGIV5(void); + +// MTU5 TGIW5 +#pragma interrupt (Excep_MTU5_TGIW5(vect=141)) +void Excep_MTU5_TGIW5(void); + +// TPU0 TGI0A +#pragma interrupt (Excep_TPU0_TGI0A(vect=142)) +void Excep_TPU0_TGI0A(void); + +// TPU0 TGI0B +#pragma interrupt (Excep_TPU0_TGI0B(vect=143)) +void Excep_TPU0_TGI0B(void); + +// TPU0 TGI0C +#pragma interrupt (Excep_TPU0_TGI0C(vect=144)) +void Excep_TPU0_TGI0C(void); + +// TPU0 TGI0D +#pragma interrupt (Excep_TPU0_TGI0D(vect=145)) +void Excep_TPU0_TGI0D(void); + +// TPU0 TCI0V +#pragma interrupt (Excep_TPU0_TCI0V(vect=146)) +void Excep_TPU0_TCI0V(void); + +// TPU1 TGI1A +#pragma interrupt (Excep_TPU1_TGI1A(vect=147)) +void Excep_TPU1_TGI1A(void); + +// TPU1 TGI1B +#pragma interrupt (Excep_TPU1_TGI1B(vect=148)) +void Excep_TPU1_TGI1B(void); + +// TPU1 TCI1V +#pragma interrupt (Excep_TPU1_TCI1V(vect=149)) +void Excep_TPU1_TCI1V(void); + +// TPU1 TCI1U +#pragma interrupt (Excep_TPU1_TCI1U(vect=150)) +void Excep_TPU1_TCI1U(void); + +// TPU2 TGI2A +#pragma interrupt (Excep_TPU2_TGI2A(vect=151)) +void Excep_TPU2_TGI2A(void); + +// TPU2 TGI2B +#pragma interrupt (Excep_TPU2_TGI2B(vect=152)) +void Excep_TPU2_TGI2B(void); + +// TPU2 TCI2V +#pragma interrupt (Excep_TPU2_TCI2V(vect=153)) +void Excep_TPU2_TCI2V(void); + +// TPU2 TCI2U +#pragma interrupt (Excep_TPU2_TCI2U(vect=154)) +void Excep_TPU2_TCI2U(void); + +// TPU3 TGI3A +#pragma interrupt (Excep_TPU3_TGI3A(vect=155)) +void Excep_TPU3_TGI3A(void); + +// TPU3 TGI3B +#pragma interrupt (Excep_TPU3_TGI3B(vect=156)) +void Excep_TPU3_TGI3B(void); + +// TPU3 TGI3C +#pragma interrupt (Excep_TPU3_TGI3C(vect=157)) +void Excep_TPU3_TGI3C(void); + +// TPU3 TGI3D +#pragma interrupt (Excep_TPU3_TGI3D(vect=158)) +void Excep_TPU3_TGI3D(void); + +// TPU3 TCI3V +#pragma interrupt (Excep_TPU3_TCI3V(vect=159)) +void Excep_TPU3_TCI3V(void); + +// TPU4 TGI4A +#pragma interrupt (Excep_TPU4_TGI4A(vect=160)) +void Excep_TPU4_TGI4A(void); + +// TPU4 TGI4B +#pragma interrupt (Excep_TPU4_TGI4B(vect=161)) +void Excep_TPU4_TGI4B(void); + +// TPU4 TCI4V +#pragma interrupt (Excep_TPU4_TCI4V(vect=162)) +void Excep_TPU4_TCI4V(void); + +// TPU4 TCI4U +#pragma interrupt (Excep_TPU4_TCI4U(vect=163)) +void Excep_TPU4_TCI4U(void); + +// TPU5 TGI5A +#pragma interrupt (Excep_TPU5_TGI5A(vect=164)) +void Excep_TPU5_TGI5A(void); + +// TPU5 TGI5B +#pragma interrupt (Excep_TPU5_TGI5B(vect=165)) +void Excep_TPU5_TGI5B(void); + +// TPU5 TCI5V +#pragma interrupt (Excep_TPU5_TCI5V(vect=166)) +void Excep_TPU5_TCI5V(void); + +// TPU5 TCI5U +#pragma interrupt (Excep_TPU5_TCI5U(vect=167)) +void Excep_TPU5_TCI5U(void); + +// vector 168 reserved +// vector 169 reserved + +// POE OEI1 +#pragma interrupt (Excep_POE_OEI1(vect=170)) +void Excep_POE_OEI1(void); + +// POE OEI2 +#pragma interrupt (Excep_POE_OEI2(vect=171)) +void Excep_POE_OEI2(void); + +// vector 172 reserved +// vector 173 reserved + +// TMR0 CMIA0 +// Used by the FreeRTOS demo. +//#pragma interrupt (Excep_TMR0_CMIA0(vect=174)) +//void Excep_TMR0_CMIA0(void); + +// TMR0 CMIB0 +#pragma interrupt (Excep_TMR0_CMIB0(vect=175)) +void Excep_TMR0_CMIB0(void); + +// TMR0 OVI0 +#pragma interrupt (Excep_TMR0_OVI0(vect=176)) +void Excep_TMR0_OVI0(void); + +// TMR1 CMIA1 +#pragma interrupt (Excep_TMR1_CMIA1(vect=177)) +void Excep_TMR1_CMIA1(void); + +// TMR1 CMIB1 +#pragma interrupt (Excep_TMR1_CMIB1(vect=178)) +void Excep_TMR1_CMIB1(void); + +// TMR1 OVI1 +#pragma interrupt (Excep_TMR1_OVI1(vect=179)) +void Excep_TMR1_OVI1(void); + +// TMR2 CMIA2 +// Used by teh FreeRTOS demo. +//#pragma interrupt (Excep_TMR2_CMIA2(vect=180)) +//void Excep_TMR2_CMIA2(void); + +// TMR2 CMIB2 +#pragma interrupt (Excep_TMR2_CMIB2(vect=181)) +void Excep_TMR2_CMIB2(void); + +// TMR2 OVI2 +#pragma interrupt (Excep_TMR2_OVI2(vect=182)) +void Excep_TMR2_OVI2(void); + +// TMR3 CMIA3 +#pragma interrupt (Excep_TMR3_CMIA3(vect=183)) +void Excep_TMR3_CMIA3(void); + +// TMR3 CMIB3 +#pragma interrupt (Excep_TMR3_CMIB3(vect=184)) +void Excep_TMR3_CMIB3(void); + +// TMR3 OVI3 +#pragma interrupt (Excep_TMR3_OVI3(vect=185)) +void Excep_TMR3_OVI3(void); + +// vector 186 reserved +// vector 187 reserved +// vector 188 reserved +// vector 189 reserved +// vector 190 reserved +// vector 191 reserved +// vector 192 reserved +// vector 193 reserved +// vector 194 reserved +// vector 195 reserved +// vector 196 reserved +// vector 197 reserved + +// DMAC DMAC0I +#pragma interrupt (Excep_DMAC_DMAC0I(vect=198)) +void Excep_DMAC_DMAC0I(void); + +// DMAC DMAC1I +#pragma interrupt (Excep_DMAC_DMAC1I(vect=199)) +void Excep_DMAC_DMAC1I(void); + +// DMAC DMAC2I +#pragma interrupt (Excep_DMAC_DMAC2I(vect=200)) +void Excep_DMAC_DMAC2I(void); + +// DMAC DMAC3I +#pragma interrupt (Excep_DMAC_DMAC3I(vect=201)) +void Excep_DMAC_DMAC3I(void); + +// vector 202 reserved +// vector 203 reserved +// vector 204 reserved +// vector 205 reserved +// vector 206 reserved +// vector 207 reserved +// vector 208 reserved +// vector 209 reserved +// vector 210 reserved +// vector 211 reserved +// vector 212 reserved +// vector 213 reserved + +// SCI0 ERI0 +#pragma interrupt (Excep_SCI0_ERI0(vect=214)) +void Excep_SCI0_ERI0(void); + +// SCI0 RXI0 +#pragma interrupt (Excep_SCI0_RXI0(vect=215)) +void Excep_SCI0_RXI0(void); + +// SCI0 TXI0 +#pragma interrupt (Excep_SCI0_TXI0(vect=216)) +void Excep_SCI0_TXI0(void); + +// SCI0 TEI0 +#pragma interrupt (Excep_SCI0_TEI0(vect=217)) +void Excep_SCI0_TEI0(void); + +// SCI1 ERI1 +#pragma interrupt (Excep_SCI1_ERI1(vect=218)) +void Excep_SCI1_ERI1(void); + +// SCI1 RXI1 +#pragma interrupt (Excep_SCI1_RXI1(vect=219)) +void Excep_SCI1_RXI1(void); + +// SCI1 TXI1 +#pragma interrupt (Excep_SCI1_TXI1(vect=220)) +void Excep_SCI1_TXI1(void); + +// SCI1 TEI1 +#pragma interrupt (Excep_SCI1_TEI1(vect=221)) +void Excep_SCI1_TEI1(void); + +// SCI5 ERI5 +#pragma interrupt (Excep_SCI5_ERI5(vect=222)) +void Excep_SCI5_ERI5(void); + +// SCI5 RXI5 +#pragma interrupt (Excep_SCI5_RXI5(vect=223)) +void Excep_SCI5_RXI5(void); + +// SCI5 TXI5 +#pragma interrupt (Excep_SCI5_TXI5(vect=224)) +void Excep_SCI5_TXI5(void); + +// SCI5 TEI5 +#pragma interrupt (Excep_SCI5_TEI5(vect=225)) +void Excep_SCI5_TEI5(void); + +// SCI6 ERI6 +#pragma interrupt (Excep_SCI6_ERI6(vect=226)) +void Excep_SCI6_ERI6(void); + +// SCI6 RXI6 +#pragma interrupt (Excep_SCI6_RXI6(vect=227)) +void Excep_SCI6_RXI6(void); + +// SCI6 TXI6 +#pragma interrupt (Excep_SCI6_TXI6(vect=228)) +void Excep_SCI6_TXI6(void); + +// SCI6 TEI6 +#pragma interrupt (Excep_SCI6_TEI6(vect=229)) +void Excep_SCI6_TEI6(void); + +// SCI8 ERI8 +#pragma interrupt (Excep_SCI8_ERI8(vect=230)) +void Excep_SCI8_ERI8(void); + +// SCI8 RXI8 +#pragma interrupt (Excep_SCI8_RXI8(vect=231)) +void Excep_SCI8_RXI8(void); + +// SCI8 TXI8 +#pragma interrupt (Excep_SCI8_TXI8(vect=232)) +void Excep_SCI8_TXI8(void); + +// SCI8 TEI8 +#pragma interrupt (Excep_SCI8_TEI8(vect=233)) +void Excep_SCI8_TEI8(void); + +// SCI9 ERI9 +#pragma interrupt (Excep_SCI9_ERI9(vect=234)) +void Excep_SCI9_ERI9(void); + +// SCI9 RXI9 +#pragma interrupt (Excep_SCI9_RXI9(vect=235)) +void Excep_SCI9_RXI9(void); + +// SCI9 TXI9 +#pragma interrupt (Excep_SCI9_TXI9(vect=236)) +void Excep_SCI9_TXI9(void); + +// SCI9 TEI9 +#pragma interrupt (Excep_SCI9_TEI9(vect=237)) +void Excep_SCI9_TEI9(void); + +// SCI12 ERI12 +#pragma interrupt (Excep_SCI12_ERI12(vect=238)) +void Excep_SCI12_ERI12(void); + +// SCI12 RXI12 +#pragma interrupt (Excep_SCI12_RXI12(vect=239)) +void Excep_SCI12_RXI12(void); + +// SCI12 TXI12 +#pragma interrupt (Excep_SCI12_TXI12(vect=240)) +void Excep_SCI12_TXI12(void); + +// SCI12 TEI12 +#pragma interrupt (Excep_SCI12_TEI12(vect=241)) +void Excep_SCI12_TEI12(void); + +// SCI12 SCIX0 +#pragma interrupt (Excep_SCI12_SCIX0(vect=242)) +void Excep_SCI12_SCIX0(void); + +// SCI12 SCIX1 +#pragma interrupt (Excep_SCI12_SCIX1(vect=243)) +void Excep_SCI12_SCIX1(void); + +// SCI12 SCIX2 +#pragma interrupt (Excep_SCI12_SCIX2(vect=244)) +void Excep_SCI12_SCIX2(void); + +// SCI12 SCIX3 +#pragma interrupt (Excep_SCI12_SCIX3(vect=245)) +void Excep_SCI12_SCIX3(void); + +// RIIC0 EEI0 +#pragma interrupt (Excep_RIIC0_EEI0(vect=246)) +void Excep_RIIC0_EEI0(void); + +// RIIC0 RXI0 +#pragma interrupt (Excep_RIIC0_RXI0(vect=247)) +void Excep_RIIC0_RXI0(void); + +// RIIC0 TXI0 +#pragma interrupt (Excep_RIIC0_TXI0(vect=248)) +void Excep_RIIC0_TXI0(void); + +// RIIC0 TEI0 +#pragma interrupt (Excep_RIIC0_TEI0(vect=249)) +void Excep_RIIC0_TEI0(void); + +// vector 250 reserved +// vector 251 reserved +// vector 252 reserved +// vector 253 reserved +// vector 254 reserved +// vector 255 reserved + +//;<> +//;Power On Reset PC +extern void PowerON_Reset_PC(void); +//;<> diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c new file mode 100644 index 000000000..7a23f21fe --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.c @@ -0,0 +1,115 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_CGC_Create +* Description : This function initializes the clock generator. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_CGC_Create(void) +{ + uint32_t sckcr_dummy; + volatile uint32_t memorywaitcycle; + + /* Set main clock control registers */ + SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | _00_CGC_MAINOSC_UNDER10M; + SYSTEM.MOSCWTCR.BYTE = _06_CGC_OSC_WAIT_CYCLE_32768; + + /* Set main clock operation */ + SYSTEM.MOSCCR.BIT.MOSTP = 0U; + + /* Wait for main clock oscillator wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.MOOVF); + + /* Set system clock */ + sckcr_dummy = _00000000_CGC_PCLKD_DIV_1 | _00000100_CGC_PCLKB_DIV_2 | _00001000_CGC_PCLKA_DIV_2 | + _00010000_CGC_BCLK_DIV_2 | _00000000_CGC_ICLK_DIV_1 | _10000000_CGC_FCLK_DIV_2; + SYSTEM.SCKCR.LONG = sckcr_dummy; + + while (SYSTEM.SCKCR.LONG != sckcr_dummy); + + /* Set PLL circuit */ + SYSTEM.PLLCR.WORD = _0000_CGC_PLL_FREQ_DIV_1 | _0C00_CGC_PLL_FREQ_MUL_6_5; + SYSTEM.PLLCR2.BIT.PLLEN = 0U; + + /* Wait for PLL wait counter overflow */ + while (1U != SYSTEM.OSCOVFSR.BIT.PLOVF); + + /* Disable sub-clock */ + SYSTEM.SOSCCR.BIT.SOSTP = 1U; + + /* Wait for the register modification to complete */ + while (1U != SYSTEM.SOSCCR.BIT.SOSTP); + + /* Disable sub-clock */ + RTC.RCR3.BIT.RTCEN = 0U; + + /* Wait for the register modification to complete */ + while (0U != RTC.RCR3.BIT.RTCEN); + + /* Set BCLK */ + SYSTEM.SCKCR.BIT.PSTOP1 = 1U; + + /* Set memory wait cycle setting register */ + SYSTEM.MEMWAIT.BIT.MEMWAIT = 1U; + memorywaitcycle = SYSTEM.MEMWAIT.BYTE; + memorywaitcycle++; + + /* Set clock source */ + SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL; + + while (SYSTEM.SCKCR3.WORD != _0400_CGC_CLOCKSOURCE_PLL); + + /* Set LOCO */ + SYSTEM.LOCOCR.BIT.LCSTP = 1U; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h new file mode 100644 index 000000000..59e2c6850 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc.h @@ -0,0 +1,227 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef CGC_H +#define CGC_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ +/* + System Clock Control Register (SCKCR) +*/ +/* Peripheral Module Clock D (PCLKD) */ +#define _00000000_CGC_PCLKD_DIV_1 (0x00000000UL) /* x1 */ +#define _00000001_CGC_PCLKD_DIV_2 (0x00000001UL) /* x1/2 */ +#define _00000002_CGC_PCLKD_DIV_4 (0x00000002UL) /* x1/4 */ +#define _00000003_CGC_PCLKD_DIV_8 (0x00000003UL) /* x1/8 */ +#define _00000004_CGC_PCLKD_DIV_16 (0x00000004UL) /* x1/16 */ +#define _00000005_CGC_PCLKD_DIV_32 (0x00000005UL) /* x1/32 */ +#define _00000006_CGC_PCLKD_DIV_64 (0x00000006UL) /* x1/64 */ +/* Peripheral Module Clock B (PCLKB) */ +#define _00000000_CGC_PCLKB_DIV_1 (0x00000000UL) /* x1 */ +#define _00000100_CGC_PCLKB_DIV_2 (0x00000100UL) /* x1/2 */ +#define _00000200_CGC_PCLKB_DIV_4 (0x00000200UL) /* x1/4 */ +#define _00000300_CGC_PCLKB_DIV_8 (0x00000300UL) /* x1/8 */ +#define _00000400_CGC_PCLKB_DIV_16 (0x00000400UL) /* x1/16 */ +#define _00000500_CGC_PCLKB_DIV_32 (0x00000500UL) /* x1/32 */ +#define _00000600_CGC_PCLKB_DIV_64 (0x00000600UL) /* x1/64 */ +/* Peripheral Module Clock A (PCLKA) */ +#define _00000000_CGC_PCLKA_DIV_1 (0x00000000UL) /* x1 */ +#define _00001000_CGC_PCLKA_DIV_2 (0x00001000UL) /* x1/2 */ +#define _00002000_CGC_PCLKA_DIV_4 (0x00002000UL) /* x1/4 */ +#define _00003000_CGC_PCLKA_DIV_8 (0x00003000UL) /* x1/8 */ +#define _00004000_CGC_PCLKA_DIV_16 (0x00004000UL) /* x1/16 */ +#define _00005000_CGC_PCLKA_DIV_32 (0x00005000UL) /* x1/32 */ +#define _00006000_CGC_PCLKA_DIV_64 (0x00006000UL) /* x1/64 */ +/* External Bus Clock (BCLK) */ +#define _00000000_CGC_BCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _00010000_CGC_BCLK_DIV_2 (0x00010000UL) /* x1/2 */ +#define _00020000_CGC_BCLK_DIV_4 (0x00020000UL) /* x1/4 */ +#define _00030000_CGC_BCLK_DIV_8 (0x00030000UL) /* x1/8 */ +#define _00040000_CGC_BCLK_DIV_16 (0x00040000UL) /* x1/16 */ +#define _00050000_CGC_BCLK_DIV_32 (0x00050000UL) /* x1/32 */ +#define _00060000_CGC_BCLK_DIV_64 (0x00060000UL) /* x1/64 */ +/* System Clock (ICLK) */ +#define _00000000_CGC_ICLK_DIV_1 (0x00000000UL) /* x1 */ +#define _01000000_CGC_ICLK_DIV_2 (0x01000000UL) /* x1/2 */ +#define _02000000_CGC_ICLK_DIV_4 (0x02000000UL) /* x1/4 */ +#define _03000000_CGC_ICLK_DIV_8 (0x03000000UL) /* x1/8 */ +#define _04000000_CGC_ICLK_DIV_16 (0x04000000UL) /* x1/16 */ +#define _05000000_CGC_ICLK_DIV_32 (0x05000000UL) /* x1/32 */ +#define _06000000_CGC_ICLK_DIV_64 (0x06000000UL) /* x1/64 */ +/* System Clock (FCLK) */ +#define _00000000_CGC_FCLK_DIV_1 (0x00000000UL) /* x1 */ +#define _10000000_CGC_FCLK_DIV_2 (0x10000000UL) /* x1/2 */ +#define _20000000_CGC_FCLK_DIV_4 (0x20000000UL) /* x1/4 */ +#define _30000000_CGC_FCLK_DIV_8 (0x30000000UL) /* x1/8 */ +#define _40000000_CGC_FCLK_DIV_16 (0x40000000UL) /* x1/16 */ +#define _50000000_CGC_FCLK_DIV_32 (0x50000000UL) /* x1/32 */ +#define _60000000_CGC_FCLK_DIV_64 (0x60000000UL) /* x1/64 */ + +/* + System Clock Control Register 3 (SCKCR3) +*/ +#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLOCKSOURCE_PLL (0x0400U) /* PLL circuit */ + +/* + PLL Control Register (PLLCR) +*/ +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_4 (0x0002U) /* x1/4 */ +/* Frequency Multiplication Factor Select (STC[5:0]) */ +#define _0700_CGC_PLL_FREQ_MUL_4_0 (0x0700U) /* x4 */ +#define _0800_CGC_PLL_FREQ_MUL_4_5 (0x0800U) /* x4.5 */ +#define _0900_CGC_PLL_FREQ_MUL_5_0 (0x0900U) /* x5 */ +#define _0A00_CGC_PLL_FREQ_MUL_5_5 (0x0A00U) /* x5.5 */ +#define _0B00_CGC_PLL_FREQ_MUL_6_0 (0x0B00U) /* x6 */ +#define _0C00_CGC_PLL_FREQ_MUL_6_5 (0x0C00U) /* x6.5 */ +#define _0D00_CGC_PLL_FREQ_MUL_7_0 (0x0D00U) /* x7 */ +#define _0E00_CGC_PLL_FREQ_MUL_7_5 (0x0E00U) /* x7.5 */ +#define _0F00_CGC_PLL_FREQ_MUL_8_0 (0x0F00U) /* x8 */ +#define _1000_CGC_PLL_FREQ_MUL_8_5 (0x1000U) /* x8.5 */ +#define _1100_CGC_PLL_FREQ_MUL_9_0 (0x1100U) /* x9 */ +#define _1200_CGC_PLL_FREQ_MUL_9_5 (0x1200U) /* x9.5 */ +#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300U) /* x10 */ +#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400U) /* x10.5 */ +#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500U) /* x11 */ +#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600U) /* 11.5 */ +#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700U) /* x12 */ +#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800U) /* x12.5 */ +#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900U) /* x13 */ +#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1A00U) /* x13.5 */ +/* + USB-dedicated PLL Control Register (UPLLCR) +*/ +/* USB-dedicated PLL Input Frequency Division Ratio Select (UPLIDIV[1:0]) */ +#define _0000_CGC_UPLL_DIV_1 (0x0000U) /* x1 */ +#define _0001_CGC_UPLL_DIV_2 (0x0001U) /* x1/2 */ +#define _0002_CGC_UPLL_DIV_4 (0x0002U) /* x1/4 */ +/* UCLK Source USB-Dedicated PLL Select (UCKUPLLSEL) */ +#define _0000_CGC_UCLK_SYSCLK (0x0000U) /* System clock is selected as UCLK */ +#define _0010_CGC_UCLK_USBPLL (0x0010U) /* USB-dedicated PLL is selected as UCLK */ +/* Frequency Multiplication Factor Select (USTC[5:0]) */ +#define _0700_CGC_UPLL_MUL_4 (0x0700U) /* x4 */ +#define _0B00_CGC_UPLL_MUL_6 (0x0B00U) /* x6 */ +#define _0F00_CGC_UPLL_MUL_8 (0x0F00U) /* x8 */ +#define _1700_CGC_UPLL_MUL_12 (0x1700U) /* x12 */ + +/* + High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) +*/ +/* HOCO Frequency Setting (HCFRQ[1:0]) */ +#define _00_CGC_HOCO_CLK_32 (0x00U) /* 32 MHz */ +#define _03_CGC_HOCO_CLK_54 (0x03U) /* 54 MHz */ + +/* + Oscillation Stop Detection Control Register (OSTDCR) +*/ +/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */ +#define _00_CGC_OSC_STOP_INT_DISABLE (0x00U) /* The oscillation stop detection interrupt is disabled */ +#define _01_CGC_OSC_STOP_INT_ENABLE (0x01U) /* The oscillation stop detection interrupt is enabled */ +/* Oscillation Stop Detection Function Enable (OSTDE) */ +#define _00_CGC_OSC_STOP_DISABLE (0x00U) /* Oscillation stop detection function is disabled */ +#define _80_CGC_OSC_STOP_ENABLE (0x80U) /* Oscillation stop detection function is enabled */ + +/* + Main Clock Oscillator Wait Control Register (MOSCWTCR) +*/ +/* Main Clock Oscillator Wait Time (MSTS[4:0]) */ +#define _00_CGC_OSC_WAIT_CYCLE_2 (0x00U) /* Wait time = 2 cycles */ +#define _01_CGC_OSC_WAIT_CYCLE_1024 (0x01U) /* Wait time = 1024 cycles */ +#define _02_CGC_OSC_WAIT_CYCLE_2048 (0x02U) /* Wait time = 2048 cycles */ +#define _03_CGC_OSC_WAIT_CYCLE_4096 (0x03U) /* Wait time = 4096 cycles */ +#define _04_CGC_OSC_WAIT_CYCLE_8192 (0x04U) /* Wait time = 8192 cycles */ +#define _05_CGC_OSC_WAIT_CYCLE_16384 (0x05U) /* Wait time = 16384 cycles */ +#define _06_CGC_OSC_WAIT_CYCLE_32768 (0x06U) /* Wait time = 32768 cycles */ +#define _07_CGC_OSC_WAIT_CYCLE_65536 (0x07U) /* Wait time = 65536 cycles */ + +/* + Clock Output Control Register (CKOCR) +*/ +/* Clock Output Source Select (CKOSEL[2:0]) */ +#define _0000_CGC_CLKOUT_LOCO (0x0000U) /* LOCO */ +#define _0100_CGC_CLKOUT_HOCO (0x0100U) /* HOCO */ +#define _0200_CGC_CLKOUT_MAINCLK (0x0200U) /* Main clock oscillator */ +#define _0300_CGC_CLKOUT_SUBCLK (0x0300U) /* Sub-clock oscillator */ +#define _0400_CGC_CLKOUT_PLLCLK (0x0400U) /* PLL clock oscillator */ +/* Clock Output Division Ratio Select (CKODIV[2:0]) */ +#define _0000_CGC_CLKOUT_DIV_1 (0x0000U) /* x1 */ +#define _1000_CGC_CLKOUT_DIV_2 (0x1000U) /* x1/2 */ +#define _2000_CGC_CLKOUT_DIV_4 (0x2000U) /* x1/4 */ +#define _3000_CGC_CLKOUT_DIV_8 (0x3000U) /* x1/8 */ +#define _4000_CGC_CLKOUT_DIV_16 (0x4000U) /* x1/16 */ +/* Clock Output Control (CKOSTP) */ +#define _0000_CGC_CLKOUT_ENABLE (0x0000U) /* CLKOUT pin output is operating */ +#define _8000_CGC_CLKOUT_DISABLE (0x8000U) /* CLKOUT pin output is stopped (fixed at low level) */ + +/* + Main Clock Oscillator Forced Oscillation Control Register (MOFCR) +*/ +/* Main Oscillator Drive Capability Switch (MODRV21) */ +#define _00_CGC_MAINOSC_UNDER10M (0x00U) /* 1 MHz to 10 MHz */ +#define _20_CGC_MAINOSC_OVER10M (0x20U) /* 10 MHz to 20 MHz */ +/* Main Clock Oscillator Switch (MOSEL) */ +#define _00_CGC_MAINOSC_RESONATOR (0x00U) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40U) /* External oscillator input */ + +/* + Low-power timer control register 1 (LPTCR1) +*/ +/* Low-Power Timer Clock Division Ratio Select (LPCNTPSSEL[2:0]) */ +#define _01_CGC_LPT_CLK_DIV_2 (0x01U) /* x1/2 */ +#define _02_CGC_LPT_CLK_DIV_4 (0x02U) /* x1/4 */ +#define _03_CGC_LPT_CLK_DIV_8 (0x03U) /* x1/8 */ +#define _04_CGC_LPT_CLK_DIV_16 (0x04U) /* x1/16 */ +#define _05_CGC_LPT_CLK_DIV_32 (0x05U) /* x1/32 */ +/* Low-Power Timer Clock Source Select (LPCNTCKSEL) */ +#define _00_CGC_LPT_SOURCE_SUB (0x00U) /* Sub-clock */ +#define _10_CGC_LPT_SOURCE_IWDT (0x10U) /* IWDT-dedicated on-chip */ + + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void R_CGC_Create(void); + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c new file mode 100644 index 000000000..4b653fff0 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_cgc_user.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_cgc_user.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements device driver for CGC module. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c new file mode 100644 index 000000000..430cda236 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_dbsct.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_dbsct.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Setting of B. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#pragma unpack + +#pragma section C C$DSEC +extern const struct { + uint8_t *rom_s; /* Start address of the initialized data section in ROM */ + uint8_t *rom_e; /* End address of the initialized data section in ROM */ + uint8_t *ram_s; /* Start address of the initialized data section in RAM */ +} _DTBL[] = { + { __sectop("D"), __secend("D"), __sectop("R") }, + { __sectop("D_2"), __secend("D_2"), __sectop("R_2") }, + { __sectop("D_1"), __secend("D_1"), __sectop("R_1") } +}; +#pragma section C C$BSEC +extern const struct { + uint8_t *b_s; /* Start address of non-initialized data section */ + uint8_t *b_e; /* End address of non-initialized data section */ +} _BTBL[] = { + { __sectop("B"), __secend("B") }, + { __sectop("B_2"), __secend("B_2") }, + { __sectop("B_1"), __secend("B_1") } +}; + +#pragma section + +/* +** CTBL prevents excessive output of L1100 messages when linking. +** Even if CTBL is deleted, the operation of the program does not change. +*/ +uint8_t * const _CTBL[] = { + __sectop("C_1"), __sectop("C_2"), __sectop("C"), + __sectop("W_1"), __sectop("W_2"), __sectop("W"), + __sectop("L"), __sectop("SU"), + __sectop("C$DSEC"), __sectop("C$BSEC"), + __sectop("C$INIT"), __sectop("C$VTBL"), __sectop("C$VECT") +}; + +#pragma packoption + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c new file mode 100644 index 000000000..30fdc9df3 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_hardware_setup.c @@ -0,0 +1,87 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_hardware_setup.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements system initializing function. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: R_Systeminit +* Description : This function initializes every macro. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_Systeminit(void) +{ + /* Enable writing to registers related to operating modes, LPC, LPT, LVD, CGC and software reset */ + SYSTEM.PRCR.WORD = 0xA50FU; + + /* Enable writing to MPC pin function control registers */ + MPC.PWPR.BIT.B0WI = 0U; + MPC.PWPR.BIT.PFSWE = 1U; + + /* Set peripheral settings */ + R_CGC_Create(); + + /* Disable writing to MPC pin function control registers */ + MPC.PWPR.BIT.PFSWE = 0U; + MPC.PWPR.BIT.B0WI = 1U; + + /* Enable protection */ + SYSTEM.PRCR.WORD = 0xA500U; +} +/*********************************************************************************************************************** +* Function Name: HardwareSetup +* Description : This function initializes hardware setting. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void HardwareSetup(void) +{ + R_Systeminit(); +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c new file mode 100644 index 000000000..2343d7c46 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_intprg.c @@ -0,0 +1,99 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_intprg.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Setting of B. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include "r_cg_vect.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#pragma section IntPRG + +/* Undefined Instruction Exception */ +void r_undefined_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Privileged Instruction Exception */ +void r_privileged_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Floating Point Exception */ +void r_floatingpoint_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Access Exception */ +void r_access_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Reserved */ +void r_reserved_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* NMI */ +void r_nmi_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* BRK */ +void r_brk_exception(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h new file mode 100644 index 000000000..fde1c5181 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_macrodriver.h @@ -0,0 +1,100 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_macrodriver.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements general head file. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef MODULEID_H +#define MODULEID_H +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "../iodefine.h" +#include + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + +/* Status list definition */ +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) /* error argument input error */ +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + +#endif + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#ifndef __TYPEDEF__ + #ifndef _STD_USING_INT_TYPES + #define _SYS_INT_TYPES_H + #ifndef _STD_USING_BIT_TYPES + #define __int8_t_defined + typedef signed char int8_t; + typedef signed short int16_t; + #endif + + typedef unsigned char uint8_t; + typedef unsigned short uint16_t; + typedef signed long int32_t; + typedef unsigned long uint32_t; + + typedef signed char int_least8_t; + typedef signed short int_least16_t; + typedef signed long int_least32_t; + typedef unsigned char uint_least8_t; + typedef unsigned short uint_least16_t; + typedef unsigned long uint_least32_t; + #endif + + typedef unsigned short MD_STATUS; + #define __TYPEDEF__ +#endif + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +void HardwareSetup(void); +void R_Systeminit(void); + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_main.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_main.c new file mode 100644 index 000000000..d8ae57956 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_main.c @@ -0,0 +1,90 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_main.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file implements main function. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_cgc.h" +/* Start user code for include. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +/* Start user code for global. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + + +void R_MAIN_UserInit(void); +/*********************************************************************************************************************** +* Function Name: main +* Description : This function implements main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void main(void) +{ + R_MAIN_UserInit(); + /* Start user code. Do not edit comment generated here */ + while (1U) + { + ; + } + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: R_MAIN_UserInit +* Description : This function adds user code before implementing main function. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void R_MAIN_UserInit(void) +{ + /* Start user code. Do not edit comment generated here */ + uint16_t protect_dummy = (uint16_t)(SYSTEM.PRCR.WORD & 0x000FU); + + /* Disable protect bit */ + SYSTEM.PRCR.WORD = 0xA50FU; + + SYSTEM.VBATTCR.BYTE = 0x81U; + + /* Restore the previous state of the protect register */ + SYSTEM.PRCR.WORD = (uint16_t)(0xA500U | protect_dummy); + /* End user code. Do not edit comment generated here */ +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c new file mode 100644 index 000000000..d8b14c896 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_resetprg.c @@ -0,0 +1,94 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_resetprg.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Reset program. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include <_h_c_lib.h> +//#include // Remove the comment when you use errno +//#include // Remove the comment when you use rand() +#include "r_cg_stacksct.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif +void PowerON_Reset_PC(void); +void main(void); +#ifdef __cplusplus +} +#endif + +#define PSW_init 0x00010000 /* PSW bit pattern */ +#define FPSW_init 0x00000000 /* FPSW bit base pattern */ + +#pragma section ResetPRG /* output PowerON_Reset_PC to PResetPRG section */ + +#pragma entry PowerON_Reset_PC + +void PowerON_Reset_PC(void) +{ +#ifdef __RXV2 + set_extb(__sectop("EXCEPTVECT")); +#endif + set_intb(__sectop("C$VECT")); + +#ifdef __ROZ /* Initialize FPSW */ +#define _ROUND 0x00000001 /* Let FPSW RMbits=01 (round to zero) */ +#else +#define _ROUND 0x00000000 /* Let FPSW RMbits=00 (round to nearest) */ +#endif +#ifdef __DOFF +#define _DENOM 0x00000100 /* Let FPSW DNbit=1 (denormal as zero) */ +#else +#define _DENOM 0x00000000 /* Let FPSW DNbit=0 (denormal as is) */ +#endif + + set_fpsw(FPSW_init | _ROUND | _DENOM); + + _INITSCT(); /* Initialize Sections */ + HardwareSetup(); /* Use Hardware Setup */ + nop(); + set_psw(PSW_init); /* Set Ubit & Ibit for PSW */ + main(); + brk(); +} +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c new file mode 100644 index 000000000..2d118c276 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.c @@ -0,0 +1,86 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Program of sbrk. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include +#include +#include "r_cg_sbrk.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + +int8_t *sbrk(size_t size); + +extern int8_t *_s1ptr; + +union HEAP_TYPE +{ + int16_t dummy ; /* Dummy for 4-byte boundary */ + int8_t heap[HEAPSIZE]; /* Declaration of the area managed by sbrk */ +}; + +static union HEAP_TYPE heap_area ; + +/* End address allocated by sbrk */ +static int8_t *brk = (int8_t *) &heap_area; + +/**************************************************************************/ +/* sbrk:Memory area allocation */ +/* Return value:Start address of allocated area (Pass) */ +/* -1 (Failure) */ +/**************************************************************************/ +int8_t *sbrk(size_t size) /* Assigned area size */ +{ + int8_t *p; + + if (brk+size > heap_area.heap + HEAPSIZE) /* Empty area size */ + { + p = (int8_t *)-1; + } + else + { + p = brk; /* Area assignment */ + brk += size; /* End address update */ + } + + return p; +} + +/* Start user code for adding. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h new file mode 100644 index 000000000..dc14a2132 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_sbrk.h @@ -0,0 +1,48 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sbrk.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Header file of sbrk file. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef _SBRK_H +#define _SBRK_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ +#define HEAPSIZE (0x400U) /* Size of area managed by sbrk */ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h new file mode 100644 index 000000000..40a247509 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_stacksct.h @@ -0,0 +1,50 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_stacksct.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : Setting of Stack area. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef _STACKSCT_H +#define _STACKSCT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +#pragma stacksize su = 0x100 +#pragma stacksize si = 0x300 + + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h new file mode 100644 index 000000000..767d34492 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_userdefine.h @@ -0,0 +1,38 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_userdefine.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file includes user definition. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef _USER_DEF_H +#define _USER_DEF_H + +/*********************************************************************************************************************** +User definitions +***********************************************************************************************************************/ +#define FAST_INTERRUPT_VECTOR 0 + +/* Start user code for function. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h new file mode 100644 index 000000000..49c995016 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vect.h @@ -0,0 +1,79 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_vect.h +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file contains definition of vector. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ +#ifndef _VECT_H +#define _VECT_H + +/*********************************************************************************************************************** +Macro definitions (Register bit) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Global functions +***********************************************************************************************************************/ +/* Undefined */ +#pragma interrupt (r_undefined_exception) +void r_undefined_exception(void); + +/* Access Exception */ +#pragma interrupt (r_access_exception) +void r_access_exception(void); + +/* Privileged Instruction Exception */ +#pragma interrupt (r_privileged_exception) +void r_privileged_exception(void); + +/* Floating Point Exception */ +#pragma interrupt (r_floatingpoint_exception) +void r_floatingpoint_exception(void); + +/* Reserved */ +#pragma interrupt (r_reserved_exception) +void r_reserved_exception(void); + +/* NMI */ +#pragma interrupt (r_nmi_exception) +void r_nmi_exception(void); + +/* BRK */ +#pragma interrupt (r_brk_exception(vect=0)) +void r_brk_exception(void); + +/*;<> */ +/*;Power On Reset PC */ +extern void PowerON_Reset_PC(void); +/*;<> */ + +#endif \ No newline at end of file diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c new file mode 100644 index 000000000..ddfb8b3de --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/cg_src/r_cg_vecttbl.c @@ -0,0 +1,130 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. +* No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED +* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY +* LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, +* INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR +* ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2015 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_vecttbl.c +* Version : Code Generator for RX231 V1.00.00.03 [10 Jul 2015] +* Device(s) : R5F52318AxFP +* Tool-Chain : CCRX +* Description : This file initializes the vector table. +* Creation Date: 23/09/2015 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_vect.h" +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ + + +#define OFS0_VAL 0xFFFFFFFFUL +#define OFS1_VAL 0xFFFFFFFFUL + +#pragma section C EXCEPTVECT +/* Start user code for adding. Do not edit comment generated here */ +void (*const Excpt_Vectors[])(void) = { +/*;0xffffff80 MDE register */ +#ifdef __BIG + /* Big endian */ + (void (*)(void))0xfffffff8, +#else + /* Little endian */ + (void (*)(void))0xffffffff, +#endif +/*;0xffffff84 Reserved */ + r_reserved_exception, +/*;0xffffff88 OFS1 register */ + (void (*) (void)) OFS1_VAL, +/*;0xffffff8c OFS0 register */ + (void (*) (void)) OFS0_VAL, +/*;0xffffff90 Reserved */ + r_reserved_exception, +/*;0xffffff94 Reserved */ + r_reserved_exception, +/*;0xffffff98 Reserved */ + r_reserved_exception, +/*;0xffffff9c Reserved */ + r_reserved_exception, +/*;0xffffffa0 ID */ + (void (*)(void))0xffffffff, +/*;0xffffffa4 ID */ + (void (*)(void))0xffffffff, +/*;0xffffffa8 ID */ + (void (*)(void))0xffffffff, +/*;0xffffffac ID */ + (void (*)(void))0xffffffff, +/*;0xffffffb0 Reserved */ + r_reserved_exception, +/*;0xffffffb4 Reserved */ + r_reserved_exception, +/*;0xffffffb8 Reserved */ + r_reserved_exception, +/*;0xffffffbc Reserved */ + r_reserved_exception, +/*;0xffffffc0 Reserved */ + r_reserved_exception, +/*;0xffffffc4 Reserved */ + r_reserved_exception, +/*;0xffffffc8 Reserved */ + r_reserved_exception, +/*;0xffffffcc Reserved */ + r_reserved_exception, +/*;0xffffffd0 Exception(Privileged Instruction) */ + r_privileged_exception, +/*;0xffffffd4 Exception(Access) */ + r_access_exception, +/*;0xffffffd8 Reserved */ + r_reserved_exception, +/*;0xffffffdc Exception(Undefined Instruction) */ + r_undefined_exception, +/*;0xffffffe0 Reserved */ + r_reserved_exception, +/*;0xffffffe4 Exception(Floating Point) */ + r_floatingpoint_exception, +/*;0xffffffe8 Reserved */ + r_reserved_exception, +/*;0xffffffec Reserved */ + r_reserved_exception, +/*;0xfffffff0 Reserved */ + r_reserved_exception, +/*;0xfffffff4 Reserved */ + r_reserved_exception, +/*;0xfffffff8 NMI */ + r_nmi_exception, +}; +/* End user code. Do not edit comment generated here */ + +#pragma section C RESETVECT +void (*const Reset_Vectors[])(void) = { +/*;<> */ +/*;Power On Reset PC */ + /*(void*)*/ PowerON_Reset_PC +/*;<> */ +}; diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/iodefine.h b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/iodefine.h new file mode 100644 index 000000000..0e1684ea2 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/iodefine.h @@ -0,0 +1,12985 @@ +/***************************************************************/ +/* */ +/* PROJECT NAME : RTOSDemo */ +/* FILE : iodefine.h */ +/* DESCRIPTION : I/O register definitions */ +/* CPU SERIES : RX200 */ +/* CPU TYPE : RX231 */ +/* */ +/* This file is generated by e2 studio. */ +/* */ +/***************************************************************/ + + + + +/********************************************************************************* +* +* Device : RX/RX200/RX231 +* +* File Name : iodefine.h +* +* Abstract : Definition of I/O Register. +* +* History : 0.5A (2014-09-18) [Hardware Manual Revision : 0.50] +* : 1.0A (2015-05-18) [Hardware Manual Revision : 1.00] +* : 1.0C (2015-07-21) [Hardware Manual Revision : 1.00] +* +* NOTE : THIS IS A TYPICAL EXAMPLE. +* +* Copyright (C) 2015 (2014) Renesas Electronics Corporation. +* +*********************************************************************************/ +/********************************************************************************/ +/* */ +/* DESCRIPTION : Definition of ICU Register */ +/* CPU TYPE : RX231 */ +/* */ +/* Usage : IR,DTCER,IER,IPR of ICU Register */ +/* The following IR, DTCE, IEN, IPR macro functions simplify usage. */ +/* The bit access operation is "Bit_Name(interrupt source,name)". */ +/* A part of the name can be omitted. */ +/* for example : */ +/* IR(MTU0,TGIA0) = 0; expands to : */ +/* ICU.IR[114].BIT.IR = 0; */ +/* */ +/* DTCE(ICU,IRQ0) = 1; expands to : */ +/* ICU.DTCER[64].BIT.DTCE = 1; */ +/* */ +/* IEN(CMT0,CMI0) = 1; expands to : */ +/* ICU.IER[0x03].BIT.IEN4 = 1; */ +/* */ +/* IPR(MTU1,TGIA1) = 2; expands to : */ +/* IPR(MTU1,TGI ) = 2; // TGIA1,TGIB1 share IPR level. */ +/* ICU.IPR[121].BIT.IPR = 2; */ +/* */ +/* IPR(SCI0,ERI0) = 3; expands to : */ +/* IPR(SCI0, ) = 3; // SCI0 uses single IPR for all sources. */ +/* ICU.IPR[214].BIT.IPR = 3; */ +/* */ +/* Usage : #pragma interrupt Function_Identifier(vect=**) */ +/* The number of vector is "(interrupt source, name)". */ +/* for example : */ +/* #pragma interrupt INT_IRQ0(vect=VECT(ICU,IRQ0)) expands to : */ +/* #pragma interrupt INT_IRQ0(vect=64) */ +/* #pragma interrupt INT_CMT0_CMI0(vect=VECT(CMT0,CMI0)) expands to : */ +/* #pragma interrupt INT_CMT0_CMI0(vect=28) */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=VECT(MTU0,TGIA0)) expands to : */ +/* #pragma interrupt INT_MTU0_TGIA0(vect=114) */ +/* #pragma interrupt INT_TPU0_TGI0A(vect=VECT(TPU0,TGI0A)) expands to : */ +/* #pragma interrupt INT_TPU0_TGI0A(vect=142) */ +/* */ +/* Usage : MSTPCRA,MSTPCRB,MSTPCRC of SYSTEM Register */ +/* The bit access operation is "MSTP(name)". */ +/* The name that can be used is a macro name defined with "iodefine.h". */ +/* for example : */ +/* MSTP(TMR2) = 0; // TMR2,TMR3,TMR23 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA4 = 0; */ +/* MSTP(SCI0) = 0; // SCI0,SMCI0 expands to : */ +/* SYSTEM.MSTPCRB.BIT.MSTPB31 = 0; */ +/* MSTP(MTU4) = 0; // MTU,MTU0,MTU1,MTU2,MTU3,MTU4,MTU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA9 = 0; */ +/* MSTP(TPU4) = 0; // TPU,TPU0,TPU1,TPU2,TPU3,TPU4,TPU5 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA13 = 0; */ +/* MSTP(CMT3) = 0; // CMT2,CMT3 expands to : */ +/* SYSTEM.MSTPCRA.BIT.MSTPA14 = 0; */ +/* */ +/* */ +/********************************************************************************/ +#ifndef __RX231IODEFINE_HEADER__ +#define __RX231IODEFINE_HEADER__ +#pragma bit_order left +#pragma unpack +struct st_bsc { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char STSCLR:1; + } BIT; + } BERCLR; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TOEN:1; + unsigned char IGAEN:1; + } BIT; + } BEREN; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MST:3; + unsigned char :2; + unsigned char TO:1; + unsigned char IA:1; + } BIT; + } BERSR1; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ADDR:13; + unsigned short :3; + } BIT; + } BERSR2; + char wk3[4]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short BPEB:2; + unsigned short BPFB:2; + unsigned short BPHB:2; + unsigned short BPGB:2; + unsigned short BPIB:2; + unsigned short BPRO:2; + unsigned short BPRA:2; + } BIT; + } BUSPRI; + char wk4[7408]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS0MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS0WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS0WCR2; + char wk5[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS1MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS1WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS1WCR2; + char wk6[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS2MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS2WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS2WCR2; + char wk7[6]; + union { + unsigned short WORD; + struct { + unsigned short PRMOD:1; + unsigned short :5; + unsigned short PWENB:1; + unsigned short PRENB:1; + unsigned short :4; + unsigned short EWENB:1; + unsigned short :2; + unsigned short WRMOD:1; + } BIT; + } CS3MOD; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long CSRWAIT:5; + unsigned long :3; + unsigned long CSWWAIT:5; + unsigned long :5; + unsigned long CSPRWAIT:3; + unsigned long :5; + unsigned long CSPWWAIT:3; + } BIT; + } CS3WCR1; + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CSON:3; + unsigned long :1; + unsigned long WDON:3; + unsigned long :1; + unsigned long WRON:3; + unsigned long :1; + unsigned long RDON:3; + unsigned long :2; + unsigned long AWAIT:2; + unsigned long :1; + unsigned long WDOFF:3; + unsigned long :1; + unsigned long CSWOFF:3; + unsigned long :1; + unsigned long CSROFF:3; + } BIT; + } CS3WCR2; + char wk8[1990]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS0CR; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS0REC; + char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS1CR; + char wk11[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS1REC; + char wk12[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS2CR; + char wk13[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS2REC; + char wk14[6]; + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short MPXEN:1; + unsigned short :3; + unsigned short EMODE:1; + unsigned short :2; + unsigned short BSIZE:2; + unsigned short :3; + unsigned short EXENB:1; + } BIT; + } CS3CR; + char wk15[6]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short WRCV:4; + unsigned short :4; + unsigned short RRCV:4; + } BIT; + } CS3REC; + char wk16[68]; + union { + unsigned short WORD; + struct { + unsigned short RCVENM7:1; + unsigned short RCVENM6:1; + unsigned short RCVENM5:1; + unsigned short RCVENM4:1; + unsigned short RCVENM3:1; + unsigned short RCVENM2:1; + unsigned short RCVENM1:1; + unsigned short RCVENM0:1; + unsigned short RCVEN7:1; + unsigned short RCVEN6:1; + unsigned short RCVEN5:1; + unsigned short RCVEN4:1; + unsigned short RCVEN3:1; + unsigned short RCVEN2:1; + unsigned short RCVEN1:1; + unsigned short RCVEN0:1; + } BIT; + } CSRECEN; +}; + +struct st_cac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CFME:1; + } BIT; + } CACR0; + union { + unsigned char BYTE; + struct { + unsigned char EDGES:2; + unsigned char TCSS:2; + unsigned char FMCS:3; + unsigned char CACREFE:1; + } BIT; + } CACR1; + union { + unsigned char BYTE; + struct { + unsigned char DFS:2; + unsigned char RCDS:2; + unsigned char RSCS:3; + unsigned char RPS:1; + } BIT; + } CACR2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char OVFFCL:1; + unsigned char MENDFCL:1; + unsigned char FERRFCL:1; + unsigned char :1; + unsigned char OVFIE:1; + unsigned char MENDIE:1; + unsigned char FERRIE:1; + } BIT; + } CAICR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char OVFF:1; + unsigned char MENDF:1; + unsigned char FERRF:1; + } BIT; + } CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +}; + +struct st_rscan { + union { + unsigned short WORD; + struct { + unsigned short :3; + unsigned short TSSS:1; + unsigned short TSP:4; + unsigned short :3; + unsigned short DCS:1; + unsigned short MME:1; + unsigned short DRE:1; + unsigned short DCE:1; + unsigned short TPRI:1; + } BIT; + } GCFGL; + union { + unsigned short WORD; + struct { + unsigned short ITRCP:16; + } BIT; + } GCFGH; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short THLEIE:1; + unsigned short MEIE:1; + unsigned short DEIE:1; + unsigned short :5; + unsigned short GSLPR:1; + unsigned short GMDC:2; + } BIT; + } GCTRL; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short TSRST:1; + } BIT; + } GCTRH; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short GRAMINIT:1; + unsigned short GSLPSTS:1; + unsigned short GHLTSTS:1; + unsigned short GRSTSTS:1; + } BIT; + } GSTS; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char THLES:1; + unsigned char MES:1; + unsigned char DEF:1; + } BIT; + } GERFLL; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short TS:16; + } BIT; + } GTSC; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short RNC0:5; + } BIT; + } GAFLCFG; + union { + unsigned short WORD; + struct { + unsigned short :11; + unsigned short NRXMB:5; + } BIT; + } RMNB; + union { + unsigned short WORD; + struct { + unsigned short RMNS:16; + } BIT; + } RMND0; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short RFIGCV:3; + unsigned short RFIM:1; + unsigned short :1; + unsigned short RFDC:3; + unsigned short :6; + unsigned short RFIE:1; + unsigned short RFE:1; + } BIT; + } RFCC0; + union { + unsigned short WORD; + struct { + unsigned short RFIGCV:3; + unsigned short RFIM:1; + unsigned short :1; + unsigned short RFDC:3; + unsigned short :6; + unsigned short RFIE:1; + unsigned short RFE:1; + } BIT; + } RFCC1; + char wk2[4]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RFMC:6; + unsigned short :4; + unsigned short RFIF:1; + unsigned short RFMLT:1; + unsigned short RFFLL:1; + unsigned short RFEMP:1; + } BIT; + } RFSTS0; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RFMC:6; + unsigned short :4; + unsigned short RFIF:1; + unsigned short RFMLT:1; + unsigned short RFFLL:1; + unsigned short RFEMP:1; + } BIT; + } RFSTS1; + char wk3[4]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short RFPC:8; + } BIT; + } RFPCTR0; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short RFPC:8; + } BIT; + } RFPCTR1; + char wk4[20]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RF1MLT:1; + unsigned char RF0MLT:1; + } BIT; + } RFMSTS; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char RF1IF:1; + unsigned char RF0IF:1; + } BIT; + } RFISTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CF0IF:1; + } BIT; + } CFISTS; + char wk6[36]; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short THIF0:1; + unsigned short CFTIF0:1; + unsigned short TAIF0:1; + unsigned short TSIF0:1; + } BIT; + } GTINTSTS; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RPAGE:1; + } BIT; + } GRWCR; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short RTMPS:3; + unsigned short :8; + } BIT; + } GTSTCFG; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char RTME:1; + unsigned char :2; + } BIT; + } GTSTCTRL; + char wk7[5]; + union { + unsigned short WORD; + struct { + unsigned short LOCK:16; + } BIT; + } GLOCKK; + char wk8[10]; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL0; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL0; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH0; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH0; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML0; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS0; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH0; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR0; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL0; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF00; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH0; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF10; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL1; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF20; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH1; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF30; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML1; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL1; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH1; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH1; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL1; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS1; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH1; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR1; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL2; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF01; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH2; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF11; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML2; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF21; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH2; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF31; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL2; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL2; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH2; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH2; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL3; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS2; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH3; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR2; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML3; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF02; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH3; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF12; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL3; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF22; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH3; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF32; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL4; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL3; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH4; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH3; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML4; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS3; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH4; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR3; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL4; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF03; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH4; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF13; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL5; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF23; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH5; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF33; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML5; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL4; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH5; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH4; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL5; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS4; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH5; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR4; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL6; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF04; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH6; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF14; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML6; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF24; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH6; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF34; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL6; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL5; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH6; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH5; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL7; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS5; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH7; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR5; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML7; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF05; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH7; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF15; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL7; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF25; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH7; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF35; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL8; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL6; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH8; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH6; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML8; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS6; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH8; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR6; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL8; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF06; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH8; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF16; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL9; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF26; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH9; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF36; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML9; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL7; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH9; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH7; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL9; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS7; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH9; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR7; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL10; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF07; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH10; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF17; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML10; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF27; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH10; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF37; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL10; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL8; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH10; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH8; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL11; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS8; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH11; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR8; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML11; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF08; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH11; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF18; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL11; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF28; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH11; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF38; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL12; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL9; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH12; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH9; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML12; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS9; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH12; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR9; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL12; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF09; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH12; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF19; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL13; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF29; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH13; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF39; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML13; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL10; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH13; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH10; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL13; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS10; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH13; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR10; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL14; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF010; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH14; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF110; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML14; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF210; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH14; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF310; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL14; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL11; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH14; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH11; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLID:16; + } BIT; + } GAFLIDL15; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS11; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDE:1; + unsigned short GAFLRTR:1; + unsigned short GAFLLB:1; + unsigned short GAFLID:13; + } BIT; + } GAFLIDH15; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR11; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDM:16; + } BIT; + } GAFLML15; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF011; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLIDEM:1; + unsigned short GAFLRTRM:1; + unsigned short :1; + unsigned short GAFLIDM:13; + } BIT; + } GAFLMH15; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF111; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLRMV:1; + unsigned short GAFLRMDP:7; + unsigned short :3; + unsigned short GAFLFDP4:1; + unsigned short :2; + unsigned short GAFLFDP1:1; + unsigned short GAFLFDP0:1; + } BIT; + } GAFLPL15; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF211; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short GAFLDLC:4; + unsigned short GAFLPTR:12; + } BIT; + } GAFLPH15; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF311; + }; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL12; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH12; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS12; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR12; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF012; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF112; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF212; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF312; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL13; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH13; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS13; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR13; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF013; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF113; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF213; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF313; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL14; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH14; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS14; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR14; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF014; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF114; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF214; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF314; + union { + unsigned short WORD; + struct { + unsigned short RMID:16; + } BIT; + } RMIDL15; + union { + unsigned short WORD; + struct { + unsigned short RMIDE:1; + unsigned short RMRTR:1; + unsigned short :1; + unsigned short RMID:13; + } BIT; + } RMIDH15; + union { + unsigned short WORD; + struct { + unsigned short RMTS:16; + } BIT; + } RMTS15; + union { + unsigned short WORD; + struct { + unsigned short RMDLC:4; + unsigned short RMPTR:12; + } BIT; + } RMPTR15; + union { + unsigned short WORD; + struct { + unsigned short RMDB1:8; + unsigned short RMDB0:8; + } BIT; + } RMDF015; + union { + unsigned short WORD; + struct { + unsigned short RMDB3:8; + unsigned short RMDB2:8; + } BIT; + } RMDF115; + union { + unsigned short WORD; + struct { + unsigned short RMDB5:8; + unsigned short RMDB4:8; + } BIT; + } RMDF215; + union { + unsigned short WORD; + struct { + unsigned short RMDB7:8; + unsigned short RMDB6:8; + } BIT; + } RMDF315; + char wk9[224]; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC0; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC1; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC2; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC3; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC4; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC5; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC6; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC7; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC8; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC9; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC10; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC11; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC12; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC13; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC14; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC15; + union { + union { + unsigned short WORD; + struct { + unsigned short RFID:16; + } BIT; + } RFIDL0; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC16; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFIDE:1; + unsigned short RFRTR:1; + unsigned short :1; + unsigned short RFID:13; + } BIT; + } RFIDH0; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC17; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFTS:16; + } BIT; + } RFTS0; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC18; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDLC:4; + unsigned short RFPTR:12; + } BIT; + } RFPTR0; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC19; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB1:8; + unsigned short RFDB0:8; + } BIT; + } RFDF00; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC20; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB3:8; + unsigned short RFDB2:8; + } BIT; + } RFDF10; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC21; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB5:8; + unsigned short RFDB4:8; + } BIT; + } RFDF20; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC22; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB7:8; + unsigned short RFDB6:8; + } BIT; + } RFDF30; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC23; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFID:16; + } BIT; + } RFIDL1; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC24; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFIDE:1; + unsigned short RFRTR:1; + unsigned short :1; + unsigned short RFID:13; + } BIT; + } RFIDH1; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC25; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFTS:16; + } BIT; + } RFTS1; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC26; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDLC:4; + unsigned short RFPTR:12; + } BIT; + } RFPTR1; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC27; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB1:8; + unsigned short RFDB0:8; + } BIT; + } RFDF01; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC28; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB3:8; + unsigned short RFDB2:8; + } BIT; + } RFDF11; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC29; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB5:8; + unsigned short RFDB4:8; + } BIT; + } RFDF21; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC30; + }; + union { + union { + unsigned short WORD; + struct { + unsigned short RFDB7:8; + unsigned short RFDB6:8; + } BIT; + } RFDF31; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC31; + }; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC32; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC33; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC34; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC35; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC36; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC37; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC38; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC39; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC40; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC41; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC42; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC43; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC44; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC45; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC46; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC47; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC48; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC49; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC50; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC51; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC52; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC53; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC54; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC55; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC56; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC57; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC58; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC59; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC60; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC61; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC62; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC63; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC64; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC65; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC66; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC67; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC68; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC69; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC70; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC71; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC72; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC73; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC74; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC75; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC76; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC77; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC78; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC79; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC80; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC81; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC82; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC83; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC84; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC85; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC86; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC87; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC88; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC89; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC90; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC91; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC92; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC93; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC94; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC95; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC96; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC97; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC98; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC99; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC100; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC101; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC102; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC103; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC104; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC105; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC106; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC107; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC108; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC109; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC110; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC111; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC112; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC113; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC114; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC115; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC116; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC117; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC118; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC119; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC120; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC121; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC122; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC123; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC124; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC125; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC126; + union { + unsigned short WORD; + struct { + unsigned short RDTA:16; + } BIT; + } RPGACC127; +}; + +struct st_rscan0 { + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short BRP:10; + } BIT; + } CFGL; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short SJW:2; + unsigned short :1; + unsigned short TSEG2:3; + unsigned short TSEG1:4; + } BIT; + } CFGH; + union { + unsigned short WORD; + struct { + unsigned short ALIE:1; + unsigned short BLIE:1; + unsigned short OLIE:1; + unsigned short BORIE:1; + unsigned short BOEIE:1; + unsigned short EPIE:1; + unsigned short EWIE:1; + unsigned short BEIE:1; + unsigned short :4; + unsigned short RTBO:1; + unsigned short CSLPR:1; + unsigned short CHMDC:2; + } BIT; + } CTRL; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short CTMS:2; + unsigned short CTME:1; + unsigned short ERRD:1; + unsigned short BOM:2; + unsigned short :4; + unsigned short TAIE:1; + } BIT; + } CTRH; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short COMSTS:1; + unsigned short RECSTS:1; + unsigned short TRMSTS:1; + unsigned short BOSTS:1; + unsigned short EPSTS:1; + unsigned short CSLPSTS:1; + unsigned short CHLTSTS:1; + unsigned short CRSTSTS:1; + } BIT; + } STSL; + union { + unsigned short WORD; + struct { + unsigned short TEC:8; + unsigned short REC:8; + } BIT; + } STSH; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short ADERR:1; + unsigned short B0ERR:1; + unsigned short B1ERR:1; + unsigned short CERR:1; + unsigned short AERR:1; + unsigned short FERR:1; + unsigned short SERR:1; + unsigned short ALF:1; + unsigned short BLF:1; + unsigned short OVLF:1; + unsigned short BORF:1; + unsigned short BOEF:1; + unsigned short EPF:1; + unsigned short EWF:1; + unsigned short BEF:1; + } BIT; + } ERFLL; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short CRCREG:15; + } BIT; + } ERFLH; + char wk0[64]; + union { + unsigned short WORD; + struct { + unsigned short CFIGCV:3; + unsigned short CFIM:1; + unsigned short :1; + unsigned short CFDC:3; + unsigned short :5; + unsigned short CFTXIE:1; + unsigned short CFRXIE:1; + unsigned short CFE:1; + } BIT; + } CFCCL0; + union { + unsigned short WORD; + struct { + unsigned short CFITT:8; + unsigned short :2; + unsigned short CFTML:2; + unsigned short CFITR:1; + unsigned short CFITSS:1; + unsigned short CFM:2; + } BIT; + } CFCCH0; + char wk1[4]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short CFMC:6; + unsigned short :3; + unsigned short CFTXIF:1; + unsigned short CFRXIF:1; + unsigned short CFMLT:1; + unsigned short CFFLL:1; + unsigned short CFEMP:1; + } BIT; + } CFSTS0; + char wk2[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CFPC:8; + } BIT; + } CFPCTR0; + char wk3[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CF0MLT:1; + } BIT; + } CFMSTS; + char wk4[2]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TMOM:1; + unsigned char TMTAR:1; + unsigned char TMTR:1; + } BIT; + } TMC0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TMOM:1; + unsigned char TMTAR:1; + unsigned char TMTR:1; + } BIT; + } TMC1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TMOM:1; + unsigned char TMTAR:1; + unsigned char TMTR:1; + } BIT; + } TMC2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TMOM:1; + unsigned char TMTAR:1; + unsigned char TMTR:1; + } BIT; + } TMC3; + char wk5[4]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TMTARM:1; + unsigned char TMTRM:1; + unsigned char TMTRF:2; + unsigned char TMTSTS:1; + } BIT; + } TMSTS0; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TMTARM:1; + unsigned char TMTRM:1; + unsigned char TMTRF:2; + unsigned char TMTSTS:1; + } BIT; + } TMSTS1; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TMTARM:1; + unsigned char TMTRM:1; + unsigned char TMTRF:2; + unsigned char TMTSTS:1; + } BIT; + } TMSTS2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char TMTARM:1; + unsigned char TMTRM:1; + unsigned char TMTRF:2; + unsigned char TMTSTS:1; + } BIT; + } TMSTS3; + char wk6[4]; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short TMTRSTS3:1; + unsigned short TMTRSTS2:1; + unsigned short TMTRSTS1:1; + unsigned short TMTRSTS0:1; + } BIT; + } TMTRSTS; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short TMTCSTS3:1; + unsigned short TMTCSTS2:1; + unsigned short TMTCSTS1:1; + unsigned short TMTCSTS0:1; + } BIT; + } TMTCSTS; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short TMTASTS3:1; + unsigned short TMTASTS2:1; + unsigned short TMTASTS1:1; + unsigned short TMTASTS0:1; + } BIT; + } TMTASTS; + union { + unsigned short WORD; + struct { + unsigned short :12; + unsigned short TMIE3:1; + unsigned short TMIE2:1; + unsigned short TMIE1:1; + unsigned short TMIE0:1; + } BIT; + } TMIEC; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short THLDTE:1; + unsigned short THLIM:1; + unsigned short THLIE:1; + unsigned short :7; + unsigned short THLE:1; + } BIT; + } THLCC0; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short THLMC:4; + unsigned short :4; + unsigned short THLIF:1; + unsigned short THLELT:1; + unsigned short THLFLL:1; + unsigned short THLEMP:1; + } BIT; + } THLSTS0; + char wk8[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short THLPC:8; + } BIT; + } THLPCTR0; + char wk9[602]; + union { + unsigned short WORD; + struct { + unsigned short CFID:16; + } BIT; + } CFIDL0; + union { + unsigned short WORD; + struct { + unsigned short CFIDE:1; + unsigned short CFRTR:1; + unsigned short THLEN:1; + unsigned short CFID:13; + } BIT; + } CFIDH0; + union { + unsigned short WORD; + struct { + unsigned short CFTS:16; + } BIT; + } CFTS0; + union { + unsigned short WORD; + struct { + unsigned short CFDLC:4; + unsigned short CFPTR:12; + } BIT; + } CFPTR0; + union { + unsigned short WORD; + struct { + unsigned short CFDB1:8; + unsigned short CFDB0:8; + } BIT; + } CFDF00; + union { + unsigned short WORD; + struct { + unsigned short CFDB3:8; + unsigned short CFDB2:8; + } BIT; + } CFDF10; + union { + unsigned short WORD; + struct { + unsigned short CFDB5:8; + unsigned short CFDB4:8; + } BIT; + } CFDF20; + union { + unsigned short WORD; + struct { + unsigned short CFDB7:8; + unsigned short CFDB6:8; + } BIT; + } CFDF30; + char wk10[16]; + union { + unsigned short WORD; + struct { + unsigned short TMID:16; + } BIT; + } TMIDL0; + union { + unsigned short WORD; + struct { + unsigned short TMIDE:1; + unsigned short TMRTR:1; + unsigned short THLEN:1; + unsigned short TMID:13; + } BIT; + } TMIDH0; + char wk11[2]; + union { + unsigned short WORD; + struct { + unsigned short TMDLC:4; + unsigned short :4; + unsigned short TMPTR:8; + } BIT; + } TMPTR0; + union { + unsigned short WORD; + struct { + unsigned short TMDB1:8; + unsigned short TMDB0:8; + } BIT; + } TMDF00; + union { + unsigned short WORD; + struct { + unsigned short TMDB3:8; + unsigned short TMDB2:8; + } BIT; + } TMDF10; + union { + unsigned short WORD; + struct { + unsigned short TMDB5:8; + unsigned short TMDB4:8; + } BIT; + } TMDF20; + union { + unsigned short WORD; + struct { + unsigned short TMDB7:8; + unsigned short TMDB6:8; + } BIT; + } TMDF30; + union { + unsigned short WORD; + struct { + unsigned short TMID:16; + } BIT; + } TMIDL1; + union { + unsigned short WORD; + struct { + unsigned short TMIDE:1; + unsigned short TMRTR:1; + unsigned short THLEN:1; + unsigned short TMID:13; + } BIT; + } TMIDH1; + char wk12[2]; + union { + unsigned short WORD; + struct { + unsigned short TMDLC:4; + unsigned short :4; + unsigned short TMPTR:8; + } BIT; + } TMPTR1; + union { + unsigned short WORD; + struct { + unsigned short TMDB1:8; + unsigned short TMDB0:8; + } BIT; + } TMDF01; + union { + unsigned short WORD; + struct { + unsigned short TMDB3:8; + unsigned short TMDB2:8; + } BIT; + } TMDF11; + union { + unsigned short WORD; + struct { + unsigned short TMDB5:8; + unsigned short TMDB4:8; + } BIT; + } TMDF21; + union { + unsigned short WORD; + struct { + unsigned short TMDB7:8; + unsigned short TMDB6:8; + } BIT; + } TMDF31; + union { + unsigned short WORD; + struct { + unsigned short TMID:16; + } BIT; + } TMIDL2; + union { + unsigned short WORD; + struct { + unsigned short TMIDE:1; + unsigned short TMRTR:1; + unsigned short THLEN:1; + unsigned short TMID:13; + } BIT; + } TMIDH2; + char wk13[2]; + union { + unsigned short WORD; + struct { + unsigned short TMDLC:4; + unsigned short :4; + unsigned short TMPTR:8; + } BIT; + } TMPTR2; + union { + unsigned short WORD; + struct { + unsigned short TMDB1:8; + unsigned short TMDB0:8; + } BIT; + } TMDF02; + union { + unsigned short WORD; + struct { + unsigned short TMDB3:8; + unsigned short TMDB2:8; + } BIT; + } TMDF12; + union { + unsigned short WORD; + struct { + unsigned short TMDB5:8; + unsigned short TMDB4:8; + } BIT; + } TMDF22; + union { + unsigned short WORD; + struct { + unsigned short TMDB7:8; + unsigned short TMDB6:8; + } BIT; + } TMDF32; + union { + unsigned short WORD; + struct { + unsigned short TMID:16; + } BIT; + } TMIDL3; + union { + unsigned short WORD; + struct { + unsigned short TMIDE:1; + unsigned short TMRTR:1; + unsigned short THLEN:1; + unsigned short TMID:13; + } BIT; + } TMIDH3; + char wk14[2]; + union { + unsigned short WORD; + struct { + unsigned short TMDLC:4; + unsigned short :4; + unsigned short TMPTR:8; + } BIT; + } TMPTR3; + union { + unsigned short WORD; + struct { + unsigned short TMDB1:8; + unsigned short TMDB0:8; + } BIT; + } TMDF03; + union { + unsigned short WORD; + struct { + unsigned short TMDB3:8; + unsigned short TMDB2:8; + } BIT; + } TMDF13; + union { + unsigned short WORD; + struct { + unsigned short TMDB5:8; + unsigned short TMDB4:8; + } BIT; + } TMDF23; + union { + unsigned short WORD; + struct { + unsigned short TMDB7:8; + unsigned short TMDB6:8; + } BIT; + } TMDF33; + char wk15[64]; + union { + unsigned short WORD; + struct { + unsigned short TID:8; + unsigned short :3; + unsigned short BN:2; + unsigned short :1; + unsigned short BT:2; + } BIT; + } THLACC0; +}; + +struct st_cmpb { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB1INI:1; + unsigned char :3; + unsigned char CPB0INI:1; + } BIT; + } CPBCNT1; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB1WCP:1; + unsigned char :3; + unsigned char CPB0WCP:1; + } BIT; + } CPBCNT2; + union { + unsigned char BYTE; + struct { + unsigned char CPB1OUT:1; + unsigned char :3; + unsigned char CPB0OUT:1; + unsigned char :3; + } BIT; + } CPBFLG; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CPB1INTPL:1; + unsigned char CPB1INTEG:1; + unsigned char CPB1INTEN:1; + unsigned char :1; + unsigned char CPB0INTPL:1; + unsigned char CPB0INTEG:1; + unsigned char CPB0INTEN:1; + } BIT; + } CPBINT; + union { + unsigned char BYTE; + struct { + unsigned char CPB1F:2; + unsigned char :1; + unsigned char CPB1FEN:1; + unsigned char CPB0F:2; + unsigned char :1; + unsigned char CPB0FEN:1; + } BIT; + } CPBF; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CPBSPDMD:1; + } BIT; + } CPBMD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB1VRF:1; + unsigned char :3; + unsigned char CPB0VRF:1; + } BIT; + } CPBREF; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CPB1OP:1; + unsigned char CPB1OE:1; + unsigned char :2; + unsigned char CPB0OP:1; + unsigned char CPB0OE:1; + } BIT; + } CPBOCR; + char wk0[24]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB3INI:1; + unsigned char :3; + unsigned char CPB2INI:1; + } BIT; + } CPB1CNT1; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB3WCP:1; + unsigned char :3; + unsigned char CPB2WCP:1; + } BIT; + } CPB1CNT2; + union { + unsigned char BYTE; + struct { + unsigned char CPB3OUT:1; + unsigned char :3; + unsigned char CPB2OUT:1; + unsigned char :3; + } BIT; + } CPB1FLG; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CPB3INTPL:1; + unsigned char CPB3INTEG:1; + unsigned char CPB3INTEN:1; + unsigned char :1; + unsigned char CPB2INTPL:1; + unsigned char CPB2INTEG:1; + unsigned char CPB2INTEN:1; + } BIT; + } CPB1INT; + union { + unsigned char BYTE; + struct { + unsigned char CPB3F:2; + unsigned char :1; + unsigned char CPB3FEN:1; + unsigned char CPB2F:2; + unsigned char :1; + unsigned char CPB2FEN:1; + } BIT; + } CPB1F; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CPB1SPDMD:1; + } BIT; + } CPB1MD; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CPB3VRF:1; + unsigned char :3; + unsigned char CPB2VRF:1; + } BIT; + } CPB1REF; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CPB3OP:1; + unsigned char CPB3OE:1; + unsigned char :2; + unsigned char CPB2OP:1; + unsigned char CPB2OE:1; + } BIT; + } CPB1OCR; +}; + +struct st_cmt { + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR1:1; + unsigned short STR0:1; + } BIT; + } CMSTR0; + char wk0[14]; + union { + unsigned short WORD; + struct { + unsigned short :14; + unsigned short STR3:1; + unsigned short STR2:1; + } BIT; + } CMSTR1; +}; + +struct st_cmt0 { + union { + unsigned short WORD; + struct { + unsigned short :9; + unsigned short CMIE:1; + unsigned short :4; + unsigned short CKS:2; + } BIT; + } CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +}; + +struct st_crc { + union { + unsigned char BYTE; + struct { + unsigned char DORCLR:1; + unsigned char :4; + unsigned char LMS:1; + unsigned char GPS:2; + } BIT; + } CRCCR; + unsigned char CRCDIR; + unsigned short CRCDOR; +}; + +struct st_ctsu { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CTSUINIT:1; + unsigned char :1; + unsigned char CTSUSNZ:1; + unsigned char CTSUCAP:1; + unsigned char CTSUSTRT:1; + } BIT; + } CTSUCR0; + union { + unsigned char BYTE; + struct { + unsigned char CTSUMD:2; + unsigned char CTSUCLK:2; + unsigned char CTSUATUNE1:1; + unsigned char CTSUATUNE0:1; + unsigned char CTSUCSW:1; + unsigned char CTSUPON:1; + } BIT; + } CTSUCR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CTSUSOFF:1; + unsigned char CTSUPRMODE:2; + unsigned char CTSUPRRATIO:4; + } BIT; + } CTSUSDPRS; + union { + unsigned char BYTE; + struct { + unsigned char CTSUSST:8; + } BIT; + } CTSUSST; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CTSUMCH0:6; + } BIT; + } CTSUMCH0; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CTSUMCH1:6; + } BIT; + } CTSUMCH1; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHAC07:1; + unsigned char CTSUCHAC06:1; + unsigned char CTSUCHAC05:1; + unsigned char CTSUCHAC04:1; + unsigned char CTSUCHAC03:1; + unsigned char CTSUCHAC02:1; + unsigned char CTSUCHAC01:1; + unsigned char CTSUCHAC00:1; + } BIT; + } CTSUCHAC0; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHAC17:1; + unsigned char CTSUCHAC16:1; + unsigned char CTSUCHAC15:1; + unsigned char CTSUCHAC14:1; + unsigned char CTSUCHAC13:1; + unsigned char CTSUCHAC12:1; + unsigned char CTSUCHAC11:1; + unsigned char CTSUCHAC10:1; + } BIT; + } CTSUCHAC1; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHAC27:1; + unsigned char CTSUCHAC26:1; + unsigned char CTSUCHAC25:1; + unsigned char CTSUCHAC24:1; + unsigned char CTSUCHAC23:1; + unsigned char CTSUCHAC22:1; + unsigned char CTSUCHAC21:1; + unsigned char CTSUCHAC20:1; + } BIT; + } CTSUCHAC2; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHAC37:1; + unsigned char CTSUCHAC36:1; + unsigned char CTSUCHAC35:1; + unsigned char CTSUCHAC34:1; + unsigned char CTSUCHAC33:1; + unsigned char CTSUCHAC32:1; + unsigned char CTSUCHAC31:1; + unsigned char CTSUCHAC30:1; + } BIT; + } CTSUCHAC3; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CTSUCHAC43:1; + unsigned char CTSUCHAC42:1; + unsigned char CTSUCHAC41:1; + unsigned char CTSUCHAC40:1; + } BIT; + } CTSUCHAC4; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHTRC07:1; + unsigned char CTSUCHTRC06:1; + unsigned char CTSUCHTRC05:1; + unsigned char CTSUCHTRC04:1; + unsigned char CTSUCHTRC03:1; + unsigned char CTSUCHTRC02:1; + unsigned char CTSUCHTRC01:1; + unsigned char CTSUCHTRC00:1; + } BIT; + } CTSUCHTRC0; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHTRC17:1; + unsigned char CTSUCHTRC16:1; + unsigned char CTSUCHTRC15:1; + unsigned char CTSUCHTRC14:1; + unsigned char CTSUCHTRC13:1; + unsigned char CTSUCHTRC12:1; + unsigned char CTSUCHTRC11:1; + unsigned char CTSUCHTRC10:1; + } BIT; + } CTSUCHTRC1; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHTRC27:1; + unsigned char CTSUCHTRC26:1; + unsigned char CTSUCHTRC25:1; + unsigned char CTSUCHTRC24:1; + unsigned char CTSUCHTRC23:1; + unsigned char CTSUCHTRC22:1; + unsigned char CTSUCHTRC21:1; + unsigned char CTSUCHTRC20:1; + } BIT; + } CTSUCHTRC2; + union { + unsigned char BYTE; + struct { + unsigned char CTSUCHTRC37:1; + unsigned char CTSUCHTRC36:1; + unsigned char CTSUCHTRC35:1; + unsigned char CTSUCHTRC34:1; + unsigned char CTSUCHTRC33:1; + unsigned char CTSUCHTRC32:1; + unsigned char CTSUCHTRC31:1; + unsigned char CTSUCHTRC30:1; + } BIT; + } CTSUCHTRC3; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char CTSUCHTRC43:1; + unsigned char CTSUCHTRC42:1; + unsigned char CTSUCHTRC41:1; + unsigned char CTSUCHTRC40:1; + } BIT; + } CTSUCHTRC4; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CTSUSSCNT:2; + unsigned char :2; + unsigned char CTSUSSMOD:2; + } BIT; + } CTSUDCLKC; + union { + unsigned char BYTE; + struct { + unsigned char CTSUPS:1; + unsigned char CTSUROVF:1; + unsigned char CTSUSOVF:1; + unsigned char CTSUDTSR:1; + unsigned char :1; + unsigned char CTSUSTC:3; + } BIT; + } CTSUST; + union { + unsigned short WORD; + struct { + unsigned short :4; + unsigned short CTSUSSDIV:4; + unsigned short :8; + } BIT; + } CTSUSSC; + union { + unsigned short WORD; + struct { + unsigned short CTSUSNUM:6; + unsigned short CTSUSO:10; + } BIT; + } CTSUSO0; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short CTSUICOG:2; + unsigned short CTSUSDPA:5; + unsigned short CTSURICOA:8; + } BIT; + } CTSUSO1; + union { + unsigned short WORD; + struct { + unsigned short CTSUSC:16; + } BIT; + } CTSUSC; + union { + unsigned short WORD; + struct { + unsigned short CTSURC:16; + } BIT; + } CTSURC; + union { + unsigned short WORD; + struct { + unsigned short CTSUICOMP:1; + unsigned short :15; + } BIT; + } CTSUERRS; +}; + +struct st_da { + unsigned short DADR0; + unsigned short DADR1; + union { + unsigned char BYTE; + struct { + unsigned char DAOE1:1; + unsigned char DAOE0:1; + unsigned char :6; + } BIT; + } DACR; + union { + unsigned char BYTE; + struct { + unsigned char DPSEL:1; + unsigned char :7; + } BIT; + } DADPR; + union { + unsigned char BYTE; + struct { + unsigned char DAADST:1; + unsigned char :7; + } BIT; + } DAADSCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char REF:3; + } BIT; + } DAVREFCR; +}; + +struct st_dmac { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DMST:1; + } BIT; + } DMAST; +}; + +struct st_dmac0 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[2]; + unsigned long DMOFR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_dmac1 { + void *DMSAR; + void *DMDAR; + unsigned long DMCRA; + unsigned short DMCRB; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short MD:2; + unsigned short DTS:2; + unsigned short :2; + unsigned short SZ:2; + unsigned short :6; + unsigned short DCTG:2; + } BIT; + } DMTMD; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char DTIE:1; + unsigned char ESIE:1; + unsigned char RPTIE:1; + unsigned char SARIE:1; + unsigned char DARIE:1; + } BIT; + } DMINT; + union { + unsigned short WORD; + struct { + unsigned short SM:2; + unsigned short :1; + unsigned short SARA:5; + unsigned short DM:2; + unsigned short :1; + unsigned short DARA:5; + } BIT; + } DMAMD; + char wk2[6]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTE:1; + } BIT; + } DMCNT; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char CLRS:1; + unsigned char :3; + unsigned char SWREQ:1; + } BIT; + } DMREQ; + union { + unsigned char BYTE; + struct { + unsigned char ACT:1; + unsigned char :2; + unsigned char DTIF:1; + unsigned char :3; + unsigned char ESIF:1; + } BIT; + } DMSTS; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DISEL:1; + } BIT; + } DMCSL; +}; + +struct st_doc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char DOPCFCL:1; + unsigned char DOPCF:1; + unsigned char DOPCIE:1; + unsigned char :1; + unsigned char DCSEL:1; + unsigned char OMS:2; + } BIT; + } DOCR; + char wk0[1]; + unsigned short DODIR; + unsigned short DODSR; +}; + +struct st_dtc { + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char RRS:1; + unsigned char :4; + } BIT; + } DTCCR; + char wk0[3]; + void *DTCVBR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SHORT:1; + } BIT; + } DTCADMOD; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCST:1; + } BIT; + } DTCST; + char wk2[1]; + union { + unsigned short WORD; + struct { + unsigned short ACT:1; + unsigned short :7; + unsigned short VECN:8; + } BIT; + } DTCSTS; +}; + +struct st_elc { + union { + unsigned char BYTE; + struct { + unsigned char ELCON:1; + unsigned char :7; + } BIT; + } ELCR; + union { + unsigned char BYTE; + struct { + unsigned char ELS:8; + } BIT; + } ELSR[30]; + union { + unsigned char BYTE; + struct { + unsigned char MTU3MD:2; + unsigned char MTU2MD:2; + unsigned char MTU1MD:2; + unsigned char :2; + } BIT; + } ELOPA; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char MTU4MD:2; + } BIT; + } ELOPB; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LPTMD:2; + unsigned char CMT1MD:2; + unsigned char :2; + } BIT; + } ELOPC; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char TMR2MD:2; + unsigned char :2; + unsigned char TMR0MD:2; + } BIT; + } ELOPD; + union { + unsigned char BYTE; + struct { + unsigned char PGR7:1; + unsigned char PGR6:1; + unsigned char PGR5:1; + unsigned char PGR4:1; + unsigned char PGR3:1; + unsigned char PGR2:1; + unsigned char PGR1:1; + unsigned char PGR0:1; + } BIT; + } PGR1; + union { + unsigned char BYTE; + struct { + unsigned char PGR7:1; + unsigned char PGR6:1; + unsigned char PGR5:1; + unsigned char PGR4:1; + unsigned char PGR3:1; + unsigned char PGR2:1; + unsigned char PGR1:1; + unsigned char PGR0:1; + } BIT; + } PGR2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PGCO:3; + unsigned char :1; + unsigned char PGCOVE:1; + unsigned char PGCI:2; + } BIT; + } PGC1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PGCO:3; + unsigned char :1; + unsigned char PGCOVE:1; + unsigned char PGCI:2; + } BIT; + } PGC2; + union { + unsigned char BYTE; + struct { + unsigned char PDBF7:1; + unsigned char PDBF6:1; + unsigned char PDBF5:1; + unsigned char PDBF4:1; + unsigned char PDBF3:1; + unsigned char PDBF2:1; + unsigned char PDBF1:1; + unsigned char PDBF0:1; + } BIT; + } PDBF1; + union { + unsigned char BYTE; + struct { + unsigned char PDBF7:1; + unsigned char PDBF6:1; + unsigned char PDBF5:1; + unsigned char PDBF4:1; + unsigned char PDBF3:1; + unsigned char PDBF2:1; + unsigned char PDBF1:1; + unsigned char PDBF0:1; + } BIT; + } PDBF2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSM:2; + unsigned char PSP:2; + unsigned char PSB:3; + } BIT; + } PEL3; + union { + unsigned char BYTE; + struct { + unsigned char WI:1; + unsigned char WE:1; + unsigned char :5; + unsigned char SEG:1; + } BIT; + } ELSEGR; +}; + +struct st_flash { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DFLEN:1; + } BIT; + } DFLCTL; + char wk0[111]; + union { + unsigned char BYTE; + struct { + unsigned char FMS2:1; + unsigned char LVPE:1; + unsigned char :1; + unsigned char FMS1:1; + unsigned char RPDIS:1; + unsigned char :1; + unsigned char FMS0:1; + unsigned char :1; + } BIT; + } FPMCR; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char EXS:1; + } BIT; + } FASR; + char wk2[3]; + unsigned short FSARL; + char wk3[6]; + unsigned short FSARH; + char wk4[2]; + union { + unsigned char BYTE; + struct { + unsigned char OPST:1; + unsigned char STOP:1; + unsigned char :2; + unsigned char CMD:4; + } BIT; + } FCR; + char wk5[3]; + unsigned short FEARL; + char wk6[6]; + unsigned short FEARH; + char wk7[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char FRESET:1; + } BIT; + } FRESETR; + char wk8[7]; + union { + unsigned char BYTE; + struct { + unsigned char EXRDY:1; + unsigned char FRDY:1; + unsigned char :6; + } BIT; + } FSTATR1; + char wk9[3]; + unsigned short FWB0; + char wk10[6]; + unsigned short FWB1; + char wk11[6]; + unsigned short FWB2; + char wk12[2]; + unsigned short FWB3; + char wk13[58]; + unsigned char FPR; + char wk14[3]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PERR:1; + } BIT; + } FPSR; + char wk15[59]; + union { + unsigned short WORD; + struct { + unsigned short :7; + unsigned short SASMF:1; + unsigned short :8; + } BIT; + } FSCMR; + char wk16[6]; + unsigned short FAWSMR; + char wk17[6]; + unsigned short FAWEMR; + char wk18[6]; + union { + unsigned char BYTE; + struct { + unsigned char SAS:2; + unsigned char :1; + unsigned char PCKA:5; + } BIT; + } FISR; + char wk19[3]; + union { + unsigned char BYTE; + struct { + unsigned char OPST:1; + unsigned char :4; + unsigned char CMD:3; + } BIT; + } FEXCR; + char wk20[3]; + unsigned short FEAML; + char wk21[6]; + unsigned short FEAMH; + char wk22[6]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char EILGLERR:1; + unsigned char ILGLERR:1; + unsigned char BCERR:1; + unsigned char :1; + unsigned char PRGERR:1; + unsigned char ERERR:1; + } BIT; + } FSTATR0; + char wk23[15809]; + union { + unsigned short WORD; + struct { + unsigned short FEKEY:8; + unsigned short FENTRYD:1; + unsigned short :6; + unsigned short FENTRY0:1; + } BIT; + } FENTRYR; +}; + +struct st_flashconst { + unsigned long UIDR0; + unsigned long UIDR1; + unsigned long UIDR2; + unsigned long UIDR3; +}; + +struct st_icu { + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IR:1; + } BIT; + } IR[254]; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char DTCE:1; + } BIT; + } DTCER[253]; + char wk1[3]; + union { + unsigned char BYTE; + struct { + unsigned char IEN7:1; + unsigned char IEN6:1; + unsigned char IEN5:1; + unsigned char IEN4:1; + unsigned char IEN3:1; + unsigned char IEN2:1; + unsigned char IEN1:1; + unsigned char IEN0:1; + } BIT; + } IER[32]; + char wk2[192]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SWINT:1; + } BIT; + } SWINTR; + char wk3[15]; + union { + unsigned short WORD; + struct { + unsigned short FIEN:1; + unsigned short :7; + unsigned short FVCT:8; + } BIT; + } FIR; + char wk4[14]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IPR:4; + } BIT; + } IPR[251]; + char wk5[5]; + unsigned char DMRSR0; + char wk6[3]; + unsigned char DMRSR1; + char wk7[3]; + unsigned char DMRSR2; + char wk8[3]; + unsigned char DMRSR3; + char wk9[243]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char IRQMD:2; + unsigned char :2; + } BIT; + } IRQCR[8]; + char wk10[8]; + union { + unsigned char BYTE; + struct { + unsigned char FLTEN7:1; + unsigned char FLTEN6:1; + unsigned char FLTEN5:1; + unsigned char FLTEN4:1; + unsigned char FLTEN3:1; + unsigned char FLTEN2:1; + unsigned char FLTEN1:1; + unsigned char FLTEN0:1; + } BIT; + } IRQFLTE0; + char wk11[3]; + union { + unsigned short WORD; + struct { + unsigned short FCLKSEL7:2; + unsigned short FCLKSEL6:2; + unsigned short FCLKSEL5:2; + unsigned short FCLKSEL4:2; + unsigned short FCLKSEL3:2; + unsigned short FCLKSEL2:2; + unsigned short FCLKSEL1:2; + unsigned short FCLKSEL0:2; + } BIT; + } IRQFLTC0; + char wk12[106]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char VBATST:1; + unsigned char LVD2ST:1; + unsigned char LVD1ST:1; + unsigned char IWDTST:1; + unsigned char WDTST:1; + unsigned char OSTST:1; + unsigned char NMIST:1; + } BIT; + } NMISR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char VBATEN:1; + unsigned char LVD2EN:1; + unsigned char LVD1EN:1; + unsigned char IWDTEN:1; + unsigned char WDTEN:1; + unsigned char OSTEN:1; + unsigned char NMIEN:1; + } BIT; + } NMIER; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char VBATCLR:1; + unsigned char LVD2CLR:1; + unsigned char LVD1CLR:1; + unsigned char IWDTCLR:1; + unsigned char WDTCLR:1; + unsigned char OSTCLR:1; + unsigned char NMICLR:1; + } BIT; + } NMICLR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char NMIMD:1; + unsigned char :3; + } BIT; + } NMICR; + char wk13[12]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char NFLTEN:1; + } BIT; + } NMIFLTE; + char wk14[3]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char NFCLKSEL:2; + } BIT; + } NMIFLTC; +}; + +struct st_irda { + union { + unsigned char BYTE; + struct { + unsigned char IRE:1; + unsigned char IRCKS:3; + unsigned char IRTXINV:1; + unsigned char IRRXINV:1; + unsigned char :2; + } BIT; + } IRCR; +}; + +struct st_iwdt { + unsigned char IWDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } IWDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } IWDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + unsigned char :7; + } BIT; + } IWDTRCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char SLCSTP:1; + unsigned char :7; + } BIT; + } IWDTCSTPR; +}; + +struct st_lpt { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char LPCMRE0:1; + unsigned char :1; + unsigned char LPCNTCKSEL:1; + unsigned char :1; + unsigned char LPCNTPSSEL:3; + } BIT; + } LPTCR1; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char LPCNTSTP:1; + } BIT; + } LPTCR2; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LPCNTRST:1; + unsigned char LPCNTEN:1; + } BIT; + } LPTCR3; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short LPCNTPRD:16; + } BIT; + } LPTPRD; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short LPCMR0:16; + } BIT; + } LPCMR0; + char wk2[2]; + union { + unsigned short WORD; + struct { + unsigned short LPWKUPEN:1; + unsigned short :15; + } BIT; + } LPWUCR; +}; + +struct st_mpc { + union { + unsigned char BYTE; + struct { + unsigned char CS7E:1; + unsigned char CS6E:1; + unsigned char CS5E:1; + unsigned char CS4E:1; + unsigned char CS3E:1; + unsigned char CS2E:1; + unsigned char CS1E:1; + unsigned char CS0E:1; + } BIT; + } PFCSE; + char wk0[3]; + union { + unsigned char BYTE; + struct { + unsigned char A15E:1; + unsigned char A14E:1; + unsigned char A13E:1; + unsigned char A12E:1; + unsigned char A11E:1; + unsigned char A10E:1; + unsigned char A9E:1; + unsigned char A8E:1; + } BIT; + } PFAOE0; + union { + unsigned char BYTE; + struct { + unsigned char A23E:1; + unsigned char A22E:1; + unsigned char A21E:1; + unsigned char A20E:1; + unsigned char A19E:1; + unsigned char A18E:1; + unsigned char A17E:1; + unsigned char A16E:1; + } BIT; + } PFAOE1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char WR1BC1E:1; + unsigned char :1; + unsigned char DHE:1; + unsigned char :3; + unsigned char ADRLE:1; + } BIT; + } PFBCR0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char ALEOE:1; + unsigned char WAITS:2; + } BIT; + } PFBCR1; + char wk1[23]; + union { + unsigned char BYTE; + struct { + unsigned char B0WI:1; + unsigned char PFSWE:1; + unsigned char :6; + } BIT; + } PWPR; + char wk2[35]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P03PFS; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P05PFS; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P07PFS; + char wk5[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P12PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P13PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P14PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P15PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P16PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P17PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P20PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P21PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P22PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P23PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P24PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P25PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P26PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } P27PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P30PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P31PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P32PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P33PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } P34PFS; + char wk6[3]; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P40PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P41PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P42PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P43PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P44PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P45PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P46PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :7; + } BIT; + } P47PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P50PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P51PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P52PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P53PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P54PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P55PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } P56PFS; + char wk7[33]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PA3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PA4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PA7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PB1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PB7PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC3PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC4PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC5PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC6PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PC7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PD7PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE0PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE1PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE2PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE3PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char :2; + unsigned char PSEL:5; + } BIT; + } PE4PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE5PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE6PFS; + union { + unsigned char BYTE; + struct { + unsigned char ASEL:1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PE7PFS; + char wk8[16]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PH0PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PH1PFS; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char ISEL:1; + unsigned char :1; + unsigned char PSEL:5; + } BIT; + } PH2PFS; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PH3PFS; + char wk9[7]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PSEL:5; + } BIT; + } PJ3PFS; +}; + +struct st_mpu { + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE0; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE0; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE1; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE1; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE2; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE2; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE3; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE3; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE4; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE4; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE5; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE5; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE6; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE6; + union { + unsigned long LONG; + struct { + unsigned long RSPN:28; + unsigned long :4; + } BIT; + } RSPAGE7; + union { + unsigned long LONG; + struct { + unsigned long REPN:28; + unsigned long UAC:3; + unsigned long V:1; + } BIT; + } REPAGE7; + char wk0[192]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long MPEN:1; + } BIT; + } MPEN; + union { + unsigned long LONG; + struct { + unsigned long :28; + unsigned long UBAC:3; + unsigned long :1; + } BIT; + } MPBAC; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long CLR:1; + } BIT; + } MPECLR; + union { + unsigned long LONG; + struct { + unsigned long :29; + unsigned long DRW:1; + unsigned long DMPER:1; + unsigned long IMPER:1; + } BIT; + } MPESTS; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long DEA:32; + } BIT; + } MPDEA; + char wk2[8]; + union { + unsigned long LONG; + struct { + unsigned long SA:32; + } BIT; + } MPSA; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short S:1; + } BIT; + } MPOPS; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short INV:1; + } BIT; + } MPOPI; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long HITI:8; + unsigned long :12; + unsigned long UHACI:3; + unsigned long :1; + } BIT; + } MHITI; + union { + unsigned long LONG; + struct { + unsigned long :8; + unsigned long HITD:8; + unsigned long :12; + unsigned long UHACD:3; + unsigned long :1; + } BIT; + } MHITD; +}; + +struct st_mtu { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OE4D:1; + unsigned char OE4C:1; + unsigned char OE3D:1; + unsigned char OE4B:1; + unsigned char OE4A:1; + unsigned char OE3B:1; + } BIT; + } TOER; + char wk0[2]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BDC:1; + unsigned char N:1; + unsigned char P:1; + unsigned char FB:1; + unsigned char WF:1; + unsigned char VF:1; + unsigned char UF:1; + } BIT; + } TGCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PSYE:1; + unsigned char :2; + unsigned char TOCL:1; + unsigned char TOCS:1; + unsigned char OLSN:1; + unsigned char OLSP:1; + } BIT; + } TOCR1; + union { + unsigned char BYTE; + struct { + unsigned char BF:2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOCR2; + char wk1[4]; + unsigned short TCDR; + unsigned short TDDR; + char wk2[8]; + unsigned short TCNTS; + unsigned short TCBR; + char wk3[12]; + union { + unsigned char BYTE; + struct { + unsigned char T3AEN:1; + unsigned char T3ACOR:3; + unsigned char T4VEN:1; + unsigned char T4VCOR:3; + } BIT; + } TITCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char T3ACNT:3; + unsigned char :1; + unsigned char T4VCNT:3; + } BIT; + } TITCNT; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char BTE:2; + } BIT; + } TBTER; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TDER:1; + } BIT; + } TDER; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char OLS3N:1; + unsigned char OLS3P:1; + unsigned char OLS2N:1; + unsigned char OLS2P:1; + unsigned char OLS1N:1; + unsigned char OLS1P:1; + } BIT; + } TOLBR; + char wk6[41]; + union { + unsigned char BYTE; + struct { + unsigned char CCE:1; + unsigned char :6; + unsigned char WRE:1; + } BIT; + } TWCR; + char wk7[31]; + union { + unsigned char BYTE; + struct { + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char :3; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char :3; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; + char wk8[2]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char RWE:1; + } BIT; + } TRWER; +}; + +struct st_mtu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[111]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char BFE:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; + char wk1[16]; + unsigned short TGRE; + unsigned short TGRF; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TGIEF:1; + unsigned char TGIEE:1; + } BIT; + } TIER2; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; +}; + +struct st_mtu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[238]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + char wk3[4]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char I2BE:1; + unsigned char I2AE:1; + unsigned char I1BE:1; + unsigned char I1AE:1; + } BIT; + } TICCR; +}; + +struct st_mtu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[365]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char CCLR:2; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char :2; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_mtu3 { + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :2; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk3[7]; + unsigned short TCNT; + char wk4[6]; + unsigned short TGRA; + unsigned short TGRB; + char wk5[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk8[90]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; +}; + +struct st_mtu4 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + char wk2[2]; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + char wk3[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char TTGE2:1; + unsigned char :1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + char wk4[8]; + unsigned short TCNT; + char wk5[8]; + unsigned short TGRA; + unsigned short TGRB; + char wk6[8]; + unsigned short TGRC; + unsigned short TGRD; + char wk7[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :7; + } BIT; + } TSR; + char wk8[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TTSE:1; + unsigned char TTSB:1; + unsigned char TTSA:1; + } BIT; + } TBTM; + char wk9[6]; + union { + unsigned short WORD; + struct { + unsigned short BF:2; + unsigned short :6; + unsigned short UT4AE:1; + unsigned short DT4AE:1; + unsigned short UT4BE:1; + unsigned short DT4BE:1; + unsigned short ITA3AE:1; + unsigned short ITA4VE:1; + unsigned short ITB3AE:1; + unsigned short ITB4VE:1; + } BIT; + } TADCR; + char wk10[2]; + unsigned short TADCORA; + unsigned short TADCORB; + unsigned short TADCOBRA; + unsigned short TADCOBRB; + char wk11[72]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; +}; + +struct st_mtu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char :1; + unsigned char NFWEN:1; + unsigned char NFVEN:1; + unsigned char NFUEN:1; + } BIT; + } NFCR; + char wk1[490]; + unsigned short TCNTU; + unsigned short TGRU; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRU; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORU; + char wk3[9]; + unsigned short TCNTV; + unsigned short TGRV; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRV; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORV; + char wk5[9]; + unsigned short TCNTW; + unsigned short TGRW; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char TPSC:2; + } BIT; + } TCRW; + char wk6[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char IOC:5; + } BIT; + } TIORW; + char wk7[11]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char TGIE5U:1; + unsigned char TGIE5V:1; + unsigned char TGIE5W:1; + } BIT; + } TIER; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CSTU5:1; + unsigned char CSTV5:1; + unsigned char CSTW5:1; + } BIT; + } TSTR; + char wk9[1]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char CMPCLR5U:1; + unsigned char CMPCLR5V:1; + unsigned char CMPCLR5W:1; + } BIT; + } TCNTCMPCLR; +}; + +struct st_poe { + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char POE3F:1; + unsigned char POE2F:1; + unsigned char POE1F:1; + unsigned char POE0F:1; + unsigned char :3; + unsigned char PIE1:1; + unsigned char POE3M:2; + unsigned char POE2M:2; + unsigned char POE1M:2; + unsigned char POE0M:2; + } BIT; + } ICSR1; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char OSF1:1; + unsigned char :5; + unsigned char OCE1:1; + unsigned char OIE1:1; + unsigned char :8; + } BIT; + } OCSR1; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :3; + unsigned char POE8F:1; + unsigned char :2; + unsigned char POE8E:1; + unsigned char PIE2:1; + unsigned char :6; + unsigned char POE8M:2; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CH0HIZ:1; + unsigned char CH34HIZ:1; + } BIT; + } SPOER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char PE3ZE:1; + unsigned char PE2ZE:1; + unsigned char PE1ZE:1; + unsigned char PE0ZE:1; + } BIT; + } POECR1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char P1CZEA:1; + unsigned char P2CZEA:1; + unsigned char P3CZEA:1; + unsigned char :4; + } BIT; + } POECR2; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned char H; + unsigned char L; + } BYTE; + struct { + unsigned char :3; + unsigned char OSTSTF:1; + unsigned char :2; + unsigned char OSTSTE:1; + unsigned char :8; + unsigned char :1; + } BIT; + } ICSR3; +}; + +struct st_port { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char PSEL5:1; + unsigned char :1; + unsigned char PSEL3:1; + unsigned char :1; + unsigned char PSEL1:1; + unsigned char PSEL0:1; + } BIT; + } PSRB; + union { + unsigned char BYTE; + struct { + unsigned char PSEL7:1; + unsigned char PSEL6:1; + unsigned char :6; + } BIT; + } PSRA; +}; + +struct st_port0 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char :1; + unsigned char B5:1; + unsigned char :1; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PCR; +}; + +struct st_port1 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } PMR; + char wk3[32]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :4; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[61]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :2; + } BIT; + } DSCR; +}; + +struct st_port2 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[33]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[60]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_port3 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[34]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :3; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[59]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_port4 { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; +}; + +struct st_port5 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[36]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[57]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_porta { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[41]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[52]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portb { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[42]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[51]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portc { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[43]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[50]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portd { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk4[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_porte { + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[45]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char B6:1; + unsigned char :1; + unsigned char B4:1; + unsigned char :1; + unsigned char B2:1; + unsigned char :1; + unsigned char B0:1; + } BIT; + } ODR1; + char wk4[48]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char B7:1; + unsigned char B6:1; + unsigned char B5:1; + unsigned char B4:1; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_porth { + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PMR; + char wk3[95]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } PCR; + char wk4[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char B2:1; + unsigned char B1:1; + unsigned char B0:1; + } BIT; + } DSCR; +}; + +struct st_portj { + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PDR; + char wk0[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PODR; + char wk1[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PIDR; + char wk2[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PMR; + char wk3[49]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } ODR0; + char wk4[45]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } PCR; + char wk5[31]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char B3:1; + unsigned char :3; + } BIT; + } DSCR; +}; + +struct st_riic { + union { + unsigned char BYTE; + struct { + unsigned char ICE:1; + unsigned char IICRST:1; + unsigned char CLO:1; + unsigned char SOWP:1; + unsigned char SCLO:1; + unsigned char SDAO:1; + unsigned char SCLI:1; + unsigned char SDAI:1; + } BIT; + } ICCR1; + union { + unsigned char BYTE; + struct { + unsigned char BBSY:1; + unsigned char MST:1; + unsigned char TRS:1; + unsigned char :1; + unsigned char SP:1; + unsigned char RS:1; + unsigned char ST:1; + unsigned char :1; + } BIT; + } ICCR2; + union { + unsigned char BYTE; + struct { + unsigned char MTWP:1; + unsigned char CKS:3; + unsigned char BCWP:1; + unsigned char BC:3; + } BIT; + } ICMR1; + union { + unsigned char BYTE; + struct { + unsigned char DLCS:1; + unsigned char SDDL:3; + unsigned char :1; + unsigned char TMOH:1; + unsigned char TMOL:1; + unsigned char TMOS:1; + } BIT; + } ICMR2; + union { + unsigned char BYTE; + struct { + unsigned char SMBS:1; + unsigned char WAIT:1; + unsigned char RDRFS:1; + unsigned char ACKWP:1; + unsigned char ACKBT:1; + unsigned char ACKBR:1; + unsigned char NF:2; + } BIT; + } ICMR3; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SCLE:1; + unsigned char NFE:1; + unsigned char NACKE:1; + unsigned char SALE:1; + unsigned char NALE:1; + unsigned char MALE:1; + unsigned char TMOE:1; + } BIT; + } ICFER; + union { + unsigned char BYTE; + struct { + unsigned char HOAE:1; + unsigned char :1; + unsigned char DIDE:1; + unsigned char :1; + unsigned char GCAE:1; + unsigned char SAR2E:1; + unsigned char SAR1E:1; + unsigned char SAR0E:1; + } BIT; + } ICSER; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char TEIE:1; + unsigned char RIE:1; + unsigned char NAKIE:1; + unsigned char SPIE:1; + unsigned char STIE:1; + unsigned char ALIE:1; + unsigned char TMOIE:1; + } BIT; + } ICIER; + union { + unsigned char BYTE; + struct { + unsigned char HOA:1; + unsigned char :1; + unsigned char DID:1; + unsigned char :1; + unsigned char GCA:1; + unsigned char AAS2:1; + unsigned char AAS1:1; + unsigned char AAS0:1; + } BIT; + } ICSR1; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char TEND:1; + unsigned char RDRF:1; + unsigned char NACKF:1; + unsigned char STOP:1; + unsigned char START:1; + unsigned char AL:1; + unsigned char TMOF:1; + } BIT; + } ICSR2; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL0; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU0; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL1; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU1; + union { + unsigned char BYTE; + struct { + unsigned char SVA:7; + unsigned char SVA0:1; + } BIT; + } SARL2; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SVA:2; + unsigned char FS:1; + } BIT; + } SARU2; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRL:5; + } BIT; + } ICBRL; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char BRH:5; + } BIT; + } ICBRH; + unsigned char ICDRT; + unsigned char ICDRR; +}; + +struct st_rspi { + union { + unsigned char BYTE; + struct { + unsigned char SPRIE:1; + unsigned char SPE:1; + unsigned char SPTIE:1; + unsigned char SPEIE:1; + unsigned char MSTR:1; + unsigned char MODFEN:1; + unsigned char TXMD:1; + unsigned char SPMS:1; + } BIT; + } SPCR; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char SSL3P:1; + unsigned char SSL2P:1; + unsigned char SSL1P:1; + unsigned char SSL0P:1; + } BIT; + } SSLP; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MOIFE:1; + unsigned char MOIFV:1; + unsigned char :2; + unsigned char SPLP2:1; + unsigned char SPLP:1; + } BIT; + } SPPCR; + union { + unsigned char BYTE; + struct { + unsigned char SPRF:1; + unsigned char :1; + unsigned char SPTEF:1; + unsigned char :1; + unsigned char PERF:1; + unsigned char MODF:1; + unsigned char IDLNF:1; + unsigned char OVRF:1; + } BIT; + } SPSR; + union { + unsigned long LONG; + struct { + unsigned short H; + } WORD; + } SPDR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPSLN:3; + } BIT; + } SPSCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SPECM:3; + unsigned char :1; + unsigned char SPCP:3; + } BIT; + } SPSSR; + unsigned char SPBR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SPLW:1; + unsigned char SPRDTD:1; + unsigned char :2; + unsigned char SPFC:2; + } BIT; + } SPDCR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SCKDL:3; + } BIT; + } SPCKD; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SLNDL:3; + } BIT; + } SSLND; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SPNDL:3; + } BIT; + } SPND; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SCKASE:1; + unsigned char PTE:1; + unsigned char SPIIE:1; + unsigned char SPOE:1; + unsigned char SPPE:1; + } BIT; + } SPCR2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD0; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD1; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD2; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD3; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD4; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD5; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD6; + union { + unsigned short WORD; + struct { + unsigned short SCKDEN:1; + unsigned short SLNDEN:1; + unsigned short SPNDEN:1; + unsigned short LSBF:1; + unsigned short SPB:4; + unsigned short SSLKP:1; + unsigned short SSLA:3; + unsigned short BRDV:2; + unsigned short CPOL:1; + unsigned short CPHA:1; + } BIT; + } SPCMD7; +}; + +struct st_rtc { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char F1HZ:1; + unsigned char F2HZ:1; + unsigned char F4HZ:1; + unsigned char F8HZ:1; + unsigned char F16HZ:1; + unsigned char F32HZ:1; + unsigned char F64HZ:1; + } BIT; + } R64CNT; + char wk0[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCNT; + unsigned char BCNT0; + }; + char wk1[1]; + union { + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCNT; + unsigned char BCNT1; + }; + char wk2[1]; + union { + unsigned char BCNT2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCNT; + }; + char wk3[1]; + union { + unsigned char BCNT3; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char DAYW:3; + } BIT; + } RWKCNT; + }; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCNT; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCNT; + char wk6[1]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRCNT; + union { + unsigned char BCNT0AR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECAR; + }; + char wk7[1]; + union { + unsigned char BCNT1AR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINAR; + }; + char wk8[1]; + union { + unsigned char BCNT2AR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRAR; + }; + char wk9[1]; + union { + unsigned char BCNT3AR; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :4; + unsigned char DAYW:3; + } BIT; + } RWKAR; + }; + char wk10[1]; + union { + unsigned char BCNT0AER; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :1; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYAR; + }; + char wk11[1]; + union { + unsigned char BCNT1AER; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :2; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONAR; + }; + char wk12[1]; + union { + unsigned short BCNT2AER; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short YR10:4; + unsigned short YR1:4; + } BIT; + } RYRAR; + }; + union { + unsigned char BCNT3AER; + union { + unsigned char BYTE; + struct { + unsigned char ENB:1; + unsigned char :7; + } BIT; + } RYRAREN; + }; + char wk13[3]; + union { + unsigned char BYTE; + struct { + unsigned char PES:4; + unsigned char RTCOS:1; + unsigned char PIE:1; + unsigned char CIE:1; + unsigned char AIE:1; + } BIT; + } RCR1; + char wk14[1]; + union { + unsigned char BYTE; + struct { + unsigned char CNTMD:1; + unsigned char HR24:1; + unsigned char AADJP:1; + unsigned char AADJE:1; + unsigned char RTCOE:1; + unsigned char ADJ30:1; + unsigned char RESET:1; + unsigned char START:1; + } BIT; + } RCR2; + char wk15[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char RTCDV:3; + unsigned char RTCEN:1; + } BIT; + } RCR3; + char wk16[7]; + union { + unsigned char BYTE; + struct { + unsigned char PMADJ:2; + unsigned char ADJ:6; + } BIT; + } RADJ; + char wk17[17]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR0; + char wk18[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR1; + char wk19[1]; + union { + unsigned char BYTE; + struct { + unsigned char TCEN:1; + unsigned char :1; + unsigned char TCNF:2; + unsigned char :1; + unsigned char TCST:1; + unsigned char TCCT:2; + } BIT; + } RTCCR2; + char wk20[13]; + union { + unsigned char BCNT0CP0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP0; + }; + char wk21[1]; + union { + unsigned char BCNT1CP0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP0; + }; + char wk22[1]; + union { + unsigned char BCNT2CP0; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP0; + }; + char wk23[3]; + union { + unsigned char BCNT3CP0; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP0; + }; + char wk24[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP0; + char wk25[5]; + union { + unsigned char BCNT0CP1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP1; + }; + char wk26[1]; + union { + unsigned char BCNT1CP1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP1; + }; + char wk27[1]; + union { + unsigned char BCNT2CP1; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP1; + }; + char wk28[3]; + union { + unsigned char BCNT3CP1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP1; + }; + char wk29[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP1; + char wk30[5]; + union { + unsigned char BCNT0CP2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char SEC10:3; + unsigned char SEC1:4; + } BIT; + } RSECCP2; + }; + char wk31[1]; + union { + unsigned char BCNT1CP2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MIN10:3; + unsigned char MIN1:4; + } BIT; + } RMINCP2; + }; + char wk32[1]; + union { + unsigned char BCNT2CP2; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char PM:1; + unsigned char HR10:2; + unsigned char HR1:4; + } BIT; + } RHRCP2; + }; + char wk33[3]; + union { + unsigned char BCNT3CP2; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char DATE10:2; + unsigned char DATE1:4; + } BIT; + } RDAYCP2; + }; + char wk34[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MON10:1; + unsigned char MON1:4; + } BIT; + } RMONCP2; +}; + +struct st_s12ad { + union { + unsigned short WORD; + struct { + unsigned short ADST:1; + unsigned short ADCS:2; + unsigned short ADIE:1; + unsigned short :1; + unsigned short ADHSC:1; + unsigned short TRGE:1; + unsigned short EXTRG:1; + unsigned short DBLE:1; + unsigned short GBADIE:1; + unsigned short :1; + unsigned short DBLANS:5; + } BIT; + } ADCSR; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANSA007:1; + unsigned short ANSA006:1; + unsigned short ANSA005:1; + unsigned short ANSA004:1; + unsigned short ANSA003:1; + unsigned short ANSA002:1; + unsigned short ANSA001:1; + unsigned short ANSA000:1; + } BIT; + } ADANSA0; + union { + unsigned short WORD; + struct { + unsigned short ANSA115:1; + unsigned short ANSA114:1; + unsigned short ANSA113:1; + unsigned short ANSA112:1; + unsigned short ANSA111:1; + unsigned short ANSA110:1; + unsigned short ANSA109:1; + unsigned short ANSA108:1; + unsigned short ANSA107:1; + unsigned short ANSA106:1; + unsigned short ANSA105:1; + unsigned short ANSA104:1; + unsigned short ANSA103:1; + unsigned short ANSA102:1; + unsigned short ANSA101:1; + unsigned short ANSA100:1; + } BIT; + } ADANSA1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ADS007:1; + unsigned short ADS006:1; + unsigned short ADS005:1; + unsigned short ADS004:1; + unsigned short ADS003:1; + unsigned short ADS002:1; + unsigned short ADS001:1; + unsigned short ADS000:1; + } BIT; + } ADADS0; + union { + unsigned short WORD; + struct { + unsigned short ADS115:1; + unsigned short ADS114:1; + unsigned short ADS113:1; + unsigned short ADS112:1; + unsigned short ADS111:1; + unsigned short ADS110:1; + unsigned short ADS109:1; + unsigned short ADS108:1; + unsigned short ADS107:1; + unsigned short ADS106:1; + unsigned short ADS105:1; + unsigned short ADS104:1; + unsigned short ADS103:1; + unsigned short ADS102:1; + unsigned short ADS101:1; + unsigned short ADS100:1; + } BIT; + } ADADS1; + union { + unsigned char BYTE; + struct { + unsigned char AVEE:1; + unsigned char :4; + unsigned char ADC:3; + } BIT; + } ADADC; + char wk1[1]; + union { + unsigned short WORD; + struct { + unsigned short ADRFMT:1; + unsigned short :3; + unsigned short DIAGM:1; + unsigned short DIAGLD:1; + unsigned short DIAGVAL:2; + unsigned short :2; + unsigned short ACE:1; + unsigned short :5; + } BIT; + } ADCER; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short TRSA:6; + unsigned short :2; + unsigned short TRSB:6; + } BIT; + } ADSTRGR; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short OCSA:1; + unsigned short TSSA:1; + unsigned short :6; + unsigned short OCSAD:1; + unsigned short TSSAD:1; + } BIT; + } ADEXICR; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short ANSB007:1; + unsigned short ANSB006:1; + unsigned short ANSB005:1; + unsigned short ANSB004:1; + unsigned short ANSB003:1; + unsigned short ANSB002:1; + unsigned short ANSB001:1; + unsigned short ANSB000:1; + } BIT; + } ADANSB0; + union { + unsigned short WORD; + struct { + unsigned short ANSB115:1; + unsigned short ANSB114:1; + unsigned short ANSB113:1; + unsigned short ANSB112:1; + unsigned short ANSB111:1; + unsigned short ANSB110:1; + unsigned short ANSB109:1; + unsigned short ANSB108:1; + unsigned short ANSB107:1; + unsigned short ANSB106:1; + unsigned short ANSB105:1; + unsigned short ANSB104:1; + unsigned short ANSB103:1; + unsigned short ANSB102:1; + unsigned short ANSB101:1; + unsigned short ANSB100:1; + } BIT; + } ADANSB1; + unsigned short ADDBLDR; + unsigned short ADTSDR; + unsigned short ADOCDR; + union { + unsigned short WORD; + union { + struct { + unsigned short DIAGST:2; + unsigned short :2; + unsigned short AD:12; + } RIGHT; + struct { + unsigned short AD:12; + unsigned short :2; + unsigned short DIAGST:2; + } LEFT; + } BIT; + } ADRD; + unsigned short ADDR0; + unsigned short ADDR1; + unsigned short ADDR2; + unsigned short ADDR3; + unsigned short ADDR4; + unsigned short ADDR5; + unsigned short ADDR6; + unsigned short ADDR7; + char wk2[16]; + unsigned short ADDR16; + unsigned short ADDR17; + unsigned short ADDR18; + unsigned short ADDR19; + unsigned short ADDR20; + unsigned short ADDR21; + unsigned short ADDR22; + unsigned short ADDR23; + unsigned short ADDR24; + unsigned short ADDR25; + unsigned short ADDR26; + unsigned short ADDR27; + unsigned short ADDR28; + unsigned short ADDR29; + unsigned short ADDR30; + unsigned short ADDR31; + char wk4[26]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ADNDIS:5; + } BIT; + } ADDISCR; + char wk5[2]; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char ELCC:2; + } BIT; + } ADELCCR; + char wk6[2]; + union { + unsigned short WORD; + struct { + unsigned short GBRP:1; + unsigned short :13; + unsigned short GBRSCN:1; + unsigned short PGS:1; + } BIT; + } ADGSPCR; + char wk7[8]; + union { + unsigned char BYTE; + struct { + unsigned char ADSLP:1; + unsigned char :2; + unsigned char LVSEL:1; + unsigned char :2; + unsigned char HVSEL:2; + } BIT; + } ADHVREFCNT; + char wk8[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char MONCMPB:1; + unsigned char MONCMPA:1; + unsigned char :3; + unsigned char MONCOMB:1; + } BIT; + } ADWINMON; + char wk9[3]; + union { + unsigned short WORD; + struct { + unsigned short :1; + unsigned short WCMPE:1; + unsigned short :2; + unsigned short CMPAE:1; + unsigned short :1; + unsigned short CMPBE:1; + unsigned short :7; + unsigned short CMPAB:2; + } BIT; + } ADCMPCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPOCA:1; + unsigned char CMPTSA:1; + } BIT; + } ADCMPANSER; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPLOCA:1; + unsigned char CMPLTSA:1; + } BIT; + } ADCMPLER; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPCHA007:1; + unsigned short CMPCHA006:1; + unsigned short CMPCHA005:1; + unsigned short CMPCHA004:1; + unsigned short CMPCHA003:1; + unsigned short CMPCHA002:1; + unsigned short CMPCHA001:1; + unsigned short CMPCHA000:1; + } BIT; + } ADCMPANSR0; + union { + unsigned short WORD; + struct { + unsigned short CMPCHA115:1; + unsigned short CMPCHA114:1; + unsigned short CMPCHA113:1; + unsigned short CMPCHA112:1; + unsigned short CMPCHA111:1; + unsigned short CMPCHA110:1; + unsigned short CMPCHA109:1; + unsigned short CMPCHA108:1; + unsigned short CMPCHA107:1; + unsigned short CMPCHA106:1; + unsigned short CMPCHA105:1; + unsigned short CMPCHA104:1; + unsigned short CMPCHA103:1; + unsigned short CMPCHA102:1; + unsigned short CMPCHA101:1; + unsigned short CMPCHA100:1; + } BIT; + } ADCMPANSR1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPLCHA007:1; + unsigned short CMPLCHA006:1; + unsigned short CMPLCHA005:1; + unsigned short CMPLCHA004:1; + unsigned short CMPLCHA003:1; + unsigned short CMPLCHA002:1; + unsigned short CMPLCHA001:1; + unsigned short CMPLCHA000:1; + } BIT; + } ADCMPLR0; + union { + unsigned short WORD; + struct { + unsigned short CMPLCHA115:1; + unsigned short CMPLCHA114:1; + unsigned short CMPLCHA113:1; + unsigned short CMPLCHA112:1; + unsigned short CMPLCHA111:1; + unsigned short CMPLCHA110:1; + unsigned short CMPLCHA109:1; + unsigned short CMPLCHA108:1; + unsigned short CMPLCHA107:1; + unsigned short CMPLCHA106:1; + unsigned short CMPLCHA105:1; + unsigned short CMPLCHA104:1; + unsigned short CMPLCHA103:1; + unsigned short CMPLCHA102:1; + unsigned short CMPLCHA101:1; + unsigned short CMPLCHA100:1; + } BIT; + } ADCMPLR1; + unsigned short ADCMPDR0; + unsigned short ADCMPDR1; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short CMPSTCHA007:1; + unsigned short CMPSTCHA006:1; + unsigned short CMPSTCHA005:1; + unsigned short CMPSTCHA004:1; + unsigned short CMPSTCHA003:1; + unsigned short CMPSTCHA002:1; + unsigned short CMPSTCHA001:1; + unsigned short CMPSTCHA000:1; + } BIT; + } ADCMPSR0; + union { + unsigned short WORD; + struct { + unsigned short CMPSTCHA115:1; + unsigned short CMPSTCHA114:1; + unsigned short CMPSTCHA113:1; + unsigned short CMPSTCHA112:1; + unsigned short CMPSTCHA111:1; + unsigned short CMPSTCHA110:1; + unsigned short CMPSTCHA109:1; + unsigned short CMPSTCHA108:1; + unsigned short CMPSTCHA107:1; + unsigned short CMPSTCHA106:1; + unsigned short CMPSTCHA105:1; + unsigned short CMPSTCHA104:1; + unsigned short CMPSTCHA103:1; + unsigned short CMPSTCHA102:1; + unsigned short CMPSTCHA101:1; + unsigned short CMPSTCHA100:1; + } BIT; + } ADCMPSR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char CMPSTOCA:1; + unsigned char CMPSTTSA:1; + } BIT; + } ADCMPSER; + char wk10[1]; + union { + unsigned char BYTE; + struct { + unsigned char CMPLB:1; + unsigned char :1; + unsigned char CMPCHB:6; + } BIT; + } ADCMPBNSR; + char wk11[1]; + unsigned short ADWINLLB; + unsigned short ADWINULB; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CMPSTB:1; + } BIT; + } ADCMPBSR; + char wk12[3]; + unsigned short ADBUF0; + unsigned short ADBUF1; + unsigned short ADBUF2; + unsigned short ADBUF3; + unsigned short ADBUF4; + unsigned short ADBUF5; + unsigned short ADBUF6; + unsigned short ADBUF7; + unsigned short ADBUF8; + unsigned short ADBUF9; + unsigned short ADBUF10; + unsigned short ADBUF11; + unsigned short ADBUF12; + unsigned short ADBUF13; + unsigned short ADBUF14; + unsigned short ADBUF15; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BUFEN:1; + } BIT; + } ADBUFEN; + char wk13[1]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char PTROVF:1; + unsigned char BUFPTR:4; + } BIT; + } ADBUFPTR; + char wk14[10]; + unsigned char ADSSTRL; + unsigned char ADSSTRT; + unsigned char ADSSTRO; + unsigned char ADSSTR0; + unsigned char ADSSTR1; + unsigned char ADSSTR2; + unsigned char ADSSTR3; + unsigned char ADSSTR4; + unsigned char ADSSTR5; + unsigned char ADSSTR6; + unsigned char ADSSTR7; +}; + +struct st_sci0 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_sci12 { + union { + unsigned char BYTE; + struct { + unsigned char CM:1; + unsigned char CHR:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char STOP:1; + unsigned char MP:1; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char FER:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + union { + unsigned char BYTE; + struct { + unsigned char RXDESEL:1; + unsigned char BGDM:1; + unsigned char NFEN:1; + unsigned char ABCS:1; + unsigned char :1; + unsigned char BRME:1; + unsigned char :1; + unsigned char ACS0:1; + } BIT; + } SEMR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char NFCS:3; + } BIT; + } SNFR; + union { + unsigned char BYTE; + struct { + unsigned char IICDL:5; + unsigned char :2; + unsigned char IICM:1; + } BIT; + } SIMR1; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char IICACKT:1; + unsigned char :3; + unsigned char IICCSC:1; + unsigned char IICINTM:1; + } BIT; + } SIMR2; + union { + unsigned char BYTE; + struct { + unsigned char IICSCLS:2; + unsigned char IICSDAS:2; + unsigned char IICSTIF:1; + unsigned char IICSTPREQ:1; + unsigned char IICRSTAREQ:1; + unsigned char IICSTAREQ:1; + } BIT; + } SIMR3; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char IICACKR:1; + } BIT; + } SISR; + union { + unsigned char BYTE; + struct { + unsigned char CKPH:1; + unsigned char CKPOL:1; + unsigned char :1; + unsigned char MFF:1; + unsigned char :1; + unsigned char MSS:1; + unsigned char CTSE:1; + unsigned char SSE:1; + } BIT; + } SPMR; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; + char wk0[13]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ESME:1; + } BIT; + } ESMER; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char BRME:1; + unsigned char RXDSF:1; + unsigned char SFSF:1; + unsigned char :1; + } BIT; + } CR0; + union { + unsigned char BYTE; + struct { + unsigned char PIBS:3; + unsigned char PIBE:1; + unsigned char CF1DS:2; + unsigned char CF0RE:1; + unsigned char BFE:1; + } BIT; + } CR1; + union { + unsigned char BYTE; + struct { + unsigned char RTS:2; + unsigned char BCCS:2; + unsigned char :1; + unsigned char DFCS:3; + } BIT; + } CR2; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SDST:1; + } BIT; + } CR3; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SHARPS:1; + unsigned char :2; + unsigned char RXDXPS:1; + unsigned char TXDXPS:1; + } BIT; + } PCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDIE:1; + unsigned char BCDIE:1; + unsigned char PIBDIE:1; + unsigned char CF1MIE:1; + unsigned char CF0MIE:1; + unsigned char BFDIE:1; + } BIT; + } ICR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDF:1; + unsigned char BCDF:1; + unsigned char PIBDF:1; + unsigned char CF1MF:1; + unsigned char CF0MF:1; + unsigned char BFDF:1; + } BIT; + } STR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char AEDCL:1; + unsigned char BCDCL:1; + unsigned char PIBDCL:1; + unsigned char CF1MCL:1; + unsigned char CF0MCL:1; + unsigned char BFDCL:1; + } BIT; + } STCR; + unsigned char CF0DR; + union { + unsigned char BYTE; + struct { + unsigned char CF0CE7:1; + unsigned char CF0CE6:1; + unsigned char CF0CE5:1; + unsigned char CF0CE4:1; + unsigned char CF0CE3:1; + unsigned char CF0CE2:1; + unsigned char CF0CE1:1; + unsigned char CF0CE0:1; + } BIT; + } CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union { + unsigned char BYTE; + struct { + unsigned char CF1CE7:1; + unsigned char CF1CE6:1; + unsigned char CF1CE5:1; + unsigned char CF1CE4:1; + unsigned char CF1CE3:1; + unsigned char CF1CE2:1; + unsigned char CF1CE1:1; + unsigned char CF1CE0:1; + } BIT; + } CF1CR; + unsigned char CF1RR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCST:1; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char TCSS:3; + unsigned char TWRC:1; + unsigned char :1; + unsigned char TOMS:2; + } BIT; + } TMR; + unsigned char TPRE; + unsigned char TCNT; +}; + +struct st_sdhi { + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long CMD12AT:2; +// unsigned long TRSTP:1; +// unsigned long CMDRW:1; +// unsigned long CMDTP:1; +// unsigned long RSPTP:3; +// unsigned long ACMD:2; +// unsigned long CMDIDX:6; +// } BIT; + } SDCMD; + char wk0[4]; + unsigned long SDARG; + char wk1[4]; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long SDBLKCNTEN:1; + unsigned long :7; + unsigned long STP:1; + } BIT; + } SDSTOP; + unsigned long SDBLKCNT; + unsigned long SDRSP10; + char wk2[4]; + unsigned long SDRSP32; + char wk3[4]; + unsigned long SDRSP54; + char wk4[4]; + unsigned long SDRSP76; + char wk5[4]; + union { + unsigned long LONG; +// struct { +// unsigned long :21; +// unsigned long SDD3MON:1; +// unsigned long SDD3IN:1; +// unsigned long SDD3RM:1; +// unsigned long SDWPMON:1; +// unsigned long :1; +// unsigned long SDCDMON:1; +// unsigned long SDCDIN:1; +// unsigned long SDCDRM:1; +// unsigned long ACEND:1; +// unsigned long :1; +// unsigned long RSPEND:1; +// } BIT; + } SDSTS1; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long ILA:1; +// unsigned long CBSY:1; +// unsigned long SDCLKCREN:1; +// unsigned long :3; +// unsigned long BWE:1; +// unsigned long BRE:1; +// unsigned long SDD0MON:1; +// unsigned long RSPTO:1; +// unsigned long ILR:1; +// unsigned long ILW:1; +// unsigned long DTO:1; +// unsigned long ENDE:1; +// unsigned long CRCE:1; +// unsigned long CMDE:1; +// } BIT; + } SDSTS2; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long SDD3INM:1; + unsigned long SDD3RMM:1; + unsigned long :3; + unsigned long SDCDINM:1; + unsigned long SDCDRMM:1; + unsigned long ACENDM:1; + unsigned long :1; + unsigned long RSPENDM:1; + } BIT; + } SDIMSK1; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long ILAM:1; + unsigned long :5; + unsigned long BWEM:1; + unsigned long BREM:1; + unsigned long :1; + unsigned long RSPTOM:1; + unsigned long ILRM:1; + unsigned long ILWM:1; + unsigned long DTTOM:1; + unsigned long ENDEM:1; + unsigned long CRCEM:1; + unsigned long CMDEM:1; + } BIT; + } SDIMSK2; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long CLKCTRLEN:1; + unsigned long CLKEN:1; + unsigned long CLKSEL:8; + } BIT; + } SDCLKCR; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long LEN:10; + } BIT; + } SDSIZE; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long WIDTH:1; + unsigned long :7; + unsigned long TOP:4; + unsigned long CTOP:4; + } BIT; + } SDOPT; + char wk6[4]; + union { + unsigned long LONG; + struct { + unsigned long :17; + unsigned long CRCTK:3; + unsigned long CRCTKE:1; + unsigned long RDCRCE:1; + unsigned long RSPCRCE1:1; + unsigned long RSPCRCE0:1; + unsigned long :2; + unsigned long CRCLENE:1; + unsigned long RDLENE:1; + unsigned long RSPLENE1:1; + unsigned long RSPLENE0:1; + unsigned long CMDE1:1; + unsigned long CMDE0:1; + } BIT; + } SDERSTS1; + union { + unsigned long LONG; + struct { + unsigned long :25; + unsigned long CRCBSYTO:1; + unsigned long CRCTO:1; + unsigned long RDTO:1; + unsigned long BSYTO1:1; + unsigned long BSYTO0:1; + unsigned long RSPTO1:1; + unsigned long RSPTO0:1; + } BIT; + } SDERSTS2; + unsigned long SDBUFR; + char wk7[4]; + union { + unsigned long LONG; + struct { + unsigned long :22; + unsigned long C52PUB:1; + unsigned long IOABT:1; + unsigned long :5; + unsigned long RWREQ:1; + unsigned long :1; + unsigned long INTEN:1; + } BIT; + } SDIOMD; + union { + unsigned long LONG; +// struct { +// unsigned long :16; +// unsigned long EXWT:1; +// unsigned long EXPUB52:1; +// unsigned long :13; +// unsigned long IOIRQ:1; +// } BIT; + } SDIOSTS; + union { + unsigned long LONG; + struct { + unsigned long :16; + unsigned long EXWTM:1; + unsigned long EXPUB52M:1; + unsigned long :13; + unsigned long IOIRQM:1; + } BIT; + } SDIOIMSK; + char wk8[316]; + union { + unsigned long LONG; + struct { + unsigned long :30; + unsigned long DMAEN:1; + unsigned long :1; + } BIT; + } SDDMAEN; + char wk9[12]; + union { + unsigned long LONG; + struct { + unsigned long :31; + unsigned long SDRST:1; + } BIT; + } SDRST; + char wk10[28]; + union { + unsigned long LONG; + struct { + unsigned long :24; + unsigned long BRSWP:1; + unsigned long BWSWP:1; + unsigned long :6; + } BIT; + } SDSWAP; +}; + +struct st_smci { + union { + unsigned char BYTE; + struct { + unsigned char GM:1; + unsigned char BLK:1; + unsigned char PE:1; + unsigned char PM:1; + unsigned char BCP:2; + unsigned char CKS:2; + } BIT; + } SMR; + unsigned char BRR; + union { + unsigned char BYTE; + struct { + unsigned char TIE:1; + unsigned char RIE:1; + unsigned char TE:1; + unsigned char RE:1; + unsigned char MPIE:1; + unsigned char TEIE:1; + unsigned char CKE:2; + } BIT; + } SCR; + unsigned char TDR; + union { + unsigned char BYTE; + struct { + unsigned char TDRE:1; + unsigned char RDRF:1; + unsigned char ORER:1; + unsigned char ERS:1; + unsigned char PER:1; + unsigned char TEND:1; + unsigned char MPB:1; + unsigned char MPBT:1; + } BIT; + } SSR; + unsigned char RDR; + union { + unsigned char BYTE; + struct { + unsigned char BCP2:1; + unsigned char :2; + unsigned char CHR1:1; + unsigned char SDIR:1; + unsigned char SINV:1; + unsigned char :1; + unsigned char SMIF:1; + } BIT; + } SCMR; + char wk0[7]; + union { + unsigned short WORD; + struct { + unsigned char TDRH; + unsigned char TDRL; + } BYTE; + } TDRHL; + union { + unsigned short WORD; + struct { + unsigned char RDRH; + unsigned char RDRL; + } BYTE; + } RDRHL; + unsigned char MDDR; +}; + +struct st_ssi { + union { + unsigned long LONG; + struct { + unsigned long :1; + unsigned long CKS:1; + unsigned long TUIEN:1; + unsigned long TOIEN:1; + unsigned long RUIEN:1; + unsigned long ROIEN:1; + unsigned long IIEN:1; + unsigned long :1; + unsigned long CHNL:2; + unsigned long DWL:3; + unsigned long SWL:3; + unsigned long SCKD:1; + unsigned long SWSD:1; + unsigned long SCKP:1; + unsigned long SWSP:1; + unsigned long SPDP:1; + unsigned long SDTA:1; + unsigned long PDTA:1; + unsigned long DEL:1; + unsigned long CKDV:4; + unsigned long MUEN:1; + unsigned long :1; + unsigned long TEN:1; + unsigned long REN:1; + } BIT; + } SSICR; + union { + unsigned long LONG; + struct { + unsigned long :2; + unsigned long TUIRQ:1; + unsigned long TOIRQ:1; + unsigned long RUIRQ:1; + unsigned long ROIRQ:1; + unsigned long IIRQ:1; + unsigned long :18; + unsigned long TCHNO:2; + unsigned long TSWNO:1; + unsigned long RCHNO:2; + unsigned long RSWNO:1; + unsigned long IDST:1; + } BIT; + } SSISR; + char wk0[8]; + union { + unsigned long LONG; + struct { + unsigned long AUCKE:1; + unsigned long :14; + unsigned long SSIRST:1; + unsigned long :8; + unsigned long TTRG:2; + unsigned long RTRG:2; + unsigned long TIE:1; + unsigned long RIE:1; + unsigned long TFRST:1; + unsigned long RFRST:1; + } BIT; + } SSIFCR; + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long TDC:4; + unsigned long :7; + unsigned long TDE:1; + unsigned long :4; + unsigned long RDC:4; + unsigned long :7; + unsigned long RDF:1; + } BIT; + } SSIFSR; + unsigned long SSIFTDR; + unsigned long SSIFRDR; + union { + unsigned long LONG; + struct { + unsigned long :23; + unsigned long CONT:1; + unsigned long :8; + } BIT; + } SSITDMR; +}; + +struct st_system { + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short MD:1; + } BIT; + } MDMONR; + char wk0[4]; + union { + unsigned short WORD; + struct { + unsigned short KEY:8; + unsigned short :6; + unsigned short EXBE:1; + unsigned short ROME:1; + } BIT; + } SYSCR0; + union { + unsigned short WORD; + struct { + unsigned short :15; + unsigned short RAME:1; + } BIT; + } SYSCR1; + char wk1[2]; + union { + unsigned short WORD; + struct { + unsigned short SSBY:1; + unsigned short OPE:1; + unsigned short :14; + } BIT; + } SBYCR; + char wk2[2]; + union { + unsigned long LONG; + struct { + unsigned long :3; + unsigned long MSTPA28:1; + unsigned long :8; + unsigned long MSTPA19:1; + unsigned long :1; + unsigned long MSTPA17:1; + unsigned long :1; + unsigned long MSTPA15:1; + unsigned long MSTPA14:1; + unsigned long MSTPA13:1; + unsigned long :3; + unsigned long MSTPA9:1; + unsigned long :3; + unsigned long MSTPA5:1; + unsigned long MSTPA4:1; + unsigned long :4; + } BIT; + } MSTPCRA; + union { + unsigned long LONG; + struct { + unsigned long MSTPB31:1; + unsigned long MSTPB30:1; + unsigned long :3; + unsigned long MSTPB26:1; + unsigned long MSTPB25:1; + unsigned long :1; + unsigned long MSTPB23:1; + unsigned long :1; + unsigned long MSTPB21:1; + unsigned long :1; + unsigned long MSTPB19:1; + unsigned long :1; + unsigned long MSTPB17:1; + unsigned long :6; + unsigned long MSTPB10:1; + unsigned long MSTPB9:1; + unsigned long :2; + unsigned long MSTPB6:1; + unsigned long :1; + unsigned long MSTPB4:1; + unsigned long :3; + unsigned long MSTPB0:1; + } BIT; + } MSTPCRB; + union { + unsigned long LONG; + struct { + unsigned long DSLPE:1; + unsigned long MSTPC30:1; + unsigned long MSTPC29:1; + unsigned long MSTPC28:1; + unsigned long MSTPC27:1; + unsigned long MSTPC26:1; + unsigned long :5; + unsigned long MSTPC20:1; + unsigned long MSTPC19:1; + unsigned long :17; + unsigned long MSTPC1:1; + unsigned long MSTPC0:1; + } BIT; + } MSTPCRC; + union { + unsigned long LONG; + struct { + unsigned long MSTPD31:1; + unsigned long :11; + unsigned long MSTPD19:1; + unsigned long :3; + unsigned long MSTPD15:1; + unsigned long :4; + unsigned long MSTPD10:1; + unsigned long :10; + } BIT; + } MSTPCRD; + union { + unsigned long LONG; + struct { + unsigned long FCK:4; + unsigned long ICK:4; + unsigned long PSTOP1:1; + unsigned long :3; + unsigned long BCK:4; + unsigned long PCKA:4; + unsigned long PCKB:4; + unsigned long :4; + unsigned long PCKD:4; + } BIT; + } SCKCR; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned short :5; + unsigned short CKSEL:3; + unsigned short :8; + } BIT; + } SCKCR3; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short STC:6; + unsigned short :6; + unsigned short PLIDIV:2; + } BIT; + } PLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char PLLEN:1; + } BIT; + } PLLCR2; + char wk4[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short USTC:6; + unsigned short :3; + unsigned short UCKUPLLSEL:1; + unsigned short :2; + unsigned short UPLIDIV:2; + } BIT; + } UPLLCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char UPLLEN:1; + } BIT; + } UPLLCR2; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char BCLKDIV:1; + } BIT; + } BCKCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MEMWAIT:1; + } BIT; + } MEMWAIT; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char MOSTP:1; + } BIT; + } MOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char SOSTP:1; + } BIT; + } SOSCCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char LCSTP:1; + } BIT; + } LOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char ILCSTP:1; + } BIT; + } ILOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char HCSTP:1; + } BIT; + } HOCOCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char HCFRQ:2; + } BIT; + } HOCOCR2; + char wk6[4]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char UPLOVF:1; + unsigned char :1; + unsigned char HCOVF:1; + unsigned char PLOVF:1; + unsigned char :1; + unsigned char MOOVF:1; + } BIT; + } OSCOVFSR; + char wk7[1]; + union { + unsigned short WORD; + struct { + unsigned short CKOSTP:1; + unsigned short CKODIV:3; + unsigned short CKOSEL:4; + unsigned short :8; + } BIT; + } CKOCR; + union { + unsigned char BYTE; + struct { + unsigned char OSTDE:1; + unsigned char :6; + unsigned char OSTDIE:1; + } BIT; + } OSTDCR; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char OSTDF:1; + } BIT; + } OSTDSR; + char wk8[30]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char LOCOTRD:5; + } BIT; + } LOCOTRR; + char wk9[3]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char ILOCOTRD:5; + } BIT; + } ILOCOTRR; + char wk10[3]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char HOCOTRD:6; + } BIT; + } HOCOTRR0; + char wk11[2]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char HOCOTRD:6; + } BIT; + } HOCOTRR3; + char wk12[52]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char OPCMTSF:1; + unsigned char :1; + unsigned char OPCM:3; + } BIT; + } OPCCR; + union { + unsigned char BYTE; + struct { + unsigned char RSTCKEN:1; + unsigned char :4; + unsigned char RSTCKSEL:3; + } BIT; + } RSTCKCR; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char MSTS:5; + } BIT; + } MOSCWTCR; + char wk13[7]; + union { + unsigned char BYTE; + struct { + unsigned char :3; + unsigned char SOPCMTSF:1; + unsigned char :3; + unsigned char SOPCM:1; + } BIT; + } SOPCCR; + char wk14[21]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char SWRF:1; + unsigned char WDTRF:1; + unsigned char IWDTRF:1; + } BIT; + } RSTSR2; + char wk15[1]; + unsigned short SWRR; + char wk16[28]; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD1IRQSEL:1; + unsigned char LVD1IDTSEL:2; + } BIT; + } LVD1CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD1MON:1; + unsigned char LVD1DET:1; + } BIT; + } LVD1SR; + union { + unsigned char BYTE; + struct { + unsigned char :5; + unsigned char LVD2IRQSEL:1; + unsigned char LVD2IDTSEL:2; + } BIT; + } LVD2CR1; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char LVD2MON:1; + unsigned char LVD2DET:1; + } BIT; + } LVD2SR; + char wk17[794]; + union { + unsigned short WORD; + struct { + unsigned short PRKEY:8; + unsigned short :4; + unsigned short PRC3:1; + unsigned short PRC2:1; + unsigned short PRC1:1; + unsigned short PRC0:1; + } BIT; + } PRCR; + char wk18[48784]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char LVD2RF:1; + unsigned char LVD1RF:1; + unsigned char LVD0RF:1; + unsigned char PORF:1; + } BIT; + } RSTSR0; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char CWSF:1; + } BIT; + } RSTSR1; + char wk19[1]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char MOSEL:1; + unsigned char MODRV21:1; + unsigned char :5; + } BIT; + } MOFCR; + char wk20[3]; + union { + unsigned char BYTE; + struct { + unsigned char :1; + unsigned char LVD2E:1; + unsigned char LVD1E:1; + unsigned char :1; + unsigned char EXVCCINP2:1; + unsigned char :3; + } BIT; + } LVCMPCR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char LVD2LVL:2; + unsigned char LVD1LVL:4; + } BIT; + } LVDLVLR; + char wk21[1]; + union { + unsigned char BYTE; + struct { + unsigned char LVD1RN:1; + unsigned char LVD1RI:1; + unsigned char :3; + unsigned char LVD1CMPE:1; + unsigned char :1; + unsigned char LVD1RIE:1; + } BIT; + } LVD1CR0; + union { + unsigned char BYTE; + struct { + unsigned char LVD2RN:1; + unsigned char LVD2RI:1; + unsigned char :3; + unsigned char LVD2CMPE:1; + unsigned char :1; + unsigned char LVD2RIE:1; + } BIT; + } LVD2CR0; + char wk22[1]; + union { + unsigned char BYTE; + struct { + unsigned char VBTLVDLVL:2; + unsigned char :1; + unsigned char VBTLVDEN:1; + unsigned char :3; + unsigned char VBATTDIS:1; + } BIT; + } VBATTCR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char VBTLVDMON:1; + unsigned char VBATRLVDETF:1; + } BIT; + } VBATTSR; + union { + unsigned char BYTE; + struct { + unsigned char :6; + unsigned char VBTLVDISEL:1; + unsigned char VBTLVDIE:1; + } BIT; + } VBTLVDICR; +}; + +struct st_tempsconst { + union { + unsigned long LONG; + struct { + unsigned long :4; + unsigned long TSCD:12; + unsigned long :16; + } BIT; + } TSCDR; +}; + +struct st_tmr0 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; + char wk5[1]; + union { + unsigned char BYTE; + struct { + unsigned char :7; + unsigned char TCS:1; + } BIT; + } TCSTR; +}; + +struct st_tmr1 { + union { + unsigned char BYTE; + struct { + unsigned char CMIEB:1; + unsigned char CMIEA:1; + unsigned char OVIE:1; + unsigned char CCLR:2; + unsigned char :3; + } BIT; + } TCR; + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :4; + unsigned char OSB:2; + unsigned char OSA:2; + } BIT; + } TCSR; + char wk1[1]; + unsigned char TCORA; + char wk2[1]; + unsigned char TCORB; + char wk3[1]; + unsigned char TCNT; + char wk4[1]; + union { + unsigned char BYTE; + struct { + unsigned char TMRIS:1; + unsigned char :2; + unsigned char CSS:2; + unsigned char CKS:3; + } BIT; + } TCCR; +}; + +struct st_tmr01 { + unsigned short TCORA; + unsigned short TCORB; + unsigned short TCNT; + unsigned short TCCR; +}; + +struct st_tpu { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char CST5:1; + unsigned char CST4:1; + unsigned char CST3:1; + unsigned char CST2:1; + unsigned char CST1:1; + unsigned char CST0:1; + } BIT; + } TSTR; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char SYNC5:1; + unsigned char SYNC4:1; + unsigned char SYNC3:1; + unsigned char SYNC2:1; + unsigned char SYNC1:1; + unsigned char SYNC0:1; + } BIT; + } TSYR; +}; + +struct st_tpu0 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[7]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu1 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[22]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu2 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[37]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu3 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[52]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIORH; + union { + unsigned char BYTE; + struct { + unsigned char IOD:4; + unsigned char IOC:4; + } BIT; + } TIORL; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; + unsigned short TGRC; + unsigned short TGRD; +}; + +struct st_tpu4 { + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk0[67]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk1[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_tpu5 { + char wk0[1]; + union { + unsigned char BYTE; + struct { + unsigned char :2; + unsigned char NFCS:2; + unsigned char NFDEN:1; + unsigned char NFCEN:1; + unsigned char NFBEN:1; + unsigned char NFAEN:1; + } BIT; + } NFCR; + char wk1[82]; + union { + unsigned char BYTE; + struct { + unsigned char CCLR:3; + unsigned char CKEG:2; + unsigned char TPSC:3; + } BIT; + } TCR; + union { + unsigned char BYTE; + struct { + unsigned char ICSELD:1; + unsigned char ICSELB:1; + unsigned char BFB:1; + unsigned char BFA:1; + unsigned char MD:4; + } BIT; + } TMDR; + union { + unsigned char BYTE; + struct { + unsigned char IOB:4; + unsigned char IOA:4; + } BIT; + } TIOR; + char wk2[1]; + union { + unsigned char BYTE; + struct { + unsigned char TTGE:1; + unsigned char :1; + unsigned char TCIEU:1; + unsigned char TCIEV:1; + unsigned char TGIED:1; + unsigned char TGIEC:1; + unsigned char TGIEB:1; + unsigned char TGIEA:1; + } BIT; + } TIER; + union { + unsigned char BYTE; + struct { + unsigned char TCFD:1; + unsigned char :1; + unsigned char TCFU:1; + unsigned char TCFV:1; + unsigned char TGFD:1; + unsigned char TGFC:1; + unsigned char TGFB:1; + unsigned char TGFA:1; + } BIT; + } TSR; + unsigned short TCNT; + unsigned short TGRA; + unsigned short TGRB; +}; + +struct st_usb0 { + union { + unsigned short WORD; +// struct { +// unsigned short :5; +// unsigned short SCKE:1; +// unsigned short :1; +// unsigned short CNEN:1; +// unsigned short :1; +// unsigned short DCFM:1; +// unsigned short DRPD:1; +// unsigned short DPRPU:1; +// unsigned short DMRPU:1; +// unsigned short :2; +// unsigned short USBE:1; +// } BIT; + } SYSCFG; + char wk0[2]; + union { + unsigned short WORD; + struct { + unsigned short OVCMON:2; + unsigned short :7; + unsigned short HTACT:1; + unsigned short :3; + unsigned short IDMON:1; + unsigned short LNST:2; + } BIT; + } SYSSTS0; + char wk1[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :4; +// unsigned short HNPBTOA:1; +// unsigned short EXICEN:1; +// unsigned short VBUSEN:1; +// unsigned short WKUP:1; +// unsigned short RWUPE:1; +// unsigned short USBRST:1; +// unsigned short RESUME:1; +// unsigned short UACT:1; +// unsigned short :1; +// unsigned short RHST:3; +// } BIT; + } DVSTCTR0; + char wk2[10]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } CFIFO; + char wk3[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D0FIFO; + char wk4[2]; + union { + unsigned short WORD; + struct { + unsigned char L; + unsigned char H; + } BYTE; + } D1FIFO; + char wk5[2]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short :3; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :2; +// unsigned short ISEL:1; +// unsigned short :1; +// unsigned short CURPIPE:4; +// } BIT; + } CFIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } CFIFOCTR; + char wk6[4]; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D0FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D0FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short RCNT:1; +// unsigned short REW:1; +// unsigned short DCLRM:1; +// unsigned short DREQE:1; +// unsigned short :1; +// unsigned short MBW:1; +// unsigned short :1; +// unsigned short BIGEND:1; +// unsigned short :4; +// unsigned short CURPIPE:4; +// } BIT; + } D1FIFOSEL; + union { + unsigned short WORD; +// struct { +// unsigned short BVAL:1; +// unsigned short BCLR:1; +// unsigned short FRDY:1; +// unsigned short :4; +// unsigned short DTLN:9; +// } BIT; + } D1FIFOCTR; + union { + unsigned short WORD; +// struct { +// unsigned short VBSE:1; +// unsigned short RSME:1; +// unsigned short SOFE:1; +// unsigned short DVSE:1; +// unsigned short CTRE:1; +// unsigned short BEMPE:1; +// unsigned short NRDYE:1; +// unsigned short BRDYE:1; +// unsigned short :8; +// } BIT; + } INTENB0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCRE:1; +// unsigned short BCHGE:1; +// unsigned short :1; +// unsigned short DTCHE:1; +// unsigned short ATTCHE:1; +// unsigned short :4; +// unsigned short EOFERRE:1; +// unsigned short SIGNE:1; +// unsigned short SACKE:1; +// unsigned short :3; +// unsigned short PDDETINTE0:1; +// } BIT; + } INTENB1; + char wk7[2]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BRDYE:1; + unsigned short PIPE8BRDYE:1; + unsigned short PIPE7BRDYE:1; + unsigned short PIPE6BRDYE:1; + unsigned short PIPE5BRDYE:1; + unsigned short PIPE4BRDYE:1; + unsigned short PIPE3BRDYE:1; + unsigned short PIPE2BRDYE:1; + unsigned short PIPE1BRDYE:1; + unsigned short PIPE0BRDYE:1; + } BIT; + } BRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9NRDYE:1; + unsigned short PIPE8NRDYE:1; + unsigned short PIPE7NRDYE:1; + unsigned short PIPE6NRDYE:1; + unsigned short PIPE5NRDYE:1; + unsigned short PIPE4NRDYE:1; + unsigned short PIPE3NRDYE:1; + unsigned short PIPE2NRDYE:1; + unsigned short PIPE1NRDYE:1; + unsigned short PIPE0NRDYE:1; + } BIT; + } NRDYENB; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PIPE9BEMPE:1; + unsigned short PIPE8BEMPE:1; + unsigned short PIPE7BEMPE:1; + unsigned short PIPE6BEMPE:1; + unsigned short PIPE5BEMPE:1; + unsigned short PIPE4BEMPE:1; + unsigned short PIPE3BEMPE:1; + unsigned short PIPE2BEMPE:1; + unsigned short PIPE1BEMPE:1; + unsigned short PIPE0BEMPE:1; + } BIT; + } BEMPENB; + union { + unsigned short WORD; +// struct { +// unsigned short :7; +// unsigned short TRNENSEL:1; +// unsigned short :1; +// unsigned short BRDYM:1; +// unsigned short :1; +// unsigned short EDGESTS:1; +// unsigned short :4; +// } BIT; + } SOFCFG; + char wk8[2]; + union { + unsigned short WORD; +// struct { +// unsigned short VBINT:1; +// unsigned short RESM:1; +// unsigned short SOFR:1; +// unsigned short DVST:1; +// unsigned short CTRT:1; +// unsigned short BEMP:1; +// unsigned short NRDY:1; +// unsigned short BRDY:1; +// unsigned short VBSTS:1; +// unsigned short DVSQ:3; +// unsigned short VALID:1; +// unsigned short CTSQ:3; +// } BIT; + } INTSTS0; + union { + unsigned short WORD; +// struct { +// unsigned short OVRCR:1; +// unsigned short BCHG:1; +// unsigned short :1; +// unsigned short DTCH:1; +// unsigned short ATTCH:1; +// unsigned short :4; +// unsigned short EOFERR:1; +// unsigned short SIGN:1; +// unsigned short SACK:1; +// unsigned short :3; +// unsigned short PDDETINT0:1; +// } BIT; + } INTSTS1; + char wk9[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BRDY:1; +// unsigned short PIPE8BRDY:1; +// unsigned short PIPE7BRDY:1; +// unsigned short PIPE6BRDY:1; +// unsigned short PIPE5BRDY:1; +// unsigned short PIPE4BRDY:1; +// unsigned short PIPE3BRDY:1; +// unsigned short PIPE2BRDY:1; +// unsigned short PIPE1BRDY:1; +// unsigned short PIPE0BRDY:1; +// } BIT; + } BRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9NRDY:1; +// unsigned short PIPE8NRDY:1; +// unsigned short PIPE7NRDY:1; +// unsigned short PIPE6NRDY:1; +// unsigned short PIPE5NRDY:1; +// unsigned short PIPE4NRDY:1; +// unsigned short PIPE3NRDY:1; +// unsigned short PIPE2NRDY:1; +// unsigned short PIPE1NRDY:1; +// unsigned short PIPE0NRDY:1; +// } BIT; + } NRDYSTS; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short PIPE9BEMP:1; +// unsigned short PIPE8BEMP:1; +// unsigned short PIPE7BEMP:1; +// unsigned short PIPE6BEMP:1; +// unsigned short PIPE5BEMP:1; +// unsigned short PIPE4BEMP:1; +// unsigned short PIPE3BEMP:1; +// unsigned short PIPE2BEMP:1; +// unsigned short PIPE1BEMP:1; +// unsigned short PIPE0BEMP:1; +// } BIT; + } BEMPSTS; + union { + unsigned short WORD; +// struct { +// unsigned short OVRN:1; +// unsigned short CRCE:1; +// unsigned short :3; +// unsigned short FRNM:11; +// } BIT; + } FRMNUM; + char wk10[6]; + union { + unsigned short WORD; + struct { + unsigned short BREQUEST:8; + unsigned short BMREQUESTTYPE:8; + } BIT; + } USBREQ; + unsigned short USBVAL; + unsigned short USBINDX; + unsigned short USBLENG; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short :4; +// } BIT; + } DCPCFG; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :5; +// unsigned short MXPS:7; +// } BIT; + } DCPMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short SUREQ:1; +// unsigned short :2; +// unsigned short SUREQCLR:1; +// unsigned short :2; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :2; +// unsigned short CCPL:1; +// unsigned short PID:2; +// } BIT; + } DCPCTR; + char wk11[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :12; +// unsigned short PIPESEL:4; +// } BIT; + } PIPESEL; + char wk12[2]; + union { + unsigned short WORD; +// struct { +// unsigned short TYPE:2; +// unsigned short :3; +// unsigned short BFRE:1; +// unsigned short DBLB:1; +// unsigned short :1; +// unsigned short SHTNAK:1; +// unsigned short :2; +// unsigned short DIR:1; +// unsigned short EPNUM:4; +// } BIT; + } PIPECFG; + char wk13[2]; + union { + unsigned short WORD; +// struct { +// unsigned short DEVSEL:4; +// unsigned short :3; +// unsigned short MXPS:9; +// } BIT; + } PIPEMAXP; + union { + unsigned short WORD; +// struct { +// unsigned short :3; +// unsigned short IFIS:1; +// unsigned short :9; +// unsigned short IITV:3; +// } BIT; + } PIPEPERI; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE1CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE2CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE3CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE4CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short INBUFM:1; +// unsigned short :3; +// unsigned short ATREPM:1; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE5CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE6CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE7CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE8CTR; + union { + unsigned short WORD; +// struct { +// unsigned short BSTS:1; +// unsigned short :5; +// unsigned short ACLRM:1; +// unsigned short SQCLR:1; +// unsigned short SQSET:1; +// unsigned short SQMON:1; +// unsigned short PBUSY:1; +// unsigned short :3; +// unsigned short PID:2; +// } BIT; + } PIPE9CTR; + char wk14[14]; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE1TRE; + unsigned short PIPE1TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE2TRE; + unsigned short PIPE2TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE3TRE; + unsigned short PIPE3TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE4TRE; + unsigned short PIPE4TRN; + union { + unsigned short WORD; +// struct { +// unsigned short :6; +// unsigned short TRENB:1; +// unsigned short TRCLR:1; +// unsigned short :8; +// } BIT; + } PIPE5TRE; + unsigned short PIPE5TRN; + char wk15[12]; + union { + unsigned short WORD; + struct { + unsigned short :6; + unsigned short PDDETSTS0:1; + unsigned short CHGDETSTS0:1; + unsigned short BATCHGE0:1; + unsigned short :1; + unsigned short VDMSRCE0:1; + unsigned short IDPSINKE0:1; + unsigned short VDPSRCE0:1; + unsigned short IDMSINKE0:1; + unsigned short IDPSRCE0:1; + unsigned short RPDME0:1; + } BIT; + } USBBCCTRL0; + char wk16[26]; + union { + unsigned short WORD; + struct { + unsigned short :8; + unsigned short VDCEN:1; + unsigned short :6; + unsigned short VDDUSBE:1; + } BIT; + } USBMC; + char wk17[2]; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD0; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD1; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD2; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD3; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD4; + union { + unsigned short WORD; +// struct { +// unsigned short :8; +// unsigned short USBSPD:2; +// unsigned short :6; +// } BIT; + } DEVADD5; +}; + +struct st_wdt { + unsigned char WDTRR; + char wk0[1]; + union { + unsigned short WORD; + struct { + unsigned short :2; + unsigned short RPSS:2; + unsigned short :2; + unsigned short RPES:2; + unsigned short CKS:4; + unsigned short :2; + unsigned short TOPS:2; + } BIT; + } WDTCR; + union { + unsigned short WORD; + struct { + unsigned short REFEF:1; + unsigned short UNDFF:1; + unsigned short CNTVAL:14; + } BIT; + } WDTSR; + union { + unsigned char BYTE; + struct { + unsigned char RSTIRQS:1; + unsigned char :7; + } BIT; + } WDTRCR; +}; + +enum enum_ir { +IR_BSC_BUSERR=16,IR_FCU_FRDYI=23, +IR_ICU_SWINT=27, +IR_CMT0_CMI0,IR_CMT1_CMI1, +IR_CMT2_CMI2,IR_CMT3_CMI3, +IR_CAC_FERRF,IR_CAC_MENDF,IR_CAC_OVFF, +IR_USB0_D0FIFO0=36,IR_USB0_D1FIFO0,IR_USB0_USBI0, +IR_SDHI_SBFAI=40,IR_SDHI_CDETI,IR_SDHI_CACI,IR_SDHI_SDACI, +IR_RSPI0_SPEI0,IR_RSPI0_SPRI0,IR_RSPI0_SPTI0,IR_RSPI0_SPII0, +IR_RSCAN_COMFRXINT=52,IR_RSCAN_RXFINT,IR_RSCAN_TXINT,IR_RSCAN_CHERRINT,IR_RSCAN_GLERRINT, +IR_DOC_DOPCF, +IR_CMPB_CMPB0,IR_CMPB_CMPB1, +IR_CTSU_CTSUWR,IR_CTSU_CTSURD,IR_CTSU_CTSUFN, +IR_RTC_CUP, +IR_ICU_IRQ0,IR_ICU_IRQ1,IR_ICU_IRQ2,IR_ICU_IRQ3,IR_ICU_IRQ4,IR_ICU_IRQ5,IR_ICU_IRQ6,IR_ICU_IRQ7, +IR_ELC_ELSR8I=80, +IR_LVD_LVD1=88,IR_LVD_LVD2, +IR_CMPA_CMPA1=88,IR_CMPA_CMPA2, +IR_USB0_USBR0, +IR_VBATT_VBTLVDI, +IR_RTC_ALM,IR_RTC_PRD, +IR_S12AD_S12ADI0=102,IR_S12AD_GBADI, +IR_CMPB1_CMPB2,IR_CMPB1_CMPB3, +IR_ELC_ELSR18I,IR_ELC_ELSR19I, +IR_SSI0_SSIF0,IR_SSI0_SSIRXI0,IR_SSI0_SSITXI0, +IR_SECURITY_RD,IR_SECURITY_WR,IR_SECURITY_ERR, +IR_MTU0_TGIA0,IR_MTU0_TGIB0,IR_MTU0_TGIC0,IR_MTU0_TGID0,IR_MTU0_TCIV0,IR_MTU0_TGIE0,IR_MTU0_TGIF0, +IR_MTU1_TGIA1,IR_MTU1_TGIB1,IR_MTU1_TCIV1,IR_MTU1_TCIU1, +IR_MTU2_TGIA2,IR_MTU2_TGIB2,IR_MTU2_TCIV2,IR_MTU2_TCIU2, +IR_MTU3_TGIA3,IR_MTU3_TGIB3,IR_MTU3_TGIC3,IR_MTU3_TGID3,IR_MTU3_TCIV3, +IR_MTU4_TGIA4,IR_MTU4_TGIB4,IR_MTU4_TGIC4,IR_MTU4_TGID4,IR_MTU4_TCIV4, +IR_MTU5_TGIU5,IR_MTU5_TGIV5,IR_MTU5_TGIW5, +IR_TPU0_TGI0A,IR_TPU0_TGI0B,IR_TPU0_TGI0C,IR_TPU0_TGI0D,IR_TPU0_TCI0V, +IR_TPU1_TGI1A,IR_TPU1_TGI1B,IR_TPU1_TCI1V,IR_TPU1_TCI1U, +IR_TPU2_TGI2A,IR_TPU2_TGI2B,IR_TPU2_TCI2V,IR_TPU2_TCI2U, +IR_TPU3_TGI3A,IR_TPU3_TGI3B,IR_TPU3_TGI3C,IR_TPU3_TGI3D,IR_TPU3_TCI3V, +IR_TPU4_TGI4A,IR_TPU4_TGI4B,IR_TPU4_TCI4V,IR_TPU4_TCI4U, +IR_TPU5_TGI5A,IR_TPU5_TGI5B,IR_TPU5_TCI5V,IR_TPU5_TCI5U, +IR_POE_OEI1=170,IR_POE_OEI2, +IR_TMR0_CMIA0=174,IR_TMR0_CMIB0,IR_TMR0_OVI0, +IR_TMR1_CMIA1,IR_TMR1_CMIB1,IR_TMR1_OVI1, +IR_TMR2_CMIA2,IR_TMR2_CMIB2,IR_TMR2_OVI2, +IR_TMR3_CMIA3,IR_TMR3_CMIB3,IR_TMR3_OVI3, +IR_DMAC_DMAC0I=198,IR_DMAC_DMAC1I,IR_DMAC_DMAC2I,IR_DMAC_DMAC3I, +IR_SCI0_ERI0=214,IR_SCI0_RXI0,IR_SCI0_TXI0,IR_SCI0_TEI0, +IR_SCI1_ERI1,IR_SCI1_RXI1,IR_SCI1_TXI1,IR_SCI1_TEI1, +IR_SCI5_ERI5,IR_SCI5_RXI5,IR_SCI5_TXI5,IR_SCI5_TEI5, +IR_SCI6_ERI6,IR_SCI6_RXI6,IR_SCI6_TXI6,IR_SCI6_TEI6, +IR_SCI8_ERI8,IR_SCI8_RXI8,IR_SCI8_TXI8,IR_SCI8_TEI8, +IR_SCI9_ERI9,IR_SCI9_RXI9,IR_SCI9_TXI9,IR_SCI9_TEI9, +IR_SCI12_ERI12,IR_SCI12_RXI12,IR_SCI12_TXI12,IR_SCI12_TEI12,IR_SCI12_SCIX0,IR_SCI12_SCIX1,IR_SCI12_SCIX2,IR_SCI12_SCIX3, +IR_RIIC0_EEI0,IR_RIIC0_RXI0,IR_RIIC0_TXI0,IR_RIIC0_TEI0 +}; + +enum enum_dtce { +DTCE_ICU_SWINT=27, +DTCE_CMT0_CMI0,DTCE_CMT1_CMI1, +DTCE_CMT2_CMI2,DTCE_CMT3_CMI3, +DTCE_USB0_D0FIFO0=36,DTCE_USB0_D1FIFO0, +DTCE_SDHI_SBFAI=40, +DTCE_RSPI0_SPRI0=45,DTCE_RSPI0_SPTI0, +DTCE_RSCAN_COMFRXINT=52, +DTCE_CMPB_CMPB0=58,DTCE_CMPB_CMPB1, +DTCE_CTSU_CTSUWR,DTCE_CTSU_CTSURD, +DTCE_ICU_IRQ0=64,DTCE_ICU_IRQ1,DTCE_ICU_IRQ2,DTCE_ICU_IRQ3,DTCE_ICU_IRQ4,DTCE_ICU_IRQ5,DTCE_ICU_IRQ6,DTCE_ICU_IRQ7, +DTCE_S12AD_S12ADI0=102,DTCE_S12AD_GBADI, +DTCE_CMPB1_CMPB2,DTCE_CMPB1_CMPB3, +DTCE_ELC_ELSR18I,DTCE_ELC_ELSR19I, +DTCE_SSI0_SSIRXI0=109,DTCE_SSI0_SSITXI0, +DTCE_SECURITY_RD,DTCE_SECURITY_WR, +DTCE_MTU0_TGIA0=114,DTCE_MTU0_TGIB0,DTCE_MTU0_TGIC0,DTCE_MTU0_TGID0, +DTCE_MTU1_TGIA1=121,DTCE_MTU1_TGIB1, +DTCE_MTU2_TGIA2=125,DTCE_MTU2_TGIB2, +DTCE_MTU3_TGIA3=129,DTCE_MTU3_TGIB3,DTCE_MTU3_TGIC3,DTCE_MTU3_TGID3, +DTCE_MTU4_TGIA4=134,DTCE_MTU4_TGIB4,DTCE_MTU4_TGIC4,DTCE_MTU4_TGID4,DTCE_MTU4_TCIV4, +DTCE_MTU5_TGIU5,DTCE_MTU5_TGIV5,DTCE_MTU5_TGIW5, +DTCE_TPU0_TGI0A,DTCE_TPU0_TGI0B,DTCE_TPU0_TGI0C,DTCE_TPU0_TGI0D, +DTCE_TPU1_TGI1A=147,DTCE_TPU1_TGI1B, +DTCE_TPU2_TGI2A=151,DTCE_TPU2_TGI2B, +DTCE_TPU3_TGI3A=155,DTCE_TPU3_TGI3B,DTCE_TPU3_TGI3C,DTCE_TPU3_TGI3D, +DTCE_TPU4_TGI4A=160,DTCE_TPU4_TGI4B, +DTCE_TPU5_TGI5A=164,DTCE_TPU5_TGI5B, +DTCE_TMR0_CMIA0=174,DTCE_TMR0_CMIB0, +DTCE_TMR1_CMIA1=177,DTCE_TMR1_CMIB1, +DTCE_TMR2_CMIA2=180,DTCE_TMR2_CMIB2, +DTCE_TMR3_CMIA3=183,DTCE_TMR3_CMIB3, +DTCE_DMAC_DMAC0I=198,DTCE_DMAC_DMAC1I,DTCE_DMAC_DMAC2I,DTCE_DMAC_DMAC3I, +DTCE_SCI0_RXI0=215,DTCE_SCI0_TXI0, +DTCE_SCI1_RXI1=219,DTCE_SCI1_TXI1, +DTCE_SCI5_RXI5=223,DTCE_SCI5_TXI5, +DTCE_SCI6_RXI6=227,DTCE_SCI6_TXI6, +DTCE_SCI8_RXI8=231,DTCE_SCI8_TXI8, +DTCE_SCI9_RXI9=235,DTCE_SCI9_TXI9, +DTCE_SCI12_RXI12=239,DTCE_SCI12_TXI12, +DTCE_RIIC0_RXI0=247,DTCE_RIIC0_TXI0 +}; + +enum enum_ier { +IER_BSC_BUSERR=0x02, +IER_FCU_FRDYI=0x02, +IER_ICU_SWINT=0x03, +IER_CMT0_CMI0=0x03,IER_CMT1_CMI1=0x03, +IER_CMT2_CMI2=0x03,IER_CMT3_CMI3=0x03, +IER_CAC_FERRF=0x04,IER_CAC_MENDF=0x04,IER_CAC_OVFF=0x04, +IER_USB0_D0FIFO0=0x04,IER_USB0_D1FIFO0=0x04,IER_USB0_USBI0=0x04, +IER_SDHI_SBFAI=0x05,IER_SDHI_CDETI=0x05,IER_SDHI_CACI=0x05,IER_SDHI_SDACI=0x05, +IER_RSPI0_SPEI0=0x05,IER_RSPI0_SPRI0=0x05,IER_RSPI0_SPTI0=0x05,IER_RSPI0_SPII0=0x05, +IER_RSCAN_COMFRXINT=0x06,IER_RSCAN_RXFINT=0x06,IER_RSCAN_TXINT=0x06,IER_RSCAN_CHERRINT=0x06,IER_RSCAN_GLERRINT=0x07, +IER_DOC_DOPCF=0x07, +IER_CMPB_CMPB0=0x07,IER_CMPB_CMPB1=0x07, +IER_CTSU_CTSUWR=0x07,IER_CTSU_CTSURD=0x07,IER_CTSU_CTSUFN=0x07, +IER_RTC_CUP=0x07, +IER_ICU_IRQ0=0x08,IER_ICU_IRQ1=0x08,IER_ICU_IRQ2=0x08,IER_ICU_IRQ3=0x08,IER_ICU_IRQ4=0x08,IER_ICU_IRQ5=0x08,IER_ICU_IRQ6=0x08,IER_ICU_IRQ7=0x08, +IER_ELC_ELSR8I=0x0A, +IER_LVD_LVD1=0x0B,IER_LVD_LVD2=0x0B, +IER_CMPA_CMPA1=0x0B,IER_CMPA_CMPA2=0x0B, +IER_USB0_USBR0=0x0B, +IER_VBATT_VBTLVDI=0x0B, +IER_RTC_ALM=0x0B,IER_RTC_PRD=0x0B, +IER_S12AD_S12ADI0=0x0C,IER_S12AD_GBADI=0x0C, +IER_CMPB1_CMPB2=0x0D,IER_CMPB1_CMPB3=0x0D, +IER_ELC_ELSR18I=0x0D,IER_ELC_ELSR19I=0x0D, +IER_SSI0_SSIF0=0x0D,IER_SSI0_SSIRXI0=0x0D,IER_SSI0_SSITXI0=0x0D, +IER_SECURITY_RD=0x0D,IER_SECURITY_WR=0x0E,IER_SECURITY_ERR=0x0E, +IER_MTU0_TGIA0=0x0E,IER_MTU0_TGIB0=0x0E,IER_MTU0_TGIC0=0x0E,IER_MTU0_TGID0=0x0E,IER_MTU0_TCIV0=0x0E,IER_MTU0_TGIE0=0x0E,IER_MTU0_TGIF0=0x0F, +IER_MTU1_TGIA1=0x0F,IER_MTU1_TGIB1=0x0F,IER_MTU1_TCIV1=0x0F,IER_MTU1_TCIU1=0x0F, +IER_MTU2_TGIA2=0x0F,IER_MTU2_TGIB2=0x0F,IER_MTU2_TCIV2=0x0F,IER_MTU2_TCIU2=0x10, +IER_MTU3_TGIA3=0x10,IER_MTU3_TGIB3=0x10,IER_MTU3_TGIC3=0x10,IER_MTU3_TGID3=0x10,IER_MTU3_TCIV3=0x10, +IER_MTU4_TGIA4=0x10,IER_MTU4_TGIB4=0x10,IER_MTU4_TGIC4=0x11,IER_MTU4_TGID4=0x11,IER_MTU4_TCIV4=0x11, +IER_MTU5_TGIU5=0x11,IER_MTU5_TGIV5=0x11,IER_MTU5_TGIW5=0x11, +IER_TPU0_TGI0A=0x11,IER_TPU0_TGI0B=0x11,IER_TPU0_TGI0C=0x12,IER_TPU0_TGI0D=0x12,IER_TPU0_TCI0V=0x12, +IER_TPU1_TGI1A=0x12,IER_TPU1_TGI1B=0x12,IER_TPU1_TCI1V=0x12,IER_TPU1_TCI1U=0x12, +IER_TPU2_TGI2A=0x12,IER_TPU2_TGI2B=0x13,IER_TPU2_TCI2V=0x13,IER_TPU2_TCI2U=0x13, +IER_TPU3_TGI3A=0x13,IER_TPU3_TGI3B=0x13,IER_TPU3_TGI3C=0x13,IER_TPU3_TGI3D=0x13,IER_TPU3_TCI3V=0x13, +IER_TPU4_TGI4A=0x14,IER_TPU4_TGI4B=0x14,IER_TPU4_TCI4V=0x14,IER_TPU4_TCI4U=0x14, +IER_TPU5_TGI5A=0x14,IER_TPU5_TGI5B=0x14,IER_TPU5_TCI5V=0x14,IER_TPU5_TCI5U=0x14, +IER_POE_OEI1=0x15,IER_POE_OEI2=0x15, +IER_TMR0_CMIA0=0x15,IER_TMR0_CMIB0=0x15,IER_TMR0_OVI0=0x16, +IER_TMR1_CMIA1=0x16,IER_TMR1_CMIB1=0x16,IER_TMR1_OVI1=0x16, +IER_TMR2_CMIA2=0x16,IER_TMR2_CMIB2=0x16,IER_TMR2_OVI2=0x16, +IER_TMR3_CMIA3=0x16,IER_TMR3_CMIB3=0x17,IER_TMR3_OVI3=0x17, +IER_DMAC_DMAC0I=0x18,IER_DMAC_DMAC1I=0x18,IER_DMAC_DMAC2I=0x19,IER_DMAC_DMAC3I=0x19, +IER_SCI0_ERI0=0x1A,IER_SCI0_RXI0=0x1A,IER_SCI0_TXI0=0x1B,IER_SCI0_TEI0=0x1B, +IER_SCI1_ERI1=0x1B,IER_SCI1_RXI1=0x1B,IER_SCI1_TXI1=0x1B,IER_SCI1_TEI1=0x1B, +IER_SCI5_ERI5=0x1B,IER_SCI5_RXI5=0x1B,IER_SCI5_TXI5=0x1C,IER_SCI5_TEI5=0x1C, +IER_SCI6_ERI6=0x1C,IER_SCI6_RXI6=0x1C,IER_SCI6_TXI6=0x1C,IER_SCI6_TEI6=0x1C, +IER_SCI8_ERI8=0x1C,IER_SCI8_RXI8=0x1C,IER_SCI8_TXI8=0x1D,IER_SCI8_TEI8=0x1D, +IER_SCI9_ERI9=0x1D,IER_SCI9_RXI9=0x1D,IER_SCI9_TXI9=0x1D,IER_SCI9_TEI9=0x1D, +IER_SCI12_ERI12=0x1D,IER_SCI12_RXI12=0x1D,IER_SCI12_TXI12=0x1E,IER_SCI12_TEI12=0x1E,IER_SCI12_SCIX0=0x1E,IER_SCI12_SCIX1=0x1E,IER_SCI12_SCIX2=0x1E,IER_SCI12_SCIX3=0x1E, +IER_RIIC0_EEI0=0x1E,IER_RIIC0_RXI0=0x1E,IER_RIIC0_TXI0=0x1F,IER_RIIC0_TEI0=0x1F +}; + +enum enum_ipr { +IPR_BSC_BUSERR=0, +IPR_FCU_FRDYI=2, +IPR_ICU_SWINT=3, +IPR_CMT0_CMI0=4,IPR_CMT1_CMI1=5, +IPR_CMT2_CMI2=6,IPR_CMT3_CMI3=7, +IPR_CAC_FERRF=32,IPR_CAC_MENDF=33,IPR_CAC_OVFF=34, +IPR_USB0_D0FIFO0=36,IPR_USB0_D1FIFO0=37,IPR_USB0_USBI0=38, +IPR_SDHI_SBFAI=40,IPR_SDHI_CDETI=41,IPR_SDHI_CACI=42,IPR_SDHI_SDACI=43, +IPR_RSPI0_SPEI0=44,IPR_RSPI0_SPRI0=44,IPR_RSPI0_SPTI0=44,IPR_RSPI0_SPII0=44, +IPR_RSCAN_COMFRXINT=52,IPR_RSCAN_RXFINT=53,IPR_RSCAN_TXINT=54,IPR_RSCAN_CHERRINT=55,IPR_RSCAN_GLERRINT=56, +IPR_DOC_DOPCF=57, +IPR_CMPB_CMPB0=58,IPR_CMPB_CMPB1=59, +IPR_CTSU_CTSUWR=60,IPR_CTSU_CTSURD=60,IPR_CTSU_CTSUFN=60, +IPR_RTC_CUP=63, +IPR_ICU_IRQ0=64,IPR_ICU_IRQ1=65,IPR_ICU_IRQ2=66,IPR_ICU_IRQ3=67,IPR_ICU_IRQ4=68,IPR_ICU_IRQ5=69,IPR_ICU_IRQ6=70,IPR_ICU_IRQ7=71, +IPR_ELC_ELSR8I=80, +IPR_LVD_LVD1=88,IPR_LVD_LVD2=89, +IPR_CMPA_CMPA1=88,IPR_CMPA_CMPA2=89, +IPR_USB0_USBR0=90, +IPR_VBATT_VBTLVDI=91, +IPR_RTC_ALM=92,IPR_RTC_PRD=93, +IPR_S12AD_S12ADI0=102,IPR_S12AD_GBADI=103, +IPR_CMPB1_CMPB2=104,IPR_CMPB1_CMPB3=105, +IPR_ELC_ELSR18I=106,IPR_ELC_ELSR19I=107, +IPR_SSI0_SSIF0=108,IPR_SSI0_SSIRXI0=108,IPR_SSI0_SSITXI0=108, +IPR_SECURITY_RD=111,IPR_SECURITY_WR=111,IPR_SECURITY_ERR=113, +IPR_MTU0_TGIA0=114,IPR_MTU0_TGIB0=114,IPR_MTU0_TGIC0=114,IPR_MTU0_TGID0=114,IPR_MTU0_TCIV0=118,IPR_MTU0_TGIE0=118,IPR_MTU0_TGIF0=118, +IPR_MTU1_TGIA1=121,IPR_MTU1_TGIB1=121,IPR_MTU1_TCIV1=123,IPR_MTU1_TCIU1=123, +IPR_MTU2_TGIA2=125,IPR_MTU2_TGIB2=125,IPR_MTU2_TCIV2=127,IPR_MTU2_TCIU2=127, +IPR_MTU3_TGIA3=129,IPR_MTU3_TGIB3=129,IPR_MTU3_TGIC3=129,IPR_MTU3_TGID3=129,IPR_MTU3_TCIV3=133, +IPR_MTU4_TGIA4=134,IPR_MTU4_TGIB4=134,IPR_MTU4_TGIC4=134,IPR_MTU4_TGID4=134,IPR_MTU4_TCIV4=138, +IPR_MTU5_TGIU5=139,IPR_MTU5_TGIV5=139,IPR_MTU5_TGIW5=139, +IPR_TPU0_TGI0A=142,IPR_TPU0_TGI0B=142,IPR_TPU0_TGI0C=142,IPR_TPU0_TGI0D=142,IPR_TPU0_TCI0V=146, +IPR_TPU1_TGI1A=147,IPR_TPU1_TGI1B=147,IPR_TPU1_TCI1V=149,IPR_TPU1_TCI1U=149, +IPR_TPU2_TGI2A=151,IPR_TPU2_TGI2B=151,IPR_TPU2_TCI2V=153,IPR_TPU2_TCI2U=153, +IPR_TPU3_TGI3A=155,IPR_TPU3_TGI3B=155,IPR_TPU3_TGI3C=155,IPR_TPU3_TGI3D=155,IPR_TPU3_TCI3V=159, +IPR_TPU4_TGI4A=160,IPR_TPU4_TGI4B=160,IPR_TPU4_TCI4V=162,IPR_TPU4_TCI4U=162, +IPR_TPU5_TGI5A=164,IPR_TPU5_TGI5B=164,IPR_TPU5_TCI5V=166,IPR_TPU5_TCI5U=166, +IPR_POE_OEI1=170,IPR_POE_OEI2=171, +IPR_TMR0_CMIA0=174,IPR_TMR0_CMIB0=174,IPR_TMR0_OVI0=174, +IPR_TMR1_CMIA1=177,IPR_TMR1_CMIB1=177,IPR_TMR1_OVI1=177, +IPR_TMR2_CMIA2=180,IPR_TMR2_CMIB2=180,IPR_TMR2_OVI2=180, +IPR_TMR3_CMIA3=183,IPR_TMR3_CMIB3=183,IPR_TMR3_OVI3=183, +IPR_DMAC_DMAC0I=198,IPR_DMAC_DMAC1I=199,IPR_DMAC_DMAC2I=200,IPR_DMAC_DMAC3I=201, +IPR_SCI0_ERI0=214,IPR_SCI0_RXI0=214,IPR_SCI0_TXI0=214,IPR_SCI0_TEI0=214, +IPR_SCI1_ERI1=218,IPR_SCI1_RXI1=218,IPR_SCI1_TXI1=218,IPR_SCI1_TEI1=218, +IPR_SCI5_ERI5=222,IPR_SCI5_RXI5=222,IPR_SCI5_TXI5=222,IPR_SCI5_TEI5=222, +IPR_SCI6_ERI6=226,IPR_SCI6_RXI6=226,IPR_SCI6_TXI6=226,IPR_SCI6_TEI6=226, +IPR_SCI8_ERI8=230,IPR_SCI8_RXI8=230,IPR_SCI8_TXI8=230,IPR_SCI8_TEI8=230, +IPR_SCI9_ERI9=234,IPR_SCI9_RXI9=234,IPR_SCI9_TXI9=234,IPR_SCI9_TEI9=234, +IPR_SCI12_ERI12=238,IPR_SCI12_RXI12=238,IPR_SCI12_TXI12=238,IPR_SCI12_TEI12=238,IPR_SCI12_SCIX0=242,IPR_SCI12_SCIX1=243,IPR_SCI12_SCIX2=244,IPR_SCI12_SCIX3=245, +IPR_RIIC0_EEI0=246,IPR_RIIC0_RXI0=247,IPR_RIIC0_TXI0=248,IPR_RIIC0_TEI0=249, +IPR_BSC_=0, +IPR_FCU_=2, +IPR_RSPI0_=44, +IPR_DOC_=57, +IPR_VBATT_=91, +IPR_MTU1_TGI=121, +IPR_MTU1_TCI=123, +IPR_MTU2_TGI=125, +IPR_MTU2_TCI=127, +IPR_MTU3_TGI=129, +IPR_MTU4_TGI=134, +IPR_MTU5_=139, +IPR_MTU5_TGI=139, +IPR_TPU0_TGI=142, +IPR_TPU1_TGI=147, +IPR_TPU1_TCI=149, +IPR_TPU2_TGI=151, +IPR_TPU2_TCI=153, +IPR_TPU3_TGI=155, +IPR_TPU4_TGI=160, +IPR_TPU4_TCI=162, +IPR_TPU5_TGI=164, +IPR_TPU5_TCI=166, +IPR_TMR0_=174, +IPR_TMR1_=177, +IPR_TMR2_=180, +IPR_TMR3_=183, +IPR_SCI0_=214, +IPR_SCI1_=218, +IPR_SCI5_=222, +IPR_SCI6_=226, +IPR_SCI8_=230, +IPR_SCI9_=234 +}; + +#define IEN_BSC_BUSERR IEN0 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMT2_CMI2 IEN6 +#define IEN_CMT3_CMI3 IEN7 +#define IEN_CAC_FERRF IEN0 +#define IEN_CAC_MENDF IEN1 +#define IEN_CAC_OVFF IEN2 +#define IEN_USB0_D0FIFO0 IEN4 +#define IEN_USB0_D1FIFO0 IEN5 +#define IEN_USB0_USBI0 IEN6 +#define IEN_SDHI_SBFAI IEN0 +#define IEN_SDHI_CDETI IEN1 +#define IEN_SDHI_CACI IEN2 +#define IEN_SDHI_SDACI IEN3 +#define IEN_RSPI0_SPEI0 IEN4 +#define IEN_RSPI0_SPRI0 IEN5 +#define IEN_RSPI0_SPTI0 IEN6 +#define IEN_RSPI0_SPII0 IEN7 +#define IEN_RSCAN_COMFRXINT IEN4 +#define IEN_RSCAN_RXFINT IEN5 +#define IEN_RSCAN_TXINT IEN6 +#define IEN_RSCAN_CHERRINT IEN7 +#define IEN_RSCAN_GLERRINT IEN0 +#define IEN_DOC_DOPCF IEN1 +#define IEN_CMPB_CMPB0 IEN2 +#define IEN_CMPB_CMPB1 IEN3 +#define IEN_CTSU_CTSUWR IEN4 +#define IEN_CTSU_CTSURD IEN5 +#define IEN_CTSU_CTSUFN IEN6 +#define IEN_RTC_CUP IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ELC_ELSR8I IEN0 +#define IEN_LVD_LVD1 IEN0 +#define IEN_LVD_LVD2 IEN1 +#define IEN_CMPA_CMPA1 IEN0 +#define IEN_CMPA_CMPA2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_VBATT_VBTLVDI IEN3 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_S12AD_S12ADI0 IEN6 +#define IEN_S12AD_GBADI IEN7 +#define IEN_CMPB1_CMPB2 IEN0 +#define IEN_CMPB1_CMPB3 IEN1 +#define IEN_ELC_ELSR18I IEN2 +#define IEN_ELC_ELSR19I IEN3 +#define IEN_SSI0_SSIF0 IEN4 +#define IEN_SSI0_SSIRXI0 IEN5 +#define IEN_SSI0_SSITXI0 IEN6 +#define IEN_SECURITY_RD IEN7 +#define IEN_SECURITY_WR IEN0 +#define IEN_SECURITY_ERR IEN1 +#define IEN_MTU0_TGIA0 IEN2 +#define IEN_MTU0_TGIB0 IEN3 +#define IEN_MTU0_TGIC0 IEN4 +#define IEN_MTU0_TGID0 IEN5 +#define IEN_MTU0_TCIV0 IEN6 +#define IEN_MTU0_TGIE0 IEN7 +#define IEN_MTU0_TGIF0 IEN0 +#define IEN_MTU1_TGIA1 IEN1 +#define IEN_MTU1_TGIB1 IEN2 +#define IEN_MTU1_TCIV1 IEN3 +#define IEN_MTU1_TCIU1 IEN4 +#define IEN_MTU2_TGIA2 IEN5 +#define IEN_MTU2_TGIB2 IEN6 +#define IEN_MTU2_TCIV2 IEN7 +#define IEN_MTU2_TCIU2 IEN0 +#define IEN_MTU3_TGIA3 IEN1 +#define IEN_MTU3_TGIB3 IEN2 +#define IEN_MTU3_TGIC3 IEN3 +#define IEN_MTU3_TGID3 IEN4 +#define IEN_MTU3_TCIV3 IEN5 +#define IEN_MTU4_TGIA4 IEN6 +#define IEN_MTU4_TGIB4 IEN7 +#define IEN_MTU4_TGIC4 IEN0 +#define IEN_MTU4_TGID4 IEN1 +#define IEN_MTU4_TCIV4 IEN2 +#define IEN_MTU5_TGIU5 IEN3 +#define IEN_MTU5_TGIV5 IEN4 +#define IEN_MTU5_TGIW5 IEN5 +#define IEN_TPU0_TGI0A IEN6 +#define IEN_TPU0_TGI0B IEN7 +#define IEN_TPU0_TGI0C IEN0 +#define IEN_TPU0_TGI0D IEN1 +#define IEN_TPU0_TCI0V IEN2 +#define IEN_TPU1_TGI1A IEN3 +#define IEN_TPU1_TGI1B IEN4 +#define IEN_TPU1_TCI1V IEN5 +#define IEN_TPU1_TCI1U IEN6 +#define IEN_TPU2_TGI2A IEN7 +#define IEN_TPU2_TGI2B IEN0 +#define IEN_TPU2_TCI2V IEN1 +#define IEN_TPU2_TCI2U IEN2 +#define IEN_TPU3_TGI3A IEN3 +#define IEN_TPU3_TGI3B IEN4 +#define IEN_TPU3_TGI3C IEN5 +#define IEN_TPU3_TGI3D IEN6 +#define IEN_TPU3_TCI3V IEN7 +#define IEN_TPU4_TGI4A IEN0 +#define IEN_TPU4_TGI4B IEN1 +#define IEN_TPU4_TCI4V IEN2 +#define IEN_TPU4_TCI4U IEN3 +#define IEN_TPU5_TGI5A IEN4 +#define IEN_TPU5_TGI5B IEN5 +#define IEN_TPU5_TCI5V IEN6 +#define IEN_TPU5_TCI5U IEN7 +#define IEN_POE_OEI1 IEN2 +#define IEN_POE_OEI2 IEN3 +#define IEN_TMR0_CMIA0 IEN6 +#define IEN_TMR0_CMIB0 IEN7 +#define IEN_TMR0_OVI0 IEN0 +#define IEN_TMR1_CMIA1 IEN1 +#define IEN_TMR1_CMIB1 IEN2 +#define IEN_TMR1_OVI1 IEN3 +#define IEN_TMR2_CMIA2 IEN4 +#define IEN_TMR2_CMIB2 IEN5 +#define IEN_TMR2_OVI2 IEN6 +#define IEN_TMR3_CMIA3 IEN7 +#define IEN_TMR3_CMIB3 IEN0 +#define IEN_TMR3_OVI3 IEN1 +#define IEN_DMAC_DMAC0I IEN6 +#define IEN_DMAC_DMAC1I IEN7 +#define IEN_DMAC_DMAC2I IEN0 +#define IEN_DMAC_DMAC3I IEN1 +#define IEN_SCI0_ERI0 IEN6 +#define IEN_SCI0_RXI0 IEN7 +#define IEN_SCI0_TXI0 IEN0 +#define IEN_SCI0_TEI0 IEN1 +#define IEN_SCI1_ERI1 IEN2 +#define IEN_SCI1_RXI1 IEN3 +#define IEN_SCI1_TXI1 IEN4 +#define IEN_SCI1_TEI1 IEN5 +#define IEN_SCI5_ERI5 IEN6 +#define IEN_SCI5_RXI5 IEN7 +#define IEN_SCI5_TXI5 IEN0 +#define IEN_SCI5_TEI5 IEN1 +#define IEN_SCI6_ERI6 IEN2 +#define IEN_SCI6_RXI6 IEN3 +#define IEN_SCI6_TXI6 IEN4 +#define IEN_SCI6_TEI6 IEN5 +#define IEN_SCI8_ERI8 IEN6 +#define IEN_SCI8_RXI8 IEN7 +#define IEN_SCI8_TXI8 IEN0 +#define IEN_SCI8_TEI8 IEN1 +#define IEN_SCI9_ERI9 IEN2 +#define IEN_SCI9_RXI9 IEN3 +#define IEN_SCI9_TXI9 IEN4 +#define IEN_SCI9_TEI9 IEN5 +#define IEN_SCI12_ERI12 IEN6 +#define IEN_SCI12_RXI12 IEN7 +#define IEN_SCI12_TXI12 IEN0 +#define IEN_SCI12_TEI12 IEN1 +#define IEN_SCI12_SCIX0 IEN2 +#define IEN_SCI12_SCIX1 IEN3 +#define IEN_SCI12_SCIX2 IEN4 +#define IEN_SCI12_SCIX3 IEN5 +#define IEN_RIIC0_EEI0 IEN6 +#define IEN_RIIC0_RXI0 IEN7 +#define IEN_RIIC0_TXI0 IEN0 +#define IEN_RIIC0_TEI0 IEN1 + +#define VECT_BSC_BUSERR 16 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMT2_CMI2 30 +#define VECT_CMT3_CMI3 31 +#define VECT_CAC_FERRF 32 +#define VECT_CAC_MENDF 33 +#define VECT_CAC_OVFF 34 +#define VECT_USB0_D0FIFO0 36 +#define VECT_USB0_D1FIFO0 37 +#define VECT_USB0_USBI0 38 +#define VECT_SDHI_SBFAI 40 +#define VECT_SDHI_CDETI 41 +#define VECT_SDHI_CACI 42 +#define VECT_SDHI_SDACI 43 +#define VECT_RSPI0_SPEI0 44 +#define VECT_RSPI0_SPRI0 45 +#define VECT_RSPI0_SPTI0 46 +#define VECT_RSPI0_SPII0 47 +#define VECT_RSCAN_COMFRXINT 52 +#define VECT_RSCAN_RXFINT 53 +#define VECT_RSCAN_TXINT 54 +#define VECT_RSCAN_CHERRINT 55 +#define VECT_RSCAN_GLERRINT 56 +#define VECT_DOC_DOPCF 57 +#define VECT_CMPB_CMPB0 58 +#define VECT_CMPB_CMPB1 59 +#define VECT_CTSU_CTSUWR 60 +#define VECT_CTSU_CTSURD 61 +#define VECT_CTSU_CTSUFN 62 +#define VECT_RTC_CUP 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ELC_ELSR8I 80 +#define VECT_LVD_LVD1 88 +#define VECT_LVD_LVD2 89 +#define VECT_CMPA_CMPA1 88 +#define VECT_CMPA_CMPA2 89 +#define VECT_USB0_USBR0 90 +#define VECT_VBATT_VBTLVDI 91 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_S12AD_S12ADI0 102 +#define VECT_S12AD_GBADI 103 +#define VECT_CMPB1_CMPB2 104 +#define VECT_CMPB1_CMPB3 105 +#define VECT_ELC_ELSR18I 106 +#define VECT_ELC_ELSR19I 107 +#define VECT_SSI0_SSIF0 108 +#define VECT_SSI0_SSIRXI0 109 +#define VECT_SSI0_SSITXI0 110 +#define VECT_SECURITY_RD 111 +#define VECT_SECURITY_WR 112 +#define VECT_SECURITY_ERR 113 +#define VECT_MTU0_TGIA0 114 +#define VECT_MTU0_TGIB0 115 +#define VECT_MTU0_TGIC0 116 +#define VECT_MTU0_TGID0 117 +#define VECT_MTU0_TCIV0 118 +#define VECT_MTU0_TGIE0 119 +#define VECT_MTU0_TGIF0 120 +#define VECT_MTU1_TGIA1 121 +#define VECT_MTU1_TGIB1 122 +#define VECT_MTU1_TCIV1 123 +#define VECT_MTU1_TCIU1 124 +#define VECT_MTU2_TGIA2 125 +#define VECT_MTU2_TGIB2 126 +#define VECT_MTU2_TCIV2 127 +#define VECT_MTU2_TCIU2 128 +#define VECT_MTU3_TGIA3 129 +#define VECT_MTU3_TGIB3 130 +#define VECT_MTU3_TGIC3 131 +#define VECT_MTU3_TGID3 132 +#define VECT_MTU3_TCIV3 133 +#define VECT_MTU4_TGIA4 134 +#define VECT_MTU4_TGIB4 135 +#define VECT_MTU4_TGIC4 136 +#define VECT_MTU4_TGID4 137 +#define VECT_MTU4_TCIV4 138 +#define VECT_MTU5_TGIU5 139 +#define VECT_MTU5_TGIV5 140 +#define VECT_MTU5_TGIW5 141 +#define VECT_TPU0_TGI0A 142 +#define VECT_TPU0_TGI0B 143 +#define VECT_TPU0_TGI0C 144 +#define VECT_TPU0_TGI0D 145 +#define VECT_TPU0_TCI0V 146 +#define VECT_TPU1_TGI1A 147 +#define VECT_TPU1_TGI1B 148 +#define VECT_TPU1_TCI1V 149 +#define VECT_TPU1_TCI1U 150 +#define VECT_TPU2_TGI2A 151 +#define VECT_TPU2_TGI2B 152 +#define VECT_TPU2_TCI2V 153 +#define VECT_TPU2_TCI2U 154 +#define VECT_TPU3_TGI3A 155 +#define VECT_TPU3_TGI3B 156 +#define VECT_TPU3_TGI3C 157 +#define VECT_TPU3_TGI3D 158 +#define VECT_TPU3_TCI3V 159 +#define VECT_TPU4_TGI4A 160 +#define VECT_TPU4_TGI4B 161 +#define VECT_TPU4_TCI4V 162 +#define VECT_TPU4_TCI4U 163 +#define VECT_TPU5_TGI5A 164 +#define VECT_TPU5_TGI5B 165 +#define VECT_TPU5_TCI5V 166 +#define VECT_TPU5_TCI5U 167 +#define VECT_POE_OEI1 170 +#define VECT_POE_OEI2 171 +#define VECT_TMR0_CMIA0 174 +#define VECT_TMR0_CMIB0 175 +#define VECT_TMR0_OVI0 176 +#define VECT_TMR1_CMIA1 177 +#define VECT_TMR1_CMIB1 178 +#define VECT_TMR1_OVI1 179 +#define VECT_TMR2_CMIA2 180 +#define VECT_TMR2_CMIB2 181 +#define VECT_TMR2_OVI2 182 +#define VECT_TMR3_CMIA3 183 +#define VECT_TMR3_CMIB3 184 +#define VECT_TMR3_OVI3 185 +#define VECT_DMAC_DMAC0I 198 +#define VECT_DMAC_DMAC1I 199 +#define VECT_DMAC_DMAC2I 200 +#define VECT_DMAC_DMAC3I 201 +#define VECT_SCI0_ERI0 214 +#define VECT_SCI0_RXI0 215 +#define VECT_SCI0_TXI0 216 +#define VECT_SCI0_TEI0 217 +#define VECT_SCI1_ERI1 218 +#define VECT_SCI1_RXI1 219 +#define VECT_SCI1_TXI1 220 +#define VECT_SCI1_TEI1 221 +#define VECT_SCI5_ERI5 222 +#define VECT_SCI5_RXI5 223 +#define VECT_SCI5_TXI5 224 +#define VECT_SCI5_TEI5 225 +#define VECT_SCI6_ERI6 226 +#define VECT_SCI6_RXI6 227 +#define VECT_SCI6_TXI6 228 +#define VECT_SCI6_TEI6 229 +#define VECT_SCI8_ERI8 230 +#define VECT_SCI8_RXI8 231 +#define VECT_SCI8_TXI8 232 +#define VECT_SCI8_TEI8 233 +#define VECT_SCI9_ERI9 234 +#define VECT_SCI9_RXI9 235 +#define VECT_SCI9_TXI9 236 +#define VECT_SCI9_TEI9 237 +#define VECT_SCI12_ERI12 238 +#define VECT_SCI12_RXI12 239 +#define VECT_SCI12_TXI12 240 +#define VECT_SCI12_TEI12 241 +#define VECT_SCI12_SCIX0 242 +#define VECT_SCI12_SCIX1 243 +#define VECT_SCI12_SCIX2 244 +#define VECT_SCI12_SCIX3 245 +#define VECT_RIIC0_EEI0 246 +#define VECT_RIIC0_RXI0 247 +#define VECT_RIIC0_TXI0 248 +#define VECT_RIIC0_TEI0 249 + +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_CMPB SYSTEM.MSTPCRB.BIT.MSTPB10 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_RSCAN SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_RSCAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_IRDA SYSTEM.MSTPCRC.BIT.MSTPC20 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_SDHI SYSTEM.MSTPCRD.BIT.MSTPD19 +#define MSTP_SSI0 SYSTEM.MSTPCRD.BIT.MSTPD15 +#define MSTP_CTSU SYSTEM.MSTPCRD.BIT.MSTPD10 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define BSC (*(volatile struct st_bsc __evenaccess *)0x81300) +#define CAC (*(volatile struct st_cac __evenaccess *)0x8B000) +#define CMPB (*(volatile struct st_cmpb __evenaccess *)0x8C580) +#define CMT (*(volatile struct st_cmt __evenaccess *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 __evenaccess *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 __evenaccess *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 __evenaccess *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 __evenaccess *)0x88018) +#define CRC (*(volatile struct st_crc __evenaccess *)0x88280) +#define CTSU (*(volatile struct st_ctsu __evenaccess *)0xA0900) +#define DA (*(volatile struct st_da __evenaccess *)0x88040) +#define DMAC (*(volatile struct st_dmac __evenaccess *)0x82200) +#define DMAC0 (*(volatile struct st_dmac0 __evenaccess *)0x82000) +#define DMAC1 (*(volatile struct st_dmac1 __evenaccess *)0x82040) +#define DMAC2 (*(volatile struct st_dmac1 __evenaccess *)0x82080) +#define DMAC3 (*(volatile struct st_dmac1 __evenaccess *)0x820C0) +#define DOC (*(volatile struct st_doc __evenaccess *)0x8B080) +#define DTC (*(volatile struct st_dtc __evenaccess *)0x82400) +#define ELC (*(volatile struct st_elc __evenaccess *)0x8B100) +#define FLASH (*(volatile struct st_flash __evenaccess *)0x7FC090) +#define FLASHCONST (*(volatile struct st_flashconst __evenaccess *)0x7FC350) +#define ICU (*(volatile struct st_icu __evenaccess *)0x87000) +#define IRDA (*(volatile struct st_irda __evenaccess *)0x88410) +#define IWDT (*(volatile struct st_iwdt __evenaccess *)0x88030) +#define LPT (*(volatile struct st_lpt __evenaccess *)0x800B0) +#define MPC (*(volatile struct st_mpc __evenaccess *)0x8C100) +#define MPU (*(volatile struct st_mpu __evenaccess *)0x86400) +#define MTU (*(volatile struct st_mtu __evenaccess *)0xD0A0A) +#define MTU0 (*(volatile struct st_mtu0 __evenaccess *)0xD0A90) +#define MTU1 (*(volatile struct st_mtu1 __evenaccess *)0xD0A90) +#define MTU2 (*(volatile struct st_mtu2 __evenaccess *)0xD0A92) +#define MTU3 (*(volatile struct st_mtu3 __evenaccess *)0xD0A00) +#define MTU4 (*(volatile struct st_mtu4 __evenaccess *)0xD0A00) +#define MTU5 (*(volatile struct st_mtu5 __evenaccess *)0xD0A94) +#define POE (*(volatile struct st_poe __evenaccess *)0x88900) +#define PORT (*(volatile struct st_port __evenaccess *)0x8C120) +#define PORT0 (*(volatile struct st_port0 __evenaccess *)0x8C000) +#define PORT1 (*(volatile struct st_port1 __evenaccess *)0x8C001) +#define PORT2 (*(volatile struct st_port2 __evenaccess *)0x8C002) +#define PORT3 (*(volatile struct st_port3 __evenaccess *)0x8C003) +#define PORT4 (*(volatile struct st_port4 __evenaccess *)0x8C004) +#define PORT5 (*(volatile struct st_port5 __evenaccess *)0x8C005) +#define PORTA (*(volatile struct st_porta __evenaccess *)0x8C00A) +#define PORTB (*(volatile struct st_portb __evenaccess *)0x8C00B) +#define PORTC (*(volatile struct st_portc __evenaccess *)0x8C00C) +#define PORTD (*(volatile struct st_portd __evenaccess *)0x8C00D) +#define PORTE (*(volatile struct st_porte __evenaccess *)0x8C00E) +#define PORTH (*(volatile struct st_porth __evenaccess *)0x8C011) +#define PORTJ (*(volatile struct st_portj __evenaccess *)0x8C012) +#define RIIC0 (*(volatile struct st_riic __evenaccess *)0x88300) +#define RSCAN (*(volatile struct st_rscan __evenaccess *)0xA8322) +#define RSCAN0 (*(volatile struct st_rscan0 __evenaccess *)0xA8300) +#define RSPI0 (*(volatile struct st_rspi __evenaccess *)0x88380) +#define RTC (*(volatile struct st_rtc __evenaccess *)0x8C400) +#define S12AD (*(volatile struct st_s12ad __evenaccess *)0x89000) +#define SCI0 (*(volatile struct st_sci0 __evenaccess *)0x8A000) +#define SCI1 (*(volatile struct st_sci0 __evenaccess *)0x8A020) +#define SCI5 (*(volatile struct st_sci0 __evenaccess *)0x8A0A0) +#define SCI6 (*(volatile struct st_sci0 __evenaccess *)0x8A0C0) +#define SCI8 (*(volatile struct st_sci0 __evenaccess *)0x8A100) +#define SCI9 (*(volatile struct st_sci0 __evenaccess *)0x8A120) +#define SCI12 (*(volatile struct st_sci12 __evenaccess *)0x8B300) +#define SDHI (*(volatile struct st_sdhi __evenaccess *)0x8AC00) +#define SMCI0 (*(volatile struct st_smci __evenaccess *)0x8A000) +#define SMCI1 (*(volatile struct st_smci __evenaccess *)0x8A020) +#define SMCI2 (*(volatile struct st_smci __evenaccess *)0x8A040) +#define SMCI3 (*(volatile struct st_smci __evenaccess *)0x8A060) +#define SMCI4 (*(volatile struct st_smci __evenaccess *)0x8A080) +#define SMCI5 (*(volatile struct st_smci __evenaccess *)0x8A0A0) +#define SMCI6 (*(volatile struct st_smci __evenaccess *)0x8A0C0) +#define SMCI7 (*(volatile struct st_smci __evenaccess *)0x8A0E0) +#define SMCI8 (*(volatile struct st_smci __evenaccess *)0x8A100) +#define SMCI9 (*(volatile struct st_smci __evenaccess *)0x8A120) +#define SMCI10 (*(volatile struct st_smci __evenaccess *)0x8A140) +#define SMCI11 (*(volatile struct st_smci __evenaccess *)0x8A150) +#define SMCI12 (*(volatile struct st_smci __evenaccess *)0x8B300) +#define SSI0 (*(volatile struct st_ssi __evenaccess *)0x8A500) +#define SYSTEM (*(volatile struct st_system __evenaccess *)0x80000) +#define TEMPSCONST (*(volatile struct st_tempsconst __evenaccess *)0x7FC0A0) +#define TMR0 (*(volatile struct st_tmr0 __evenaccess *)0x88200) +#define TMR1 (*(volatile struct st_tmr1 __evenaccess *)0x88201) +#define TMR2 (*(volatile struct st_tmr0 __evenaccess *)0x88210) +#define TMR3 (*(volatile struct st_tmr1 __evenaccess *)0x88211) +#define TMR01 (*(volatile struct st_tmr01 __evenaccess *)0x88204) +#define TMR23 (*(volatile struct st_tmr01 __evenaccess *)0x88214) +#define TPU (*(volatile struct st_tpu __evenaccess *)0x88100) +#define TPU0 (*(volatile struct st_tpu0 __evenaccess *)0x88108) +#define TPU1 (*(volatile struct st_tpu1 __evenaccess *)0x88108) +#define TPU2 (*(volatile struct st_tpu2 __evenaccess *)0x8810A) +#define TPU3 (*(volatile struct st_tpu3 __evenaccess *)0x8810A) +#define TPU4 (*(volatile struct st_tpu4 __evenaccess *)0x8810C) +#define TPU5 (*(volatile struct st_tpu5 __evenaccess *)0x8810C) +#define USB0 (*(volatile struct st_usb0 __evenaccess *)0xA0000) +#define WDT (*(volatile struct st_wdt __evenaccess *)0x88020) +#pragma bit_order +#pragma packoption +#endif diff --git a/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/main.c b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/main.c new file mode 100644 index 000000000..409c03775 --- /dev/null +++ b/FreeRTOS/Demo/RX200_RX231-RSK_Renesas_e2studio/src/main.c @@ -0,0 +1,251 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup, standard FreeRTOS hook functions, and the ISR hander called + * by the RTOS after interrupt entry (including nesting) has been taken care of. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +/* Start user code. Do not edit comment generated here */ +uint16_t usProtectDummy = ( uint16_t ) ( SYSTEM.PRCR.WORD & 0x000FU ); + + /* Disable protect bit */ + SYSTEM.PRCR.WORD = 0xA50FU; + + SYSTEM.VBATTCR.BYTE = 0x81U; + + /* Restore the previous state of the protect register */ + SYSTEM.PRCR.WORD = ( uint16_t )( 0xA500U | usProtectDummy ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + extern void vFullDemoTickHook( void ); + + vFullDemoTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* The RX port uses this callback function to configure its tick interrupt. +This allows the application to choose the tick interrupt source. */ +void vApplicationSetupTimerInterrupt( void ) +{ +const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL; + + /* Disable register write protection. */ + SYSTEM.PRCR.WORD = ulEnableRegisterWrite; + + /* Enable compare match timer 0. */ + MSTP( CMT0 ) = 0; + + /* Interrupt on compare match. */ + CMT0.CMCR.BIT.CMIE = 1; + + /* Set the compare match value. */ + CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); + + /* Divide the PCLK by 8. */ + CMT0.CMCR.BIT.CKS = 0; + + /* Enable the interrupt... */ + _IEN( _CMT0_CMI0 ) = 1; + + /* ...and set its priority to the application defined kernel priority. */ + _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the timer. */ + CMT.CMSTR0.BIT.STR0 = 1; + + /* Reneable register protection. */ + SYSTEM.PRCR.WORD = ulDisableRegisterWrite; +} + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.cproject b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.cproject index bc67806b2..592b8164c 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.cproject +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.cproject @@ -120,7 +120,7 @@ - + @@ -134,5 +134,9 @@ - + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.project b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.project index e1a619318..d82dcb065 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.project +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.project @@ -42,6 +42,15 @@ + + 1442924121510 + + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-RTOSDemo + + 1442756186478 src/FreeRTOS_Source @@ -51,6 +60,15 @@ 1.0-name-matches-false-false-croutine.c + + 1442924751731 + src/Full_Demo + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*_IAR.* + + 1442753620317 src/FreeRTOS_Source/portable diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/language.settings.xml b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/language.settings.xml index ec00737f5..809fddcfc 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/language.settings.xml +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/.settings/language.settings.xml @@ -3,7 +3,7 @@ - + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewd new file mode 100644 index 000000000..3ef1570c0 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewd @@ -0,0 +1,771 @@ + + + + 2 + + Debug + + RX + + 1 + + C-SPY + 3 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RXEMUE20 + 4 + + 4 + 1 + 1 + + + + + + + + + + + + + + + RXE2LITE + 1 + + 0 + 1 + 1 + + + + + + + + + + + + + + + RXJLINK + 4 + + 5 + 1 + 1 + + + + + + + + + + + + + + + + + + SIMRX + 1 + + 1 + 1 + 1 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + Release + + RX + + 0 + + C-SPY + 3 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RXEMUE20 + 4 + + 4 + 1 + 0 + + + + + + + + + + + + + + + RXE2LITE + 1 + + 0 + 1 + 0 + + + + + + + + + + + + + + + RXJLINK + 4 + + 5 + 1 + 0 + + + + + + + + + + + + + + + + + + SIMRX + 1 + + 1 + 1 + 0 + + + + + + + + + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Quadros\Quadros_EWB7_Plugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXRxPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewp b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..9ea5290e2 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.ewp @@ -0,0 +1,2050 @@ + + + + 2 + + Debug + + RX + + 1 + + General + 6 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRX + 8 + + 17 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARX + 6 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 1 + + 0 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 4 + + 6 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 1 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + RX + + 0 + + General + 6 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCRX + 8 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARX + 6 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 1 + + 0 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 4 + + 6 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 1 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Blinky_Demo + + $PROJ_DIR$\src\Blinky_Demo\main_blinky.c + + + + cg_src + + $PROJ_DIR$\src\cg_src\r_cg_cgc.c + + + $PROJ_DIR$\src\cg_src\r_cg_hardware_setup.c + + + $PROJ_DIR$\src\cg_src\r_cg_icu.c + + + $PROJ_DIR$\src\cg_src\r_cg_port.c + + + $PROJ_DIR$\src\cg_src\r_cg_sci.c + + + $PROJ_DIR$\src\cg_src\r_cg_sci_user_iar.c + + + + FreeRTOS_Source + + portable + + MemMang + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + + + + $PROJ_DIR$\..\..\Source\portable\IAR\RXv2\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\RXv2\port_asm.s + + + + $PROJ_DIR$\..\..\Source\event_groups.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\Source\timers.c + + + + Full_Demo + + Standard_Demo_Tasks + + $PROJ_DIR$\..\Common\Minimal\BlockQ.c + + + $PROJ_DIR$\..\Common\Minimal\blocktim.c + + + $PROJ_DIR$\..\Common\Minimal\countsem.c + + + $PROJ_DIR$\..\Common\Minimal\death.c + + + $PROJ_DIR$\..\Common\Minimal\dynamic.c + + + $PROJ_DIR$\..\Common\Minimal\EventGroupsDemo.c + + + $PROJ_DIR$\..\Common\Minimal\flop.c + + + $PROJ_DIR$\..\Common\Minimal\GenQTest.c + + + $PROJ_DIR$\..\Common\Minimal\IntQueue.c + + + $PROJ_DIR$\..\Common\Minimal\IntSemTest.c + + + $PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c + + + $PROJ_DIR$\..\Common\Minimal\recmutex.c + + + $PROJ_DIR$\..\Common\Minimal\semtest.c + + + $PROJ_DIR$\..\Common\Minimal\TaskNotify.c + + + $PROJ_DIR$\..\Common\Minimal\TimerDemo.c + + + + $PROJ_DIR$\src\Full_Demo\IntQueueTimer.c + + + $PROJ_DIR$\src\Full_Demo\main_full.c + + + $PROJ_DIR$\src\Full_Demo\RegTest_IAR.s + + + + $PROJ_DIR$\src\FreeRTOSConfig.h + + + $PROJ_DIR$\src\main.c + + + $PROJ_DIR$\src\rskrx71mdef.h + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.eww b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo/.settings/CodeGenerator/cgprojectDatas.datas b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/RTOSDemo/.settings/CodeGenerator/cgprojectDatas.datas deleted file mode 100644 index e69de29bb..000000000 diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat new file mode 100644 index 000000000..ac83a6234 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.cspy.bat @@ -0,0 +1,40 @@ +@REM This batch file has been generated by the IAR Embedded Workbench +@REM C-SPY Debugger, as an aid to preparing a command line for running +@REM the cspybat command line utility using the appropriate settings. +@REM +@REM Note that this file is generated every time a new debug session +@REM is initialized, so you may want to move or rename the file before +@REM making changes. +@REM +@REM You can launch cspybat by typing the name of this batch file followed +@REM by the name of the debug file (usually an ELF/DWARF or UBROF file). +@REM +@REM Read about available command line parameters in the C-SPY Debugging +@REM Guide. Hints about additional command line parameters that may be +@REM useful in specific cases: +@REM --download_only Downloads a code image without starting a debug +@REM session afterwards. +@REM --silent Omits the sign-on message. +@REM --timeout Limits the maximum allowed execution time. +@REM + + +@echo off + +if not "%1" == "" goto debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +goto end + +:debugFile + +@echo on + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_RSK_GCC_e2studio_IAR\settings\RTOSDemo.Debug.driver.xcl" + +@echo off +:end \ No newline at end of file diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl new file mode 100644 index 000000000..1830f5d18 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.driver.xcl @@ -0,0 +1,37 @@ + -B + +"-p" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\config\debugger\ior5f571ml.ddf" + +"--endian" + +"l" + +"--double" + +"32" + +"--core" + +"rxv2" + +"--int" + +"32" + +"-d" + +"emue20" + +"--drv_mode" + +"debugging" + +"--drv_communication" + +"USB" + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl new file mode 100644 index 000000000..0ada92176 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.Debug.general.xcl @@ -0,0 +1,11 @@ +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxproc.dll" + +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxe1e20.dll" + +"C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\RX700_RX71M_RSK_GCC_e2studio_IAR\Debug\Exe\RTOSDemo.out" + +--plugin "C:\DevTools\IAR Systems\Embedded Workbench 7.2\rx\bin\rxbat.dll" + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt new file mode 100644 index 000000000..4f7e51010 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dbgdt @@ -0,0 +1,244 @@ + + + + + + + 20 + 1622 + + + 20 + 1216 + 324 + 81 + + + + 255 + 27 + 27 + 27 + + + + + Disassembly + _I0 + + + 500 + 20 + + + + 2 + 0 + 0 + + + 1 + 1 + + + + 2 + 0 + 0 + + + + + + + + + TabID-6594-3339 + Debug Log + Debug-Log + + + + TabID-6072-3348 + Build + Build + + + + 0 + + + + + TabID-17343-3342 + Workspace + Workspace + + + RTOSDemo + + + + + 0 + + + + + + TextEditor + $WS_DIR$\src\main.c + 0 + 0 + 0 + 0 + 0 + 66 + 5312 + 5312 + + + TextEditor + $WS_DIR$\src\Full_Demo\RegTest_IAR.s + 0 + 0 + 0 + 0 + 0 + 144 + 5881 + 5881 + + + TextEditor + $WS_DIR$\..\Common\Minimal\flop.c + 0 + 0 + 0 + 0 + 0 + 126 + 6956 + 6956 + + + TextEditor + $WS_DIR$\..\Common\Minimal\TimerDemo.c + 0 + 0 + 0 + 0 + 0 + 242 + 12612 + 12612 + + + TextEditor + $WS_DIR$\..\Common\Minimal\IntQueue.c + 0 + 0 + 0 + 0 + 0 + 381 + 0 + 0 + + + TextEditor + $WS_DIR$\src\Full_Demo\IntQueueTimer.c + 0 + 0 + 0 + 0 + 0 + 154 + 7349 + 7349 + + 5 + + 0 + + + 1000000 + 1000000 + + + 1 + + + + + + + iaridepm.enu1 + + + + + + + debuggergui.enu1 + + + + + + + + + + -2 + -2 + 718 + 329 + -2 + -2 + 200 + 200 + 119048 + 203252 + 197024 + 731707 + + + + + + + + + + + + + + + + -2 + -2 + 198 + 1682 + -2 + -2 + 1684 + 200 + 1002381 + 203252 + 119048 + 203252 + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni new file mode 100644 index 000000000..c48d2fd74 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.dni @@ -0,0 +1,250 @@ +[DebugChecksum] +Checksum=-126027898 +[CodeCoverage] +Enabled=_ 0 +[Stack] +FillEnabled=0 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnLogOnly=1 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[CallStack] +ShowArgs=0 +[Disassembly] +MixedMode=1 +[E1/E20] +BlockBits=15 +B0=1,0 +B1=1,1024 +B2=1,2048 +B3=1,3072 +StartEnabled=0 +StartSymbol= +StopEnabled=0 +StopSymbol= +RecordingCondition=0 +TraceMode=0 +TraceOutput=0 +TraceType=0 +TraceCapacity=0 +TraceRestart=0 +TraceTimeStamp=0 +TraceTimestampDivision=0 +TraceDataTransfer=1 +TraceStackOperation=1 +TraceStringOperation=1 +TraceArithmeticalOperation=1 +TraceLogicalOperation=1 +TraceBitOperation=1 +TraceFPU=1 +TraceException=1 +OperatingFrequency=0.000000 +PerfEnabled=0 +PerfCondition=0,0 +PerfDisplayTime=0,0 +PerfOnlyOnce=0,0 +PerfUse64Bit=0 +ChipName=R5F571ML +PinMode=0 +RegMode=0 +Endian=0 +ExtMemBlockNum=55 +ExtMemEndian_000=0 +ExtMemCondAccess_000=0 +ExtMemEndian_001=0 +ExtMemCondAccess_001=0 +ExtMemEndian_002=0 +ExtMemCondAccess_002=0 +ExtMemEndian_003=0 +ExtMemCondAccess_003=0 +ExtMemEndian_004=0 +ExtMemCondAccess_004=0 +ExtMemEndian_005=0 +ExtMemCondAccess_005=0 +ExtMemEndian_006=0 +ExtMemCondAccess_006=0 +ExtMemEndian_007=0 +ExtMemCondAccess_007=0 +ExtMemEndian_008=0 +ExtMemCondAccess_008=0 +ExtMemEndian_009=0 +ExtMemCondAccess_009=0 +ExtMemEndian_010=0 +ExtMemCondAccess_010=0 +ExtMemEndian_011=0 +ExtMemCondAccess_011=0 +ExtMemEndian_012=0 +ExtMemCondAccess_012=0 +ExtMemEndian_013=0 +ExtMemCondAccess_013=0 +ExtMemEndian_014=0 +ExtMemCondAccess_014=0 +ExtMemEndian_015=0 +ExtMemCondAccess_015=0 +ExtMemEndian_016=0 +ExtMemCondAccess_016=0 +ExtMemEndian_017=0 +ExtMemCondAccess_017=0 +ExtMemEndian_018=0 +ExtMemCondAccess_018=0 +ExtMemEndian_019=0 +ExtMemCondAccess_019=0 +ExtMemEndian_020=0 +ExtMemCondAccess_020=0 +ExtMemEndian_021=0 +ExtMemCondAccess_021=0 +ExtMemEndian_022=0 +ExtMemCondAccess_022=0 +ExtMemEndian_023=0 +ExtMemCondAccess_023=0 +ExtMemEndian_024=0 +ExtMemCondAccess_024=0 +ExtMemEndian_025=0 +ExtMemCondAccess_025=0 +ExtMemEndian_026=0 +ExtMemCondAccess_026=0 +ExtMemEndian_027=0 +ExtMemCondAccess_027=0 +ExtMemEndian_028=0 +ExtMemCondAccess_028=0 +ExtMemEndian_029=0 +ExtMemCondAccess_029=0 +ExtMemEndian_030=0 +ExtMemCondAccess_030=0 +ExtMemEndian_031=0 +ExtMemCondAccess_031=0 +ExtMemEndian_032=0 +ExtMemCondAccess_032=0 +ExtMemEndian_033=0 +ExtMemCondAccess_033=0 +ExtMemEndian_034=0 +ExtMemCondAccess_034=0 +ExtMemEndian_035=0 +ExtMemCondAccess_035=0 +ExtMemEndian_036=0 +ExtMemCondAccess_036=0 +ExtMemEndian_037=0 +ExtMemCondAccess_037=0 +ExtMemEndian_038=0 +ExtMemCondAccess_038=0 +ExtMemEndian_039=0 +ExtMemCondAccess_039=0 +ExtMemEndian_040=0 +ExtMemCondAccess_040=0 +ExtMemEndian_041=0 +ExtMemCondAccess_041=0 +ExtMemEndian_042=0 +ExtMemCondAccess_042=0 +ExtMemEndian_043=0 +ExtMemCondAccess_043=0 +ExtMemEndian_044=0 +ExtMemCondAccess_044=0 +ExtMemEndian_045=0 +ExtMemCondAccess_045=0 +ExtMemEndian_046=0 +ExtMemCondAccess_046=0 +ExtMemEndian_047=0 +ExtMemCondAccess_047=0 +ExtMemEndian_048=0 +ExtMemCondAccess_048=0 +ExtMemEndian_049=0 +ExtMemCondAccess_049=0 +ExtMemEndian_050=0 +ExtMemCondAccess_050=0 +ExtMemEndian_051=0 +ExtMemCondAccess_051=0 +ExtMemEndian_052=0 +ExtMemCondAccess_052=0 +ExtMemEndian_053=0 +ExtMemCondAccess_053=0 +ExtMemEndian_054=0 +ExtMemCondAccess_054=0 +InputClock=25.000000 +ICLK=240.000000 +AllowClkSrcChange=0 +WorkRamStart=4096 +ComunicationSelect=0 +UseExtal=1 +JtagClock=10 +FINE=2000000 +EraseFlash=1,0 +DebugFlags=0,0 +EmulatorMode=0 +PowerTargetFromEmulator=1 +Voltage=0 +UseExtFlashFile_0=0 +ExtFlashFile_0= +EraseExtFlashBeforeDownload_0=0 +UseExtFlashFile_1=0 +ExtFlashFile_1= +EraseExtFlashBeforeDownload_1=0 +UseExtFlashFile_2=0 +ExtFlashFile_2= +EraseExtFlashBeforeDownload_2=0 +UseExtFlashFile_3=0 +ExtFlashFile_3= +EraseExtFlashBeforeDownload_3=0 +NeedInitExtMem=0 +NeedInit=0 +[CallStackLog] +Enabled=0 +[CallStackStripe] +ShowTiming=1 +[InterruptLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +SumSortOrder=0 +[DataLog] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +SumEnabled=0 +ShowTimeSum=1 +[Breakpoints2] +Count=0 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +Base=0 +UseAuto=0 +TypeViolation=1 +UnspecRange=1 +ActionState=1 +[Simulator] +Freq=98000000 +[DataSample] +LogEnabled=0 +GraphEnabled=0 +ShowTimeLog=1 +[DriverProfiling] +Enabled=0 +Mode=1 +Graph=0 +Symbiont=0 +Exclusions= +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" +[Breakpoints] +Count=0 +[Monitor Execution] +Leave target running=0 +Release target=0 +[Trace1] +Enabled=0 +ShowSource=1 +[Aliases] +Count=0 +SuppressDialog=0 diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt new file mode 100644 index 000000000..d82098c0f --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wsdt @@ -0,0 +1,77 @@ + + + + + + RTOSDemo/Debug + + + + + + + + + 310272727 + + + + + + + 20121632481 + + + 20 + 1622 + + + + + + + + + TabID-13537-752 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Blinky_DemoRTOSDemo/FreeRTOS_SourceRTOSDemo/FreeRTOS_Source/portableRTOSDemo/Full_DemoRTOSDemo/Full_Demo/Standard_Demo_TasksRTOSDemo/cg_src + + + + 0 + + + TabID-29660-3316 + Build + Build + + + + TabID-19897-23353 + Debug Log + Debug-Log + + + + + 0 + + + + + + TextEditor$WS_DIR$\src\main.c000006653125312TextEditor$WS_DIR$\src\Full_Demo\RegTest_IAR.s0000014458815881TextEditor$WS_DIR$\..\Common\Minimal\flop.c0000012669566956TextEditor$WS_DIR$\..\Common\Minimal\TimerDemo.c000002421261212612TextEditor$WS_DIR$\..\Common\Minimal\IntQueue.c0000038100TextEditor$WS_DIR$\src\Full_Demo\IntQueueTimer.c0000014273497349TextEditor$WS_DIR$\..\..\Source\portable\IAR\RXv2\port.c00000614241424160100000010000001 + + + + + + + iaridepm.enu1-2-2742400-2-2200200119048203252239286756098-2-21981682-2-216842001002381203252119048203252 + + + + diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos new file mode 100644 index 000000000..ecdc2c482 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/settings/RTOSDemo.wspos @@ -0,0 +1,2 @@ +[MainWindow] +WindowPlacement=_ 519 0 1619 872 3 diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h index 75141fdca..5faf0cea9 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/FreeRTOSConfig.h @@ -71,7 +71,14 @@ #define FREERTOS_CONFIG_H /* Renesas hardware definition header. */ -#include "iodefine.h" +#ifdef __ICCRX__ + #include + #include +#endif + +#ifdef __GNUC__ + #include "iodefine.h" +#endif /*----------------------------------------------------------- * Application specific definitions. @@ -128,7 +135,7 @@ kernel is doing. */ /* The peripheral used to generate the tick interrupt is configured as part of the application code. This constant should be set to the vector number of the peripheral chosen. As supplied this is CMT0. */ -#define configTICK_VECTOR _CMT0_CMI0 +#define configTICK_VECTOR 28 /*vect _CMT0_CMI0*/ /* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c index 0da468ed3..bd4d82417 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/IntQueueTimer.c @@ -68,9 +68,9 @@ */ /* - * This file contains the non-portable and therefore RX62N specific parts of - * the IntQueue standard demo task - namely the configuration of the timers - * that generate the interrupts and the interrupt entry points. + * This file contains the non-portable and therefore RX specific parts of the + * IntQueue standard demo task - namely the configuration of the timers that + * generate the interrupts and the interrupt entry points. */ /* Scheduler includes. */ @@ -81,23 +81,8 @@ #include "IntQueueTimer.h" #include "IntQueue.h" -/* Hardware specifics. */ -#include "iodefine.h" - -#define IPR_PERIB_INTB128 128 -#define IPR_PERIB_INTB129 129 -#define IER_PERIB_INTB128 0x10 -#define IER_PERIB_INTB129 0x10 -#define IEN_PERIB_INTB128 IEN0 -#define IEN_PERIB_INTB129 IEN1 -#define IR_PERIB_INTB128 128 -#define IR_PERIB_INTB129 129 - -void vIntQTimerISR0( void ) __attribute__ ((interrupt)); -void vIntQTimerISR1( void ) __attribute__ ((interrupt)); - #define tmrTIMER_0_1_FREQUENCY ( 2000UL ) -#define tmrTIMER_2_3_FREQUENCY ( 2001UL ) +#define tmrTIMER_2_3_FREQUENCY ( 2301UL ) void vInitialiseTimerForIntQueueTest( void ) { @@ -107,7 +92,7 @@ void vInitialiseTimerForIntQueueTest( void ) /* Give write access. */ SYSTEM.PRCR.WORD = 0xa502; - /* Cascade two 8bit timer channels to generate the interrupts. + /* Cascade two 8bit timer channels to generate the interrupts. 8bit timer unit 1 (TMR0 and TMR1) and 8bit timer unit 2 (TMR2 and TMR3 are utilised for this test. */ @@ -130,11 +115,11 @@ void vInitialiseTimerForIntQueueTest( void ) /* 16 bit operation ( count from timer 1,2 ). */ TMR0.TCCR.BIT.CSS = 3; TMR2.TCCR.BIT.CSS = 3; - + /* Use PCLK as the input. */ TMR1.TCCR.BIT.CSS = 1; TMR3.TCCR.BIT.CSS = 1; - + /* Divide PCLK by 8. */ TMR1.TCCR.BIT.CKS = 2; TMR3.TCCR.BIT.CKS = 2; @@ -143,11 +128,9 @@ void vInitialiseTimerForIntQueueTest( void ) TMR0.TCR.BIT.CMIEA = 1; TMR2.TCR.BIT.CMIEA = 1; - /* Map TMR0 CMIA0 interrupt to vector slot B number 128 and set - priority above the kernel's priority, but below the max syscall - priority. */ - ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */ - IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; + /* Set priority and enable interrupt. */ + ICU.SLIBXR128.BYTE = 3; /* Three is TMR0 compare match A. */ + IPR( PERIB, INTB128 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 1; IEN( PERIB, INTB128 ) = 1; /* Ensure that the flag is set to 0, otherwise the interrupt will not be @@ -155,8 +138,8 @@ void vInitialiseTimerForIntQueueTest( void ) IR( PERIB, INTB128 ) = 0; /* Do the same for TMR2, but to vector 129. */ - ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */ - IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; + ICU.SLIBXR129.BYTE = 9; /* Nine is TMR2 compare match A. */ + IPR( PERIB, INTB129 ) = configMAX_SYSCALL_INTERRUPT_PRIORITY - 2; IEN( PERIB, INTB129 ) = 1; IR( PERIB, INTB129 ) = 0; } @@ -164,25 +147,49 @@ void vInitialiseTimerForIntQueueTest( void ) } /*-----------------------------------------------------------*/ -/* On vector 128. */ -void vIntQTimerISR0( void ) -{ - /* Enable interrupts to allow interrupt nesting. */ - __asm volatile( "setpsw i" ); +#ifdef __GNUC__ + + void vIntQTimerISR0( void ) __attribute__ ((interrupt)); + void vIntQTimerISR1( void ) __attribute__ ((interrupt)); + + void vIntQTimerISR0( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xFirstTimerHandler() ); + } + /*-----------------------------------------------------------*/ + + void vIntQTimerISR1( void ) + { + /* Enable interrupts to allow interrupt nesting. */ + __asm volatile( "setpsw i" ); + + portYIELD_FROM_ISR( xSecondTimerHandler() ); + } +#endif /* __GNUC__ */ +/*-----------------------------------------------------------*/ + +#ifdef __ICCRX__ + +#pragma vector = VECT_PERIB_INTB128 +__interrupt void vT0_1InterruptHandler( void ) +{ + __enable_interrupt(); portYIELD_FROM_ISR( xFirstTimerHandler() ); } /*-----------------------------------------------------------*/ -/* On vector 129. */ -void vIntQTimerISR1( void ) +#pragma vector = VECT_PERIB_INTB129 +__interrupt void vT2_3InterruptHandler( void ) { - /* Enable interrupts to allow interrupt nesting. */ - __asm volatile( "setpsw i" ); - + __enable_interrupt(); portYIELD_FROM_ISR( xSecondTimerHandler() ); } +#endif /* __ICCRX__ */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S deleted file mode 100644 index 310079738..000000000 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest.S +++ /dev/null @@ -1,302 +0,0 @@ -;/* -; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. -; All rights reserved -; -; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. -; -; *************************************************************************** -; * * -; * FreeRTOS provides completely free yet professionally developed, * -; * robust, strictly quality controlled, supported, and cross * -; * platform software that has become a de facto standard. * -; * * -; * Help yourself get started quickly and support the FreeRTOS * -; * project by purchasing a FreeRTOS tutorial book, reference * -; * manual, or both from: http://www.FreeRTOS.org/Documentation * -; * * -; * Thank you! * -; * * -; *************************************************************************** -; -; This file is part of the FreeRTOS distribution. -; -; FreeRTOS is free software; you can redistribute it and/or modify it under -; the terms of the GNU General Public License (version 2) as published by the -; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. -; -; >>! NOTE: The modification to the GPL is included to allow you to distribute -; >>! a combined work that includes FreeRTOS without being obliged to provide -; >>! the source code for proprietary components outside of the FreeRTOS -; >>! kernel. -; -; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY -; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS -; FOR A PARTICULAR PURPOSE. Full license text is available from the following -; link: http://www.freertos.org/a00114.html -; -; 1 tab == 4 spaces! -; -; *************************************************************************** -; * * -; * Having a problem? Start by reading the FAQ "My application does * -; * not run, what could be wrong?" * -; * * -; * http://www.FreeRTOS.org/FAQHelp.html * -; * * -; *************************************************************************** -; -; http://www.FreeRTOS.org - Documentation, books, training, latest versions, -; license and Real Time Engineers Ltd. contact details.; -; -; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, -; including FreeRTOS+Trace - an indispensable productivity tool, a DOS -; compatible FAT file system, and our tiny thread aware UDP/IP stack. -; -; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High -; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS -; licenses offer ticketed support, indemnification and middleware. -; -; http://www.SafeRTOS.com - High Integrity Systems also provide a safety -; engineered and independently SIL3 certified version for use in safety and -; mission critical applications that require provable dependability. -; -; 1 tab == 4 spaces! -;*/ - - .global _vRegTest1Implementation - .global _vRegTest2Implementation - - .extern _ulRegTest1LoopCounter - .extern _ulRegTest2LoopCounter - - .text - - -;/* This function is explained in the comments at the top of main.c. */ -_vRegTest1Implementation: - - ;/* Put a known value in the guard byte of the accumulators. */ - MOV.L #10, R1 - MVTACGU R1, A0 - MOV.L #20, R1 - MVTACGU R1, A1 - - ;/* Put a known value in each register. */ - MOV.L #1, R1 - MOV.L #2, R2 - MOV.L #3, R3 - MOV.L #4, R4 - MOV.L #5, R5 - MOV.L #6, R6 - MOV.L #7, R7 - MOV.L #8, R8 - MOV.L #9, R9 - MOV.L #10, R10 - MOV.L #11, R11 - MOV.L #12, R12 - MOV.L #13, R13 - MOV.L #14, R14 - MOV.L #15, R15 - - ;/* Put a known value in the hi and low of the accumulators. */ - MVTACHI R1, A0 - MVTACLO R2, A0 - MVTACHI R3, A1 - MVTACLO R4, A1 - - ;/* Loop, checking each itteration that each register still contains the - ;expected value. */ -TestLoop1: - - ;/* Push the registers that are going to get clobbered. */ - PUSHM R14-R15 - - ;/* Increment the loop counter to show this task is still getting CPU time. */ - MOV.L #_ulRegTest1LoopCounter, R14 - MOV.L [ R14 ], R15 - ADD #1, R15 - MOV.L R15, [ R14 ] - - ;/* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */ - MOV.L #1, R14 - MOV.L #0872E0H, R15 - MOV.B R14, [R15] - NOP - NOP - - ;/* Check accumulators. */ - MVFACHI #0, A0, R15 - CMP #1, R15 - BNE RegTest1Error - MVFACLO #0, A0, R15 - CMP #2, R15 - BNE RegTest1Error - MVFACGU #0, A0, R15 - CMP #10, R15 - BNE RegTest1Error - MVFACHI #0, A1, R15 - CMP #3, R15 - BNE RegTest1Error - MVFACLO #0, A1, R15 - CMP #4, R15 - BNE RegTest1Error - MVFACGU #0, A1, R15 - CMP #20, R15 - BNE RegTest1Error - - ;/* Restore the clobbered registers. */ - POPM R14-R15 - - ;/* Now compare each register to ensure it still contains the value that was - ;set before this loop was entered. */ - CMP #1, R1 - BNE RegTest1Error - CMP #2, R2 - BNE RegTest1Error - CMP #3, R3 - BNE RegTest1Error - CMP #4, R4 - BNE RegTest1Error - CMP #5, R5 - BNE RegTest1Error - CMP #6, R6 - BNE RegTest1Error - CMP #7, R7 - BNE RegTest1Error - CMP #8, R8 - BNE RegTest1Error - CMP #9, R9 - BNE RegTest1Error - CMP #10, R10 - BNE RegTest1Error - CMP #11, R11 - BNE RegTest1Error - CMP #12, R12 - BNE RegTest1Error - CMP #13, R13 - BNE RegTest1Error - CMP #14, R14 - BNE RegTest1Error - CMP #15, R15 - BNE RegTest1Error - - ;/* All comparisons passed, start a new itteratio of this loop. */ - BRA TestLoop1 - -RegTest1Error: - ;/* A compare failed, just loop here so the loop counter stops incrementing - ;- causing the check task to indicate the error. */ - BRA RegTest1Error -;/*-----------------------------------------------------------*/ - -;/* This function is explained in the comments at the top of main.c. */ -_vRegTest2Implementation: - - ;/* Put a known value in the guard byte of the accumulators. */ - MOV.L #1H, R1 - MVTACGU R1, A0 - MOV.L #2H, R1 - MVTACGU R1, A1 - - ;/* Put a known value in each general purpose register. */ - MOV.L #10H, R1 - MOV.L #20H, R2 - MOV.L #30H, R3 - MOV.L #40H, R4 - MOV.L #50H, R5 - MOV.L #60H, R6 - MOV.L #70H, R7 - MOV.L #80H, R8 - MOV.L #90H, R9 - MOV.L #100H, R10 - MOV.L #110H, R11 - MOV.L #120H, R12 - MOV.L #130H, R13 - MOV.L #140H, R14 - MOV.L #150H, R15 - - ;/* Put a known value in the hi and low of the accumulators. */ - MVTACHI R1, A0 - MVTACLO R2, A0 - MVTACHI R3, A1 - MVTACLO R4, A1 - - ;/* Loop, checking each itteration that each register still contains the - ;expected value. */ -TestLoop2: - - ;/* Push the registers that are going to get clobbered. */ - PUSHM R14-R15 - - ;/* Increment the loop counter to show this task is still getting CPU time. */ - MOV.L #_ulRegTest2LoopCounter, R14 - MOV.L [ R14 ], R15 - ADD #1, R15 - MOV.L R15, [ R14 ] - - ;/* Check accumulators. */ - MVFACHI #0, A0, R15 - CMP #10H, R15 - BNE RegTest1Error - MVFACLO #0, A0, R15 - CMP #20H, R15 - BNE RegTest1Error - MVFACGU #0, A0, R15 - CMP #1H, R15 - BNE RegTest1Error - MVFACHI #0, A1, R15 - CMP #30H, R15 - BNE RegTest1Error - MVFACLO #0, A1, R15 - CMP #40H, R15 - BNE RegTest1Error - MVFACGU #0, A1, R15 - CMP #2H, R15 - BNE RegTest1Error - - ;/* Restore the clobbered registers. */ - POPM R14-R15 - - ;/* Now compare each register to ensure it still contains the value that was - ;set before this loop was entered. */ - CMP #10H, R1 - BNE RegTest2Error - CMP #20H, R2 - BNE RegTest2Error - CMP #30H, R3 - BNE RegTest2Error - CMP #40H, R4 - BNE RegTest2Error - CMP #50H, R5 - BNE RegTest2Error - CMP #60H, R6 - BNE RegTest2Error - CMP #70H, R7 - BNE RegTest2Error - CMP #80H, R8 - BNE RegTest2Error - CMP #90H, R9 - BNE RegTest2Error - CMP #100H, R10 - BNE RegTest2Error - CMP #110H, R11 - BNE RegTest2Error - CMP #120H, R12 - BNE RegTest2Error - CMP #130H, R13 - BNE RegTest2Error - CMP #140H, R14 - BNE RegTest2Error - CMP #150H, R15 - BNE RegTest2Error - - ;/* All comparisons passed, start a new itteratio of this loop. */ - BRA TestLoop2 - -RegTest2Error: - ;/* A compare failed, just loop here so the loop counter stops incrementing - ;- causing the check task to indicate the error. */ - BRA RegTest2Error - - - .END diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_GCC.S b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_GCC.S new file mode 100644 index 000000000..310079738 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_GCC.S @@ -0,0 +1,302 @@ +;/* +; FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. +; All rights reserved +; +; VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. +; +; *************************************************************************** +; * * +; * FreeRTOS provides completely free yet professionally developed, * +; * robust, strictly quality controlled, supported, and cross * +; * platform software that has become a de facto standard. * +; * * +; * Help yourself get started quickly and support the FreeRTOS * +; * project by purchasing a FreeRTOS tutorial book, reference * +; * manual, or both from: http://www.FreeRTOS.org/Documentation * +; * * +; * Thank you! * +; * * +; *************************************************************************** +; +; This file is part of the FreeRTOS distribution. +; +; FreeRTOS is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License (version 2) as published by the +; Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. +; +; >>! NOTE: The modification to the GPL is included to allow you to distribute +; >>! a combined work that includes FreeRTOS without being obliged to provide +; >>! the source code for proprietary components outside of the FreeRTOS +; >>! kernel. +; +; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY +; WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS +; FOR A PARTICULAR PURPOSE. Full license text is available from the following +; link: http://www.freertos.org/a00114.html +; +; 1 tab == 4 spaces! +; +; *************************************************************************** +; * * +; * Having a problem? Start by reading the FAQ "My application does * +; * not run, what could be wrong?" * +; * * +; * http://www.FreeRTOS.org/FAQHelp.html * +; * * +; *************************************************************************** +; +; http://www.FreeRTOS.org - Documentation, books, training, latest versions, +; license and Real Time Engineers Ltd. contact details.; +; +; http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, +; including FreeRTOS+Trace - an indispensable productivity tool, a DOS +; compatible FAT file system, and our tiny thread aware UDP/IP stack. +; +; http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High +; Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS +; licenses offer ticketed support, indemnification and middleware. +; +; http://www.SafeRTOS.com - High Integrity Systems also provide a safety +; engineered and independently SIL3 certified version for use in safety and +; mission critical applications that require provable dependability. +; +; 1 tab == 4 spaces! +;*/ + + .global _vRegTest1Implementation + .global _vRegTest2Implementation + + .extern _ulRegTest1LoopCounter + .extern _ulRegTest2LoopCounter + + .text + + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest1Implementation: + + ;/* Put a known value in the guard byte of the accumulators. */ + MOV.L #10, R1 + MVTACGU R1, A0 + MOV.L #20, R1 + MVTACGU R1, A1 + + ;/* Put a known value in each register. */ + MOV.L #1, R1 + MOV.L #2, R2 + MOV.L #3, R3 + MOV.L #4, R4 + MOV.L #5, R5 + MOV.L #6, R6 + MOV.L #7, R7 + MOV.L #8, R8 + MOV.L #9, R9 + MOV.L #10, R10 + MOV.L #11, R11 + MOV.L #12, R12 + MOV.L #13, R13 + MOV.L #14, R14 + MOV.L #15, R15 + + ;/* Put a known value in the hi and low of the accumulators. */ + MVTACHI R1, A0 + MVTACLO R2, A0 + MVTACHI R3, A1 + MVTACLO R4, A1 + + ;/* Loop, checking each itteration that each register still contains the + ;expected value. */ +TestLoop1: + + ;/* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + ;/* Increment the loop counter to show this task is still getting CPU time. */ + MOV.L #_ulRegTest1LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ;/* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */ + MOV.L #1, R14 + MOV.L #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ;/* Check accumulators. */ + MVFACHI #0, A0, R15 + CMP #1, R15 + BNE RegTest1Error + MVFACLO #0, A0, R15 + CMP #2, R15 + BNE RegTest1Error + MVFACGU #0, A0, R15 + CMP #10, R15 + BNE RegTest1Error + MVFACHI #0, A1, R15 + CMP #3, R15 + BNE RegTest1Error + MVFACLO #0, A1, R15 + CMP #4, R15 + BNE RegTest1Error + MVFACGU #0, A1, R15 + CMP #20, R15 + BNE RegTest1Error + + ;/* Restore the clobbered registers. */ + POPM R14-R15 + + ;/* Now compare each register to ensure it still contains the value that was + ;set before this loop was entered. */ + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + ;/* All comparisons passed, start a new itteratio of this loop. */ + BRA TestLoop1 + +RegTest1Error: + ;/* A compare failed, just loop here so the loop counter stops incrementing + ;- causing the check task to indicate the error. */ + BRA RegTest1Error +;/*-----------------------------------------------------------*/ + +;/* This function is explained in the comments at the top of main.c. */ +_vRegTest2Implementation: + + ;/* Put a known value in the guard byte of the accumulators. */ + MOV.L #1H, R1 + MVTACGU R1, A0 + MOV.L #2H, R1 + MVTACGU R1, A1 + + ;/* Put a known value in each general purpose register. */ + MOV.L #10H, R1 + MOV.L #20H, R2 + MOV.L #30H, R3 + MOV.L #40H, R4 + MOV.L #50H, R5 + MOV.L #60H, R6 + MOV.L #70H, R7 + MOV.L #80H, R8 + MOV.L #90H, R9 + MOV.L #100H, R10 + MOV.L #110H, R11 + MOV.L #120H, R12 + MOV.L #130H, R13 + MOV.L #140H, R14 + MOV.L #150H, R15 + + ;/* Put a known value in the hi and low of the accumulators. */ + MVTACHI R1, A0 + MVTACLO R2, A0 + MVTACHI R3, A1 + MVTACLO R4, A1 + + ;/* Loop, checking each itteration that each register still contains the + ;expected value. */ +TestLoop2: + + ;/* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + ;/* Increment the loop counter to show this task is still getting CPU time. */ + MOV.L #_ulRegTest2LoopCounter, R14 + MOV.L [ R14 ], R15 + ADD #1, R15 + MOV.L R15, [ R14 ] + + ;/* Check accumulators. */ + MVFACHI #0, A0, R15 + CMP #10H, R15 + BNE RegTest1Error + MVFACLO #0, A0, R15 + CMP #20H, R15 + BNE RegTest1Error + MVFACGU #0, A0, R15 + CMP #1H, R15 + BNE RegTest1Error + MVFACHI #0, A1, R15 + CMP #30H, R15 + BNE RegTest1Error + MVFACLO #0, A1, R15 + CMP #40H, R15 + BNE RegTest1Error + MVFACGU #0, A1, R15 + CMP #2H, R15 + BNE RegTest1Error + + ;/* Restore the clobbered registers. */ + POPM R14-R15 + + ;/* Now compare each register to ensure it still contains the value that was + ;set before this loop was entered. */ + CMP #10H, R1 + BNE RegTest2Error + CMP #20H, R2 + BNE RegTest2Error + CMP #30H, R3 + BNE RegTest2Error + CMP #40H, R4 + BNE RegTest2Error + CMP #50H, R5 + BNE RegTest2Error + CMP #60H, R6 + BNE RegTest2Error + CMP #70H, R7 + BNE RegTest2Error + CMP #80H, R8 + BNE RegTest2Error + CMP #90H, R9 + BNE RegTest2Error + CMP #100H, R10 + BNE RegTest2Error + CMP #110H, R11 + BNE RegTest2Error + CMP #120H, R12 + BNE RegTest2Error + CMP #130H, R13 + BNE RegTest2Error + CMP #140H, R14 + BNE RegTest2Error + CMP #150H, R15 + BNE RegTest2Error + + ;/* All comparisons passed, start a new itteratio of this loop. */ + BRA TestLoop2 + +RegTest2Error: + ;/* A compare failed, just loop here so the loop counter stops incrementing + ;- causing the check task to indicate the error. */ + BRA RegTest2Error + + + .END diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s new file mode 100644 index 000000000..af07b4bf0 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/Full_Demo/RegTest_IAR.s @@ -0,0 +1,304 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + PUBLIC _vRegTest1Implementation + PUBLIC _vRegTest2Implementation + + EXTERN _ulRegTest1LoopCounter + EXTERN _ulRegTest2LoopCounter + + RSEG CODE:CODE(4) + +/* This function is explained in the comments at the top of main.c. */ +_vRegTest1Implementation: + + ;/* Put a known value in the guard byte of the accumulators. */ + MOV.L #10, R1 + MVTACGU R1, A0 + MOV.L #20, R1 + MVTACGU R1, A1 + + /* Put a known value in each register. */ + MOV #1, R1 + MOV #2, R2 + MOV #3, R3 + MOV #4, R4 + MOV #5, R5 + MOV #6, R6 + MOV #7, R7 + MOV #8, R8 + MOV #9, R9 + MOV #10, R10 + MOV #11, R11 + MOV #12, R12 + MOV #13, R13 + MOV #14, R14 + MOV #15, R15 + + ;/* Put a known value in the hi and low of the accumulators. */ + MVTACHI R1, A0 + MVTACLO R2, A0 + MVTACHI R3, A1 + MVTACLO R4, A1 + /* Loop, checking each itteration that each register still contains the + expected value. */ +TestLoop1: + + /* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + /* Increment the loop counter to show this task is still getting CPU time. */ + MOV #_ulRegTest1LoopCounter, R14 + MOV [ R14 ], R15 + ADD #1, R15 + MOV R15, [ R14 ] + + /* Yield to extend the text coverage. Set the bit in the ITU SWINTR register. */ + MOV #1, R14 + MOV #0872E0H, R15 + MOV.B R14, [R15] + NOP + NOP + + ;/* Check accumulators. */ + MVFACHI #0, A0, R15 + CMP #1, R15 + BNE RegTest1Error + MVFACLO #0, A0, R15 + CMP #2, R15 + BNE RegTest1Error + MVFACGU #0, A0, R15 + CMP #10, R15 + BNE RegTest1Error + MVFACHI #0, A1, R15 + CMP #3, R15 + BNE RegTest1Error + MVFACLO #0, A1, R15 + CMP #4, R15 + BNE RegTest1Error + MVFACGU #0, A1, R15 + CMP #20, R15 + BNE RegTest1Error + + /* Restore the clobbered registers. */ + POPM R14-R15 + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + CMP #1, R1 + BNE RegTest1Error + CMP #2, R2 + BNE RegTest1Error + CMP #3, R3 + BNE RegTest1Error + CMP #4, R4 + BNE RegTest1Error + CMP #5, R5 + BNE RegTest1Error + CMP #6, R6 + BNE RegTest1Error + CMP #7, R7 + BNE RegTest1Error + CMP #8, R8 + BNE RegTest1Error + CMP #9, R9 + BNE RegTest1Error + CMP #10, R10 + BNE RegTest1Error + CMP #11, R11 + BNE RegTest1Error + CMP #12, R12 + BNE RegTest1Error + CMP #13, R13 + BNE RegTest1Error + CMP #14, R14 + BNE RegTest1Error + CMP #15, R15 + BNE RegTest1Error + + /* All comparisons passed, start a new itteratio of this loop. */ + BRA TestLoop1 + +RegTest1Error: + /* A compare failed, just loop here so the loop counter stops incrementing + - causing the check task to indicate the error. */ + BRA RegTest1Error +/*-----------------------------------------------------------*/ + +/* This function is explained in the comments at the top of main.c. */ +_vRegTest2Implementation: + + ;/* Put a known value in the guard byte of the accumulators. */ + MOV.L #1H, R1 + MVTACGU R1, A0 + MOV.L #2H, R1 + MVTACGU R1, A1 + + /* Put a known value in each register. */ + MOV #10H, R1 + MOV #20H, R2 + MOV #30H, R3 + MOV #40H, R4 + MOV #50H, R5 + MOV #60H, R6 + MOV #70H, R7 + MOV #80H, R8 + MOV #90H, R9 + MOV #100H, R10 + MOV #110H, R11 + MOV #120H, R12 + MOV #130H, R13 + MOV #140H, R14 + MOV #150H, R15 + + ;/* Put a known value in the hi and low of the accumulators. */ + MVTACHI R1, A0 + MVTACLO R2, A0 + MVTACHI R3, A1 + MVTACLO R4, A1 + + /* Loop, checking each itteration that each register still contains the + expected value. */ +TestLoop2: + + /* Push the registers that are going to get clobbered. */ + PUSHM R14-R15 + + /* Increment the loop counter to show this task is still getting CPU time. */ + MOV #_ulRegTest2LoopCounter, R14 + MOV [ R14 ], R15 + ADD #1, R15 + MOV R15, [ R14 ] + + ;/* Check accumulators. */ + MVFACHI #0, A0, R15 + CMP #10H, R15 + BNE RegTest1Error + MVFACLO #0, A0, R15 + CMP #20H, R15 + BNE RegTest1Error + MVFACGU #0, A0, R15 + CMP #1H, R15 + BNE RegTest1Error + MVFACHI #0, A1, R15 + CMP #30H, R15 + BNE RegTest1Error + MVFACLO #0, A1, R15 + CMP #40H, R15 + BNE RegTest1Error + MVFACGU #0, A1, R15 + CMP #2H, R15 + BNE RegTest1Error + + /* Restore the clobbered registers. */ + POPM R14-R15 + + /* Now compare each register to ensure it still contains the value that was + set before this loop was entered. */ + CMP #10H, R1 + BNE RegTest2Error + CMP #20H, R2 + BNE RegTest2Error + CMP #30H, R3 + BNE RegTest2Error + CMP #40H, R4 + BNE RegTest2Error + CMP #50H, R5 + BNE RegTest2Error + CMP #60H, R6 + BNE RegTest2Error + CMP #70H, R7 + BNE RegTest2Error + CMP #80H, R8 + BNE RegTest2Error + CMP #90H, R9 + BNE RegTest2Error + CMP #100H, R10 + BNE RegTest2Error + CMP #110H, R11 + BNE RegTest2Error + CMP #120H, R12 + BNE RegTest2Error + CMP #130H, R13 + BNE RegTest2Error + CMP #140H, R14 + BNE RegTest2Error + CMP #150H, R15 + BNE RegTest2Error + + /* All comparisons passed, start a new itteratio of this loop. */ + BRA TestLoop2 + +RegTest2Error: + /* A compare failed, just loop here so the loop counter stops incrementing + - causing the check task to indicate the error. */ + BRA RegTest2Error + + + END diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h new file mode 100644 index 000000000..1516a0753 --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/PriorityDefinitions.h @@ -0,0 +1,86 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef PRIORITY_DEFINITIONS_H +#define PRIORITY_DEFINITIONS_H + +#ifndef __IASMRX__ + #error This file is only intended to be included from the FreeRTOS IAR port layer assembly file. +#endif + +/* The interrupt priority used by the kernel itself for the tick interrupt and +the pended interrupt. This would normally be the lowest priority. */ +#define configKERNEL_INTERRUPT_PRIORITY 1 + +/* The maximum interrupt priority from which FreeRTOS API calls can be made. +Interrupts that use a priority above this will not be effected by anything the +kernel is doing. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#endif /* PRIORITY_DEFINITIONS_H */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h index bd639b9ac..a099d50ff 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_macrodriver.h @@ -2,15 +2,15 @@ * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. +* applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * @@ -30,8 +30,14 @@ /*********************************************************************************************************************** Includes ***********************************************************************************************************************/ -#include "../iodefine.h" -//_RB_#include +#ifdef __ICCRX__ + #include + #include +#endif + +#ifdef __GNUC__ + #include "iodefine.h" +#endif /*********************************************************************************************************************** Macro definitions (Register bit) @@ -66,7 +72,7 @@ Macro definitions Typedef definitions ***********************************************************************************************************************/ #ifndef __TYPEDEF__ - #ifndef _STD_USING_INT_TYPES + #if !defined( _STD_USING_INT_TYPES ) && !defined( _STDINT ) #define _SYS_INT_TYPES_H #ifndef _STD_USING_BIT_TYPES #ifndef __int8_t_defined diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c index 4b2528c33..db13525db 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci.c @@ -2,15 +2,15 @@ * DISCLAIMER * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. * No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all -* applicable laws, including copyright laws. +* applicable laws, including copyright laws. * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIESREGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY * LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR * ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability -* of this software. By using this software, you agree to the additional terms and conditions found by accessing the +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability +* of this software. By using this software, you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer * @@ -78,11 +78,11 @@ void R_SCI7_Create(void) SCI7.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED; /* Set control registers */ - SCI7.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | + SCI7.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE; - SCI7.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | + SCI7.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST | _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; - SCI7.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK | + SCI7.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | _00_SCI_NOISE_FILTER_DISABLE | _10_SCI_8_BASE_CLOCK | _00_SCI_BAUDRATE_SINGLE | _00_SCI_BIT_MODULATION_DISABLE; /* Set bitrate */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user_iar.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user_iar.c new file mode 100644 index 000000000..56dbc223a --- /dev/null +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/cg_src/r_cg_sci_user_iar.c @@ -0,0 +1,241 @@ +/*Adapted for IAR Embedded Workbench*/ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2013, 2014 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +* File Name : r_cg_sci_user.c +* Version : Code Generator for RX64M V1.00.01.01 [09 May 2014] +* Device(s) : R5F571MLCxFC +* Tool-Chain : IAR Embedded Workbench +* Description : This file implements device driver for SCI module. +* Creation Date: 30/06/2014 +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Pragma directive +***********************************************************************************************************************/ +/* Start user code for pragma. Do not edit comment generated here */ +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +Includes +***********************************************************************************************************************/ +#include "r_cg_macrodriver.h" +#include "r_cg_sci.h" +/* Start user code for include. Do not edit comment generated here */ +#include "rskrx71mdef.h" +//_RB_#include "r_cg_cmt.h" +/* End user code. Do not edit comment generated here */ +#include "r_cg_userdefine.h" + +/*********************************************************************************************************************** +Global variables and functions +***********************************************************************************************************************/ +extern uint8_t * gp_sci7_tx_address; /* SCI7 send buffer address */ +extern uint16_t g_sci7_tx_count; /* SCI7 send data number */ +extern uint8_t * gp_sci7_rx_address; /* SCI7 receive buffer address */ +extern uint16_t g_sci7_rx_count; /* SCI7 receive data number */ +extern uint16_t g_sci7_rx_length; /* SCI7 receive data length */ +/* Start user code for global. Do not edit comment generated here */ + +/* Global used to receive a character from the PC terminal */ +uint8_t g_rx_char; + +/* Flag used to control transmission to PC terminal */ +volatile uint8_t g_tx_flag = FALSE; + +/* Flag used locally to detect transmission complete */ +static volatile uint8_t sci7_txdone; + +/* End user code. Do not edit comment generated here */ + +/*********************************************************************************************************************** +* Function Name: r_sci7_transmit_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#pragma vector=VECT(SCI7,TXI7) +__interrupt static void r_sci7_transmit_interrupt(void) +{ + if (g_sci7_tx_count > 0U) + { + SCI7.TDR = *gp_sci7_tx_address; + gp_sci7_tx_address++; + g_sci7_tx_count--; + } + else + { + SCI7.SCR.BIT.TIE = 0U; + SCI7.SCR.BIT.TEIE = 1U; + } +} + +/*********************************************************************************************************************** +* Function Name: r_sci7_transmitend_interrupt +* Description : This function is TEI7 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_sci7_transmitend_interrupt(void) +{ + MPC.P90PFS.BYTE = 0x00U; + PORT9.PMR.BYTE &= 0xFEU; + SCI7.SCR.BIT.TIE = 0U; + SCI7.SCR.BIT.TE = 0U; + SCI7.SCR.BIT.TEIE = 0U; + + r_sci7_callback_transmitend(); +} +/*********************************************************************************************************************** +* Function Name: r_sci7_receive_interrupt +* Description : None +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +#pragma vector=VECT(SCI7,RXI7) +__interrupt static void r_sci7_receive_interrupt(void) +{ + if (g_sci7_rx_length > g_sci7_rx_count) + { + *gp_sci7_rx_address = SCI7.RDR; + gp_sci7_rx_address++; + g_sci7_rx_count++; + + if (g_sci7_rx_length <= g_sci7_rx_count) + { + r_sci7_callback_receiveend(); + } + } +} +/*********************************************************************************************************************** +* Function Name: r_sci7_receiveerror_interrupt +* Description : This function is ERI7 interrupt service routine. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +void r_sci7_receiveerror_interrupt(void) +{ + uint8_t err_type; + + r_sci7_callback_receiveerror(); + + /* Clear overrun, framing and parity error flags */ + err_type = SCI7.SSR.BYTE; + err_type &= 0xC7U; + err_type |= 0xC0U; + SCI7.SSR.BYTE = err_type; +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_transmitend +* Description : This function is a callback function when SCI7 finishes transmission. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_transmitend(void) +{ + /* Start user code. Do not edit comment generated here */ + sci7_txdone = TRUE; + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_receiveend +* Description : This function is a callback function when SCI7 finishes reception. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_receiveend(void) +{ + /* Start user code. Do not edit comment generated here */ + /* Check the contents of g_rx_char */ + if ('z' == g_rx_char) + { + /* Stop the timer used to control transmission to PC terminal*/ +// R_CMT1_Stop(); + + /* Turn off LED0 and turn on LED1 to indicate serial transmission + inactive */ + LED0 = LED_OFF; + LED1 = LED_ON; + } + else + { + /* Start the timer used to control transmission to PC terminal*/ +//_RB_ R_CMT1_Start(); + + /* Turn on LED0 and turn off LED1 to indicate serial transmission + active */ + LED0 = LED_ON; + LED1 = LED_OFF; + } + + /* Set up SCI7 receive buffer again */ + R_SCI7_Serial_Receive((uint8_t *)&g_rx_char, 1); + /* End user code. Do not edit comment generated here */ +} +/*********************************************************************************************************************** +* Function Name: r_sci7_callback_receiveerror +* Description : This function is a callback function when SCI7 reception encounters error. +* Arguments : None +* Return Value : None +***********************************************************************************************************************/ +static void r_sci7_callback_receiveerror(void) +{ + /* Start user code. Do not edit comment generated here */ + /* End user code. Do not edit comment generated here */ +} + +/*********************************************************************************************************************** +* Function Name: R_SCI7_AsyncTransmit +* Description : This function sends SCI7 data and waits for the transmit end flag. +* Arguments : tx_buf - +* transfer buffer pointer +* tx_num - +* buffer size +* Return Value : status - +* MD_OK or MD_ARGERROR +***********************************************************************************************************************/ +MD_STATUS R_SCI7_AsyncTransmit (uint8_t * const tx_buf, const uint16_t tx_num) +{ + MD_STATUS status = MD_OK; + + /* clear the flag before initiating a new transmission */ + sci7_txdone = FALSE; + + /* Send the data using the API */ + status = R_SCI7_Serial_Send(tx_buf, tx_num); + + /* Wait for the transmit end flag */ + while (FALSE == sci7_txdone) + { + /* Wait */ + } + return (status); +} +/*********************************************************************************************************************** +* End of function R_SCI7_AsyncTransmit +***********************************************************************************************************************/ + + +/* End user code. Do not edit comment generated here */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c index 1a79fb545..75cfe547d 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_GCC_e2studio_IAR/src/main.c @@ -248,6 +248,23 @@ const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500 /* Reneable register protection. */ SYSTEM.PRCR.WORD = ulDisableRegisterWrite; } +/*-----------------------------------------------------------*/ + +#ifdef __ICCRX__ + + #include + /* Called from the C start up code when compiled with IAR. */ + #pragma diag_suppress = Pm011 + int __low_level_init(void) + #pragma diag_default = Pm011 + { + extern void R_Systeminit( void ); + + __disable_interrupt(); + R_Systeminit(); + return (int)(1U); + } +#endif /* __ICCRX__ */ diff --git a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h index caa49c718..e7bad4fc4 100644 --- a/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/RX700_RX71M_RSK_Renesas_e2studio/src/FreeRTOSConfig.h @@ -88,7 +88,7 @@ #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 1 #define configUSE_TICK_HOOK 1 -#define configCPU_CLOCK_HZ ( 120000000UL ) /*_RB_ guess*/ +#define configCPU_CLOCK_HZ ( 120000000UL ) /*_RB_ guess cg shows 240 and 120*/ #define configPERIPHERAL_CLOCK_HZ ( 60000000UL ) /*_RB_ guess*/ #define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 140 ) diff --git a/FreeRTOS/Source/portable/IAR/RX100/portmacro.h b/FreeRTOS/Source/portable/IAR/RX100/portmacro.h index 041be341e..50efc54ff 100644 --- a/FreeRTOS/Source/portable/IAR/RX100/portmacro.h +++ b/FreeRTOS/Source/portable/IAR/RX100/portmacro.h @@ -179,6 +179,11 @@ extern void vTaskExitCritical( void ); #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) +/* Prevent warnings of undefined behaviour: the order of volatile accesses is +undefined - all warnings have been manually checked and are not an issue, and +the warnings cannot be prevent by code changes without undesirable effects. */ +#pragma diag_suppress=Pa082 + #ifdef __cplusplus } #endif diff --git a/FreeRTOS/Source/portable/IAR/RXv2/port.c b/FreeRTOS/Source/portable/IAR/RXv2/port.c new file mode 100644 index 000000000..1ba4c92c5 --- /dev/null +++ b/FreeRTOS/Source/portable/IAR/RXv2/port.c @@ -0,0 +1,244 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Implementation of functions defined in portable.h for the SH2A port. + *----------------------------------------------------------*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Library includes. */ +#include "string.h" + +/* Hardware specifics. */ +#warning RX600v1 port included chip specific header file here. +#include + +/*-----------------------------------------------------------*/ + +/* Tasks should start with interrupts enabled and in Supervisor mode, therefore +PSW is set with U and I set, and PM and IPL clear. */ +#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) +#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) + +/*-----------------------------------------------------------*/ + +/* + * Function to start the first task executing - written in asm code as direct + * access to registers is required. + */ +extern void prvStartFirstTask( void ); + +/* + * The tick ISR handler. The peripheral used is configured by the application + * via a hook/callback function. + */ +__interrupt void vTickISR( void ); + +/*-----------------------------------------------------------*/ + +extern void *pxCurrentTCB; + +/*-----------------------------------------------------------*/ + +/* + * See header file for description. + */ +StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) +{ + /* R0 is not included as it is the stack pointer. */ + + *pxTopOfStack = 0x00; + pxTopOfStack--; + *pxTopOfStack = portINITIAL_PSW; + pxTopOfStack--; + *pxTopOfStack = ( StackType_t ) pxCode; + + /* When debugging it can be useful if every register is set to a known + value. Otherwise code space can be saved by just setting the registers + that need to be set. */ + #ifdef USE_FULL_REGISTER_INITIALISATION + { + pxTopOfStack--; + *pxTopOfStack = 0xffffffff; /* r15. */ + pxTopOfStack--; + *pxTopOfStack = 0xeeeeeeee; + pxTopOfStack--; + *pxTopOfStack = 0xdddddddd; + pxTopOfStack--; + *pxTopOfStack = 0xcccccccc; + pxTopOfStack--; + *pxTopOfStack = 0xbbbbbbbb; + pxTopOfStack--; + *pxTopOfStack = 0xaaaaaaaa; + pxTopOfStack--; + *pxTopOfStack = 0x99999999; + pxTopOfStack--; + *pxTopOfStack = 0x88888888; + pxTopOfStack--; + *pxTopOfStack = 0x77777777; + pxTopOfStack--; + *pxTopOfStack = 0x66666666; + pxTopOfStack--; + *pxTopOfStack = 0x55555555; + pxTopOfStack--; + *pxTopOfStack = 0x44444444; + pxTopOfStack--; + *pxTopOfStack = 0x33333333; + pxTopOfStack--; + *pxTopOfStack = 0x22222222; + pxTopOfStack--; + } + #else + { + pxTopOfStack -= 15; + } + #endif + + *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ + pxTopOfStack--; + *pxTopOfStack = portINITIAL_FPSW; + pxTopOfStack--; + *pxTopOfStack = 0x11111111; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x22222222; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x33333333; /* Accumulator 0. */ + pxTopOfStack--; + *pxTopOfStack = 0x44444444; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x55555555; /* Accumulator 1. */ + pxTopOfStack--; + *pxTopOfStack = 0x66666666; /* Accumulator 1. */ + + return pxTopOfStack; +} +/*-----------------------------------------------------------*/ + +BaseType_t xPortStartScheduler( void ) +{ +extern void vApplicationSetupTimerInterrupt( void ); + + /* Use pxCurrentTCB just so it does not get optimised away. */ + if( pxCurrentTCB != NULL ) + { + /* Call an application function to set up the timer that will generate the + tick interrupt. This way the application can decide which peripheral to + use. A demo application is provided to show a suitable example. */ + vApplicationSetupTimerInterrupt(); + + /* Enable the software interrupt. */ + _IEN( _ICU_SWINT ) = 1; + + /* Ensure the software interrupt is clear. */ + _IR( _ICU_SWINT ) = 0; + + /* Ensure the software interrupt is set to the kernel priority. */ + _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; + + /* Start the first task. */ + prvStartFirstTask(); + } + + /* Should not get here. */ + return pdFAIL; +} +/*-----------------------------------------------------------*/ + +#pragma vector = configTICK_VECTOR +__interrupt void vTickISR( void ) +{ + /* Re-enable interrupts. */ + __enable_interrupt(); + + /* Increment the tick, and perform any processing the new tick value + necessitates. */ + __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY ); + { + if( xTaskIncrementTick() != pdFALSE ) + { + taskYIELD(); + } + } + __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY ); +} +/*-----------------------------------------------------------*/ + +void vPortEndScheduler( void ) +{ + /* Not implemented in ports where there is nothing to return to. + Artificially force an assert. */ + configASSERT( pxCurrentTCB == NULL ); +} +/*-----------------------------------------------------------*/ + + + diff --git a/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s b/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s new file mode 100644 index 000000000..023ac1a91 --- /dev/null +++ b/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s @@ -0,0 +1,242 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#include "PriorityDefinitions.h" + + PUBLIC _prvStartFirstTask + PUBLIC ___interrupt_27 + + EXTERN _pxCurrentTCB + EXTERN _vTaskSwitchContext + + RSEG CODE:CODE(4) + +_prvStartFirstTask: + + /* When starting the scheduler there is nothing that needs moving to the + interrupt stack because the function is not called from an interrupt. + Just ensure the current stack is the user stack. */ + SETPSW U + + /* Obtain the location of the stack associated with which ever task + pxCurrentTCB is currently pointing to. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [R15], R15 + MOV.L [R15], R0 + + /* Restore the registers from the stack of the task pointed to by + pxCurrentTCB. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + + /* Floating point status word. */ + MVTC R15, FPSW + + /* R1 to R15 - R0 is not included as it is the SP. */ + POPM R1-R15 + + /* This pops the remaining registers. */ + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + +/* The software interrupt - overwrite the default 'weak' definition. */ +___interrupt_27: + + /* Re-enable interrupts. */ + SETPSW I + + /* Move the data that was automatically pushed onto the interrupt stack when + the interrupt occurred from the interrupt stack to the user stack. + + R15 is saved before it is clobbered. */ + PUSH.L R15 + + /* Read the user stack pointer. */ + MVFC USP, R15 + + /* Move the address down to the data being moved. */ + SUB #12, R15 + MVTC R15, USP + + /* Copy the data across, R15, then PC, then PSW. */ + MOV.L [ R0 ], [ R15 ] + MOV.L 4[ R0 ], 4[ R15 ] + MOV.L 8[ R0 ], 8[ R15 ] + + /* Move the interrupt stack pointer to its new correct position. */ + ADD #12, R0 + + /* All the rest of the registers are saved directly to the user stack. */ + SETPSW U + + /* Save the rest of the general registers (R15 has been saved already). */ + PUSHM R1-R14 + + /* Save the FPSW and accumulator. */ + MVFC FPSW, R15 + PUSH.L R15 + MVFACGU #0, A1, R15 + PUSH.L R15 + MVFACHI #0, A1, R15 + PUSH.L R15 + /* Low order word. */ + MVFACLO #0, A1, R15 + PUSH.L R15 + MVFACGU #0, A0, R15 + PUSH.L R15 + MVFACHI #0, A0, R15 + PUSH.L R15 + /* Low order word. */ + MVFACLO #0, A0, R15 + PUSH.L R15 + + /* Save the stack pointer to the TCB. */ + MOV.L #_pxCurrentTCB, R15 + MOV.L [ R15 ], R15 + MOV.L R0, [ R15 ] + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + structures are being accessed. */ + MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY + + /* Select the next task to run. */ + BSR.A _vTaskSwitchContext + + /* Reset the interrupt mask as no more data structure access is required. */ + MVTIPL #configKERNEL_INTERRUPT_PRIORITY + + /* Load the stack pointer of the task that is now selected as the Running + state task from its TCB. */ + MOV.L #_pxCurrentTCB,R15 + MOV.L [ R15 ], R15 + MOV.L [ R15 ], R0 + + /* Restore the context of the new task. The PSW (Program Status Word) and + PC will be popped by the RTE instruction. */ + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A0 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A0 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A0 + POP R15 + + /* Accumulator low 32 bits. */ + MVTACLO R15, A1 + POP R15 + + /* Accumulator high 32 bits. */ + MVTACHI R15, A1 + POP R15 + + /* Accumulator guard. */ + MVTACGU R15, A1 + POP R15 + MVTC R15, FPSW + POPM R1-R15 + RTE + NOP + NOP + +/*-----------------------------------------------------------*/ + + END + diff --git a/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h b/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h new file mode 100644 index 000000000..bc8b55355 --- /dev/null +++ b/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h @@ -0,0 +1,186 @@ +/* + FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef PORTMACRO_H +#define PORTMACRO_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*----------------------------------------------------------- + * Port specific definitions. + * + * The settings in this file configure FreeRTOS correctly for the + * given hardware and compiler. + * + * These settings should not be altered. + *----------------------------------------------------------- + */ + +/* Type definitions - these are a bit legacy and not really used now, other than +portSTACK_TYPE and portBASE_TYPE. */ +#define portCHAR char +#define portFLOAT float +#define portDOUBLE double +#define portLONG long +#define portSHORT short +#define portSTACK_TYPE uint32_t +#define portBASE_TYPE long + +typedef portSTACK_TYPE StackType_t; +typedef long BaseType_t; +typedef unsigned long UBaseType_t; + + +#if( configUSE_16_BIT_TICKS == 1 ) + typedef uint16_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffff +#else + typedef uint32_t TickType_t; + #define portMAX_DELAY ( TickType_t ) 0xffffffffUL + + /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do + not need to be guarded with a critical section. */ + #define portTICK_TYPE_IS_ATOMIC 1 +#endif +/*-----------------------------------------------------------*/ + +/* Hardware specifics. */ +#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ +#define portSTACK_GROWTH -1 +#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) +#define portNOP() __no_operation() + +/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" +where portITU_SWINTR is the location of the software interrupt register +(0x000872E0). Don't rely on the assembler to select a register, so instead +save and restore clobbered registers manually. */ +#define portYIELD() \ + __asm volatile \ + ( \ + "PUSH.L R10 \n" \ + "MOV.L #0x872E0, R10 \n" \ + "MOV.B #0x1, [R10] \n" \ + "MOV.L [R10], R10 \n" \ + "POP R10 \n" \ + ) + +#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) portYIELD() + +/* These macros should not be called directly, but through the +taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is +performed if configASSERT() is defined to ensure an assertion handler does not +inadvertently attempt to lower the IPL when the call to assert was triggered +because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY +when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API +functions are those that end in FromISR. FreeRTOS maintains a separate +interrupt API to ensure API function and interrupt entry is as fast and as +simple as possible. */ +#define portENABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) 0 ) +#ifdef configASSERT + #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) + #define portDISABLE_INTERRUPTS() if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#else + #define portDISABLE_INTERRUPTS() __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY ) +#endif + +/* Critical nesting counts are stored in the TCB. */ +#define portCRITICAL_NESTING_IN_TCB ( 1 ) + +/* The critical nesting functions defined within tasks.c. */ +extern void vTaskEnterCritical( void ); +extern void vTaskExitCritical( void ); +#define portENTER_CRITICAL() vTaskEnterCritical() +#define portEXIT_CRITICAL() vTaskExitCritical() + +/* As this port allows interrupt nesting... */ +#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS() +#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) ) + +/*-----------------------------------------------------------*/ + +/* Task function macros as described on the FreeRTOS.org WEB site. */ +#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) +#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) + +/* Prevent warnings of undefined behaviour: the order of volatile accesses is +undefined - all warnings have been manually checked and are not an issue, and +the warnings cannot be prevent by code changes without undesirable effects. */ +#pragma diag_suppress=Pa082 + +#ifdef __cplusplus +} +#endif + +#endif /* PORTMACRO_H */ + diff --git a/FreeRTOS/Source/portable/MemMang/heap_4.c b/FreeRTOS/Source/portable/MemMang/heap_4.c index ce482d005..b89cadbc4 100644 --- a/FreeRTOS/Source/portable/MemMang/heap_4.c +++ b/FreeRTOS/Source/portable/MemMang/heap_4.c @@ -237,7 +237,7 @@ void *pvReturn = NULL; pxBlock->xBlockSize = xWantedSize; /* Insert the new block into the list of free blocks. */ - prvInsertBlockIntoFreeList( ( pxNewBlockLink ) ); + prvInsertBlockIntoFreeList( pxNewBlockLink ); } else { diff --git a/FreeRTOS/Source/tasks.c b/FreeRTOS/Source/tasks.c index 858337971..bd767423c 100644 --- a/FreeRTOS/Source/tasks.c +++ b/FreeRTOS/Source/tasks.c @@ -3581,7 +3581,6 @@ TCB_t *pxTCB; { portASSERT_IF_IN_ISR(); } - } else {