From: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Date: Fri, 6 Jun 2008 07:24:13 +0000 (+0900)
Subject: sh: Add support Renesas SH7763
X-Git-Tag: v1.3.4-rc1~103^2~1
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=60179098a95eaa972007d7ec58e4c1588029720f;p=u-boot

sh: Add support Renesas SH7763

Renesas SH7763 has 3 SCIF, MMC, LCDC, Ethernet and other.
This patch supprts CPU register's header file.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---

diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h
index c200ba5a46..5a8a5a149c 100644
--- a/include/asm-sh/cpu_sh4.h
+++ b/include/asm-sh/cpu_sh4.h
@@ -35,6 +35,8 @@
 # include <asm/cpu_sh7750.h>
 #elif defined (CONFIG_CPU_SH7722)
 # include <asm/cpu_sh7722.h>
+#elif defined (CONFIG_CPU_SH7763)
+# include <asm/cpu_sh7763.h>
 #elif defined (CONFIG_CPU_SH7780)
 # include <asm/cpu_sh7780.h>
 #else
diff --git a/include/asm-sh/cpu_sh7763.h b/include/asm-sh/cpu_sh7763.h
new file mode 100644
index 0000000000..78b456b4b2
--- /dev/null
+++ b/include/asm-sh/cpu_sh7763.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_CPU_SH7763_H_
+#define _ASM_CPU_SH7763_H_
+
+/* CACHE */
+#define CACHE_OC_NUM_WAYS	1
+#define CCR				0xFF00001C
+#define CCR_CACHE_INIT	0x0000090b
+
+/* SCIF */
+/* SCIF0 */
+#define SCIF0_BASE	SCSMR0
+#define SCSMR0		0xFFE00000
+
+/* SCIF1 */
+#define SCIF1_BASE	SCSMR1
+#define SCSMR1		0xFFE08000
+
+/* SCIF2 */
+#define SCIF2_BASE	SCSMR2
+#define SCSMR2		0xFFE10000
+
+/* Watchdog Timer */
+#define WTCNT		WDTST
+#define WDTST		0xFFCC0000
+
+/* TMU */
+#define TSTR		0xFFD80004
+#define TCOR0		0xFFD80008
+#define TCNT0		0xFFD8000C
+#define TCR0		0xFFD80010
+
+#endif /* _ASM_CPU_SH7763_H_ */