From: Shaohui Xie <Shaohui.Xie@freescale.com>
Date: Thu, 22 Sep 2011 09:27:29 +0000 (+0800)
Subject: powerpc/p2041rdb: updated description of cpld command
X-Git-Tag: v2011.12-rc1~600^2~12
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=60820457ccf6e9c8b7a9afc2b45c78a84f8edda8;p=u-boot

powerpc/p2041rdb: updated description of cpld command

According to CPLD 2.2, the default configuration is changed, so updated the
description of CPLD command, otherwise it will confusing.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/board/freescale/p2041rdb/cpld.c b/board/freescale/p2041rdb/cpld.c
index 37b0ed5727..2ad89a84e2 100644
--- a/board/freescale/p2041rdb/cpld.c
+++ b/board/freescale/p2041rdb/cpld.c
@@ -159,14 +159,14 @@ U_BOOT_CMD(
 	"cpld_cmd watchdog <watchdog_period> - set the watchdog period\n"
 	"	period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n"
 	"cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
-	"	lane 6: 0 -> slot1 (Default)\n"
-	"		1 -> SGMII\n"
-	"	lane a: 0 -> slot2 (Default)\n"
-	"		1 -> AURORA\n"
-	"	lane c: 0 -> slot2 (Default)\n"
-	"		1 -> SATA0\n"
-	"	lane d: 0 -> slot2 (Default)\n"
-	"		1 -> SATA1\n"
+	"	lane 6: 0 -> slot1\n"
+	"		1 -> SGMII (Default)\n"
+	"	lane a: 0 -> slot2\n"
+	"		1 -> AURORA (Default)\n"
+	"	lane c: 0 -> slot2\n"
+	"		1 -> SATA0 (Default)\n"
+	"	lane d: 0 -> slot2\n"
+	"		1 -> SATA1 (Default)\n"
 #ifdef DEBUG
 	"cpld_cmd dump - display the CPLD registers\n"
 #endif