From: Marek Vasut <marek.vasut+renesas@gmail.com>
Date: Mon, 27 Nov 2017 05:38:12 +0000 (+0100)
Subject: ARM: rmobile: Clean up ad-hoc clock macros
X-Git-Tag: v2018.01-rc1~26^2~8
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=61e2ff8e822d73e152cacf60130b86f88eccee6c;p=u-boot

ARM: rmobile: Clean up ad-hoc clock macros

As we have a proper clock framework driver, these macros are not
needed, so drop them and clean up the whitelist.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---

diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h
index 805c0c254e..740e0517be 100644
--- a/include/configs/salvator-x.h
+++ b/include/configs/salvator-x.h
@@ -17,7 +17,6 @@
 /* SCIF */
 #define CONFIG_CONS_SCIF2
 #define CONFIG_CONS_INDEX	2
-#define CONFIG_SH_SCIF_CLK_FREQ        CONFIG_S3D4_CLK_FREQ
 
 /* [A] Hyper Flash */
 /* use to RPC(SPI Multi I/O Bus Controller) */
@@ -28,14 +27,7 @@
 
 /* Board Clock */
 /* XTAL_CLK : 33.33MHz */
-#define RCAR_XTAL_CLK		33333333u
-#define CONFIG_SYS_CLK_FREQ	RCAR_XTAL_CLK
-/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
-/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz          */
-#define CONFIG_CP_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
-#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 192 / 2)
-#define CONFIG_S3D2_CLK_FREQ	(266666666u/2)
-#define CONFIG_S3D4_CLK_FREQ	(266666666u/4)
+#define CONFIG_SYS_CLK_FREQ	33333333u
 
 /* Generic Timer Definitions (use in assembler source) */
 #define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
@@ -52,9 +44,6 @@
 
 #define CONFIG_SYS_I2C_POWERIC_ADDR	0x30
 
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ		200000000
-
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
 #define CONFIG_SYS_MMC_ENV_DEV		1
diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h
index d6092d5096..c613c733f5 100644
--- a/include/configs/ulcb.h
+++ b/include/configs/ulcb.h
@@ -17,7 +17,6 @@
 /* SCIF */
 #define CONFIG_CONS_SCIF2
 #define CONFIG_CONS_INDEX	2
-#define CONFIG_SH_SCIF_CLK_FREQ        CONFIG_S3D4_CLK_FREQ
 
 /* [A] Hyper Flash */
 /* use to RPC(SPI Multi I/O Bus Controller) */
@@ -28,14 +27,7 @@
 
 /* Board Clock */
 /* XTAL_CLK : 33.33MHz */
-#define RCAR_XTAL_CLK		33333333u
-#define CONFIG_SYS_CLK_FREQ	RCAR_XTAL_CLK
-/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
-/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz          */
-#define CONFIG_CP_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
-#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 192 / 2)
-#define CONFIG_S3D2_CLK_FREQ	(266666666u/2)
-#define CONFIG_S3D4_CLK_FREQ	(266666666u/4)
+#define CONFIG_SYS_CLK_FREQ	33333333u
 
 /* Generic Timer Definitions (use in assembler source) */
 #define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
@@ -65,9 +57,6 @@ unsigned char ulcb_softspi_read(void);
 
 #define CONFIG_SYS_I2C_POWERIC_ADDR	0x30
 
-/* SDHI */
-#define CONFIG_SH_SDHI_FREQ		200000000
-
 /* Environment in eMMC, at the end of 2nd "boot sector" */
 #define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
 #define CONFIG_SYS_MMC_ENV_DEV		1
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 4ce87484c3..c2fe81e552 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -346,7 +346,6 @@ CONFIG_CPU_SH7785
 CONFIG_CPU_SH_TYPE_R
 CONFIG_CPU_TYPE_R
 CONFIG_CPU_VR41XX
-CONFIG_CP_CLK_FREQ
 CONFIG_CQSPI_DECODER
 CONFIG_CQSPI_REF_CLK
 CONFIG_CRC32
@@ -1886,8 +1885,6 @@ CONFIG_RUN_FROM_DDR1
 CONFIG_RUN_FROM_IRAM_ONLY
 CONFIG_RX_DESCR_NUM
 CONFIG_S32V234
-CONFIG_S3D2_CLK_FREQ
-CONFIG_S3D4_CLK_FREQ
 CONFIG_S5P
 CONFIG_S5PC100
 CONFIG_S5PC110