From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 26 Feb 2016 05:21:43 +0000 (+0900)
Subject: ARM: uniphier: refactor DDR-PHY init code
X-Git-Tag: v2016.03-rc3~6^2~15
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=6257a0b0e9b84fca5853e225e1de8023de5f1668;p=u-boot

ARM: uniphier: refactor DDR-PHY init code

The if-else statements for the frequency-dependent register settings
seem clumsy.  Moving them to arrays would make it cleaner.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
index ef1941e5a6..eb9bf24da0 100644
--- a/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/ddrphy-ph1-ld4.c
@@ -4,31 +4,52 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <common.h>
+#include <linux/err.h>
 #include <linux/types.h>
 #include <linux/io.h>
 
 #include "ddrphy-regs.h"
 
+enum dram_freq {
+	DRAM_FREQ_1333M,
+	DRAM_FREQ_1600M,
+	DRAM_FREQ_NR,
+};
+
+static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04};
+static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E};
+static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80};
+static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100};
+static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66};
+static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400};
+static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
+static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
+static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
+
 int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus)
 {
+	enum dram_freq freq_e;
 	u32 tmp;
 
-	writel(0x0300c473, &phy->pgcr[1]);
-	if (freq == 1333) {
-		writel(0x0a806844, &phy->ptr[0]);
-		writel(0x208e0124, &phy->ptr[1]);
-	} else {
-		writel(0x0c807d04, &phy->ptr[0]);
-		writel(0x2710015E, &phy->ptr[1]);
+	switch (freq) {
+	case 1333:
+		freq_e = DRAM_FREQ_1333M;
+		break;
+	case 1600:
+		freq_e = DRAM_FREQ_1600M;
+		break;
+	default:
+		printf("unsupported DRAM frequency %d MHz\n", freq);
+		return -EINVAL;
 	}
+
+	writel(0x0300c473, &phy->pgcr[1]);
+	writel(ddrphy_ptr0[freq_e], &phy->ptr[0]);
+	writel(ddrphy_ptr1[freq_e], &phy->ptr[1]);
 	writel(0x00083DEF, &phy->ptr[2]);
-	if (freq == 1333) {
-		writel(0x0f051616, &phy->ptr[3]);
-		writel(0x06ae08d6, &phy->ptr[4]);
-	} else {
-		writel(0x12061A80, &phy->ptr[3]);
-		writel(0x08027100, &phy->ptr[4]);
-	}
+	writel(ddrphy_ptr3[freq_e], &phy->ptr[3]);
+	writel(ddrphy_ptr4[freq_e], &phy->ptr[4]);
 	writel(0xF004001A, &phy->dsgcr);
 
 	/* change the value of the on-die pull-up/pull-down registors */
@@ -38,23 +59,12 @@ int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, bool ddr3plus)
 	writel(tmp, &phy->dxccr);
 
 	writel(0x0000040B, &phy->dcr);
-	if (freq == 1333) {
-		writel(0x85589955, &phy->dtpr[0]);
-		writel(0x1a8363c0, &phy->dtpr[1]);
-		writel(0x5002c200, &phy->dtpr[2]);
-		writel(0x00000b51, &phy->mr0);
-	} else {
-		writel(0x999cbb66, &phy->dtpr[0]);
-		writel(0x1a878400, &phy->dtpr[1]);
-		writel(0xa00214f8, &phy->dtpr[2]);
-		writel(0x00000d71, &phy->mr0);
-	}
+	writel(ddrphy_dtpr0[freq_e], &phy->dtpr[0]);
+	writel(ddrphy_dtpr1[freq_e], &phy->dtpr[1]);
+	writel(ddrphy_dtpr2[freq_e], &phy->dtpr[2]);
+	writel(ddrphy_mr0[freq_e], &phy->mr0);
 	writel(0x00000006, &phy->mr1);
-	if (freq == 1333)
-		writel(0x00000290, &phy->mr2);
-	else
-		writel(0x00000298, &phy->mr2);
-
+	writel(ddrphy_mr2[freq_e], &phy->mr2);
 	writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
 
 	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))