From: York Sun <yorksun@freescale.com>
Date: Fri, 17 Aug 2012 08:22:42 +0000 (+0000)
Subject: powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only
X-Git-Tag: v2012.10-rc2~67^2~6
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=62f739fe465c41a2c5be0a46b3330c12b213dc07;p=u-boot

powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only

Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 4fd4f8fc33..b47268c20e 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -383,7 +383,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 
 				retval = compute_dimm_parameters(spd, pdimm, i);
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
-				if (retval != 0) {
+				if (!i && !j && retval) {
 					printf("SPD error on controller %d! "
 					"Trying fallback to raw timing "
 					"calculation\n", i);