From: Paul Burton Date: Wed, 21 Sep 2016 10:18:59 +0000 (+0100) Subject: MIPS: Ensure cache ops complete in mips_cache_reset X-Git-Tag: v2016.11-rc1~120^2~14 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=639200f6a0dcfe67e4c923b6108703e192946388;p=u-boot MIPS: Ensure cache ops complete in mips_cache_reset Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton --- diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 53e903a27e..698a5afdee 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -420,6 +420,8 @@ l2_unbypass: #endif return: + /* Ensure all cache operations complete before returning */ + sync jr ra END(mips_cache_reset)