From: rtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Date: Mon, 10 Apr 2017 01:01:11 +0000 (+0000)
Subject: Add more "memory" clobbers into asm code of GCC/ARM_CRx_No_GIC port to make it robust... 
X-Git-Tag: V10.0.0~20
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=645c42f19658d071234055ee9961e82664810f09;p=freertos

Add more "memory" clobbers into asm code of GCC/ARM_CRx_No_GIC port to make it robust with higher optimisation in newer versions of GCC.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2499 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
---

diff --git a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
index b8399c563..01bce44bb 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
@@ -254,7 +254,7 @@ uint32_t ulAPSR;
 
 	/* Only continue if the CPU is not in User mode.  The CPU must be in a
 	Privileged mode for the scheduler to start. */
-	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
 	ulAPSR &= portAPSR_MODE_BITS_MASK;
 	configASSERT( ulAPSR != portAPSR_USER_MODE );
 
@@ -354,7 +354,7 @@ uint32_t ulInitialFPSCR = 0;
 	ulPortTaskHasFPUContext = pdTRUE;
 
 	/* Initialise the floating point status register. */
-	__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) );
+	__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
 }
 /*-----------------------------------------------------------*/
 
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
index 5fe5011df..1801f338d 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
+++ b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
@@ -128,7 +128,7 @@ extern volatile uint32_t ulPortYieldRequired;	\
 
 #define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
 #define portYIELD() __asm volatile ( "SWI 0		\n"				\
-									 "ISB		  " );
+									 "ISB		  " ::: "memory" );
 
 
 /*-----------------------------------------------------------
@@ -148,16 +148,16 @@ extern void vPortInstallFreeRTOSVectorTable( void );
 globally enable and disable interrupts. */
 #define portENTER_CRITICAL()		vPortEnterCritical();
 #define portEXIT_CRITICAL()			vPortExitCritical();
-#define portENABLE_INTERRUPTS()		__asm volatile ( "CPSIE i 	\n"	);
+#define portENABLE_INTERRUPTS()		__asm volatile ( "CPSIE i 	\n"	::: "memory" );
 #define portDISABLE_INTERRUPTS()	__asm volatile ( "CPSID i 	\n"		\
 													 "DSB		\n"		\
-													 "ISB		  " );
+													 "ISB		  " ::: "memory" );
 
 __attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
 {
 volatile uint32_t ulCPSR;
 
-	__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) );
+	__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" );
 	ulCPSR &= portINTERRUPT_ENABLE_BIT;
 	portDISABLE_INTERRUPTS();
 	return ulCPSR;