From: Spencer Oliver <spen@spen-soft.co.uk>
Date: Tue, 1 May 2012 12:18:42 +0000 (+0100)
Subject: cortex-m3: support connecting under reset
X-Git-Tag: v0.6.0-rc1~98
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=6637cf9229c741f2a1e6a7d153895c33c1646e2d;p=openocd

cortex-m3: support connecting under reset

Some targets support connecting while the target's srst is asserted.
Tested on stm32 family.

Change-Id: I9df43623025e37832155aeee7aa099b844b85f16
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/606
Tested-by: jenkins
---

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 09a51b7b..f992bde4 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -952,6 +952,16 @@ static int cortex_m3_assert_reset(struct target *target)
 		return ERROR_OK;
 	}
 
+	/* some cores support connecting while srst is asserted
+	 * use that mode is it has been configured */
+
+	bool srst_asserted = false;
+
+	if (jtag_reset_config & RESET_SRST_NO_GATING) {
+		adapter_assert_reset();
+		srst_asserted = true;
+	}
+
 	/* Enable debug requests */
 	int retval;
 	retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -996,7 +1006,8 @@ static int cortex_m3_assert_reset(struct target *target)
 
 	if (jtag_reset_config & RESET_HAS_SRST) {
 		/* default to asserting srst */
-		adapter_assert_reset();
+		if (!srst_asserted)
+			adapter_assert_reset();
 	} else {
 		/* Use a standard Cortex-M3 software reset mechanism.
 		 * We default to using VECRESET as it is supported on all current cores.