From: Icenowy Zheng <icenowy@aosc.xyz>
Date: Sat, 3 Jun 2017 09:10:17 +0000 (+0800)
Subject: sunxi: add bank detection code to H3 DRAM initialization code
X-Git-Tag: v2017.07-rc2~3^2~12
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=66b12526f0bdfb284a5152cd31d5eed849e7b873;p=u-boot

sunxi: add bank detection code to H3 DRAM initialization code

Some DDR2 DRAM have only four banks, not eight.

Add code to detect this situation.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
---

diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index de683a1b63..3f54c8ee09 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -31,6 +31,7 @@ struct dram_para {
 	u8 bus_full_width;
 	u8 dual_rank;
 	u8 row_bits;
+	u8 bank_bits;
 	const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
 	const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
 	const u8 ac_delays[31];
@@ -449,7 +450,7 @@ static void mctl_set_cr(uint16_t socid, struct dram_para *para)
 			(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 
 	writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
-	       MCTL_CR_EIGHT_BANKS |
+	       (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS : MCTL_CR_FOUR_BANKS) |
 	       MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
 	       (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
 	       MCTL_CR_PAGE_SIZE(para->page_size) |
@@ -689,10 +690,19 @@ static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
 	/* detect row address bits */
 	para->page_size = 512;
 	para->row_bits = 16;
+	para->bank_bits = 2;
 	mctl_set_cr(socid, para);
 
 	for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
-		if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
+		if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits)) * para->page_size))
+			break;
+
+	/* detect bank address bits */
+	para->bank_bits = 3;
+	mctl_set_cr(socid, para);
+
+	for (para->bank_bits = 2; para->bank_bits < 3; para->bank_bits++)
+		if (mctl_mem_matches((1 << para->bank_bits) * para->page_size))
 			break;
 
 	/* detect page size */
@@ -786,6 +796,7 @@ unsigned long sunxi_dram_init(void)
 		.dual_rank = 0,
 		.bus_full_width = 1,
 		.row_bits = 15,
+		.bank_bits = 3,
 		.page_size = 4096,
 
 #if defined(CONFIG_MACH_SUN8I_H3)
@@ -850,6 +861,6 @@ unsigned long sunxi_dram_init(void)
 	mctl_auto_detect_dram_size(socid, &para);
 	mctl_set_cr(socid, &para);
 
-	return (1UL << (para.row_bits + 3)) * para.page_size *
-						(para.dual_rank ? 2 : 1);
+	return (1UL << (para.row_bits + para.bank_bits)) * para.page_size *
+	       (para.dual_rank ? 2 : 1);
 }