From: Michal Simek Date: Tue, 8 Sep 2015 15:07:01 +0000 (+0200) Subject: net: zynq: Fix MDC setting for zynq X-Git-Tag: v2016.01-rc2~243^2~2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=6777f3863044bf58082a3fdd67a890f2b5080e14;p=u-boot net: zynq: Fix MDC setting for zynq Based on spec: "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations)" Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47 which is above of 2.5MHz. Using 48 divider will give us correct setting according spec (111/48=2.31). Signed-off-by: Michal Simek Acked-by: Joe Hershberger --- diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 4db3ed4339..858093f0d7 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -58,7 +58,7 @@ #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */ +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ #ifdef CONFIG_ARM64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */