From: Kever Yang Date: Tue, 13 Jun 2017 02:03:11 +0000 (+0800) Subject: rockchip: clk: rk3036: correct setting for pll integer mode X-Git-Tag: v2017.07-rc3~32^2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=6a464d9cab63f5317bc914e2de52a4de98377743;p=u-boot rockchip: clk: rk3036: correct setting for pll integer mode According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll integer mode, while the '0' means the frac mode. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich Acked-by: Simon Glass Signed-off-by: Philipp Tomsich --- diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 28652df72d..5ecf5129d8 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -40,7 +40,7 @@ enum { #hz "Hz cannot be hit with PLL "\ "divisors on line " __stringify(__LINE__)); -/* use interge mode*/ +/* use integer mode*/ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); @@ -61,8 +61,8 @@ static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ); - /* use interger mode */ - rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); + /* use integer mode */ + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); rk_clrsetreg(&pll->con0, PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,