From: Prabhakar Kushwaha Date: Thu, 8 Mar 2018 10:00:24 +0000 (+0530) Subject: armv8: fsl-layerscape: Add support of GPIO structure X-Git-Tag: v2018.05-rc1~11^2~19 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=6b1373f2452a26b0c48ba8797d28e8c005016caf;p=u-boot armv8: fsl-layerscape: Add support of GPIO structure Layerscape Gen2 SoC supports GPIO registers to control GPIO signals. Adding support of GPIO structure to access GPIO registers. Signed-off-by: Pratiyush Srivastava Signed-off-by: Prabhakar Kushwaha Signed-off-by: Calvin Johnson Acked-by: Joe Hershberger --- diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 1ff5cac344..b1950054aa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -82,6 +82,11 @@ #define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000) #define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000) +#define GPIO1_BASE_ADDR (CONFIG_SYS_IMMR + 0x1300000) +#define GPIO2_BASE_ADDR (CONFIG_SYS_IMMR + 0x1310000) +#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) +#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) + #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) @@ -591,6 +596,16 @@ struct ccsr_serdes { u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ }; +struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; + u32 gpibe; +}; + /* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) #define SMMU_SCR1 (SMMU_BASE + 0x4)