From: Marian Balakowicz <m8@semihalf.com>
Date: Tue, 14 Mar 2006 15:12:48 +0000 (+0100)
Subject: Add sync in do_reset() routine for MPC83xx after RPR register
X-Git-Tag: LABEL_2006_04_18_1106~7^2~2^2~6
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=6d8ae5abb5311bd8e306a5a060dcfbeb0874a169;p=u-boot

Add sync in do_reset() routine for MPC83xx after RPR register
was written to. It is need on some targets when BAT translation
is enabled.
---

diff --git a/CHANGELOG b/CHANGELOG
index 304ea23f79..f4819235a8 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,10 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
 
+* Add sync in do_reset() routine for MPC83xx after RPR register
+  was written to. It is need on some targets when BAT translation
+  is enabled.
+
 * Add bit definitions for MPC83xx DDR controller registers.
 
 * Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index e49e4fe0ee..63f82422f5 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -93,6 +93,8 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 	/* enable Reset Control Reg */
 	immap->reset.rpr = 0x52535445;
+	__asm__ __volatile__ ("sync");
+	__asm__ __volatile__ ("isync");
 
 	/* confirm Reset Control Reg is enabled */
 	while(!((immap->reset.rcer) & RCER_CRE));