From: Janne Grunau <j@jannau.net>
Date: Sun, 16 Feb 2014 20:57:18 +0000 (+0100)
Subject: ARM: OMAP4: fix DDR timings for OMAP4430 ES2.0
X-Git-Tag: v2014.04-rc2~72^2~5^2~7
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=6e2192a3d80b315d071dfe0cbb70a35fe0a262e9;p=u-boot

ARM: OMAP4: fix DDR timings for OMAP4430 ES2.0

DDR timings were broken since 47abc3df701d8bc26f311350aa523fc1d0f8ad4e
for PandaBoard EA1.

Signed-off-by: Janne Grunau <j@jannau.net>
---

diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 4dec73e9ec..029533c851 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -172,6 +172,20 @@ struct dplls omap4430_dplls_es1 = {
 	.ddr = NULL
 };
 
+struct dplls omap4430_dplls_es20 = {
+	.mpu = mpu_dpll_params_1200mhz,
+	.core = core_dpll_params_es2_1600mhz_ddr200mhz,
+	.per = per_dpll_params_1536mhz,
+	.iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+	.abe = abe_dpll_params_sysclk_196608khz,
+#else
+	.abe = &abe_dpll_params_32k_196608khz,
+#endif
+	.usb = usb_dpll_params_1920mhz,
+	.ddr = NULL
+};
+
 struct dplls omap4430_dplls = {
 	.mpu = mpu_dpll_params_1200mhz,
 	.core = core_dpll_params_1600mhz,
@@ -413,6 +427,10 @@ void hw_data_init(void)
 	break;
 
 	case OMAP4430_ES2_0:
+	*dplls_data = &omap4430_dplls_es20;
+	*omap_vcores = &omap4430_volts;
+	break;
+
 	case OMAP4430_ES2_1:
 	case OMAP4430_ES2_2:
 	case OMAP4430_ES2_3: