From: richardbarry Date: Wed, 4 Sep 2013 16:03:31 +0000 (+0000) Subject: Rename directories with XMC4500 in their name that now contain XMC4200 and XMC4000... X-Git-Tag: V7.5.3~41 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=6e811e7c3fcf598fbd49d9d709064fa0131c67cd;p=freertos Rename directories with XMC4500 in their name that now contain XMC4200 and XMC4000 build configurations to instead say XMC4000. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2025 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/FreeRTOSConfig.h new file mode 100644 index 000000000..51df1616b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/FreeRTOSConfig.h @@ -0,0 +1,200 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* Ensure stdint is only used by the compiler, and not the assembler. */ +#ifdef __ICCARM__ + #include + extern uint32_t SystemCoreClock; +#endif /* __ICCARM__ */ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_QUEUE_SETS 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 6 /* 63 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +/* Demo application specific settings. */ +#ifdef __ICCARM__ + #if defined( PART_XMC4500 ) + /* Hardware includes. */ + #include "XMC4500.h" + #include "System_XMC4500.h" + + /* Configure pin P3.9 for the LED. */ + #define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 ) + /* To toggle the single LED */ + #define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 ) + #elif defined( PART_XMC4400 ) + /* Hardware includes. */ + #include "XMC4400.h" + #include "System_XMC4200.h" + + /* Configure pin P5.2 for the LED. */ + #define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 ) + /* To toggle the single LED */ + #define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 ) + #elif defined( PART_XMC4200 ) + /* Hardware includes. */ + #include "XMC4200.h" + #include "System_XMC4200.h" + + /* Configure pin P2.1 for the LED. */ + #define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL + /* To toggle the single LED */ + #define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 ) + #else + #error Part number not specified in project options + #endif +#endif + +#endif /* FREERTOS_CONFIG_H */ + diff --git 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$TOOLKIT_DIR$\plugins\rtos\uCOS-III\uCOS-III-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin + 0 + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/RTOSDemo.ewp b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/RTOSDemo.ewp new file mode 100644 index 000000000..402737146 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/RTOSDemo.ewp @@ -0,0 +1,2923 @@ + + + + 2 + + XMC4500 + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 29 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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$PROJ_DIR$\..\Common\Minimal\QueueOverwrite.c + + + $PROJ_DIR$\..\Common\Minimal\QueueSet.c + + + $PROJ_DIR$\..\Common\Minimal\recmutex.c + + + $PROJ_DIR$\..\Common\Minimal\sp_flop.c + + + + FreeRTOS_Source + + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_4.c + + + $PROJ_DIR$\..\..\Source\list.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\port.c + + + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM4F\portasm.s + + + $PROJ_DIR$\..\..\Source\queue.c + + + $PROJ_DIR$\..\..\Source\tasks.c + + + $PROJ_DIR$\..\..\Source\timers.c + + + + System + + $PROJ_DIR$\system\startup_XMC4200.s + + XMC4500 + XMC4400 + + + + $PROJ_DIR$\system\startup_XMC4400.s + + XMC4500 + XMC4200 + + + + $PROJ_DIR$\system\startup_XMC4500.s + + XMC4200 + XMC4400 + + + + $PROJ_DIR$\system\System_XMC4200.c + + XMC4500 + XMC4400 + + + + $PROJ_DIR$\system\System_XMC4400.c + + XMC4500 + XMC4200 + + + + $PROJ_DIR$\system\system_XMC4500.c + + XMC4200 + XMC4400 + + + + + $PROJ_DIR$\FreeRTOSConfig.h + + + $PROJ_DIR$\main.c + + + $PROJ_DIR$\main_blinky.c + + + $PROJ_DIR$\main_full.c + + + $PROJ_DIR$\RegTest.s + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/RTOSDemo.eww new file mode 100644 index 000000000..239a9381e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/RTOSDemo.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\RTOSDemo.ewp + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/RegTest.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/RegTest.s new file mode 100644 index 000000000..45105d369 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/RegTest.s @@ -0,0 +1,525 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#include + + + RSEG CODE:CODE(2) + thumb + + EXTERN ulRegTest1LoopCounter + EXTERN ulRegTest2LoopCounter + + PUBLIC vRegTest1Task + PUBLIC vRegTest2Task + PUBLIC vRegTestClearFlopRegistersToParameterValue + PUBLIC ulRegTestCheckFlopRegistersContainParameterValue + +/*-----------------------------------------------------------*/ + +vRegTest1Task + + /* Fill the core registers with known values. */ + mov r0, #100 + mov r1, #101 + mov r2, #102 + mov r3, #103 + mov r4, #104 + mov r5, #105 + mov r6, #106 + mov r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + /* Fill the VFP registers with known values. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + +reg1_loop: + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d1 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d2 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d3 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + vmov r0, r1, d4 + cmp r0, #108 + bne reg1_error_loopf + cmp r1, #109 + bne reg1_error_loopf + vmov r0, r1, d5 + cmp r0, #110 + bne reg1_error_loopf + cmp r1, #111 + bne reg1_error_loopf + vmov r0, r1, d6 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d7 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d8 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d9 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + vmov r0, r1, d10 + cmp r0, #108 + bne reg1_error_loopf + cmp r1, #109 + bne reg1_error_loopf + vmov r0, r1, d11 + cmp r0, #110 + bne reg1_error_loopf + cmp r1, #111 + bne reg1_error_loopf + vmov r0, r1, d12 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d13 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d14 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d15 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg1_loopf_pass + +reg1_error_loopf + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg1_error_loopf + +reg1_loopf_pass + + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + cmp r8, #108 + bne reg1_error_loop + cmp r9, #109 + bne reg1_error_loop + cmp r10, #110 + bne reg1_error_loop + cmp r11, #111 + bne reg1_error_loop + cmp r12, #112 + bne reg1_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + +/*-----------------------------------------------------------*/ + + +vRegTest2Task + + /* Set all the core registers to known values. */ + mov r0, #-1 + mov r1, #1 + mov r2, #2 + mov r3, #3 + mov r4, #4 + mov r5, #5 + mov r6, #6 + mov r7, #7 + mov r8, #8 + mov r9, #9 + mov r10, #10 + mov r11, #11 + mov r12, #12 + + /* Set all the VFP to known values. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + +reg2_loop: + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d1 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d2 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d3 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + vmov r0, r1, d4 + cmp r0, #8 + bne reg2_error_loopf + cmp r1, #9 + bne reg2_error_loopf + vmov r0, r1, d5 + cmp r0, #10 + bne reg2_error_loopf + cmp r1, #11 + bne reg2_error_loopf + vmov r0, r1, d6 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d7 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d8 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d9 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + vmov r0, r1, d10 + cmp r0, #8 + bne reg2_error_loopf + cmp r1, #9 + bne reg2_error_loopf + vmov r0, r1, d11 + cmp r0, #10 + bne reg2_error_loopf + cmp r1, #11 + bne reg2_error_loopf + vmov r0, r1, d12 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d13 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d14 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d15 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg2_loopf_pass + +reg2_error_loopf + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg2_error_loopf + +reg2_loopf_pass + + cmp r0, #-1 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + cmp r8, #8 + bne reg2_error_loop + cmp r9, #9 + bne reg2_error_loop + cmp r10, #10 + bne reg2_error_loop + cmp r11, #11 + bne reg2_error_loop + cmp r12, #12 + bne reg2_error_loop + + /* Increment the loop counter to indicate this test is still functioning + correctly. */ + push { r0-r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ + lsl r0, r0, #28 /* Shift to PendSV bit */ + str r0, [r1] + dsb + + pop { r0-r1 } + + /* Start again. */ + b reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + This loop ensures the loop counter variable stops incrementing. */ + b reg2_error_loop + +/*-----------------------------------------------------------*/ + +vRegTestClearFlopRegistersToParameterValue + + /* Clobber the auto saved registers. */ + vmov d0, r0, r0 + vmov d1, r0, r0 + vmov d2, r0, r0 + vmov d3, r0, r0 + vmov d4, r0, r0 + vmov d5, r0, r0 + vmov d6, r0, r0 + vmov d7, r0, r0 + bx lr + +/*-----------------------------------------------------------*/ + +ulRegTestCheckFlopRegistersContainParameterValue + + vmov r1, s0 + cmp r0, r1 + bne return_error + vmov r1, s1 + cmp r0, r1 + bne return_error + vmov r1, s2 + cmp r0, r1 + bne return_error + vmov r1, s3 + cmp r0, r1 + bne return_error + vmov r1, s4 + cmp r0, r1 + bne return_error + vmov r1, s5 + cmp r0, r1 + bne return_error + vmov r1, s6 + cmp r0, r1 + bne return_error + vmov r1, s7 + cmp r0, r1 + bne return_error + vmov r1, s8 + cmp r0, r1 + bne return_error + vmov r1, s9 + cmp r0, r1 + bne return_error + vmov r1, s10 + cmp r0, r1 + bne return_error + vmov r1, s11 + cmp r0, r1 + bne return_error + vmov r1, s12 + cmp r0, r1 + bne return_error + vmov r1, s13 + cmp r0, r1 + bne return_error + vmov r1, s14 + cmp r0, r1 + bne return_error + vmov r1, s15 + cmp r0, r1 + bne return_error + +return_pass + mov r0, #1 + bx lr + +return_error + mov r0, #0 + bx lr + + END + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/XMC4500_Flash.icf b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/XMC4500_Flash.icf new file mode 100644 index 000000000..7c7a4f309 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/XMC4500_Flash.icf @@ -0,0 +1,41 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x0C000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0C0FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __DRAM1_start__ = 0x20000000; +define symbol __DRAM1_end__ = 0x20007FFF; + +define symbol __DRAM2_start__ = 0x30000000; +define symbol __DRAM2_end__ = 0x30007FFF; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region DRAM1_region = mem:[from __DRAM1_start__ to __DRAM1_end__]; +define region DRAM2_region = mem:[from __DRAM2_start__ to __DRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region {readonly}; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; +place in DRAM1_region{ section .dram1}; +place in DRAM2_region{ section .dram2}; + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main.c new file mode 100644 index 000000000..9dfc362fd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main.c @@ -0,0 +1,239 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup and FreeRTOS hook functions. + * + * + * Additional code: + * + * This demo does not contain a non-kernel interrupt service routine that + * can be used as an example for application writers to use as a reference. + * Therefore, the framework of a dummy (not installed) handler is provided + * in this file. The dummy function is called Dummy_IRQHandler(). Please + * ensure to read the comments in the function itself, but more importantly, + * the notes on the function contained on the documentation page for this demo + * that is found on the FreeRTOS.org web site. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Standard demo includes. */ +#include "QueueSet.h" +#include "QueueOverwrite.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ + +/* + * Set up the hardware ready to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +extern void main_blinky( void ); +extern void main_full( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + configCONFIGURE_LED(); + + /* Ensure all priority bits are assigned as preemption priority bits. */ + NVIC_SetPriorityGrouping( 0 ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* vApplicationMallocFailedHook() will only be called if + configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + function that will get called if a call to pvPortMalloc() fails. + pvPortMalloc() is called internally by the kernel whenever a task, queue, + timer or semaphore is created. It is also called by various parts of the + demo application. If heap_1.c or heap_2.c are used, then the size of the + heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + to query the size of free heap space that remains (although it does not + provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + task. It is essential that code added to this hook function never attempts + to block in any way (for example, call xQueueReceive() with a block time + specified, or call vTaskDelay()). If the application makes use of the + vTaskDelete() API function (as this demo application does) then it is also + important that vApplicationIdleHook() is permitted to return to its calling + function, because it is the responsibility of the idle task to clean up + memory allocated by the kernel to any task that has since been deleted. */ +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + /* This function will be called by each tick interrupt if + configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + added here, but the tick hook is called from an interrupt context, so + code must not attempt to block, and only the interrupt safe FreeRTOS API + functions can be used (those that end in FromISR()). */ + + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* Write to a queue that is in use as part of the queue set demo to + demonstrate using queue sets from an ISR. */ + vQueueSetAccessQueueSetFromISR(); + + /* Test the ISR safe queue overwrite functions. */ + vQueueOverwritePeriodicISRDemo(); + } + #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ +} +/*-----------------------------------------------------------*/ + +#ifdef JUST_AN_EXAMPLE_ISR + +void Dummy_IRQHandler(void) +{ +long lHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt if necessary. */ + Dummy_ClearITPendingBit(); + + /* This interrupt does nothing more than demonstrate how to synchronise a + task with an interrupt. A semaphore is used for this purpose. Note + lHigherPriorityTaskWoken is initialised to zero. */ + xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); + + /* If there was a task that was blocked on the semaphore, and giving the + semaphore caused the task to unblock, and the unblocked task has a priority + higher than the current Running state task (the task that this interrupt + interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE + internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the + portEND_SWITCHING_ISR() macro will result in a context switch being pended to + ensure this interrupt returns directly to the unblocked, higher priority, + task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ + portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); +} + +#endif /* JUST_AN_EXAMPLE_ISR */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_blinky.c new file mode 100644 index 000000000..83d8398d8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_blinky.c @@ -0,0 +1,232 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles the LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_RATE_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* Values passed to the two tasks just to check the task parameter +functionality. */ +#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) +#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) + +/*-----------------------------------------------------------*/ + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/* + * Called by main() to create the simply blinky style application if + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + */ +void main_blinky( void ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static xQueueHandle xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +portTickType xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. + The block time is specified in ticks, the constant used converts ticks + to ms. While in the Blocked state this task will not consume any CPU + time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + configTOGGLE_LED(); + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_full.c new file mode 100644 index 000000000..29c5be7bd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/main_full.c @@ -0,0 +1,297 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the comprehensive test and demo version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + ****************************************************************************** + * + * main_full() creates all the demo application tasks and a software timer, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" timer - The check software timer period is initially set to three + * seconds. The callback function associated with the check software timer + * checks that all the standard demo tasks, and the register check tasks, are + * not only still executing, but are executing without reporting any errors. If + * the check software timer discovers that a task has either stalled, or + * reported an error, then it changes its own execution period from the initial + * three seconds, to just 200ms. The check software timer callback function + * also toggles the single LED each time it is called. This provides a visual + * indication of the system status: If the LED toggles every three seconds, + * then no issues have been discovered. If the LED toggles every 200ms, then + * an issue has been discovered with at least one task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "QueueSet.h" +#include "QueueOverwrite.h" + +/* Priorities for the demo application tasks. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_RATE_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_RATE_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS ) + +/*-----------------------------------------------------------*/ + +/* + * The check timer callback function, as described at the top of this file. + */ +static void prvCheckTimerCallback( xTimerHandle xTimer ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the FPU registers, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly file. + */ +extern void vRegTest1Task( void *pvParameters ); +extern void vRegTest2Task( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check software timer. If the variables keep +incrementing, then the register check tasks has not discovered any errors. If +a variable stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ +xTimerHandle xCheckTimer = NULL; + + /* Start all the other standard demo/test tasks. The have not particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartQueueSetTasks(); + vStartQueueOverwriteTask( tskIDLE_PRIORITY ); + vStartDynamicPriorityTasks(); + vCreateBlockTimeTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + + /* Create the register check tasks, as described at the top of this + file */ + xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + + /* Create the software timer that performs the 'check' functionality, + as described at the top of this file. */ + xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + if( xCheckTimer != NULL ) + { + xTimerStart( xCheckTimer, mainDONT_BLOCK ); + } + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following line + will never be reached. If the following line does execute, then there was + insufficient FreeRTOS heap memory available for the idle and/or timer tasks + to be created. See the memory management section on the FreeRTOS web site + for more details. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTimerCallback( xTimerHandle xTimer ) +{ +static long lChangedTimerPeriodAlready = pdFALSE; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreQueueSetTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound = pdTRUE; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound = pdTRUE; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + everything is ok. A faster toggle indicates an error. */ + configTOGGLE_LED(); + + /* Have any errors been latch in ulErrorFound? If so, shorten the + period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + This will result in an increase in the rate at which mainCHECK_LED + toggles. */ + if( ulErrorFound != pdFALSE ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + Functions called from inside of a timer callback function must + *never* attempt to block. */ + xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/System_XMC4200.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/System_XMC4200.c new file mode 100644 index 000000000..d2385b4b1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/System_XMC4200.c @@ -0,0 +1,708 @@ +/**************************************************************************//** + * @file system_XMC4200.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4000 Device Series + * @version V3.0.1 Alpha + * @date 26. September 2012 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include +#include + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 +#define SCU_CLOCK_BACK_UP_FACTORY 2 +#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 + + +#define HIB_CLOCK_FOSI 1 +#define HIB_CLOCK_OSCULP 2 + + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 +/* not avalible in config wizzard*/ +/* +* mandatory clock parameters ************************************************** +* +* source for clock generation +* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) +* +**************************************************************************************/ +// Selection of imput lock for PLL +/*************************************************************************************/ +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC + +/*************************************************************************************/ +// Standby clock selection for Backup clock source trimming +/*************************************************************************************/ +#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP +//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI + +/*************************************************************************************/ +// Global clock parameters +/*************************************************************************************/ +#define CLOCK_FSYS 80000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define CLOCK_BACK_UP 24000000 + +/*************************************************************************************/ +/* OSC_HP setup parameters */ +/*************************************************************************************/ +#define SCU_OSC_HP_MODE 0xF0 +#define SCU_OSCHPWDGDIV 2 + +/*************************************************************************************/ +/* MAIN PLL setup parameters */ +/*************************************************************************************/ +//Divider settings for external crystal @ 12 MHz +/*************************************************************************************/ +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K2DIV 5 +#define SCU_PLL_PDIV 1 +#define SCU_PLL_NDIV 79 + +/*************************************************************************************/ +//Divider settings for use of backup clock source trimmed +/*************************************************************************************/ +//#define SCU_PLL_K1DIV 1 +//#define SCU_PLL_K2DIV 5 +//#define SCU_PLL_PDIV 3 +//#define SCU_PLL_NDIV 79 +/*************************************************************************************/ + + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 +/* not avalible in config wizzard*/ +#define SCU_USBPLL_PDIV 0 +#define SCU_USBPLL_NDIV 31 +#define SCU_USBDIV 3 + +/*--------------------- Flash Wait State Configuration ------------------------------- +// +// Flash Wait State Configuration +// Flash Wait State +// <0=> 3 WS +// <1=> 4 WS +// <2=> 5 WS +// <3=> 6 WS +// +// +*/ + +#define PMU_FLASH 1 +#define PMU_FLASH_WS 0x00000000 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> Divided value of USB PLL output +// <3=> Divided value of PLL Clock +// Clockout divider <1-10><#-1> +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000000 +#define SCU_CLOCKOUT_DIV 0x00000009 +#define SCU_CLOCKOUT_PIN 0x00000001 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +#if SCU_CLOCK_SETUP +uint32_t SystemCoreClock = CLOCK_FSYS; +#else +uint32_t SystemCoreClock = CLOCK_BACK_UP; +#endif + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void); +#endif + +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void); +#endif + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +int temp; + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + +/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ +SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + +/* Setup the WDT */ +#if WDT_SETUP + +WDT->CTR &= ~WDTENB_nVal; + +#endif + + +/* Setup the Flash Wait State */ +#if PMU_FLASH +temp = FLASH0->FCON; +temp &= ~FLASH_FCON_WSPFLASH_Msk; +temp |= PMU_FLASH_WS+3; +FLASH0->FCON = temp; +#endif + + +/* Setup the clockout */ +#if SCU_CLOCKOUT_SETUP + +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; +/*set PLL div for clkout */ +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; + +if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ + } +else { + PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ + } + +#endif + + +/* Setup the System clock */ +#if SCU_CLOCK_SETUP +SystemClockSetup(); +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ + + +/* Setup the USB PL */ +#if SCU_USB_CLOCK_SETUP +USBClockSetup(); +#endif + + + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ +unsigned int PDIV; +unsigned int NDIV; +unsigned int K2DIV; +unsigned int long VCO; + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +if (SCU_CLK->SYSCLKCR == 0x00010000) +{ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ + /* check if PLL is locked */ + /* read back divider settings */ + PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; + NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; + K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; + + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ + /* the selected clock is the Backup clock fofi */ + VCO = (CLOCK_BACK_UP/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + + } + else + { + /* the selected clock is the PLL external oscillator */ + VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + } + + + } +} +else +{ +SystemCoreClock = CLOCK_BACK_UP; +} + + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void) +{ +int temp; +unsigned int long VCO; +int stepping_K2DIV; + +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +} + +/* Enable OSC_HP if not already on*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + /********************************************************************************************************************/ + /* Use external crystal for PLL clock input */ + /********************************************************************************************************************/ + + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) + { + /********************************************************************************************************************/ + /* Use factory trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) + { + /********************************************************************************************************************/ + /* Use automatic trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* check for HIB Domain enabled */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ + + /* check for HIB Domain is not in reset state */ + if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ + + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) + { + /****************************************************************************************************************/ + /* Use fOSI as source of the standby clock */ + /****************************************************************************************************************/ + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + } + else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) + { + /****************************************************************************************************************/ + /* Use fULP as source of the standby clock */ + /****************************************************************************************************************/ + /*check OSCUL if running correct*/ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); + + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ + /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ + /* select OSCUL clock for RTC*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*enable OSCULP WDG Alarm Enable*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*wait now for clock is stable */ + do + { + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + for(temp=0;temp<=0xFFFF;temp++); + } + while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); + + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + } + // now OSCULP is running and can be used + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + } + } + + /********************************************************************************************************************/ + /* Setup and look the main PLL */ + /********************************************************************************************************************/ + +if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ + /* Systen is still running from internal clock */ + /* select FOFI as system clock */ + if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ + + + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/24000000)-1; + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + /* setup time out loop */ + /* Timeout for wait loo ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + + if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + } + else return(0); + + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /* we may have to reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /*********************************************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 60MHz + *********************************************************/ + if (CLOCK_FSYS > 60000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/60000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 90MHz + *********************************************************/ + if (CLOCK_FSYS > 90000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/90000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + } + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void) +{ +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* check and if not already running enable OSC_HP */ + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + /* check if Main PLL is switched on for OSC WD*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); + /* Setup USBDIV settings USB clock */ + SCU_CLK->USBCLKCR = SCU_USBDIV; + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/System_XMC4400.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/System_XMC4400.c new file mode 100644 index 000000000..70162d923 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/System_XMC4400.c @@ -0,0 +1,707 @@ +/**************************************************************************//** + * @file system_XMC4400.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4500 Device Series + * @version V3.0.1 Alpha + * @date 17. September 2012 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include +#include + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 +#define SCU_CLOCK_BACK_UP_FACTORY 2 +#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 + + +#define HIB_CLOCK_FOSI 1 +#define HIB_CLOCK_OSCULP 2 + + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 +/* not avalible in config wizzard*/ +/* +* mandatory clock parameters ************************************************** +* +* source for clock generation +* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) +* +**************************************************************************************/ +// Selection of imput lock for PLL +/*************************************************************************************/ +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC + +/*************************************************************************************/ +// Standby clock selection for Backup clock source trimming +/*************************************************************************************/ +#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP +//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI + +/*************************************************************************************/ +// Global clock parameters +/*************************************************************************************/ +#define CLOCK_FSYS 120000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define CLOCK_BACK_UP 24000000 + +/*************************************************************************************/ +/* OSC_HP setup parameters */ +/*************************************************************************************/ +#define SCU_OSC_HP_MODE 0xF0 +#define SCU_OSCHPWDGDIV 2 + +/*************************************************************************************/ +/* MAIN PLL setup parameters */ +/*************************************************************************************/ +//Divider settings for external crystal @ 12 MHz +/*************************************************************************************/ +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K2DIV 3 +#define SCU_PLL_PDIV 1 +#define SCU_PLL_NDIV 79 + +/*************************************************************************************/ +//Divider settings for use of backup clock source trimmed +/*************************************************************************************/ +//#define SCU_PLL_K1DIV 1 +//#define SCU_PLL_K2DIV 3 +//#define SCU_PLL_PDIV 3 +//#define SCU_PLL_NDIV 79 +/*************************************************************************************/ + + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 +/* not avalible in config wizzard*/ +#define SCU_USBPLL_PDIV 0 +#define SCU_USBPLL_NDIV 31 +#define SCU_USBDIV 3 + +/*--------------------- Flash Wait State Configuration ------------------------------- +// +// Flash Wait State Configuration +// Flash Wait State +// <0=> 3 WS +// <1=> 4 WS +// <2=> 5 WS +// <3=> 6 WS +// +// +*/ + +#define PMU_FLASH 1 +#define PMU_FLASH_WS 0x00000000 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> Divided value of USB PLL output +// <3=> Divided value of PLL Clock +// Clockout divider <1-10><#-1> +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000000 +#define SCU_CLOCKOUT_DIV 0x00000009 +#define SCU_CLOCKOUT_PIN 0x00000001 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +#if SCU_CLOCK_SETUP +uint32_t SystemCoreClock = CLOCK_FSYS; +#else +uint32_t SystemCoreClock = CLOCK_BACK_UP; +#endif + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void); +#endif + +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void); +#endif + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +int temp; + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + +/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ +SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + +/* Setup the WDT */ +#if WDT_SETUP + +WDT->CTR &= ~WDTENB_nVal; + +#endif + + +/* Setup the Flash Wait State */ +#if PMU_FLASH +temp = FLASH0->FCON; +temp &= ~FLASH_FCON_WSPFLASH_Msk; +temp |= PMU_FLASH_WS+3; +FLASH0->FCON = temp; +#endif + + +/* Setup the clockout */ +#if SCU_CLOCKOUT_SETUP + +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; +/*set PLL div for clkout */ +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; + +if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ + } +else { + PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ + } + +#endif + + +/* Setup the System clock */ +#if SCU_CLOCK_SETUP +SystemClockSetup(); +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ + + +/* Setup the USB PL */ +#if SCU_USB_CLOCK_SETUP +USBClockSetup(); +#endif + + + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ +unsigned int PDIV; +unsigned int NDIV; +unsigned int K2DIV; +unsigned int long VCO; + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +if (SCU_CLK->SYSCLKCR == 0x00010000) +{ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ + /* check if PLL is locked */ + /* read back divider settings */ + PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; + NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; + K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; + + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ + /* the selected clock is the Backup clock fofi */ + VCO = (CLOCK_BACK_UP/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + + } + else + { + /* the selected clock is the PLL external oscillator */ + VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + } + + + } +} +else +{ +SystemCoreClock = CLOCK_BACK_UP; +} + + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void) +{ +int temp; +unsigned int long VCO; +int stepping_K2DIV; + +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +} + +/* Enable OSC_HP if not already on*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + /********************************************************************************************************************/ + /* Use external crystal for PLL clock input */ + /********************************************************************************************************************/ + + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) + { + /********************************************************************************************************************/ + /* Use factory trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) + { + /********************************************************************************************************************/ + /* Use automatic trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* check for HIB Domain enabled */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ + + /* check for HIB Domain is not in reset state */ + if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ + + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) + { + /****************************************************************************************************************/ + /* Use fOSI as source of the standby clock */ + /****************************************************************************************************************/ + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + } + else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) + { + /****************************************************************************************************************/ + /* Use fULP as source of the standby clock */ + /****************************************************************************************************************/ + /*check OSCUL if running correct*/ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); + + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ + /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ + /* select OSCUL clock for RTC*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*enable OSCULP WDG Alarm Enable*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*wait now for clock is stable */ + do + { + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + for(temp=0;temp<=0xFFFF;temp++); + } + while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); + + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + } + // now OSCULP is running and can be used + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + } + } + + /********************************************************************************************************************/ + /* Setup and look the main PLL */ + /********************************************************************************************************************/ + +if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ + /* Systen is still running from internal clock */ + /* select FOFI as system clock */ + if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ + + + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/24000000)-1; + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + /* setup time out loop */ + /* Timeout for wait loo ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + + if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + } + else return(0); + + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /* we may have to reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /*********************************************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 60MHz + *********************************************************/ + if (CLOCK_FSYS > 60000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/60000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 90MHz + *********************************************************/ + if (CLOCK_FSYS > 90000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/90000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + } + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void) +{ +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* check and if not already running enable OSC_HP */ + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + /* check if Main PLL is switched on for OSC WD*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); + /* Setup USBDIV settings USB clock */ + SCU_CLK->USBCLKCR = SCU_USBDIV; + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/XMC4200.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/XMC4200.h new file mode 100644 index 000000000..3984b45cb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/XMC4200.h @@ -0,0 +1,13138 @@ + +/****************************************************************************************************//** + * @file XMC4200.h + * + * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for + * XMC4200 from Infineon. + * + * @version V1.1.0 (Reference Manual v1.1) + * @date 10. January 2013 + * + * @note Generated with SVDConv V2.78b + * from CMSIS SVD File 'XMC4200_Processed_SVD.xml' Version 1.1.0 (Reference Manual v1.1), + *******************************************************************************************************/ + + + +/** @addtogroup Infineon + * @{ + */ + +/** @addtogroup XMC4200 + * @{ + */ + +#ifndef XMC4200_H +#define XMC4200_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* --------------------- XMC4200 Specific Interrupt Numbers --------------------- */ + SCU_0_IRQn = 0, /*!< 0 SCU_0 */ + ERU0_0_IRQn = 1, /*!< 1 ERU0_0 */ + ERU0_1_IRQn = 2, /*!< 2 ERU0_1 */ + ERU0_2_IRQn = 3, /*!< 3 ERU0_2 */ + ERU0_3_IRQn = 4, /*!< 4 ERU0_3 */ + ERU1_0_IRQn = 5, /*!< 5 ERU1_0 */ + ERU1_1_IRQn = 6, /*!< 6 ERU1_1 */ + ERU1_2_IRQn = 7, /*!< 7 ERU1_2 */ + ERU1_3_IRQn = 8, /*!< 8 ERU1_3 */ + PMU0_0_IRQn = 12, /*!< 12 PMU0_0 */ + VADC0_C0_0_IRQn = 14, /*!< 14 VADC0_C0_0 */ + VADC0_C0_1_IRQn = 15, /*!< 15 VADC0_C0_1 */ + VADC0_C0_2_IRQn = 16, /*!< 16 VADC0_C0_2 */ + VADC0_C0_3_IRQn = 17, /*!< 17 VADC0_C0_3 */ + VADC0_G0_0_IRQn = 18, /*!< 18 VADC0_G0_0 */ + VADC0_G0_1_IRQn = 19, /*!< 19 VADC0_G0_1 */ + VADC0_G0_2_IRQn = 20, /*!< 20 VADC0_G0_2 */ + VADC0_G0_3_IRQn = 21, /*!< 21 VADC0_G0_3 */ + VADC0_G1_0_IRQn = 22, /*!< 22 VADC0_G1_0 */ + VADC0_G1_1_IRQn = 23, /*!< 23 VADC0_G1_1 */ + VADC0_G1_2_IRQn = 24, /*!< 24 VADC0_G1_2 */ + VADC0_G1_3_IRQn = 25, /*!< 25 VADC0_G1_3 */ + DAC0_0_IRQn = 42, /*!< 42 DAC0_0 */ + DAC0_1_IRQn = 43, /*!< 43 DAC0_1 */ + CCU40_0_IRQn = 44, /*!< 44 CCU40_0 */ + CCU40_1_IRQn = 45, /*!< 45 CCU40_1 */ + CCU40_2_IRQn = 46, /*!< 46 CCU40_2 */ + CCU40_3_IRQn = 47, /*!< 47 CCU40_3 */ + CCU41_0_IRQn = 48, /*!< 48 CCU41_0 */ + CCU41_1_IRQn = 49, /*!< 49 CCU41_1 */ + CCU41_2_IRQn = 50, /*!< 50 CCU41_2 */ + CCU41_3_IRQn = 51, /*!< 51 CCU41_3 */ + CCU80_0_IRQn = 60, /*!< 60 CCU80_0 */ + CCU80_1_IRQn = 61, /*!< 61 CCU80_1 */ + CCU80_2_IRQn = 62, /*!< 62 CCU80_2 */ + CCU80_3_IRQn = 63, /*!< 63 CCU80_3 */ + POSIF0_0_IRQn = 68, /*!< 68 POSIF0_0 */ + POSIF0_1_IRQn = 69, /*!< 69 POSIF0_1 */ + HRPWM_0_IRQn = 72, /*!< 72 HRPWM_0 */ + HRPWM_1_IRQn = 73, /*!< 73 HRPWM_1 */ + HRPWM_2_IRQn = 74, /*!< 74 HRPWM_0 */ + HRPWM_3_IRQn = 75, /*!< 75 HRPWM_1 */ + CAN0_0_IRQn = 76, /*!< 76 CAN0_0 */ + CAN0_1_IRQn = 77, /*!< 77 CAN0_1 */ + CAN0_2_IRQn = 78, /*!< 78 CAN0_2 */ + CAN0_3_IRQn = 79, /*!< 79 CAN0_3 */ + CAN0_4_IRQn = 80, /*!< 80 CAN0_4 */ + CAN0_5_IRQn = 81, /*!< 81 CAN0_5 */ + CAN0_6_IRQn = 82, /*!< 82 CAN0_6 */ + CAN0_7_IRQn = 83, /*!< 83 CAN0_7 */ + USIC0_0_IRQn = 84, /*!< 84 USIC0_0 */ + USIC0_1_IRQn = 85, /*!< 85 USIC0_1 */ + USIC0_2_IRQn = 86, /*!< 86 USIC0_2 */ + USIC0_3_IRQn = 87, /*!< 87 USIC0_3 */ + USIC0_4_IRQn = 88, /*!< 88 USIC0_4 */ + USIC0_5_IRQn = 89, /*!< 89 USIC0_5 */ + USIC1_0_IRQn = 90, /*!< 90 USIC1_0 */ + USIC1_1_IRQn = 91, /*!< 91 USIC1_1 */ + USIC1_2_IRQn = 92, /*!< 92 USIC1_2 */ + USIC1_3_IRQn = 93, /*!< 93 USIC1_3 */ + USIC1_4_IRQn = 94, /*!< 94 USIC1_4 */ + USIC1_5_IRQn = 95, /*!< 95 USIC1_5 */ + LEDTS0_0_IRQn = 102, /*!< 102 LEDTS0_0 */ + FCE0_0_IRQn = 104, /*!< 104 FCE0_0 */ + GPDMA0_0_IRQn = 105, /*!< 105 GPDMA0_0 */ + USB0_0_IRQn = 107, /*!< 107 USB0_0 */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ +#define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4200.h" /*!< XMC4200 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4400.h" /*!< XMC4400 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< /*!< Cortex-M4 processor and core peripherals */ +#include "system_XMC4500.h" /*!< XMC4500 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ +/* Macro to modify desired bitfields of a register */ +#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ + ((uint32_t)mask)) | \ + (reg & ((uint32_t)~((uint32_t)mask))) + +/* Macro to modify desired bitfields of a register */ +#define WR_REG_SIZE(reg, mask, pos, val, size) { \ +uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ +uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ +uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ +uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ +reg = (uint##size##_t) (VAL2 | VAL4);\ +} + +/** Macro to read bitfields from a register */ +#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) + +/** Macro to read bitfields from a register */ +#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ + (uint32_t)mask) >> pos) ) + +/** Macro to set a bit in register */ +#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/system_XMC4400.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/system_XMC4400.h new file mode 100644 index 000000000..953e1b099 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/system_XMC4400.h @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file system_XMC4400.h + * @brief Header file for the XMC4400-Series systeminit + * + * @version V1.0 + * @date 17. August 2012 + * + * @note + * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. + * This file can be freely distributed within development tools that are supporting such microcontrollers. + + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * + ******************************************************************************/ + + +#ifndef __SYSTEM_XMC4400_H +#define __SYSTEM_XMC4400_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/system_XMC4500.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/system_XMC4500.c new file mode 100644 index 000000000..74ecf74d3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/system_XMC4500.c @@ -0,0 +1,705 @@ +/**************************************************************************//** + * @file system_XMC4500.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4500 Device Series + * @version V3.0.1 Alpha + * @date 17. September 2012 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "system_XMC4500.h" +#include + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 +#define SCU_CLOCK_BACK_UP_FACTORY 2 +#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 + + +#define HIB_CLOCK_FOSI 1 +#define HIB_CLOCK_OSCULP 2 + + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 +/* not avalible in config wizzard*/ +/* +* mandatory clock parameters ************************************************** +* +* source for clock generation +* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) +* +**************************************************************************************/ +// Selection of imput lock for PLL +/*************************************************************************************/ +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC + +/*************************************************************************************/ +// Standby clock selection for Backup clock source trimming +/*************************************************************************************/ +#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP +//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI + +/*************************************************************************************/ +// Global clock parameters +/*************************************************************************************/ +#define CLOCK_FSYS 120000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define CLOCK_BACK_UP 24000000 + +/*************************************************************************************/ +/* OSC_HP setup parameters */ +/*************************************************************************************/ +#define SCU_OSC_HP_MODE 0xF0 +#define SCU_OSCHPWDGDIV 2 + +/*************************************************************************************/ +/* MAIN PLL setup parameters */ +/*************************************************************************************/ +//Divider settings for external crystal @ 12 MHz +/*************************************************************************************/ +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K2DIV 3 +#define SCU_PLL_PDIV 1 +#define SCU_PLL_NDIV 79 + +/*************************************************************************************/ +//Divider settings for use of backup clock source trimmed +/*************************************************************************************/ +//#define SCU_PLL_K1DIV 1 +//#define SCU_PLL_K2DIV 3 +//#define SCU_PLL_PDIV 3 +//#define SCU_PLL_NDIV 79 +/*************************************************************************************/ + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 +/* not avalible in config wizzard*/ +#define SCU_USBPLL_PDIV 0 +#define SCU_USBPLL_NDIV 31 +#define SCU_USBDIV 3 + +/*--------------------- Flash Wait State Configuration ------------------------------- +// +// Flash Wait State Configuration +// Flash Wait State +// <0=> 3 WS +// <1=> 4 WS +// <2=> 5 WS +// <3=> 6 WS +// +// +*/ + +#define PMU_FLASH 1 +#define PMU_FLASH_WS 0x00000000 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> Divided value of USB PLL output +// <3=> Divided value of PLL Clock +// Clockout divider <1-10><#-1> +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000003 +#define SCU_CLOCKOUT_DIV 0x00000009 +#define SCU_CLOCKOUT_PIN 0x00000001 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +#if SCU_CLOCK_SETUP +uint32_t SystemCoreClock = CLOCK_FSYS; +#else +uint32_t SystemCoreClock = CLOCK_BACK_UP; +#endif + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void); +#endif + +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void); +#endif + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +int temp; + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + +/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ +SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + +/* Setup the WDT */ +#if WDT_SETUP + +WDT->CTR &= ~WDTENB_nVal; + +#endif + +/* Setup the Flash Wait State */ +#if PMU_FLASH +temp = FLASH0->FCON; +temp &= ~FLASH_FCON_WSPFLASH_Msk; +temp |= PMU_FLASH_WS+3; +FLASH0->FCON = temp; +#endif + + +/* Setup the clockout */ +#if SCU_CLOCKOUT_SETUP + +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; +/*set PLL div for clkout */ +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; + +if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ + } +else { + PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ + } + +#endif + + +/* Setup the System clock */ +#if SCU_CLOCK_SETUP +SystemClockSetup(); +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ + + +/* Setup the USB PL */ +#if SCU_USB_CLOCK_SETUP +USBClockSetup(); +#endif + + + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ +unsigned int PDIV; +unsigned int NDIV; +unsigned int K2DIV; +unsigned int long VCO; + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +if (SCU_CLK->SYSCLKCR == 0x00010000) +{ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ + /* check if PLL is locked */ + /* read back divider settings */ + PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; + NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; + K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; + + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ + /* the selected clock is the Backup clock fofi */ + VCO = (CLOCK_BACK_UP/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + + } + else + { + /* the selected clock is the PLL external oscillator */ + VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + } + + + } +} +else +{ +SystemCoreClock = CLOCK_BACK_UP; +} + + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void) +{ +int temp; +unsigned int long VCO; +int stepping_K2DIV; + +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +} + +/* Enable OSC_HP if not already on*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + /********************************************************************************************************************/ + /* Use external crystal for PLL clock input */ + /********************************************************************************************************************/ + + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) + { + /********************************************************************************************************************/ + /* Use factory trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) + { + /********************************************************************************************************************/ + /* Use automatic trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* check for HIB Domain enabled */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ + + /* check for HIB Domain is not in reset state */ + if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ + + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) + { + /****************************************************************************************************************/ + /* Use fOSI as source of the standby clock */ + /****************************************************************************************************************/ + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + } + else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) + { + /****************************************************************************************************************/ + /* Use fULP as source of the standby clock */ + /****************************************************************************************************************/ + /*check OSCUL if running correct*/ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); + + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ + /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ + /* select OSCUL clock for RTC*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*enable OSCULP WDG Alarm Enable*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*wait now for clock is stable */ + do + { + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + for(temp=0;temp<=0xFFFF;temp++); + } + while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); + + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + } + // now OSCULP is running and can be used + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + } + } + + /********************************************************************************************************************/ + /* Setup and look the main PLL */ + /********************************************************************************************************************/ + +if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ + /* Systen is still running from internal clock */ + /* select FOFI as system clock */ + if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ + + + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/24000000)-1; + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + /* setup time out loop */ + /* Timeout for wait loo ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + + if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + } + else return(0); + + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /* we may have to reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /*********************************************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 60MHz + *********************************************************/ + if (CLOCK_FSYS > 60000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/60000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 90MHz + *********************************************************/ + if (CLOCK_FSYS > 90000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/90000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + } + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void) +{ +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + + /* check if PLL is switched on */ +if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* check and if not already running enable OSC_HP */ + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + /* check if Main PLL is switched on for OSC WD*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); + /* Setup USBDIV settings USB clock */ + SCU_CLK->USBCLKCR = SCU_USBDIV; + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/system_XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/system_XMC4500.h new file mode 100644 index 000000000..73eb6d590 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_IAR/system/system_XMC4500.h @@ -0,0 +1,114 @@ +/**************************************************************************//** + * @file system_XMC4500.h + * @brief Header file for the XMC4500-Series systeminit + * + * @version V1.6 + * @date 23. October 2012 + * + * @note + * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. + * This file can be freely distributed within development tools that are supporting such microcontrollers. + + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * + ******************************************************************************/ + + +#ifndef __SYSTEM_XMC4500_H +#define __SYSTEM_XMC4500_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 + + + +/* + * mandatory clock parameters ************************************************** + */ +/* source for clock generation + * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) + * mandatory for old system_xmc4500.c files - please do not remove!!! + **************************************************************************************/ + +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +#define CLOCK_OSC_HP 24000000 +#define CLOCK_BACK_UP 24000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define SYSTEM_FREQUENCY 120000000 + +/* OSC_HP setup parameters */ +#define OSC_HP_MODE 0 +#define OSCHPWDGDIV 2 + +/* MAIN PLL setup parameters */ + + +#define PLL_K1DIV 1 +#define PLL_K2DIV 3 +#define PLL_PDIV 1 +#define PLL_NDIV 79 + + + +#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz +#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz +#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz + + + +#define USBPLL_PDIV 1 +#define USBPLL_NDIV 15 + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Dbg_Flash.ini b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Dbg_Flash.ini new file mode 100644 index 000000000..307511920 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Dbg_Flash.ini @@ -0,0 +1,2 @@ +_WDWORD(0xE0002008, 0x00000000); // Clear FPB 0 (FP_COMP0) + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Dbg_RAM TraceETM.ini b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Dbg_RAM TraceETM.ini new file mode 100644 index 000000000..4c624d397 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Dbg_RAM TraceETM.ini @@ -0,0 +1,36 @@ +/*---------------------------------------------------------------------------- + * Name: Dbg_RAM.ini + * Purpose: RAM Debug Initialization File + * Note(s): + *---------------------------------------------------------------------------- + * This file is part of the uVision/ARM development tools. + * This software may only be used under the terms of a valid, current, + * end user licence from KEIL for a compatible version of KEIL software + * development tools. Nothing else gives you the right to use this software. + * + * This software is supplied "AS IS" without warranties of any kind. + * + * Copyright (c) 2008-2011 Keil - An ARM Company. All rights reserved. + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Setup() configure PC & SP for RAM Debug + *----------------------------------------------------------------------------*/ +FUNC void Setup (void) { + SP = _RDWORD(0x10000000); // Setup Stack Pointer + PC = _RDWORD(0x10000004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x10000000); // Setup Vector Table Offset Register +} + +_WDWORD(0x5000413C, 0x001F3700); // Enable RAM + +_WDWORD(0x48028674, 0x00001405); // Enable ETM Pins P6 + +_WDWORD(0x48028274, 0x00401405); // Enable ETM Pins P2 + +LOAD %L INCREMENTAL // load the application + +Setup(); // Setup for Running + +/*g, main*/ + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Dbg_RAM.ini b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Dbg_RAM.ini new file mode 100644 index 000000000..832a6eb0c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Dbg_RAM.ini @@ -0,0 +1,32 @@ +/*---------------------------------------------------------------------------- + * Name: Dbg_RAM.ini + * Purpose: RAM Debug Initialization File + * Note(s): + *---------------------------------------------------------------------------- + * This file is part of the uVision/ARM development tools. + * This software may only be used under the terms of a valid, current, + * end user licence from KEIL for a compatible version of KEIL software + * development tools. Nothing else gives you the right to use this software. + * + * This software is supplied "AS IS" without warranties of any kind. + * + * Copyright (c) 2008-2011 Keil - An ARM Company. All rights reserved. + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Setup() configure PC & SP for RAM Debug + *----------------------------------------------------------------------------*/ +FUNC void Setup (void) { + SP = _RDWORD(0x10000000); // Setup Stack Pointer + PC = _RDWORD(0x10000004); // Setup Program Counter + _WDWORD(0xE000ED08, 0x10000000); // Setup Vector Table Offset Register +} + +_WDWORD(0x5000413C, 0x001F3700); // Enable RAM + +LOAD %L INCREMENTAL // load the application + +Setup(); // Setup for Running + +/*g, main*/ + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/FreeRTOSConfig.h new file mode 100644 index 000000000..e1e30d39c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/FreeRTOSConfig.h @@ -0,0 +1,196 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#include +extern uint32_t SystemCoreClock; + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 6 /* 63 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define vPortSVCHandler SVC_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + + +/* Demo application specific settings. */ +#if defined( PART_XMC4500 ) + /* Hardware includes. */ + #include "XMC4500.h" + #include "System_XMC4500.h" + + /* Configure pin P3.9 for the LED. */ + #define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 ) + /* To toggle the single LED */ + #define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 ) +#elif defined( PART_XMC4400 ) + /* Hardware includes. */ + #include "XMC4400.h" + #include "System_XMC4200.h" + + /* Configure pin P5.2 for the LED. */ + #define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 ) + /* To toggle the single LED */ + #define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 ) +#elif defined( PART_XMC4200 ) + /* Hardware includes. */ + #include "XMC4200.h" + #include "System_XMC4200.h" + + /* Configure pin P2.1 for the LED. */ + #define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL + /* To toggle the single LED */ + #define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 ) +#else + #error Part number not specified in project options +#endif + + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RTOSDemo.uvopt b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RTOSDemo.uvopt new file mode 100644 index 000000000..c03a8bbea --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RTOSDemo.uvopt @@ -0,0 +1,1047 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + RTOSDemo - XMC4500 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 0 + + 255 + + + 0 + Data Sheet + DATASHTS\Infineon\XMC4500\xmc4500_ds.pdf + + + 1 + User Manual + DATASHTS\Infineon\XMC4500\xmc4500_um.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF + + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 1 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + DLGDARM + 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+ + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=120,149,354,683,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + DLGUARM + (105=-1,-1,-1,-1,0) + + + 0 + ULP2CM3 + -UP1048084 -O143 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(001DB083) -L01(8) -TO18 -TC10000000 -TP28 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000 + + + 0 + UL2CM3 + -UM0356BUE -O751 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO16 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FN2 -FC800 -FD20000000 -FF0XMC4500_1024 -FF1XMC4500c_1024 -FL0100000 -FL1100000 -FS0C000000 -FS18000000 + + + + + + 0 + 1 + xTickCount + + + + + 1 + 5 + 0x0C000000 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + RTOSDemo - XMC4400 + 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-FS0C000000 -FL040000 + + + 0 + DLGDARM + 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+ 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\Infineon\XMC4200-4100\XMC4200-4100_ds.pdf + + + 1 + User Manual + DATASHTS\Infineon\XMC4200-4100\XMC4200-4100_ds.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF + + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 7 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U591000435 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8009 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC4200_4100_256 -FS0C000000 -FL040000 + + + 0 + DLGDARM + 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+ + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + DLGUARM + / + + + 0 + ULP2CM3 + -UP1048084 -O143 -S0 -C0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(001DB083) -L01(8) -TO18 -TC10000000 -TP28 -TDX0 -TDD0 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0XMC4500 -FS0C000000 -FL0100000 -FF1XMC4500c -FS18000000 -FL1100000 + + + 0 + UL2CM3 + -FD20000000 -FC800 -FN2 -FF0XMC4200_4100_256 -FS0C000000 -FL040000 -FF1XMC4200_4100c_256 -FS18000000 -FL140000) + + + + + + 1 + 5 + 0x0C000000 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Startup + 0 + 0 + 0 + 0 + + 1 + 1 + 2 + 0 + 0 + 61 + 0 + 0 + 0 + 0 + .\startup_XMC4500.s + startup_XMC4500.s + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\System_XMC4500.c + System_XMC4500.c + 0 + 0 + + + 1 + 3 + 2 + 0 + 0 + 0 + 0 + 279 + 288 + 0 + .\startup_XMC4200.s + startup_XMC4200.s + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\system_XMC4200.c + system_XMC4200.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 20 + 0 + 0 + 0 + 0 + .\system_XMC4400.c + system_XMC4400.c + 0 + 0 + + + 1 + 6 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup_XMC4400.s + startup_XMC4400.s + 0 + 0 + + + + + Demo_Source + 1 + 0 + 0 + 0 + + 2 + 7 + 1 + 0 + 0 + 4 + 0 + 113 + 140 + 0 + .\main.c + main.c + 0 + 0 + + + 2 + 8 + 5 + 0 + 0 + 34 + 0 + 143 + 187 + 0 + .\FreeRTOSConfig.h + FreeRTOSConfig.h + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + 0 + 367 + 418 + 0 + .\RegTest.c + RegTest.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 16 + 0 + 241 + 274 + 0 + .\main_full.c + main_full.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + 0 + 123 + 141 + 0 + .\main_blinky.c + main_blinky.c + 0 + 0 + + + + + FreeRTOS_Source + 0 + 0 + 0 + 0 + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\timers.c + timers.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\list.c + list.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\queue.c + queue.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\tasks.c + tasks.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\portable\RVDS\ARM_CM4F\port.c + port.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\Source\portable\MemMang\heap_4.c + heap_4.c + 0 + 0 + + + + + Common_Demo_Source + 1 + 0 + 0 + 0 + + 4 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\semtest.c + semtest.c + 0 + 0 + + + 4 + 19 + 1 + 0 + 0 + 0 + 0 + 195 + 203 + 0 + ..\Common\Minimal\sp_flop.c + sp_flop.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\blocktim.c + blocktim.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\countsem.c + countsem.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\dynamic.c + dynamic.c + 0 + 0 + + + 4 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\GenQTest.c + GenQTest.c + 0 + 0 + + + 4 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\Common\Minimal\recmutex.c + recmutex.c + 0 + 0 + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RTOSDemo.uvproj b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RTOSDemo.uvproj new file mode 100644 index 000000000..a9854674f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RTOSDemo.uvproj @@ -0,0 +1,2036 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + RTOSDemo - XMC4500 + 0x4 + ARM-ADS + + + XMC4500-1024 + Infineon + IRAM(0x20000000-0x2000FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x0C000000-0x0C0FFFFF) IROM2(0x08000000-0x080FFFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\Infineon\XMC4500\startup_XMC4500.s" ("Infineon XMC4500 Startup Code") + UL2CM3(-FD20000000 -FC800 -FN2 -FF0XMC4500_1024 -FS0C000000 -FL0100000 -FF1XMC4500c_1024 -FS18000000 -FL1100000) + 6264 + XMC4500.h + + + + + + + + + + SFD\Infineon\XMC4500\xmc4500.sfr + 0 + + + + Infineon\XMC4500\ + Infineon\XMC4500\ + + 0 + 0 + 0 + 0 + 1 + + .\Flash\ + RTOSDemo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 1 + + + + + + + + + + + + + + BIN\UL2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 1 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0xc000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0xc000000 + 0x100000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpu Cortex-M4.fp --no_allow_fpreg_for_nonfpdata + rvkdm PART_XMC4500 + + ..\CORTEX_M4F_Infineon_XMC4500_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;..\Common\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x0C000000 + 0x10000000 + + + + --entry=Reset_Handler + + + + + + + + Startup + + + startup_XMC4500.s + 2 + .\startup_XMC4500.s + + + System_XMC4500.c + 1 + .\System_XMC4500.c + + + startup_XMC4200.s + 2 + .\startup_XMC4200.s + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + system_XMC4200.c + 1 + .\system_XMC4200.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + system_XMC4400.c + 1 + .\system_XMC4400.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + startup_XMC4400.s + 2 + .\startup_XMC4400.s + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + Demo_Source + + + main.c + 1 + .\main.c + + + FreeRTOSConfig.h + 5 + .\FreeRTOSConfig.h + + + RegTest.c + 1 + .\RegTest.c + + + main_full.c + 1 + .\main_full.c + + + main_blinky.c + 1 + .\main_blinky.c + + + + + FreeRTOS_Source + + + timers.c + 1 + ..\..\Source\timers.c + + + list.c + 1 + ..\..\Source\list.c + + + queue.c + 1 + ..\..\Source\queue.c + + + tasks.c + 1 + ..\..\Source\tasks.c + + + port.c + 1 + ..\..\Source\portable\RVDS\ARM_CM4F\port.c + + + heap_4.c + 1 + ..\..\Source\portable\MemMang\heap_4.c + + + + + Common_Demo_Source + + + semtest.c + 1 + ..\Common\Minimal\semtest.c + + + sp_flop.c + 1 + ..\Common\Minimal\sp_flop.c + + + blocktim.c + 1 + ..\Common\Minimal\blocktim.c + + + countsem.c + 1 + ..\Common\Minimal\countsem.c + + + dynamic.c + 1 + ..\Common\Minimal\dynamic.c + + + GenQTest.c + 1 + ..\Common\Minimal\GenQTest.c + + + recmutex.c + 1 + ..\Common\Minimal\recmutex.c + + + + + + + RTOSDemo - XMC4400 + 0x4 + ARM-ADS + + + XMC4400-512 + Infineon + IRAM(0x20000000-0x20007FFF) IRAM2(0x1FFFC000-0x1FFFFFFF) IROM(0x0C000000-0x0C07FFFF) IROM2(0x08000000-0x0807FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\Infineon\XMC4400\startup_XMC4400.s" ("Infineon XMC4400 Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN2 -FF0XMC4400_512 -FS0C000000 -FL080000 -FF1XMC4400c_512 -FS18000000 -FL180000) + 6644 + XMC4400.h + + + + + + + + + + SFD\Infineon\XMC4400\xmc4400.SFR + 0 + + + + Infineon\XMC4400\ + Infineon\XMC4400\ + + 0 + 0 + 0 + 0 + 1 + + .\Flash\ + RTOSDemo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 7 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 1 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0xc000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0xc000000 + 0x80000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x1fffc000 + 0x4000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpu Cortex-M4.fp --no_allow_fpreg_for_nonfpdata + rvkdm PART_XMC4400 + + ..\CORTEX_M4F_Infineon_XMC4500_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;..\Common\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x0C000000 + 0x10000000 + + + + --entry=Reset_Handler + + + + + + + + Startup + + + startup_XMC4500.s + 2 + .\startup_XMC4500.s + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + System_XMC4500.c + 1 + .\System_XMC4500.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + startup_XMC4200.s + 2 + .\startup_XMC4200.s + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + system_XMC4200.c + 1 + .\system_XMC4200.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + system_XMC4400.c + 1 + .\system_XMC4400.c + + + startup_XMC4400.s + 2 + .\startup_XMC4400.s + + + + + Demo_Source + + + main.c + 1 + .\main.c + + + FreeRTOSConfig.h + 5 + .\FreeRTOSConfig.h + + + RegTest.c + 1 + .\RegTest.c + + + main_full.c + 1 + .\main_full.c + + + main_blinky.c + 1 + .\main_blinky.c + + + + + FreeRTOS_Source + + + timers.c + 1 + ..\..\Source\timers.c + + + list.c + 1 + ..\..\Source\list.c + + + queue.c + 1 + ..\..\Source\queue.c + + + tasks.c + 1 + ..\..\Source\tasks.c + + + port.c + 1 + ..\..\Source\portable\RVDS\ARM_CM4F\port.c + + + heap_4.c + 1 + ..\..\Source\portable\MemMang\heap_4.c + + + + + Common_Demo_Source + + + semtest.c + 1 + ..\Common\Minimal\semtest.c + + + sp_flop.c + 1 + ..\Common\Minimal\sp_flop.c + + + blocktim.c + 1 + ..\Common\Minimal\blocktim.c + + + countsem.c + 1 + ..\Common\Minimal\countsem.c + + + dynamic.c + 1 + ..\Common\Minimal\dynamic.c + + + GenQTest.c + 1 + ..\Common\Minimal\GenQTest.c + + + recmutex.c + 1 + ..\Common\Minimal\recmutex.c + + + + + + + RTOSDemo - XMC4200 + 0x4 + ARM-ADS + + + XMC4200-256 + Infineon + IRAM(0x20000000-0x20005FFF) IRAM2(0x1FFFE000-0x1FFFFFFF) IROM(0x0C000000-0x0C03FFFF) IROM2(0x08000000-0x0803FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\Infineon\XMC4200-4100\startup_XMC4200.s" ("Infineon XMC4200/4100 Startup Code") + UL2CM3(-FD20000000 -FC800 -FN2 -FF0XMC4200_4100_256 -FS0C000000 -FL040000 -FF1XMC4200_4100c_256 -FS18000000 -FL140000) + 6705 + XMC4200.h + + + + + + + + + + SFD\Infineon\XMC4200-4100\xmc4200.SFR + 0 + + + + Infineon\XMC4200-4100\ + Infineon\XMC4200-4100\ + + 0 + 0 + 0 + 0 + 1 + + .\Flash\ + RTOSDemo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU -REMAP + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 7 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 1 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 1 + 0xc000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0xc000000 + 0x40000 + + + 1 + 0x8000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x6000 + + + 0 + 0x1fffe000 + 0x2000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpu Cortex-M4.fp --no_allow_fpreg_for_nonfpdata + rvkdm PART_XMC4200 + + ..\CORTEX_M4F_Infineon_XMC4500_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM4F;..\Common\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x0C000000 + 0x10000000 + + + + --entry=Reset_Handler + + + + + + + + Startup + + + startup_XMC4500.s + 2 + .\startup_XMC4500.s + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + System_XMC4500.c + 1 + .\System_XMC4500.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + startup_XMC4200.s + 2 + .\startup_XMC4200.s + + + system_XMC4200.c + 1 + .\system_XMC4200.c + + + system_XMC4400.c + 1 + .\system_XMC4400.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + startup_XMC4400.s + 2 + .\startup_XMC4400.s + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + Demo_Source + + + main.c + 1 + .\main.c + + + FreeRTOSConfig.h + 5 + .\FreeRTOSConfig.h + + + RegTest.c + 1 + .\RegTest.c + + + main_full.c + 1 + .\main_full.c + + + main_blinky.c + 1 + .\main_blinky.c + + + + + FreeRTOS_Source + + + timers.c + 1 + ..\..\Source\timers.c + + + list.c + 1 + ..\..\Source\list.c + + + queue.c + 1 + ..\..\Source\queue.c + + + tasks.c + 1 + ..\..\Source\tasks.c + + + port.c + 1 + ..\..\Source\portable\RVDS\ARM_CM4F\port.c + + + heap_4.c + 1 + ..\..\Source\portable\MemMang\heap_4.c + + + + + Common_Demo_Source + + + semtest.c + 1 + ..\Common\Minimal\semtest.c + + + sp_flop.c + 1 + ..\Common\Minimal\sp_flop.c + + + blocktim.c + 1 + ..\Common\Minimal\blocktim.c + + + countsem.c + 1 + ..\Common\Minimal\countsem.c + + + dynamic.c + 1 + ..\Common\Minimal\dynamic.c + + + GenQTest.c + 1 + ..\Common\Minimal\GenQTest.c + + + recmutex.c + 1 + ..\Common\Minimal\recmutex.c + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RegTest.c new file mode 100644 index 000000000..2c42e38f1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/RegTest.c @@ -0,0 +1,521 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +__asm vRegTest1Task( void ) +{ + PRESERVE8 + IMPORT ulRegTest1LoopCounter + + /* Fill the core registers with known values. */ + mov r0, #100 + mov r1, #101 + mov r2, #102 + mov r3, #103 + mov r4, #104 + mov r5, #105 + mov r6, #106 + mov r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + /* Fill the VFP registers with known values. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + +reg1_loop + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d1 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d2 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d3 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + vmov r0, r1, d4 + cmp r0, #108 + bne reg1_error_loopf + cmp r1, #109 + bne reg1_error_loopf + vmov r0, r1, d5 + cmp r0, #110 + bne reg1_error_loopf + cmp r1, #111 + bne reg1_error_loopf + vmov r0, r1, d6 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d7 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d8 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d9 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + vmov r0, r1, d10 + cmp r0, #108 + bne reg1_error_loopf + cmp r1, #109 + bne reg1_error_loopf + vmov r0, r1, d11 + cmp r0, #110 + bne reg1_error_loopf + cmp r1, #111 + bne reg1_error_loopf + vmov r0, r1, d12 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d13 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d14 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d15 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg1_loopf_pass + +reg1_error_loopf + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg1_error_loopf + +reg1_loopf_pass + + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + cmp r8, #108 + bne reg1_error_loop + cmp r9, #109 + bne reg1_error_loop + cmp r10, #110 + bne reg1_error_loop + cmp r11, #111 + bne reg1_error_loop + cmp r12, #112 + bne reg1_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg1_loop + +reg1_error_loop + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + nop +} +/*-----------------------------------------------------------*/ + +__asm vRegTest2Task( void ) +{ + PRESERVE8 + IMPORT ulRegTest2LoopCounter + + /* Set all the core registers to known values. */ + mov r0, #-1 + mov r1, #1 + mov r2, #2 + mov r3, #3 + mov r4, #4 + mov r5, #5 + mov r6, #6 + mov r7, #7 + mov r8, #8 + mov r9, #9 + mov r10, #10 + mov r11, #11 + mov r12, #12 + + /* Set all the VFP to known values. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + +reg2_loop + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d1 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d2 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d3 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + vmov r0, r1, d4 + cmp r0, #8 + bne reg2_error_loopf + cmp r1, #9 + bne reg2_error_loopf + vmov r0, r1, d5 + cmp r0, #10 + bne reg2_error_loopf + cmp r1, #11 + bne reg2_error_loopf + vmov r0, r1, d6 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d7 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d8 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d9 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + vmov r0, r1, d10 + cmp r0, #8 + bne reg2_error_loopf + cmp r1, #9 + bne reg2_error_loopf + vmov r0, r1, d11 + cmp r0, #10 + bne reg2_error_loopf + cmp r1, #11 + bne reg2_error_loopf + vmov r0, r1, d12 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d13 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d14 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d15 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg2_loopf_pass + +reg2_error_loopf + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg2_error_loopf + +reg2_loopf_pass + + cmp r0, #-1 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + cmp r8, #8 + bne reg2_error_loop + cmp r9, #9 + bne reg2_error_loop + cmp r10, #10 + bne reg2_error_loop + cmp r11, #11 + bne reg2_error_loop + cmp r12, #12 + bne reg2_error_loop + + /* Increment the loop counter to indicate this test is still functioning + correctly. */ + push { r0-r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ + lsl r0, r0, #28 /* Shift to PendSV bit */ + str r0, [r1] + dsb + + pop { r0-r1 } + + /* Start again. */ + b reg2_loop + +reg2_error_loop + /* If this line is hit then there was an error in a core register value. + This loop ensures the loop counter variable stops incrementing. */ + b reg2_error_loop + nop +} +/*-----------------------------------------------------------*/ + +__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue ) +{ + PRESERVE8 + + /* Clobber the auto saved registers. */ + vmov d0, r0, r0 + vmov d1, r0, r0 + vmov d2, r0, r0 + vmov d3, r0, r0 + vmov d4, r0, r0 + vmov d5, r0, r0 + vmov d6, r0, r0 + vmov d7, r0, r0 + bx lr +} +/*-----------------------------------------------------------*/ + +__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue ) +{ + PRESERVE8 + + vmov r1, s0 + cmp r0, r1 + bne return_error + vmov r1, s1 + cmp r0, r1 + bne return_error + vmov r1, s2 + cmp r0, r1 + bne return_error + vmov r1, s3 + cmp r0, r1 + bne return_error + vmov r1, s4 + cmp r0, r1 + bne return_error + vmov r1, s5 + cmp r0, r1 + bne return_error + vmov r1, s6 + cmp r0, r1 + bne return_error + vmov r1, s7 + cmp r0, r1 + bne return_error + vmov r1, s8 + cmp r0, r1 + bne return_error + vmov r1, s9 + cmp r0, r1 + bne return_error + vmov r1, s10 + cmp r0, r1 + bne return_error + vmov r1, s11 + cmp r0, r1 + bne return_error + vmov r1, s12 + cmp r0, r1 + bne return_error + vmov r1, s13 + cmp r0, r1 + bne return_error + vmov r1, s14 + cmp r0, r1 + bne return_error + vmov r1, s15 + cmp r0, r1 + bne return_error + +return_pass + mov r0, #1 + bx lr + +return_error + mov r0, #0 + bx lr +} + + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/System_XMC4500.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/System_XMC4500.c new file mode 100644 index 000000000..06fd3aca6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/System_XMC4500.c @@ -0,0 +1,705 @@ +/**************************************************************************//** + * @file system_XMC4500.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4500 Device Series + * @version V3.0.1 Alpha + * @date 17. September 2012 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include "system_XMC4500.h" +#include + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 +#define SCU_CLOCK_BACK_UP_FACTORY 2 +#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 + + +#define HIB_CLOCK_FOSI 1 +#define HIB_CLOCK_OSCULP 2 + + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 +/* not avalible in config wizzard*/ +/* +* mandatory clock parameters ************************************************** +* +* source for clock generation +* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) +* +**************************************************************************************/ +// Selection of imput lock for PLL +/*************************************************************************************/ +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC + +/*************************************************************************************/ +// Standby clock selection for Backup clock source trimming +/*************************************************************************************/ +#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP +//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI + +/*************************************************************************************/ +// Global clock parameters +/*************************************************************************************/ +#define CLOCK_FSYS 120000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define CLOCK_BACK_UP 24000000 + +/*************************************************************************************/ +/* OSC_HP setup parameters */ +/*************************************************************************************/ +#define SCU_OSC_HP_MODE 0xF0 +#define SCU_OSCHPWDGDIV 2 + +/*************************************************************************************/ +/* MAIN PLL setup parameters */ +/*************************************************************************************/ +//Divider settings for external crystal @ 12 MHz +/*************************************************************************************/ +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K2DIV 3 +#define SCU_PLL_PDIV 1 +#define SCU_PLL_NDIV 79 + +/*************************************************************************************/ +//Divider settings for use of backup clock source trimmed +/*************************************************************************************/ +//#define SCU_PLL_K1DIV 1 +//#define SCU_PLL_K2DIV 3 +//#define SCU_PLL_PDIV 3 +//#define SCU_PLL_NDIV 79 +/*************************************************************************************/ + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 +/* not avalible in config wizzard*/ +#define SCU_USBPLL_PDIV 0 +#define SCU_USBPLL_NDIV 31 +#define SCU_USBDIV 3 + +/*--------------------- Flash Wait State Configuration ------------------------------- +// +// Flash Wait State Configuration +// Flash Wait State +// <0=> 3 WS +// <1=> 4 WS +// <2=> 5 WS +// <3=> 6 WS +// +// +*/ + +#define PMU_FLASH 1 +#define PMU_FLASH_WS 0x00000000 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> Divided value of USB PLL output +// <3=> Divided value of PLL Clock +// Clockout divider <1-10><#-1> +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000003 +#define SCU_CLOCKOUT_DIV 0x00000009 +#define SCU_CLOCKOUT_PIN 0x00000001 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +#if SCU_CLOCK_SETUP +uint32_t SystemCoreClock = CLOCK_FSYS; +#else +uint32_t SystemCoreClock = CLOCK_BACK_UP; +#endif + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void); +#endif + +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void); +#endif + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +int temp; + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + +/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ +SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + +/* Setup the WDT */ +#if WDT_SETUP + +WDT->CTR &= ~WDTENB_nVal; + +#endif + +/* Setup the Flash Wait State */ +#if PMU_FLASH +temp = FLASH0->FCON; +temp &= ~FLASH_FCON_WSPFLASH_Msk; +temp |= PMU_FLASH_WS+3; +FLASH0->FCON = temp; +#endif + + +/* Setup the clockout */ +#if SCU_CLOCKOUT_SETUP + +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; +/*set PLL div for clkout */ +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; + +if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ + } +else { + PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ + } + +#endif + + +/* Setup the System clock */ +#if SCU_CLOCK_SETUP +SystemClockSetup(); +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ + + +/* Setup the USB PL */ +#if SCU_USB_CLOCK_SETUP +USBClockSetup(); +#endif + + + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ +unsigned int PDIV; +unsigned int NDIV; +unsigned int K2DIV; +unsigned int long VCO; + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +if (SCU_CLK->SYSCLKCR == 0x00010000) +{ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ + /* check if PLL is locked */ + /* read back divider settings */ + PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; + NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; + K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; + + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ + /* the selected clock is the Backup clock fofi */ + VCO = (CLOCK_BACK_UP/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + + } + else + { + /* the selected clock is the PLL external oscillator */ + VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + } + + + } +} +else +{ +SystemCoreClock = CLOCK_BACK_UP; +} + + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void) +{ +int temp; +unsigned int long VCO; +int stepping_K2DIV; + +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +} + +/* Enable OSC_HP if not already on*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + /********************************************************************************************************************/ + /* Use external crystal for PLL clock input */ + /********************************************************************************************************************/ + + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) + { + /********************************************************************************************************************/ + /* Use factory trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) + { + /********************************************************************************************************************/ + /* Use automatic trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* check for HIB Domain enabled */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ + + /* check for HIB Domain is not in reset state */ + if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ + + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) + { + /****************************************************************************************************************/ + /* Use fOSI as source of the standby clock */ + /****************************************************************************************************************/ + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + } + else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) + { + /****************************************************************************************************************/ + /* Use fULP as source of the standby clock */ + /****************************************************************************************************************/ + /*check OSCUL if running correct*/ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); + + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ + /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ + /* select OSCUL clock for RTC*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*enable OSCULP WDG Alarm Enable*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*wait now for clock is stable */ + do + { + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + for(temp=0;temp<=0xFFFF;temp++); + } + while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); + + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + } + // now OSCULP is running and can be used + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + } + } + + /********************************************************************************************************************/ + /* Setup and look the main PLL */ + /********************************************************************************************************************/ + +if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ + /* Systen is still running from internal clock */ + /* select FOFI as system clock */ + if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ + + + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/24000000)-1; + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + /* setup time out loop */ + /* Timeout for wait loo ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + + if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + } + else return(0); + + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /* we may have to reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /*********************************************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 60MHz + *********************************************************/ + if (CLOCK_FSYS > 60000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/60000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 90MHz + *********************************************************/ + if (CLOCK_FSYS > 90000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/90000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + } + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void) +{ +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + + /* check if PLL is switched on */ +if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* check and if not already running enable OSC_HP */ + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + /* check if Main PLL is switched on for OSC WD*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); + /* Setup USBDIV settings USB clock */ + SCU_CLK->USBCLKCR = SCU_USBDIV; + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/System_XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/System_XMC4500.h new file mode 100644 index 000000000..73eb6d590 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/System_XMC4500.h @@ -0,0 +1,114 @@ +/**************************************************************************//** + * @file system_XMC4500.h + * @brief Header file for the XMC4500-Series systeminit + * + * @version V1.6 + * @date 23. October 2012 + * + * @note + * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. + * This file can be freely distributed within development tools that are supporting such microcontrollers. + + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * + ******************************************************************************/ + + +#ifndef __SYSTEM_XMC4500_H +#define __SYSTEM_XMC4500_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 + + + +/* + * mandatory clock parameters ************************************************** + */ +/* source for clock generation + * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) + * mandatory for old system_xmc4500.c files - please do not remove!!! + **************************************************************************************/ + +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +#define CLOCK_OSC_HP 24000000 +#define CLOCK_BACK_UP 24000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define SYSTEM_FREQUENCY 120000000 + +/* OSC_HP setup parameters */ +#define OSC_HP_MODE 0 +#define OSCHPWDGDIV 2 + +/* MAIN PLL setup parameters */ + + +#define PLL_K1DIV 1 +#define PLL_K2DIV 3 +#define PLL_PDIV 1 +#define PLL_NDIV 79 + + + +#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz +#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz +#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz + + + +#define USBPLL_PDIV 1 +#define USBPLL_NDIV 15 + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Template.sct b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Template.sct new file mode 100644 index 000000000..785967479 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/Template.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x0C000000 0x00100000 { ; load region size_region + ER_IROM1 0x0C000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x10000000 0x00010000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main.c new file mode 100644 index 000000000..768a44d96 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main.c @@ -0,0 +1,224 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup and FreeRTOS hook functions. + * + * + * Additional code: + * + * This demo does not contain a non-kernel interrupt service routine that + * can be used as an example for application writers to use as a reference. + * Therefore, the framework of a dummy (not installed) handler is provided + * in this file. The dummy function is called Dummy_IRQHandler(). Please + * ensure to read the comments in the function itself, but more importantly, + * the notes on the function contained on the documentation page for this demo + * that is found on the FreeRTOS.org web site. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ + +/* + * Set up the hardware ready to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +extern void main_blinky( void ); +extern void main_full( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + configCONFIGURE_LED(); + + /* Ensure all priority bits are assigned as preemption priority bits. */ + NVIC_SetPriorityGrouping( 0 ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* vApplicationMallocFailedHook() will only be called if + configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + function that will get called if a call to pvPortMalloc() fails. + pvPortMalloc() is called internally by the kernel whenever a task, queue, + timer or semaphore is created. It is also called by various parts of the + demo application. If heap_1.c or heap_2.c are used, then the size of the + heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + to query the size of free heap space that remains (although it does not + provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + task. It is essential that code added to this hook function never attempts + to block in any way (for example, call xQueueReceive() with a block time + specified, or call vTaskDelay()). If the application makes use of the + vTaskDelete() API function (as this demo application does) then it is also + important that vApplicationIdleHook() is permitted to return to its calling + function, because it is the responsibility of the idle task to clean up + memory allocated by the kernel to any task that has since been deleted. */ +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + /* This function will be called by each tick interrupt if + configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + added here, but the tick hook is called from an interrupt context, so + code must not attempt to block, and only the interrupt safe FreeRTOS API + functions can be used (those that end in FromISR()). */ +} +/*-----------------------------------------------------------*/ + +#ifdef JUST_AN_EXAMPLE_ISR + +void Dummy_IRQHandler(void) +{ +long lHigherPriorityTaskWoken = pdFALSE; + + /* Clear the interrupt if necessary. */ + Dummy_ClearITPendingBit(); + + /* This interrupt does nothing more than demonstrate how to synchronise a + task with an interrupt. A semaphore is used for this purpose. Note + lHigherPriorityTaskWoken is initialised to zero. */ + xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); + + /* If there was a task that was blocked on the semaphore, and giving the + semaphore caused the task to unblock, and the unblocked task has a priority + higher than the current Running state task (the task that this interrupt + interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE + internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the + portEND_SWITCHING_ISR() macro will result in a context switch being pended to + ensure this interrupt returns directly to the unblocked, higher priority, + task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ + portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); +} + +#endif /* JUST_AN_EXAMPLE_ISR */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_blinky.c new file mode 100644 index 000000000..83d8398d8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_blinky.c @@ -0,0 +1,232 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles the LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_RATE_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* Values passed to the two tasks just to check the task parameter +functionality. */ +#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) +#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) + +/*-----------------------------------------------------------*/ + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/* + * Called by main() to create the simply blinky style application if + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + */ +void main_blinky( void ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static xQueueHandle xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +portTickType xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. + The block time is specified in ticks, the constant used converts ticks + to ms. While in the Blocked state this task will not consume any CPU + time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + configTOGGLE_LED(); + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_full.c new file mode 100644 index 000000000..a9cda91ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/main_full.c @@ -0,0 +1,290 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the comprehensive test and demo version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + ****************************************************************************** + * + * main_full() creates all the demo application tasks and a software timer, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" timer - The check software timer period is initially set to three + * seconds. The callback function associated with the check software timer + * checks that all the standard demo tasks, and the register check tasks, are + * not only still executing, but are executing without reporting any errors. If + * the check software timer discovers that a task has either stalled, or + * reported an error, then it changes its own execution period from the initial + * three seconds, to just 200ms. The check software timer callback function + * also toggles the single LED each time it is called. This provides a visual + * indication of the system status: If the LED toggles every three seconds, + * then no issues have been discovered. If the LED toggles every 200ms, then + * an issue has been discovered with at least one task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" + +/* Priorities for the demo application tasks. */ +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_RATE_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_RATE_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS ) + +/*-----------------------------------------------------------*/ + +/* + * The check timer callback function, as described at the top of this file. + */ +static void prvCheckTimerCallback( xTimerHandle xTimer ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the FPU registers, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly file. + */ +extern void vRegTest1Task( void *pvParameters ); +extern void vRegTest2Task( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check software timer. If the variables keep +incrementing, then the register check tasks has not discovered any errors. If +a variable stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ +xTimerHandle xCheckTimer = NULL; + + /* Start all the other standard demo/test tasks. The have not particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartDynamicPriorityTasks(); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + + /* Create the register check tasks, as described at the top of this + file */ + xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); + + /* Create the software timer that performs the 'check' functionality, + as described at the top of this file. */ + xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + if( xCheckTimer != NULL ) + { + xTimerStart( xCheckTimer, mainDONT_BLOCK ); + } + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following line + will never be reached. If the following line does execute, then there was + insufficient FreeRTOS heap memory available for the idle and/or timer tasks + to be created. See the memory management section on the FreeRTOS web site + for more details. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTimerCallback( xTimerHandle xTimer ) +{ +static long lChangedTimerPeriodAlready = pdFALSE; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = pdTRUE; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound = pdTRUE; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound = pdTRUE; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + everything is ok. A faster toggle indicates an error. */ + configTOGGLE_LED(); + + /* Have any errors been latch in ulErrorFound? If so, shorten the + period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + This will result in an increase in the rate at which mainCHECK_LED + toggles. */ + if( ulErrorFound != pdFALSE ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + Functions called from inside of a timer callback function must + *never* attempt to block. */ + xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/startup_XMC4200.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/startup_XMC4200.s new file mode 100644 index 000000000..a246e4302 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/startup_XMC4200.s @@ -0,0 +1,455 @@ +;*****************************************************************************/ +; * @file startup_XMC4200.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Infineon XMC4200 Device Series +; * @version V1.00 +; * @date 05. February 2013 +; * +; * @note +; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +;/* ********************* Version History *********************************** */ +;/* *************************************************************************** +; V0.1 , September 2012, First version +; V1.0 , February 2013, FIX for CPU prefetch bug implemented +;**************************************************************************** */ + + +;* <<< Use Configuration Wizard in Context Menu >>> + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ +;/* +; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001). +; * A veneer defined below will first +; * be executed which in turn branches to the final exception handler. +; * +; * In addition to defining the veneers, the vector table must for these buggy +; * devices contain the veneers. +; */ + +;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define +;or use define below + GBLL WORKAROUND_PMU_CM001 + +;/* A macro to setup a vector table entry based on STEP ID */ + IF :DEF:WORKAROUND_PMU_CM001 + MACRO + ExcpVector $Handler + DCD $Handler._Veneer + MEND + ELSE + MACRO + ExcpVector $Handler + DCD $Handler + MEND + ENDIF + +;/* A macro to ease definition of the various handlers based on STEP ID */ + IF :DEF:WORKAROUND_PMU_CM001 + + ;/* First define the final exception handler */ + MACRO + ExcpHandler $Handler_Func +$Handler_Func\ + PROC + EXPORT $Handler_Func [WEAK] + B . + ENDP + + ;/* And then define a veneer that will branch to the final excp handler */ +$Handler_Func._Veneer\ + PROC + EXPORT $Handler_Func._Veneer [WEAK] + LDR R0, =$Handler_Func + PUSH {LR} + BLX R0 + POP {PC} + ALIGN + LTORG + ENDP + MEND + + ELSE + + ;/* No prefetch bug, hence define only the final exception handler */ + MACRO + ExcpHandler $Handler_Func +$Handler_Func\ + PROC + EXPORT $Handler_Func [WEAK] + B . + ENDP + MEND + + ENDIF +;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */ + + +;* ================== START OF VECTOR TABLE DEFINITION ====================== */ +;* Vector Table - This gets programed into VTOR register */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + + +__Vectors + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + ExcpVector NMI_Handler ; NMI Handler + ExcpVector HardFault_Handler ; Hard Fault Handler + ExcpVector MemManage_Handler ; MPU Fault Handler + ExcpVector BusFault_Handler ; Bus Fault Handler + ExcpVector UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + ExcpVector DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals + ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0 + ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0 + ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1 + ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2 + ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3 + ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0 + ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1 + ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2 + ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0 + DCD 0 ; Reserved + ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0 + ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1 + ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1 + ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3 + ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0 + ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1 + ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2 + ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3 + ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0 + ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1 + ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2 + ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0 + ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1 + ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0 + ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1 + ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2 + ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3 + ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0 + ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1 + ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2 + ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0 + ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1 + ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2 + ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0 + ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1 + DCD 0 ; Reserved + DCD 0 ; Reserved + ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0 + ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1 + ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2 + ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3 + ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0 + ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1 + ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2 + ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3 + ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4 + ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5 + ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6 + ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7 + ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0 + ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1 + ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2 + ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3 + ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4 + ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5 + ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0 + ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1 + ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2 + ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3 + ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4 + ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0 + DCD 0 ; Reserved + ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0 + ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0 + DCD 0 ; Reserved + ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +;* ================== END OF VECTOR TABLE DEFINITION ======================= */ + +;* ================== START OF VECTOR ROUTINES ============================= */ + + AREA |.text|, CODE, READONLY + +;* Reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ; Remap vector table + LDR R0, =__Vectors + LDR R1, =0xE000ED08 ;*VTOR register + STR R0,[R1] + + ;* C routines are likely to be called. Setup the stack now + LDR SP,=__initial_sp + + LDR R0, = SystemInit + BLX R0 + + ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is + ;weakly defined here though for a potential override. + + LDR R0, = SystemInit_DAVE3 + BLX R0 + + ;* Reset stack pointer before zipping off to user application + LDR SP,=__initial_sp + + LDR R0, =__main + BX R0 + + ALIGN + ENDP + + + + +;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ + + + +;/* Default exception Handlers - Users may override this default functionality by +; defining handlers of the same name in their C code */ + + ExcpHandler NMI_Handler + ExcpHandler HardFault_Handler + ExcpHandler MemManage_Handler + ExcpHandler BusFault_Handler + ExcpHandler UsageFault_Handler + ExcpHandler SVC_Handler + ExcpHandler DebugMon_Handler + ExcpHandler PendSV_Handler + ExcpHandler SysTick_Handler + +;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ + +;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ + +;* IRQ Handlers */ + ExcpHandler SCU_0_IRQHandler + ExcpHandler ERU0_0_IRQHandler + ExcpHandler ERU0_1_IRQHandler + ExcpHandler ERU0_2_IRQHandler + ExcpHandler ERU0_3_IRQHandler + ExcpHandler ERU1_0_IRQHandler + ExcpHandler ERU1_1_IRQHandler + ExcpHandler ERU1_2_IRQHandler + ExcpHandler ERU1_3_IRQHandler + ExcpHandler PMU0_0_IRQHandler + ExcpHandler VADC0_C0_0_IRQHandler + ExcpHandler VADC0_C0_1_IRQHandler + ExcpHandler VADC0_C0_2_IRQHandler + ExcpHandler VADC0_C0_3_IRQHandler + ExcpHandler VADC0_G0_0_IRQHandler + ExcpHandler VADC0_G0_1_IRQHandler + ExcpHandler VADC0_G0_2_IRQHandler + ExcpHandler VADC0_G0_3_IRQHandler + ExcpHandler VADC0_G1_0_IRQHandler + ExcpHandler VADC0_G1_1_IRQHandler + ExcpHandler VADC0_G1_2_IRQHandler + ExcpHandler VADC0_G1_3_IRQHandler + ExcpHandler DAC0_0_IRQHandler + ExcpHandler DAC0_1_IRQHandler + ExcpHandler CCU40_0_IRQHandler + ExcpHandler CCU40_1_IRQHandler + ExcpHandler CCU40_2_IRQHandler + ExcpHandler CCU40_3_IRQHandler + ExcpHandler CCU41_0_IRQHandler + ExcpHandler CCU41_1_IRQHandler + ExcpHandler CCU41_2_IRQHandler + ExcpHandler CCU41_3_IRQHandler + ExcpHandler CCU80_0_IRQHandler + ExcpHandler CCU80_1_IRQHandler + ExcpHandler CCU80_2_IRQHandler + ExcpHandler CCU80_3_IRQHandler + ExcpHandler POSIF0_0_IRQHandler + ExcpHandler POSIF0_1_IRQHandler + ExcpHandler HRPWM_0_IRQHandler + ExcpHandler HRPWM_1_IRQHandler + ExcpHandler HRPWM_2_IRQHandler + ExcpHandler HRPWM_3_IRQHandler + ExcpHandler CAN0_0_IRQHandler + ExcpHandler CAN0_1_IRQHandler + ExcpHandler CAN0_2_IRQHandler + ExcpHandler CAN0_3_IRQHandler + ExcpHandler CAN0_4_IRQHandler + ExcpHandler CAN0_5_IRQHandler + ExcpHandler CAN0_6_IRQHandler + ExcpHandler CAN0_7_IRQHandler + ExcpHandler USIC0_0_IRQHandler + ExcpHandler USIC0_1_IRQHandler + ExcpHandler USIC0_2_IRQHandler + ExcpHandler USIC0_3_IRQHandler + ExcpHandler USIC0_4_IRQHandler + ExcpHandler USIC0_5_IRQHandler + ExcpHandler USIC1_0_IRQHandler + ExcpHandler USIC1_1_IRQHandler + ExcpHandler USIC1_2_IRQHandler + ExcpHandler USIC1_3_IRQHandler + ExcpHandler USIC1_4_IRQHandler + ExcpHandler USIC1_5_IRQHandler + ExcpHandler LEDTS0_0_IRQHandler + ExcpHandler FCE0_0_IRQHandler + ExcpHandler GPDMA0_0_IRQHandler + ExcpHandler USB0_0_IRQHandler + +;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ + +;* Definition of the default weak SystemInit_DAVE3 function. +;* This function will be called by the CMSIS SystemInit function. +;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3 +;* which will overule this weak definition +SystemInit_DAVE3 PROC + EXPORT SystemInit_DAVE3 [WEAK] + NOP + BX LR + ENDP + +;* Definition of the default weak DAVE3 function for clock App usage. +;* AllowPLLInitByStartup Handler */ +AllowPLLInitByStartup PROC + EXPORT AllowPLLInitByStartup [WEAK] + MOV R0,#1 + BX LR + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE***** diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/startup_XMC4400.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/startup_XMC4400.s new file mode 100644 index 000000000..cebede580 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/startup_XMC4400.s @@ -0,0 +1,486 @@ +;*****************************************************************************/ +; * @file startup_XMC4400.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Infineon XMC4400 Device Series +; * @version V1.00 +; * @date 05. February 2013 +; * +; * @note +; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +;/* ********************* Version History *********************************** */ +;/* *************************************************************************** +; V0.2 , August 2012, First version +; V1.0 , February 2013, FIX for CPU prefetch bug implemented +;**************************************************************************** */ + + +;* <<< Use Configuration Wizard in Context Menu >>> + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ +;/* +; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001). +; * A veneer defined below will first +; * be executed which in turn branches to the final exception handler. +; * +; * In addition to defining the veneers, the vector table must for these buggy +; * devices contain the veneers. +; */ + +;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define +;or use define below + GBLL WORKAROUND_PMU_CM001 + +;/* A macro to setup a vector table entry based on STEP ID */ + IF :DEF:WORKAROUND_PMU_CM001 + MACRO + ExcpVector $Handler + DCD $Handler._Veneer + MEND + ELSE + MACRO + ExcpVector $Handler + DCD $Handler + MEND + ENDIF + +;/* A macro to ease definition of the various handlers based on STEP ID */ + IF :DEF:WORKAROUND_PMU_CM001 + + ;/* First define the final exception handler */ + MACRO + ExcpHandler $Handler_Func +$Handler_Func\ + PROC + EXPORT $Handler_Func [WEAK] + B . + ENDP + + ;/* And then define a veneer that will branch to the final excp handler */ +$Handler_Func._Veneer\ + PROC + EXPORT $Handler_Func._Veneer [WEAK] + LDR R0, =$Handler_Func + PUSH {LR} + BLX R0 + POP {PC} + ALIGN + LTORG + ENDP + MEND + + ELSE + + ;/* No prefetch bug, hence define only the final exception handler */ + MACRO + ExcpHandler $Handler_Func +$Handler_Func\ + PROC + EXPORT $Handler_Func [WEAK] + B . + ENDP + MEND + + ENDIF +;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */ + + +;* ================== START OF VECTOR TABLE DEFINITION ====================== */ +;* Vector Table - This gets programed into VTOR register */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + + +__Vectors + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + ExcpVector NMI_Handler ; NMI Handler + ExcpVector HardFault_Handler ; Hard Fault Handler + ExcpVector MemManage_Handler ; MPU Fault Handler + ExcpVector BusFault_Handler ; Bus Fault Handler + ExcpVector UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + ExcpVector DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals + ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0 + ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0 + ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1 + ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2 + ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3 + ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0 + ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1 + ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2 + ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0 + DCD 0 ; Reserved + ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0 + ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1 + ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1 + ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3 + ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0 + ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1 + ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2 + ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3 + ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0 + ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1 + ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2 + ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3 + ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0 + ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1 + ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2 + ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3 + ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0 + ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1 + ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2 + ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3 + ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0 + ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1 + ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2 + ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3 + ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4 + ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5 + ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6 + ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7 + ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0 + ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1 + ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0 + ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1 + ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2 + ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3 + ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0 + ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1 + ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2 + ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3 + ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0 + ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1 + ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2 + ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3 + ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0 + ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1 + ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2 + ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3 + ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0 + ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1 + ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2 + ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3 + ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0 + ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1 + ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2 + ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3 + ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0 + ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1 + ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0 + ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1 + ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0 + ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1 + ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2 + ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3 + ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0 + ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1 + ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2 + ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3 + ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4 + ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5 + ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6 + ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7 + ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0 + ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1 + ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2 + ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3 + ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4 + ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5 + ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0 + ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1 + ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2 + ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3 + ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4 + ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0 + DCD 0 ; Reserved + ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0 + ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0 + DCD 0 ; Reserved + ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0 + ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +;* ================== END OF VECTOR TABLE DEFINITION ======================= */ + +;* ================== START OF VECTOR ROUTINES ============================= */ + + AREA |.text|, CODE, READONLY + +;* Reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ; Remap vector table + LDR R0, =__Vectors + LDR R1, =0xE000ED08 ;*VTOR register + STR R0,[R1] + + ;* C routines are likely to be called. Setup the stack now + LDR SP,=__initial_sp + + LDR R0, = SystemInit + BLX R0 + + ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is + ;weakly defined here though for a potential override. + + LDR R0, = SystemInit_DAVE3 + BLX R0 + + ;* Reset stack pointer before zipping off to user application + LDR SP,=__initial_sp + + LDR R0, =__main + BX R0 + + ALIGN + ENDP + + + + +;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ + + + +;/* Default exception Handlers - Users may override this default functionality by +; defining handlers of the same name in their C code */ + + ExcpHandler NMI_Handler + ExcpHandler HardFault_Handler + ExcpHandler MemManage_Handler + ExcpHandler BusFault_Handler + ExcpHandler UsageFault_Handler + ExcpHandler SVC_Handler + ExcpHandler DebugMon_Handler + ExcpHandler PendSV_Handler + ExcpHandler SysTick_Handler + +;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ + +;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ + +;* IRQ Handlers */ + ExcpHandler SCU_0_IRQHandler + ExcpHandler ERU0_0_IRQHandler + ExcpHandler ERU0_1_IRQHandler + ExcpHandler ERU0_2_IRQHandler + ExcpHandler ERU0_3_IRQHandler + ExcpHandler ERU1_0_IRQHandler + ExcpHandler ERU1_1_IRQHandler + ExcpHandler ERU1_2_IRQHandler + ExcpHandler ERU1_3_IRQHandler + ExcpHandler PMU0_0_IRQHandler + ExcpHandler VADC0_C0_0_IRQHandler + ExcpHandler VADC0_C0_1_IRQHandler + ExcpHandler VADC0_C0_2_IRQHandler + ExcpHandler VADC0_C0_3_IRQHandler + ExcpHandler VADC0_G0_0_IRQHandler + ExcpHandler VADC0_G0_1_IRQHandler + ExcpHandler VADC0_G0_2_IRQHandler + ExcpHandler VADC0_G0_3_IRQHandler + ExcpHandler VADC0_G1_0_IRQHandler + ExcpHandler VADC0_G1_1_IRQHandler + ExcpHandler VADC0_G1_2_IRQHandler + ExcpHandler VADC0_G1_3_IRQHandler + ExcpHandler VADC0_G2_0_IRQHandler + ExcpHandler VADC0_G2_1_IRQHandler + ExcpHandler VADC0_G2_2_IRQHandler + ExcpHandler VADC0_G2_3_IRQHandler + ExcpHandler VADC0_G3_0_IRQHandler + ExcpHandler VADC0_G3_1_IRQHandler + ExcpHandler VADC0_G3_2_IRQHandler + ExcpHandler VADC0_G3_3_IRQHandler + ExcpHandler DSD0_0_IRQHandler + ExcpHandler DSD0_1_IRQHandler + ExcpHandler DSD0_2_IRQHandler + ExcpHandler DSD0_3_IRQHandler + ExcpHandler DSD0_4_IRQHandler + ExcpHandler DSD0_5_IRQHandler + ExcpHandler DSD0_6_IRQHandler + ExcpHandler DSD0_7_IRQHandler + ExcpHandler DAC0_0_IRQHandler + ExcpHandler DAC0_1_IRQHandler + ExcpHandler CCU40_0_IRQHandler + ExcpHandler CCU40_1_IRQHandler + ExcpHandler CCU40_2_IRQHandler + ExcpHandler CCU40_3_IRQHandler + ExcpHandler CCU41_0_IRQHandler + ExcpHandler CCU41_1_IRQHandler + ExcpHandler CCU41_2_IRQHandler + ExcpHandler CCU41_3_IRQHandler + ExcpHandler CCU42_0_IRQHandler + ExcpHandler CCU42_1_IRQHandler + ExcpHandler CCU42_2_IRQHandler + ExcpHandler CCU42_3_IRQHandler + ExcpHandler CCU43_0_IRQHandler + ExcpHandler CCU43_1_IRQHandler + ExcpHandler CCU43_2_IRQHandler + ExcpHandler CCU43_3_IRQHandler + ExcpHandler CCU80_0_IRQHandler + ExcpHandler CCU80_1_IRQHandler + ExcpHandler CCU80_2_IRQHandler + ExcpHandler CCU80_3_IRQHandler + ExcpHandler CCU81_0_IRQHandler + ExcpHandler CCU81_1_IRQHandler + ExcpHandler CCU81_2_IRQHandler + ExcpHandler CCU81_3_IRQHandler + ExcpHandler POSIF0_0_IRQHandler + ExcpHandler POSIF0_1_IRQHandler + ExcpHandler POSIF1_0_IRQHandler + ExcpHandler POSIF1_1_IRQHandler + ExcpHandler HRPWM_0_IRQHandler + ExcpHandler HRPWM_1_IRQHandler + ExcpHandler HRPWM_2_IRQHandler + ExcpHandler HRPWM_3_IRQHandler + ExcpHandler CAN0_0_IRQHandler + ExcpHandler CAN0_1_IRQHandler + ExcpHandler CAN0_2_IRQHandler + ExcpHandler CAN0_3_IRQHandler + ExcpHandler CAN0_4_IRQHandler + ExcpHandler CAN0_5_IRQHandler + ExcpHandler CAN0_6_IRQHandler + ExcpHandler CAN0_7_IRQHandler + ExcpHandler USIC0_0_IRQHandler + ExcpHandler USIC0_1_IRQHandler + ExcpHandler USIC0_2_IRQHandler + ExcpHandler USIC0_3_IRQHandler + ExcpHandler USIC0_4_IRQHandler + ExcpHandler USIC0_5_IRQHandler + ExcpHandler USIC1_0_IRQHandler + ExcpHandler USIC1_1_IRQHandler + ExcpHandler USIC1_2_IRQHandler + ExcpHandler USIC1_3_IRQHandler + ExcpHandler USIC1_4_IRQHandler + ExcpHandler USIC1_5_IRQHandler + ExcpHandler LEDTS0_0_IRQHandler + ExcpHandler FCE0_0_IRQHandler + ExcpHandler GPDMA0_0_IRQHandler + ExcpHandler USB0_0_IRQHandler + ExcpHandler ETH0_0_IRQHandler + +;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ + +;* Definition of the default weak SystemInit_DAVE3 function. +;* This function will be called by the CMSIS SystemInit function. +;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3 +;* which will overule this weak definition +SystemInit_DAVE3 PROC + EXPORT SystemInit_DAVE3 [WEAK] + NOP + BX LR + ENDP + +;* Definition of the default weak DAVE3 function for clock App usage. +;* AllowPLLInitByStartup Handler */ +AllowPLLInitByStartup PROC + EXPORT AllowPLLInitByStartup [WEAK] + MOV R0,#1 + BX LR + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE***** diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/startup_XMC4500.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/startup_XMC4500.s new file mode 100644 index 000000000..1f2422253 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/startup_XMC4500.s @@ -0,0 +1,491 @@ +;*****************************************************************************/ +; * @file startup_XMC4500.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Infineon XMC4500 Device Series +; * @version V1.20 +; * @date 05. February 2013 +; * +; * @note +; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +;/* ********************* Version History *********************************** */ +;/* *************************************************************************** +; V1.00 , February 2012, First version +; V1.10 , August 2012, Adding Dave3 init function call +; V1.20 , February 2013, FIX for CPU prefetch bug implemented +;**************************************************************************** */ + + +;* <<< Use Configuration Wizard in Context Menu >>> + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ +;/* +; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001). +; * A veneer defined below will first +; * be executed which in turn branches to the final exception handler. +; * +; * In addition to defining the veneers, the vector table must for these buggy +; * devices contain the veneers. +; */ + +;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define +;or use define below + GBLL WORKAROUND_PMU_CM001 + +;/* A macro to setup a vector table entry based on STEP ID */ + IF :DEF:WORKAROUND_PMU_CM001 + MACRO + ExcpVector $Handler + DCD $Handler._Veneer + MEND + ELSE + MACRO + ExcpVector $Handler + DCD $Handler + MEND + ENDIF + +;/* A macro to ease definition of the various handlers based on STEP ID */ + IF :DEF:WORKAROUND_PMU_CM001 + + ;/* First define the final exception handler */ + MACRO + ExcpHandler $Handler_Func +$Handler_Func\ + PROC + EXPORT $Handler_Func [WEAK] + B . + ENDP + + ;/* And then define a veneer that will branch to the final excp handler */ +$Handler_Func._Veneer\ + PROC + EXPORT $Handler_Func._Veneer [WEAK] + LDR R0, =$Handler_Func + PUSH {LR} + BLX R0 + POP {PC} + ALIGN + LTORG + ENDP + MEND + + ELSE + + ;/* No prefetch bug, hence define only the final exception handler */ + MACRO + ExcpHandler $Handler_Func +$Handler_Func\ + PROC + EXPORT $Handler_Func [WEAK] + B . + ENDP + MEND + + ENDIF +;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */ + + +;* ================== START OF VECTOR TABLE DEFINITION ====================== */ +;* Vector Table - This gets programed into VTOR register */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + + +__Vectors + DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + + ExcpVector NMI_Handler ; NMI Handler + ExcpVector HardFault_Handler ; Hard Fault Handler + ExcpVector MemManage_Handler ; MPU Fault Handler + ExcpVector BusFault_Handler ; Bus Fault Handler + ExcpVector UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + ExcpVector DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals + ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0 + ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0 + ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1 + ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2 + ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3 + ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0 + ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1 + ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2 + ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0 + DCD 0 ; Reserved + ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0 + ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1 + ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1 + ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3 + ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0 + ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1 + ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2 + ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3 + ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0 + ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1 + ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2 + ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3 + ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0 + ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1 + ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2 + ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3 + ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0 + ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1 + ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2 + ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3 + ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0 + ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1 + ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2 + ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3 + ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4 + ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5 + ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6 + ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7 + ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0 + ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1 + ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0 + ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1 + ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2 + ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3 + ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0 + ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1 + ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2 + ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3 + ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0 + ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1 + ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2 + ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3 + ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0 + ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1 + ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2 + ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3 + ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0 + ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1 + ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2 + ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3 + ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0 + ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1 + ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2 + ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3 + ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0 + ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1 + ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0 + ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0 + ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1 + ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2 + ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3 + ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4 + ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5 + ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6 + ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7 + ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0 + ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1 + ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2 + ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3 + ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4 + ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5 + ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0 + ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1 + ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2 + ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3 + ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4 + ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5 + ExcpVector USIC2_0_IRQHandler ; Handler name for SR USIC2_0 + ExcpVector USIC2_1_IRQHandler ; Handler name for SR USIC2_1 + ExcpVector USIC2_2_IRQHandler ; Handler name for SR USIC2_2 + ExcpVector USIC2_3_IRQHandler ; Handler name for SR USIC2_3 + ExcpVector USIC2_4_IRQHandler ; Handler name for SR USIC2_4 + ExcpVector USIC2_5_IRQHandler ; Handler name for SR USIC2_5 + ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0 + DCD 0 ; Reserved + ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0 + ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0 + ExcpVector SDMMC0_0_IRQHandler ; Handler name for SR SDMMC0_0 + ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0 + ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0 + DCD 0 ; Reserved + ExcpVector GPDMA1_0_IRQHandler ; Handler name for SR GPDMA1_0 + DCD 0 ; Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +;* ================== END OF VECTOR TABLE DEFINITION ======================= */ + +;* ================== START OF VECTOR ROUTINES ============================= */ + + AREA |.text|, CODE, READONLY + +;* Reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + ; Remap vector table + LDR R0, =__Vectors + LDR R1, =0xE000ED08 ;*VTOR register + STR R0,[R1] + + ;* C routines are likely to be called. Setup the stack now + LDR SP,=__initial_sp + + LDR R0, = SystemInit + BLX R0 + + ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is + ;weakly defined here though for a potential override. + + LDR R0, = SystemInit_DAVE3 + BLX R0 + + ;* Reset stack pointer before zipping off to user application + LDR SP,=__initial_sp + + LDR R0, =__main + BX R0 + + ALIGN + ENDP + + + + +;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ + + + +;/* Default exception Handlers - Users may override this default functionality by +; defining handlers of the same name in their C code */ + + ExcpHandler NMI_Handler + ExcpHandler HardFault_Handler + ExcpHandler MemManage_Handler + ExcpHandler BusFault_Handler + ExcpHandler UsageFault_Handler + ExcpHandler SVC_Handler + ExcpHandler DebugMon_Handler + ExcpHandler PendSV_Handler + ExcpHandler SysTick_Handler + +;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ + +;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ + +;* IRQ Handlers */ + ExcpHandler SCU_0_IRQHandler + ExcpHandler ERU0_0_IRQHandler + ExcpHandler ERU0_1_IRQHandler + ExcpHandler ERU0_2_IRQHandler + ExcpHandler ERU0_3_IRQHandler + ExcpHandler ERU1_0_IRQHandler + ExcpHandler ERU1_1_IRQHandler + ExcpHandler ERU1_2_IRQHandler + ExcpHandler ERU1_3_IRQHandler + ExcpHandler PMU0_0_IRQHandler + ExcpHandler VADC0_C0_0_IRQHandler + ExcpHandler VADC0_C0_1_IRQHandler + ExcpHandler VADC0_C0_2_IRQHandler + ExcpHandler VADC0_C0_3_IRQHandler + ExcpHandler VADC0_G0_0_IRQHandler + ExcpHandler VADC0_G0_1_IRQHandler + ExcpHandler VADC0_G0_2_IRQHandler + ExcpHandler VADC0_G0_3_IRQHandler + ExcpHandler VADC0_G1_0_IRQHandler + ExcpHandler VADC0_G1_1_IRQHandler + ExcpHandler VADC0_G1_2_IRQHandler + ExcpHandler VADC0_G1_3_IRQHandler + ExcpHandler VADC0_G2_0_IRQHandler + ExcpHandler VADC0_G2_1_IRQHandler + ExcpHandler VADC0_G2_2_IRQHandler + ExcpHandler VADC0_G2_3_IRQHandler + ExcpHandler VADC0_G3_0_IRQHandler + ExcpHandler VADC0_G3_1_IRQHandler + ExcpHandler VADC0_G3_2_IRQHandler + ExcpHandler VADC0_G3_3_IRQHandler + ExcpHandler DSD0_0_IRQHandler + ExcpHandler DSD0_1_IRQHandler + ExcpHandler DSD0_2_IRQHandler + ExcpHandler DSD0_3_IRQHandler + ExcpHandler DSD0_4_IRQHandler + ExcpHandler DSD0_5_IRQHandler + ExcpHandler DSD0_6_IRQHandler + ExcpHandler DSD0_7_IRQHandler + ExcpHandler DAC0_0_IRQHandler + ExcpHandler DAC0_1_IRQHandler + ExcpHandler CCU40_0_IRQHandler + ExcpHandler CCU40_1_IRQHandler + ExcpHandler CCU40_2_IRQHandler + ExcpHandler CCU40_3_IRQHandler + ExcpHandler CCU41_0_IRQHandler + ExcpHandler CCU41_1_IRQHandler + ExcpHandler CCU41_2_IRQHandler + ExcpHandler CCU41_3_IRQHandler + ExcpHandler CCU42_0_IRQHandler + ExcpHandler CCU42_1_IRQHandler + ExcpHandler CCU42_2_IRQHandler + ExcpHandler CCU42_3_IRQHandler + ExcpHandler CCU43_0_IRQHandler + ExcpHandler CCU43_1_IRQHandler + ExcpHandler CCU43_2_IRQHandler + ExcpHandler CCU43_3_IRQHandler + ExcpHandler CCU80_0_IRQHandler + ExcpHandler CCU80_1_IRQHandler + ExcpHandler CCU80_2_IRQHandler + ExcpHandler CCU80_3_IRQHandler + ExcpHandler CCU81_0_IRQHandler + ExcpHandler CCU81_1_IRQHandler + ExcpHandler CCU81_2_IRQHandler + ExcpHandler CCU81_3_IRQHandler + ExcpHandler POSIF0_0_IRQHandler + ExcpHandler POSIF0_1_IRQHandler + ExcpHandler POSIF1_0_IRQHandler + ExcpHandler POSIF1_1_IRQHandler + ExcpHandler CAN0_0_IRQHandler + ExcpHandler CAN0_1_IRQHandler + ExcpHandler CAN0_2_IRQHandler + ExcpHandler CAN0_3_IRQHandler + ExcpHandler CAN0_4_IRQHandler + ExcpHandler CAN0_5_IRQHandler + ExcpHandler CAN0_6_IRQHandler + ExcpHandler CAN0_7_IRQHandler + ExcpHandler USIC0_0_IRQHandler + ExcpHandler USIC0_1_IRQHandler + ExcpHandler USIC0_2_IRQHandler + ExcpHandler USIC0_3_IRQHandler + ExcpHandler USIC0_4_IRQHandler + ExcpHandler USIC0_5_IRQHandler + ExcpHandler USIC1_0_IRQHandler + ExcpHandler USIC1_1_IRQHandler + ExcpHandler USIC1_2_IRQHandler + ExcpHandler USIC1_3_IRQHandler + ExcpHandler USIC1_4_IRQHandler + ExcpHandler USIC1_5_IRQHandler + ExcpHandler USIC2_0_IRQHandler + ExcpHandler USIC2_1_IRQHandler + ExcpHandler USIC2_2_IRQHandler + ExcpHandler USIC2_3_IRQHandler + ExcpHandler USIC2_4_IRQHandler + ExcpHandler USIC2_5_IRQHandler + ExcpHandler LEDTS0_0_IRQHandler + ExcpHandler FCE0_0_IRQHandler + ExcpHandler GPDMA0_0_IRQHandler + ExcpHandler SDMMC0_0_IRQHandler + ExcpHandler USB0_0_IRQHandler + ExcpHandler ETH0_0_IRQHandler + ExcpHandler GPDMA1_0_IRQHandler + +;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ + +;* Definition of the default weak SystemInit_DAVE3 function. +;* This function will be called by the CMSIS SystemInit function. +;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3 +;* which will overule this weak definition +SystemInit_DAVE3 PROC + EXPORT SystemInit_DAVE3 [WEAK] + NOP + BX LR + ENDP + +;* Definition of the default weak DAVE3 function for clock App usage. +;* AllowPLLInitByStartup Handler */ +AllowPLLInitByStartup PROC + EXPORT AllowPLLInitByStartup [WEAK] + MOV R0,#1 + BX LR + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE***** diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4200.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4200.c new file mode 100644 index 000000000..4b7f348f2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4200.c @@ -0,0 +1,708 @@ +/**************************************************************************//** + * @file system_XMC4200.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4000 Device Series + * @version V3.0.1 Alpha + * @date 26. September 2012 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include +#include + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 +#define SCU_CLOCK_BACK_UP_FACTORY 2 +#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 + + +#define HIB_CLOCK_FOSI 1 +#define HIB_CLOCK_OSCULP 2 + + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 +/* not avalible in config wizzard*/ +/* +* mandatory clock parameters ************************************************** +* +* source for clock generation +* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) +* +**************************************************************************************/ +// Selection of imput lock for PLL +/*************************************************************************************/ +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC + +/*************************************************************************************/ +// Standby clock selection for Backup clock source trimming +/*************************************************************************************/ +#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP +//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI + +/*************************************************************************************/ +// Global clock parameters +/*************************************************************************************/ +#define CLOCK_FSYS 80000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define CLOCK_BACK_UP 24000000 + +/*************************************************************************************/ +/* OSC_HP setup parameters */ +/*************************************************************************************/ +#define SCU_OSC_HP_MODE 0xF0 +#define SCU_OSCHPWDGDIV 2 + +/*************************************************************************************/ +/* MAIN PLL setup parameters */ +/*************************************************************************************/ +//Divider settings for external crystal @ 12 MHz +/*************************************************************************************/ +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K2DIV 5 +#define SCU_PLL_PDIV 1 +#define SCU_PLL_NDIV 79 + +/*************************************************************************************/ +//Divider settings for use of backup clock source trimmed +/*************************************************************************************/ +//#define SCU_PLL_K1DIV 1 +//#define SCU_PLL_K2DIV 5 +//#define SCU_PLL_PDIV 3 +//#define SCU_PLL_NDIV 79 +/*************************************************************************************/ + + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 +/* not avalible in config wizzard*/ +#define SCU_USBPLL_PDIV 0 +#define SCU_USBPLL_NDIV 31 +#define SCU_USBDIV 3 + +/*--------------------- Flash Wait State Configuration ------------------------------- +// +// Flash Wait State Configuration +// Flash Wait State +// <0=> 3 WS +// <1=> 4 WS +// <2=> 5 WS +// <3=> 6 WS +// +// +*/ + +#define PMU_FLASH 1 +#define PMU_FLASH_WS 0x00000000 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> Divided value of USB PLL output +// <3=> Divided value of PLL Clock +// Clockout divider <1-10><#-1> +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000000 +#define SCU_CLOCKOUT_DIV 0x00000009 +#define SCU_CLOCKOUT_PIN 0x00000001 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +#if SCU_CLOCK_SETUP +uint32_t SystemCoreClock = CLOCK_FSYS; +#else +uint32_t SystemCoreClock = CLOCK_BACK_UP; +#endif + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void); +#endif + +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void); +#endif + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +int temp; + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + +/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ +SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + +/* Setup the WDT */ +#if WDT_SETUP + +WDT->CTR &= ~WDTENB_nVal; + +#endif + + +/* Setup the Flash Wait State */ +#if PMU_FLASH +temp = FLASH0->FCON; +temp &= ~FLASH_FCON_WSPFLASH_Msk; +temp |= PMU_FLASH_WS+3; +FLASH0->FCON = temp; +#endif + + +/* Setup the clockout */ +#if SCU_CLOCKOUT_SETUP + +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; +/*set PLL div for clkout */ +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; + +if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ + } +else { + PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ + } + +#endif + + +/* Setup the System clock */ +#if SCU_CLOCK_SETUP +SystemClockSetup(); +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ + + +/* Setup the USB PL */ +#if SCU_USB_CLOCK_SETUP +USBClockSetup(); +#endif + + + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ +unsigned int PDIV; +unsigned int NDIV; +unsigned int K2DIV; +unsigned int long VCO; + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +if (SCU_CLK->SYSCLKCR == 0x00010000) +{ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ + /* check if PLL is locked */ + /* read back divider settings */ + PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; + NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; + K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; + + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ + /* the selected clock is the Backup clock fofi */ + VCO = (CLOCK_BACK_UP/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + + } + else + { + /* the selected clock is the PLL external oscillator */ + VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + } + + + } +} +else +{ +SystemCoreClock = CLOCK_BACK_UP; +} + + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void) +{ +int temp; +unsigned int long VCO; +int stepping_K2DIV; + +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +} + +/* Enable OSC_HP if not already on*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + /********************************************************************************************************************/ + /* Use external crystal for PLL clock input */ + /********************************************************************************************************************/ + + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) + { + /********************************************************************************************************************/ + /* Use factory trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) + { + /********************************************************************************************************************/ + /* Use automatic trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* check for HIB Domain enabled */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ + + /* check for HIB Domain is not in reset state */ + if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ + + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) + { + /****************************************************************************************************************/ + /* Use fOSI as source of the standby clock */ + /****************************************************************************************************************/ + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + } + else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) + { + /****************************************************************************************************************/ + /* Use fULP as source of the standby clock */ + /****************************************************************************************************************/ + /*check OSCUL if running correct*/ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); + + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ + /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ + /* select OSCUL clock for RTC*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*enable OSCULP WDG Alarm Enable*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*wait now for clock is stable */ + do + { + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + for(temp=0;temp<=0xFFFF;temp++); + } + while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); + + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + } + // now OSCULP is running and can be used + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + } + } + + /********************************************************************************************************************/ + /* Setup and look the main PLL */ + /********************************************************************************************************************/ + +if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ + /* Systen is still running from internal clock */ + /* select FOFI as system clock */ + if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ + + + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/24000000)-1; + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + /* setup time out loop */ + /* Timeout for wait loo ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + + if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + } + else return(0); + + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /* we may have to reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /*********************************************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 60MHz + *********************************************************/ + if (CLOCK_FSYS > 60000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/60000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 90MHz + *********************************************************/ + if (CLOCK_FSYS > 90000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/90000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + } + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void) +{ +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* check and if not already running enable OSC_HP */ + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + /* check if Main PLL is switched on for OSC WD*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); + /* Setup USBDIV settings USB clock */ + SCU_CLK->USBCLKCR = SCU_USBDIV; + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4200.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4200.h new file mode 100644 index 000000000..33d38c1a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4200.h @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file system_XMC4200.h + * @brief Header file for the XMC4200-Series systeminit + * + * @version V1.0 + * @date 27. August 2012 + * + * @note + * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. + * This file can be freely distributed within development tools that are supporting such microcontrollers. + + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * + ******************************************************************************/ + + +#ifndef __SYSTEM_XMC4200_H +#define __SYSTEM_XMC4200_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4400.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4400.c new file mode 100644 index 000000000..dfbbf9e8d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4400.c @@ -0,0 +1,707 @@ +/**************************************************************************//** + * @file system_XMC4400.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for the Infineon XMC4500 Device Series + * @version V3.0.1 Alpha + * @date 17. September 2012 + * + * @note + * Copyright (C) 2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include +#include + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + +/* clock definitions, do not modify! */ +#define SCU_CLOCK_CRYSTAL 1 +#define SCU_CLOCK_BACK_UP_FACTORY 2 +#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 + + +#define HIB_CLOCK_FOSI 1 +#define HIB_CLOCK_OSCULP 2 + + + + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Configuration +// Disable Watchdog +// +// +*/ +#define WDT_SETUP 1 +#define WDTENB_nVal 0x00000001 + +/*--------------------- CLOCK Configuration ------------------------------- +// +// Main Clock Configuration +// CPU clock divider +// <0=> fCPU = fSYS +// <1=> fCPU = fSYS / 2 +// Peripheral Bus clock divider +// <0=> fPB = fCPU +// <1=> fPB = fCPU / 2 +// CCU Bus clock divider +// <0=> fCCU = fCPU +// <1=> fCCU = fCPU / 2 +// +// +// +*/ + +#define SCU_CLOCK_SETUP 1 +#define SCU_CPUCLKCR_DIV 0x00000000 +#define SCU_PBCLKCR_DIV 0x00000000 +#define SCU_CCUCLKCR_DIV 0x00000000 +/* not avalible in config wizzard*/ +/* +* mandatory clock parameters ************************************************** +* +* source for clock generation +* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) +* +**************************************************************************************/ +// Selection of imput lock for PLL +/*************************************************************************************/ +#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY +//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC + +/*************************************************************************************/ +// Standby clock selection for Backup clock source trimming +/*************************************************************************************/ +#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP +//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI + +/*************************************************************************************/ +// Global clock parameters +/*************************************************************************************/ +#define CLOCK_FSYS 120000000 +#define CLOCK_CRYSTAL_FREQUENCY 12000000 +#define CLOCK_BACK_UP 24000000 + +/*************************************************************************************/ +/* OSC_HP setup parameters */ +/*************************************************************************************/ +#define SCU_OSC_HP_MODE 0xF0 +#define SCU_OSCHPWDGDIV 2 + +/*************************************************************************************/ +/* MAIN PLL setup parameters */ +/*************************************************************************************/ +//Divider settings for external crystal @ 12 MHz +/*************************************************************************************/ +#define SCU_PLL_K1DIV 1 +#define SCU_PLL_K2DIV 3 +#define SCU_PLL_PDIV 1 +#define SCU_PLL_NDIV 79 + +/*************************************************************************************/ +//Divider settings for use of backup clock source trimmed +/*************************************************************************************/ +//#define SCU_PLL_K1DIV 1 +//#define SCU_PLL_K2DIV 3 +//#define SCU_PLL_PDIV 3 +//#define SCU_PLL_NDIV 79 +/*************************************************************************************/ + + +/*--------------------- USB CLOCK Configuration --------------------------- +// +// USB Clock Configuration +// +// +// +*/ + +#define SCU_USB_CLOCK_SETUP 0 +/* not avalible in config wizzard*/ +#define SCU_USBPLL_PDIV 0 +#define SCU_USBPLL_NDIV 31 +#define SCU_USBDIV 3 + +/*--------------------- Flash Wait State Configuration ------------------------------- +// +// Flash Wait State Configuration +// Flash Wait State +// <0=> 3 WS +// <1=> 4 WS +// <2=> 5 WS +// <3=> 6 WS +// +// +*/ + +#define PMU_FLASH 1 +#define PMU_FLASH_WS 0x00000000 + + +/*--------------------- CLOCKOUT Configuration ------------------------------- +// +// Clock OUT Configuration +// Clockout Source Selection +// <0=> System Clock +// <2=> Divided value of USB PLL output +// <3=> Divided value of PLL Clock +// Clockout divider <1-10><#-1> +// Clockout Pin Selection +// <0=> P1.15 +// <1=> P0.8 +// +// +// +// +*/ + +#define SCU_CLOCKOUT_SETUP 0 +#define SCU_CLOCKOUT_SOURCE 0x00000000 +#define SCU_CLOCKOUT_DIV 0x00000009 +#define SCU_CLOCKOUT_PIN 0x00000001 + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +#if SCU_CLOCK_SETUP +uint32_t SystemCoreClock = CLOCK_FSYS; +#else +uint32_t SystemCoreClock = CLOCK_BACK_UP; +#endif + +/*---------------------------------------------------------------------------- + static functions declarations + *----------------------------------------------------------------------------*/ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void); +#endif + +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void); +#endif + + +/** + * @brief Setup the microcontroller system. + * Initialize the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +int temp; + +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ + (3UL << 11*2) ); /* set CP11 Full Access */ +#endif + +/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ +SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); + +/* Setup the WDT */ +#if WDT_SETUP + +WDT->CTR &= ~WDTENB_nVal; + +#endif + + +/* Setup the Flash Wait State */ +#if PMU_FLASH +temp = FLASH0->FCON; +temp &= ~FLASH_FCON_WSPFLASH_Msk; +temp |= PMU_FLASH_WS+3; +FLASH0->FCON = temp; +#endif + + +/* Setup the clockout */ +#if SCU_CLOCKOUT_SETUP + +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; +/*set PLL div for clkout */ +SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; + +if (SCU_CLOCKOUT_PIN) { + PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ + PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); + PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ + } +else { + PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ + PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ + } + +#endif + + +/* Setup the System clock */ +#if SCU_CLOCK_SETUP +SystemClockSetup(); +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ + + +/* Setup the USB PL */ +#if SCU_USB_CLOCK_SETUP +USBClockSetup(); +#endif + + + +} + + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ +unsigned int PDIV; +unsigned int NDIV; +unsigned int K2DIV; +unsigned int long VCO; + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +if (SCU_CLK->SYSCLKCR == 0x00010000) +{ + if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ + /* check if PLL is locked */ + /* read back divider settings */ + PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; + NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; + K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; + + if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ + /* the selected clock is the Backup clock fofi */ + VCO = (CLOCK_BACK_UP/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + + } + else + { + /* the selected clock is the PLL external oscillator */ + VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; + SystemCoreClock = VCO/K2DIV; + /* in case the sysclock div is used */ + SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); + } + + + } +} +else +{ +SystemCoreClock = CLOCK_BACK_UP; +} + + +} + + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_CLOCK_SETUP == 1) +static int SystemClockSetup(void) +{ +int temp; +unsigned int long VCO; +int stepping_K2DIV; + +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ +/* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + +} + +/* Enable OSC_HP if not already on*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) + { + /********************************************************************************************************************/ + /* Use external crystal for PLL clock input */ + /********************************************************************************************************************/ + + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* select external OSC as PLL input */ + SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) + { + /********************************************************************************************************************/ + /* Use factory trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + } + else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) + { + /********************************************************************************************************************/ + /* Use automatic trimming Back-up clock for PLL clock input */ + /********************************************************************************************************************/ + /* check for HIB Domain enabled */ + if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) + SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ + + /* check for HIB Domain is not in reset state */ + if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) + SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ + + /* PLL Back up clock selected */ + SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; + + if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) + { + /****************************************************************************************************************/ + /* Use fOSI as source of the standby clock */ + /****************************************************************************************************************/ + SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + } + else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) + { + /****************************************************************************************************************/ + /* Use fULP as source of the standby clock */ + /****************************************************************************************************************/ + /*check OSCUL if running correct*/ + if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) + { + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); + + SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ + /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ + /* select OSCUL clock for RTC*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*enable OSCULP WDG Alarm Enable*/ + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + /*wait now for clock is stable */ + do + { + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + for(temp=0;temp<=0xFFFF;temp++); + } + while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); + + SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); + } + // now OSCULP is running and can be used + SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; + while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); + + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; + /*TRIAL for delay loop*/ + for(temp=0;temp<=0xFFFF;temp++); + + } + } + + /********************************************************************************************************************/ + /* Setup and look the main PLL */ + /********************************************************************************************************************/ + +if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ + /* Systen is still running from internal clock */ + /* select FOFI as system clock */ + if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ + + + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/24000000)-1; + /* Go to bypass the Main PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; + /* disconnect OSC_HP to PLL */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + /* we may have to set OSCDISCDIS */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + /* connect OSC_HP to PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; + /* wait for PLL Lock */ + /* setup time out loop */ + /* Timeout for wait loo ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + + if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) + { + /* Go back to the Main PLL */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; + } + else return(0); + + + /********************************************************* + here we need to setup the system clock divider + *********************************************************/ + + SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; + SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; + SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; + + + /* Switch system clock to PLL */ + SCU_CLK->SYSCLKCR |= 0x00010000; + + /* we may have to reset OSCDISCDIS */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; + + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /*********************************************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 60MHz + *********************************************************/ + if (CLOCK_FSYS > 60000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/60000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /********************************************************* + here the ramp up of the system clock starts FSys < 90MHz + *********************************************************/ + if (CLOCK_FSYS > 90000000){ + /*calulation for stepping*/ + if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) + VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); + + stepping_K2DIV = (VCO/90000000)-1; + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + } + else + { + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + return(1); + } + + /*********************************************************/ + /* Delay for next K2 step ~50µs */ + /*********************************************************/ + SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + + while (SysTick->VAL >= 100); /* wait for ~50µs */ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + /********************************/ + + /* Setup devider settings for main PLL */ + SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); + + SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ + } + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + +/** + * @brief - + * @note - + * @param None + * @retval None + */ +#if (SCU_USB_CLOCK_SETUP == 1) +static int USBClockSetup(void) +{ +/* this weak function enables DAVE3 clock App usage */ +if(AllowPLLInitByStartup()){ + +/* check if PLL is switched on */ +if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); +} + +/* check and if not already running enable OSC_HP */ + if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ + /* check if Main PLL is switched on for OSC WD*/ + if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ + /* enable PLL first */ + SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); + } + SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ + /* setup OSC WDG devider */ + SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); + /* restart OSC Watchdog */ + SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; + + /* Timeout for wait loop ~150ms */ + /********************************/ + SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + do + { + ;/* wait for ~150ms */ + }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ + if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) + return(0);/* Return Error */ + + } + + +/* Setup USB PLL */ + /* Go to bypass the Main PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; + /* disconnect OSC_FI to PLL */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; + /* Setup devider settings for main PLL */ + SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); + /* Setup USBDIV settings USB clock */ + SCU_CLK->USBCLKCR = SCU_USBDIV; + /* we may have to set OSCDISCDIS */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; + /* connect OSC_FI to PLL */ + SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; + /* restart PLL Lock detection */ + SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; + /* wait for PLL Lock */ + while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); + + }/* end this weak function enables DAVE3 clock App usage */ + return(1); + +} +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4400.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4400.h new file mode 100644 index 000000000..953e1b099 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4000_Keil/system_XMC4400.h @@ -0,0 +1,72 @@ +/**************************************************************************//** + * @file system_XMC4400.h + * @brief Header file for the XMC4400-Series systeminit + * + * @version V1.0 + * @date 17. August 2012 + * + * @note + * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. + * This file can be freely distributed within development tools that are supporting such microcontrollers. + + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + * + ******************************************************************************/ + + +#ifndef __SYSTEM_XMC4400_H +#define __SYSTEM_XMC4400_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +extern void SystemInit (void); + + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/* this weak function enables DAVE3 clock App usage */ +extern uint32_t AllowPLLInitByStartup(void); + + + +#ifdef __cplusplus +} +#endif + + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h deleted file mode 100644 index 51df1616b..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/FreeRTOSConfig.h +++ /dev/null @@ -1,200 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -/* Ensure stdint is only used by the compiler, and not the assembler. */ -#ifdef __ICCARM__ - #include - extern uint32_t SystemCoreClock; -#endif /* __ICCARM__ */ - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 1 -#define configCPU_CLOCK_HZ ( SystemCoreClock ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) ) -#define configMAX_TASK_NAME_LEN ( 10 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configQUEUE_REGISTRY_SIZE 8 -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configGENERATE_RUN_TIME_STATS 0 -#define configUSE_QUEUE_SETS 1 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( 2 ) -#define configTIMER_QUEUE_LENGTH 5 -#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - -/* Cortex-M specific definitions. */ -#ifdef __NVIC_PRIO_BITS - /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ - #define configPRIO_BITS __NVIC_PRIO_BITS -#else - #define configPRIO_BITS 6 /* 63 priority levels */ -#endif - -/* The lowest interrupt priority that can be used in a call to a "set priority" -function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f - -/* The highest interrupt priority that can be used by any interrupt service -routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL -INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER -PRIORITY THAN THIS! (higher priorities are lower numeric values. */ -#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 - -/* Interrupt priorities used by the kernel port layer itself. These are generic -to all Cortex-M ports, and do not rely on any particular library functions. */ -#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) -/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! -See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ -#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) - -/* Normal assert() semantics without relying on the provision of an assert.h -header file. */ -#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } - -/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS -standard names. */ -#define vPortSVCHandler SVC_Handler -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler - -/* Demo application specific settings. */ -#ifdef __ICCARM__ - #if defined( PART_XMC4500 ) - /* Hardware includes. */ - #include "XMC4500.h" - #include "System_XMC4500.h" - - /* Configure pin P3.9 for the LED. */ - #define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 ) - /* To toggle the single LED */ - #define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 ) - #elif defined( PART_XMC4400 ) - /* Hardware includes. */ - #include "XMC4400.h" - #include "System_XMC4200.h" - - /* Configure pin P5.2 for the LED. */ - #define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 ) - /* To toggle the single LED */ - #define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 ) - #elif defined( PART_XMC4200 ) - /* Hardware includes. */ - #include "XMC4200.h" - #include "System_XMC4200.h" - - /* Configure pin P2.1 for the LED. */ - #define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL - /* To toggle the single LED */ - #define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 ) - #else - #error Part number not specified in project options - #endif -#endif - -#endif /* FREERTOS_CONFIG_H */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd deleted file mode 100644 index 10b837d23..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.ewd +++ /dev/null @@ -1,3898 +0,0 @@ - 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- XMC4500 - XMC4200 - - - - $PROJ_DIR$\system\startup_XMC4500.s - - XMC4200 - XMC4400 - - - - $PROJ_DIR$\system\System_XMC4200.c - - XMC4500 - XMC4400 - - - - $PROJ_DIR$\system\System_XMC4400.c - - XMC4500 - XMC4200 - - - - $PROJ_DIR$\system\system_XMC4500.c - - XMC4200 - XMC4400 - - - - - $PROJ_DIR$\FreeRTOSConfig.h - - - $PROJ_DIR$\main.c - - - $PROJ_DIR$\main_blinky.c - - - $PROJ_DIR$\main_full.c - - - $PROJ_DIR$\RegTest.s - - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.eww b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.eww deleted file mode 100644 index 239a9381e..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RTOSDemo.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\RTOSDemo.ewp - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s deleted file mode 100644 index 45105d369..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/RegTest.s +++ /dev/null @@ -1,525 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -#include - - - RSEG CODE:CODE(2) - thumb - - EXTERN ulRegTest1LoopCounter - EXTERN ulRegTest2LoopCounter - - PUBLIC vRegTest1Task - PUBLIC vRegTest2Task - PUBLIC vRegTestClearFlopRegistersToParameterValue - PUBLIC ulRegTestCheckFlopRegistersContainParameterValue - -/*-----------------------------------------------------------*/ - -vRegTest1Task - - /* Fill the core registers with known values. */ - mov r0, #100 - mov r1, #101 - mov r2, #102 - mov r3, #103 - mov r4, #104 - mov r5, #105 - mov r6, #106 - mov r7, #107 - mov r8, #108 - mov r9, #109 - mov r10, #110 - mov r11, #111 - mov r12, #112 - - /* Fill the VFP registers with known values. */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - -reg1_loop: - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d1 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d2 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d3 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - vmov r0, r1, d4 - cmp r0, #108 - bne reg1_error_loopf - cmp r1, #109 - bne reg1_error_loopf - vmov r0, r1, d5 - cmp r0, #110 - bne reg1_error_loopf - cmp r1, #111 - bne reg1_error_loopf - vmov r0, r1, d6 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d7 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d8 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d9 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - vmov r0, r1, d10 - cmp r0, #108 - bne reg1_error_loopf - cmp r1, #109 - bne reg1_error_loopf - vmov r0, r1, d11 - cmp r0, #110 - bne reg1_error_loopf - cmp r1, #111 - bne reg1_error_loopf - vmov r0, r1, d12 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d13 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d14 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d15 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg1_loopf_pass - -reg1_error_loopf - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg1_error_loopf - -reg1_loopf_pass - - cmp r0, #100 - bne reg1_error_loop - cmp r1, #101 - bne reg1_error_loop - cmp r2, #102 - bne reg1_error_loop - cmp r3, #103 - bne reg1_error_loop - cmp r4, #104 - bne reg1_error_loop - cmp r5, #105 - bne reg1_error_loop - cmp r6, #106 - bne reg1_error_loop - cmp r7, #107 - bne reg1_error_loop - cmp r8, #108 - bne reg1_error_loop - cmp r9, #109 - bne reg1_error_loop - cmp r10, #110 - bne reg1_error_loop - cmp r11, #111 - bne reg1_error_loop - cmp r12, #112 - bne reg1_error_loop - - /* Everything passed, increment the loop counter. */ - push { r0-r1 } - ldr r0, =ulRegTest1LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r0-r1 } - - /* Start again. */ - b reg1_loop - -reg1_error_loop: - /* If this line is hit then there was an error in a core register value. - The loop ensures the loop counter stops incrementing. */ - b reg1_error_loop - -/*-----------------------------------------------------------*/ - - -vRegTest2Task - - /* Set all the core registers to known values. */ - mov r0, #-1 - mov r1, #1 - mov r2, #2 - mov r3, #3 - mov r4, #4 - mov r5, #5 - mov r6, #6 - mov r7, #7 - mov r8, #8 - mov r9, #9 - mov r10, #10 - mov r11, #11 - mov r12, #12 - - /* Set all the VFP to known values. */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - -reg2_loop: - - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d1 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d2 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d3 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - vmov r0, r1, d4 - cmp r0, #8 - bne reg2_error_loopf - cmp r1, #9 - bne reg2_error_loopf - vmov r0, r1, d5 - cmp r0, #10 - bne reg2_error_loopf - cmp r1, #11 - bne reg2_error_loopf - vmov r0, r1, d6 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d7 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d8 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d9 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - vmov r0, r1, d10 - cmp r0, #8 - bne reg2_error_loopf - cmp r1, #9 - bne reg2_error_loopf - vmov r0, r1, d11 - cmp r0, #10 - bne reg2_error_loopf - cmp r1, #11 - bne reg2_error_loopf - vmov r0, r1, d12 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d13 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d14 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d15 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg2_loopf_pass - -reg2_error_loopf - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg2_error_loopf - -reg2_loopf_pass - - cmp r0, #-1 - bne reg2_error_loop - cmp r1, #1 - bne reg2_error_loop - cmp r2, #2 - bne reg2_error_loop - cmp r3, #3 - bne reg2_error_loop - cmp r4, #4 - bne reg2_error_loop - cmp r5, #5 - bne reg2_error_loop - cmp r6, #6 - bne reg2_error_loop - cmp r7, #7 - bne reg2_error_loop - cmp r8, #8 - bne reg2_error_loop - cmp r9, #9 - bne reg2_error_loop - cmp r10, #10 - bne reg2_error_loop - cmp r11, #11 - bne reg2_error_loop - cmp r12, #12 - bne reg2_error_loop - - /* Increment the loop counter to indicate this test is still functioning - correctly. */ - push { r0-r1 } - ldr r0, =ulRegTest2LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - - /* Yield to increase test coverage. */ - movs r0, #0x01 - ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ - lsl r0, r0, #28 /* Shift to PendSV bit */ - str r0, [r1] - dsb - - pop { r0-r1 } - - /* Start again. */ - b reg2_loop - -reg2_error_loop: - /* If this line is hit then there was an error in a core register value. - This loop ensures the loop counter variable stops incrementing. */ - b reg2_error_loop - -/*-----------------------------------------------------------*/ - -vRegTestClearFlopRegistersToParameterValue - - /* Clobber the auto saved registers. */ - vmov d0, r0, r0 - vmov d1, r0, r0 - vmov d2, r0, r0 - vmov d3, r0, r0 - vmov d4, r0, r0 - vmov d5, r0, r0 - vmov d6, r0, r0 - vmov d7, r0, r0 - bx lr - -/*-----------------------------------------------------------*/ - -ulRegTestCheckFlopRegistersContainParameterValue - - vmov r1, s0 - cmp r0, r1 - bne return_error - vmov r1, s1 - cmp r0, r1 - bne return_error - vmov r1, s2 - cmp r0, r1 - bne return_error - vmov r1, s3 - cmp r0, r1 - bne return_error - vmov r1, s4 - cmp r0, r1 - bne return_error - vmov r1, s5 - cmp r0, r1 - bne return_error - vmov r1, s6 - cmp r0, r1 - bne return_error - vmov r1, s7 - cmp r0, r1 - bne return_error - vmov r1, s8 - cmp r0, r1 - bne return_error - vmov r1, s9 - cmp r0, r1 - bne return_error - vmov r1, s10 - cmp r0, r1 - bne return_error - vmov r1, s11 - cmp r0, r1 - bne return_error - vmov r1, s12 - cmp r0, r1 - bne return_error - vmov r1, s13 - cmp r0, r1 - bne return_error - vmov r1, s14 - cmp r0, r1 - bne return_error - vmov r1, s15 - cmp r0, r1 - bne return_error - -return_pass - mov r0, #1 - bx lr - -return_error - mov r0, #0 - bx lr - - END - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/XMC4500_Flash.icf b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/XMC4500_Flash.icf deleted file mode 100644 index 7c7a4f309..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/XMC4500_Flash.icf +++ /dev/null @@ -1,41 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x0C000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x0C000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0C0FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x10000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x1000FFFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x400; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __DRAM1_start__ = 0x20000000; -define symbol __DRAM1_end__ = 0x20007FFF; - -define symbol __DRAM2_start__ = 0x30000000; -define symbol __DRAM2_end__ = 0x30007FFF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region DRAM1_region = mem:[from __DRAM1_start__ to __DRAM1_end__]; -define region DRAM2_region = mem:[from __DRAM2_start__ to __DRAM2_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region {readonly}; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; -place in DRAM1_region{ section .dram1}; -place in DRAM2_region{ section .dram2}; - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c deleted file mode 100644 index 9dfc362fd..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * This project provides two demo applications. A simple blinky style project, - * and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to - * select between the two. The simply blinky demo is implemented and described - * in main_blinky.c. The more comprehensive test and demo application is - * implemented and described in main_full.c. - * - * This file implements the code that is not demo specific, including the - * hardware setup and FreeRTOS hook functions. - * - * - * Additional code: - * - * This demo does not contain a non-kernel interrupt service routine that - * can be used as an example for application writers to use as a reference. - * Therefore, the framework of a dummy (not installed) handler is provided - * in this file. The dummy function is called Dummy_IRQHandler(). Please - * ensure to read the comments in the function itself, but more importantly, - * the notes on the function contained on the documentation page for this demo - * that is found on the FreeRTOS.org web site. - */ - -/* Standard includes. */ -#include - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Standard demo includes. */ -#include "QueueSet.h" -#include "QueueOverwrite.h" - -/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 - -/*-----------------------------------------------------------*/ - -/* - * Set up the hardware ready to run this demo. - */ -static void prvSetupHardware( void ); - -/* - * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. - * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. - */ -extern void main_blinky( void ); -extern void main_full( void ); - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - configCONFIGURE_LED(); - - /* Ensure all priority bits are assigned as preemption priority bits. */ - NVIC_SetPriorityGrouping( 0 ); -} -/*-----------------------------------------------------------*/ - -void vApplicationMallocFailedHook( void ) -{ - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ -} -/*-----------------------------------------------------------*/ - -void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName ) -{ - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); -} -/*-----------------------------------------------------------*/ - -void vApplicationTickHook( void ) -{ - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ - - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 - { - /* Write to a queue that is in use as part of the queue set demo to - demonstrate using queue sets from an ISR. */ - vQueueSetAccessQueueSetFromISR(); - - /* Test the ISR safe queue overwrite functions. */ - vQueueOverwritePeriodicISRDemo(); - } - #endif /* mainCREATE_SIMPLE_BLINKY_DEMO_ONLY */ -} -/*-----------------------------------------------------------*/ - -#ifdef JUST_AN_EXAMPLE_ISR - -void Dummy_IRQHandler(void) -{ -long lHigherPriorityTaskWoken = pdFALSE; - - /* Clear the interrupt if necessary. */ - Dummy_ClearITPendingBit(); - - /* This interrupt does nothing more than demonstrate how to synchronise a - task with an interrupt. A semaphore is used for this purpose. Note - lHigherPriorityTaskWoken is initialised to zero. */ - xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); - - /* If there was a task that was blocked on the semaphore, and giving the - semaphore caused the task to unblock, and the unblocked task has a priority - higher than the current Running state task (the task that this interrupt - interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE - internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the - portEND_SWITCHING_ISR() macro will result in a context switch being pended to - ensure this interrupt returns directly to the unblocked, higher priority, - task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ - portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); -} - -#endif /* JUST_AN_EXAMPLE_ISR */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c deleted file mode 100644 index 83d8398d8..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_blinky.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky style - * project, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select - * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY - * in main.c. This file implements the simply blinky style version. - * - * NOTE 2: This file only contains the source code that is specific to the - * basic demo. Generic functions, such FreeRTOS hook functions, and functions - * required to configure the hardware, are defined in main.c. - ****************************************************************************** - * - * main_blinky() creates one queue, and two tasks. It then starts the - * scheduler. - * - * The Queue Send Task: - * The queue send task is implemented by the prvQueueSendTask() function in - * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly - * block for 200 milliseconds, before sending the value 100 to the queue that - * was created within main_blinky(). Once the value is sent, the task loops - * back around to block for another 200 milliseconds. - * - * The Queue Receive Task: - * The queue receive task is implemented by the prvQueueReceiveTask() function - * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly - * blocks on attempts to read data from the queue that was created within - * main_blinky(). When data is received, the task checks the value of the - * data, and if the value equals the expected 100, toggles the LED. The 'block - * time' parameter passed to the queue receive function specifies that the - * task should be held in the Blocked state indefinitely to wait for data to - * be available on the queue. The queue receive task will only leave the - * Blocked state when the queue send task writes to the queue. As the queue - * send task writes to the queue every 200 milliseconds, the queue receive - * task leaves the Blocked state every 200 milliseconds, and therefore toggles - * the LED every 200 milliseconds. - */ - -/* Standard includes. */ -#include - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_RATE_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS ) - -/* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) - -/* Values passed to the two tasks just to check the task parameter -functionality. */ -#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) -#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) - -/*-----------------------------------------------------------*/ - -/* - * The tasks as described in the comments at the top of this file. - */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); - -/* - * Called by main() to create the simply blinky style application if - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. - */ -void main_blinky( void ); - -/*-----------------------------------------------------------*/ - -/* The queue used by both tasks. */ -static xQueueHandle xQueue = NULL; - -/*-----------------------------------------------------------*/ - -void main_blinky( void ) -{ - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvQueueSendTask( void *pvParameters ) -{ -portTickType xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } -} -/*-----------------------------------------------------------*/ - -static void prvQueueReceiveTask( void *pvParameters ) -{ -unsigned long ulReceivedValue; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - configTOGGLE_LED(); - ulReceivedValue = 0U; - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c deleted file mode 100644 index 29c5be7bd..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/main_full.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky style - * project, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select - * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY - * in main.c. This file implements the comprehensive test and demo version. - * - * NOTE 2: This file only contains the source code that is specific to the - * full demo. Generic functions, such FreeRTOS hook functions, and functions - * required to configure the hardware, are defined in main.c. - ****************************************************************************** - * - * main_full() creates all the demo application tasks and a software timer, then - * starts the scheduler. The web documentation provides more details of the - * standard demo application tasks, which provide no particular functionality, - * but do provide a good example of how to use the FreeRTOS API. - * - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Reg test" tasks - These fill both the core and floating point registers with - * known values, then check that each register maintains its expected value for - * the lifetime of the task. Each task uses a different set of values. The reg - * test tasks execute with a very low priority, so get preempted very - * frequently. A register containing an unexpected value is indicative of an - * error in the context switching mechanism. - * - * "Check" timer - The check software timer period is initially set to three - * seconds. The callback function associated with the check software timer - * checks that all the standard demo tasks, and the register check tasks, are - * not only still executing, but are executing without reporting any errors. If - * the check software timer discovers that a task has either stalled, or - * reported an error, then it changes its own execution period from the initial - * three seconds, to just 200ms. The check software timer callback function - * also toggles the single LED each time it is called. This provides a visual - * indication of the system status: If the LED toggles every three seconds, - * then no issues have been discovered. If the LED toggles every 200ms, then - * an issue has been discovered with at least one task. - */ - -/* Standard includes. */ -#include - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "semphr.h" - -/* Standard demo application includes. */ -#include "flop.h" -#include "semtest.h" -#include "dynamic.h" -#include "blocktim.h" -#include "countsem.h" -#include "GenQTest.h" -#include "recmutex.h" -#include "QueueSet.h" -#include "QueueOverwrite.h" - -/* Priorities for the demo application tasks. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) - -/* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) - -/* The period after which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_RATE_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS ) - -/* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_RATE_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS ) - -/*-----------------------------------------------------------*/ - -/* - * The check timer callback function, as described at the top of this file. - */ -static void prvCheckTimerCallback( xTimerHandle xTimer ); - -/* - * Register check tasks, and the tasks used to write over and check the contents - * of the FPU registers, as described at the top of this file. The nature of - * these files necessitates that they are written in an assembly file. - */ -extern void vRegTest1Task( void *pvParameters ); -extern void vRegTest2Task( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The following two variables are used to communicate the status of the -register check tasks to the check software timer. If the variables keep -incrementing, then the register check tasks has not discovered any errors. If -a variable stops incrementing, then an error has been found. */ -volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; - -/*-----------------------------------------------------------*/ - -void main_full( void ) -{ -xTimerHandle xCheckTimer = NULL; - - /* Start all the other standard demo/test tasks. The have not particular - functionality, but do demonstrate how to use the FreeRTOS API and test the - kernel port. */ - vStartQueueSetTasks(); - vStartQueueOverwriteTask( tskIDLE_PRIORITY ); - vStartDynamicPriorityTasks(); - vCreateBlockTimeTasks(); - vStartGenericQueueTasks( tskIDLE_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - - /* Create the register check tasks, as described at the top of this - file */ - xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - if( xCheckTimer != NULL ) - { - xTimerStart( xCheckTimer, mainDONT_BLOCK ); - } - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvCheckTimerCallback( xTimerHandle xTimer ) -{ -static long lChangedTimerPeriodAlready = pdFALSE; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorFound = pdFALSE; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreQueueSetTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. */ - configTOGGLE_LED(); - - /* Have any errors been latch in ulErrorFound? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( ulErrorFound != pdFALSE ) - { - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block. */ - xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4200.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4200.c deleted file mode 100644 index d2385b4b1..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4200.c +++ /dev/null @@ -1,708 +0,0 @@ -/**************************************************************************//** - * @file system_XMC4200.c - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File - * for the Infineon XMC4000 Device Series - * @version V3.0.1 Alpha - * @date 26. September 2012 - * - * @note - * Copyright (C) 2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include -#include - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemCoreClock; - -/* clock definitions, do not modify! */ -#define SCU_CLOCK_CRYSTAL 1 -#define SCU_CLOCK_BACK_UP_FACTORY 2 -#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 - - -#define HIB_CLOCK_FOSI 1 -#define HIB_CLOCK_OSCULP 2 - - - - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - - - -/*--------------------- Watchdog Configuration ------------------------------- -// -// Watchdog Configuration -// Disable Watchdog -// -// -*/ -#define WDT_SETUP 1 -#define WDTENB_nVal 0x00000001 - -/*--------------------- CLOCK Configuration ------------------------------- -// -// Main Clock Configuration -// CPU clock divider -// <0=> fCPU = fSYS -// <1=> fCPU = fSYS / 2 -// Peripheral Bus clock divider -// <0=> fPB = fCPU -// <1=> fPB = fCPU / 2 -// CCU Bus clock divider -// <0=> fCCU = fCPU -// <1=> fCCU = fCPU / 2 -// -// -// -*/ - -#define SCU_CLOCK_SETUP 1 -#define SCU_CPUCLKCR_DIV 0x00000000 -#define SCU_PBCLKCR_DIV 0x00000000 -#define SCU_CCUCLKCR_DIV 0x00000000 -/* not avalible in config wizzard*/ -/* -* mandatory clock parameters ************************************************** -* -* source for clock generation -* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) -* -**************************************************************************************/ -// Selection of imput lock for PLL -/*************************************************************************************/ -#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC - -/*************************************************************************************/ -// Standby clock selection for Backup clock source trimming -/*************************************************************************************/ -#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP -//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI - -/*************************************************************************************/ -// Global clock parameters -/*************************************************************************************/ -#define CLOCK_FSYS 80000000 -#define CLOCK_CRYSTAL_FREQUENCY 12000000 -#define CLOCK_BACK_UP 24000000 - -/*************************************************************************************/ -/* OSC_HP setup parameters */ -/*************************************************************************************/ -#define SCU_OSC_HP_MODE 0xF0 -#define SCU_OSCHPWDGDIV 2 - -/*************************************************************************************/ -/* MAIN PLL setup parameters */ -/*************************************************************************************/ -//Divider settings for external crystal @ 12 MHz -/*************************************************************************************/ -#define SCU_PLL_K1DIV 1 -#define SCU_PLL_K1DIV 1 -#define SCU_PLL_K2DIV 5 -#define SCU_PLL_PDIV 1 -#define SCU_PLL_NDIV 79 - -/*************************************************************************************/ -//Divider settings for use of backup clock source trimmed -/*************************************************************************************/ -//#define SCU_PLL_K1DIV 1 -//#define SCU_PLL_K2DIV 5 -//#define SCU_PLL_PDIV 3 -//#define SCU_PLL_NDIV 79 -/*************************************************************************************/ - - -/*--------------------- USB CLOCK Configuration --------------------------- -// -// USB Clock Configuration -// -// -// -*/ - -#define SCU_USB_CLOCK_SETUP 0 -/* not avalible in config wizzard*/ -#define SCU_USBPLL_PDIV 0 -#define SCU_USBPLL_NDIV 31 -#define SCU_USBDIV 3 - -/*--------------------- Flash Wait State Configuration ------------------------------- -// -// Flash Wait State Configuration -// Flash Wait State -// <0=> 3 WS -// <1=> 4 WS -// <2=> 5 WS -// <3=> 6 WS -// -// -*/ - -#define PMU_FLASH 1 -#define PMU_FLASH_WS 0x00000000 - - -/*--------------------- CLOCKOUT Configuration ------------------------------- -// -// Clock OUT Configuration -// Clockout Source Selection -// <0=> System Clock -// <2=> Divided value of USB PLL output -// <3=> Divided value of PLL Clock -// Clockout divider <1-10><#-1> -// Clockout Pin Selection -// <0=> P1.15 -// <1=> P0.8 -// -// -// -// -*/ - -#define SCU_CLOCKOUT_SETUP 0 -#define SCU_CLOCKOUT_SOURCE 0x00000000 -#define SCU_CLOCKOUT_DIV 0x00000009 -#define SCU_CLOCKOUT_PIN 0x00000001 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -#if SCU_CLOCK_SETUP -uint32_t SystemCoreClock = CLOCK_FSYS; -#else -uint32_t SystemCoreClock = CLOCK_BACK_UP; -#endif - -/*---------------------------------------------------------------------------- - static functions declarations - *----------------------------------------------------------------------------*/ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void); -#endif - -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void); -#endif - - -/** - * @brief Setup the microcontroller system. - * Initialize the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ -int temp; - -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) -SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ -#endif - -/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ -SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); - -/* Setup the WDT */ -#if WDT_SETUP - -WDT->CTR &= ~WDTENB_nVal; - -#endif - - -/* Setup the Flash Wait State */ -#if PMU_FLASH -temp = FLASH0->FCON; -temp &= ~FLASH_FCON_WSPFLASH_Msk; -temp |= PMU_FLASH_WS+3; -FLASH0->FCON = temp; -#endif - - -/* Setup the clockout */ -#if SCU_CLOCKOUT_SETUP - -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; -/*set PLL div for clkout */ -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; - -if (SCU_CLOCKOUT_PIN) { - PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ - PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); - PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ - } -else { - PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ - PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ - } - -#endif - - -/* Setup the System clock */ -#if SCU_CLOCK_SETUP -SystemClockSetup(); -#endif - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ - - -/* Setup the USB PL */ -#if SCU_USB_CLOCK_SETUP -USBClockSetup(); -#endif - - - -} - - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ -unsigned int PDIV; -unsigned int NDIV; -unsigned int K2DIV; -unsigned int long VCO; - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -if (SCU_CLK->SYSCLKCR == 0x00010000) -{ - if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ - /* check if PLL is locked */ - /* read back divider settings */ - PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; - NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; - K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; - - if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ - /* the selected clock is the Backup clock fofi */ - VCO = (CLOCK_BACK_UP/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - - } - else - { - /* the selected clock is the PLL external oscillator */ - VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - } - - - } -} -else -{ -SystemCoreClock = CLOCK_BACK_UP; -} - - -} - - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void) -{ -int temp; -unsigned int long VCO; -int stepping_K2DIV; - -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - -/* check if PLL is switched on */ -if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ -/* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - -} - -/* Enable OSC_HP if not already on*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) - { - /********************************************************************************************************************/ - /* Use external crystal for PLL clock input */ - /********************************************************************************************************************/ - - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* select external OSC as PLL input */ - SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) - { - /********************************************************************************************************************/ - /* Use factory trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) - { - /********************************************************************************************************************/ - /* Use automatic trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* check for HIB Domain enabled */ - if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) - SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ - - /* check for HIB Domain is not in reset state */ - if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) - SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ - - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) - { - /****************************************************************************************************************/ - /* Use fOSI as source of the standby clock */ - /****************************************************************************************************************/ - SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - } - else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) - { - /****************************************************************************************************************/ - /* Use fULP as source of the standby clock */ - /****************************************************************************************************************/ - /*check OSCUL if running correct*/ - if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) - { - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); - - SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ - /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ - /* select OSCUL clock for RTC*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*enable OSCULP WDG Alarm Enable*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*wait now for clock is stable */ - do - { - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - for(temp=0;temp<=0xFFFF;temp++); - } - while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); - - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - } - // now OSCULP is running and can be used - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - } - } - - /********************************************************************************************************************/ - /* Setup and look the main PLL */ - /********************************************************************************************************************/ - -if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ - /* Systen is still running from internal clock */ - /* select FOFI as system clock */ - if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ - - - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/24000000)-1; - /* Go to bypass the Main PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; - /* disconnect OSC_HP to PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - /* we may have to set OSCDISCDIS */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - /* connect OSC_HP to PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; - /* wait for PLL Lock */ - /* setup time out loop */ - /* Timeout for wait loo ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - - if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) - { - /* Go back to the Main PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; - } - else return(0); - - - /********************************************************* - here we need to setup the system clock divider - *********************************************************/ - - SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; - SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; - SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; - - - /* Switch system clock to PLL */ - SCU_CLK->SYSCLKCR |= 0x00010000; - - /* we may have to reset OSCDISCDIS */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /*********************************************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 60MHz - *********************************************************/ - if (CLOCK_FSYS > 60000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/60000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 90MHz - *********************************************************/ - if (CLOCK_FSYS > 90000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/90000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - } - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void) -{ -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - -/* check if PLL is switched on */ -if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); -} - -/* check and if not already running enable OSC_HP */ - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - /* check if Main PLL is switched on for OSC WD*/ - if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - } - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - - -/* Setup USB PLL */ - /* Go to bypass the Main PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; - /* disconnect OSC_FI to PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); - /* Setup USBDIV settings USB clock */ - SCU_CLK->USBCLKCR = SCU_USBDIV; - /* we may have to set OSCDISCDIS */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; - /* connect OSC_FI to PLL */ - SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; - /* wait for PLL Lock */ - while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); - - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4400.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4400.c deleted file mode 100644 index 70162d923..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/System_XMC4400.c +++ /dev/null @@ -1,707 +0,0 @@ -/**************************************************************************//** - * @file system_XMC4400.c - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File - * for the Infineon XMC4500 Device Series - * @version V3.0.1 Alpha - * @date 17. September 2012 - * - * @note - * Copyright (C) 2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include -#include - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemCoreClock; - -/* clock definitions, do not modify! */ -#define SCU_CLOCK_CRYSTAL 1 -#define SCU_CLOCK_BACK_UP_FACTORY 2 -#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 - - -#define HIB_CLOCK_FOSI 1 -#define HIB_CLOCK_OSCULP 2 - - - - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - - - -/*--------------------- Watchdog Configuration ------------------------------- -// -// Watchdog Configuration -// Disable Watchdog -// -// -*/ -#define WDT_SETUP 1 -#define WDTENB_nVal 0x00000001 - -/*--------------------- CLOCK Configuration ------------------------------- -// -// Main Clock Configuration -// CPU clock divider -// <0=> fCPU = fSYS -// <1=> fCPU = fSYS / 2 -// Peripheral Bus clock divider -// <0=> fPB = fCPU -// <1=> fPB = fCPU / 2 -// CCU Bus clock divider -// <0=> fCCU = fCPU -// <1=> fCCU = fCPU / 2 -// -// -// -*/ - -#define SCU_CLOCK_SETUP 1 -#define SCU_CPUCLKCR_DIV 0x00000000 -#define SCU_PBCLKCR_DIV 0x00000000 -#define SCU_CCUCLKCR_DIV 0x00000000 -/* not avalible in config wizzard*/ -/* -* mandatory clock parameters ************************************************** -* -* source for clock generation -* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) -* -**************************************************************************************/ -// Selection of imput lock for PLL -/*************************************************************************************/ -#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC - -/*************************************************************************************/ -// Standby clock selection for Backup clock source trimming -/*************************************************************************************/ -#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP -//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI - -/*************************************************************************************/ -// Global clock parameters -/*************************************************************************************/ -#define CLOCK_FSYS 120000000 -#define CLOCK_CRYSTAL_FREQUENCY 12000000 -#define CLOCK_BACK_UP 24000000 - -/*************************************************************************************/ -/* OSC_HP setup parameters */ -/*************************************************************************************/ -#define SCU_OSC_HP_MODE 0xF0 -#define SCU_OSCHPWDGDIV 2 - -/*************************************************************************************/ -/* MAIN PLL setup parameters */ -/*************************************************************************************/ -//Divider settings for external crystal @ 12 MHz -/*************************************************************************************/ -#define SCU_PLL_K1DIV 1 -#define SCU_PLL_K2DIV 3 -#define SCU_PLL_PDIV 1 -#define SCU_PLL_NDIV 79 - -/*************************************************************************************/ -//Divider settings for use of backup clock source trimmed -/*************************************************************************************/ -//#define SCU_PLL_K1DIV 1 -//#define SCU_PLL_K2DIV 3 -//#define SCU_PLL_PDIV 3 -//#define SCU_PLL_NDIV 79 -/*************************************************************************************/ - - -/*--------------------- USB CLOCK Configuration --------------------------- -// -// USB Clock Configuration -// -// -// -*/ - -#define SCU_USB_CLOCK_SETUP 0 -/* not avalible in config wizzard*/ -#define SCU_USBPLL_PDIV 0 -#define SCU_USBPLL_NDIV 31 -#define SCU_USBDIV 3 - -/*--------------------- Flash Wait State Configuration ------------------------------- -// -// Flash Wait State Configuration -// Flash Wait State -// <0=> 3 WS -// <1=> 4 WS -// <2=> 5 WS -// <3=> 6 WS -// -// -*/ - -#define PMU_FLASH 1 -#define PMU_FLASH_WS 0x00000000 - - -/*--------------------- CLOCKOUT Configuration ------------------------------- -// -// Clock OUT Configuration -// Clockout Source Selection -// <0=> System Clock -// <2=> Divided value of USB PLL output -// <3=> Divided value of PLL Clock -// Clockout divider <1-10><#-1> -// Clockout Pin Selection -// <0=> P1.15 -// <1=> P0.8 -// -// -// -// -*/ - -#define SCU_CLOCKOUT_SETUP 0 -#define SCU_CLOCKOUT_SOURCE 0x00000000 -#define SCU_CLOCKOUT_DIV 0x00000009 -#define SCU_CLOCKOUT_PIN 0x00000001 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -#if SCU_CLOCK_SETUP -uint32_t SystemCoreClock = CLOCK_FSYS; -#else -uint32_t SystemCoreClock = CLOCK_BACK_UP; -#endif - -/*---------------------------------------------------------------------------- - static functions declarations - *----------------------------------------------------------------------------*/ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void); -#endif - -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void); -#endif - - -/** - * @brief Setup the microcontroller system. - * Initialize the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ -int temp; - -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) -SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ -#endif - -/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ -SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); - -/* Setup the WDT */ -#if WDT_SETUP - -WDT->CTR &= ~WDTENB_nVal; - -#endif - - -/* Setup the Flash Wait State */ -#if PMU_FLASH -temp = FLASH0->FCON; -temp &= ~FLASH_FCON_WSPFLASH_Msk; -temp |= PMU_FLASH_WS+3; -FLASH0->FCON = temp; -#endif - - -/* Setup the clockout */ -#if SCU_CLOCKOUT_SETUP - -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; -/*set PLL div for clkout */ -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; - -if (SCU_CLOCKOUT_PIN) { - PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ - PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); - PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ - } -else { - PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ - PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ - } - -#endif - - -/* Setup the System clock */ -#if SCU_CLOCK_SETUP -SystemClockSetup(); -#endif - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ - - -/* Setup the USB PL */ -#if SCU_USB_CLOCK_SETUP -USBClockSetup(); -#endif - - - -} - - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ -unsigned int PDIV; -unsigned int NDIV; -unsigned int K2DIV; -unsigned int long VCO; - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -if (SCU_CLK->SYSCLKCR == 0x00010000) -{ - if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ - /* check if PLL is locked */ - /* read back divider settings */ - PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; - NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; - K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; - - if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ - /* the selected clock is the Backup clock fofi */ - VCO = (CLOCK_BACK_UP/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - - } - else - { - /* the selected clock is the PLL external oscillator */ - VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - } - - - } -} -else -{ -SystemCoreClock = CLOCK_BACK_UP; -} - - -} - - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void) -{ -int temp; -unsigned int long VCO; -int stepping_K2DIV; - -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - -/* check if PLL is switched on */ -if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ -/* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - -} - -/* Enable OSC_HP if not already on*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) - { - /********************************************************************************************************************/ - /* Use external crystal for PLL clock input */ - /********************************************************************************************************************/ - - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* select external OSC as PLL input */ - SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) - { - /********************************************************************************************************************/ - /* Use factory trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) - { - /********************************************************************************************************************/ - /* Use automatic trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* check for HIB Domain enabled */ - if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) - SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ - - /* check for HIB Domain is not in reset state */ - if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) - SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ - - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) - { - /****************************************************************************************************************/ - /* Use fOSI as source of the standby clock */ - /****************************************************************************************************************/ - SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - } - else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) - { - /****************************************************************************************************************/ - /* Use fULP as source of the standby clock */ - /****************************************************************************************************************/ - /*check OSCUL if running correct*/ - if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) - { - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); - - SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ - /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ - /* select OSCUL clock for RTC*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*enable OSCULP WDG Alarm Enable*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*wait now for clock is stable */ - do - { - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - for(temp=0;temp<=0xFFFF;temp++); - } - while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); - - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - } - // now OSCULP is running and can be used - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - } - } - - /********************************************************************************************************************/ - /* Setup and look the main PLL */ - /********************************************************************************************************************/ - -if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ - /* Systen is still running from internal clock */ - /* select FOFI as system clock */ - if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ - - - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/24000000)-1; - /* Go to bypass the Main PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; - /* disconnect OSC_HP to PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - /* we may have to set OSCDISCDIS */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - /* connect OSC_HP to PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; - /* wait for PLL Lock */ - /* setup time out loop */ - /* Timeout for wait loo ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - - if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) - { - /* Go back to the Main PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; - } - else return(0); - - - /********************************************************* - here we need to setup the system clock divider - *********************************************************/ - - SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; - SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; - SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; - - - /* Switch system clock to PLL */ - SCU_CLK->SYSCLKCR |= 0x00010000; - - /* we may have to reset OSCDISCDIS */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /*********************************************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 60MHz - *********************************************************/ - if (CLOCK_FSYS > 60000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/60000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 90MHz - *********************************************************/ - if (CLOCK_FSYS > 90000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/90000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - } - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void) -{ -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - -/* check if PLL is switched on */ -if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); -} - -/* check and if not already running enable OSC_HP */ - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - /* check if Main PLL is switched on for OSC WD*/ - if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - } - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - - -/* Setup USB PLL */ - /* Go to bypass the Main PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; - /* disconnect OSC_FI to PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); - /* Setup USBDIV settings USB clock */ - SCU_CLK->USBCLKCR = SCU_USBDIV; - /* we may have to set OSCDISCDIS */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; - /* connect OSC_FI to PLL */ - SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; - /* wait for PLL Lock */ - while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); - - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4200.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4200.h deleted file mode 100644 index 3984b45cb..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/XMC4200.h +++ /dev/null @@ -1,13138 +0,0 @@ - -/****************************************************************************************************//** - * @file XMC4200.h - * - * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for - * XMC4200 from Infineon. - * - * @version V1.1.0 (Reference Manual v1.1) - * @date 10. January 2013 - * - * @note Generated with SVDConv V2.78b - * from CMSIS SVD File 'XMC4200_Processed_SVD.xml' Version 1.1.0 (Reference Manual v1.1), - *******************************************************************************************************/ - - - -/** @addtogroup Infineon - * @{ - */ - -/** @addtogroup XMC4200 - * @{ - */ - -#ifndef XMC4200_H -#define XMC4200_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { -/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* --------------------- XMC4200 Specific Interrupt Numbers --------------------- */ - SCU_0_IRQn = 0, /*!< 0 SCU_0 */ - ERU0_0_IRQn = 1, /*!< 1 ERU0_0 */ - ERU0_1_IRQn = 2, /*!< 2 ERU0_1 */ - ERU0_2_IRQn = 3, /*!< 3 ERU0_2 */ - ERU0_3_IRQn = 4, /*!< 4 ERU0_3 */ - ERU1_0_IRQn = 5, /*!< 5 ERU1_0 */ - ERU1_1_IRQn = 6, /*!< 6 ERU1_1 */ - ERU1_2_IRQn = 7, /*!< 7 ERU1_2 */ - ERU1_3_IRQn = 8, /*!< 8 ERU1_3 */ - PMU0_0_IRQn = 12, /*!< 12 PMU0_0 */ - VADC0_C0_0_IRQn = 14, /*!< 14 VADC0_C0_0 */ - VADC0_C0_1_IRQn = 15, /*!< 15 VADC0_C0_1 */ - VADC0_C0_2_IRQn = 16, /*!< 16 VADC0_C0_2 */ - VADC0_C0_3_IRQn = 17, /*!< 17 VADC0_C0_3 */ - VADC0_G0_0_IRQn = 18, /*!< 18 VADC0_G0_0 */ - VADC0_G0_1_IRQn = 19, /*!< 19 VADC0_G0_1 */ - VADC0_G0_2_IRQn = 20, /*!< 20 VADC0_G0_2 */ - VADC0_G0_3_IRQn = 21, /*!< 21 VADC0_G0_3 */ - VADC0_G1_0_IRQn = 22, /*!< 22 VADC0_G1_0 */ - VADC0_G1_1_IRQn = 23, /*!< 23 VADC0_G1_1 */ - VADC0_G1_2_IRQn = 24, /*!< 24 VADC0_G1_2 */ - VADC0_G1_3_IRQn = 25, /*!< 25 VADC0_G1_3 */ - DAC0_0_IRQn = 42, /*!< 42 DAC0_0 */ - DAC0_1_IRQn = 43, /*!< 43 DAC0_1 */ - CCU40_0_IRQn = 44, /*!< 44 CCU40_0 */ - CCU40_1_IRQn = 45, /*!< 45 CCU40_1 */ - CCU40_2_IRQn = 46, /*!< 46 CCU40_2 */ - CCU40_3_IRQn = 47, /*!< 47 CCU40_3 */ - CCU41_0_IRQn = 48, /*!< 48 CCU41_0 */ - CCU41_1_IRQn = 49, /*!< 49 CCU41_1 */ - CCU41_2_IRQn = 50, /*!< 50 CCU41_2 */ - CCU41_3_IRQn = 51, /*!< 51 CCU41_3 */ - CCU80_0_IRQn = 60, /*!< 60 CCU80_0 */ - CCU80_1_IRQn = 61, /*!< 61 CCU80_1 */ - CCU80_2_IRQn = 62, /*!< 62 CCU80_2 */ - CCU80_3_IRQn = 63, /*!< 63 CCU80_3 */ - POSIF0_0_IRQn = 68, /*!< 68 POSIF0_0 */ - POSIF0_1_IRQn = 69, /*!< 69 POSIF0_1 */ - HRPWM_0_IRQn = 72, /*!< 72 HRPWM_0 */ - HRPWM_1_IRQn = 73, /*!< 73 HRPWM_1 */ - HRPWM_2_IRQn = 74, /*!< 74 HRPWM_0 */ - HRPWM_3_IRQn = 75, /*!< 75 HRPWM_1 */ - CAN0_0_IRQn = 76, /*!< 76 CAN0_0 */ - CAN0_1_IRQn = 77, /*!< 77 CAN0_1 */ - CAN0_2_IRQn = 78, /*!< 78 CAN0_2 */ - CAN0_3_IRQn = 79, /*!< 79 CAN0_3 */ - CAN0_4_IRQn = 80, /*!< 80 CAN0_4 */ - CAN0_5_IRQn = 81, /*!< 81 CAN0_5 */ - CAN0_6_IRQn = 82, /*!< 82 CAN0_6 */ - CAN0_7_IRQn = 83, /*!< 83 CAN0_7 */ - USIC0_0_IRQn = 84, /*!< 84 USIC0_0 */ - USIC0_1_IRQn = 85, /*!< 85 USIC0_1 */ - USIC0_2_IRQn = 86, /*!< 86 USIC0_2 */ - USIC0_3_IRQn = 87, /*!< 87 USIC0_3 */ - USIC0_4_IRQn = 88, /*!< 88 USIC0_4 */ - USIC0_5_IRQn = 89, /*!< 89 USIC0_5 */ - USIC1_0_IRQn = 90, /*!< 90 USIC1_0 */ - USIC1_1_IRQn = 91, /*!< 91 USIC1_1 */ - USIC1_2_IRQn = 92, /*!< 92 USIC1_2 */ - USIC1_3_IRQn = 93, /*!< 93 USIC1_3 */ - USIC1_4_IRQn = 94, /*!< 94 USIC1_4 */ - USIC1_5_IRQn = 95, /*!< 95 USIC1_5 */ - LEDTS0_0_IRQn = 102, /*!< 102 LEDTS0_0 */ - FCE0_0_IRQn = 104, /*!< 104 FCE0_0 */ - GPDMA0_0_IRQn = 105, /*!< 105 GPDMA0_0 */ - USB0_0_IRQn = 107, /*!< 107 USB0_0 */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */ -#define __CM4_REV 0x0200 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include /*!< Cortex-M4 processor and core peripherals */ -#include "system_XMC4200.h" /*!< XMC4200 System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ -/* Macro to modify desired bitfields of a register */ -#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ - ((uint32_t)mask)) | \ - (reg & ((uint32_t)~((uint32_t)mask))) - -/* Macro to modify desired bitfields of a register */ -#define WR_REG_SIZE(reg, mask, pos, val, size) { \ -uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ -uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ -uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ -uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ -reg = (uint##size##_t) (VAL2 | VAL4);\ -} - -/** Macro to read bitfields from a register */ -#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) - -/** Macro to read bitfields from a register */ -#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ - (uint32_t)mask) >> pos) ) - -/** Macro to set a bit in register */ -#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< /*!< Cortex-M4 processor and core peripherals */ -#include "system_XMC4400.h" /*!< XMC4400 System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ -/* Macro to modify desired bitfields of a register */ -#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ - ((uint32_t)mask)) | \ - (reg & ((uint32_t)~((uint32_t)mask))) - -/* Macro to modify desired bitfields of a register */ -#define WR_REG_SIZE(reg, mask, pos, val, size) { \ -uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ -uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ -uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ -uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ -reg = (uint##size##_t) (VAL2 | VAL4);\ -} - -/** Macro to read bitfields from a register */ -#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) - -/** Macro to read bitfields from a register */ -#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ - (uint32_t)mask) >> pos) ) - -/** Macro to set a bit in register */ -#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< /*!< Cortex-M4 processor and core peripherals */ -#include "system_XMC4500.h" /*!< XMC4500 System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ -/* Macro to modify desired bitfields of a register */ -#define WR_REG(reg, mask, pos, val) reg = (((uint32_t)val << pos) & \ - ((uint32_t)mask)) | \ - (reg & ((uint32_t)~((uint32_t)mask))) - -/* Macro to modify desired bitfields of a register */ -#define WR_REG_SIZE(reg, mask, pos, val, size) { \ -uint##size##_t VAL1 = (uint##size##_t)((uint##size##_t)val << pos); \ -uint##size##_t VAL2 = (uint##size##_t) (VAL1 & (uint##size##_t)mask); \ -uint##size##_t VAL3 = (uint##size##_t)~((uint##size##_t)mask); \ -uint##size##_t VAL4 = (uint##size##_t) ((uint##size##_t)reg & VAL3); \ -reg = (uint##size##_t) (VAL2 | VAL4);\ -} - -/** Macro to read bitfields from a register */ -#define RD_REG(reg, mask, pos) (((uint32_t)reg & (uint32_t)mask) >> pos) - -/** Macro to read bitfields from a register */ -#define RD_REG_SIZE(reg, mask, pos,size) ((uint##size##_t)(((uint32_t)reg & \ - (uint32_t)mask) >> pos) ) - -/** Macro to set a bit in register */ -#define SET_BIT(reg, pos) (reg |= ((uint32_t)1< - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -extern void SystemInit (void); - - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/* this weak function enables DAVE3 clock App usage */ -extern uint32_t AllowPLLInitByStartup(void); - - - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4400.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4400.h deleted file mode 100644 index 953e1b099..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4400.h +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************//** - * @file system_XMC4400.h - * @brief Header file for the XMC4400-Series systeminit - * - * @version V1.0 - * @date 17. August 2012 - * - * @note - * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. - - * - * @par - * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. - * This file can be freely distributed within development tools that are supporting such microcontrollers. - - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - * - ******************************************************************************/ - - -#ifndef __SYSTEM_XMC4400_H -#define __SYSTEM_XMC4400_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -extern void SystemInit (void); - - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/* this weak function enables DAVE3 clock App usage */ -extern uint32_t AllowPLLInitByStartup(void); - - - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.c deleted file mode 100644 index 74ecf74d3..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.c +++ /dev/null @@ -1,705 +0,0 @@ -/**************************************************************************//** - * @file system_XMC4500.c - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File - * for the Infineon XMC4500 Device Series - * @version V3.0.1 Alpha - * @date 17. September 2012 - * - * @note - * Copyright (C) 2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include "system_XMC4500.h" -#include - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemCoreClock; - -/* clock definitions, do not modify! */ -#define SCU_CLOCK_CRYSTAL 1 -#define SCU_CLOCK_BACK_UP_FACTORY 2 -#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 - - -#define HIB_CLOCK_FOSI 1 -#define HIB_CLOCK_OSCULP 2 - - - - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - - - -/*--------------------- Watchdog Configuration ------------------------------- -// -// Watchdog Configuration -// Disable Watchdog -// -// -*/ -#define WDT_SETUP 1 -#define WDTENB_nVal 0x00000001 - -/*--------------------- CLOCK Configuration ------------------------------- -// -// Main Clock Configuration -// CPU clock divider -// <0=> fCPU = fSYS -// <1=> fCPU = fSYS / 2 -// Peripheral Bus clock divider -// <0=> fPB = fCPU -// <1=> fPB = fCPU / 2 -// CCU Bus clock divider -// <0=> fCCU = fCPU -// <1=> fCCU = fCPU / 2 -// -// -// -*/ - -#define SCU_CLOCK_SETUP 1 -#define SCU_CPUCLKCR_DIV 0x00000000 -#define SCU_PBCLKCR_DIV 0x00000000 -#define SCU_CCUCLKCR_DIV 0x00000000 -/* not avalible in config wizzard*/ -/* -* mandatory clock parameters ************************************************** -* -* source for clock generation -* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) -* -**************************************************************************************/ -// Selection of imput lock for PLL -/*************************************************************************************/ -#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC - -/*************************************************************************************/ -// Standby clock selection for Backup clock source trimming -/*************************************************************************************/ -#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP -//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI - -/*************************************************************************************/ -// Global clock parameters -/*************************************************************************************/ -#define CLOCK_FSYS 120000000 -#define CLOCK_CRYSTAL_FREQUENCY 12000000 -#define CLOCK_BACK_UP 24000000 - -/*************************************************************************************/ -/* OSC_HP setup parameters */ -/*************************************************************************************/ -#define SCU_OSC_HP_MODE 0xF0 -#define SCU_OSCHPWDGDIV 2 - -/*************************************************************************************/ -/* MAIN PLL setup parameters */ -/*************************************************************************************/ -//Divider settings for external crystal @ 12 MHz -/*************************************************************************************/ -#define SCU_PLL_K1DIV 1 -#define SCU_PLL_K2DIV 3 -#define SCU_PLL_PDIV 1 -#define SCU_PLL_NDIV 79 - -/*************************************************************************************/ -//Divider settings for use of backup clock source trimmed -/*************************************************************************************/ -//#define SCU_PLL_K1DIV 1 -//#define SCU_PLL_K2DIV 3 -//#define SCU_PLL_PDIV 3 -//#define SCU_PLL_NDIV 79 -/*************************************************************************************/ - -/*--------------------- USB CLOCK Configuration --------------------------- -// -// USB Clock Configuration -// -// -// -*/ - -#define SCU_USB_CLOCK_SETUP 0 -/* not avalible in config wizzard*/ -#define SCU_USBPLL_PDIV 0 -#define SCU_USBPLL_NDIV 31 -#define SCU_USBDIV 3 - -/*--------------------- Flash Wait State Configuration ------------------------------- -// -// Flash Wait State Configuration -// Flash Wait State -// <0=> 3 WS -// <1=> 4 WS -// <2=> 5 WS -// <3=> 6 WS -// -// -*/ - -#define PMU_FLASH 1 -#define PMU_FLASH_WS 0x00000000 - - -/*--------------------- CLOCKOUT Configuration ------------------------------- -// -// Clock OUT Configuration -// Clockout Source Selection -// <0=> System Clock -// <2=> Divided value of USB PLL output -// <3=> Divided value of PLL Clock -// Clockout divider <1-10><#-1> -// Clockout Pin Selection -// <0=> P1.15 -// <1=> P0.8 -// -// -// -// -*/ - -#define SCU_CLOCKOUT_SETUP 0 -#define SCU_CLOCKOUT_SOURCE 0x00000003 -#define SCU_CLOCKOUT_DIV 0x00000009 -#define SCU_CLOCKOUT_PIN 0x00000001 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -#if SCU_CLOCK_SETUP -uint32_t SystemCoreClock = CLOCK_FSYS; -#else -uint32_t SystemCoreClock = CLOCK_BACK_UP; -#endif - -/*---------------------------------------------------------------------------- - static functions declarations - *----------------------------------------------------------------------------*/ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void); -#endif - -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void); -#endif - - -/** - * @brief Setup the microcontroller system. - * Initialize the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ -int temp; - -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) -SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ -#endif - -/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ -SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); - -/* Setup the WDT */ -#if WDT_SETUP - -WDT->CTR &= ~WDTENB_nVal; - -#endif - -/* Setup the Flash Wait State */ -#if PMU_FLASH -temp = FLASH0->FCON; -temp &= ~FLASH_FCON_WSPFLASH_Msk; -temp |= PMU_FLASH_WS+3; -FLASH0->FCON = temp; -#endif - - -/* Setup the clockout */ -#if SCU_CLOCKOUT_SETUP - -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; -/*set PLL div for clkout */ -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; - -if (SCU_CLOCKOUT_PIN) { - PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ - PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); - //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ - } -else { - PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ - //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ - } - -#endif - - -/* Setup the System clock */ -#if SCU_CLOCK_SETUP -SystemClockSetup(); -#endif - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ - - -/* Setup the USB PL */ -#if SCU_USB_CLOCK_SETUP -USBClockSetup(); -#endif - - - -} - - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ -unsigned int PDIV; -unsigned int NDIV; -unsigned int K2DIV; -unsigned int long VCO; - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -if (SCU_CLK->SYSCLKCR == 0x00010000) -{ - if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ - /* check if PLL is locked */ - /* read back divider settings */ - PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; - NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; - K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; - - if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ - /* the selected clock is the Backup clock fofi */ - VCO = (CLOCK_BACK_UP/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - - } - else - { - /* the selected clock is the PLL external oscillator */ - VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - } - - - } -} -else -{ -SystemCoreClock = CLOCK_BACK_UP; -} - - -} - - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void) -{ -int temp; -unsigned int long VCO; -int stepping_K2DIV; - -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - -/* check if PLL is switched on */ -if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ -/* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - -} - -/* Enable OSC_HP if not already on*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) - { - /********************************************************************************************************************/ - /* Use external crystal for PLL clock input */ - /********************************************************************************************************************/ - - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* select external OSC as PLL input */ - SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) - { - /********************************************************************************************************************/ - /* Use factory trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) - { - /********************************************************************************************************************/ - /* Use automatic trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* check for HIB Domain enabled */ - if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) - SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ - - /* check for HIB Domain is not in reset state */ - if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) - SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ - - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) - { - /****************************************************************************************************************/ - /* Use fOSI as source of the standby clock */ - /****************************************************************************************************************/ - SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - } - else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) - { - /****************************************************************************************************************/ - /* Use fULP as source of the standby clock */ - /****************************************************************************************************************/ - /*check OSCUL if running correct*/ - if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) - { - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); - - SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ - /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ - /* select OSCUL clock for RTC*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*enable OSCULP WDG Alarm Enable*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*wait now for clock is stable */ - do - { - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - for(temp=0;temp<=0xFFFF;temp++); - } - while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); - - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - } - // now OSCULP is running and can be used - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - } - } - - /********************************************************************************************************************/ - /* Setup and look the main PLL */ - /********************************************************************************************************************/ - -if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ - /* Systen is still running from internal clock */ - /* select FOFI as system clock */ - if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ - - - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/24000000)-1; - /* Go to bypass the Main PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; - /* disconnect OSC_HP to PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - /* we may have to set OSCDISCDIS */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - /* connect OSC_HP to PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; - /* wait for PLL Lock */ - /* setup time out loop */ - /* Timeout for wait loo ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - - if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) - { - /* Go back to the Main PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; - } - else return(0); - - - /********************************************************* - here we need to setup the system clock divider - *********************************************************/ - - SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; - SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; - SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; - - - /* Switch system clock to PLL */ - SCU_CLK->SYSCLKCR |= 0x00010000; - - /* we may have to reset OSCDISCDIS */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /*********************************************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 60MHz - *********************************************************/ - if (CLOCK_FSYS > 60000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/60000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 90MHz - *********************************************************/ - if (CLOCK_FSYS > 90000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/90000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - } - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void) -{ -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - - /* check if PLL is switched on */ -if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); -} - -/* check and if not already running enable OSC_HP */ - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - /* check if Main PLL is switched on for OSC WD*/ - if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - } - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - - -/* Setup USB PLL */ - /* Go to bypass the Main PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; - /* disconnect OSC_FI to PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); - /* Setup USBDIV settings USB clock */ - SCU_CLK->USBCLKCR = SCU_USBDIV; - /* we may have to set OSCDISCDIS */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; - /* connect OSC_FI to PLL */ - SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; - /* wait for PLL Lock */ - while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); - - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.h deleted file mode 100644 index 73eb6d590..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR/system/system_XMC4500.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************//** - * @file system_XMC4500.h - * @brief Header file for the XMC4500-Series systeminit - * - * @version V1.6 - * @date 23. October 2012 - * - * @note - * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. - - * - * @par - * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. - * This file can be freely distributed within development tools that are supporting such microcontrollers. - - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - * - ******************************************************************************/ - - -#ifndef __SYSTEM_XMC4500_H -#define __SYSTEM_XMC4500_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -extern void SystemInit (void); - - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/* this weak function enables DAVE3 clock App usage */ -extern uint32_t AllowPLLInitByStartup(void); - - -/* clock definitions, do not modify! */ -#define SCU_CLOCK_CRYSTAL 1 - - - -/* - * mandatory clock parameters ************************************************** - */ -/* source for clock generation - * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) - * mandatory for old system_xmc4500.c files - please do not remove!!! - **************************************************************************************/ - -#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL -#define CLOCK_OSC_HP 24000000 -#define CLOCK_BACK_UP 24000000 -#define CLOCK_CRYSTAL_FREQUENCY 12000000 -#define SYSTEM_FREQUENCY 120000000 - -/* OSC_HP setup parameters */ -#define OSC_HP_MODE 0 -#define OSCHPWDGDIV 2 - -/* MAIN PLL setup parameters */ - - -#define PLL_K1DIV 1 -#define PLL_K2DIV 3 -#define PLL_PDIV 1 -#define PLL_NDIV 79 - - - -#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz -#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz -#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz - - - -#define USBPLL_PDIV 1 -#define USBPLL_NDIV 15 - - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_Flash.ini b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_Flash.ini deleted file mode 100644 index 307511920..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_Flash.ini +++ /dev/null @@ -1,2 +0,0 @@ -_WDWORD(0xE0002008, 0x00000000); // Clear FPB 0 (FP_COMP0) - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM TraceETM.ini b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM TraceETM.ini deleted file mode 100644 index 4c624d397..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM TraceETM.ini +++ /dev/null @@ -1,36 +0,0 @@ -/*---------------------------------------------------------------------------- - * Name: Dbg_RAM.ini - * Purpose: RAM Debug Initialization File - * Note(s): - *---------------------------------------------------------------------------- - * This file is part of the uVision/ARM development tools. - * This software may only be used under the terms of a valid, current, - * end user licence from KEIL for a compatible version of KEIL software - * development tools. Nothing else gives you the right to use this software. - * - * This software is supplied "AS IS" without warranties of any kind. - * - * Copyright (c) 2008-2011 Keil - An ARM Company. All rights reserved. - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Setup() configure PC & SP for RAM Debug - *----------------------------------------------------------------------------*/ -FUNC void Setup (void) { - SP = _RDWORD(0x10000000); // Setup Stack Pointer - PC = _RDWORD(0x10000004); // Setup Program Counter - _WDWORD(0xE000ED08, 0x10000000); // Setup Vector Table Offset Register -} - -_WDWORD(0x5000413C, 0x001F3700); // Enable RAM - -_WDWORD(0x48028674, 0x00001405); // Enable ETM Pins P6 - -_WDWORD(0x48028274, 0x00401405); // Enable ETM Pins P2 - -LOAD %L INCREMENTAL // load the application - -Setup(); // Setup for Running - -/*g, main*/ - \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM.ini b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM.ini deleted file mode 100644 index 832a6eb0c..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Dbg_RAM.ini +++ /dev/null @@ -1,32 +0,0 @@ -/*---------------------------------------------------------------------------- - * Name: Dbg_RAM.ini - * Purpose: RAM Debug Initialization File - * Note(s): - *---------------------------------------------------------------------------- - * This file is part of the uVision/ARM development tools. - * This software may only be used under the terms of a valid, current, - * end user licence from KEIL for a compatible version of KEIL software - * development tools. Nothing else gives you the right to use this software. - * - * This software is supplied "AS IS" without warranties of any kind. - * - * Copyright (c) 2008-2011 Keil - An ARM Company. All rights reserved. - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Setup() configure PC & SP for RAM Debug - *----------------------------------------------------------------------------*/ -FUNC void Setup (void) { - SP = _RDWORD(0x10000000); // Setup Stack Pointer - PC = _RDWORD(0x10000004); // Setup Program Counter - _WDWORD(0xE000ED08, 0x10000000); // Setup Vector Table Offset Register -} - -_WDWORD(0x5000413C, 0x001F3700); // Enable RAM - -LOAD %L INCREMENTAL // load the application - -Setup(); // Setup for Running - -/*g, main*/ - \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h deleted file mode 100644 index e1e30d39c..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/FreeRTOSConfig.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html. - *----------------------------------------------------------*/ - -#include -extern uint32_t SystemCoreClock; - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 0 -#define configCPU_CLOCK_HZ ( SystemCoreClock ) -#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 22800 ) ) -#define configMAX_TASK_NAME_LEN ( 10 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configQUEUE_REGISTRY_SIZE 8 -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configGENERATE_RUN_TIME_STATS 0 - -/* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) - -/* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( 2 ) -#define configTIMER_QUEUE_LENGTH 5 -#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 - -/* Cortex-M specific definitions. */ -#ifdef __NVIC_PRIO_BITS - /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ - #define configPRIO_BITS __NVIC_PRIO_BITS -#else - #define configPRIO_BITS 6 /* 63 priority levels */ -#endif - -/* The lowest interrupt priority that can be used in a call to a "set priority" -function. */ -#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x3f - -/* The highest interrupt priority that can be used by any interrupt service -routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL -INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER -PRIORITY THAN THIS! (higher priorities are lower numeric values. */ -#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5 - -/* Interrupt priorities used by the kernel port layer itself. These are generic -to all Cortex-M ports, and do not rely on any particular library functions. */ -#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) -/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! -See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ -#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) - -/* Normal assert() semantics without relying on the provision of an assert.h -header file. */ -#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } - -/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS -standard names. */ -#define vPortSVCHandler SVC_Handler -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler - - -/* Demo application specific settings. */ -#if defined( PART_XMC4500 ) - /* Hardware includes. */ - #include "XMC4500.h" - #include "System_XMC4500.h" - - /* Configure pin P3.9 for the LED. */ - #define configCONFIGURE_LED() ( PORT3->IOCR8 = 0x00008000 ) - /* To toggle the single LED */ - #define configTOGGLE_LED() ( PORT3->OMR = 0x02000200 ) -#elif defined( PART_XMC4400 ) - /* Hardware includes. */ - #include "XMC4400.h" - #include "System_XMC4200.h" - - /* Configure pin P5.2 for the LED. */ - #define configCONFIGURE_LED() ( PORT5->IOCR0 = 0x00800000 ) - /* To toggle the single LED */ - #define configTOGGLE_LED() ( PORT5->OMR = 0x00040004 ) -#elif defined( PART_XMC4200 ) - /* Hardware includes. */ - #include "XMC4200.h" - #include "System_XMC4200.h" - - /* Configure pin P2.1 for the LED. */ - #define configCONFIGURE_LED() PORT2->IOCR0 = 0x00008000; PORT2->HWSEL &= ~0x0000000cUL - /* To toggle the single LED */ - #define configTOGGLE_LED() ( PORT2->OMR = 0x00020002 ) -#else - #error Part number not specified in project options -#endif - - -#endif /* FREERTOS_CONFIG_H */ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt deleted file mode 100644 index c03a8bbea..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RTOSDemo.uvopt +++ /dev/null @@ -1,1047 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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- - heap_4.c - 1 - ..\..\Source\portable\MemMang\heap_4.c - - - - - Common_Demo_Source - - - semtest.c - 1 - ..\Common\Minimal\semtest.c - - - sp_flop.c - 1 - ..\Common\Minimal\sp_flop.c - - - blocktim.c - 1 - ..\Common\Minimal\blocktim.c - - - countsem.c - 1 - ..\Common\Minimal\countsem.c - - - dynamic.c - 1 - ..\Common\Minimal\dynamic.c - - - GenQTest.c - 1 - ..\Common\Minimal\GenQTest.c - - - recmutex.c - 1 - ..\Common\Minimal\recmutex.c - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c deleted file mode 100644 index 2c42e38f1..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/RegTest.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - - -__asm vRegTest1Task( void ) -{ - PRESERVE8 - IMPORT ulRegTest1LoopCounter - - /* Fill the core registers with known values. */ - mov r0, #100 - mov r1, #101 - mov r2, #102 - mov r3, #103 - mov r4, #104 - mov r5, #105 - mov r6, #106 - mov r7, #107 - mov r8, #108 - mov r9, #109 - mov r10, #110 - mov r11, #111 - mov r12, #112 - - /* Fill the VFP registers with known values. */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - -reg1_loop - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d1 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d2 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d3 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - vmov r0, r1, d4 - cmp r0, #108 - bne reg1_error_loopf - cmp r1, #109 - bne reg1_error_loopf - vmov r0, r1, d5 - cmp r0, #110 - bne reg1_error_loopf - cmp r1, #111 - bne reg1_error_loopf - vmov r0, r1, d6 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d7 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d8 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d9 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - vmov r0, r1, d10 - cmp r0, #108 - bne reg1_error_loopf - cmp r1, #109 - bne reg1_error_loopf - vmov r0, r1, d11 - cmp r0, #110 - bne reg1_error_loopf - cmp r1, #111 - bne reg1_error_loopf - vmov r0, r1, d12 - cmp r0, #100 - bne reg1_error_loopf - cmp r1, #101 - bne reg1_error_loopf - vmov r0, r1, d13 - cmp r0, #102 - bne reg1_error_loopf - cmp r1, #103 - bne reg1_error_loopf - vmov r0, r1, d14 - cmp r0, #104 - bne reg1_error_loopf - cmp r1, #105 - bne reg1_error_loopf - vmov r0, r1, d15 - cmp r0, #106 - bne reg1_error_loopf - cmp r1, #107 - bne reg1_error_loopf - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg1_loopf_pass - -reg1_error_loopf - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg1_error_loopf - -reg1_loopf_pass - - cmp r0, #100 - bne reg1_error_loop - cmp r1, #101 - bne reg1_error_loop - cmp r2, #102 - bne reg1_error_loop - cmp r3, #103 - bne reg1_error_loop - cmp r4, #104 - bne reg1_error_loop - cmp r5, #105 - bne reg1_error_loop - cmp r6, #106 - bne reg1_error_loop - cmp r7, #107 - bne reg1_error_loop - cmp r8, #108 - bne reg1_error_loop - cmp r9, #109 - bne reg1_error_loop - cmp r10, #110 - bne reg1_error_loop - cmp r11, #111 - bne reg1_error_loop - cmp r12, #112 - bne reg1_error_loop - - /* Everything passed, increment the loop counter. */ - push { r0-r1 } - ldr r0, =ulRegTest1LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r0-r1 } - - /* Start again. */ - b reg1_loop - -reg1_error_loop - /* If this line is hit then there was an error in a core register value. - The loop ensures the loop counter stops incrementing. */ - b reg1_error_loop - nop -} -/*-----------------------------------------------------------*/ - -__asm vRegTest2Task( void ) -{ - PRESERVE8 - IMPORT ulRegTest2LoopCounter - - /* Set all the core registers to known values. */ - mov r0, #-1 - mov r1, #1 - mov r2, #2 - mov r3, #3 - mov r4, #4 - mov r5, #5 - mov r6, #6 - mov r7, #7 - mov r8, #8 - mov r9, #9 - mov r10, #10 - mov r11, #11 - mov r12, #12 - - /* Set all the VFP to known values. */ - vmov d0, r0, r1 - vmov d1, r2, r3 - vmov d2, r4, r5 - vmov d3, r6, r7 - vmov d4, r8, r9 - vmov d5, r10, r11 - vmov d6, r0, r1 - vmov d7, r2, r3 - vmov d8, r4, r5 - vmov d9, r6, r7 - vmov d10, r8, r9 - vmov d11, r10, r11 - vmov d12, r0, r1 - vmov d13, r2, r3 - vmov d14, r4, r5 - vmov d15, r6, r7 - -reg2_loop - - /* Check all the VFP registers still contain the values set above. - First save registers that are clobbered by the test. */ - push { r0-r1 } - - vmov r0, r1, d0 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d1 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d2 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d3 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - vmov r0, r1, d4 - cmp r0, #8 - bne reg2_error_loopf - cmp r1, #9 - bne reg2_error_loopf - vmov r0, r1, d5 - cmp r0, #10 - bne reg2_error_loopf - cmp r1, #11 - bne reg2_error_loopf - vmov r0, r1, d6 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d7 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d8 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d9 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - vmov r0, r1, d10 - cmp r0, #8 - bne reg2_error_loopf - cmp r1, #9 - bne reg2_error_loopf - vmov r0, r1, d11 - cmp r0, #10 - bne reg2_error_loopf - cmp r1, #11 - bne reg2_error_loopf - vmov r0, r1, d12 - cmp r0, #-1 - bne reg2_error_loopf - cmp r1, #1 - bne reg2_error_loopf - vmov r0, r1, d13 - cmp r0, #2 - bne reg2_error_loopf - cmp r1, #3 - bne reg2_error_loopf - vmov r0, r1, d14 - cmp r0, #4 - bne reg2_error_loopf - cmp r1, #5 - bne reg2_error_loopf - vmov r0, r1, d15 - cmp r0, #6 - bne reg2_error_loopf - cmp r1, #7 - bne reg2_error_loopf - - /* Restore the registers that were clobbered by the test. */ - pop {r0-r1} - - /* VFP register test passed. Jump to the core register test. */ - b reg2_loopf_pass - -reg2_error_loopf - /* If this line is hit then a VFP register value was found to be - incorrect. */ - b reg2_error_loopf - -reg2_loopf_pass - - cmp r0, #-1 - bne reg2_error_loop - cmp r1, #1 - bne reg2_error_loop - cmp r2, #2 - bne reg2_error_loop - cmp r3, #3 - bne reg2_error_loop - cmp r4, #4 - bne reg2_error_loop - cmp r5, #5 - bne reg2_error_loop - cmp r6, #6 - bne reg2_error_loop - cmp r7, #7 - bne reg2_error_loop - cmp r8, #8 - bne reg2_error_loop - cmp r9, #9 - bne reg2_error_loop - cmp r10, #10 - bne reg2_error_loop - cmp r11, #11 - bne reg2_error_loop - cmp r12, #12 - bne reg2_error_loop - - /* Increment the loop counter to indicate this test is still functioning - correctly. */ - push { r0-r1 } - ldr r0, =ulRegTest2LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - - /* Yield to increase test coverage. */ - movs r0, #0x01 - ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ - lsl r0, r0, #28 /* Shift to PendSV bit */ - str r0, [r1] - dsb - - pop { r0-r1 } - - /* Start again. */ - b reg2_loop - -reg2_error_loop - /* If this line is hit then there was an error in a core register value. - This loop ensures the loop counter variable stops incrementing. */ - b reg2_error_loop - nop -} -/*-----------------------------------------------------------*/ - -__asm vRegTestClearFlopRegistersToParameterValue( unsigned long ulValue ) -{ - PRESERVE8 - - /* Clobber the auto saved registers. */ - vmov d0, r0, r0 - vmov d1, r0, r0 - vmov d2, r0, r0 - vmov d3, r0, r0 - vmov d4, r0, r0 - vmov d5, r0, r0 - vmov d6, r0, r0 - vmov d7, r0, r0 - bx lr -} -/*-----------------------------------------------------------*/ - -__asm ulRegTestCheckFlopRegistersContainParameterValue( unsigned long ulValue ) -{ - PRESERVE8 - - vmov r1, s0 - cmp r0, r1 - bne return_error - vmov r1, s1 - cmp r0, r1 - bne return_error - vmov r1, s2 - cmp r0, r1 - bne return_error - vmov r1, s3 - cmp r0, r1 - bne return_error - vmov r1, s4 - cmp r0, r1 - bne return_error - vmov r1, s5 - cmp r0, r1 - bne return_error - vmov r1, s6 - cmp r0, r1 - bne return_error - vmov r1, s7 - cmp r0, r1 - bne return_error - vmov r1, s8 - cmp r0, r1 - bne return_error - vmov r1, s9 - cmp r0, r1 - bne return_error - vmov r1, s10 - cmp r0, r1 - bne return_error - vmov r1, s11 - cmp r0, r1 - bne return_error - vmov r1, s12 - cmp r0, r1 - bne return_error - vmov r1, s13 - cmp r0, r1 - bne return_error - vmov r1, s14 - cmp r0, r1 - bne return_error - vmov r1, s15 - cmp r0, r1 - bne return_error - -return_pass - mov r0, #1 - bx lr - -return_error - mov r0, #0 - bx lr -} - - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c deleted file mode 100644 index 06fd3aca6..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.c +++ /dev/null @@ -1,705 +0,0 @@ -/**************************************************************************//** - * @file system_XMC4500.c - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File - * for the Infineon XMC4500 Device Series - * @version V3.0.1 Alpha - * @date 17. September 2012 - * - * @note - * Copyright (C) 2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include "system_XMC4500.h" -#include - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemCoreClock; - -/* clock definitions, do not modify! */ -#define SCU_CLOCK_CRYSTAL 1 -#define SCU_CLOCK_BACK_UP_FACTORY 2 -#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 - - -#define HIB_CLOCK_FOSI 1 -#define HIB_CLOCK_OSCULP 2 - - - - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - - - -/*--------------------- Watchdog Configuration ------------------------------- -// -// Watchdog Configuration -// Disable Watchdog -// -// -*/ -#define WDT_SETUP 1 -#define WDTENB_nVal 0x00000001 - -/*--------------------- CLOCK Configuration ------------------------------- -// -// Main Clock Configuration -// CPU clock divider -// <0=> fCPU = fSYS -// <1=> fCPU = fSYS / 2 -// Peripheral Bus clock divider -// <0=> fPB = fCPU -// <1=> fPB = fCPU / 2 -// CCU Bus clock divider -// <0=> fCCU = fCPU -// <1=> fCCU = fCPU / 2 -// -// -// -*/ - -#define SCU_CLOCK_SETUP 1 -#define SCU_CPUCLKCR_DIV 0x00000000 -#define SCU_PBCLKCR_DIV 0x00000000 -#define SCU_CCUCLKCR_DIV 0x00000000 -/* not avalible in config wizzard*/ -/* -* mandatory clock parameters ************************************************** -* -* source for clock generation -* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) -* -**************************************************************************************/ -// Selection of imput lock for PLL -/*************************************************************************************/ -#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC - -/*************************************************************************************/ -// Standby clock selection for Backup clock source trimming -/*************************************************************************************/ -#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP -//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI - -/*************************************************************************************/ -// Global clock parameters -/*************************************************************************************/ -#define CLOCK_FSYS 120000000 -#define CLOCK_CRYSTAL_FREQUENCY 12000000 -#define CLOCK_BACK_UP 24000000 - -/*************************************************************************************/ -/* OSC_HP setup parameters */ -/*************************************************************************************/ -#define SCU_OSC_HP_MODE 0xF0 -#define SCU_OSCHPWDGDIV 2 - -/*************************************************************************************/ -/* MAIN PLL setup parameters */ -/*************************************************************************************/ -//Divider settings for external crystal @ 12 MHz -/*************************************************************************************/ -#define SCU_PLL_K1DIV 1 -#define SCU_PLL_K2DIV 3 -#define SCU_PLL_PDIV 1 -#define SCU_PLL_NDIV 79 - -/*************************************************************************************/ -//Divider settings for use of backup clock source trimmed -/*************************************************************************************/ -//#define SCU_PLL_K1DIV 1 -//#define SCU_PLL_K2DIV 3 -//#define SCU_PLL_PDIV 3 -//#define SCU_PLL_NDIV 79 -/*************************************************************************************/ - -/*--------------------- USB CLOCK Configuration --------------------------- -// -// USB Clock Configuration -// -// -// -*/ - -#define SCU_USB_CLOCK_SETUP 0 -/* not avalible in config wizzard*/ -#define SCU_USBPLL_PDIV 0 -#define SCU_USBPLL_NDIV 31 -#define SCU_USBDIV 3 - -/*--------------------- Flash Wait State Configuration ------------------------------- -// -// Flash Wait State Configuration -// Flash Wait State -// <0=> 3 WS -// <1=> 4 WS -// <2=> 5 WS -// <3=> 6 WS -// -// -*/ - -#define PMU_FLASH 1 -#define PMU_FLASH_WS 0x00000000 - - -/*--------------------- CLOCKOUT Configuration ------------------------------- -// -// Clock OUT Configuration -// Clockout Source Selection -// <0=> System Clock -// <2=> Divided value of USB PLL output -// <3=> Divided value of PLL Clock -// Clockout divider <1-10><#-1> -// Clockout Pin Selection -// <0=> P1.15 -// <1=> P0.8 -// -// -// -// -*/ - -#define SCU_CLOCKOUT_SETUP 0 -#define SCU_CLOCKOUT_SOURCE 0x00000003 -#define SCU_CLOCKOUT_DIV 0x00000009 -#define SCU_CLOCKOUT_PIN 0x00000001 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -#if SCU_CLOCK_SETUP -uint32_t SystemCoreClock = CLOCK_FSYS; -#else -uint32_t SystemCoreClock = CLOCK_BACK_UP; -#endif - -/*---------------------------------------------------------------------------- - static functions declarations - *----------------------------------------------------------------------------*/ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void); -#endif - -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void); -#endif - - -/** - * @brief Setup the microcontroller system. - * Initialize the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ -int temp; - -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) -SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ -#endif - -/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ -SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); - -/* Setup the WDT */ -#if WDT_SETUP - -WDT->CTR &= ~WDTENB_nVal; - -#endif - -/* Setup the Flash Wait State */ -#if PMU_FLASH -temp = FLASH0->FCON; -temp &= ~FLASH_FCON_WSPFLASH_Msk; -temp |= PMU_FLASH_WS+3; -FLASH0->FCON = temp; -#endif - - -/* Setup the clockout */ -#if SCU_CLOCKOUT_SETUP - -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; -/*set PLL div for clkout */ -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; - -if (SCU_CLOCKOUT_PIN) { - PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ - PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); - //PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ - } -else { - PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ - //PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ - } - -#endif - - -/* Setup the System clock */ -#if SCU_CLOCK_SETUP -SystemClockSetup(); -#endif - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ - - -/* Setup the USB PL */ -#if SCU_USB_CLOCK_SETUP -USBClockSetup(); -#endif - - - -} - - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ -unsigned int PDIV; -unsigned int NDIV; -unsigned int K2DIV; -unsigned int long VCO; - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -if (SCU_CLK->SYSCLKCR == 0x00010000) -{ - if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ - /* check if PLL is locked */ - /* read back divider settings */ - PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; - NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; - K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; - - if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ - /* the selected clock is the Backup clock fofi */ - VCO = (CLOCK_BACK_UP/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - - } - else - { - /* the selected clock is the PLL external oscillator */ - VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - } - - - } -} -else -{ -SystemCoreClock = CLOCK_BACK_UP; -} - - -} - - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void) -{ -int temp; -unsigned int long VCO; -int stepping_K2DIV; - -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - -/* check if PLL is switched on */ -if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ -/* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - -} - -/* Enable OSC_HP if not already on*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) - { - /********************************************************************************************************************/ - /* Use external crystal for PLL clock input */ - /********************************************************************************************************************/ - - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* select external OSC as PLL input */ - SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) - { - /********************************************************************************************************************/ - /* Use factory trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) - { - /********************************************************************************************************************/ - /* Use automatic trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* check for HIB Domain enabled */ - if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) - SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ - - /* check for HIB Domain is not in reset state */ - if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) - SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ - - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) - { - /****************************************************************************************************************/ - /* Use fOSI as source of the standby clock */ - /****************************************************************************************************************/ - SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - } - else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) - { - /****************************************************************************************************************/ - /* Use fULP as source of the standby clock */ - /****************************************************************************************************************/ - /*check OSCUL if running correct*/ - if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) - { - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); - - SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ - /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ - /* select OSCUL clock for RTC*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*enable OSCULP WDG Alarm Enable*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*wait now for clock is stable */ - do - { - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - for(temp=0;temp<=0xFFFF;temp++); - } - while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); - - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - } - // now OSCULP is running and can be used - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - } - } - - /********************************************************************************************************************/ - /* Setup and look the main PLL */ - /********************************************************************************************************************/ - -if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ - /* Systen is still running from internal clock */ - /* select FOFI as system clock */ - if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ - - - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/24000000)-1; - /* Go to bypass the Main PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; - /* disconnect OSC_HP to PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - /* we may have to set OSCDISCDIS */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - /* connect OSC_HP to PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; - /* wait for PLL Lock */ - /* setup time out loop */ - /* Timeout for wait loo ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - - if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) - { - /* Go back to the Main PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; - } - else return(0); - - - /********************************************************* - here we need to setup the system clock divider - *********************************************************/ - - SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; - SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; - SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; - - - /* Switch system clock to PLL */ - SCU_CLK->SYSCLKCR |= 0x00010000; - - /* we may have to reset OSCDISCDIS */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /*********************************************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 60MHz - *********************************************************/ - if (CLOCK_FSYS > 60000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/60000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 90MHz - *********************************************************/ - if (CLOCK_FSYS > 90000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/90000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - } - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void) -{ -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - - /* check if PLL is switched on */ -if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); -} - -/* check and if not already running enable OSC_HP */ - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - /* check if Main PLL is switched on for OSC WD*/ - if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - } - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - - -/* Setup USB PLL */ - /* Go to bypass the Main PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; - /* disconnect OSC_FI to PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); - /* Setup USBDIV settings USB clock */ - SCU_CLK->USBCLKCR = SCU_USBDIV; - /* we may have to set OSCDISCDIS */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; - /* connect OSC_FI to PLL */ - SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; - /* wait for PLL Lock */ - while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); - - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.h deleted file mode 100644 index 73eb6d590..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/System_XMC4500.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************//** - * @file system_XMC4500.h - * @brief Header file for the XMC4500-Series systeminit - * - * @version V1.6 - * @date 23. October 2012 - * - * @note - * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. - - * - * @par - * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. - * This file can be freely distributed within development tools that are supporting such microcontrollers. - - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - * - ******************************************************************************/ - - -#ifndef __SYSTEM_XMC4500_H -#define __SYSTEM_XMC4500_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -extern void SystemInit (void); - - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/* this weak function enables DAVE3 clock App usage */ -extern uint32_t AllowPLLInitByStartup(void); - - -/* clock definitions, do not modify! */ -#define SCU_CLOCK_CRYSTAL 1 - - - -/* - * mandatory clock parameters ************************************************** - */ -/* source for clock generation - * range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) - * mandatory for old system_xmc4500.c files - please do not remove!!! - **************************************************************************************/ - -#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL -#define CLOCK_OSC_HP 24000000 -#define CLOCK_BACK_UP 24000000 -#define CLOCK_CRYSTAL_FREQUENCY 12000000 -#define SYSTEM_FREQUENCY 120000000 - -/* OSC_HP setup parameters */ -#define OSC_HP_MODE 0 -#define OSCHPWDGDIV 2 - -/* MAIN PLL setup parameters */ - - -#define PLL_K1DIV 1 -#define PLL_K2DIV 3 -#define PLL_PDIV 1 -#define PLL_NDIV 79 - - - -#define PLL_K2DIV_STEP_1 19 //PLL output is 24Mhz -#define PLL_K2DIV_STEP_2 7 //PLL output to 60Mhz -#define PLL_K2DIV_STEP_3 4 //PLL output to 96Mhz - - - -#define USBPLL_PDIV 1 -#define USBPLL_NDIV 15 - - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Template.sct b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Template.sct deleted file mode 100644 index 785967479..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/Template.sct +++ /dev/null @@ -1,15 +0,0 @@ -; ************************************************************* -; *** Scatter-Loading Description File generated by uVision *** -; ************************************************************* - -LR_IROM1 0x0C000000 0x00100000 { ; load region size_region - ER_IROM1 0x0C000000 0x00100000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x10000000 0x00010000 { ; RW data - .ANY (+RW +ZI) - } -} - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c deleted file mode 100644 index 768a44d96..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * This project provides two demo applications. A simple blinky style project, - * and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to - * select between the two. The simply blinky demo is implemented and described - * in main_blinky.c. The more comprehensive test and demo application is - * implemented and described in main_full.c. - * - * This file implements the code that is not demo specific, including the - * hardware setup and FreeRTOS hook functions. - * - * - * Additional code: - * - * This demo does not contain a non-kernel interrupt service routine that - * can be used as an example for application writers to use as a reference. - * Therefore, the framework of a dummy (not installed) handler is provided - * in this file. The dummy function is called Dummy_IRQHandler(). Please - * ensure to read the comments in the function itself, but more importantly, - * the notes on the function contained on the documentation page for this demo - * that is found on the FreeRTOS.org web site. - */ - -/* Standard includes. */ -#include - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, -or 0 to run the more comprehensive test and demo application. */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 - -/*-----------------------------------------------------------*/ - -/* - * Set up the hardware ready to run this demo. - */ -static void prvSetupHardware( void ); - -/* - * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. - * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. - */ -extern void main_blinky( void ); -extern void main_full( void ); - -/*-----------------------------------------------------------*/ - -int main( void ) -{ - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; -} -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - configCONFIGURE_LED(); - - /* Ensure all priority bits are assigned as preemption priority bits. */ - NVIC_SetPriorityGrouping( 0 ); -} -/*-----------------------------------------------------------*/ - -void vApplicationMallocFailedHook( void ) -{ - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); -} -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ -} -/*-----------------------------------------------------------*/ - -void vApplicationStackOverflowHook( xTaskHandle pxTask, signed char *pcTaskName ) -{ - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); -} -/*-----------------------------------------------------------*/ - -void vApplicationTickHook( void ) -{ - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ -} -/*-----------------------------------------------------------*/ - -#ifdef JUST_AN_EXAMPLE_ISR - -void Dummy_IRQHandler(void) -{ -long lHigherPriorityTaskWoken = pdFALSE; - - /* Clear the interrupt if necessary. */ - Dummy_ClearITPendingBit(); - - /* This interrupt does nothing more than demonstrate how to synchronise a - task with an interrupt. A semaphore is used for this purpose. Note - lHigherPriorityTaskWoken is initialised to zero. */ - xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken ); - - /* If there was a task that was blocked on the semaphore, and giving the - semaphore caused the task to unblock, and the unblocked task has a priority - higher than the current Running state task (the task that this interrupt - interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE - internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the - portEND_SWITCHING_ISR() macro will result in a context switch being pended to - ensure this interrupt returns directly to the unblocked, higher priority, - task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */ - portEND_SWITCHING_ISR( lHigherPriorityTaskWoken ); -} - -#endif /* JUST_AN_EXAMPLE_ISR */ diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_blinky.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_blinky.c deleted file mode 100644 index 83d8398d8..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_blinky.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky style - * project, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select - * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY - * in main.c. This file implements the simply blinky style version. - * - * NOTE 2: This file only contains the source code that is specific to the - * basic demo. Generic functions, such FreeRTOS hook functions, and functions - * required to configure the hardware, are defined in main.c. - ****************************************************************************** - * - * main_blinky() creates one queue, and two tasks. It then starts the - * scheduler. - * - * The Queue Send Task: - * The queue send task is implemented by the prvQueueSendTask() function in - * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly - * block for 200 milliseconds, before sending the value 100 to the queue that - * was created within main_blinky(). Once the value is sent, the task loops - * back around to block for another 200 milliseconds. - * - * The Queue Receive Task: - * The queue receive task is implemented by the prvQueueReceiveTask() function - * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly - * blocks on attempts to read data from the queue that was created within - * main_blinky(). When data is received, the task checks the value of the - * data, and if the value equals the expected 100, toggles the LED. The 'block - * time' parameter passed to the queue receive function specifies that the - * task should be held in the Blocked state indefinitely to wait for data to - * be available on the queue. The queue receive task will only leave the - * Blocked state when the queue send task writes to the queue. As the queue - * send task writes to the queue every 200 milliseconds, the queue receive - * task leaves the Blocked state every 200 milliseconds, and therefore toggles - * the LED every 200 milliseconds. - */ - -/* Standard includes. */ -#include - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "semphr.h" - -/* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_RATE_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS ) - -/* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) - -/* Values passed to the two tasks just to check the task parameter -functionality. */ -#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) -#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) - -/*-----------------------------------------------------------*/ - -/* - * The tasks as described in the comments at the top of this file. - */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); - -/* - * Called by main() to create the simply blinky style application if - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. - */ -void main_blinky( void ); - -/*-----------------------------------------------------------*/ - -/* The queue used by both tasks. */ -static xQueueHandle xQueue = NULL; - -/*-----------------------------------------------------------*/ - -void main_blinky( void ) -{ - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvQueueSendTask( void *pvParameters ) -{ -portTickType xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } -} -/*-----------------------------------------------------------*/ - -static void prvQueueReceiveTask( void *pvParameters ) -{ -unsigned long ulReceivedValue; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - configTOGGLE_LED(); - ulReceivedValue = 0U; - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c deleted file mode 100644 index a9cda91ad..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/main_full.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky style - * project, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select - * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY - * in main.c. This file implements the comprehensive test and demo version. - * - * NOTE 2: This file only contains the source code that is specific to the - * full demo. Generic functions, such FreeRTOS hook functions, and functions - * required to configure the hardware, are defined in main.c. - ****************************************************************************** - * - * main_full() creates all the demo application tasks and a software timer, then - * starts the scheduler. The web documentation provides more details of the - * standard demo application tasks, which provide no particular functionality, - * but do provide a good example of how to use the FreeRTOS API. - * - * In addition to the standard demo tasks, the following tasks and tests are - * defined and/or created within this file: - * - * "Reg test" tasks - These fill both the core and floating point registers with - * known values, then check that each register maintains its expected value for - * the lifetime of the task. Each task uses a different set of values. The reg - * test tasks execute with a very low priority, so get preempted very - * frequently. A register containing an unexpected value is indicative of an - * error in the context switching mechanism. - * - * "Check" timer - The check software timer period is initially set to three - * seconds. The callback function associated with the check software timer - * checks that all the standard demo tasks, and the register check tasks, are - * not only still executing, but are executing without reporting any errors. If - * the check software timer discovers that a task has either stalled, or - * reported an error, then it changes its own execution period from the initial - * three seconds, to just 200ms. The check software timer callback function - * also toggles the single LED each time it is called. This provides a visual - * indication of the system status: If the LED toggles every three seconds, - * then no issues have been discovered. If the LED toggles every 200ms, then - * an issue has been discovered with at least one task. - */ - -/* Standard includes. */ -#include - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "semphr.h" - -/* Standard demo application includes. */ -#include "flop.h" -#include "semtest.h" -#include "dynamic.h" -#include "blocktim.h" -#include "countsem.h" -#include "GenQTest.h" -#include "recmutex.h" - -/* Priorities for the demo application tasks. */ -#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) -#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) -#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) -#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) - -/* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) - -/* The period after which the check timer will expire, in ms, provided no errors -have been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_RATE_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS ) - -/* The period at which the check timer will expire, in ms, if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_RATE_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_RATE_MS ) - -/*-----------------------------------------------------------*/ - -/* - * The check timer callback function, as described at the top of this file. - */ -static void prvCheckTimerCallback( xTimerHandle xTimer ); - -/* - * Register check tasks, and the tasks used to write over and check the contents - * of the FPU registers, as described at the top of this file. The nature of - * these files necessitates that they are written in an assembly file. - */ -extern void vRegTest1Task( void *pvParameters ); -extern void vRegTest2Task( void *pvParameters ); - -/*-----------------------------------------------------------*/ - -/* The following two variables are used to communicate the status of the -register check tasks to the check software timer. If the variables keep -incrementing, then the register check tasks has not discovered any errors. If -a variable stops incrementing, then an error has been found. */ -volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; - -/*-----------------------------------------------------------*/ - -void main_full( void ) -{ -xTimerHandle xCheckTimer = NULL; - - /* Start all the other standard demo/test tasks. The have not particular - functionality, but do demonstrate how to use the FreeRTOS API and test the - kernel port. */ - vStartDynamicPriorityTasks(); - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartGenericQueueTasks( tskIDLE_PRIORITY ); - vStartRecursiveMutexTasks(); - vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); - vStartMathTasks( mainFLOP_TASK_PRIORITY ); - - /* Create the register check tasks, as described at the top of this - file */ - xTaskCreate( vRegTest1Task, ( signed char * ) "Reg1", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - xTaskCreate( vRegTest2Task, ( signed char * ) "Reg2", configMINIMAL_STACK_SIZE, ( void * ) NULL, tskIDLE_PRIORITY, NULL ); - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - if( xCheckTimer != NULL ) - { - xTimerStart( xCheckTimer, mainDONT_BLOCK ); - } - - /* Start the scheduler. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following line - will never be reached. If the following line does execute, then there was - insufficient FreeRTOS heap memory available for the idle and/or timer tasks - to be created. See the memory management section on the FreeRTOS web site - for more details. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvCheckTimerCallback( xTimerHandle xTimer ) -{ -static long lChangedTimerPeriodAlready = pdFALSE; -static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -unsigned long ulErrorFound = pdFALSE; - - /* Check all the demo tasks (other than the flash tasks) to ensure - that they are all still running, and that none have detected an error. */ - - if( xAreMathsTaskStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - if( xAreSemaphoreTasksStillRunning() != pdTRUE ) - { - ulErrorFound = pdTRUE; - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound = pdTRUE; - } - ulLastRegTest2Value = ulRegTest2LoopCounter; - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. */ - configTOGGLE_LED(); - - /* Have any errors been latch in ulErrorFound? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( ulErrorFound != pdFALSE ) - { - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block. */ - xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4200.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4200.s deleted file mode 100644 index a246e4302..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4200.s +++ /dev/null @@ -1,455 +0,0 @@ -;*****************************************************************************/ -; * @file startup_XMC4200.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Infineon XMC4200 Device Series -; * @version V1.00 -; * @date 05. February 2013 -; * -; * @note -; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -;/* ********************* Version History *********************************** */ -;/* *************************************************************************** -; V0.1 , September 2012, First version -; V1.0 , February 2013, FIX for CPU prefetch bug implemented -;**************************************************************************** */ - - -;* <<< Use Configuration Wizard in Context Menu >>> - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ -;/* -; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001). -; * A veneer defined below will first -; * be executed which in turn branches to the final exception handler. -; * -; * In addition to defining the veneers, the vector table must for these buggy -; * devices contain the veneers. -; */ - -;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define -;or use define below - GBLL WORKAROUND_PMU_CM001 - -;/* A macro to setup a vector table entry based on STEP ID */ - IF :DEF:WORKAROUND_PMU_CM001 - MACRO - ExcpVector $Handler - DCD $Handler._Veneer - MEND - ELSE - MACRO - ExcpVector $Handler - DCD $Handler - MEND - ENDIF - -;/* A macro to ease definition of the various handlers based on STEP ID */ - IF :DEF:WORKAROUND_PMU_CM001 - - ;/* First define the final exception handler */ - MACRO - ExcpHandler $Handler_Func -$Handler_Func\ - PROC - EXPORT $Handler_Func [WEAK] - B . - ENDP - - ;/* And then define a veneer that will branch to the final excp handler */ -$Handler_Func._Veneer\ - PROC - EXPORT $Handler_Func._Veneer [WEAK] - LDR R0, =$Handler_Func - PUSH {LR} - BLX R0 - POP {PC} - ALIGN - LTORG - ENDP - MEND - - ELSE - - ;/* No prefetch bug, hence define only the final exception handler */ - MACRO - ExcpHandler $Handler_Func -$Handler_Func\ - PROC - EXPORT $Handler_Func [WEAK] - B . - ENDP - MEND - - ENDIF -;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */ - - -;* ================== START OF VECTOR TABLE DEFINITION ====================== */ -;* Vector Table - This gets programed into VTOR register */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - - - -__Vectors - DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - - ExcpVector NMI_Handler ; NMI Handler - ExcpVector HardFault_Handler ; Hard Fault Handler - ExcpVector MemManage_Handler ; MPU Fault Handler - ExcpVector BusFault_Handler ; Bus Fault Handler - ExcpVector UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - ExcpVector DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals - ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0 - ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0 - ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1 - ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2 - ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3 - ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0 - ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1 - ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2 - ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0 - DCD 0 ; Reserved - ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0 - ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1 - ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1 - ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3 - ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0 - ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1 - ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2 - ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3 - ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0 - ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1 - ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2 - ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0 - ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1 - ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0 - ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1 - ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2 - ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3 - ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0 - ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1 - ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2 - ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0 - ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1 - ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2 - ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0 - ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1 - DCD 0 ; Reserved - DCD 0 ; Reserved - ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0 - ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1 - ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2 - ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3 - ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0 - ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1 - ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2 - ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3 - ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4 - ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5 - ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6 - ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7 - ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0 - ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1 - ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2 - ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3 - ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4 - ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5 - ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0 - ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1 - ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2 - ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3 - ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4 - ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0 - DCD 0 ; Reserved - ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0 - ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0 - DCD 0 ; Reserved - ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -;* ================== END OF VECTOR TABLE DEFINITION ======================= */ - -;* ================== START OF VECTOR ROUTINES ============================= */ - - AREA |.text|, CODE, READONLY - -;* Reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - ; Remap vector table - LDR R0, =__Vectors - LDR R1, =0xE000ED08 ;*VTOR register - STR R0,[R1] - - ;* C routines are likely to be called. Setup the stack now - LDR SP,=__initial_sp - - LDR R0, = SystemInit - BLX R0 - - ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is - ;weakly defined here though for a potential override. - - LDR R0, = SystemInit_DAVE3 - BLX R0 - - ;* Reset stack pointer before zipping off to user application - LDR SP,=__initial_sp - - LDR R0, =__main - BX R0 - - ALIGN - ENDP - - - - -;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ - - - -;/* Default exception Handlers - Users may override this default functionality by -; defining handlers of the same name in their C code */ - - ExcpHandler NMI_Handler - ExcpHandler HardFault_Handler - ExcpHandler MemManage_Handler - ExcpHandler BusFault_Handler - ExcpHandler UsageFault_Handler - ExcpHandler SVC_Handler - ExcpHandler DebugMon_Handler - ExcpHandler PendSV_Handler - ExcpHandler SysTick_Handler - -;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ - -;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ - -;* IRQ Handlers */ - ExcpHandler SCU_0_IRQHandler - ExcpHandler ERU0_0_IRQHandler - ExcpHandler ERU0_1_IRQHandler - ExcpHandler ERU0_2_IRQHandler - ExcpHandler ERU0_3_IRQHandler - ExcpHandler ERU1_0_IRQHandler - ExcpHandler ERU1_1_IRQHandler - ExcpHandler ERU1_2_IRQHandler - ExcpHandler ERU1_3_IRQHandler - ExcpHandler PMU0_0_IRQHandler - ExcpHandler VADC0_C0_0_IRQHandler - ExcpHandler VADC0_C0_1_IRQHandler - ExcpHandler VADC0_C0_2_IRQHandler - ExcpHandler VADC0_C0_3_IRQHandler - ExcpHandler VADC0_G0_0_IRQHandler - ExcpHandler VADC0_G0_1_IRQHandler - ExcpHandler VADC0_G0_2_IRQHandler - ExcpHandler VADC0_G0_3_IRQHandler - ExcpHandler VADC0_G1_0_IRQHandler - ExcpHandler VADC0_G1_1_IRQHandler - ExcpHandler VADC0_G1_2_IRQHandler - ExcpHandler VADC0_G1_3_IRQHandler - ExcpHandler DAC0_0_IRQHandler - ExcpHandler DAC0_1_IRQHandler - ExcpHandler CCU40_0_IRQHandler - ExcpHandler CCU40_1_IRQHandler - ExcpHandler CCU40_2_IRQHandler - ExcpHandler CCU40_3_IRQHandler - ExcpHandler CCU41_0_IRQHandler - ExcpHandler CCU41_1_IRQHandler - ExcpHandler CCU41_2_IRQHandler - ExcpHandler CCU41_3_IRQHandler - ExcpHandler CCU80_0_IRQHandler - ExcpHandler CCU80_1_IRQHandler - ExcpHandler CCU80_2_IRQHandler - ExcpHandler CCU80_3_IRQHandler - ExcpHandler POSIF0_0_IRQHandler - ExcpHandler POSIF0_1_IRQHandler - ExcpHandler HRPWM_0_IRQHandler - ExcpHandler HRPWM_1_IRQHandler - ExcpHandler HRPWM_2_IRQHandler - ExcpHandler HRPWM_3_IRQHandler - ExcpHandler CAN0_0_IRQHandler - ExcpHandler CAN0_1_IRQHandler - ExcpHandler CAN0_2_IRQHandler - ExcpHandler CAN0_3_IRQHandler - ExcpHandler CAN0_4_IRQHandler - ExcpHandler CAN0_5_IRQHandler - ExcpHandler CAN0_6_IRQHandler - ExcpHandler CAN0_7_IRQHandler - ExcpHandler USIC0_0_IRQHandler - ExcpHandler USIC0_1_IRQHandler - ExcpHandler USIC0_2_IRQHandler - ExcpHandler USIC0_3_IRQHandler - ExcpHandler USIC0_4_IRQHandler - ExcpHandler USIC0_5_IRQHandler - ExcpHandler USIC1_0_IRQHandler - ExcpHandler USIC1_1_IRQHandler - ExcpHandler USIC1_2_IRQHandler - ExcpHandler USIC1_3_IRQHandler - ExcpHandler USIC1_4_IRQHandler - ExcpHandler USIC1_5_IRQHandler - ExcpHandler LEDTS0_0_IRQHandler - ExcpHandler FCE0_0_IRQHandler - ExcpHandler GPDMA0_0_IRQHandler - ExcpHandler USB0_0_IRQHandler - -;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ - -;* Definition of the default weak SystemInit_DAVE3 function. -;* This function will be called by the CMSIS SystemInit function. -;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3 -;* which will overule this weak definition -SystemInit_DAVE3 PROC - EXPORT SystemInit_DAVE3 [WEAK] - NOP - BX LR - ENDP - -;* Definition of the default weak DAVE3 function for clock App usage. -;* AllowPLLInitByStartup Handler */ -AllowPLLInitByStartup PROC - EXPORT AllowPLLInitByStartup [WEAK] - MOV R0,#1 - BX LR - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE***** diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4400.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4400.s deleted file mode 100644 index cebede580..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4400.s +++ /dev/null @@ -1,486 +0,0 @@ -;*****************************************************************************/ -; * @file startup_XMC4400.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Infineon XMC4400 Device Series -; * @version V1.00 -; * @date 05. February 2013 -; * -; * @note -; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -;/* ********************* Version History *********************************** */ -;/* *************************************************************************** -; V0.2 , August 2012, First version -; V1.0 , February 2013, FIX for CPU prefetch bug implemented -;**************************************************************************** */ - - -;* <<< Use Configuration Wizard in Context Menu >>> - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ -;/* -; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001). -; * A veneer defined below will first -; * be executed which in turn branches to the final exception handler. -; * -; * In addition to defining the veneers, the vector table must for these buggy -; * devices contain the veneers. -; */ - -;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define -;or use define below - GBLL WORKAROUND_PMU_CM001 - -;/* A macro to setup a vector table entry based on STEP ID */ - IF :DEF:WORKAROUND_PMU_CM001 - MACRO - ExcpVector $Handler - DCD $Handler._Veneer - MEND - ELSE - MACRO - ExcpVector $Handler - DCD $Handler - MEND - ENDIF - -;/* A macro to ease definition of the various handlers based on STEP ID */ - IF :DEF:WORKAROUND_PMU_CM001 - - ;/* First define the final exception handler */ - MACRO - ExcpHandler $Handler_Func -$Handler_Func\ - PROC - EXPORT $Handler_Func [WEAK] - B . - ENDP - - ;/* And then define a veneer that will branch to the final excp handler */ -$Handler_Func._Veneer\ - PROC - EXPORT $Handler_Func._Veneer [WEAK] - LDR R0, =$Handler_Func - PUSH {LR} - BLX R0 - POP {PC} - ALIGN - LTORG - ENDP - MEND - - ELSE - - ;/* No prefetch bug, hence define only the final exception handler */ - MACRO - ExcpHandler $Handler_Func -$Handler_Func\ - PROC - EXPORT $Handler_Func [WEAK] - B . - ENDP - MEND - - ENDIF -;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */ - - -;* ================== START OF VECTOR TABLE DEFINITION ====================== */ -;* Vector Table - This gets programed into VTOR register */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - - - -__Vectors - DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - - ExcpVector NMI_Handler ; NMI Handler - ExcpVector HardFault_Handler ; Hard Fault Handler - ExcpVector MemManage_Handler ; MPU Fault Handler - ExcpVector BusFault_Handler ; Bus Fault Handler - ExcpVector UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - ExcpVector DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Interrupt Handlers for Service Requests (SR) from XMC4400 Peripherals - ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0 - ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0 - ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1 - ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2 - ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3 - ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0 - ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1 - ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2 - ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0 - DCD 0 ; Reserved - ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0 - ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1 - ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1 - ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3 - ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0 - ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1 - ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2 - ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3 - ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0 - ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1 - ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2 - ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3 - ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0 - ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1 - ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2 - ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3 - ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0 - ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1 - ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2 - ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3 - ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0 - ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1 - ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2 - ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3 - ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4 - ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5 - ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6 - ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7 - ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0 - ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1 - ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0 - ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1 - ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2 - ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3 - ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0 - ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1 - ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2 - ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3 - ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0 - ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1 - ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2 - ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3 - ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0 - ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1 - ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2 - ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3 - ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0 - ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1 - ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2 - ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3 - ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0 - ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1 - ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2 - ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3 - ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0 - ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1 - ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0 - ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1 - ExcpVector HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0 - ExcpVector HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1 - ExcpVector HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2 - ExcpVector HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3 - ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0 - ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1 - ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2 - ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3 - ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4 - ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5 - ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6 - ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7 - ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0 - ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1 - ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2 - ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3 - ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4 - ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5 - ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0 - ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1 - ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2 - ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3 - ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4 - ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0 - DCD 0 ; Reserved - ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0 - ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0 - DCD 0 ; Reserved - ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0 - ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -;* ================== END OF VECTOR TABLE DEFINITION ======================= */ - -;* ================== START OF VECTOR ROUTINES ============================= */ - - AREA |.text|, CODE, READONLY - -;* Reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - ; Remap vector table - LDR R0, =__Vectors - LDR R1, =0xE000ED08 ;*VTOR register - STR R0,[R1] - - ;* C routines are likely to be called. Setup the stack now - LDR SP,=__initial_sp - - LDR R0, = SystemInit - BLX R0 - - ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is - ;weakly defined here though for a potential override. - - LDR R0, = SystemInit_DAVE3 - BLX R0 - - ;* Reset stack pointer before zipping off to user application - LDR SP,=__initial_sp - - LDR R0, =__main - BX R0 - - ALIGN - ENDP - - - - -;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ - - - -;/* Default exception Handlers - Users may override this default functionality by -; defining handlers of the same name in their C code */ - - ExcpHandler NMI_Handler - ExcpHandler HardFault_Handler - ExcpHandler MemManage_Handler - ExcpHandler BusFault_Handler - ExcpHandler UsageFault_Handler - ExcpHandler SVC_Handler - ExcpHandler DebugMon_Handler - ExcpHandler PendSV_Handler - ExcpHandler SysTick_Handler - -;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ - -;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ - -;* IRQ Handlers */ - ExcpHandler SCU_0_IRQHandler - ExcpHandler ERU0_0_IRQHandler - ExcpHandler ERU0_1_IRQHandler - ExcpHandler ERU0_2_IRQHandler - ExcpHandler ERU0_3_IRQHandler - ExcpHandler ERU1_0_IRQHandler - ExcpHandler ERU1_1_IRQHandler - ExcpHandler ERU1_2_IRQHandler - ExcpHandler ERU1_3_IRQHandler - ExcpHandler PMU0_0_IRQHandler - ExcpHandler VADC0_C0_0_IRQHandler - ExcpHandler VADC0_C0_1_IRQHandler - ExcpHandler VADC0_C0_2_IRQHandler - ExcpHandler VADC0_C0_3_IRQHandler - ExcpHandler VADC0_G0_0_IRQHandler - ExcpHandler VADC0_G0_1_IRQHandler - ExcpHandler VADC0_G0_2_IRQHandler - ExcpHandler VADC0_G0_3_IRQHandler - ExcpHandler VADC0_G1_0_IRQHandler - ExcpHandler VADC0_G1_1_IRQHandler - ExcpHandler VADC0_G1_2_IRQHandler - ExcpHandler VADC0_G1_3_IRQHandler - ExcpHandler VADC0_G2_0_IRQHandler - ExcpHandler VADC0_G2_1_IRQHandler - ExcpHandler VADC0_G2_2_IRQHandler - ExcpHandler VADC0_G2_3_IRQHandler - ExcpHandler VADC0_G3_0_IRQHandler - ExcpHandler VADC0_G3_1_IRQHandler - ExcpHandler VADC0_G3_2_IRQHandler - ExcpHandler VADC0_G3_3_IRQHandler - ExcpHandler DSD0_0_IRQHandler - ExcpHandler DSD0_1_IRQHandler - ExcpHandler DSD0_2_IRQHandler - ExcpHandler DSD0_3_IRQHandler - ExcpHandler DSD0_4_IRQHandler - ExcpHandler DSD0_5_IRQHandler - ExcpHandler DSD0_6_IRQHandler - ExcpHandler DSD0_7_IRQHandler - ExcpHandler DAC0_0_IRQHandler - ExcpHandler DAC0_1_IRQHandler - ExcpHandler CCU40_0_IRQHandler - ExcpHandler CCU40_1_IRQHandler - ExcpHandler CCU40_2_IRQHandler - ExcpHandler CCU40_3_IRQHandler - ExcpHandler CCU41_0_IRQHandler - ExcpHandler CCU41_1_IRQHandler - ExcpHandler CCU41_2_IRQHandler - ExcpHandler CCU41_3_IRQHandler - ExcpHandler CCU42_0_IRQHandler - ExcpHandler CCU42_1_IRQHandler - ExcpHandler CCU42_2_IRQHandler - ExcpHandler CCU42_3_IRQHandler - ExcpHandler CCU43_0_IRQHandler - ExcpHandler CCU43_1_IRQHandler - ExcpHandler CCU43_2_IRQHandler - ExcpHandler CCU43_3_IRQHandler - ExcpHandler CCU80_0_IRQHandler - ExcpHandler CCU80_1_IRQHandler - ExcpHandler CCU80_2_IRQHandler - ExcpHandler CCU80_3_IRQHandler - ExcpHandler CCU81_0_IRQHandler - ExcpHandler CCU81_1_IRQHandler - ExcpHandler CCU81_2_IRQHandler - ExcpHandler CCU81_3_IRQHandler - ExcpHandler POSIF0_0_IRQHandler - ExcpHandler POSIF0_1_IRQHandler - ExcpHandler POSIF1_0_IRQHandler - ExcpHandler POSIF1_1_IRQHandler - ExcpHandler HRPWM_0_IRQHandler - ExcpHandler HRPWM_1_IRQHandler - ExcpHandler HRPWM_2_IRQHandler - ExcpHandler HRPWM_3_IRQHandler - ExcpHandler CAN0_0_IRQHandler - ExcpHandler CAN0_1_IRQHandler - ExcpHandler CAN0_2_IRQHandler - ExcpHandler CAN0_3_IRQHandler - ExcpHandler CAN0_4_IRQHandler - ExcpHandler CAN0_5_IRQHandler - ExcpHandler CAN0_6_IRQHandler - ExcpHandler CAN0_7_IRQHandler - ExcpHandler USIC0_0_IRQHandler - ExcpHandler USIC0_1_IRQHandler - ExcpHandler USIC0_2_IRQHandler - ExcpHandler USIC0_3_IRQHandler - ExcpHandler USIC0_4_IRQHandler - ExcpHandler USIC0_5_IRQHandler - ExcpHandler USIC1_0_IRQHandler - ExcpHandler USIC1_1_IRQHandler - ExcpHandler USIC1_2_IRQHandler - ExcpHandler USIC1_3_IRQHandler - ExcpHandler USIC1_4_IRQHandler - ExcpHandler USIC1_5_IRQHandler - ExcpHandler LEDTS0_0_IRQHandler - ExcpHandler FCE0_0_IRQHandler - ExcpHandler GPDMA0_0_IRQHandler - ExcpHandler USB0_0_IRQHandler - ExcpHandler ETH0_0_IRQHandler - -;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ - -;* Definition of the default weak SystemInit_DAVE3 function. -;* This function will be called by the CMSIS SystemInit function. -;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3 -;* which will overule this weak definition -SystemInit_DAVE3 PROC - EXPORT SystemInit_DAVE3 [WEAK] - NOP - BX LR - ENDP - -;* Definition of the default weak DAVE3 function for clock App usage. -;* AllowPLLInitByStartup Handler */ -AllowPLLInitByStartup PROC - EXPORT AllowPLLInitByStartup [WEAK] - MOV R0,#1 - BX LR - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE***** diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s deleted file mode 100644 index 1f2422253..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/startup_XMC4500.s +++ /dev/null @@ -1,491 +0,0 @@ -;*****************************************************************************/ -; * @file startup_XMC4500.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Infineon XMC4500 Device Series -; * @version V1.20 -; * @date 05. February 2013 -; * -; * @note -; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -;/* ********************* Version History *********************************** */ -;/* *************************************************************************** -; V1.00 , February 2012, First version -; V1.10 , August 2012, Adding Dave3 init function call -; V1.20 , February 2013, FIX for CPU prefetch bug implemented -;**************************************************************************** */ - - -;* <<< Use Configuration Wizard in Context Menu >>> - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -;/* ===========START : MACRO DEFINITION MACRO DEFINITION ================== */ -;/* -; * STEP_AB and below have the prefetch functional deviation (Errata id: PMU_CM.001). -; * A veneer defined below will first -; * be executed which in turn branches to the final exception handler. -; * -; * In addition to defining the veneers, the vector table must for these buggy -; * devices contain the veneers. -; */ - -;set WORKAROUND_PMU_CM001 under Options for target - Asm - Define -;or use define below - GBLL WORKAROUND_PMU_CM001 - -;/* A macro to setup a vector table entry based on STEP ID */ - IF :DEF:WORKAROUND_PMU_CM001 - MACRO - ExcpVector $Handler - DCD $Handler._Veneer - MEND - ELSE - MACRO - ExcpVector $Handler - DCD $Handler - MEND - ENDIF - -;/* A macro to ease definition of the various handlers based on STEP ID */ - IF :DEF:WORKAROUND_PMU_CM001 - - ;/* First define the final exception handler */ - MACRO - ExcpHandler $Handler_Func -$Handler_Func\ - PROC - EXPORT $Handler_Func [WEAK] - B . - ENDP - - ;/* And then define a veneer that will branch to the final excp handler */ -$Handler_Func._Veneer\ - PROC - EXPORT $Handler_Func._Veneer [WEAK] - LDR R0, =$Handler_Func - PUSH {LR} - BLX R0 - POP {PC} - ALIGN - LTORG - ENDP - MEND - - ELSE - - ;/* No prefetch bug, hence define only the final exception handler */ - MACRO - ExcpHandler $Handler_Func -$Handler_Func\ - PROC - EXPORT $Handler_Func [WEAK] - B . - ENDP - MEND - - ENDIF -;/* ============= END OF MACRO DEFINITION MACRO DEFINITION ================== */ - - -;* ================== START OF VECTOR TABLE DEFINITION ====================== */ -;* Vector Table - This gets programed into VTOR register */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - - - -__Vectors - DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - - ExcpVector NMI_Handler ; NMI Handler - ExcpVector HardFault_Handler ; Hard Fault Handler - ExcpVector MemManage_Handler ; MPU Fault Handler - ExcpVector BusFault_Handler ; Bus Fault Handler - ExcpVector UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - ExcpVector DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Interrupt Handlers for Service Requests (SR) from XMC4500 Peripherals - ExcpVector SCU_0_IRQHandler ; Handler name for SR SCU_0 - ExcpVector ERU0_0_IRQHandler ; Handler name for SR ERU0_0 - ExcpVector ERU0_1_IRQHandler ; Handler name for SR ERU0_1 - ExcpVector ERU0_2_IRQHandler ; Handler name for SR ERU0_2 - ExcpVector ERU0_3_IRQHandler ; Handler name for SR ERU0_3 - ExcpVector ERU1_0_IRQHandler ; Handler name for SR ERU1_0 - ExcpVector ERU1_1_IRQHandler ; Handler name for SR ERU1_1 - ExcpVector ERU1_2_IRQHandler ; Handler name for SR ERU1_2 - ExcpVector ERU1_3_IRQHandler ; Handler name for SR ERU1_3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - ExcpVector PMU0_0_IRQHandler ; Handler name for SR PMU0_0 - DCD 0 ; Reserved - ExcpVector VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0 - ExcpVector VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1 - ExcpVector VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1 - ExcpVector VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3 - ExcpVector VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0 - ExcpVector VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1 - ExcpVector VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2 - ExcpVector VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3 - ExcpVector VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0 - ExcpVector VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1 - ExcpVector VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2 - ExcpVector VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3 - ExcpVector VADC0_G2_0_IRQHandler ; Handler name for SR VADC0_G2_0 - ExcpVector VADC0_G2_1_IRQHandler ; Handler name for SR VADC0_G2_1 - ExcpVector VADC0_G2_2_IRQHandler ; Handler name for SR VADC0_G2_2 - ExcpVector VADC0_G2_3_IRQHandler ; Handler name for SR VADC0_G2_3 - ExcpVector VADC0_G3_0_IRQHandler ; Handler name for SR VADC0_G3_0 - ExcpVector VADC0_G3_1_IRQHandler ; Handler name for SR VADC0_G3_1 - ExcpVector VADC0_G3_2_IRQHandler ; Handler name for SR VADC0_G3_2 - ExcpVector VADC0_G3_3_IRQHandler ; Handler name for SR VADC0_G3_3 - ExcpVector DSD0_0_IRQHandler ; Handler name for SR DSD0_0 - ExcpVector DSD0_1_IRQHandler ; Handler name for SR DSD0_1 - ExcpVector DSD0_2_IRQHandler ; Handler name for SR DSD0_2 - ExcpVector DSD0_3_IRQHandler ; Handler name for SR DSD0_3 - ExcpVector DSD0_4_IRQHandler ; Handler name for SR DSD0_4 - ExcpVector DSD0_5_IRQHandler ; Handler name for SR DSD0_5 - ExcpVector DSD0_6_IRQHandler ; Handler name for SR DSD0_6 - ExcpVector DSD0_7_IRQHandler ; Handler name for SR DSD0_7 - ExcpVector DAC0_0_IRQHandler ; Handler name for SR DAC0_0 - ExcpVector DAC0_1_IRQHandler ; Handler name for SR DAC0_1 - ExcpVector CCU40_0_IRQHandler ; Handler name for SR CCU40_0 - ExcpVector CCU40_1_IRQHandler ; Handler name for SR CCU40_1 - ExcpVector CCU40_2_IRQHandler ; Handler name for SR CCU40_2 - ExcpVector CCU40_3_IRQHandler ; Handler name for SR CCU40_3 - ExcpVector CCU41_0_IRQHandler ; Handler name for SR CCU41_0 - ExcpVector CCU41_1_IRQHandler ; Handler name for SR CCU41_1 - ExcpVector CCU41_2_IRQHandler ; Handler name for SR CCU41_2 - ExcpVector CCU41_3_IRQHandler ; Handler name for SR CCU41_3 - ExcpVector CCU42_0_IRQHandler ; Handler name for SR CCU42_0 - ExcpVector CCU42_1_IRQHandler ; Handler name for SR CCU42_1 - ExcpVector CCU42_2_IRQHandler ; Handler name for SR CCU42_2 - ExcpVector CCU42_3_IRQHandler ; Handler name for SR CCU42_3 - ExcpVector CCU43_0_IRQHandler ; Handler name for SR CCU43_0 - ExcpVector CCU43_1_IRQHandler ; Handler name for SR CCU43_1 - ExcpVector CCU43_2_IRQHandler ; Handler name for SR CCU43_2 - ExcpVector CCU43_3_IRQHandler ; Handler name for SR CCU43_3 - ExcpVector CCU80_0_IRQHandler ; Handler name for SR CCU80_0 - ExcpVector CCU80_1_IRQHandler ; Handler name for SR CCU80_1 - ExcpVector CCU80_2_IRQHandler ; Handler name for SR CCU80_2 - ExcpVector CCU80_3_IRQHandler ; Handler name for SR CCU80_3 - ExcpVector CCU81_0_IRQHandler ; Handler name for SR CCU81_0 - ExcpVector CCU81_1_IRQHandler ; Handler name for SR CCU81_1 - ExcpVector CCU81_2_IRQHandler ; Handler name for SR CCU81_2 - ExcpVector CCU81_3_IRQHandler ; Handler name for SR CCU81_3 - ExcpVector POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0 - ExcpVector POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1 - ExcpVector POSIF1_0_IRQHandler ; Handler name for SR POSIF1_0 - ExcpVector POSIF1_1_IRQHandler ; Handler name for SR POSIF1_1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - ExcpVector CAN0_0_IRQHandler ; Handler name for SR CAN0_0 - ExcpVector CAN0_1_IRQHandler ; Handler name for SR CAN0_1 - ExcpVector CAN0_2_IRQHandler ; Handler name for SR CAN0_2 - ExcpVector CAN0_3_IRQHandler ; Handler name for SR CAN0_3 - ExcpVector CAN0_4_IRQHandler ; Handler name for SR CAN0_4 - ExcpVector CAN0_5_IRQHandler ; Handler name for SR CAN0_5 - ExcpVector CAN0_6_IRQHandler ; Handler name for SR CAN0_6 - ExcpVector CAN0_7_IRQHandler ; Handler name for SR CAN0_7 - ExcpVector USIC0_0_IRQHandler ; Handler name for SR USIC0_0 - ExcpVector USIC0_1_IRQHandler ; Handler name for SR USIC0_1 - ExcpVector USIC0_2_IRQHandler ; Handler name for SR USIC0_2 - ExcpVector USIC0_3_IRQHandler ; Handler name for SR USIC0_3 - ExcpVector USIC0_4_IRQHandler ; Handler name for SR USIC0_4 - ExcpVector USIC0_5_IRQHandler ; Handler name for SR USIC0_5 - ExcpVector USIC1_0_IRQHandler ; Handler name for SR USIC1_0 - ExcpVector USIC1_1_IRQHandler ; Handler name for SR USIC1_1 - ExcpVector USIC1_2_IRQHandler ; Handler name for SR USIC1_2 - ExcpVector USIC1_3_IRQHandler ; Handler name for SR USIC1_3 - ExcpVector USIC1_4_IRQHandler ; Handler name for SR USIC1_4 - ExcpVector USIC1_5_IRQHandler ; Handler name for SR USIC1_5 - ExcpVector USIC2_0_IRQHandler ; Handler name for SR USIC2_0 - ExcpVector USIC2_1_IRQHandler ; Handler name for SR USIC2_1 - ExcpVector USIC2_2_IRQHandler ; Handler name for SR USIC2_2 - ExcpVector USIC2_3_IRQHandler ; Handler name for SR USIC2_3 - ExcpVector USIC2_4_IRQHandler ; Handler name for SR USIC2_4 - ExcpVector USIC2_5_IRQHandler ; Handler name for SR USIC2_5 - ExcpVector LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0 - DCD 0 ; Reserved - ExcpVector FCE0_0_IRQHandler ; Handler name for SR FCE0_0 - ExcpVector GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0 - ExcpVector SDMMC0_0_IRQHandler ; Handler name for SR SDMMC0_0 - ExcpVector USB0_0_IRQHandler ; Handler name for SR USB0_0 - ExcpVector ETH0_0_IRQHandler ; Handler name for SR ETH0_0 - DCD 0 ; Reserved - ExcpVector GPDMA1_0_IRQHandler ; Handler name for SR GPDMA1_0 - DCD 0 ; Reserved -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -;* ================== END OF VECTOR TABLE DEFINITION ======================= */ - -;* ================== START OF VECTOR ROUTINES ============================= */ - - AREA |.text|, CODE, READONLY - -;* Reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - ; Remap vector table - LDR R0, =__Vectors - LDR R1, =0xE000ED08 ;*VTOR register - STR R0,[R1] - - ;* C routines are likely to be called. Setup the stack now - LDR SP,=__initial_sp - - LDR R0, = SystemInit - BLX R0 - - ;SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is - ;weakly defined here though for a potential override. - - LDR R0, = SystemInit_DAVE3 - BLX R0 - - ;* Reset stack pointer before zipping off to user application - LDR SP,=__initial_sp - - LDR R0, =__main - BX R0 - - ALIGN - ENDP - - - - -;* ========== START OF EXCEPTION HANDLER DEFINITION ======================== */ - - - -;/* Default exception Handlers - Users may override this default functionality by -; defining handlers of the same name in their C code */ - - ExcpHandler NMI_Handler - ExcpHandler HardFault_Handler - ExcpHandler MemManage_Handler - ExcpHandler BusFault_Handler - ExcpHandler UsageFault_Handler - ExcpHandler SVC_Handler - ExcpHandler DebugMon_Handler - ExcpHandler PendSV_Handler - ExcpHandler SysTick_Handler - -;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ - -;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ - -;* IRQ Handlers */ - ExcpHandler SCU_0_IRQHandler - ExcpHandler ERU0_0_IRQHandler - ExcpHandler ERU0_1_IRQHandler - ExcpHandler ERU0_2_IRQHandler - ExcpHandler ERU0_3_IRQHandler - ExcpHandler ERU1_0_IRQHandler - ExcpHandler ERU1_1_IRQHandler - ExcpHandler ERU1_2_IRQHandler - ExcpHandler ERU1_3_IRQHandler - ExcpHandler PMU0_0_IRQHandler - ExcpHandler VADC0_C0_0_IRQHandler - ExcpHandler VADC0_C0_1_IRQHandler - ExcpHandler VADC0_C0_2_IRQHandler - ExcpHandler VADC0_C0_3_IRQHandler - ExcpHandler VADC0_G0_0_IRQHandler - ExcpHandler VADC0_G0_1_IRQHandler - ExcpHandler VADC0_G0_2_IRQHandler - ExcpHandler VADC0_G0_3_IRQHandler - ExcpHandler VADC0_G1_0_IRQHandler - ExcpHandler VADC0_G1_1_IRQHandler - ExcpHandler VADC0_G1_2_IRQHandler - ExcpHandler VADC0_G1_3_IRQHandler - ExcpHandler VADC0_G2_0_IRQHandler - ExcpHandler VADC0_G2_1_IRQHandler - ExcpHandler VADC0_G2_2_IRQHandler - ExcpHandler VADC0_G2_3_IRQHandler - ExcpHandler VADC0_G3_0_IRQHandler - ExcpHandler VADC0_G3_1_IRQHandler - ExcpHandler VADC0_G3_2_IRQHandler - ExcpHandler VADC0_G3_3_IRQHandler - ExcpHandler DSD0_0_IRQHandler - ExcpHandler DSD0_1_IRQHandler - ExcpHandler DSD0_2_IRQHandler - ExcpHandler DSD0_3_IRQHandler - ExcpHandler DSD0_4_IRQHandler - ExcpHandler DSD0_5_IRQHandler - ExcpHandler DSD0_6_IRQHandler - ExcpHandler DSD0_7_IRQHandler - ExcpHandler DAC0_0_IRQHandler - ExcpHandler DAC0_1_IRQHandler - ExcpHandler CCU40_0_IRQHandler - ExcpHandler CCU40_1_IRQHandler - ExcpHandler CCU40_2_IRQHandler - ExcpHandler CCU40_3_IRQHandler - ExcpHandler CCU41_0_IRQHandler - ExcpHandler CCU41_1_IRQHandler - ExcpHandler CCU41_2_IRQHandler - ExcpHandler CCU41_3_IRQHandler - ExcpHandler CCU42_0_IRQHandler - ExcpHandler CCU42_1_IRQHandler - ExcpHandler CCU42_2_IRQHandler - ExcpHandler CCU42_3_IRQHandler - ExcpHandler CCU43_0_IRQHandler - ExcpHandler CCU43_1_IRQHandler - ExcpHandler CCU43_2_IRQHandler - ExcpHandler CCU43_3_IRQHandler - ExcpHandler CCU80_0_IRQHandler - ExcpHandler CCU80_1_IRQHandler - ExcpHandler CCU80_2_IRQHandler - ExcpHandler CCU80_3_IRQHandler - ExcpHandler CCU81_0_IRQHandler - ExcpHandler CCU81_1_IRQHandler - ExcpHandler CCU81_2_IRQHandler - ExcpHandler CCU81_3_IRQHandler - ExcpHandler POSIF0_0_IRQHandler - ExcpHandler POSIF0_1_IRQHandler - ExcpHandler POSIF1_0_IRQHandler - ExcpHandler POSIF1_1_IRQHandler - ExcpHandler CAN0_0_IRQHandler - ExcpHandler CAN0_1_IRQHandler - ExcpHandler CAN0_2_IRQHandler - ExcpHandler CAN0_3_IRQHandler - ExcpHandler CAN0_4_IRQHandler - ExcpHandler CAN0_5_IRQHandler - ExcpHandler CAN0_6_IRQHandler - ExcpHandler CAN0_7_IRQHandler - ExcpHandler USIC0_0_IRQHandler - ExcpHandler USIC0_1_IRQHandler - ExcpHandler USIC0_2_IRQHandler - ExcpHandler USIC0_3_IRQHandler - ExcpHandler USIC0_4_IRQHandler - ExcpHandler USIC0_5_IRQHandler - ExcpHandler USIC1_0_IRQHandler - ExcpHandler USIC1_1_IRQHandler - ExcpHandler USIC1_2_IRQHandler - ExcpHandler USIC1_3_IRQHandler - ExcpHandler USIC1_4_IRQHandler - ExcpHandler USIC1_5_IRQHandler - ExcpHandler USIC2_0_IRQHandler - ExcpHandler USIC2_1_IRQHandler - ExcpHandler USIC2_2_IRQHandler - ExcpHandler USIC2_3_IRQHandler - ExcpHandler USIC2_4_IRQHandler - ExcpHandler USIC2_5_IRQHandler - ExcpHandler LEDTS0_0_IRQHandler - ExcpHandler FCE0_0_IRQHandler - ExcpHandler GPDMA0_0_IRQHandler - ExcpHandler SDMMC0_0_IRQHandler - ExcpHandler USB0_0_IRQHandler - ExcpHandler ETH0_0_IRQHandler - ExcpHandler GPDMA1_0_IRQHandler - -;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ - -;* Definition of the default weak SystemInit_DAVE3 function. -;* This function will be called by the CMSIS SystemInit function. -;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3 -;* which will overule this weak definition -SystemInit_DAVE3 PROC - EXPORT SystemInit_DAVE3 [WEAK] - NOP - BX LR - ENDP - -;* Definition of the default weak DAVE3 function for clock App usage. -;* AllowPLLInitByStartup Handler */ -AllowPLLInitByStartup PROC - EXPORT AllowPLLInitByStartup [WEAK] - MOV R0,#1 - BX LR - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* Copyright (C) 2009-2013 ARM Limited *****END OF FILE***** diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.c deleted file mode 100644 index 4b7f348f2..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.c +++ /dev/null @@ -1,708 +0,0 @@ -/**************************************************************************//** - * @file system_XMC4200.c - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File - * for the Infineon XMC4000 Device Series - * @version V3.0.1 Alpha - * @date 26. September 2012 - * - * @note - * Copyright (C) 2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include -#include - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemCoreClock; - -/* clock definitions, do not modify! */ -#define SCU_CLOCK_CRYSTAL 1 -#define SCU_CLOCK_BACK_UP_FACTORY 2 -#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 - - -#define HIB_CLOCK_FOSI 1 -#define HIB_CLOCK_OSCULP 2 - - - - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - - - -/*--------------------- Watchdog Configuration ------------------------------- -// -// Watchdog Configuration -// Disable Watchdog -// -// -*/ -#define WDT_SETUP 1 -#define WDTENB_nVal 0x00000001 - -/*--------------------- CLOCK Configuration ------------------------------- -// -// Main Clock Configuration -// CPU clock divider -// <0=> fCPU = fSYS -// <1=> fCPU = fSYS / 2 -// Peripheral Bus clock divider -// <0=> fPB = fCPU -// <1=> fPB = fCPU / 2 -// CCU Bus clock divider -// <0=> fCCU = fCPU -// <1=> fCCU = fCPU / 2 -// -// -// -*/ - -#define SCU_CLOCK_SETUP 1 -#define SCU_CPUCLKCR_DIV 0x00000000 -#define SCU_PBCLKCR_DIV 0x00000000 -#define SCU_CCUCLKCR_DIV 0x00000000 -/* not avalible in config wizzard*/ -/* -* mandatory clock parameters ************************************************** -* -* source for clock generation -* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) -* -**************************************************************************************/ -// Selection of imput lock for PLL -/*************************************************************************************/ -#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC - -/*************************************************************************************/ -// Standby clock selection for Backup clock source trimming -/*************************************************************************************/ -#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP -//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI - -/*************************************************************************************/ -// Global clock parameters -/*************************************************************************************/ -#define CLOCK_FSYS 80000000 -#define CLOCK_CRYSTAL_FREQUENCY 12000000 -#define CLOCK_BACK_UP 24000000 - -/*************************************************************************************/ -/* OSC_HP setup parameters */ -/*************************************************************************************/ -#define SCU_OSC_HP_MODE 0xF0 -#define SCU_OSCHPWDGDIV 2 - -/*************************************************************************************/ -/* MAIN PLL setup parameters */ -/*************************************************************************************/ -//Divider settings for external crystal @ 12 MHz -/*************************************************************************************/ -#define SCU_PLL_K1DIV 1 -#define SCU_PLL_K1DIV 1 -#define SCU_PLL_K2DIV 5 -#define SCU_PLL_PDIV 1 -#define SCU_PLL_NDIV 79 - -/*************************************************************************************/ -//Divider settings for use of backup clock source trimmed -/*************************************************************************************/ -//#define SCU_PLL_K1DIV 1 -//#define SCU_PLL_K2DIV 5 -//#define SCU_PLL_PDIV 3 -//#define SCU_PLL_NDIV 79 -/*************************************************************************************/ - - -/*--------------------- USB CLOCK Configuration --------------------------- -// -// USB Clock Configuration -// -// -// -*/ - -#define SCU_USB_CLOCK_SETUP 0 -/* not avalible in config wizzard*/ -#define SCU_USBPLL_PDIV 0 -#define SCU_USBPLL_NDIV 31 -#define SCU_USBDIV 3 - -/*--------------------- Flash Wait State Configuration ------------------------------- -// -// Flash Wait State Configuration -// Flash Wait State -// <0=> 3 WS -// <1=> 4 WS -// <2=> 5 WS -// <3=> 6 WS -// -// -*/ - -#define PMU_FLASH 1 -#define PMU_FLASH_WS 0x00000000 - - -/*--------------------- CLOCKOUT Configuration ------------------------------- -// -// Clock OUT Configuration -// Clockout Source Selection -// <0=> System Clock -// <2=> Divided value of USB PLL output -// <3=> Divided value of PLL Clock -// Clockout divider <1-10><#-1> -// Clockout Pin Selection -// <0=> P1.15 -// <1=> P0.8 -// -// -// -// -*/ - -#define SCU_CLOCKOUT_SETUP 0 -#define SCU_CLOCKOUT_SOURCE 0x00000000 -#define SCU_CLOCKOUT_DIV 0x00000009 -#define SCU_CLOCKOUT_PIN 0x00000001 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -#if SCU_CLOCK_SETUP -uint32_t SystemCoreClock = CLOCK_FSYS; -#else -uint32_t SystemCoreClock = CLOCK_BACK_UP; -#endif - -/*---------------------------------------------------------------------------- - static functions declarations - *----------------------------------------------------------------------------*/ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void); -#endif - -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void); -#endif - - -/** - * @brief Setup the microcontroller system. - * Initialize the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ -int temp; - -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) -SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ -#endif - -/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ -SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); - -/* Setup the WDT */ -#if WDT_SETUP - -WDT->CTR &= ~WDTENB_nVal; - -#endif - - -/* Setup the Flash Wait State */ -#if PMU_FLASH -temp = FLASH0->FCON; -temp &= ~FLASH_FCON_WSPFLASH_Msk; -temp |= PMU_FLASH_WS+3; -FLASH0->FCON = temp; -#endif - - -/* Setup the clockout */ -#if SCU_CLOCKOUT_SETUP - -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; -/*set PLL div for clkout */ -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; - -if (SCU_CLOCKOUT_PIN) { - PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ - PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); - PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ - } -else { - PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ - PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ - } - -#endif - - -/* Setup the System clock */ -#if SCU_CLOCK_SETUP -SystemClockSetup(); -#endif - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ - - -/* Setup the USB PL */ -#if SCU_USB_CLOCK_SETUP -USBClockSetup(); -#endif - - - -} - - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ -unsigned int PDIV; -unsigned int NDIV; -unsigned int K2DIV; -unsigned int long VCO; - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -if (SCU_CLK->SYSCLKCR == 0x00010000) -{ - if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ - /* check if PLL is locked */ - /* read back divider settings */ - PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; - NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; - K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; - - if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ - /* the selected clock is the Backup clock fofi */ - VCO = (CLOCK_BACK_UP/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - - } - else - { - /* the selected clock is the PLL external oscillator */ - VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - } - - - } -} -else -{ -SystemCoreClock = CLOCK_BACK_UP; -} - - -} - - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void) -{ -int temp; -unsigned int long VCO; -int stepping_K2DIV; - -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - -/* check if PLL is switched on */ -if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ -/* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - -} - -/* Enable OSC_HP if not already on*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) - { - /********************************************************************************************************************/ - /* Use external crystal for PLL clock input */ - /********************************************************************************************************************/ - - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* select external OSC as PLL input */ - SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) - { - /********************************************************************************************************************/ - /* Use factory trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) - { - /********************************************************************************************************************/ - /* Use automatic trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* check for HIB Domain enabled */ - if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) - SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ - - /* check for HIB Domain is not in reset state */ - if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) - SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ - - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) - { - /****************************************************************************************************************/ - /* Use fOSI as source of the standby clock */ - /****************************************************************************************************************/ - SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - } - else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) - { - /****************************************************************************************************************/ - /* Use fULP as source of the standby clock */ - /****************************************************************************************************************/ - /*check OSCUL if running correct*/ - if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) - { - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); - - SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ - /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ - /* select OSCUL clock for RTC*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*enable OSCULP WDG Alarm Enable*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*wait now for clock is stable */ - do - { - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - for(temp=0;temp<=0xFFFF;temp++); - } - while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); - - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - } - // now OSCULP is running and can be used - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - } - } - - /********************************************************************************************************************/ - /* Setup and look the main PLL */ - /********************************************************************************************************************/ - -if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ - /* Systen is still running from internal clock */ - /* select FOFI as system clock */ - if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ - - - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/24000000)-1; - /* Go to bypass the Main PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; - /* disconnect OSC_HP to PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - /* we may have to set OSCDISCDIS */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - /* connect OSC_HP to PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; - /* wait for PLL Lock */ - /* setup time out loop */ - /* Timeout for wait loo ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - - if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) - { - /* Go back to the Main PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; - } - else return(0); - - - /********************************************************* - here we need to setup the system clock divider - *********************************************************/ - - SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; - SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; - SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; - - - /* Switch system clock to PLL */ - SCU_CLK->SYSCLKCR |= 0x00010000; - - /* we may have to reset OSCDISCDIS */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /*********************************************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 60MHz - *********************************************************/ - if (CLOCK_FSYS > 60000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/60000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 90MHz - *********************************************************/ - if (CLOCK_FSYS > 90000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/90000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - } - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void) -{ -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - -/* check if PLL is switched on */ -if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); -} - -/* check and if not already running enable OSC_HP */ - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - /* check if Main PLL is switched on for OSC WD*/ - if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - } - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - - -/* Setup USB PLL */ - /* Go to bypass the Main PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; - /* disconnect OSC_FI to PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); - /* Setup USBDIV settings USB clock */ - SCU_CLK->USBCLKCR = SCU_USBDIV; - /* we may have to set OSCDISCDIS */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; - /* connect OSC_FI to PLL */ - SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; - /* wait for PLL Lock */ - while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); - - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.h deleted file mode 100644 index 33d38c1a7..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4200.h +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************//** - * @file system_XMC4200.h - * @brief Header file for the XMC4200-Series systeminit - * - * @version V1.0 - * @date 27. August 2012 - * - * @note - * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. - - * - * @par - * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. - * This file can be freely distributed within development tools that are supporting such microcontrollers. - - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - * - ******************************************************************************/ - - -#ifndef __SYSTEM_XMC4200_H -#define __SYSTEM_XMC4200_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -extern void SystemInit (void); - - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/* this weak function enables DAVE3 clock App usage */ -extern uint32_t AllowPLLInitByStartup(void); - - - -#ifdef __cplusplus -} -#endif - - -#endif diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.c b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.c deleted file mode 100644 index dfbbf9e8d..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.c +++ /dev/null @@ -1,707 +0,0 @@ -/**************************************************************************//** - * @file system_XMC4400.c - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File - * for the Infineon XMC4500 Device Series - * @version V3.0.1 Alpha - * @date 17. September 2012 - * - * @note - * Copyright (C) 2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include -#include - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemCoreClock; - -/* clock definitions, do not modify! */ -#define SCU_CLOCK_CRYSTAL 1 -#define SCU_CLOCK_BACK_UP_FACTORY 2 -#define SCU_CLOCK_BACK_UP_AUTOMATIC 3 - - -#define HIB_CLOCK_FOSI 1 -#define HIB_CLOCK_OSCULP 2 - - - - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - - - -/*--------------------- Watchdog Configuration ------------------------------- -// -// Watchdog Configuration -// Disable Watchdog -// -// -*/ -#define WDT_SETUP 1 -#define WDTENB_nVal 0x00000001 - -/*--------------------- CLOCK Configuration ------------------------------- -// -// Main Clock Configuration -// CPU clock divider -// <0=> fCPU = fSYS -// <1=> fCPU = fSYS / 2 -// Peripheral Bus clock divider -// <0=> fPB = fCPU -// <1=> fPB = fCPU / 2 -// CCU Bus clock divider -// <0=> fCCU = fCPU -// <1=> fCCU = fCPU / 2 -// -// -// -*/ - -#define SCU_CLOCK_SETUP 1 -#define SCU_CPUCLKCR_DIV 0x00000000 -#define SCU_PBCLKCR_DIV 0x00000000 -#define SCU_CCUCLKCR_DIV 0x00000000 -/* not avalible in config wizzard*/ -/* -* mandatory clock parameters ************************************************** -* -* source for clock generation -* range: SCU_CLOCK_CRYSTAL (crystal or external clock at crystal input) -* -**************************************************************************************/ -// Selection of imput lock for PLL -/*************************************************************************************/ -#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_CRYSTAL -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_FACTORY -//#define SCU_PLL_CLOCK_INPUT SCU_CLOCK_BACK_UP_AUTOMATIC - -/*************************************************************************************/ -// Standby clock selection for Backup clock source trimming -/*************************************************************************************/ -#define SCU_STANDBY_CLOCK HIB_CLOCK_OSCULP -//#define SCU_STANDBY_CLOCK HIB_CLOCK_FOSI - -/*************************************************************************************/ -// Global clock parameters -/*************************************************************************************/ -#define CLOCK_FSYS 120000000 -#define CLOCK_CRYSTAL_FREQUENCY 12000000 -#define CLOCK_BACK_UP 24000000 - -/*************************************************************************************/ -/* OSC_HP setup parameters */ -/*************************************************************************************/ -#define SCU_OSC_HP_MODE 0xF0 -#define SCU_OSCHPWDGDIV 2 - -/*************************************************************************************/ -/* MAIN PLL setup parameters */ -/*************************************************************************************/ -//Divider settings for external crystal @ 12 MHz -/*************************************************************************************/ -#define SCU_PLL_K1DIV 1 -#define SCU_PLL_K2DIV 3 -#define SCU_PLL_PDIV 1 -#define SCU_PLL_NDIV 79 - -/*************************************************************************************/ -//Divider settings for use of backup clock source trimmed -/*************************************************************************************/ -//#define SCU_PLL_K1DIV 1 -//#define SCU_PLL_K2DIV 3 -//#define SCU_PLL_PDIV 3 -//#define SCU_PLL_NDIV 79 -/*************************************************************************************/ - - -/*--------------------- USB CLOCK Configuration --------------------------- -// -// USB Clock Configuration -// -// -// -*/ - -#define SCU_USB_CLOCK_SETUP 0 -/* not avalible in config wizzard*/ -#define SCU_USBPLL_PDIV 0 -#define SCU_USBPLL_NDIV 31 -#define SCU_USBDIV 3 - -/*--------------------- Flash Wait State Configuration ------------------------------- -// -// Flash Wait State Configuration -// Flash Wait State -// <0=> 3 WS -// <1=> 4 WS -// <2=> 5 WS -// <3=> 6 WS -// -// -*/ - -#define PMU_FLASH 1 -#define PMU_FLASH_WS 0x00000000 - - -/*--------------------- CLOCKOUT Configuration ------------------------------- -// -// Clock OUT Configuration -// Clockout Source Selection -// <0=> System Clock -// <2=> Divided value of USB PLL output -// <3=> Divided value of PLL Clock -// Clockout divider <1-10><#-1> -// Clockout Pin Selection -// <0=> P1.15 -// <1=> P0.8 -// -// -// -// -*/ - -#define SCU_CLOCKOUT_SETUP 0 -#define SCU_CLOCKOUT_SOURCE 0x00000000 -#define SCU_CLOCKOUT_DIV 0x00000009 -#define SCU_CLOCKOUT_PIN 0x00000001 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -#if SCU_CLOCK_SETUP -uint32_t SystemCoreClock = CLOCK_FSYS; -#else -uint32_t SystemCoreClock = CLOCK_BACK_UP; -#endif - -/*---------------------------------------------------------------------------- - static functions declarations - *----------------------------------------------------------------------------*/ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void); -#endif - -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void); -#endif - - -/** - * @brief Setup the microcontroller system. - * Initialize the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ -int temp; - -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) -SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */ - (3UL << 11*2) ); /* set CP11 Full Access */ -#endif - -/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */ -SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk); - -/* Setup the WDT */ -#if WDT_SETUP - -WDT->CTR &= ~WDTENB_nVal; - -#endif - - -/* Setup the Flash Wait State */ -#if PMU_FLASH -temp = FLASH0->FCON; -temp &= ~FLASH_FCON_WSPFLASH_Msk; -temp |= PMU_FLASH_WS+3; -FLASH0->FCON = temp; -#endif - - -/* Setup the clockout */ -#if SCU_CLOCKOUT_SETUP - -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_SOURCE; -/*set PLL div for clkout */ -SCU_CLK->EXTCLKCR |= SCU_CLOCKOUT_DIV<<16; - -if (SCU_CLOCKOUT_PIN) { - PORT0->IOCR8 = 0x00000088; /*P0.8 --> ALT1 select + HWSEL */ - PORT0->HWSEL &= (~PORT0_HWSEL_HW8_Msk); - PORT0->PDR1 &= (~PORT0_PDR1_PD8_Msk); /*set to strong driver */ - } -else { - PORT1->IOCR12 = 0x88000000; /*P1.15--> ALT1 select */ - PORT1->PDR1 &= (~PORT1_PDR1_PD15_Msk); /*set to strong driver */ - } - -#endif - - -/* Setup the System clock */ -#if SCU_CLOCK_SETUP -SystemClockSetup(); -#endif - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -SystemCoreClockUpdate();/*!< System Clock Frequency (Core Clock)*/ - - -/* Setup the USB PL */ -#if SCU_USB_CLOCK_SETUP -USBClockSetup(); -#endif - - - -} - - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ -unsigned int PDIV; -unsigned int NDIV; -unsigned int K2DIV; -unsigned int long VCO; - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -if (SCU_CLK->SYSCLKCR == 0x00010000) -{ - if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk){ - /* check if PLL is locked */ - /* read back divider settings */ - PDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk)>>24)+1; - NDIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk)>>8)+1; - K2DIV = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk)>>16)+1; - - if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk){ - /* the selected clock is the Backup clock fofi */ - VCO = (CLOCK_BACK_UP/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - - } - else - { - /* the selected clock is the PLL external oscillator */ - VCO = (CLOCK_CRYSTAL_FREQUENCY/PDIV)*NDIV; - SystemCoreClock = VCO/K2DIV; - /* in case the sysclock div is used */ - SystemCoreClock = SystemCoreClock/((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk)+1); - } - - - } -} -else -{ -SystemCoreClock = CLOCK_BACK_UP; -} - - -} - - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_CLOCK_SETUP == 1) -static int SystemClockSetup(void) -{ -int temp; -unsigned int long VCO; -int stepping_K2DIV; - -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - -/* check if PLL is switched on */ -if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ -/* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - -} - -/* Enable OSC_HP if not already on*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL) - { - /********************************************************************************************************************/ - /* Use external crystal for PLL clock input */ - /********************************************************************************************************************/ - - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* select external OSC as PLL input */ - SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk; - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY) - { - /********************************************************************************************************************/ - /* Use factory trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - } - else if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) - { - /********************************************************************************************************************/ - /* Use automatic trimming Back-up clock for PLL clock input */ - /********************************************************************************************************************/ - /* check for HIB Domain enabled */ - if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0) - SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk; /*enable Hibernate domain*/ - - /* check for HIB Domain is not in reset state */ - if ((SCU_RESET->RSTSTAT & SCU_RESET_RSTSTAT_HIBRS_Msk)== 1) - SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk; /*de-assert hibernate reset*/ - - /* PLL Back up clock selected */ - SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk; - - if (SCU_STANDBY_CLOCK == HIB_CLOCK_FOSI) - { - /****************************************************************************************************************/ - /* Use fOSI as source of the standby clock */ - /****************************************************************************************************************/ - SCU_HIBERNATE->HDCR &= ~SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - } - else if (SCU_STANDBY_CLOCK == HIB_CLOCK_OSCULP) - { - /****************************************************************************************************************/ - /* Use fULP as source of the standby clock */ - /****************************************************************************************************************/ - /*check OSCUL if running correct*/ - if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk)!= 0) - { - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk); - - SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; /*enable OSCUL*/ - /*now ceck if the clock is OK using OSCULP Oscillator Watchdog (ULPWDG)*/ - /* select OSCUL clock for RTC*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*enable OSCULP WDG Alarm Enable*/ - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - /*wait now for clock is stable */ - do - { - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - for(temp=0;temp<=0xFFFF;temp++); - } - while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk)==SCU_HIBERNATE_HDSTAT_ULPWDG_Msk); - - SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk); - } - // now OSCULP is running and can be used - SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_STDBYSEL_Msk; - while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk); - - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FOTR_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk; - /*TRIAL for delay loop*/ - for(temp=0;temp<=0xFFFF;temp++); - - } - } - - /********************************************************************************************************************/ - /* Setup and look the main PLL */ - /********************************************************************************************************************/ - -if (!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)){ - /* Systen is still running from internal clock */ - /* select FOFI as system clock */ - if((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk) != 0x0)SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk; /*Select FOFI*/ - - - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/24000000)-1; - /* Go to bypass the Main PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk; - /* disconnect OSC_HP to PLL */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - /* we may have to set OSCDISCDIS */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - /* connect OSC_HP to PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk; - /* wait for PLL Lock */ - /* setup time out loop */ - /* Timeout for wait loo ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while ((!(SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk))&&(SysTick->VAL >= 500)); - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - - if ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)==SCU_PLL_PLLSTAT_VCOLOCK_Msk) - { - /* Go back to the Main PLL */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk; - } - else return(0); - - - /********************************************************* - here we need to setup the system clock divider - *********************************************************/ - - SCU_CLK->CPUCLKCR = SCU_CPUCLKCR_DIV; - SCU_CLK->PBCLKCR = SCU_PBCLKCR_DIV; - SCU_CLK->CCUCLKCR = SCU_CCUCLKCR_DIV; - - - /* Switch system clock to PLL */ - SCU_CLK->SYSCLKCR |= 0x00010000; - - /* we may have to reset OSCDISCDIS */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk; - - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((1250+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /*********************************************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 60MHz - *********************************************************/ - if (CLOCK_FSYS > 60000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/60000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((3000+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /********************************************************* - here the ramp up of the system clock starts FSys < 90MHz - *********************************************************/ - if (CLOCK_FSYS > 90000000){ - /*calulation for stepping*/ - if (SCU_PLL_CLOCK_INPUT == SCU_CLOCK_CRYSTAL)VCO = (CLOCK_CRYSTAL_FREQUENCY/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - if ((SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_AUTOMATIC) ||(SCU_PLL_CLOCK_INPUT == SCU_CLOCK_BACK_UP_FACTORY)) - VCO = (CLOCK_BACK_UP/(SCU_PLL_PDIV+1))*(SCU_PLL_NDIV+1); - - stepping_K2DIV = (VCO/90000000)-1; - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (stepping_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - } - else - { - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - return(1); - } - - /*********************************************************/ - /* Delay for next K2 step ~50µs */ - /*********************************************************/ - SysTick->LOAD = ((4800+100) & SysTick_LOAD_RELOAD_Msk) - 1; - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - - while (SysTick->VAL >= 100); /* wait for ~50µs */ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - /********************************/ - - /* Setup devider settings for main PLL */ - SCU_PLL->PLLCON1 = ((SCU_PLL_K1DIV) | (SCU_PLL_NDIV<<8) | (SCU_PLL_K2DIV<<16) | (SCU_PLL_PDIV<<24)); - - SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk; /* clear request for System OCS Watchdog Trap and System VCO Lock Trap */ - } - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - -/** - * @brief - - * @note - - * @param None - * @retval None - */ -#if (SCU_USB_CLOCK_SETUP == 1) -static int USBClockSetup(void) -{ -/* this weak function enables DAVE3 clock App usage */ -if(AllowPLLInitByStartup()){ - -/* check if PLL is switched on */ -if ((SCU_PLL->USBPLLCON &(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk); -} - -/* check and if not already running enable OSC_HP */ - if (SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk){ - /* check if Main PLL is switched on for OSC WD*/ - if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0){ - /* enable PLL first */ - SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk); - } - SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_HP_MODE); /*enable the OSC_HP*/ - /* setup OSC WDG devider */ - SCU_OSC->OSCHPCTRL |= (SCU_OSCHPWDGDIV<<16); - /* restart OSC Watchdog */ - SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk; - - /* Timeout for wait loop ~150ms */ - /********************************/ - SysTick->LOAD = ((5000000+100) & SysTick_LOAD_RELOAD_Msk) - 1;/* set reload register */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - do - { - ;/* wait for ~150ms */ - }while((((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380)&&(SysTick->VAL >= 500)); - - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; /* Stop SysTick Timer */ - if (((SCU_PLL->PLLSTAT) & (SCU_PLL_PLLSTAT_PLLHV_Msk | SCU_PLL_PLLSTAT_PLLLV_Msk |SCU_PLL_PLLSTAT_PLLSP_Msk)) != 0x380) - return(0);/* Return Error */ - - } - - -/* Setup USB PLL */ - /* Go to bypass the Main PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk; - /* disconnect OSC_FI to PLL */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk; - /* Setup devider settings for main PLL */ - SCU_PLL->USBPLLCON = ((SCU_USBPLL_NDIV<<8) | (SCU_USBPLL_PDIV<<24)); - /* Setup USBDIV settings USB clock */ - SCU_CLK->USBCLKCR = SCU_USBDIV; - /* we may have to set OSCDISCDIS */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk; - /* connect OSC_FI to PLL */ - SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk; - /* restart PLL Lock detection */ - SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk; - /* wait for PLL Lock */ - while (!(SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk)); - - }/* end this weak function enables DAVE3 clock App usage */ - return(1); - -} -#endif - diff --git a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.h b/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.h deleted file mode 100644 index 953e1b099..000000000 --- a/FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil/system_XMC4400.h +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************//** - * @file system_XMC4400.h - * @brief Header file for the XMC4400-Series systeminit - * - * @version V1.0 - * @date 17. August 2012 - * - * @note - * Copyright (C) 2011 Infineon Technologies AG. All rights reserved. - - * - * @par - * Infineon Technologies AG (Infineon) is supplying this software for use with Infineon’s microcontrollers. - * This file can be freely distributed within development tools that are supporting such microcontrollers. - - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - * - ******************************************************************************/ - - -#ifndef __SYSTEM_XMC4400_H -#define __SYSTEM_XMC4400_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -extern void SystemInit (void); - - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -/* this weak function enables DAVE3 clock App usage */ -extern uint32_t AllowPLLInitByStartup(void); - - - -#ifdef __cplusplus -} -#endif - - -#endif