From: Sumit Garg <sumit.garg@nxp.com>
Date: Tue, 3 Oct 2017 21:50:49 +0000 (+0530)
Subject: armv8: fsl-layerscape: Allocate Secure memory from first ddr region
X-Git-Tag: v2017.11-rc2~56^2~8
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=710d0cd79ede129d5203325c2a188c6f93c61ca3;p=u-boot

armv8: fsl-layerscape: Allocate Secure memory from first ddr region

This change is required due to trusted OS (OP-TEE) not being position
independent code, it requires compile time fixed base address.

To take care of this it is assumed that all layerscape armv8 platforms
has minimum 2G ddr in first region. So we can have fixed address
space (66 MB -> (2MB for PPA + 64MB for trusted OS)) allocated from
top of first 2G ddr region and compile trusted OS with this fixed
base address.

But one exception here is ls1012 where we have only 1G (rdb) or 512M
(frdm) ddr memory. For those we can have different fixed compile time
base addresses for trusted OS.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d21a49454e..b5ed28ab8f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -647,13 +647,14 @@ phys_size_t get_effective_memsize(void)
 
 	/*
 	 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
-	 * first region is 2GB space at 0x8000_0000. If the memory extends to
-	 * the second region (or the third region if applicable), the secure
-	 * memory and Management Complex (MC) memory should be put into the
-	 * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED
-	 * is set to the size of first region so U-Boot doesn't relocate itself
-	 * into higher address. Should DDR be configured to skip the first
-	 * region, this function needs to be adjusted.
+	 * first region is 2GB space at 0x8000_0000. Secure memory needs to
+	 * allocated from first region. If the memory extends to  the second
+	 * region (or the third region if applicable), Management Complex (MC)
+	 * memory should be put into the highest region, i.e. the end of DDR
+	 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
+	 * U-Boot doesn't relocate itself into higher address. Should DDR be
+	 * configured to skip the first region, this function needs to be
+	 * adjusted.
 	 */
 	if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
 		ea_size = CONFIG_MAX_MEM_MAPPED;
@@ -664,16 +665,10 @@ phys_size_t get_effective_memsize(void)
 
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	/* Check if we have enough space for secure memory */
-	if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) {
-		rem -= CONFIG_SYS_MEM_RESERVE_SECURE;
-	} else {
-		if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) {
-			ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
-			rem = 0;	/* Presume MC requires more memory */
-		} else {
-			printf("Error: No enough space for secure memory.\n");
-		}
-	}
+	if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
+		ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
+	else
+		printf("Error: No enough space for secure memory.\n");
 #endif
 	/* Check if we have enough memory for MC */
 	if (rem < board_reserve_ram_top(rem)) {
@@ -718,32 +713,14 @@ int dram_init_banksize(void)
 		gd->bd->bi_dram[0].size = gd->ram_size;
 	}
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
-#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
-	if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
-		gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE;
-		gd->arch.secure_ram = gd->bd->bi_dram[2].start +
-				      gd->bd->bi_dram[2].size;
+	if (gd->bd->bi_dram[0].size >
+				CONFIG_SYS_MEM_RESERVE_SECURE) {
+		gd->bd->bi_dram[0].size -=
+				CONFIG_SYS_MEM_RESERVE_SECURE;
+		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
+				      gd->bd->bi_dram[0].size;
 		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 		gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
-	} else
-#endif
-	{
-		if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
-			gd->bd->bi_dram[1].size -=
-					CONFIG_SYS_MEM_RESERVE_SECURE;
-			gd->arch.secure_ram = gd->bd->bi_dram[1].start +
-					      gd->bd->bi_dram[1].size;
-			gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-			gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
-		} else if (gd->bd->bi_dram[0].size >
-					CONFIG_SYS_MEM_RESERVE_SECURE) {
-			gd->bd->bi_dram[0].size -=
-					CONFIG_SYS_MEM_RESERVE_SECURE;
-			gd->arch.secure_ram = gd->bd->bi_dram[0].start +
-					      gd->bd->bi_dram[0].size;
-			gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
-			gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
-		}
 	}
 #endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */