From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 26 Feb 2016 05:21:46 +0000 (+0900)
Subject: ARM: uniphier: refactor UMC init code for PH1-LD4
X-Git-Tag: v2016.03-rc3~6^2~12
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=71d7ef35df49b94797ad6f32c23e23af4728b18d;p=u-boot

ARM: uniphier: refactor UMC init code for PH1-LD4

Move frequency-dependent register settings to arrays for clean-up.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
index bee3ef4bff..353ef6939e 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
@@ -13,6 +13,27 @@
 #include "ddrphy-regs.h"
 #include "umc-regs.h"
 
+enum dram_freq {
+	DRAM_FREQ_1333M,
+	DRAM_FREQ_1600M,
+	DRAM_FREQ_NR,
+};
+
+enum dram_size {
+	DRAM_SZ_128M,
+	DRAM_SZ_256M,
+	DRAM_SZ_NR,
+};
+
+static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17};
+static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24};
+static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+	{0x00240512, 0x00350512},
+	{0x002b0617, 0x003f0617},
+};
+static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
+static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};
+
 static void umc_start_ssif(void __iomem *ssif_base)
 {
 	writel(0x00000000, ssif_base + 0x0000b004);
@@ -47,35 +68,43 @@ static void umc_start_ssif(void __iomem *ssif_base)
 	writel(0x00000001, ssif_base + UMC_DMDRST);
 }
 
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
-			      int size, int freq)
+static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+			     int size, int freq)
 {
-	if (freq == 1333) {
-		writel(0x45990b11, dramcont + UMC_CMDCTLA);
-		writel(0x16958924, dramcont + UMC_CMDCTLB);
-	} else if (freq == 1600) {
-		writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
-		writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
+	enum dram_freq freq_e;
+	enum dram_size size_e;
+
+	switch (freq) {
+	case 1333:
+		freq_e = DRAM_FREQ_1333M;
+		break;
+	case 1600:
+		freq_e = DRAM_FREQ_1600M;
+		break;
+	default:
+		pr_err("unsupported DRAM frequency %d MHz\n", freq);
+		return -EINVAL;
 	}
 
-	if (freq == 1333) {
-		if (size == 1)
-			writel(0x00240512, dramcont + UMC_SPCCTLA);
-		else if (size == 2)
-			writel(0x00350512, dramcont + UMC_SPCCTLA);
-
-		writel(0x00ff0006, dramcont + UMC_SPCCTLB);
-		writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
-	} else if (freq == 1600) {
-		if (size == 1)
-			writel(0x002B0617, dramcont + UMC_SPCCTLA);
-		else if (size == 2)
-			writel(0x003F0617, dramcont + UMC_SPCCTLA);
-
-		writel(0x00ff0008, dramcont + UMC_SPCCTLB);
-		writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
+	switch (size) {
+	case 0:
+		return 0;
+	case 1:
+		size_e = DRAM_SZ_128M;
+		break;
+	case 2:
+		size_e = DRAM_SZ_256M;
+		break;
+	default:
+		pr_err("unsupported DRAM size\n");
+		return -EINVAL;
 	}
 
+	writel(umc_cmdctla_plus[freq_e], dramcont + UMC_CMDCTLA);
+	writel(umc_cmdctlb_plus[freq_e], dramcont + UMC_CMDCTLB);
+	writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA);
+	writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB);
+	writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0);
 	writel(0x04060806, dramcont + UMC_WDATACTL_D0);
 	writel(0x04a02000, dramcont + UMC_DATASET);
 	writel(0x00000000, ca_base + 0x2300);
@@ -94,6 +123,8 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
 	writel(0x200a0a00, dramcont + UMC_SPCSETB);
 	writel(0x00000000, dramcont + UMC_SPCSETD);
 	writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+
+	return 0;
 }
 
 static int umc_init_sub(int freq, int size_ch0, int size_ch1, bool ddr3plus)