From: Benoît Thébaudeau Date: Wed, 3 May 2017 09:59:06 +0000 (+0200) Subject: mx25pdk: Set the eSDHC PER clock to 48 MHz X-Git-Tag: v2017.07-rc3~29^2~15 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=747778cf69468daa1f35abb932e17032ddfe9c1a;p=u-boot mx25pdk: Set the eSDHC PER clock to 48 MHz The maximum SD clock frequency in High Speed mode is 50 MHz. This change makes it possible to get 48 MHz from the USB PLL (240 MHz / 5 / 1) instead of the previous 33.25 MHz from the AHB clock (133 MHz / 2 / 2). Signed-off-by: Benoît Thébaudeau Reviewed-by: Fabio Estevam --- diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c index 788d3c3e35..cab769cbd0 100644 --- a/board/freescale/mx25pdk/mx25pdk.c +++ b/board/freescale/mx25pdk/mx25pdk.c @@ -175,6 +175,12 @@ int board_mmc_init(bd_t *bis) imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); + /* + * Set the eSDHC1 PER clock to the maximum frequency lower than or equal + * to 50 MHz that can be obtained, which requires to use UPLL as the + * clock source. This actually gives 48 MHz. + */ + imx_set_perclk(MXC_ESDHC1_CLK, true, 50000000); esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); }