From: Kipisz, Steven Date: Thu, 29 Oct 2015 21:50:43 +0000 (-0500) Subject: board: ti: beagle_x15: Rename to indicate support for TI am57xx evms X-Git-Tag: v2016.01-rc2~290 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=74cc8b097d9aff8b8671396f66ece4cf2de0a36d;p=u-boot board: ti: beagle_x15: Rename to indicate support for TI am57xx evms BeagleBoard X15 (http://beagleboard.org/x15) support in u-boot does actually support two different platform configuration offered by TI. In addition to BeagleBoard X15, it also supports the TMDXEVM5728 (or more commonly known as AM5728-evm). Information about the TI AM57xx EVM can be found here http://www.ti.com/tool/tmdxevm5728 The EVM configuration is 1-1 compatible with BeagleBoard X15 with the additional support for mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's wlink8 offering. Hence, we rename the beagle_x15 directory to am57xx to support TI EVMs that use the AM57xx processor. By doing this we have common code reuse. This sets the stage to have a common u-boot image solution for multiple TI EVMs such as that already done for am335x and am437x. This sets the stage for upcoming multiple TI EVMs that share the same code base. NOTE: Commit eae7ae185335 ("am437x: Add am57xx_evm_defconfig using CONFIG_DM") introduced DT support for beagle_x15 under am57xx_evm platform name. However, this ignored the potential confusion arising for users as a result. To prevent this, existing beagle_x15_defconfig is renamed as am57xx_evm_nodt_defconfig to denote that this is the "non device tree" configuration for the same platform. We still retain am57xx-beagle-x15.dts at this point, since we just require the common minimum dts. As a result of this change, users should expect changes in build procedures('make am57xx_evm_nodt_defconfig' instead of 'make beagle_x15_defconfig'). Hopefully, this would be a one-time change. Signed-off-by: Steve Kipisz Signed-off-by: Schuyler Patton Acked-by: Nishanth Menon Acked-by: Lokesh Vutla --- diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 20c3bd963b..bfa264eccc 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -24,6 +24,6 @@ config SYS_SOC source "board/compulab/cm_t54/Kconfig" source "board/ti/omap5_uevm/Kconfig" source "board/ti/dra7xx/Kconfig" -source "board/ti/beagle_x15/Kconfig" +source "board/ti/am57xx/Kconfig" endif diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig new file mode 100644 index 0000000000..bdb779511b --- /dev/null +++ b/board/ti/am57xx/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BEAGLE_X15 + +config SYS_BOARD + default "am57xx" + +config SYS_VENDOR + default "ti" + +config SYS_CONFIG_NAME + default "am57xx_evm" + +endif diff --git a/board/ti/am57xx/MAINTAINERS b/board/ti/am57xx/MAINTAINERS new file mode 100644 index 0000000000..b8ae0199e3 --- /dev/null +++ b/board/ti/am57xx/MAINTAINERS @@ -0,0 +1,7 @@ +AM57XX EVM +M: Felipe Balbi +S: Maintained +F: board/ti/am57xx/ +F: include/configs/am57xx_evm.h +F: configs/am57xx_evm_defconfig +F: configs/am57xx_evm_nodt_defconfig diff --git a/board/ti/am57xx/Makefile b/board/ti/am57xx/Makefile new file mode 100644 index 0000000000..5cd6873f5e --- /dev/null +++ b/board/ti/am57xx/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Texas Instruments, +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := board.o diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c new file mode 100644 index 0000000000..042f9ab196 --- /dev/null +++ b/board/ti/am57xx/board.c @@ -0,0 +1,544 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mux_data.h" + +#ifdef CONFIG_DRIVER_TI_CPSW +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* GPIO 7_11 */ +#define GPIO_DDR_VTT_EN 203 + +const struct omap_sysinfo sysinfo = { + "Board: BeagleBoard x15\n" +}; + +static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { + .dmm_lisa_map_3 = 0x80740300, + .is_ma_present = 0x1 +}; + +void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{ + *dmm_lisa_regs = &beagle_x15_lisa_regs; +} + +static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xceef266b, + .sdram_tim2 = 0x328f7fda, + .sdram_tim3 = 0x027f88a8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00740074, + .emif_ddr_ext_phy_ctrl_3 = 0x00780078, + .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, + .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +/* Ext phy ctrl regs 1-35 */ +static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { + 0x10040100, + 0x00740074, + 0x00780078, + 0x007c007c, + 0x007b007b, + 0x00800080, + 0x00360036, + 0x00340034, + 0x00360036, + 0x00350035, + 0x00350035, + + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + + 0x00430043, + 0x003e003e, + 0x004a004a, + 0x00470047, + 0x00400040, + + 0x00000000, + 0x00600020, + 0x40011080, + 0x08102040, + + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 +}; + +static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { + .sdram_config_init = 0x61851b32, + .sdram_config = 0x61851b32, + .sdram_config2 = 0x00000000, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, + .sdram_tim1 = 0xceef266b, + .sdram_tim2 = 0x328f7fda, + .sdram_tim3 = 0x027f88a8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190b, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0024400b, + .emif_ddr_phy_ctlr_1 = 0x0e24400b, + .emif_ddr_ext_phy_ctrl_1 = 0x10040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00820082, + .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, + .emif_ddr_ext_phy_ctrl_4 = 0x00800080, + .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { + 0x10040100, + 0x00820082, + 0x008b008b, + 0x00800080, + 0x007e007e, + 0x00800080, + 0x00370037, + 0x00390039, + 0x00360036, + 0x00370037, + 0x00350035, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x01ff01ff, + 0x00540054, + 0x00540054, + 0x004e004e, + 0x004c004c, + 0x00400040, + + 0x00000000, + 0x00600020, + 0x40011080, + 0x08102040, + + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x00400040, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0 +}; + +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + switch (emif_nr) { + case 1: + *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; + break; + case 2: + *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; + break; + } +} + +void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) +{ + switch (emif_nr) { + case 1: + *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); + break; + case 2: + *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; + *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); + break; + } +} + +struct vcores_data beagle_x15_volts = { + .mpu.value = VDD_MPU_DRA752, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = TPS659038_REG_ADDR_SMPS12, + .mpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA752, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = TPS659038_REG_ADDR_SMPS45, + .eve.pmic = &tps659038, + + .gpu.value = VDD_GPU_DRA752, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = TPS659038_REG_ADDR_SMPS45, + .gpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA752, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = TPS659038_REG_ADDR_SMPS6, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA752, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = TPS659038_REG_ADDR_SMPS45, + .iva.pmic = &tps659038, +}; + +void hw_data_init(void) +{ + *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &beagle_x15_volts; + *ctrl = &dra7xx_ctrl; +} + +int board_init(void) +{ + gpmc_init(); + gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); + + return 0; +} + +int board_late_init(void) +{ + init_sata(0); + /* + * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds + * This is the POWERHOLD-in-Low behavior. + */ + palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); + return 0; +} + +void set_muxconf_regs_essential(void) +{ + do_set_mux32((*ctrl)->control_padconf_core_base, + early_padconf, ARRAY_SIZE(early_padconf)); +} + +#ifdef CONFIG_IODELAY_RECALIBRATION +void recalibrate_iodelay(void) +{ + __recalibrate_iodelay(core_padconf_array_essential, + ARRAY_SIZE(core_padconf_array_essential), + iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array)); +} +#endif + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0, 0, 0, -1, -1); + omap_mmc_init(1, 0, 0, -1, -1); + return 0; +} +#endif + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; +#endif + + return 0; +} +#endif + +#ifdef CONFIG_USB_DWC3 +static struct dwc3_device usb_otg_ss1 = { + .maximum_speed = USB_SPEED_SUPER, + .base = DRA7_USB_OTG_SS1_BASE, + .tx_fifo_resize = false, + .index = 0, +}; + +static struct dwc3_omap_device usb_otg_ss1_glue = { + .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, + .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, + .index = 0, +}; + +static struct ti_usb_phy_device usb_phy1_device = { + .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, + .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, + .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, + .index = 0, +}; + +static struct dwc3_device usb_otg_ss2 = { + .maximum_speed = USB_SPEED_HIGH, + .base = DRA7_USB_OTG_SS2_BASE, + .tx_fifo_resize = false, + .index = 1, +}; + +static struct dwc3_omap_device usb_otg_ss2_glue = { + .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, + .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, + .index = 1, +}; + +static struct ti_usb_phy_device usb_phy2_device = { + .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, + .index = 1, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + enable_usb_clocks(index); + switch (index) { + case 0: + if (init == USB_INIT_DEVICE) { + printf("port %d can't be used as device\n", index); + disable_usb_clocks(index); + return -EINVAL; + } else { + usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; + usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; + setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, + OTG_SS_CLKCTRL_MODULEMODE_HW | + OPTFCLKEN_REFCLK960M); + } + + ti_usb_phy_uboot_init(&usb_phy1_device); + dwc3_omap_uboot_init(&usb_otg_ss1_glue); + dwc3_uboot_init(&usb_otg_ss1); + break; + case 1: + if (init == USB_INIT_DEVICE) { + usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; + usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; + } else { + printf("port %d can't be used as host\n", index); + disable_usb_clocks(index); + return -EINVAL; + } + + ti_usb_phy_uboot_init(&usb_phy2_device); + dwc3_omap_uboot_init(&usb_otg_ss2_glue); + dwc3_uboot_init(&usb_otg_ss2); + break; + default: + printf("Invalid Controller Index\n"); + } + + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + switch (index) { + case 0: + case 1: + ti_usb_phy_uboot_exit(index); + dwc3_uboot_exit(index); + dwc3_omap_uboot_exit(index); + break; + default: + printf("Invalid Controller Index\n"); + } + disable_usb_clocks(index); + return 0; +} + +int usb_gadget_handle_interrupts(int index) +{ + u32 status; + + status = dwc3_omap_uboot_interrupt_status(index); + if (status) + dwc3_uboot_handle_interrupt(index); + + return 0; +} +#endif + +#ifdef CONFIG_DRIVER_TI_CPSW + +/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) + +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 1, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 2, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + uint32_t ctrl_val; + + /* try reading mac address from efuse */ + mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("ethaddr")) { + printf(" not set. Validating first E-fuse MAC\n"); + + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("ethaddr", mac_addr); + } + + mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); + mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); + mac_addr[0] = (mac_hi & 0xFF0000) >> 16; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = mac_hi & 0xFF; + mac_addr[3] = (mac_lo & 0xFF0000) >> 16; + mac_addr[4] = (mac_lo & 0xFF00) >> 8; + mac_addr[5] = mac_lo & 0xFF; + + if (!getenv("eth1addr")) { + if (is_valid_ethaddr(mac_addr)) + eth_setenv_enetaddr("eth1addr", mac_addr); + } + + ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); + ctrl_val |= 0x22; + writel(ctrl_val, (*ctrl)->control_core_control_io1); + + ret = cpsw_register(&cpsw_data); + if (ret < 0) + printf("Error %d registering CPSW switch\n", ret); + + return ret; +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +/* VTT regulator enable */ +static inline void vtt_regulator_enable(void) +{ + if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) + return; + + gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); + gpio_direction_output(GPIO_DDR_VTT_EN, 1); +} + +int board_early_init_f(void) +{ + vtt_regulator_enable(); + return 0; +} +#endif diff --git a/board/ti/am57xx/mux_data.h b/board/ti/am57xx/mux_data.h new file mode 100644 index 0000000000..23f22a02be --- /dev/null +++ b/board/ti/am57xx/mux_data.h @@ -0,0 +1,330 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Felipe Balbi + * + * Based on board/ti/dra7xx/evm.c + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _MUX_DATA_BEAGLE_X15_H_ +#define _MUX_DATA_BEAGLE_X15_H_ + +#include + +const struct pad_conf_entry core_padconf_array_essential[] = { + {GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */ + {GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */ + {GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */ + {GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */ + {GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */ + {GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */ + {GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */ + {GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */ + {GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */ + {GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */ + {GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */ + {GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */ + {GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */ + {GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */ + {GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */ + {GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */ + {GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */ + {GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */ + {GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */ + {GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin3a_d19 */ + {GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin3a_d20 */ + {GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vin3a_d21 */ + {GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin3a_d22 */ + {GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin3a_d23 */ + {GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vin3a_hsync0 */ + {GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin3a_vsync0 */ + {GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin3a_de0 */ + {GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin3a_fld0 */ + {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */ + {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */ + {GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */ + {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */ + {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */ + {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */ + {GPMC_A18, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a18.gpio2_8 */ + {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ + {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ + {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ + {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ + {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ + {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ + {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ + {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ + {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ + {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ + {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */ + {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */ + {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.vin3a_clk0 */ + {GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */ + {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */ + {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */ + {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */ + {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */ + {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */ + {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */ + {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */ + {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */ + {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */ + {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */ + {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */ + {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */ + {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */ + {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */ + {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */ + {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d11.gpio3_15 */ + {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */ + {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */ + {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */ + {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */ + {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */ + {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d21.vin1a_d21 */ + {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */ + {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */ + {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */ + {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */ + {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */ + {VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */ + {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */ + {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */ + {VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */ + {VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */ + {VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */ + {VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */ + {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */ + {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */ + {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */ + {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */ + {VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */ + {VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */ + {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ + {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ + {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ + {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ + {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ + {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ + {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ + {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ + {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ + {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ + {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ + {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ + {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */ + {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */ + {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */ + {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */ + {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */ + {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */ + {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */ + {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */ + {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */ + {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */ + {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */ + {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */ + {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */ + {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */ + {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */ + {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */ + {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */ + {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */ + {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */ + {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */ + {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */ + {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */ + {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */ + {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */ + {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */ + {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */ + {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */ + {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */ + {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */ + {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */ + {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */ + {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */ + {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */ + {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */ + {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ + {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ + {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ + {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ + {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ + {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ + {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ + {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ + {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ + {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ + {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ + {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ + {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ + {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ + {GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */ + {GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */ + {GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */ + {XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.clkout2 */ + {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */ + {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */ + {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */ + {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */ + {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */ + {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */ + {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */ + {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */ + {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */ + {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ + {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ + {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ + {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ + {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ + {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ + {MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.gpio5_10 */ + {MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.gpio5_11 */ + {MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.gpio5_12 */ + {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */ + {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.mcasp7_axr0 */ + {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */ + {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.mcasp7_aclkx */ + {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.mcasp7_fsx */ + {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */ + {MCASP2_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.mcasp2_fsx */ + {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ + {MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */ + {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */ + {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */ + {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.mcasp2_axr2 */ + {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.mcasp2_axr3 */ + {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */ + {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */ + {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */ + {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.mcasp2_axr7 */ + {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ + {MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */ + {MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */ + {MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */ + {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.uart8_rxd */ + {MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */ + {MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */ + {MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */ + {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.uart9_rxd */ + {MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */ + {MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */ + {MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */ + {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ + {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ + {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ + {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ + {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ + {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ + {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.mmc1_sdcd */ + {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */ + {GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */ + {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ + {MMC3_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_clk.mmc3_clk */ + {MMC3_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.mmc3_cmd */ + {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.mmc3_dat0 */ + {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.mmc3_dat1 */ + {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.mmc3_dat2 */ + {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.mmc3_dat3 */ + {MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */ + {MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */ + {MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */ + {MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */ + {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */ + {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */ + {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */ + {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ + {SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */ + {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ + {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ + {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */ + {SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */ + {SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */ + {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */ + {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ + {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */ + {UART1_RXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_rxd.uart1_rxd */ + {UART1_TXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_txd.uart1_txd */ + {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.Driveroff */ + {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* N/A.Driveroff */ + {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.Driveroff */ + {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */ + {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ + {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ + {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ + {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */ + {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */ + {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */ + {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */ + {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */ + {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */ + {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */ +}; + +const struct pad_conf_entry early_padconf[] = { + {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */ + {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ + {I2C1_SDA, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SCL */ +}; + +#ifdef CONFIG_IODELAY_RECALIBRATION +const struct iodelay_cfg_entry iodelay_cfg_array[] = { + {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */ + {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */ + {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */ + {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */ + {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */ + {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */ + {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */ + {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */ + {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */ + {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */ + {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */ + {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */ + {0x0264, 2466, 0}, /* CFG_GPMC_AD0_IN */ + {0x0270, 2523, 0}, /* CFG_GPMC_AD10_IN */ + {0x027C, 2453, 0}, /* CFG_GPMC_AD11_IN */ + {0x0288, 2285, 0}, /* CFG_GPMC_AD12_IN */ + {0x0294, 2206, 0}, /* CFG_GPMC_AD13_IN */ + {0x02A0, 1898, 0}, /* CFG_GPMC_AD14_IN */ + {0x02AC, 2473, 0}, /* CFG_GPMC_AD15_IN */ + {0x02B8, 2307, 0}, /* CFG_GPMC_AD1_IN */ + {0x02C4, 2691, 0}, /* CFG_GPMC_AD2_IN */ + {0x02D0, 2384, 0}, /* CFG_GPMC_AD3_IN */ + {0x02DC, 2462, 0}, /* CFG_GPMC_AD4_IN */ + {0x02E8, 2335, 0}, /* CFG_GPMC_AD5_IN */ + {0x02F4, 2370, 0}, /* CFG_GPMC_AD6_IN */ + {0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */ + {0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */ + {0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */ + {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ + {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ + {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ + {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */ + {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */ + {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */ + {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */ + {0x074C, 11, 60}, /* CFG_RGMII0_TXCTL_OUT */ + {0x0758, 7, 120}, /* CFG_RGMII0_TXD0_OUT */ + {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */ + {0x0770, 276, 120}, /* CFG_RGMII0_TXD2_OUT */ + {0x077C, 440, 120}, /* CFG_RGMII0_TXD3_OUT */ + {0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */ + {0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */ + {0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */ + {0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */ + {0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */ + {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ + {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */ + {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */ + {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ + {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ + {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ + {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ +}; +#endif +#endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig deleted file mode 100644 index a305ff1044..0000000000 --- a/board/ti/beagle_x15/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_BEAGLE_X15 - -config SYS_BOARD - default "beagle_x15" - -config SYS_VENDOR - default "ti" - -config SYS_CONFIG_NAME - default "beagle_x15" - -endif diff --git a/board/ti/beagle_x15/MAINTAINERS b/board/ti/beagle_x15/MAINTAINERS deleted file mode 100644 index 3f84defcee..0000000000 --- a/board/ti/beagle_x15/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BEAGLE X15 -M: Felipe Balbi -S: Maintained -F: board/ti/beagle_x15/ -F: include/configs/beagle_x15.h -F: configs/beagle_x15_defconfig diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile deleted file mode 100644 index 5cd6873f5e..0000000000 --- a/board/ti/beagle_x15/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2014 -# Texas Instruments, -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := board.o diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c deleted file mode 100644 index 042f9ab196..0000000000 --- a/board/ti/beagle_x15/board.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com - * - * Author: Felipe Balbi - * - * Based on board/ti/dra7xx/evm.c - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "mux_data.h" - -#ifdef CONFIG_DRIVER_TI_CPSW -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* GPIO 7_11 */ -#define GPIO_DDR_VTT_EN 203 - -const struct omap_sysinfo sysinfo = { - "Board: BeagleBoard x15\n" -}; - -static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = { - .dmm_lisa_map_3 = 0x80740300, - .is_ma_present = 0x1 -}; - -void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) -{ - *dmm_lisa_regs = &beagle_x15_lisa_regs; -} - -static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { - .sdram_config_init = 0x61851b32, - .sdram_config = 0x61851b32, - .sdram_config2 = 0x00000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xceef266b, - .sdram_tim2 = 0x328f7fda, - .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190b, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400b, - .emif_ddr_phy_ctlr_1 = 0x0e24400b, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00740074, - .emif_ddr_ext_phy_ctrl_3 = 0x00780078, - .emif_ddr_ext_phy_ctrl_4 = 0x007c007c, - .emif_ddr_ext_phy_ctrl_5 = 0x007b007b, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - -/* Ext phy ctrl regs 1-35 */ -static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = { - 0x10040100, - 0x00740074, - 0x00780078, - 0x007c007c, - 0x007b007b, - 0x00800080, - 0x00360036, - 0x00340034, - 0x00360036, - 0x00350035, - 0x00350035, - - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - - 0x00430043, - 0x003e003e, - 0x004a004a, - 0x00470047, - 0x00400040, - - 0x00000000, - 0x00600020, - 0x40011080, - 0x08102040, - - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0 -}; - -static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { - .sdram_config_init = 0x61851b32, - .sdram_config = 0x61851b32, - .sdram_config2 = 0x00000000, - .ref_ctrl = 0x000040F1, - .ref_ctrl_final = 0x00001035, - .sdram_tim1 = 0xceef266b, - .sdram_tim2 = 0x328f7fda, - .sdram_tim3 = 0x027f88a8, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x0007190b, - .temp_alert_config = 0x00000000, - .emif_ddr_phy_ctlr_1_init = 0x0024400b, - .emif_ddr_phy_ctlr_1 = 0x0e24400b, - .emif_ddr_ext_phy_ctrl_1 = 0x10040100, - .emif_ddr_ext_phy_ctrl_2 = 0x00820082, - .emif_ddr_ext_phy_ctrl_3 = 0x008b008b, - .emif_ddr_ext_phy_ctrl_4 = 0x00800080, - .emif_ddr_ext_phy_ctrl_5 = 0x007e007e, - .emif_rd_wr_lvl_rmp_win = 0x00000000, - .emif_rd_wr_lvl_rmp_ctl = 0x80000000, - .emif_rd_wr_lvl_ctl = 0x00000000, - .emif_rd_wr_exec_thresh = 0x00000305 -}; - -static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = { - 0x10040100, - 0x00820082, - 0x008b008b, - 0x00800080, - 0x007e007e, - 0x00800080, - 0x00370037, - 0x00390039, - 0x00360036, - 0x00370037, - 0x00350035, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x01ff01ff, - 0x00540054, - 0x00540054, - 0x004e004e, - 0x004c004c, - 0x00400040, - - 0x00000000, - 0x00600020, - 0x40011080, - 0x08102040, - - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x00400040, - 0x0, - 0x0, - 0x0, - 0x0, - 0x0 -}; - -void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) -{ - switch (emif_nr) { - case 1: - *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs; - break; - case 2: - *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs; - break; - } -} - -void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) -{ - switch (emif_nr) { - case 1: - *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs; - *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs); - break; - case 2: - *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs; - *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs); - break; - } -} - -struct vcores_data beagle_x15_volts = { - .mpu.value = VDD_MPU_DRA752, - .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, - .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .mpu.addr = TPS659038_REG_ADDR_SMPS12, - .mpu.pmic = &tps659038, - - .eve.value = VDD_EVE_DRA752, - .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, - .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .eve.addr = TPS659038_REG_ADDR_SMPS45, - .eve.pmic = &tps659038, - - .gpu.value = VDD_GPU_DRA752, - .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, - .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .gpu.addr = TPS659038_REG_ADDR_SMPS45, - .gpu.pmic = &tps659038, - - .core.value = VDD_CORE_DRA752, - .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, - .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .core.addr = TPS659038_REG_ADDR_SMPS6, - .core.pmic = &tps659038, - - .iva.value = VDD_IVA_DRA752, - .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, - .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, - .iva.addr = TPS659038_REG_ADDR_SMPS45, - .iva.pmic = &tps659038, -}; - -void hw_data_init(void) -{ - *prcm = &dra7xx_prcm; - *dplls_data = &dra7xx_dplls; - *omap_vcores = &beagle_x15_volts; - *ctrl = &dra7xx_ctrl; -} - -int board_init(void) -{ - gpmc_init(); - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); - - return 0; -} - -int board_late_init(void) -{ - init_sata(0); - /* - * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds - * This is the POWERHOLD-in-Low behavior. - */ - palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1); - return 0; -} - -void set_muxconf_regs_essential(void) -{ - do_set_mux32((*ctrl)->control_padconf_core_base, - early_padconf, ARRAY_SIZE(early_padconf)); -} - -#ifdef CONFIG_IODELAY_RECALIBRATION -void recalibrate_iodelay(void) -{ - __recalibrate_iodelay(core_padconf_array_essential, - ARRAY_SIZE(core_padconf_array_essential), - iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array)); -} -#endif - -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) -int board_mmc_init(bd_t *bis) -{ - omap_mmc_init(0, 0, 0, -1, -1); - omap_mmc_init(1, 0, 0, -1, -1); - return 0; -} -#endif - -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) -int spl_start_uboot(void) -{ - /* break into full u-boot on 'c' */ - if (serial_tstc() && serial_getc() == 'c') - return 1; - -#ifdef CONFIG_SPL_ENV_SUPPORT - env_init(); - env_relocate_spec(); - if (getenv_yesno("boot_os") != 1) - return 1; -#endif - - return 0; -} -#endif - -#ifdef CONFIG_USB_DWC3 -static struct dwc3_device usb_otg_ss1 = { - .maximum_speed = USB_SPEED_SUPER, - .base = DRA7_USB_OTG_SS1_BASE, - .tx_fifo_resize = false, - .index = 0, -}; - -static struct dwc3_omap_device usb_otg_ss1_glue = { - .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, - .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, - .index = 0, -}; - -static struct ti_usb_phy_device usb_phy1_device = { - .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, - .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, - .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, - .index = 0, -}; - -static struct dwc3_device usb_otg_ss2 = { - .maximum_speed = USB_SPEED_HIGH, - .base = DRA7_USB_OTG_SS2_BASE, - .tx_fifo_resize = false, - .index = 1, -}; - -static struct dwc3_omap_device usb_otg_ss2_glue = { - .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, - .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, - .index = 1, -}; - -static struct ti_usb_phy_device usb_phy2_device = { - .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, - .index = 1, -}; - -int board_usb_init(int index, enum usb_init_type init) -{ - enable_usb_clocks(index); - switch (index) { - case 0: - if (init == USB_INIT_DEVICE) { - printf("port %d can't be used as device\n", index); - disable_usb_clocks(index); - return -EINVAL; - } else { - usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; - usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; - setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, - OTG_SS_CLKCTRL_MODULEMODE_HW | - OPTFCLKEN_REFCLK960M); - } - - ti_usb_phy_uboot_init(&usb_phy1_device); - dwc3_omap_uboot_init(&usb_otg_ss1_glue); - dwc3_uboot_init(&usb_otg_ss1); - break; - case 1: - if (init == USB_INIT_DEVICE) { - usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; - usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; - } else { - printf("port %d can't be used as host\n", index); - disable_usb_clocks(index); - return -EINVAL; - } - - ti_usb_phy_uboot_init(&usb_phy2_device); - dwc3_omap_uboot_init(&usb_otg_ss2_glue); - dwc3_uboot_init(&usb_otg_ss2); - break; - default: - printf("Invalid Controller Index\n"); - } - - return 0; -} - -int board_usb_cleanup(int index, enum usb_init_type init) -{ - switch (index) { - case 0: - case 1: - ti_usb_phy_uboot_exit(index); - dwc3_uboot_exit(index); - dwc3_omap_uboot_exit(index); - break; - default: - printf("Invalid Controller Index\n"); - } - disable_usb_clocks(index); - return 0; -} - -int usb_gadget_handle_interrupts(int index) -{ - u32 status; - - status = dwc3_omap_uboot_interrupt_status(index); - if (status) - dwc3_uboot_handle_interrupt(index); - - return 0; -} -#endif - -#ifdef CONFIG_DRIVER_TI_CPSW - -/* Delay value to add to calibrated value */ -#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) -#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) -#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) -#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) -#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) -#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) -#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) -#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) -#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) -#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) - -static void cpsw_control(int enabled) -{ - /* VTP can be added here */ -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 1, - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_addr = 2, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 1, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -int board_eth_init(bd_t *bis) -{ - int ret; - uint8_t mac_addr[6]; - uint32_t mac_hi, mac_lo; - uint32_t ctrl_val; - - /* try reading mac address from efuse */ - mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); - mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); - mac_addr[0] = (mac_hi & 0xFF0000) >> 16; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = mac_hi & 0xFF; - mac_addr[3] = (mac_lo & 0xFF0000) >> 16; - mac_addr[4] = (mac_lo & 0xFF00) >> 8; - mac_addr[5] = mac_lo & 0xFF; - - if (!getenv("ethaddr")) { - printf(" not set. Validating first E-fuse MAC\n"); - - if (is_valid_ethaddr(mac_addr)) - eth_setenv_enetaddr("ethaddr", mac_addr); - } - - mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); - mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); - mac_addr[0] = (mac_hi & 0xFF0000) >> 16; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = mac_hi & 0xFF; - mac_addr[3] = (mac_lo & 0xFF0000) >> 16; - mac_addr[4] = (mac_lo & 0xFF00) >> 8; - mac_addr[5] = mac_lo & 0xFF; - - if (!getenv("eth1addr")) { - if (is_valid_ethaddr(mac_addr)) - eth_setenv_enetaddr("eth1addr", mac_addr); - } - - ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); - ctrl_val |= 0x22; - writel(ctrl_val, (*ctrl)->control_core_control_io1); - - ret = cpsw_register(&cpsw_data); - if (ret < 0) - printf("Error %d registering CPSW switch\n", ret); - - return ret; -} -#endif - -#ifdef CONFIG_BOARD_EARLY_INIT_F -/* VTT regulator enable */ -static inline void vtt_regulator_enable(void) -{ - if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) - return; - - gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); - gpio_direction_output(GPIO_DDR_VTT_EN, 1); -} - -int board_early_init_f(void) -{ - vtt_regulator_enable(); - return 0; -} -#endif diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h deleted file mode 100644 index 23f22a02be..0000000000 --- a/board/ti/beagle_x15/mux_data.h +++ /dev/null @@ -1,330 +0,0 @@ -/* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com - * - * Author: Felipe Balbi - * - * Based on board/ti/dra7xx/evm.c - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _MUX_DATA_BEAGLE_X15_H_ -#define _MUX_DATA_BEAGLE_X15_H_ - -#include - -const struct pad_conf_entry core_padconf_array_essential[] = { - {GPMC_AD0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad0.vin3a_d0 */ - {GPMC_AD1, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad1.vin3a_d1 */ - {GPMC_AD2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad2.vin3a_d2 */ - {GPMC_AD3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad3.vin3a_d3 */ - {GPMC_AD4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad4.vin3a_d4 */ - {GPMC_AD5, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad5.vin3a_d5 */ - {GPMC_AD6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad6.vin3a_d6 */ - {GPMC_AD7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad7.vin3a_d7 */ - {GPMC_AD8, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad8.vin3a_d8 */ - {GPMC_AD9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad9.vin3a_d9 */ - {GPMC_AD10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad10.vin3a_d10 */ - {GPMC_AD11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad11.vin3a_d11 */ - {GPMC_AD12, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad12.vin3a_d12 */ - {GPMC_AD13, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad13.vin3a_d13 */ - {GPMC_AD14, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_ad14.vin3a_d14 */ - {GPMC_AD15, (M2 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* gpmc_ad15.vin3a_d15 */ - {GPMC_A0, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a0.vin3a_d16 */ - {GPMC_A1, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a1.vin3a_d17 */ - {GPMC_A2, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a2.vin3a_d18 */ - {GPMC_A3, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a3.vin3a_d19 */ - {GPMC_A4, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a4.vin3a_d20 */ - {GPMC_A5, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a5.vin3a_d21 */ - {GPMC_A6, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a6.vin3a_d22 */ - {GPMC_A7, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a7.vin3a_d23 */ - {GPMC_A8, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a8.vin3a_hsync0 */ - {GPMC_A9, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a9.vin3a_vsync0 */ - {GPMC_A10, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a10.vin3a_de0 */ - {GPMC_A11, (M2 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a11.vin3a_fld0 */ - {GPMC_A12, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a12.gpio2_2 */ - {GPMC_A13, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a13.gpio2_3 */ - {GPMC_A14, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a14.gpio2_4 */ - {GPMC_A15, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a15.gpio2_5 */ - {GPMC_A16, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a16.gpio2_6 */ - {GPMC_A17, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_a17.gpio2_7 */ - {GPMC_A18, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_a18.gpio2_8 */ - {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */ - {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */ - {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */ - {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */ - {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */ - {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */ - {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */ - {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */ - {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */ - {GPMC_CS1, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_cs1.mmc2_cmd */ - {GPMC_CS0, (M14 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs0.gpio2_19 */ - {GPMC_CS2, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_cs2.gpio2_20 */ - {GPMC_CS3, (M2 | PIN_INPUT_PULLDOWN)}, /* gpmc_cs3.vin3a_clk0 */ - {GPMC_CLK, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_clk.dma_evt1 */ - {GPMC_ADVN_ALE, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_advn_ale.gpio2_23 */ - {GPMC_OEN_REN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_oen_ren.gpio2_24 */ - {GPMC_WEN, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wen.gpio2_25 */ - {GPMC_BEN0, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben0.dma_evt3 */ - {GPMC_BEN1, (M9 | PIN_INPUT_PULLDOWN)}, /* gpmc_ben1.dma_evt4 */ - {GPMC_WAIT0, (M14 | PIN_INPUT_PULLUP)}, /* gpmc_wait0.gpio2_28 */ - {VIN1B_CLK1, (M14 | PIN_INPUT_SLEW)}, /* vin1b_clk1.gpio2_31 */ - {VIN1A_D2, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d2.gpio3_6 */ - {VIN1A_D3, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d3.gpio3_7 */ - {VIN1A_D4, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d4.gpio3_8 */ - {VIN1A_D5, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d5.gpio3_9 */ - {VIN1A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d6.gpio3_10 */ - {VIN1A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d7.gpio3_11 */ - {VIN1A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d8.gpio3_12 */ - {VIN1A_D10, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d10.gpio3_14 */ - {VIN1A_D11, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d11.gpio3_15 */ - {VIN1A_D12, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d12.gpio3_16 */ - {VIN1A_D14, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d14.gpio3_18 */ - {VIN1A_D16, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d16.gpio3_20 */ - {VIN1A_D19, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d19.gpio3_23 */ - {VIN1A_D20, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d20.gpio3_24 */ - {VIN1A_D21, (M0 | PIN_INPUT_PULLDOWN)}, /* vin1a_d21.vin1a_d21 */ - {VIN1A_D22, (M14 | PIN_INPUT_PULLDOWN)}, /* vin1a_d22.gpio3_26 */ - {VIN2A_CLK0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_clk0.gpio3_28 */ - {VIN2A_DE0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_de0.gpio3_29 */ - {VIN2A_FLD0, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_fld0.gpio3_30 */ - {VIN2A_HSYNC0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_hsync0.pr1_uart0_cts_n */ - {VIN2A_VSYNC0, (M11 | PIN_INPUT_PULLUP)}, /* vin2a_vsync0.pr1_uart0_rts_n */ - {VIN2A_D0, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d0.pr1_uart0_rxd */ - {VIN2A_D1, (M11 | PIN_INPUT_PULLDOWN)}, /* vin2a_d1.pr1_uart0_txd */ - {VIN2A_D2, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d2.uart10_rxd */ - {VIN2A_D3, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d3.uart10_txd */ - {VIN2A_D4, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d4.uart10_ctsn */ - {VIN2A_D5, (M8 | PIN_INPUT_PULLDOWN)}, /* vin2a_d5.uart10_rtsn */ - {VIN2A_D6, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d6.gpio4_7 */ - {VIN2A_D7, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d7.gpio4_8 */ - {VIN2A_D8, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d8.gpio4_9 */ - {VIN2A_D9, (M14 | PIN_INPUT_PULLDOWN)}, /* vin2a_d9.gpio4_10 */ - {VIN2A_D10, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d10.ehrpwm2B */ - {VIN2A_D11, (M10 | PIN_INPUT_PULLDOWN)}, /* vin2a_d11.ehrpwm2_tripzone_input */ - {VIN2A_D12, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d12.rgmii1_txc */ - {VIN2A_D13, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d13.rgmii1_txctl */ - {VIN2A_D14, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d14.rgmii1_txd3 */ - {VIN2A_D15, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d15.rgmii1_txd2 */ - {VIN2A_D16, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d16.rgmii1_txd1 */ - {VIN2A_D17, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d17.rgmii1_txd0 */ - {VIN2A_D18, (M3 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* vin2a_d18.rgmii1_rxc */ - {VIN2A_D19, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d19.rgmii1_rxctl */ - {VIN2A_D20, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d20.rgmii1_rxd3 */ - {VIN2A_D21, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d21.rgmii1_rxd2 */ - {VIN2A_D22, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d22.rgmii1_rxd1 */ - {VIN2A_D23, (M3 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* vin2a_d23.rgmii1_rxd0 */ - {VOUT1_CLK, (M0 | PIN_OUTPUT)}, /* vout1_clk.vout1_clk */ - {VOUT1_DE, (M0 | PIN_OUTPUT)}, /* vout1_de.vout1_de */ - {VOUT1_FLD, (M14 | PIN_INPUT)}, /* vout1_fld.gpio4_21 */ - {VOUT1_HSYNC, (M0 | PIN_OUTPUT)}, /* vout1_hsync.vout1_hsync */ - {VOUT1_VSYNC, (M0 | PIN_OUTPUT)}, /* vout1_vsync.vout1_vsync */ - {VOUT1_D0, (M0 | PIN_OUTPUT)}, /* vout1_d0.vout1_d0 */ - {VOUT1_D1, (M0 | PIN_OUTPUT)}, /* vout1_d1.vout1_d1 */ - {VOUT1_D2, (M0 | PIN_OUTPUT)}, /* vout1_d2.vout1_d2 */ - {VOUT1_D3, (M0 | PIN_OUTPUT)}, /* vout1_d3.vout1_d3 */ - {VOUT1_D4, (M0 | PIN_OUTPUT)}, /* vout1_d4.vout1_d4 */ - {VOUT1_D5, (M0 | PIN_OUTPUT)}, /* vout1_d5.vout1_d5 */ - {VOUT1_D6, (M0 | PIN_OUTPUT)}, /* vout1_d6.vout1_d6 */ - {VOUT1_D7, (M0 | PIN_OUTPUT)}, /* vout1_d7.vout1_d7 */ - {VOUT1_D8, (M0 | PIN_OUTPUT)}, /* vout1_d8.vout1_d8 */ - {VOUT1_D9, (M0 | PIN_OUTPUT)}, /* vout1_d9.vout1_d9 */ - {VOUT1_D10, (M0 | PIN_OUTPUT)}, /* vout1_d10.vout1_d10 */ - {VOUT1_D11, (M0 | PIN_OUTPUT)}, /* vout1_d11.vout1_d11 */ - {VOUT1_D12, (M0 | PIN_OUTPUT)}, /* vout1_d12.vout1_d12 */ - {VOUT1_D13, (M0 | PIN_OUTPUT)}, /* vout1_d13.vout1_d13 */ - {VOUT1_D14, (M0 | PIN_OUTPUT)}, /* vout1_d14.vout1_d14 */ - {VOUT1_D15, (M0 | PIN_OUTPUT)}, /* vout1_d15.vout1_d15 */ - {VOUT1_D16, (M0 | PIN_OUTPUT)}, /* vout1_d16.vout1_d16 */ - {VOUT1_D17, (M0 | PIN_OUTPUT)}, /* vout1_d17.vout1_d17 */ - {VOUT1_D18, (M0 | PIN_OUTPUT)}, /* vout1_d18.vout1_d18 */ - {VOUT1_D19, (M0 | PIN_OUTPUT)}, /* vout1_d19.vout1_d19 */ - {VOUT1_D20, (M0 | PIN_OUTPUT)}, /* vout1_d20.vout1_d20 */ - {VOUT1_D21, (M0 | PIN_OUTPUT)}, /* vout1_d21.vout1_d21 */ - {VOUT1_D22, (M0 | PIN_OUTPUT)}, /* vout1_d22.vout1_d22 */ - {VOUT1_D23, (M0 | PIN_OUTPUT)}, /* vout1_d23.vout1_d23 */ - {MDIO_MCLK, (M0 | PIN_INPUT_PULLUP)}, /* mdio_mclk.mdio_mclk */ - {MDIO_D, (M0 | PIN_INPUT_PULLUP)}, /* mdio_d.mdio_d */ - {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)}, /* RMII_MHZ_50_CLK.gpio5_17 */ - {UART3_RXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_rxd.gpio5_18 */ - {UART3_TXD, (M14 | PIN_INPUT_PULLDOWN)}, /* uart3_txd.gpio5_19 */ - {RGMII0_TXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txc.rgmii0_txc */ - {RGMII0_TXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txctl.rgmii0_txctl */ - {RGMII0_TXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd3.rgmii0_txd3 */ - {RGMII0_TXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd2.rgmii0_txd2 */ - {RGMII0_TXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd1.rgmii0_txd1 */ - {RGMII0_TXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_txd0.rgmii0_txd0 */ - {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxc.rgmii0_rxc */ - {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxctl.rgmii0_rxctl */ - {RGMII0_RXD3, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */ - {RGMII0_RXD2, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */ - {RGMII0_RXD1, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */ - {RGMII0_RXD0, (M0 | PIN_INPUT_PULLUP | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */ - {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb1_drvvbus.usb1_drvvbus */ - {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)}, /* usb2_drvvbus.usb2_drvvbus */ - {GPIO6_14, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_14.timer1 */ - {GPIO6_15, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_15.timer2 */ - {GPIO6_16, (M10 | PIN_INPUT_PULLUP)}, /* gpio6_16.timer3 */ - {XREF_CLK0, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk0.clkout2 */ - {XREF_CLK1, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.gpio6_18 */ - {XREF_CLK2, (M14 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.gpio6_19 */ - {XREF_CLK3, (M9 | PIN_INPUT_PULLDOWN)}, /* xref_clk3.clkout3 */ - {MCASP1_ACLKX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkx.i2c3_sda */ - {MCASP1_FSX, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsx.i2c3_scl */ - {MCASP1_ACLKR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_aclkr.i2c4_sda */ - {MCASP1_FSR, (M10 | PIN_INPUT_PULLUP)}, /* mcasp1_fsr.i2c4_scl */ - {MCASP1_AXR0, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr0.i2c5_sda */ - {MCASP1_AXR1, (M10 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr1.i2c5_scl */ - {MCASP1_AXR2, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr2.gpio5_4 */ - {MCASP1_AXR3, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr3.gpio5_5 */ - {MCASP1_AXR4, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr4.gpio5_6 */ - {MCASP1_AXR5, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr5.gpio5_7 */ - {MCASP1_AXR6, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr6.gpio5_8 */ - {MCASP1_AXR7, (M14 | PIN_INPUT_PULLDOWN)}, /* mcasp1_axr7.gpio5_9 */ - {MCASP1_AXR8, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr8.gpio5_10 */ - {MCASP1_AXR9, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr9.gpio5_11 */ - {MCASP1_AXR10, (M14 | PIN_INPUT_SLEW)}, /* mcasp1_axr10.gpio5_12 */ - {MCASP1_AXR11, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* mcasp1_axr11.gpio4_17 */ - {MCASP1_AXR12, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr12.mcasp7_axr0 */ - {MCASP1_AXR13, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr13.mcasp7_axr1 */ - {MCASP1_AXR14, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr14.mcasp7_aclkx */ - {MCASP1_AXR15, (M1 | PIN_INPUT_SLEW)}, /* mcasp1_axr15.mcasp7_fsx */ - {MCASP2_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkx.mcasp2_aclkx */ - {MCASP2_FSX, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_fsx.mcasp2_fsx */ - {MCASP2_ACLKR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_aclkr.mcasp2_aclkr */ - {MCASP2_FSR, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_fsr.mcasp2_fsr */ - {MCASP2_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr0.mcasp2_axr0 */ - {MCASP2_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr1.mcasp2_axr1 */ - {MCASP2_AXR2, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr2.mcasp2_axr2 */ - {MCASP2_AXR3, (M0 | PIN_INPUT_SLEW)}, /* mcasp2_axr3.mcasp2_axr3 */ - {MCASP2_AXR4, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr4.mcasp2_axr4 */ - {MCASP2_AXR5, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr5.mcasp2_axr5 */ - {MCASP2_AXR6, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr6.mcasp2_axr6 */ - {MCASP2_AXR7, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp2_axr7.mcasp2_axr7 */ - {MCASP3_ACLKX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_aclkx.mcasp3_aclkx */ - {MCASP3_FSX, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_fsx.mcasp3_fsx */ - {MCASP3_AXR0, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr0.mcasp3_axr0 */ - {MCASP3_AXR1, (M0 | PIN_INPUT_PULLDOWN)}, /* mcasp3_axr1.mcasp3_axr1 */ - {MCASP4_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_aclkx.uart8_rxd */ - {MCASP4_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_fsx.uart8_txd */ - {MCASP4_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp4_axr0.uart8_ctsn */ - {MCASP4_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp4_axr1.uart8_rtsn */ - {MCASP5_ACLKX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_aclkx.uart9_rxd */ - {MCASP5_FSX, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_fsx.uart9_txd */ - {MCASP5_AXR0, (M3 | PIN_INPUT_PULLDOWN)}, /* mcasp5_axr0.uart9_ctsn */ - {MCASP5_AXR1, (M3 | PIN_INPUT_PULLUP)}, /* mcasp5_axr1.uart9_rtsn */ - {MMC1_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_clk.mmc1_clk */ - {MMC1_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_cmd.mmc1_cmd */ - {MMC1_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat0.mmc1_dat0 */ - {MMC1_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat1.mmc1_dat1 */ - {MMC1_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat2.mmc1_dat2 */ - {MMC1_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_dat3.mmc1_dat3 */ - {MMC1_SDCD, (M0 | PIN_INPUT_PULLUP)}, /* mmc1_sdcd.mmc1_sdcd */ - {MMC1_SDWP, (M14 | PIN_OUTPUT)}, /* mmc1_sdwp.gpio6_28 */ - {GPIO6_10, (M10 | PIN_INPUT_PULLDOWN)}, /* gpio6_10.ehrpwm2A */ - {GPIO6_11, (M14 | PIN_INPUT_PULLUP)}, /* gpio6_11.gpio6_11 */ - {MMC3_CLK, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_clk.mmc3_clk */ - {MMC3_CMD, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_cmd.mmc3_cmd */ - {MMC3_DAT0, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat0.mmc3_dat0 */ - {MMC3_DAT1, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat1.mmc3_dat1 */ - {MMC3_DAT2, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat2.mmc3_dat2 */ - {MMC3_DAT3, (M0 | PIN_INPUT_PULLUP)}, /* mmc3_dat3.mmc3_dat3 */ - {MMC3_DAT4, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat4.spi4_sclk */ - {MMC3_DAT5, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat5.spi4_d1 */ - {MMC3_DAT6, (M1 | PIN_INPUT_PULLDOWN)}, /* mmc3_dat6.spi4_d0 */ - {MMC3_DAT7, (M1 | PIN_INPUT_PULLUP)}, /* mmc3_dat7.spi4_cs0 */ - {SPI1_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_sclk.gpio7_7 */ - {SPI1_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d1.gpio7_8 */ - {SPI1_D0, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_d0.gpio7_9 */ - {SPI1_CS0, (M14 | PIN_OUTPUT)}, /* spi1_cs0.gpio7_10 */ - {SPI1_CS1, (M14 | PIN_OUTPUT_PULLUP)}, /* spi1_cs1.gpio7_11 */ - {SPI1_CS2, (M14 | PIN_INPUT_PULLDOWN)}, /* spi1_cs2.gpio7_12 */ - {SPI1_CS3, (M6 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi1_cs3.hdmi1_cec */ - {SPI2_SCLK, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_sclk.gpio7_14 */ - {SPI2_D1, (M14 | PIN_INPUT_PULLDOWN)}, /* spi2_d1.gpio7_15 */ - {SPI2_D0, (M14 | PIN_INPUT_PULLUP)}, /* spi2_d0.gpio7_16 */ - {SPI2_CS0, (M14 | PIN_INPUT_PULLUP | SLEWCONTROL)}, /* spi2_cs0.gpio7_17 */ - {DCAN1_TX, (M15 | PULL_UP)}, /* dcan1_tx.safe for dcan1_tx */ - {DCAN1_RX, (M15 | PULL_UP)}, /* dcan1_rx.safe for dcan1_rx */ - {UART1_RXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_rxd.uart1_rxd */ - {UART1_TXD, (M0 | PIN_INPUT_SLEW)}, /* uart1_txd.uart1_txd */ - {UART1_CTSN, (M15 | PIN_INPUT_PULLDOWN)}, /* uart1_ctsn.Driveroff */ - {UART2_RXD, (M15 | PIN_INPUT_PULLDOWN)}, /* N/A.Driveroff */ - {UART2_TXD, (M15 | PIN_INPUT_PULLDOWN)}, /* uart2_txd.Driveroff */ - {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */ - {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ - {I2C2_SDA, (M1 | PIN_INPUT)}, /* i2c2_sda.hdmi1_ddc_scl */ - {I2C2_SCL, (M1 | PIN_INPUT)}, /* i2c2_scl.hdmi1_ddc_sda */ - {WAKEUP0, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup0.Wakeup0 */ - {WAKEUP1, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup1.Wakeup1 */ - {WAKEUP2, (M0 | PIN_OUTPUT_PULLDOWN)}, /* Wakeup2.Wakeup2 */ - {WAKEUP3, (M0 | PIN_OUTPUT_PULLUP)}, /* Wakeup3.Wakeup3 */ - {ON_OFF, (M1 | PIN_OUTPUT_PULLUP)}, /* on_off.on_off */ - {RTC_PORZ, (M0 | PIN_OUTPUT_PULLDOWN)}, /* rtc_porz.rtc_porz */ - {RTCK, (M0 | PIN_INPUT_PULLDOWN)}, /* rtck.rtck */ -}; - -const struct pad_conf_entry early_padconf[] = { - {UART2_CTSN, (M2 | PIN_INPUT_SLEW)}, /* uart2_ctsn.uart3_rxd */ - {UART2_RTSN, (M1 | PIN_INPUT_SLEW)}, /* uart2_rtsn.uart3_txd */ - {I2C1_SDA, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SDA */ - {I2C1_SCL, (PIN_INPUT_PULLUP | M0)}, /* I2C1_SCL */ -}; - -#ifdef CONFIG_IODELAY_RECALIBRATION -const struct iodelay_cfg_entry iodelay_cfg_array[] = { - {0x0114, 2980, 0}, /* CFG_GPMC_A0_IN */ - {0x0120, 2648, 0}, /* CFG_GPMC_A10_IN */ - {0x012C, 2918, 0}, /* CFG_GPMC_A11_IN */ - {0x0198, 2917, 0}, /* CFG_GPMC_A1_IN */ - {0x0204, 3156, 178}, /* CFG_GPMC_A2_IN */ - {0x0210, 3109, 246}, /* CFG_GPMC_A3_IN */ - {0x021C, 3142, 100}, /* CFG_GPMC_A4_IN */ - {0x0228, 3084, 33}, /* CFG_GPMC_A5_IN */ - {0x0234, 2778, 0}, /* CFG_GPMC_A6_IN */ - {0x0240, 3110, 0}, /* CFG_GPMC_A7_IN */ - {0x024C, 2874, 0}, /* CFG_GPMC_A8_IN */ - {0x0258, 3072, 0}, /* CFG_GPMC_A9_IN */ - {0x0264, 2466, 0}, /* CFG_GPMC_AD0_IN */ - {0x0270, 2523, 0}, /* CFG_GPMC_AD10_IN */ - {0x027C, 2453, 0}, /* CFG_GPMC_AD11_IN */ - {0x0288, 2285, 0}, /* CFG_GPMC_AD12_IN */ - {0x0294, 2206, 0}, /* CFG_GPMC_AD13_IN */ - {0x02A0, 1898, 0}, /* CFG_GPMC_AD14_IN */ - {0x02AC, 2473, 0}, /* CFG_GPMC_AD15_IN */ - {0x02B8, 2307, 0}, /* CFG_GPMC_AD1_IN */ - {0x02C4, 2691, 0}, /* CFG_GPMC_AD2_IN */ - {0x02D0, 2384, 0}, /* CFG_GPMC_AD3_IN */ - {0x02DC, 2462, 0}, /* CFG_GPMC_AD4_IN */ - {0x02E8, 2335, 0}, /* CFG_GPMC_AD5_IN */ - {0x02F4, 2370, 0}, /* CFG_GPMC_AD6_IN */ - {0x0300, 2389, 0}, /* CFG_GPMC_AD7_IN */ - {0x030C, 2672, 0}, /* CFG_GPMC_AD8_IN */ - {0x0318, 2334, 0}, /* CFG_GPMC_AD9_IN */ - {0x06F0, 480, 0}, /* CFG_RGMII0_RXC_IN */ - {0x06FC, 111, 1641}, /* CFG_RGMII0_RXCTL_IN */ - {0x0708, 272, 1116}, /* CFG_RGMII0_RXD0_IN */ - {0x0714, 243, 1260}, /* CFG_RGMII0_RXD1_IN */ - {0x0720, 0, 1614}, /* CFG_RGMII0_RXD2_IN */ - {0x072C, 105, 1673}, /* CFG_RGMII0_RXD3_IN */ - {0x0740, 531, 120}, /* CFG_RGMII0_TXC_OUT */ - {0x074C, 11, 60}, /* CFG_RGMII0_TXCTL_OUT */ - {0x0758, 7, 120}, /* CFG_RGMII0_TXD0_OUT */ - {0x0764, 0, 0}, /* CFG_RGMII0_TXD1_OUT */ - {0x0770, 276, 120}, /* CFG_RGMII0_TXD2_OUT */ - {0x077C, 440, 120}, /* CFG_RGMII0_TXD3_OUT */ - {0x0A70, 1551, 115}, /* CFG_VIN2A_D12_OUT */ - {0x0A7C, 816, 0}, /* CFG_VIN2A_D13_OUT */ - {0x0A88, 876, 0}, /* CFG_VIN2A_D14_OUT */ - {0x0A94, 312, 0}, /* CFG_VIN2A_D15_OUT */ - {0x0AA0, 58, 0}, /* CFG_VIN2A_D16_OUT */ - {0x0AAC, 0, 0}, /* CFG_VIN2A_D17_OUT */ - {0x0AB0, 702, 0}, /* CFG_VIN2A_D18_IN */ - {0x0ABC, 136, 976}, /* CFG_VIN2A_D19_IN */ - {0x0AD4, 210, 1357}, /* CFG_VIN2A_D20_IN */ - {0x0AE0, 189, 1462}, /* CFG_VIN2A_D21_IN */ - {0x0AEC, 232, 1278}, /* CFG_VIN2A_D22_IN */ - {0x0AF8, 0, 1397}, /* CFG_VIN2A_D23_IN */ -}; -#endif -#endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig new file mode 100644 index 0000000000..3b3c0272bf --- /dev/null +++ b/configs/am57xx_evm_nodt_defconfig @@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_OMAP54XX=y +CONFIG_TARGET_BEAGLE_X15=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_SETEXPR is not set diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig deleted file mode 100644 index 3b3c0272bf..0000000000 --- a/configs/beagle_x15_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_ARM=y -CONFIG_OMAP54XX=y -CONFIG_TARGET_BEAGLE_X15=y -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h new file mode 100644 index 0000000000..6308cab8e6 --- /dev/null +++ b/include/configs/am57xx_evm.h @@ -0,0 +1,91 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated. + * Felipe Balbi + * + * Configuration settings for the TI Beagle x15 board. + * See ti_omap5_common.h for omap5 common settings. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_AM57XX_EVM_H +#define __CONFIG_AM57XX_EVM_H + +#define CONFIG_AM57XX + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_IODELAY_RECALIBRATION +#endif + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_NR_DRAM_BANKS 2 + +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" + +#define CONSOLEDEV "ttyO2" +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_OMAP_ABE_SYSCK + +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + +#include + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION + +/* CPSW Ethernet */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ +#define CONFIG_PHYLIB +#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ + +#define CONFIG_SUPPORT_EMMC_BOOT + +/* USB xHCI HOST */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI_DWC3 +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + +#define CONFIG_OMAP_USB_PHY +#define CONFIG_OMAP_USB3PHY1_HOST + +/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + +#endif /* __CONFIG_AM57XX_EVM_H */ diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h deleted file mode 100644 index d38b7b55cf..0000000000 --- a/include/configs/beagle_x15.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2014 - * Texas Instruments Incorporated. - * Felipe Balbi - * - * Configuration settings for the TI Beagle x15 board. - * See ti_omap5_common.h for omap5 common settings. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_BEAGLE_X15_H -#define __CONFIG_BEAGLE_X15_H - -#define CONFIG_AM57XX - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_IODELAY_RECALIBRATION -#endif - -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_NR_DRAM_BANKS 2 - -#define CONFIG_ENV_SIZE (64 << 10) -#define CONFIG_ENV_IS_IN_FAT -#define FAT_ENV_INTERFACE "mmc" -#define FAT_ENV_DEVICE_AND_PART "0:1" -#define FAT_ENV_FILE "uboot.env" - -#define CONSOLEDEV "ttyO2" -#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_OMAP_ABE_SYSCK - -/* Define the default GPT table for eMMC */ -#define PARTS_DEFAULT \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" - -#include - -/* Enhance our eMMC support / experience. */ -#define CONFIG_CMD_GPT -#define CONFIG_EFI_PARTITION - -/* CPSW Ethernet */ -#define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ -#define CONFIG_MII /* Required in net/eth.c */ -#define CONFIG_PHY_GIGE /* per-board part of CPSW */ -#define CONFIG_PHYLIB -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ - -#define CONFIG_SUPPORT_EMMC_BOOT - -/* USB xHCI HOST */ -#define CONFIG_CMD_USB -#define CONFIG_USB_HOST -#define CONFIG_USB_XHCI_DWC3 -#define CONFIG_USB_XHCI -#define CONFIG_USB_XHCI_OMAP -#define CONFIG_USB_STORAGE -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 - -#define CONFIG_OMAP_USB_PHY -#define CONFIG_OMAP_USB3PHY1_HOST - -/* SATA */ -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_CMD_SCSI -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -#endif /* __CONFIG_BEAGLE_X5_H */