From: Vignesh R Date: Mon, 23 Nov 2015 12:13:36 +0000 (+0530) Subject: spi: ti_qspi: Use 4-byte opcode for mmap read X-Git-Tag: v2016.03-rc1~267 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=74d49bfde3dd562ceeba2d6883caedcb3e484a6b;p=u-boot spi: ti_qspi: Use 4-byte opcode for mmap read ti-qspi driver currently uses 3-byte addressing mode(and opcodes) for memory-mapped read. This restricts maximum addressable flash size to 16MB. Enable the 4-byte addressing(and use 4-byte opcode) for memory-mapped read to allow access to addresses above 16MB. Signed-off-by: Ravi Babu [vigneshr@ti.com: Re-word commit description] Signed-off-by: Vignesh R --- diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 78d8b1368d..b5c974ce38 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -52,15 +52,15 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CMD_READ (0x3 << 0) #define QSPI_CMD_READ_DUAL (0x6b << 0) -#define QSPI_CMD_READ_QUAD (0x6b << 0) +#define QSPI_CMD_READ_QUAD (0x6c << 0) #define QSPI_CMD_READ_FAST (0x0b << 0) -#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8) +#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8) #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10) #define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) #define QSPI_SETUP0_READ_NORMAL (0x0 << 12) #define QSPI_SETUP0_READ_DUAL (0x1 << 12) #define QSPI_SETUP0_READ_QUAD (0x3 << 12) -#define QSPI_CMD_WRITE (0x2 << 16) +#define QSPI_CMD_WRITE (0x12 << 16) #define QSPI_NUM_DUMMY_BITS (0x0 << 24) /* ti qspi register set */