From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 10 Jan 2018 05:20:25 +0000 (+0800)
Subject: imx: cpu: update cpu file to support i.MX8M
X-Git-Tag: v2018.03-rc2~47^2~59
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=7537e93290bd6437622beb21b22e19a8beb8847e;p=u-boot

imx: cpu: update cpu file to support i.MX8M

Update get_reset_cause to reflect i.MX8M
Compile out get_ahb_clk and set_chipselect_size for i.MX8M

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
---

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index a32ab87e9b..fae8b0a419 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -62,6 +62,11 @@ static char *get_reset_cause(void)
 		return "WDOG4";
 	case 0x00200:
 		return "TEMPSENSE";
+#elif defined(CONFIG_MX8M)
+	case 0x00100:
+		return "WDOG2";
+	case 0x00200:
+		return "TEMPSENSE";
 #else
 	case 0x00100:
 		return "TEMPSENSE";
@@ -137,6 +142,8 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
+	case MXC_CPU_MX8MQ:
+		return "8MQ";	/* Quad-core version of the mx8m */
 	case MXC_CPU_MX7S:
 		return "7S";	/* Single-core version of the mx7 */
 	case MXC_CPU_MX7D:
@@ -259,7 +266,7 @@ int cpu_mmc_init(bd_t *bis)
 }
 #endif
 
-#ifndef CONFIG_MX7
+#if !(defined(CONFIG_MX7) || defined(CONFIG_MX8M))
 u32 get_ahb_clk(void)
 {
 	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -293,6 +300,7 @@ void arch_preboot_os(void)
 #endif
 }
 
+#ifndef CONFIG_MX8M
 void set_chipselect_size(int const cs_size)
 {
 	unsigned int reg;
@@ -323,6 +331,7 @@ void set_chipselect_size(int const cs_size)
 
 	writel(reg, &iomuxc_regs->gpr[1]);
 }
+#endif
 
 #ifdef CONFIG_NXP_BOARD_REVISION
 int nxp_board_rev(void)