From: York Sun <yorksun@freescale.com>
Date: Fri, 26 Oct 2012 16:40:14 +0000 (+0000)
Subject: powerpc/corenet_ds: Update DDR timing for single-rank DIMMs
X-Git-Tag: v2013.01-rc2~104^2~8
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=765ad3cf4d6f60f6104289d05bfa39d562c83859;p=u-boot

powerpc/corenet_ds: Update DDR timing for single-rank DIMMs

Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---

diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 4a53b8d933..da284cde95 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -139,8 +139,8 @@ static const struct board_specific_parameters udimm0[] = {
 	{2,  1250,    4,     6,   0xff,    2,  0},
 	{2,  1350,    5,     7,   0xff,    2,  0},
 	{2,  1666,    5,     8,   0xff,    2,  0},
-	{1,   850,    4,     5,   0xff,    2,  0},
-	{1,   950,    4,     7,   0xff,    2,  0},
+	{1,  1250,    4,     6,   0xff,    2,  0},
+	{1,  1335,    4,     7,   0xff,    2,  0},
 	{1,  1666,    4,     8,   0xff,    2,  0},
 	{}
 };