From: Nava kishore Manne <nava.manne@xilinx.com>
Date: Mon, 22 May 2017 06:35:17 +0000 (+0530)
Subject: arm64: zynqmp: Label whole PL part as fpga_full region
X-Git-Tag: v2018.01-rc1~59^2~56
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=7689dce753195000ceeb32274fc802cf957f24dc;p=u-boot

arm64: zynqmp: Label whole PL part as fpga_full region

This will simplify dt overlay structure for the whole PL.

Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 3dd17e6c3f..877874e7bf 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -282,7 +282,14 @@
 		compatible = "arm,cortex-a53-edac";
 	};
 
-	pcap {
+	fpga_full: fpga-full {
+		compatible = "fpga-region";
+		fpga-mgr = <&pcap>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+	};
+
+	pcap: pcap {
 		compatible = "xlnx,zynqmp-pcap-fpga";
 	};