From: Maxime Ripard Date: Fri, 3 Oct 2014 12:16:28 +0000 (+0800) Subject: ARM: sun6i: Setup the A31 UART0 muxing X-Git-Tag: v2015.01-rc1~127^2~25 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=7711539734ac71e2156b4b04464dbffa849cd4fc;p=u-boot ARM: sun6i: Setup the A31 UART0 muxing Signed-off-by: Maxime Ripard Signed-off-by: Hans de Goede [wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"] [wens@csie.org: reorder #ifs by SUN?I] [wens@csie.org: replace magic numbers with GPIO definitions] Signed-off-by: Chen-Yu Tsai Acked-by: Ian Campbell --- diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 95a74c5c06..b6d63dbb40 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -58,6 +58,10 @@ int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);