From: richardbarry <richardbarry@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Date: Sat, 12 Apr 2008 23:26:01 +0000 (+0000)
Subject: Efficiency improvement.
X-Git-Tag: V5.0.0~19
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=7777e37b42f36ccbc9cd499fa81b9aca8b4f6204;p=freertos

Efficiency improvement.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@305 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
---

diff --git a/Source/portable/MPLAB/PIC32MX/ISR_Support.h b/Source/portable/MPLAB/PIC32MX/ISR_Support.h
index e1d962744..fb6aaba79 100644
--- a/Source/portable/MPLAB/PIC32MX/ISR_Support.h
+++ b/Source/portable/MPLAB/PIC32MX/ISR_Support.h
@@ -60,21 +60,21 @@
 .macro	portSAVE_CONTEXT
 
 	/* Make room for the context. */	
-	addiu		sp,	sp, -portCONTEXT_SIZE
 
 	/* Get interrupts above the kernel priority enabled again ASAP.  First
 	save the current status so we can manipulate it, and the cause and EPC
 	registers so we capture their original values in case of interrupt nesting. */
 
 	mfc0		k0, _CP0_CAUSE
+	addiu		sp,	sp, -portCONTEXT_SIZE
 	sw			k0, portCAUSE_STACK_LOCATION(sp)
 	mfc0		k1, _CP0_STATUS
-	sw			k1, portSTATUS_STACK_LOCATION(sp)
-
 	/* Also save s6 so we can use it during this interrupt.  Any
 	nesting interrupts should maintain the values of this register
 	accross the ISR. */
 	sw			s6, 44(sp)
+	sw			k1, portSTATUS_STACK_LOCATION(sp)
+
 
 	/* s6 holds the EPC value, we may want this during the context switch. */
 	mfc0 		s6, _CP0_EPC