From: richardbarry Date: Sun, 11 May 2008 13:43:46 +0000 (+0000) Subject: First commit of PPC405 version with floating point included. X-Git-Tag: V5.0.2~47 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=7915877650317abe44e240766f08e0023333dd95;p=freertos First commit of PPC405 version with floating point included. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@350 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h new file mode 100644 index 000000000..742c82021 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/FreeRTOSConfig.h @@ -0,0 +1,110 @@ +/* + FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 250 ) +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 200000000 ) /* Clock setup from start.asm in the demo application. */ +#define configTICK_RATE_HZ ( (portTickType) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 6 ) +#define configTOTAL_HEAP_SIZE ( (size_t) (80 * 1024) ) +#define configMAX_TASK_NAME_LEN ( 20 ) +#define configUSE_16_BIT_TICKS 1 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_TRACE_FACILITY 0 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_APPLICATION_TASK_TAG 1 +#define configUSE_FPU 1 + + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 4 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vResumeFromISR 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 1 +#define configUSE_RECURSIVE_MUTEXES 1 + + +#if configUSE_FPU == 1 + /* Include the header that define the traceTASK_SWITCHED_IN() and + traceTASK_SWITCHED_OUT() macros to save and restore the floating + point registers for tasks that have requested this behaviour. */ + #include "FPU_Macros.h" +#endif + +#endif /* FREERTOS_CONFIG_H */ + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld new file mode 100644 index 000000000..0a5bdac6a --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/RTOSDemo_linker_script.ld @@ -0,0 +1,209 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: Xilinx EDK 10.1.01 EDK_K_SP1.3 */ +/* */ +/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : PowerPC405 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x100; + +/* Define Memories in the system */ + +MEMORY +{ + SRAM_C_MEM0_BASEADDR : ORIGIN = 0xFFF00000, LENGTH = 0x000FFFEC +} + +/* Specify the default entry point to the program */ + +ENTRY(_boot) +STARTUP(boot.o) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.vectors : { + __vectors_start = .; + *(.vectors) + __vectors_end = .; +} > SRAM_C_MEM0_BASEADDR + +.text : { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) +} > SRAM_C_MEM0_BASEADDR + +.init : { + KEEP (*(.init)) +} > SRAM_C_MEM0_BASEADDR + +.fini : { + KEEP (*(.fini)) +} > SRAM_C_MEM0_BASEADDR + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sdata2 : { + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > SRAM_C_MEM0_BASEADDR + +.data : { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __data_end = .; +} > SRAM_C_MEM0_BASEADDR + +.got : { + *(.got) +} > SRAM_C_MEM0_BASEADDR + +.got1 : { + *(.got1) +} > SRAM_C_MEM0_BASEADDR + +.got2 : { + *(.got2) +} > SRAM_C_MEM0_BASEADDR + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > SRAM_C_MEM0_BASEADDR + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > SRAM_C_MEM0_BASEADDR + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > SRAM_C_MEM0_BASEADDR + +.eh_frame : { + *(.eh_frame) +} > SRAM_C_MEM0_BASEADDR + +.jcr : { + *(.jcr) +} > SRAM_C_MEM0_BASEADDR + +.gcc_except_table : { + *(.gcc_except_table) +} > SRAM_C_MEM0_BASEADDR + +.sdata : { + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.sbss : { + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + __sbss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > SRAM_C_MEM0_BASEADDR + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.bss : { + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + __bss_end = .; +} > SRAM_C_MEM0_BASEADDR + +.boot0 0xFFFFFFEC : { + __boot0_start = .; + *(.boot0) + __boot0_end = .; +} + +.boot 0xFFFFFFFC : { + __boot_start = .; + *(.boot) + __boot_end = .; +} + +/* Generate Stack and Heap Sections */ + +.stack : { + _stack_end = .; + . += _STACK_SIZE; + . = ALIGN(16); + __stack = .; +} > SRAM_C_MEM0_BASEADDR + +.heap : { + . = ALIGN(16); + _heap_start = .; + . += _HEAP_SIZE; + . = ALIGN(16); + _heap_end = .; + _end = .; +} > SRAM_C_MEM0_BASEADDR + +} + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.c b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.c new file mode 100644 index 000000000..53d60d497 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.c @@ -0,0 +1,235 @@ +/* + FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * Tests the floating point context save and restore mechanism. + * + * Two tasks are created - each of which is allocated a buffer of + * portNO_FLOP_REGISTERS_TO_SAVE 32bit variables into which the flop context + * of the task is saved when the task is switched out, and from which the + * flop context of the task is restored when the task is switch in. Prior to + * the tasks being created each position in the two buffers is filled with a + * unique value - this way the flop context of each task is different. + * + * The two test tasks never block so are always in either the Running or + * Ready state. They execute at the lowest priority so will get pre-empted + * regularly, although the yield frequently so will not get much execution + * time. The lack of execution time is not a problem as its only the + * switching in and out that is being tested. + * + * Whenever a task is moved from the Ready to the Running state its flop + * context will be loaded from the buffer, but while the task is in the + * Running state the buffer is not used and can contain any value - in this + * case and for test purposes the task itself clears the buffer to zero. + * The next time the task is moved out of the Running state into the + * Ready state the flop context will once more get saved to the buffer - + * overwriting the zeros. + * + * Therefore whenever the task is not in the Running state its buffer contains + * the most recent values of its floating point registers - the zeroing out + * of the buffer while the task was executing being used to ensure the values + * the buffer contains are not stale. + * + * When neither test task is in the Running state the buffers should contain + * the unique values allocated before the tasks were created. If so then + * the floating point context has been maintained. This check is performed + * by the 'check' task (defined in main.c) by calling + * xAreFlopRegisterTestsStillRunning(). + * + * The test tasks also increment a value each time they execute. + * xAreFlopRegisterTestsStillRunning() also checks that this value has changed + * since it last ran to ensure the test tasks are still getting processing time. + */ + +/* Standard includes files. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/*-----------------------------------------------------------*/ + +#define flopNUMBER_OF_TASKS 2 +#define flopSTART_VALUE ( 0x1 ) + +/*-----------------------------------------------------------*/ + +/* The two test tasks as described at the top of this file. */ +static void vFlopTest1( void *pvParameters ); +static void vFlopTest2( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* Buffers into which the flop registers will be saved. There is a buffer for +both tasks. */ +static unsigned portLONG ulFlopRegisters[ flopNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ] = { 0 }; + +/* Variables that are incremented by the tasks to indicate that they are still +running. */ +static volatile unsigned portLONG ulFlop1CycleCount = 0, ulFlop2CycleCount = 0; + +/*-----------------------------------------------------------*/ + +void vStartFlopRegTests( void ) +{ +xTaskHandle xTaskJustCreated; +unsigned portBASE_TYPE x, y, z = flopSTART_VALUE; + + /* Fill the arrays into which the flop registers are to be saved with + known values. These are the values that will be written to the flop + registers when the tasks start, and as the tasks do not perform any + flop operations the values should never change. Each position in the + buffer contains a different value so the flop context of each task + will be different. */ + for( x = 0; x < flopNUMBER_OF_TASKS; x++ ) + { + for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1); y++ ) + { + ulFlopRegisters[ x ][ y ] = z; + z++; + } + } + + + /* Create the first task. */ + xTaskCreate( vFlopTest1, ( signed portCHAR * ) "flop1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated ); + + /* The task tag value is a value that can be associated with a task, but + is not used by the scheduler itself. Its use is down to the application so + it makes a convenient place in this case to store the pointer to the buffer + into which the flop context of the task will be stored. The first created + task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ]. */ + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) ); + + /* Do the same for the second task. */ + xTaskCreate( vFlopTest2, ( signed portCHAR * ) "flop2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) ); +} +/*-----------------------------------------------------------*/ + +static void vFlopTest1( void *pvParameters ) +{ + for( ;; ) + { + /* The values from the buffer should have now been written to the flop + registers. Clear the buffer to ensure the same values then get written + back the next time the task runs. Being preempted during this memset + could cause the test to fail, hence the critical section. */ + portENTER_CRITICAL(); + memset( ulFlopRegisters[ 0 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) ); + portEXIT_CRITICAL(); + + /* We don't have to do anything other than indicate that we are + still running. */ + ulFlop1CycleCount++; + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +static void vFlopTest2( void *pvParameters ) +{ + for( ;; ) + { + /* The values from the buffer should have now been written to the flop + registers. Clear the buffer to ensure the same values then get written + back the next time the task runs. */ + portENTER_CRITICAL(); + memset( ulFlopRegisters[ 1 ], 0x00, ( portNO_FLOP_REGISTERS_TO_SAVE * sizeof( unsigned portBASE_TYPE ) ) ); + portEXIT_CRITICAL(); + + /* We don't have to do anything other than indicate that we are + still running. */ + ulFlop2CycleCount++; + taskYIELD(); + } +} +/*-----------------------------------------------------------*/ + +portBASE_TYPE xAreFlopRegisterTestsStillRunning( void ) +{ +portBASE_TYPE xReturn = pdPASS; +unsigned portBASE_TYPE x, y, z = flopSTART_VALUE; + + /* Called from the 'check' task. + + The flop tasks cannot be currently running, check their saved registers + are as expected. The tests tasks do not perform any flop operations so + their registers should be as per their initial setting. */ + for( x = 0; x < flopNUMBER_OF_TASKS; x++ ) + { + for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ ) + { + if( ulFlopRegisters[ x ][ y ] != z ) + { + xReturn = pdFAIL; + break; + } + + z++; + } + } + + /* Check both tasks have actually been swapped in and out since this function + last executed. */ + if( ulFlop1CycleCount == 0 ) + { + xReturn = pdFAIL; + } + + if( ulFlop2CycleCount == 0 ) + { + xReturn = pdFAIL; + } + + ulFlop1CycleCount = 0; + ulFlop2CycleCount = 0; +} + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.h b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.h new file mode 100644 index 000000000..ecf30d506 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop-reg-test.h @@ -0,0 +1,56 @@ +/* + FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +#ifndef FLOP_REG_TEST_H +#define FLOP_REG_TEST_H + +void vStartFlopRegTests( void ); +portBASE_TYPE xAreFlopRegisterTestsStillRunning( void ); + +#endif diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop.c b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop.c new file mode 100644 index 000000000..8c4248669 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/flop/flop.c @@ -0,0 +1,400 @@ +/* + FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * Creates eight tasks, each of which loops continuously performing a + * floating point calculation. + * + * All the tasks run at the idle priority and never block or yield. This causes + * all eight tasks to time slice with the idle task. Running at the idle priority + * means that these tasks will get pre-empted any time another task is ready to run + * or a time slice occurs. More often than not the pre-emption will occur mid + * calculation, creating a good test of the schedulers context switch mechanism - a + * calculation producing an unexpected result could be a symptom of a corruption in + * the context of a task. + * + * This file demonstrates the use of the task tag and traceTASK_SWITCHED_IN and + * traceTASK_SWITCHED_OUT macros to save and restore the floating point context. + */ + +#include +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo program include files. */ +#include "flop.h" + +/* Misc. definitions. */ +#define mathSTACK_SIZE configMINIMAL_STACK_SIZE +#define mathNUMBER_OF_TASKS ( 8 ) + +/* Four tasks, each of which performs a different floating point calculation. +Each of the four is created twice. */ +static portTASK_FUNCTION_PROTO( vCompetingMathTask1, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask2, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask3, pvParameters ); +static portTASK_FUNCTION_PROTO( vCompetingMathTask4, pvParameters ); + +/* These variables are used to check that all the tasks are still running. If a +task gets a calculation wrong it will stop incrementing its check variable. */ +static volatile unsigned portSHORT usTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; + +/* Buffers into which the flop registers will be saved. There is a buffer for +each task created within this file. Zeroing out this array is the normal and +safe option as this will cause the task to start with all zeros in its flop +context. */ +static unsigned portLONG ulFlopRegisters[ mathNUMBER_OF_TASKS ][ portNO_FLOP_REGISTERS_TO_SAVE ] = { 0 }; + +/*-----------------------------------------------------------*/ + +void vStartMathTasks( unsigned portBASE_TYPE uxPriority ) +{ +xTaskHandle xTaskJustCreated; +portBASE_TYPE x, y; + + /* Place known values into the buffers into which the flop registers are + to be saved. This is for debug purposes only, it is not normally + required. The last position in each array is left at zero as the status + register will be loaded from there. + + It is intended that these values can be viewed being loaded into the + flop registers when a task is started - however the Insight debugger + does not seem to want to show the flop register values. */ + for( x = 0; x < mathNUMBER_OF_TASKS; x++ ) + { + for( y = 0; y < ( portNO_FLOP_REGISTERS_TO_SAVE - 1 ); y++ ) + { + ulFlopRegisters[ x ][ y ] = ( x + 1 ); + } + } + + /* Create the first task - passing it the address of the check variable + that it is going to increment. This check variable is used as an + indication that the task is still running. */ + xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math1", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 0 ] ), uxPriority, &xTaskJustCreated ); + + /* The task tag value is a value that can be associated with a task, but + is not used by the scheduler itself. Its use is down to the application so + it makes a convenient place in this case to store the pointer to the buffer + into which the flop context of the task will be stored. The first created + task uses ulFlopRegisters[ 0 ], the second ulFlopRegisters[ 1 ], etc. */ + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 0 ][ 0 ] ) ); + + /* Create another 7 tasks, allocating a buffer for each. */ + xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math2", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 1 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 1 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math3", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 2 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 2 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math4", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 3 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 3 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask1, ( signed portCHAR * ) "Math5", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 4 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 4 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask2, ( signed portCHAR * ) "Math6", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 5 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 5 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask3, ( signed portCHAR * ) "Math7", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 6 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 6 ][ 0 ] ) ); + + xTaskCreate( vCompetingMathTask4, ( signed portCHAR * ) "Math8", mathSTACK_SIZE, ( void * ) &( usTaskCheck[ 7 ] ), uxPriority, &xTaskJustCreated ); + vTaskSetApplicationTaskTag( xTaskJustCreated, ( void * ) &( ulFlopRegisters[ 7 ][ 0 ] ) ); +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask1, pvParameters ) +{ +volatile portFLOAT d1, d2, d3, d4; +volatile unsigned portSHORT *pusTaskCheckVariable; +volatile portFLOAT dAnswer; +portSHORT sError = pdFALSE; + + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + dAnswer = ( d1 + d2 ) * d3; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for(;;) + { + d1 = 123.4567; + d2 = 2345.6789; + d3 = -918.222; + + d4 = ( d1 + d2 ) * d3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask2, pvParameters ) +{ +volatile portFLOAT d1, d2, d3, d4; +volatile unsigned portSHORT *pusTaskCheckVariable; +volatile portFLOAT dAnswer; +portSHORT sError = pdFALSE; + + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + dAnswer = ( d1 / d2 ) * d3; + + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + /* Keep performing a calculation and checking the result against a constant. */ + for( ;; ) + { + d1 = -389.38; + d2 = 32498.2; + d3 = -2.0001; + + d4 = ( d1 / d2 ) * d3; + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + /* If the calculation does not match the expected constant, stop the + increment of the check variable. */ + if( fabs( d4 - dAnswer ) > 0.001 ) + { + sError = pdTRUE; + } + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know + this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask3, pvParameters ) +{ +volatile portFLOAT *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +portSHORT sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pdArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pdArray[ xPosition ] = ( portFLOAT ) xPosition + 5.5; + dTotal1 += ( portFLOAT ) xPosition + 5.5; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + dTotal2 += pdArray[ xPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +static portTASK_FUNCTION( vCompetingMathTask4, pvParameters ) +{ +volatile portFLOAT *pdArray, dTotal1, dTotal2, dDifference; +volatile unsigned portSHORT *pusTaskCheckVariable; +const size_t xArraySize = 10; +size_t xPosition; +portSHORT sError = pdFALSE; + + /* The variable this task increments to show it is still running is passed in + as the parameter. */ + pusTaskCheckVariable = ( unsigned portSHORT * ) pvParameters; + + pdArray = ( portFLOAT * ) pvPortMalloc( xArraySize * sizeof( portFLOAT ) ); + + /* Keep filling an array, keeping a running total of the values placed in the + array. Then run through the array adding up all the values. If the two totals + do not match, stop the check variable from incrementing. */ + for( ;; ) + { + dTotal1 = 0.0; + dTotal2 = 0.0; + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + pdArray[ xPosition ] = ( portFLOAT ) xPosition * 12.123; + dTotal1 += ( portFLOAT ) xPosition * 12.123; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + for( xPosition = 0; xPosition < xArraySize; xPosition++ ) + { + dTotal2 += pdArray[ xPosition ]; + } + + dDifference = dTotal1 - dTotal2; + if( fabs( dDifference ) > 0.001 ) + { + sError = pdTRUE; + } + + #if configUSE_PREEMPTION == 0 + taskYIELD(); + #endif + + if( sError == pdFALSE ) + { + /* If the calculation has always been correct, increment the check + variable so we know this task is still running okay. */ + ( *pusTaskCheckVariable )++; + } + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreMathsTaskStillRunning( void ) +{ +/* Keep a history of the check variables so we know if they have been incremented +since the last call. */ +static unsigned portSHORT usLastTaskCheck[ mathNUMBER_OF_TASKS ] = { ( unsigned portSHORT ) 0 }; +portBASE_TYPE xReturn = pdTRUE, xTask; + + /* Check the maths tasks are still running by ensuring their check variables + are still incrementing. */ + for( xTask = 0; xTask < mathNUMBER_OF_TASKS; xTask++ ) + { + if( usTaskCheck[ xTask ] == usLastTaskCheck[ xTask ] ) + { + /* The check has not incremented so an error exists. */ + xReturn = pdFALSE; + } + + usLastTaskCheck[ xTask ] = usTaskCheck[ xTask ]; + } + + return xReturn; +} + + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/main.c b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/main.c new file mode 100644 index 000000000..51e1c5f68 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/main.c @@ -0,0 +1,686 @@ +/* + FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + +/* + * Creates all the demo application tasks, then starts the scheduler. The WEB + * documentation provides more details of the demo application tasks. + * + * In addition to the standard demo tasks, the follow demo specific tasks are + * create: + * + * The "Check" task. This only executes every three seconds but has the highest + * priority so is guaranteed to get processor time. Its main function is to + * check that all the other tasks are still operational. Most tasks maintain + * a unique count that is incremented each time the task successfully completes + * its function. Should any error occur within such a task the count is + * permanently halted. The check task inspects the count of each task to ensure + * it has changed since the last time the check task executed. If all the count + * variables have changed all the tasks are still executing error free, and the + * check task toggles the onboard LED. Should any task contain an error at any time + * the LED toggle rate will change from 3 seconds to 500ms. + * + * The "Register Check" tasks. These tasks fill the CPU registers with known + * values, then check that each register still contains the expected value, the + * discovery of an unexpected value being indicative of an error in the RTOS + * context switch mechanism. The register check tasks operate at low priority + * so are switched in and out frequently. + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Xilinx library includes. */ +#include "xcache_l.h" +#include "xintc.h" + +/* Demo application includes. */ +#include "flash.h" +#include "integer.h" +#include "comtest2.h" +#include "semtest.h" +#include "BlockQ.h" +#include "dynamic.h" +#include "GenQTest.h" +#include "QPeek.h" +#include "blocktim.h" +#include "death.h" +#include "partest.h" +#include "countsem.h" +#include "recmutex.h" +#include "flop.h" +#include "flop-reg-test.h" + +/* Priorities assigned to the demo tasks. */ +#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 ) +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainQUEUE_BLOCK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainDEATH_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainGENERIC_QUEUE_PRIORITY ( tskIDLE_PRIORITY ) +#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define mainFLOP_PRIORITY ( tskIDLE_PRIORITY ) + +/* The first LED used by the COM test and check tasks respectively. */ +#define mainCOM_TEST_LED ( 4 ) +#define mainCHECK_TEST_LED ( 3 ) + +/* The baud rate used by the comtest tasks is set by the hardware, so the +baud rate parameters passed into the comtest initialisation has no effect. */ +#define mainBAUD_SET_IN_HARDWARE ( 0 ) + +/* Delay periods used by the check task. If no errors have been found then +the check LED will toggle every mainNO_ERROR_CHECK_DELAY milliseconds. If an +error has been found at any time then the toggle rate will increase to +mainERROR_CHECK_DELAY milliseconds. */ +#define mainNO_ERROR_CHECK_DELAY ( ( portTickType ) 3000 / portTICK_RATE_MS ) +#define mainERROR_CHECK_DELAY ( ( portTickType ) 500 / portTICK_RATE_MS ) + + +/* + * The tasks defined within this file - described within the comments at the + * head of this page. + */ +static void prvRegTestTask1( void *pvParameters ); +static void prvRegTestTask2( void *pvParameters ); +static void prvErrorChecks( void *pvParameters ); + +/* + * Called by the 'check' task to inspect all the standard demo tasks within + * the system, as described within the comments at the head of this page. + */ +static portSHORT prvCheckOtherTasksAreStillRunning( void ); + +/* + * Perform any hardware initialisation required by the demo application. + */ +static void prvSetupHardware( void ); + +/*-----------------------------------------------------------*/ + +/* xRegTestStatus will get set to pdFAIL by the regtest tasks if they +discover an unexpected value. */ +static unsigned portBASE_TYPE xRegTestStatus = pdPASS; + +/* Counters used to ensure the regtest tasks are still running. */ +static volatile unsigned portLONG ulRegTest1Counter = 0UL, ulRegTest2Counter = 0UL; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + + /* Must be called prior to installing any interrupt handlers! */ + vPortSetupInterruptController(); + + /* In this case prvSetupHardware() just enables the caches and and + configures the IO ports for the LED outputs. */ + prvSetupHardware(); + + /* Start the standard demo application tasks. Note that the baud rate used + by the comtest tasks is set by the hardware, so the baud rate parameter + passed has no effect. */ + vStartLEDFlashTasks( mainLED_TASK_PRIORITY ); + vStartIntegerMathTasks( tskIDLE_PRIORITY ); + vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainBAUD_SET_IN_HARDWARE, mainCOM_TEST_LED ); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartBlockingQueueTasks ( mainQUEUE_BLOCK_PRIORITY ); + vStartDynamicPriorityTasks(); + vStartGenericQueueTasks( mainGENERIC_QUEUE_PRIORITY ); + vStartQueuePeekTasks(); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartRecursiveMutexTasks(); + + #if ( configUSE_FPU == 1 ) + vStartMathTasks( mainFLOP_PRIORITY ); + vStartFlopRegTests(); + #endif + + /* Create the tasks defined within this file. */ + xTaskCreate( prvRegTestTask1, "Regtest1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTestTask2, "Regtest2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The suicide tasks must be started last as they record the number of other + tasks that exist within the system. The value is then used to ensure at run + time the number of tasks that exists is within expected bounds. */ + vCreateSuicidalTasks( mainDEATH_PRIORITY ); + + /* Now start the scheduler. Following this call the created tasks should + be executing. */ + vTaskStartScheduler( ); + + /* vTaskStartScheduler() will only return if an error occurs while the + idle task is being created. */ + for( ;; ); + + return 0; +} +/*-----------------------------------------------------------*/ + +static portSHORT prvCheckOtherTasksAreStillRunning( void ) +{ +portBASE_TYPE lReturn = pdPASS; +static unsigned portLONG ulLastRegTest1Counter= 0UL, ulLastRegTest2Counter = 0UL; + + /* The demo tasks maintain a count that increments every cycle of the task + provided that the task has never encountered an error. This function + checks the counts maintained by the tasks to ensure they are still being + incremented. A count remaining at the same value between calls therefore + indicates that an error has been detected. */ + + if( xAreIntegerMathsTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreComTestTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreQueuePeekTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + #if ( configUSE_FPU == 1 ) + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + + if( xAreFlopRegisterTestsStillRunning() != pdTRUE ) + { + lReturn = pdFAIL; + } + #endif + + /* Have the register test tasks found any errors? */ + if( xRegTestStatus != pdPASS ) + { + lReturn = pdFAIL; + } + + /* Are the register test tasks still looping? */ + if( ulLastRegTest1Counter == ulRegTest1Counter ) + { + lReturn = pdFAIL; + } + else + { + ulLastRegTest1Counter = ulRegTest1Counter; + } + + if( ulLastRegTest2Counter == ulRegTest2Counter ) + { + lReturn = pdFAIL; + } + else + { + ulLastRegTest2Counter = ulRegTest2Counter; + } + + return lReturn; +} +/*-----------------------------------------------------------*/ + +static void prvErrorChecks( void *pvParameters ) +{ +portTickType xDelayPeriod = mainNO_ERROR_CHECK_DELAY, xLastExecutionTime; +volatile unsigned portBASE_TYPE uxFreeStack; + + /* This call is just to demonstrate the use of the function - nothing is + done with the value. You would expect the stack high water mark to be + lower (the function to return a larger value) here at function entry than + later following calls to other functions. */ + uxFreeStack = uxTaskGetStackHighWaterMark( NULL ); + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. */ + for( ;; ) + { + /* Again just for demo purposes - uxFreeStack should have a lower value + here than following the call to uxTaskGetStackHighWaterMark() on the + task entry. */ + uxFreeStack = uxTaskGetStackHighWaterMark( NULL ); + + /* Wait until it is time to check again. The time we wait here depends + on whether an error has been detected or not. When an error is + detected the time is shortened resulting in a faster LED flash rate. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* See if the other tasks are all ok. */ + if( prvCheckOtherTasksAreStillRunning() != pdPASS ) + { + /* An error occurred in one of the tasks so shorten the delay + period - which has the effect of increasing the frequency of the + LED toggle. */ + xDelayPeriod = mainERROR_CHECK_DELAY; + } + + /* Flash! */ + vParTestToggleLED( mainCHECK_TEST_LED ); + } +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + XCache_EnableICache( 0x80000000 ); + XCache_EnableDCache( 0x80000000 ); + + /* Setup the IO port for use with the LED outputs. */ + vParTestInitialise(); +} +/*-----------------------------------------------------------*/ + +void prvRegTest1Pass( void ) +{ + /* Called from the inline assembler - this cannot be static + otherwise it can get optimised away. */ + ulRegTest1Counter++; +} +/*-----------------------------------------------------------*/ + +void prvRegTest2Pass( void ) +{ + /* Called from the inline assembler - this cannot be static + otherwise it can get optimised away. */ + ulRegTest2Counter++; +} +/*-----------------------------------------------------------*/ + +void prvRegTestFail( void ) +{ + /* Called from the inline assembler - this cannot be static + otherwise it can get optimised away. */ + xRegTestStatus = pdFAIL; +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTask1( void *pvParameters ) +{ + /* The first register test task as described at the top of this file. The + values used in the registers are different to those use in the second + register test task. Also, unlike the second register test task, this task + yields between setting the register values and subsequently checking the + register values. */ + asm volatile + ( + "RegTest1Start: \n\t" \ + " \n\t" \ + " li 0, 301 \n\t" \ + " mtspr 256, 0 #USPRG0 \n\t" \ + " li 0, 501 \n\t" \ + " mtspr 8, 0 #LR \n\t" \ + " li 0, 4 \n\t" \ + " mtspr 1, 0 #XER \n\t" \ + " \n\t" \ + " li 0, 1 \n\t" \ + " li 2, 2 \n\t" \ + " li 3, 3 \n\t" \ + " li 4, 4 \n\t" \ + " li 5, 5 \n\t" \ + " li 6, 6 \n\t" \ + " li 7, 7 \n\t" \ + " li 8, 8 \n\t" \ + " li 9, 9 \n\t" \ + " li 10, 10 \n\t" \ + " li 11, 11 \n\t" \ + " li 12, 12 \n\t" \ + " li 13, 13 \n\t" \ + " li 14, 14 \n\t" \ + " li 15, 15 \n\t" \ + " li 16, 16 \n\t" \ + " li 17, 17 \n\t" \ + " li 18, 18 \n\t" \ + " li 19, 19 \n\t" \ + " li 20, 20 \n\t" \ + " li 21, 21 \n\t" \ + " li 22, 22 \n\t" \ + " li 23, 23 \n\t" \ + " li 24, 24 \n\t" \ + " li 25, 25 \n\t" \ + " li 26, 26 \n\t" \ + " li 27, 27 \n\t" \ + " li 28, 28 \n\t" \ + " li 29, 29 \n\t" \ + " li 30, 30 \n\t" \ + " li 31, 31 \n\t" \ + " \n\t" \ + " sc \n\t" \ + " nop \n\t" \ + " \n\t" \ + " cmpwi 0, 1 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 2, 2 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 3, 3 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 4, 4 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 5, 5 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 6, 6 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 7, 7 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 8, 8 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 9, 9 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 10, 10 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 11, 11 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 12, 12 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 13, 13 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 14, 14 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 15, 15 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 16, 16 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 17, 17 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 18, 18 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 19, 19 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 20, 20 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 21, 21 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 22, 22 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 23, 23 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 24, 24 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 25, 25 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 26, 26 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 27, 27 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 28, 28 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 29, 29 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 30, 30 \n\t" \ + " bne RegTest1Fail \n\t" \ + " cmpwi 31, 31 \n\t" \ + " bne RegTest1Fail \n\t" \ + " \n\t" \ + " mfspr 0, 256 #USPRG0 \n\t" \ + " cmpwi 0, 301 \n\t" \ + " bne RegTest1Fail \n\t" \ + " mfspr 0, 8 #LR \n\t" \ + " cmpwi 0, 501 \n\t" \ + " bne RegTest1Fail \n\t" \ + " mfspr 0, 1 #XER \n\t" \ + " cmpwi 0, 4 \n\t" \ + " bne RegTest1Fail \n\t" \ + " \n\t" \ + " bl prvRegTest1Pass \n\t" \ + " b RegTest1Start \n\t" \ + " \n\t" \ + "RegTest1Fail: \n\t" \ + " \n\t" \ + " \n\t" \ + " bl prvRegTestFail \n\t" \ + " b RegTest1Start \n\t" \ + ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTask2( void *pvParameters ) +{ + /* The second register test task as described at the top of this file. + Note that this task fills the registers with different values to the + first register test task. */ + asm volatile + ( + "RegTest2Start: \n\t" \ + " \n\t" \ + " li 0, 300 \n\t" \ + " mtspr 256, 0 #USPRG0 \n\t" \ + " li 0, 500 \n\t" \ + " mtspr 8, 0 #LR \n\t" \ + " li 0, 4 \n\t" \ + " mtspr 1, 0 #XER \n\t" \ + " \n\t" \ + " li 0, 11 \n\t" \ + " li 2, 12 \n\t" \ + " li 3, 13 \n\t" \ + " li 4, 14 \n\t" \ + " li 5, 15 \n\t" \ + " li 6, 16 \n\t" \ + " li 7, 17 \n\t" \ + " li 8, 18 \n\t" \ + " li 9, 19 \n\t" \ + " li 10, 110 \n\t" \ + " li 11, 111 \n\t" \ + " li 12, 112 \n\t" \ + " li 13, 113 \n\t" \ + " li 14, 114 \n\t" \ + " li 15, 115 \n\t" \ + " li 16, 116 \n\t" \ + " li 17, 117 \n\t" \ + " li 18, 118 \n\t" \ + " li 19, 119 \n\t" \ + " li 20, 120 \n\t" \ + " li 21, 121 \n\t" \ + " li 22, 122 \n\t" \ + " li 23, 123 \n\t" \ + " li 24, 124 \n\t" \ + " li 25, 125 \n\t" \ + " li 26, 126 \n\t" \ + " li 27, 127 \n\t" \ + " li 28, 128 \n\t" \ + " li 29, 129 \n\t" \ + " li 30, 130 \n\t" \ + " li 31, 131 \n\t" \ + " \n\t" \ + " cmpwi 0, 11 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 2, 12 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 3, 13 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 4, 14 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 5, 15 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 6, 16 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 7, 17 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 8, 18 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 9, 19 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 10, 110 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 11, 111 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 12, 112 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 13, 113 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 14, 114 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 15, 115 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 16, 116 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 17, 117 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 18, 118 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 19, 119 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 20, 120 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 21, 121 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 22, 122 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 23, 123 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 24, 124 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 25, 125 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 26, 126 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 27, 127 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 28, 128 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 29, 129 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 30, 130 \n\t" \ + " bne RegTest2Fail \n\t" \ + " cmpwi 31, 131 \n\t" \ + " bne RegTest2Fail \n\t" \ + " \n\t" \ + " mfspr 0, 256 #USPRG0 \n\t" \ + " cmpwi 0, 300 \n\t" \ + " bne RegTest2Fail \n\t" \ + " mfspr 0, 8 #LR \n\t" \ + " cmpwi 0, 500 \n\t" \ + " bne RegTest2Fail \n\t" \ + " mfspr 0, 1 #XER \n\t" \ + " cmpwi 0, 4 \n\t" \ + " bne RegTest2Fail \n\t" \ + " \n\t" \ + " bl prvRegTest2Pass \n\t" \ + " b RegTest2Start \n\t" \ + " \n\t" \ + "RegTest2Fail: \n\t" \ + " \n\t" \ + " \n\t" \ + " bl prvRegTestFail \n\t" \ + " b RegTest2Start \n\t" \ + ); +} +/*-----------------------------------------------------------*/ + +/* This hook function will get called if there is a suspected stack overflow. +An overflow can cause the task name to be corrupted, in which case the task +handle needs to be used to determine the offending task. */ +void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName ); +void vApplicationStackOverflowHook( xTaskHandle xTask, signed portCHAR *pcTaskName ) +{ +/* To prevent the optimiser removing the variables. */ +volatile xTaskHandle xTaskIn = xTask; +volatile signed portCHAR *pcTaskNameIn = pcTaskName; + + /* The following three calls are simply to stop compiler warnings about the + functions not being used - they are called from the inline assembly. */ + prvRegTest1Pass(); + prvRegTest2Pass(); + prvRegTestFail(); + + for( ;; ); +} + + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c new file mode 100644 index 000000000..ac575c096 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/partest/partest.c @@ -0,0 +1,168 @@ +/* + FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo application includes. */ +#include "partest.h" + +/* Library includes. */ +#include "xparameters.h" +#include "xgpio_l.h" + +/* Misc hardware specific definitions. */ +#define partstALL_AS_OUTPUT 0x00 +#define partstCHANNEL_1 0x01 +#define partstMAX_4BIT_LED 0x03 + +/* The outputs are split into two IO sections, these variables maintain the +current value of either section. */ +static unsigned portBASE_TYPE uxCurrentOutput4Bit, uxCurrentOutput5Bit; + +/*-----------------------------------------------------------*/ +/* + * Setup the IO for the LED outputs. + */ +void vParTestInitialise( void ) +{ + /* Set both sets of LED's on the demo board to outputs. */ + XGpio_mSetDataDirection( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); + XGpio_mSetDataDirection( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, partstALL_AS_OUTPUT ); + + /* Start with all outputs off. */ + uxCurrentOutput4Bit = 0; + XGpio_mSetDataReg( XPAR_LEDS_4BIT_BASEADDR, partstCHANNEL_1, 0x00 ); + uxCurrentOutput5Bit = 0; + XGpio_mSetDataReg( XPAR_LEDS_POSITIONS_BASEADDR, partstCHANNEL_1, 0x00 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue ) +{ +unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; + + portENTER_CRITICAL(); + { + /* Which IO section does the LED being set/cleared belong to? The + 4 bit or 5 bit outputs? */ + if( uxLED <= partstMAX_4BIT_LED ) + { + uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; + puxCurrentValue = &uxCurrentOutput5Bit; + } + else + { + uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; + puxCurrentValue = &uxCurrentOutput4Bit; + uxLED -= partstMAX_4BIT_LED; + } + + /* Setup the bit mask accordingly. */ + uxLED = 0x01 << uxLED; + + /* Maintain the current output value. */ + if( xValue ) + { + *puxCurrentValue |= uxLED; + } + else + { + *puxCurrentValue &= ~uxLED; + } + + /* Write the value to the port. */ + XGpio_mSetDataReg( uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); + } + portEXIT_CRITICAL(); +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) +{ +unsigned portBASE_TYPE uxBaseAddress, *puxCurrentValue; + + portENTER_CRITICAL(); + { + /* Which IO section does the LED being toggled belong to? The + 4 bit or 5 bit outputs? */ + if( uxLED <= partstMAX_4BIT_LED ) + { + + uxBaseAddress = XPAR_LEDS_4BIT_BASEADDR; + puxCurrentValue = &uxCurrentOutput5Bit; + } + else + { + uxBaseAddress = XPAR_LEDS_POSITIONS_BASEADDR; + puxCurrentValue = &uxCurrentOutput4Bit; + uxLED -= partstMAX_4BIT_LED; + } + + /* Setup the bit mask accordingly. */ + uxLED = 0x01 << uxLED; + + /* Maintain the current output value. */ + if( *puxCurrentValue & uxLED ) + { + *puxCurrentValue &= ~uxLED; + } + else + { + *puxCurrentValue |= uxLED; + } + + /* Write the value to the port. */ + XGpio_mSetDataReg(uxBaseAddress, partstCHANNEL_1, *puxCurrentValue ); + } + portEXIT_CRITICAL(); +} + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c new file mode 100644 index 000000000..3e5477908 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/RTOSDemo/serial/serial.c @@ -0,0 +1,227 @@ +/* + FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + *************************************************************************** + * * + * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * + * and even write all or part of your application on your behalf. * + * See http://www.OpenRTOS.com for details of the services we provide to * + * expedite your project. * + * * + *************************************************************************** + *************************************************************************** + + Please ensure to read the configuration and relevant port sections of the + online documentation. + + http://www.FreeRTOS.org - Documentation, latest information, license and + contact details. + + http://www.SafeRTOS.com - A version that is certified for use in safety + critical systems. + + http://www.OpenRTOS.com - Commercial support, development, porting, + licensing and training services. +*/ + + +/* + BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART +*/ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "queue.h" +#include "task.h" + +/* Demo application includes. */ +#include "serial.h" + +/* Library includes. */ +#include "xparameters.h" +#include "xuartlite.h" +#include "xuartlite_l.h" + +/*-----------------------------------------------------------*/ + +/* Queues used to hold received characters, and characters waiting to be +transmitted. */ +static xQueueHandle xRxedChars; +static xQueueHandle xCharsForTx; + +/* Structure that maintains information on the UART being used. */ +static XUartLite xUART; + +/* + * Sample UART interrupt handler. Note this is used to demonstrate the kernel + * features and test the port - it is not intended to represent an efficient + * implementation. + */ +static void vSerialISR( XUartLite *pxUART ); + +/*-----------------------------------------------------------*/ + +xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) +{ + /* NOTE: The baud rate used by this driver is determined by the hardware + parameterization of the UART Lite peripheral, and the baud value passed to + this function has no effect. */ + ( void ) ulWantedBaud; + + /* Create the queues used to hold Rx and Tx characters. */ + xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); + + /* Only initialise the UART if the queues were created correctly. */ + if( ( xRxedChars != NULL ) && ( xCharsForTx != NULL ) ) + { + + XUartLite_Initialize( &xUART, XPAR_RS232_UART_DEVICE_ID ); + XUartLite_ResetFifos( &xUART ); + XUartLite_DisableInterrupt( &xUART ); + + if( xPortInstallInterruptHandler( XPAR_XPS_INTC_0_RS232_UART_INTERRUPT_INTR, ( XInterruptHandler )vSerialISR, (void *)&xUART ) == pdPASS ) + { + /* xPortInstallInterruptHandler() could fail if + vPortSetupInterruptController() has not been called prior to this + function. */ + XUartLite_EnableInterrupt( &xUART ); + } + } + + /* There is only one port so the handle is not used. */ + return ( xComPortHandle ) 0; +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) +{ + /* The port handle is not required as this driver only supports one UART. */ + ( void ) pxPort; + + /* Get the next character from the buffer. Return false if no characters + are available, or arrive before xBlockTime expires. */ + if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) + { + return pdTRUE; + } + else + { + return pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) +{ +portBASE_TYPE xReturn = pdTRUE; + + portENTER_CRITICAL(); + { + /* If the UART FIFO is full we can block posting the new data on the + Tx queue. */ + if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) ) + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + } + /* Otherwise, if there is data already in the queue we should add the + new data to the back of the queue to ensure the sequencing is + maintained. */ + else if( uxQueueMessagesWaiting( xCharsForTx ) ) + { + if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) + { + xReturn = pdFAIL; + } + } + /* If the UART FIFO is not full and there is no data already in the + queue we can write directly to the FIFO without disrupting the + sequence. */ + else + { + XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar ); + } + } + portEXIT_CRITICAL(); + + return xReturn; +} +/*-----------------------------------------------------------*/ + +void vSerialClose( xComPortHandle xPort ) +{ + /* Not supported as not required by the demo application. */ + ( void ) xPort; +} +/*-----------------------------------------------------------*/ + +static void vSerialISR( XUartLite *pxUART ) +{ +unsigned portLONG ulISRStatus; +portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE, lDidSomething; +portCHAR cChar; + + do + { + lDidSomething = pdFALSE; + + ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET ); + + if( ( ulISRStatus & XUL_SR_RX_FIFO_VALID_DATA ) != 0 ) + { + /* A character is available - place it in the queue of received + characters. This might wake a task that was blocked waiting for + data. */ + cChar = ( portCHAR ) XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET ); + xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken ); + lDidSomething = pdTRUE; + } + + if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 ) + { + /* There is space in the FIFO - if there are any characters queue for + transmission they can be sent to the UART now. This might unblock a + task that was waiting for space to become available on the Tx queue. */ + if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE ) + { + XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar ); + lDidSomething = pdTRUE; + } + } + } while( lDidSomething == pdTRUE ); + + /* If we woke any tasks we may require a context switch. */ + if( xHigherPriorityTaskWoken ) + { + portYIELD_FROM_ISR(); + } +} + + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_BifShapes.xsl b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_BifShapes.xsl new file mode 100644 index 000000000..e3f4c3fbc --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtSVG_BifShapes.xsl @@ -0,0 +1,211 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ stroke: none; + font-size: 7pt; + font-style: italic; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.buslabel { + fill: #CC3333; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.iplabel { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: italic; + font-weight: 900; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.iptype { + fill: #AA0017; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.portlabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmMHeader { + fill: #FFFFFF; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmSHeader { + fill: #810017; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.proclabel { + fill: #810017; + stroke: none; + font-size: 14pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.opblabel { + fill: #339900; + stroke: none; + font-size: 11pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.lmblabel { + fill: #9999FF; + stroke: none; + font-size: 11pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.dbglabel { + fill: #555555; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + text.iopnumb { + fill: #555555; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl new file mode 100644 index 000000000..f91415383 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLDatasheet.xsl @@ -0,0 +1,1211 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Table of Contents + + + + + + + + + + + + + +EDK Project Report + + + + + + + + + + +Block Diagram + + + + + + + + + + + BlockDiagram + +

+

+ +

+ + + + + + + + + + EDK PROJECT REPORT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ Printable Version +
+ + + + +

+

+ +
+ + + + +

+

+ BlockDiagram +
+ + + + +

+

+ +
+ + + + +

+ + + + + + + + + + + + +
+ +
+ +
+
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+ +
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+
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+ +
+
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+ +
+
+ + + + +

+ + + + + + + +
+ +
+
+ + + + +

+

+ +
+

+

+ + + + + +
line
+ + + www.xilinx.com +

+ 1-800-255-7778 +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TABLE OF CONTENTS
+

+ Overview + +

+ Block Diagram + +

+ External Ports + + + +

+ + + Processors + + + Processor + + + + +

+     + +

+           memory map + + + + +

+ Debuggers + + +

+     + + + + +

+ Interrupt Controllers + + +

+     + + + + +

+ Busses + + +

+     + + + + +

+ Bridges + + +

+     + + + + +

+ Memory + + +

+     + + + + +

+ Memory Controllers + + +

+     + + + + +

+ Peripherals + + +

+     + + + + +

+ IP + + +

+     + + + +

+ Timing Information +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ Overview +
+ Generated on + + +
+ Source + + + + + +
+ EDK Version + + + + + + NA + +
+ FPGA Family + + + + + + NA + +
+ Device + + + + + + - + +
+ # IP Instantiated + + +
+ # Processors + + +
+ # Busses + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EXTERNAL PORTS
+ + These are the external ports defined in the MHS file. + +
+ Attributes Key +

+ The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file +

+ CLK +   indicates Clock ports, (SIGIS = CLK)  +

+ INTR +   indicates Interrupt ports,(SIGIS = INTR)  +

+ RESET +   indicates Reset ports, (SIGIS = RST)  +

+ BUF or REG +   Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
+ + :1 +  CLK  +  RESET  +  INTR  +  BUF  +  REG  +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
+ + :1 +  CLK  +  RESET  +  INTR  +  BUF  +  REG  +
+ 		+   + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
+ + :1 +  CLK  +  RESET  +  INTR  +  BUF  +  REG  +
 
+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Post Synthesis Clock Limits
+ + No clocks could be identified in the design. Run platgen to generate synthesis information. + + + + These are the post synthesis clock frequencies. The critical frequencies are marked with + + + green. + +

+ + The values reported here are post synthesis estimates calculated for each individual module. These values will change after place and route is performed on the entire system. + +
MODULECLK PortMAX FREQ
+ + + + + + + + + + + +
+ + + + + + +

+

+

+ + + + + + + + +
TOCTOP
+ + + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl new file mode 100644 index 000000000..4e7beaa51 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLIPSection.xsl @@ -0,0 +1,611 @@ + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + +    + + +

+ + + + + +

+

+

+
+ {@INSTANCE} IP Image + + +

+

+
+ +
+ +

+

+ + + + + + + + + + + 1 + 0 + + + + + + + + + + 1 + 0 + + + + + + + 4 + 2 + + + + 2 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
General
IP Core + + + + + + + + + + +
Version
Driver + + API + +
License
TYPE + +
EXPIRES ON + +
Parameters
+ + These are parameters set for this module. + + Refer to the IP documentation for complete information about module parameters. + + +

+ + Parameters marked with + + yellow + + indicate parameters set by the user. + +

+ + Parameters marked with + + blue + + indicate parameters set by the system. + +
NameValue
+ + + + +
+ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
+ + + + +
+ + + + +
+ 		+ + +
 
+ 		+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameValue
+ + + + +
+ + + + +
 
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Post Synthesis Device Utilization
+ + Device utilization information is not available for this IP. Run platgen to generate synthesis information. + +
Resource TypeUsedAvailablePercent
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + NA + + + + + + + + NA + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PORT LIST
+ + The ports listed here are only those connected in the MHS file. + + Refer to the IP documentation for complete information about module ports. + + +
#NAMEDIR[LSB:MSB]SIGNAL
:1
+ Bus Interfaces +
MASTERSHIPNAMESTDBUSP2P
Bus Connections
TYPENAMEBIF
+ Interrupt Priorities +
PrioritySIGMODULE
+ + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl new file mode 100644 index 000000000..96e9f0cc7 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLMemoryMap.xsl @@ -0,0 +1,86 @@ + + + + + +]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ■ +   + + + + + ■ + + +   + + + + + + + + + + + + +
+ + MEMORY MAP +
D=DATA ADDRESSABLE    I=INSTRUCTION ADDRESSABLE
DIBASEHIGHMODULE
+ + : + +
+ + + + + + + + + + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl new file mode 100644 index 000000000..862b7107b --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/MdtXdsGen_HTMLTOCTree.xsl @@ -0,0 +1,235 @@ + + + + + + +Table of Contents + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TABLE OF CONTENTS
+

+ Overview + +

+ Block Diagram + +

+ External Ports + +

+ + + +
+ + Processors  + + + Processor  + + +
+ + + + +    

+ +           memory map

+ + + + + + +
+ Debuggers  + +
+ + + + +    

+ + + + + + +
+ Interrupt Controllers  + +
+ + + + +    

+ + + + + +
+ Busses  + +
+ + + + +    

+ + + + + +
+ Bridges  + +
+ + + +    

+ + + + + +
+ Memory  + +
+ + + +    

+ + + + + +
+ Memory Controllers  + +
+ + + +    

+ + + + + +
+ Peripherals  + +
+ + + +    

+ + + + + +
+ IP  + +
+ + + +    

+ + + + + Timing Information

+ + +
+ + + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd new file mode 100644 index 000000000..110f5ced5 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/svg10.dtd @@ -0,0 +1,1704 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/system_shapes.xml b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/system_shapes.xml new file mode 100644 index 000000000..132e36c9a --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/.dswkshop/system_shapes.xml @@ -0,0 +1,1821 @@ + + + + + + PowerPC 405 Virtex-4 + A wrapper to instantiate the PowerPC 405 Processor Block primitive + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PowerPC JTAG Controller + JTAGPPC wrapper allows the PowerPC to connect to the JTAG chain of the FPGA. + + + + + + + + + + + + + + + + + + + + + + + + Processor Local Bus (PLB) 4.6 + 'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature' + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XPS UART (Lite) + Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus. + + + + + + + + + + + + + + + + + + Serial Data In + + + Serial Data Out + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XPS General Purpose IO + General Purpose Input/Output (GPIO) core for the PLBV46 bus. + + + + + + + + + + + + + + + + + + + + + + + + GPIO1 Data IO + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XPS General Purpose IO + General Purpose Input/Output (GPIO) core for the PLBV46 bus. + + + + + + + + + + + + + + + + + + + + + + + + GPIO1 Data IO + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XPS System ACE Interface Controller(Compact Flash) + Interface between the PLBV46 and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral + + + + + + + + + + + + + + Clock Input + + + Address Input + + + Data Input/Output + + + Active LOW Chip Enable + + + Active LOW Output Enable + + + Active LOW Write Enable + + + Active high Interrupt Output + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XPS Multi-Channel External Memory Controller(SRAM/Flash) + Xilinx Multi-CHannel (MCH) PLBV46 external memory controller + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Memory Address Bus + + + Memory Byte Enable + + + Memory Write Enable + + + Memory Data Bus + + + Memory Output Enable + + + Memory Chip Enable Active Low + + + Memory Advanced Burst Address/Load New Address + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Utility Bus Split + Bus splitting primitive + + + + + + + + + Clock Generator + Clock generator for processor system. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Processor System Reset Module + Reset management module + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + XPS Interrupt Controller + intc core attached to the PLBV46 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Fabric Co-processor Bus (FCB) + Fabric Co-processor Bus (FCB) connects one or more FPGA fabric accelerator slaves to the Auxiliary Processor Unit (APU) controller in a Virtex-4 PowerPC 405. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + APU Floating Point Unit + Floating Point Unit via Auxilary Processor Unit. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/bitinit.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/bitinit.opt new file mode 100644 index 000000000..3645236a6 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/bitinit.opt @@ -0,0 +1 @@ + -pe ppc405_0 $(PPC405_0_BOOTLOOP) diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/libgen.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/libgen.opt new file mode 100644 index 000000000..77b154845 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/libgen.opt @@ -0,0 +1 @@ + -p virtex4 diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/platgen.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/platgen.opt new file mode 100644 index 000000000..25299b7db --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/platgen.opt @@ -0,0 +1,2 @@ + -p xc4vfx12ff668-10 -lang vhdl + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt new file mode 100644 index 000000000..2979e4328 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/rtosdemo_compiler.opt @@ -0,0 +1,20 @@ +ppc405_0 +RTOSDEMO_SOURCES = RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../Common/Minimal/countsem.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/recmutex.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S RTOSDemo/../../../Source/portable/MemMang/heap_2.c RTOSDemo/flop/flop.c RTOSDemo/flop/flop-reg-test.c +RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h +RTOSDEMO_CC = powerpc-eabi-gcc +RTOSDEMO_CC_SIZE = powerpc-eabi-size +RTOSDEMO_CC_OPT = -O0 +RTOSDEMO_CFLAGS = -I./RTOSDemo/flop -I../../Source/portable/GCC/PPC405_Xilinx -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -Wextra +RTOSDEMO_CC_SEARCH = # -B +RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L +RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ # -I +RTOSDEMO_LFLAGS = # -l +RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo_linker_script.ld +RTOSDEMO_CC_DEBUG_FLAG = -g +RTOSDEMO_CC_PROFILE_FLAG = # -pg +RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi +RTOSDEMO_CC_INFERRED_FLAGS= -mfpu=sp_full +RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= +RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= +RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= + $(RTOSDEMO_CC_INFERRED_FLAGS) \ diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/simgen.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/simgen.opt new file mode 100644 index 000000000..970a4ea82 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/simgen.opt @@ -0,0 +1 @@ + -p virtex4 -lang vhdl -pe ppc405_0 $(PPC405_0_BOOTLOOP) -s mti -X C:/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/ -E C:/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/ diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/system.gui b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/system.gui new file mode 100644 index 000000000..9ccbebeab --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/system.gui @@ -0,0 +1,101 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/system_routed b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/system_routed new file mode 100644 index 000000000..e69de29bb diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt new file mode 100644 index 000000000..39ff0ed04 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/testapp_peripheral_compiler.opt @@ -0,0 +1,20 @@ +ppc405_0 +TESTAPP_PERIPHERAL_SOURCES = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xintc_tapp_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_selftest_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xuartlite_intr_tapp_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xgpio_tapp_example.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/xsysace_selftest_example.c +TESTAPP_PERIPHERAL_HEADERS = /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/intc_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/uartlite_intr_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/gpio_header.h /cygdrive/c//E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/sysace_header.h +TESTAPP_PERIPHERAL_CC = powerpc-eabi-gcc +TESTAPP_PERIPHERAL_CC_SIZE = powerpc-eabi-size +TESTAPP_PERIPHERAL_CC_OPT = -O0 +TESTAPP_PERIPHERAL_CFLAGS = +TESTAPP_PERIPHERAL_CC_SEARCH = # -B +TESTAPP_PERIPHERAL_LIBPATH = -L./ppc405_0/lib/ # -L +TESTAPP_PERIPHERAL_INCLUDES = -I./ppc405_0/include/ -ITestApp_Peripheral/src/ # -I +TESTAPP_PERIPHERAL_LFLAGS = # -l +TESTAPP_PERIPHERAL_LINKER_SCRIPT = /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy2/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/TestApp_Peripheral/src/TestApp_Peripheral_LinkScr.ld +TESTAPP_PERIPHERAL_CC_DEBUG_FLAG = -g +TESTAPP_PERIPHERAL_CC_PROFILE_FLAG = # -pg +TESTAPP_PERIPHERAL_CC_GLOBPTR_FLAG= # -msdata=eabi +TESTAPP_PERIPHERAL_CC_INFERRED_FLAGS= -mfpu=sp_full +TESTAPP_PERIPHERAL_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= +TESTAPP_PERIPHERAL_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= +TESTAPP_PERIPHERAL_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= + $(TESTAPP_PERIPHERAL_CC_INFERRED_FLAGS) \ diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/vpgen.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/vpgen.opt new file mode 100644 index 000000000..8ea8f6640 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/vpgen.opt @@ -0,0 +1 @@ + -p xc4vfx12ff668-10 diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xplorer.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xplorer.opt new file mode 100644 index 000000000..37e5b1190 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xplorer.opt @@ -0,0 +1 @@ +-device xc4vfx12ff668-10data/system.ucf7 0 diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt new file mode 100644 index 000000000..33391f035 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/__xps/xpsxflow.opt @@ -0,0 +1 @@ +-device xc4vfx12ff668-10data/system.ucf 0 diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd new file mode 100644 index 000000000..110f5ced5 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/svg10.dtd @@ -0,0 +1,1704 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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font-family: Verdana Arial Helvetica sans-serif; + } + + text.mpmctitle { + fill: #FFFFFF; + stroke: none; + font-size: 16pt; + font-weight: bold; + text-anchor: middle; + font-family: Arial Verdana Helvetica sans-serif; + } + + text.mpmcbiflabel { + fill: #FFFFFF; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + + } + + text.buslabel { + fill: #CC3333; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.iplabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: 800; + text-anchor: middle; + font-family: Courier Arial Helvetica sans-serif; + } + + text.iptype { + fill: #AA0017; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: start; + font-family: Times Arial Helvetica sans-serif; + } + + text.procclass { + fill: #000000; + stroke: none; + font-size: 7pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + + text.portlabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ipdbiflbl { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: bold; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmMHeader { + fill: #FFFFFF; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mmSHeader { + fill: #810017; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + text.dbglabel { + fill: #555555; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Times Arial Helvetica sans-serif; + } + + text.iopnumb { + fill: #555555; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.ioplblgrp { + fill: #000088; + stroke: none; + font-size: 10pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + + tspan.iopgrp { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + baseline-shift:super; + font-family: Arial Courier san-serif; + } + + + text.biflabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: 900; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + + } + + text.p2pbuslabel { + fill: #000000; + stroke: none; + font-size: 10pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + writing-mode: tb; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.mpbuslabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + writing-mode: tb; + font-family: Verdana Arial Helvetica sans-serif; + } + + + text.sharedbuslabel { + fill: #000000; + stroke: none; + font-size: 10pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + + text.bciplabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Courier Arial Helvetica sans-serif; + } + + text.bciptype { + fill: #AA0017; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.splitbustxt { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: normal; + font-weight: bold; + text-anchor: middle; + font-family: sans-serif; + } + + text.horizp2pbuslabel { + fill: #000000; + stroke: none; + font-size: 6pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + + + text.keytitle { + fill: #AA0017; + stroke: none; + font-size: 12pt; + font-weight: bold; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.keyheader { + fill: #000000; + stroke: none; + font-size: 10pt; + font-weight: bold; + text-anchor: middle; + font-family: Arial Helvetica sans-serif; + } + + text.keylabel { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.keylblul { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + text-decoration: underline; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.specsheader { + fill: #000000; + stroke: none; + font-size: 10pt; + font-weight: bold; + text-anchor: start; + font-family: Arial Helvetica sans-serif; + } + + text.specsvalue { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: start; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.specsvaluemid { + fill: #000000; + stroke: none; + font-size: 8pt; + font-style: italic; + font-weight: bold; + text-anchor: middle; + font-family: Verdana Arial Helvetica sans-serif; + } + + text.intrsymbol { + fill: #000000; + stroke: none; + font-size: 8pt; + font-weight: bold; + text-anchor: start; + font-family: Arial Helvetica sans-serif; + } + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.html b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.html new file mode 100644 index 000000000..0f88d6224 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.html @@ -0,0 +1,229 @@ + + + +Block Diagram + + +

+ + + + + + + + + +
EXTERNAL PORTS
+ These are the external ports defined in the MHS file. +
+Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)  +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
+ +fpga_0_RS232_Uart_RX_pinI1fpga_0_RS232_Uart_RX
+ +fpga_0_RS232_Uart_TX_pinO1fpga_0_RS232_Uart_TX
+ +fpga_0_LEDs_4Bit_GPIO_IO_pinIO0:3fpga_0_LEDs_4Bit_GPIO_IO
+ +fpga_0_LEDs_Positions_GPIO_IO_pinIO0:4fpga_0_LEDs_Positions_GPIO_IO
+ +fpga_0_SysACE_CompactFlash_SysACE_CLK_pinI1fpga_0_SysACE_CompactFlash_SysACE_CLK
+ +fpga_0_SysACE_CompactFlash_SysACE_MPA_pinO6:1fpga_0_SysACE_CompactFlash_SysACE_MPA
+ +fpga_0_SysACE_CompactFlash_SysACE_MPD_pinIO15:0fpga_0_SysACE_CompactFlash_SysACE_MPD
+ +fpga_0_SysACE_CompactFlash_SysACE_CEN_pinO1fpga_0_SysACE_CompactFlash_SysACE_CEN
+ +fpga_0_SysACE_CompactFlash_SysACE_OEN_pinO1fpga_0_SysACE_CompactFlash_SysACE_OEN
+ +fpga_0_SysACE_CompactFlash_SysACE_WEN_pinO1fpga_0_SysACE_CompactFlash_SysACE_WEN
+ +fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pinI1fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#NAMEDIR[LSB:MSB]SIGATTRIBUTES
+ +fpga_0_SRAM_Mem_A_pinO9:29fpga_0_SRAM_Mem_A
+ +fpga_0_SRAM_Mem_BEN_pinO0:3fpga_0_SRAM_Mem_BEN
+ +fpga_0_SRAM_Mem_WEN_pinO1fpga_0_SRAM_Mem_WEN
+ +fpga_0_SRAM_Mem_DQ_pinIO0:31fpga_0_SRAM_Mem_DQ
+ +fpga_0_SRAM_Mem_OEN_pinO0:0fpga_0_SRAM_Mem_OEN
+ +fpga_0_SRAM_Mem_CEN_pinO0:0fpga_0_SRAM_Mem_CEN
+ +fpga_0_SRAM_Mem_ADV_LDN_pinO1fpga_0_SRAM_Mem_ADV_LDN
+ +fpga_0_SRAM_CLOCKO1sys_clk_s
+ +sys_clk_pinI1dcm_clk_s CLK 
+ +sys_rst_pinI1sys_rst_s RESET 
 
+
+ + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.svg b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.svg new file mode 100644 index 000000000..5991ebf29 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/blkdiagram/system.svg @@ -0,0 +1,1473 @@ + + + + + + + + + x + + + + + + x + + + + + y + x + + + + + KEY + + SYMBOLS + + bus interface + + shared bus + Bus connections + + master or initiator + + slave or target + + master slave + + monitor + External Ports + + input + + output + + inout + Interrupts + + interrupt + controller + + interrupted + processor + + interrupt + source + x = controller ID + y = priority + + COLORS + Bus Standards + + DCR + + FCB + + FSL + + LMB + + OPB + + PLB + + SOCM + + XIL (prefix) P2P + + GEN. P2P, USER, etc + + + + + SPECS + + EDK VERSION + 10.1.01 + + ARCH + virtex4 + + PART + xc4vfx12ff668-10 + + GENERATED + Sun May 11 14:31:02 2008 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + plb + + + + + + + + + + + A + xps_gpio + LEDs_4Bit + + + SPLB + + + + + + B + xps_gpio + LEDs_Positions + + + SPLB + + + + + + C + xps_uartlite + RS232_Uart + + + SPLB + + + 0 + 0 + + + + + + D + xps_mch_emc + SRAM + + + SPLB + + + + + + F + xps_sysace + SysACE_CompactFlash + + + SPLB + + + + + xps_intc + xps_intc_0 + + + SPLB + + + 0 + + + + + + + + + + + + + + + + + + + + + util_bus_split + SRAM_util_bus_split_0 + + E + + + + + clock_generator + clock_generator_0 + + G + + + + + + + + + + jtagppc_cntlr + jtagppc_0 + + + JTAG + + + + + proc_sys_reset + proc_sys_reset_0 + + H + + + RESE + + + + + apu_fpu + apu_fpu_0 + + + SFCB + + + + + ppc405_virtex4 + ppc405_0 + + + JTAG + + + IPLB0 + + + DPLB0 + + + RESE + + + MFCB + + + + 0 + + + + + + + + SLAVES OF plb + + PROCESSOR + + + + jtagppc_0_0 + + + + + + + + + + + + + + + + + + ppc_reset_bus + + + + + + + + fcb_v10_0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IP + + + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/data/system.ucf b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/data/system.ucf new file mode 100644 index 000000000..0b81c8ff8 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/data/system.ucf @@ -0,0 +1,398 @@ +############################################################################ +## This system.ucf file is generated by Base System Builder based on the +## settings in the selected Xilinx Board Definition file. Please add other +## user constraints to this file based on customer design specifications. +############################################################################ + +Net sys_clk_pin LOC=AE14; +Net sys_clk_pin IOSTANDARD = LVCMOS33; +Net sys_rst_pin LOC=D6; +Net sys_rst_pin PULLUP; +## System level constraints +Net sys_clk_pin TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; +Net sys_rst_pin TIG; +NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP"; +NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP"; +NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP"; +TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; +Net fpga_0_SRAM_CLOCK LOC=AF7; +Net fpga_0_SRAM_CLOCK SLEW = FAST; +Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_CLOCK DRIVE = 16; + +## IO Devices constraints + +#### Module RS232_Uart constraints + +Net fpga_0_RS232_Uart_RX_pin LOC=W2; +Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; +Net fpga_0_RS232_Uart_TX_pin LOC=W1; +Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33; + +#### Module LEDs_4Bit constraints + +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG; + +#### Module LEDs_Positions constraints + +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG; + +#### Module SysACE_CompactFlash constraints + +Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AF11; +Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=Y10; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AA10; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AC7; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=Y7; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AA9; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=Y9; +Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AB7; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AC9; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AB9; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AE6; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AD6; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AF9; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AE9; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AD8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AC8; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AF4; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AE4; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AD3; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AC3; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AF6; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AF5; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AA7; +Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AD5; +Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AA8; +Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=Y8; +Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AD4; +Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33; +Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin TIG; + +#### Module SRAM constraints + +Net fpga_0_SRAM_Mem_A_pin<29> LOC=Y1; +Net fpga_0_SRAM_Mem_A_pin<29> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<29> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<29> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<28> LOC=Y2; +Net fpga_0_SRAM_Mem_A_pin<28> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<28> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<28> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<27> LOC=AA1; +Net fpga_0_SRAM_Mem_A_pin<27> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<27> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<27> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<26> LOC=AB1; +Net fpga_0_SRAM_Mem_A_pin<26> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<26> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<26> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<25> LOC=AB2; +Net fpga_0_SRAM_Mem_A_pin<25> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<25> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<25> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<24> LOC=AC1; +Net fpga_0_SRAM_Mem_A_pin<24> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<24> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<24> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<23> LOC=AC2; +Net fpga_0_SRAM_Mem_A_pin<23> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<23> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<23> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<22> LOC=AD1; +Net fpga_0_SRAM_Mem_A_pin<22> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<22> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<22> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<21> LOC=AD2; +Net fpga_0_SRAM_Mem_A_pin<21> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<21> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<21> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<20> LOC=AE3; +Net fpga_0_SRAM_Mem_A_pin<20> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<20> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<20> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<19> LOC=AF3; +Net fpga_0_SRAM_Mem_A_pin<19> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<19> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<19> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<18> LOC=W3; +Net fpga_0_SRAM_Mem_A_pin<18> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<18> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<18> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<17> LOC=W6; +Net fpga_0_SRAM_Mem_A_pin<17> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<17> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<17> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<16> LOC=W5; +Net fpga_0_SRAM_Mem_A_pin<16> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<16> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<16> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<15> LOC=AA3; +Net fpga_0_SRAM_Mem_A_pin<15> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<15> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<15> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<14> LOC=AA4; +Net fpga_0_SRAM_Mem_A_pin<14> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<14> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<14> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<13> LOC=AB3; +Net fpga_0_SRAM_Mem_A_pin<13> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<13> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<13> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<12> LOC=AB4; +Net fpga_0_SRAM_Mem_A_pin<12> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<12> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<12> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<11> LOC=AC4; +Net fpga_0_SRAM_Mem_A_pin<11> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<11> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<11> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<10> LOC=AB5; +Net fpga_0_SRAM_Mem_A_pin<10> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<10> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<10> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<9> LOC=AC5; +Net fpga_0_SRAM_Mem_A_pin<9> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<9> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<9> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=Y6; +Net fpga_0_SRAM_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<3> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<3> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=Y5; +Net fpga_0_SRAM_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<2> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<2> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=Y4; +Net fpga_0_SRAM_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<1> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<1> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=Y3; +Net fpga_0_SRAM_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<0> DRIVE = 8; +Net fpga_0_SRAM_Mem_WEN_pin LOC=AB6; +Net fpga_0_SRAM_Mem_WEN_pin IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_WEN_pin SLEW = FAST; +Net fpga_0_SRAM_Mem_WEN_pin DRIVE = 8; +Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=AD13; +Net fpga_0_SRAM_Mem_DQ_pin<31> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<31> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=AC13; +Net fpga_0_SRAM_Mem_DQ_pin<30> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<30> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=AC15; +Net fpga_0_SRAM_Mem_DQ_pin<29> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<29> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=AC16; +Net fpga_0_SRAM_Mem_DQ_pin<28> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<28> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=AA11; +Net fpga_0_SRAM_Mem_DQ_pin<27> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<27> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=AA12; +Net fpga_0_SRAM_Mem_DQ_pin<26> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<26> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=AD14; +Net fpga_0_SRAM_Mem_DQ_pin<25> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<25> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=AC14; +Net fpga_0_SRAM_Mem_DQ_pin<24> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<24> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=AA13; +Net fpga_0_SRAM_Mem_DQ_pin<23> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<23> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=AB13; +Net fpga_0_SRAM_Mem_DQ_pin<22> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<22> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=AA15; +Net fpga_0_SRAM_Mem_DQ_pin<21> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<21> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=AA16; +Net fpga_0_SRAM_Mem_DQ_pin<20> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<20> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=AC11; +Net fpga_0_SRAM_Mem_DQ_pin<19> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<19> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=AC12; +Net fpga_0_SRAM_Mem_DQ_pin<18> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<18> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=AB14; +Net fpga_0_SRAM_Mem_DQ_pin<17> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<17> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=AA14; +Net fpga_0_SRAM_Mem_DQ_pin<16> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<16> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=D12; +Net fpga_0_SRAM_Mem_DQ_pin<15> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<15> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=E13; +Net fpga_0_SRAM_Mem_DQ_pin<14> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<14> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=C16; +Net fpga_0_SRAM_Mem_DQ_pin<13> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<13> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=D16; +Net fpga_0_SRAM_Mem_DQ_pin<12> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<12> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=D11; +Net fpga_0_SRAM_Mem_DQ_pin<11> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<11> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=C11; +Net fpga_0_SRAM_Mem_DQ_pin<10> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<10> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=E14; +Net fpga_0_SRAM_Mem_DQ_pin<9> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<9> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=D15; +Net fpga_0_SRAM_Mem_DQ_pin<8> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<8> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=D13; +Net fpga_0_SRAM_Mem_DQ_pin<7> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<7> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=D14; +Net fpga_0_SRAM_Mem_DQ_pin<6> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<6> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=F15; +Net fpga_0_SRAM_Mem_DQ_pin<5> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<5> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=F16; +Net fpga_0_SRAM_Mem_DQ_pin<4> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<4> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=F11; +Net fpga_0_SRAM_Mem_DQ_pin<3> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<3> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=F12; +Net fpga_0_SRAM_Mem_DQ_pin<2> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<2> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=F13; +Net fpga_0_SRAM_Mem_DQ_pin<1> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<1> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=F14; +Net fpga_0_SRAM_Mem_DQ_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<0> DRIVE = 12; +Net fpga_0_SRAM_Mem_OEN_pin<0> LOC=AC6; +Net fpga_0_SRAM_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_OEN_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_OEN_pin<0> DRIVE = 8; +Net fpga_0_SRAM_Mem_CEN_pin<0> LOC=V7; +Net fpga_0_SRAM_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_CEN_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_CEN_pin<0> DRIVE = 8; +Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=W4; +Net fpga_0_SRAM_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_ADV_LDN_pin SLEW = FAST; +Net fpga_0_SRAM_Mem_ADV_LDN_pin DRIVE = 8; + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/bitgen.ut b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/bitgen.ut new file mode 100644 index 000000000..976536332 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/bitgen.ut @@ -0,0 +1,20 @@ +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g DriveDone:No +-g StartUpClk:JTAGCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g DonePipe:No +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:NONE +#-m +-g Persist:No diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/download.cmd b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/download.cmd new file mode 100644 index 000000000..15728dcff --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/download.cmd @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 3 -file implementation/download.bit +program -p 3 +quit diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/fast_runtime.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/fast_runtime.opt new file mode 100644 index 000000000..6cc2599ab --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/fast_runtime.opt @@ -0,0 +1,82 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p ; # Partname to use - picked from xflow commandline +-nt timestamp; # NGO File generation. Regenerate only when + # source netlist is newer than existing + # NGO file (default) +-bm .bmm # Block RAM memory map file +; # User design - pick from xflow command line +-uc .ucf; # ucf constraints +.ngd; # Name of NGD file. Filebase same as design filebase +End Program ngdbuild + +# +# Options for Mapper +# +# Type "map -h " for a detailed list of map command line options +# +Program map +-o _map.ncd; # Output Mapped ncd file +-pr b; # Pack internal FF/latches into IOBs +#-fp .mfp; # Floorplan file +-ol high; +-timing; +.ngd; # Input NGD file +.pcf; # Physical constraints file +END Program map + +# +# Options for Post Map Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_map_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o _map.twr; # Output trace report file +-xml _map.twx; # Output XML version of the timing report +#-tsi _map.tsi; # Produce Timing Specification Interaction report +_map.ncd; # Input mapped ncd +.pcf; # Physical constraints file +END Program post_map_trce + +# +# Options for Place and Route +# +# Type "par -h" for a detailed list of par command line options +# +Program par +-w; # Overwrite existing placed and routed ncd +-ol high; # Overall effort level +_map.ncd; # Input mapped NCD file +.ncd; # Output placed and routed NCD +.pcf; # Input physical constraints file +END Program par + +# +# Options for Post Par Trace +# +# Type "trce -h" for a detailed list of trce command line options +# +Program post_par_trce +-e 3; # Produce error report limited to 3 items per constraint +#-o .twr; # Output trace report file +-xml .twx; # Output XML version of the timing report +#-tsi .tsi; # Produce Timing Specification Interaction report +.ncd; # Input placed and routed ncd +.pcf; # Physical constraints file +END Program post_par_trce + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt new file mode 100644 index 000000000..7adb1c0c5 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/etc/xmd_ppc405_0.opt @@ -0,0 +1 @@ +connect ppc hw -cable type xilinx_parallel port LPT1 frequency 2500000 -debugdevice cpunr 1 fpuType sp diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/platgen.opt b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/platgen.opt new file mode 100644 index 000000000..185473585 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/platgen.opt @@ -0,0 +1,5 @@ +-p +xc4vfx12ff668-10 +-lang +vhdl +system.mhs diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.bsb b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.bsb new file mode 100644 index 000000000..12d83ba87 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.bsb @@ -0,0 +1 @@ +„æÄ®Òôtt¦Êè¬ÊäæÒÞÜ@Db`\b\`bDvC„æÄ®Òôtt¦Êè„ÞÂäÈ@D°ÒØÒÜðD@D¬ÒäèÊð@h@š˜h`f@ŠìÂØêÂèÒÞÜ@ ØÂèÌÞäÚD@DbDv,„æÄ®ÒôttªàÈÂèʌ Ž‚@D‚¤†’¨Š†¨ª¤ŠD@DìÒäèÊðhDv,„æÄ®ÒôttªàÈÂèʌ Ž‚@DˆŠ¬’†Š¾¦’´ŠD@DðÆhìÌðbdDv%„æÄ®ÒôttªàÈÂèʌ Ž‚@D ‚†–‚ŽŠD@DÌÌllpDv&„æÄ®ÒôttªàÈÂèʌ Ž‚@D¦ ŠŠˆŽ¤‚ˆŠD@DZb`Dv3„æÄ®Òôtt¦Êè¦òæèÊÚ@DààÆh`j¾ìÒäèÊðh¾àØÄìhlD@Db\``\ÂDv,„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D„ª¦¾Œ¤Š¢D@Db``\``````Dv,„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D†˜–¾Œ¤Š¢D@Db``\``````Dv-„æÄ®ÒôttªàÈÂèʆØÞÆÖ@D ¤ž†¾Œ¤Š¢D@Dd``\``````Dv(„æÄ®ÒôttªàÈÂèʦòæèÊÚ@D¤¦¨¾ ž˜‚¤’¨²D@D`Dv1„æÄ®Òôtt‚ÈÈ äÞÆÊææÞä@DààÆh`j¾`D@DààÆh`j¾ìÒäèÊðhDv/„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D†‚†ŠD@DbDv3„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D†¾ª¦Š¾Œ ªD@DbDv:„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@DˆŠ„ªŽ¾’ŒD@DŒ Ž‚@”¨‚ŽDv6„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@Dˆž†š@¦’´ŠD@DœžœŠDv6„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@D’ž†š@¦’´ŠD@DœžœŠDv2„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@DààÆh`j¾`D@Dž†š¾žœ˜²D@D`Dv2„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¤¦dfd¾ªÂäèD@Dðàæ¾êÂäèØÒèÊDv9„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾„‚ªˆ¤‚¨ŠD@Drl``Dv7„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾ˆ‚¨‚¾„’¨¦D@DpDv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾žˆˆ¾ ‚¤’¨²D@D`Dv8„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D†¾ª¦Š¾ ‚¤’¨²D@D`Dv<„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@D’ž¨² ŠD@D°’˜¾ª‚¤¨¾¬bDv<„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¤¦dfd¾ªÂäèD@Dª¦Š¾’œ¨Š¤¤ª ¨D@D¨¤ªŠDv-„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾h„ÒèD@Dðàæ¾ÎàÒÞDv;„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾h„ÒèD@D’ž¨² ŠD@D°’˜¾Ž ’ž¾¬bDv2„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D˜Šˆæ¾ ÞæÒèÒÞÜæD@Dðàæ¾ÎàÒÞDv@„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D˜Šˆæ¾ ÞæÒèÒÞÜæD@D’ž¨² ŠD@D°’˜¾Ž ’ž¾¬bDv9„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¦ò悆Š¾†ÞÚàÂÆèŒØÂæÐD@Dðàæ¾æòæÂÆÊDvG„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¦ò悆Š¾†ÞÚàÂÆèŒØÂæÐD@D’ž¨² ŠD@D°’˜¾¦²¦‚†Š¾¬bDv+„æÄ®Òôtt‚ÈÈ ÊäÒàÐÊäÂØ@D¦¤‚šD@Dðàæ¾ÚÆоÊÚÆDv5„æÄ®ÒôttªàÈÂèʆÞÚàÞÜÊÜè@D¦¤‚šD@D’ž¨² ŠD@D°’˜¾Šš†¾¬bDv:„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†‚†Š¾†‚œˆ’ˆ‚¨Š¦D@D¦¤‚švDv8„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†¾†‚†Š¾„²¨Š¾¦’´ŠD@DblDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D†¾ˆ†‚†Š¾„²¨Š¾¦’´ŠD@DblDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@Dˆ†‚†Š¾†ž¤Š˜’¦¨D@Dv¦¤‚šDv9„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D’†‚†Š¾†ž¤Š˜’¦¨D@Dv¦¤‚šDv:„æÄ®ÒôttªàÈÂèʆÂÆÐÊ@DààÆh`j¾`D@D’œ¦¨‚œ†Š¾œ‚šŠD@DààÆh`j¾`Dv/„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾šŠš¨Š¦¨D@DŒ‚˜¦ŠDv1„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾ Š¤’ ¨Š¦¨D@D¨¤ªŠDv)„æÄ®ÒôttªàÈÂèʦ®@D¦®¾ŽŠœŠ¤‚¨Š¾¦®‚  ¦D@DDv7„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D’œ¦¨‚œ†Š¾œ‚šŠD@DààÆh`j¾`Dv0„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾„žž¨šŠšD@D¦¤‚šDv.„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾¦¨ˆ’œD@DœÞÜÊDv/„æÄ®ÒôttªàÈÂèʦ®@DààÆh`j¾`D@D¦®¾¦¨ˆžª¨D@DœÞÜÊDv@„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ˆ‚¨‚¾’œ¦D@D¦¤‚šDvK„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ˆ‚¨‚¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvC„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ ¤žŽ¤‚š¾’œ¦D@D¦¤‚šDvN„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾ ¤žŽ¤‚š¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvA„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¦¨‚†–¾’œ¦D@D¦¤‚šDvL„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¦¨‚†–¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤DvC„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¬Š†¨ž¤¦¾’œ¦D@D¦¤‚šDvN„æÄ®ÒôttªàÈÂèʨÊæè‚àà@D¨Êæè‚àྠÊäÒàÐÊäÂØD@D¦®¾¬Š†¨ž¤¦¾ ‚¤D@D†¾šŠš`¾„‚¦Š‚ˆˆ¤Dv \ No newline at end of file diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.make b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.make new file mode 100644 index 000000000..492fe8879 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.make @@ -0,0 +1,269 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\system.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +# Name of the Microprocessor system +# The hardware specification of the system is in file : +# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\system.mhs +# The software specification of the system is in file : +# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\system.mss + +include system_incl.make + +################################################################# +# PHONY TARGETS +################################################################# +.PHONY: dummy +.PHONY: netlistclean +.PHONY: bitsclean +.PHONY: simclean +.PHONY: vpclean + +################################################################# +# EXTERNAL TARGETS +################################################################# +all: + @echo "Makefile to build a Microprocessor system :" + @echo "Run make with any of the following targets" + @echo " " + @echo " netlist : Generates the netlist for the given MHS " + @echo " bits : Runs Implementation tools to generate the bitstream" + @echo " " + @echo " libs : Configures the sw libraries for this system" + @echo " program : Compiles the program sources for all the processor instances" + @echo " " + @echo " init_bram: Initializes bitstream with BRAM data" + @echo " ace : Generate ace file from bitstream and elf" + @echo " download : Downloads the bitstream onto the board" + @echo " " + @echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode" + @echo " simmodel : Generates HDL simulation models for chosen simulation mode" + @echo " behavioral_model : Generates behavioral HDL models with BRAM initialization" + @echo " structural_model : Generates structural simulation HDL models with BRAM initialization" + @echo " timing : Generates timing simulation HDL models with BRAM initialization" + @echo " vp : Generates virtual platform model" + @echo " " + @echo " netlistclean: Deletes netlist" + @echo " bitsclean: Deletes bit, ncd, bmm files" + @echo " hwclean : Deletes implementation dir" + @echo " libsclean: Deletes sw libraries" + @echo " programclean: Deletes compiled ELF files" + @echo " swclean : Deletes sw libraries and ELF files" + @echo " simclean : Deletes simulation dir" + @echo " vpclean : Deletes virtualplatform dir" + @echo " clean : Deletes all generated files/directories" + @echo " " + @echo " make : (Default)" + @echo " Creates a Microprocessor system using default initializations" + @echo " specified for each processor in MSS file" + + +bits: $(SYSTEM_BIT) + +ace: $(SYSTEM_ACE) + +netlist: $(POSTSYN_NETLIST) + +libs: $(LIBRARIES) + +program: $(ALL_USER_ELF_FILES) + +download: $(DOWNLOAD_BIT) dummy + @echo "*********************************************" + @echo "Downloading Bitstream onto the target board" + @echo "*********************************************" + impact -batch etc/download.cmd + +init_bram: $(DOWNLOAD_BIT) + +sim: $(DEFAULT_SIM_SCRIPT) + cd simulation/behavioral; \ + $(SIM_CMD) & + +simmodel: $(DEFAULT_SIM_SCRIPT) + +behavioral_model: $(BEHAVIORAL_SIM_SCRIPT) + +structural_model: $(STRUCTURAL_SIM_SCRIPT) + +vp: $(VPEXEC) + +clean: hwclean libsclean programclean simclean vpclean + rm -f _impact.cmd + rm -f *.log + +hwclean: netlistclean bitsclean + rm -rf implementation synthesis xst hdl + rm -rf xst.srp $(SYSTEM).srp + +netlistclean: + rm -f $(POSTSYN_NETLIST) + rm -f platgen.log + rm -f $(BMM_FILE) + +bitsclean: + rm -f $(SYSTEM_BIT) + rm -f implementation/$(SYSTEM).ncd + rm -f implementation/$(SYSTEM)_bd.bmm + rm -f implementation/$(SYSTEM)_map.ncd + +simclean: + rm -rf simulation/behavioral + rm -f simgen.log + +swclean: libsclean programclean + @echo "" + +libsclean: $(LIBSCLEAN_TARGETS) + rm -f libgen.log + +programclean: $(PROGRAMCLEAN_TARGETS) + +vpclean: + rm -rf virtualplatform + rm -f vpgen.log + +################################################################# +# SOFTWARE PLATFORM FLOW +################################################################# + + +$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt + @echo "*********************************************" + @echo "Creating software libraries..." + @echo "*********************************************" + libgen $(LIBGEN_OPTIONS) $(MSSFILE) + + +ppc405_0_libsclean: + rm -rf ppc405_0/ + +################################################################# +# SOFTWARE APPLICATION RTOSDEMO +################################################################# + +RTOSDemo_program: $(RTOSDEMO_OUTPUT) + +$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \ + $(LIBRARIES) __xps/rtosdemo_compiler.opt + @mkdir -p $(RTOSDEMO_OUTPUT_DIR) + $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \ + $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \ + $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS) + $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT) + @echo "" + +RTOSDemo_programclean: + rm -f $(RTOSDEMO_OUTPUT) + +################################################################# +# BOOTLOOP ELF FILES +################################################################# + + + +$(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP) + @mkdir -p $(BOOTLOOP_DIR) + cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP) + +################################################################# +# HARDWARE IMPLEMENTATION FLOW +################################################################# + + +$(BMM_FILE) \ +$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \ + $(CORE_STATE_DEVELOPMENT_FILES) + @echo "****************************************************" + @echo "Creating system netlist for hardware specification.." + @echo "****************************************************" + platgen $(PLATGEN_OPTIONS) $(MHSFILE) + +$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES) + @echo "Running synthesis..." + bash -c "cd synthesis; ./synthesis.sh" + +__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY) + @echo "*********************************************" + @echo "Running Xilinx Implementation tools.." + @echo "*********************************************" + @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf + xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/manage_fastruntime_opt.pl $(MANAGE_FASTRT_OPTIONS) + xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc + touch __xps/$(SYSTEM)_routed + +$(SYSTEM_BIT): __xps/$(SYSTEM)_routed + xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par + @echo "*********************************************" + @echo "Running Bitgen.." + @echo "*********************************************" + @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut + cd implementation; bitgen -w -f bitgen.ut $(SYSTEM) + +$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt + # @cp -f implementation/$(SYSTEM)_bd.bmm . + @echo "*********************************************" + @echo "Initializing BRAM contents of the bitstream" + @echo "*********************************************" + bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \ + -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT) + @rm -f $(SYSTEM)_bd.bmm + +$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT) + @echo "*********************************************" + @echo "Creating system ace file" + @echo "*********************************************" + xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -target ppc_hw -ace $(SYSTEM_ACE) + +################################################################# +# SIMULATION FLOW +################################################################# + + +################## BEHAVIORAL SIMULATION ################## + +$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating behavioral simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE) + +################## STRUCTURAL SIMULATION ################## + +$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating structural simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE) + + +################## TIMING SIMULATION ################## + +$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \ + $(BRAMINIT_ELF_FILES) + @echo "*********************************************" + @echo "Creating timing simulation models..." + @echo "*********************************************" + simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE) + +################################################################# +# VIRTUAL PLATFORM FLOW +################################################################# + + +$(VPEXEC): $(MHSFILE) __xps/vpgen.opt + @echo "****************************************************" + @echo "Creating virtual platform for hardware specification.." + @echo "****************************************************" + vpgen $(VPGEN_OPTIONS) $(MHSFILE) + +dummy: + @echo "" + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mhs b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mhs new file mode 100644 index 000000000..640fae030 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mhs @@ -0,0 +1,225 @@ + +# ############################################################################## +# Created by Base System Builder Wizard for Xilinx EDK 10.1.01 Build EDK_K_SP1.3 +# Fri May 09 11:01:33 2008 +# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1 +# Family: virtex4 +# Device: xc4vfx12 +# Package: ff668 +# Speed Grade: -10 +# Processor: ppc405_0 +# Processor clock frequency: 200.00 MHz +# Bus clock frequency: 100.00 MHz +# Total Off Chip Memory : 1 MB +# - SRAM = 1 MB +# ############################################################################## + PARAMETER VERSION = 2.1.0 + + + PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I + PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O + PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3] + PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4] + PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I + PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1] + PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0] + PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O + PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O + PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O + PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I + PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [9:29] + PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3] + PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O + PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31] + PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O, VEC = [0:0] + PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0] + PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O + PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O + PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 + PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST + + +BEGIN ppc405_virtex4 + PARAMETER INSTANCE = ppc405_0 + PARAMETER HW_VER = 2.01.a + PARAMETER C_FASTEST_PLB_CLOCK = DPLB0 + PARAMETER C_APU_CONTROL = 0b0000000000000001 + PARAMETER C_IDCR_BASEADDR = 0b0100000000 + PARAMETER C_IDCR_HIGHADDR = 0b0111111111 + BUS_INTERFACE JTAGPPC = jtagppc_0_0 + BUS_INTERFACE IPLB0 = plb + BUS_INTERFACE DPLB0 = plb + BUS_INTERFACE RESETPPC = ppc_reset_bus + BUS_INTERFACE MFCB = fcb_v10_0 + PORT CPMC405CLOCK = proc_clk_s + PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ +END + +BEGIN jtagppc_cntlr + PARAMETER INSTANCE = jtagppc_0 + PARAMETER HW_VER = 2.01.a + BUS_INTERFACE JTAGPPC0 = jtagppc_0_0 +END + +BEGIN plb_v46 + PARAMETER INSTANCE = plb + PARAMETER C_DCR_INTFCE = 0 + PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100 + PARAMETER HW_VER = 1.02.a + PORT PLB_Clk = sys_clk_s + PORT SYS_Rst = sys_bus_reset +END + +BEGIN xps_uartlite + PARAMETER INSTANCE = RS232_Uart + PARAMETER HW_VER = 1.00.a + PARAMETER C_BAUDRATE = 9600 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_ODD_PARITY = 0 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000 + PARAMETER C_BASEADDR = 0x84000000 + PARAMETER C_HIGHADDR = 0x8400ffff + BUS_INTERFACE SPLB = plb + PORT RX = fpga_0_RS232_Uart_RX + PORT TX = fpga_0_RS232_Uart_TX + PORT Interrupt = RS232_Uart_Interrupt +END + +BEGIN xps_gpio + PARAMETER INSTANCE = LEDs_4Bit + PARAMETER HW_VER = 1.00.a + PARAMETER C_GPIO_WIDTH = 4 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_IS_BIDIR = 1 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_BASEADDR = 0x81400000 + PARAMETER C_HIGHADDR = 0x8140ffff + BUS_INTERFACE SPLB = plb + PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO +END + +BEGIN xps_gpio + PARAMETER INSTANCE = LEDs_Positions + PARAMETER HW_VER = 1.00.a + PARAMETER C_GPIO_WIDTH = 5 + PARAMETER C_IS_DUAL = 0 + PARAMETER C_IS_BIDIR = 1 + PARAMETER C_ALL_INPUTS = 0 + PARAMETER C_BASEADDR = 0x81420000 + PARAMETER C_HIGHADDR = 0x8142ffff + BUS_INTERFACE SPLB = plb + PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO +END + +BEGIN xps_sysace + PARAMETER INSTANCE = SysACE_CompactFlash + PARAMETER HW_VER = 1.00.a + PARAMETER C_MEM_WIDTH = 16 + PARAMETER C_BASEADDR = 0x83600000 + PARAMETER C_HIGHADDR = 0x8360ffff + BUS_INTERFACE SPLB = plb + PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK + PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA & SysACE_CompactFlash_SysACE_MPA + PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD + PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN + PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN + PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN + PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ +END + +BEGIN xps_mch_emc + PARAMETER INSTANCE = SRAM + PARAMETER HW_VER = 1.01.a + PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 10000 + PARAMETER C_NUM_BANKS_MEM = 1 + PARAMETER C_MAX_MEM_WIDTH = 32 + PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1 + PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1 + PARAMETER C_MEM0_WIDTH = 32 + PARAMETER C_SYNCH_MEM_0 = 1 + PARAMETER C_TCEDV_PS_MEM_0 = 0 + PARAMETER C_TWC_PS_MEM_0 = 0 + PARAMETER C_TAVDV_PS_MEM_0 = 0 + PARAMETER C_TWP_PS_MEM_0 = 0 + PARAMETER C_THZCE_PS_MEM_0 = 0 + PARAMETER C_TLZWE_PS_MEM_0 = 0 + PARAMETER C_MEM0_BASEADDR = 0xfff00000 + PARAMETER C_MEM0_HIGHADDR = 0xffffffff + BUS_INTERFACE SPLB = plb + PORT Mem_A = fpga_0_SRAM_Mem_A_split + PORT Mem_BEN = fpga_0_SRAM_Mem_BEN + PORT Mem_WEN = fpga_0_SRAM_Mem_WEN + PORT Mem_DQ = fpga_0_SRAM_Mem_DQ + PORT Mem_OEN = fpga_0_SRAM_Mem_OEN + PORT Mem_CEN = fpga_0_SRAM_Mem_CEN + PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN + PORT RdClk = sys_clk_s +END + +BEGIN util_bus_split + PARAMETER INSTANCE = SRAM_util_bus_split_0 + PARAMETER HW_VER = 1.00.a + PARAMETER C_SIZE_IN = 32 + PARAMETER C_LEFT_POS = 9 + PARAMETER C_SPLIT = 30 + PORT Sig = fpga_0_SRAM_Mem_A_split + PORT Out1 = fpga_0_SRAM_Mem_A +END + +BEGIN clock_generator + PARAMETER INSTANCE = clock_generator_0 + PARAMETER HW_VER = 2.01.a + PARAMETER C_EXT_RESET_HIGH = 1 + PARAMETER C_CLKIN_FREQ = 100000000 + PARAMETER C_CLKOUT0_FREQ = 200000000 + PARAMETER C_CLKOUT0_BUF = TRUE + PARAMETER C_CLKOUT0_PHASE = 0 + PARAMETER C_CLKOUT0_GROUP = NONE + PARAMETER C_CLKOUT1_FREQ = 100000000 + PARAMETER C_CLKOUT1_BUF = TRUE + PARAMETER C_CLKOUT1_PHASE = 0 + PARAMETER C_CLKOUT1_GROUP = NONE + PORT CLKOUT0 = proc_clk_s + PORT CLKOUT1 = sys_clk_s + PORT CLKIN = dcm_clk_s + PORT LOCKED = Dcm_all_locked + PORT RST = net_gnd +END + +BEGIN proc_sys_reset + PARAMETER INSTANCE = proc_sys_reset_0 + PARAMETER HW_VER = 2.00.a + PARAMETER C_EXT_RESET_HIGH = 0 + BUS_INTERFACE RESETPPC0 = ppc_reset_bus + PORT Slowest_sync_clk = sys_clk_s + PORT Dcm_locked = Dcm_all_locked + PORT Ext_Reset_In = sys_rst_s + PORT Bus_Struct_Reset = sys_bus_reset + PORT Peripheral_Reset = sys_periph_reset +END + +BEGIN xps_intc + PARAMETER INSTANCE = xps_intc_0 + PARAMETER HW_VER = 1.00.a + PARAMETER C_BASEADDR = 0x81800000 + PARAMETER C_HIGHADDR = 0x8180ffff + BUS_INTERFACE SPLB = plb + PORT Irq = EICC405EXTINPUTIRQ + PORT Intr = RS232_Uart_Interrupt +END + +BEGIN fcb_v10 + PARAMETER INSTANCE = fcb_v10_0 + PARAMETER HW_VER = 1.00.a + PORT FCB_CLK = proc_clk_s + PORT SYS_RST = sys_bus_reset +END + +BEGIN apu_fpu + PARAMETER INSTANCE = apu_fpu_0 + PARAMETER HW_VER = 3.10.a + BUS_INTERFACE SFCB = fcb_v10_0 + PORT FPU_CLK = sys_clk_s +END + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mss b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mss new file mode 100644 index 000000000..737c30840 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.mss @@ -0,0 +1,88 @@ + + PARAMETER VERSION = 2.2.0 + + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 2.00.a + PARAMETER PROC_INSTANCE = ppc405_0 +END + + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu_ppc405 + PARAMETER DRIVER_VER = 1.10.a + PARAMETER HW_INSTANCE = ppc405_0 + PARAMETER COMPILER = powerpc-eabi-gcc + PARAMETER ARCHIVER = powerpc-eabi-ar + PARAMETER CORE_CLOCK_FREQ_HZ = 200000000 +END + + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = jtagppc_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartlite + PARAMETER DRIVER_VER = 1.13.a + PARAMETER HW_INSTANCE = RS232_Uart +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.12.a + PARAMETER HW_INSTANCE = LEDs_4Bit +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpio + PARAMETER DRIVER_VER = 2.12.a + PARAMETER HW_INSTANCE = LEDs_Positions +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = sysace + PARAMETER DRIVER_VER = 1.11.a + PARAMETER HW_INSTANCE = SysACE_CompactFlash +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = emc + PARAMETER DRIVER_VER = 2.00.a + PARAMETER HW_INSTANCE = SRAM +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = SRAM_util_bus_split_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = clock_generator_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 1.00.a + PARAMETER HW_INSTANCE = proc_sys_reset_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = intc + PARAMETER DRIVER_VER = 1.11.a + PARAMETER HW_INSTANCE = xps_intc_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = apu_fpu + PARAMETER DRIVER_VER = 2.10.a + PARAMETER HW_INSTANCE = apu_fpu_0 +END + + diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.xmp b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.xmp new file mode 100644 index 000000000..0e1cb57a5 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system.xmp @@ -0,0 +1,74 @@ +#Please do not modify this file by hand +XmpVersion: 10.1.01 +VerMgmt: 10.1.01 +IntStyle: default +MHS File: system.mhs +MSS File: system.mss +NPL File: projnav/system.ise +Architecture: virtex4 +Device: xc4vfx12 +Package: ff668 +SpeedGrade: -10 +UserCmd1: +UserCmd1Type: 0 +UserCmd2: +UserCmd2Type: 0 +TopInst: system_i +GenSimTB: 0 +InsertNoPads: 0 +WarnForEAArch: 1 +HdlLang: VHDL +Simulator: mti +SimModel: BEHAVIORAL +MixLangSim: 1 +UcfFile: data/system.ucf +FpgaImpMode: 0 +EnableParTimingError: 1 +EnableResetOptimization: 0 +ShowLicenseDialog: 1 +ICacheAddr: SRAM, +DCacheAddr: SRAM, +Processor: ppc405_0 +BootLoop: 1 +XmdStub: 0 +SwProj: RTOSDemo +Processor: ppc405_0 +Executable: RTOSDemo/executable.elf +Source: RTOSDemo/../../Common/Minimal/BlockQ.c +Source: RTOSDemo/../../Common/Minimal/blocktim.c +Source: RTOSDemo/../../Common/Minimal/comtest.c +Source: RTOSDemo/../../Common/Minimal/countsem.c +Source: RTOSDemo/../../Common/Minimal/death.c +Source: RTOSDemo/../../Common/Minimal/dynamic.c +Source: RTOSDemo/../../Common/Minimal/flash.c +Source: RTOSDemo/../../Common/Minimal/GenQTest.c +Source: RTOSDemo/../../Common/Minimal/integer.c +Source: RTOSDemo/../../Common/Minimal/QPeek.c +Source: RTOSDemo/../../Common/Minimal/recmutex.c +Source: RTOSDemo/../../Common/Minimal/semtest.c +Source: RTOSDemo/../../../Source/tasks.c +Source: RTOSDemo/../../../Source/list.c +Source: RTOSDemo/../../../Source/queue.c +Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c +Source: RTOSDemo/main.c +Source: RTOSDemo/serial/serial.c +Source: RTOSDemo/partest/partest.c +Source: RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S +Source: RTOSDemo/../../../Source/portable/MemMang/heap_2.c +Source: RTOSDemo/flop/flop.c +Source: RTOSDemo/flop/flop-reg-test.c +Header: RTOSDemo/FreeRTOSConfig.h +DefaultInit: EXECUTABLE +InitBram: 0 +Active: 1 +CompilerOptLevel: 0 +GlobPtrOpt: 0 +DebugSym: 1 +ProfileFlag: 0 +ProgStart: +StackSize: +HeapSize: +LinkerScript: RTOSDemo/RTOSDemo_linker_script.ld +ProgCCFlags: -I./RTOSDemo/flop -I../../Source/portable/GCC/PPC405_Xilinx -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -Wextra +CompileInXps: 1 +NonXpsApp: 0 diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system_incl.make b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system_incl.make new file mode 100644 index 000000000..4c29d2d22 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/system_incl.make @@ -0,0 +1,144 @@ +################################################################# +# Makefile generated by Xilinx Platform Studio +# Project:C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\system.xmp +# +# WARNING : This file will be re-generated every time a command +# to run a make target is invoked. So, any changes made to this +# file manually, will be lost when make is invoked next. +################################################################# + +XILINX_EDK_DIR = /cygdrive/c/devtools/Xilinx/10.1/EDK +NON_CYG_XILINX_EDK_DIR = C:/devtools/Xilinx/10.1/EDK + +SYSTEM = system + +MHSFILE = system.mhs + +MSSFILE = system.mss + +FPGA_ARCH = virtex4 + +DEVICE = xc4vfx12ff668-10 + +LANGUAGE = vhdl + +SEARCHPATHOPT = + +SUBMODULE_OPT = + +PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) + +LIBGEN_OPTIONS = -mhs $(MHSFILE) -p $(DEVICE) $(SEARCHPATHOPT) + +VPGEN_OPTIONS = -p $(DEVICE) $(SEARCHPATHOPT) + +MANAGE_FASTRT_OPTIONS = -reduce_fanout no + +OBSERVE_PAR_OPTIONS = -error yes + +RTOSDEMO_OUTPUT_DIR = RTOSDemo +RTOSDEMO_OUTPUT = $(RTOSDEMO_OUTPUT_DIR)/executable.elf + +MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf +PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf +PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf +BOOTLOOP_DIR = bootloops + +PPC405_0_BOOTLOOP = $(BOOTLOOP_DIR)/ppc405_0.elf + +BRAMINIT_ELF_FILES = +BRAMINIT_ELF_FILE_ARGS = + +ALL_USER_ELF_FILES = $(RTOSDEMO_OUTPUT) + +SIM_CMD = vsim + +BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.do + +STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.do + +TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.do + +DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT) + +MIX_LANG_SIM_OPT = -mixed yes + +SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) $(MIX_LANG_SIM_OPT) -s mti -X ./ -E ./ + + +LIBRARIES = \ + ppc405_0/lib/libxil.a +VPEXEC = virtualplatform/vpexec.exe + +LIBSCLEAN_TARGETS = ppc405_0_libsclean + +PROGRAMCLEAN_TARGETS = RTOSDemo_programclean + +CORE_STATE_DEVELOPMENT_FILES = + +WRAPPER_NGC_FILES = implementation/ppc405_0_wrapper.ngc \ +implementation/jtagppc_0_wrapper.ngc \ +implementation/plb_wrapper.ngc \ +implementation/rs232_uart_wrapper.ngc \ +implementation/leds_4bit_wrapper.ngc \ +implementation/leds_positions_wrapper.ngc \ +implementation/sysace_compactflash_wrapper.ngc \ +implementation/sram_wrapper.ngc \ +implementation/sram_util_bus_split_0_wrapper.ngc \ +implementation/clock_generator_0_wrapper.ngc \ +implementation/proc_sys_reset_0_wrapper.ngc \ +implementation/xps_intc_0_wrapper.ngc \ +implementation/fcb_v10_0_wrapper.ngc \ +implementation/apu_fpu_0_wrapper.ngc + +POSTSYN_NETLIST = implementation/$(SYSTEM).ngc + +SYSTEM_BIT = implementation/$(SYSTEM).bit + +DOWNLOAD_BIT = implementation/download.bit + +SYSTEM_ACE = implementation/$(SYSTEM).ace + +UCF_FILE = data/system.ucf + +BMM_FILE = implementation/$(SYSTEM).bmm + +BITGEN_UT_FILE = etc/bitgen.ut + +XFLOW_OPT_FILE = etc/fast_runtime.opt +XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE) + +XPLORER_DEPENDENCY = __xps/xplorer.opt +XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7 + +FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(BITGEN_UT_FILE) $(XFLOW_DEPENDENCY) + +################################################################# +# SOFTWARE APPLICATION RTOSDEMO +################################################################# + +RTOSDEMO_SOURCES = RTOSDemo/../../Common/Minimal/BlockQ.c RTOSDemo/../../Common/Minimal/blocktim.c RTOSDemo/../../Common/Minimal/comtest.c RTOSDemo/../../Common/Minimal/countsem.c RTOSDemo/../../Common/Minimal/death.c RTOSDemo/../../Common/Minimal/dynamic.c RTOSDemo/../../Common/Minimal/flash.c RTOSDemo/../../Common/Minimal/GenQTest.c RTOSDemo/../../Common/Minimal/integer.c RTOSDemo/../../Common/Minimal/QPeek.c RTOSDemo/../../Common/Minimal/recmutex.c RTOSDemo/../../Common/Minimal/semtest.c RTOSDemo/../../../Source/tasks.c RTOSDemo/../../../Source/list.c RTOSDemo/../../../Source/queue.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/port.c RTOSDemo/main.c RTOSDemo/serial/serial.c RTOSDemo/partest/partest.c RTOSDemo/../../../Source/portable/GCC/PPC405_Xilinx/portasm.S RTOSDemo/../../../Source/portable/MemMang/heap_2.c RTOSDemo/flop/flop.c RTOSDemo/flop/flop-reg-test.c + +RTOSDEMO_HEADERS = RTOSDemo/FreeRTOSConfig.h + +RTOSDEMO_CC = powerpc-eabi-gcc +RTOSDEMO_CC_SIZE = powerpc-eabi-size +RTOSDEMO_CC_OPT = -O0 +RTOSDEMO_CFLAGS = -I./RTOSDemo/flop -I../../Source/portable/GCC/PPC405_Xilinx -I./ppc405_0/include/ -IRTOSDemo/ -I. -I./RTOSDemo/ -I../Common/include/ -I../../Source/include/ -I./ppc405_0/include/ -I./ppc405_0/include -D GCC_PPC405 -mregnames -Wextra +RTOSDEMO_CC_SEARCH = # -B +RTOSDEMO_LIBPATH = -L./ppc405_0/lib/ # -L +RTOSDEMO_INCLUDES = -I./ppc405_0/include/ -IRTOSDemo/ # -I +RTOSDEMO_LFLAGS = # -l +RTOSDEMO_LINKER_SCRIPT = RTOSDemo/RTOSDemo_linker_script.ld +RTOSDEMO_LINKER_SCRIPT_FLAG = -Wl,-T -Wl,$(RTOSDEMO_LINKER_SCRIPT) +RTOSDEMO_CC_DEBUG_FLAG = -g +RTOSDEMO_CC_PROFILE_FLAG = # -pg +RTOSDEMO_CC_GLOBPTR_FLAG= # -msdata=eabi +RTOSDEMO_CC_INFERRED_FLAGS= -mfpu=sp_full +RTOSDEMO_CC_START_ADDR_FLAG= # # -Wl,-defsym -Wl,_START_ADDR= +RTOSDEMO_CC_STACK_SIZE_FLAG= # # -Wl,-defsym -Wl,_STACK_SIZE= +RTOSDEMO_CC_HEAP_SIZE_FLAG= # # -Wl,-defsym -Wl,_HEAP_SIZE= +RTOSDEMO_OTHER_CC_FLAGS= $(RTOSDEMO_CC_GLOBPTR_FLAG) \ + $(RTOSDEMO_CC_START_ADDR_FLAG) $(RTOSDEMO_CC_STACK_SIZE_FLAG) $(RTOSDEMO_CC_HEAP_SIZE_FLAG) \ + $(RTOSDEMO_CC_INFERRED_FLAGS) \ + $(RTOSDEMO_LINKER_SCRIPT_FLAG) $(RTOSDEMO_CC_DEBUG_FLAG) $(RTOSDEMO_CC_PROFILE_FLAG) diff --git a/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/wizlog b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/wizlog new file mode 100644 index 000000000..3f4f48396 --- /dev/null +++ b/Demo/PPC405_FPU_Xilinx_Virtex4_GCC/wizlog @@ -0,0 +1,3 @@ +WARNING:MDT - ppc405_virtex4 (ppc405_0) - + C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\dump.mhs + line 28 - ADDRESS specified by PARAMETER C_IDCR_BASEADDR is ignored