From: Philipp Tomsich Date: Fri, 27 Apr 2018 17:59:56 +0000 (+0200) Subject: arm_dpm: flush both scratch registers (R0 and R1) X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=7b94ae9e520877e7f2341b48b3bd0c0d1ca8a14b;p=openocd arm_dpm: flush both scratch registers (R0 and R1) Neither the initial loop to clear dirty registers (which visits all registers starting at R2 and counting upwards) nor the final explicit flushes ensure a write-back in arm_dpm_write_dirty_registers. This change makes sure that both our scratch registers (i.e. R0 and R1) are written back to the target. Change-Id: If65be4f371cd40af9a0cfa97f3730b070b92e981 Signed-off-by: Philipp Tomsich Reviewed-on: http://openocd.zylin.com/4506 Tested-by: jenkins Reviewed-by: Matthias Welwarsky --- diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 65790995..f9b30c18 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -587,11 +587,13 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) goto done; arm->pc->dirty = false; - /* flush R0 -- it's *very* dirty by now */ - retval = dpm_write_reg(dpm, &cache->reg_list[0], 0); - if (retval != ERROR_OK) - goto done; - cache->reg_list[0].dirty = false; + /* flush R0 and R1 (our scratch registers) */ + for (unsigned i = 0; i < 2; i++) { + retval = dpm_write_reg(dpm, &cache->reg_list[i], i); + if (retval != ERROR_OK) + goto done; + cache->reg_list[i].dirty = false; + } /* (void) */ dpm->finish(dpm); done: