From: rtel Date: Tue, 30 Jan 2018 17:42:12 +0000 (+0000) Subject: Microblaze port: Place critical section around XIntc_Enable() to protect read/modify... X-Git-Tag: V10.1.0~37 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=7ecdc73c5d0db8b4a09594a7de98e955cbf42530;p=freertos Microblaze port: Place critical section around XIntc_Enable() to protect read/modify/write operation performed inside the library. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2528 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c index 3d96be5a5..90ffe0fe9 100644 --- a/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c +++ b/FreeRTOS/Demo/MicroBlaze_Kintex7_EthernetLite/RTOSDemo/src/serial.c @@ -210,7 +210,7 @@ portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; static void prvTxHandler( void *pvUnused, unsigned portBASE_TYPE uxUnused ) { -BaseType_t xHigherPriorityTaskWoken = NULL; +BaseType_t xHigherPriorityTaskWoken = ( BaseType_t ) NULL; ( void ) pvUnused; ( void ) uxUnused; diff --git a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c b/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c index 0460e46d2..f30b9e457 100644 --- a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c +++ b/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c @@ -47,7 +47,7 @@ the scheduler being commenced interrupts should not be enabled, so the critical nesting variable is initialised to a non-zero value. */ #define portINITIAL_NESTING_VALUE ( 0xff ) -/* The bit within the MSR register that enabled/disables interrupts and +/* The bit within the MSR register that enabled/disables interrupts and exceptions respectively. */ #define portMSR_IE ( 0x02U ) #define portMSR_EE ( 0x100U ) @@ -131,7 +131,7 @@ extern void _start1( void ); disabled. Each task will enable interrupts automatically when it enters the running state for the first time. */ *pxTopOfStack = mfmsr() & ~portMSR_IE; - + #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) { /* Ensure exceptions are enabled for the task. */ @@ -305,7 +305,13 @@ int32_t lReturn; lReturn = prvEnsureInterruptControllerIsInitialised(); if( lReturn == pdPASS ) { - XIntc_Enable( &xInterruptControllerInstance, ucInterruptID ); + /* Critical section protects read/modify/writer operation inside + XIntc_Enable(). */ + portENTER_CRITICAL(); + { + XIntc_Enable( &xInterruptControllerInstance, ucInterruptID ); + } + portEXIT_CRITICAL(); } configASSERT( lReturn );