From: richardbarry Date: Thu, 14 Jan 2010 12:24:29 +0000 (+0000) Subject: Work in progress. X-Git-Tag: V6.0.3~31 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=7f1d21be031715b1134f8dfe9b88da25cf9da16d;p=freertos Work in progress. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@955 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo.tws b/Demo/SuperH_SH7216_Renesas/RTOSDemo.tws index c9d1887c1..2303b819b 100644 --- a/Demo/SuperH_SH7216_Renesas/RTOSDemo.tws +++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo.tws @@ -7,23 +7,17 @@ [GENERAL_DATA] [BREAKPOINTS] [OPEN_WORKSPACE_FILES] -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\FreeRTOSConfig.h" -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\regtest.src" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\include\list.h" "C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portmacro.h" +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portasm.src" [WORKSPACE_FILE_STATES] -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\FreeRTOSConfig.h" 88 88 1216 383 0 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" 0 0 1132 383 0 7 -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" -4 -23 1316 445 1 0 -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" 110 110 1216 383 0 5 -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" 154 154 1132 383 0 6 -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\include\list.h" 66 66 1216 383 0 1 -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" 0 0 1400 586 0 3 -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portmacro.h" 132 132 1216 383 0 4 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" 0 0 918 659 0 0 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\regtest.src" -4 -23 1016 659 1 4 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" 0 0 712 434 0 3 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" 0 0 1400 586 0 1 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portasm.src" 0 0 805 659 0 2 [LOADED_PROJECTS] "RTOSDemo" [END] diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp index 1e77fc7f7..d3ddb2e16 100644 --- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp +++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.hwp @@ -121,14 +121,17 @@ "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\dbsct.c" "User" "C source file" 2 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" "User" "C source file" 2 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" "User" "C source file" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\regtest.src" "User" "Assembly source file" 2 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" "User" "C source file" 2 "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" "User" "C source file" 2 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "User" "C source file|FreeRTOS" 2 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "User" "C source file|FreeRTOS" 2 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" "User" "C source file|FreeRTOS" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portasm.src" "User" "Assembly source file" 2 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "User" "C source file|FreeRTOS" 2 "C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "User" "C source file|FreeRTOS" 2 [FOLDER] +"Assembly source file" "Assembly source file" "C source file" "C source file" "C source file|FreeRTOS" "" [GENERAL_DATA_PROJECT] @@ -139,24 +142,26 @@ "SessionSH7216_E10A-USB_SYSTEM__SH" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\SessionSH7216_E10A-USB_SYSTEM__SH.hsf" 0 [GENERAL_DATA_SESSION_SessionSH7216_E10A-USB_SYSTEM__SH] [OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas OptLinker] -"Single Shot" "03711fb24378ac10" 4 +"Single Shot" "0d47a4b27059ac10" 4 [OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas SH Assembler] "Assembly source file" "05db08d6f178ac10" 3 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\regtest.src" "0fd8e3b27059ac10" 3 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portasm.src" "0cc802940e29ac10" 3 "Linkage symbol file" "05db08d6f178ac10" 3 [OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas SH C/C++ Compiler] -"C source file" "0a3b1de34378ac10" 2 -"C++ source file" "0a3b1de34378ac10" 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\ParTest\ParTest.c" "0a3b1de34378ac10" 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\dbsct.c" "0a3b1de34378ac10" 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" "0a3b1de34378ac10" 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" "0a3b1de34378ac10" 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" "0a3b1de34378ac10" 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" "0a3b1de34378ac10" 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "0a3b1de34378ac10" 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "0a3b1de34378ac10" 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" "0a3b1de34378ac10" 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "0a3b1de34378ac10" 2 -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "0a3b1de34378ac10" 2 +"C source file" "0deaf32ba059ac10" 2 +"C++ source file" "0deaf32ba059ac10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\ParTest\ParTest.c" "0deaf32ba059ac10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\dbsct.c" "0deaf32ba059ac10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" "0deaf32ba059ac10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" "0deaf32ba059ac10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" "0deaf32ba059ac10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" "0deaf32ba059ac10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\list.c" "0deaf32ba059ac10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\MemMang\heap_2.c" "0deaf32ba059ac10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" "0deaf32ba059ac10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\queue.c" "0deaf32ba059ac10" 2 +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\tasks.c" "0deaf32ba059ac10" 2 [OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH_Renesas SH C/C++ Library Generator] "Single Shot" "05db08d6f178ac10" 1 [OPTIONS_Debug_SH7216_E10A-USB_SYSTEM__SH] @@ -165,7 +170,7 @@ " 3 "[V|VERSION|6] [S|FORM|STYPE] [S|BYTE_COUNT_VALUE|FF] [B|DEBUG|1] [S|ROM|(D,R)] [S|CRC|NONE|00000000] [B|LIST|1] [S|LIST|^"$(CONFIGDIR)\$(PROJECTNAME).map^"] [S|SHOW|METHODCUSTOM|] [S|OUTPUT|^"$(CONFIGDIR)\$(PROJECTNAME).mot^"] [I|SPACE|^"FF^"] [B|OPTIMIZE|0] [I|CACHESIZE|000000008] [I|CACHELINE|000000020] [S|START|DVECTTBL,DINTTBL(00)|PResetPRG,PIntPRG(0800)|P,C,C$BSEC,C$DSEC,D(01000)|B,R(0FFF80000)|S(0FFFBFC00)] [B|SKIPDEPENDENCY|1] " 4 -"[V|VERSION|7] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\SH2A_FPU^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\Common\include^"] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|ALIGN4|ALL] [B|TBR|0] [B|STUFF|0] [S|BSS_ORDER|DECLARATION] [S|MXGEN_MEM0|00000000] [S|MXGEN_MEM1|00000000] [B|LIST|0] [S|GBR|AUTO] [S|INLINE|DEFAULT] [I|INLINE|20] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|OPT_RANGE|ALL] [I|MAX_UNROLL|1] [S|CPU|SH2AFPU] [S|ROUND|NEAREST] [B|CHGINCPATH|1] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1] +"[V|VERSION|7] [S|INCLUDE|^"$(PROJDIR)\..\..\..\Source\portable\Renesas\SH2A_FPU^"|^"$(PROJDIR)\..\..\..\Source\include^"|^"$(PROJDIR)\.^"|^"$(PROJDIR)\..\..\Common\include^"] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(FILELEAF).obj^"] [B|DEBUG|1] [S|ALIGN4|ALL] [S|ASSEMBLY|^"[V|VERSION|1]] [S|OUTPUTPATH|^"^"$(CONFIGDIR)\$(FILELEAF).obj^"^"]] [S|LITERAL|POOL|BRANCH|JUMP|RETURN]] [S|DISPSIZE|12]] [I|TAB|8]] [B|CHGINCPATH|1]] [S|CPU|SH2AFPU]] [S|ENDIAN|BIG]] [S|ROUND|NEAREST]] [B|DENORMALIZE|0]]^"] [B|TBR|0] [B|STUFF|0] [S|BSS_ORDER|DECLARATION] [S|MXGEN_MEM0|00000000] [S|MXGEN_MEM1|00000000] [B|LIST|0] [B|OPTIMIZE|0] [S|GBR|AUTO] [S|INLINE|DEFAULT] [I|INLINE|20] [S|MISRA2004_CHECK_RULE|ALL] [S|MISRA2004_RULE|1.1|3.4|4.1|5.2|5.3|5.4|5.5|5.6|5.7|6.1|6.2|6.3|6.4|6.5|7.1|8.1|8.2|8.3|8.5|8.6|8.7|8.8|8.11|8.12|9.2|9.3|10.1|10.2|10.3|10.4|10.5|10.6|11.1|11.2|11.3|11.4|11.5|12.1|12.2|12.3|12.4|12.5|12.6|12.7|12.8|12.9|12.10|12.11|12.12|12.13|13.1|13.2|13.3|13.4|13.7|14.1|14.2|14.3|14.4|14.5|14.6|14.7|14.8|14.9|14.10|15.1|15.2|15.3|15.4|15.5|16.1|16.2|16.3|16.4|16.5|16.6|16.8|16.9|17.3|17.4|17.5|17.6|18.1|18.2|18.4|19.1|20.2|20.4|20.5|20.7|20.8|20.9|20.10|20.11|20.12] [S|MISRA1998_CHECK_RULE|ALL] [S|MISRA1998_RULE|1|5|8|12|13|14|17|18|19|20|21|22|24|28|29|31|32|33|34|35|36|37|38|39|40|42|43|44|45|46|48|49|50|51|53|54|55|56|57|58|59|60|61|62|63|64|65|68|69|70|71|72|73|74|75|76|77|78|79|80|82|83|84|85|99|101|102|103|104|105|106|108|110|111|112|113|115|118|119|121|122|123|124|125|126|127] [S|MISRA_GROUP_FILE_PATH|^"$(PROJDIR)\$(PROJECTNAME).rde^"] [S|OPT_RANGE|ALL] [I|MAX_UNROLL|1] [S|CPU|SH2AFPU] [S|ROUND|NEAREST] [B|CHGINCPATH|1] [B|SKIPDEPENDENCY|1] [N|DEPENDSCAN|1] " 2 "[V|VERSION|7] [S|MODE|BUILD/CHANGED] [S|EXISTOUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [B|RUNTIME|1] [B|STDLIB|1] [B|STRING|1] [S|OUTPUTPATH|^"$(CONFIGDIR)\$(PROJECTNAME).lib^"] [S|ALIGN4|ALL] [B|STUFF|0] [S|BSS_ORDER|DECLARATION] [S|GBR|AUTO] [S|INLINE|DEFAULT] [I|INLINE|20] [S|OPT_RANGE|ALL] [I|MAX_UNROLL|1] [B|SAVE_CONT_REG|1] [S|CPU|SH2AFPU] [S|ROUND|NEAREST] [B|SKIPDEPENDENCY|1] " 1 diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav index 823c549d1..ac41d6529 100644 Binary files a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav and b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.nav differ diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps index 750d5a659..804f6fa50 100644 --- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps +++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/RTOSDemo.tps @@ -12,7 +12,7 @@ "SessionSH7216_E10A-USB_SYSTEM__SH" [GENERAL_DATA_PROJECT] [GENERAL_DATA_CONFIGURATION_Debug_SH7216_E10A-USB_SYSTEM__SH] -"PROJECT_FILES_MODIFIED_DATA_TAG" "TRUE" +"PROJECT_FILES_MODIFIED_DATA_TAG" "FALSE" [SESSIONS_Debug_SH7216_E10A-USB_SYSTEM__SH] "SessionSH7216_E10A-USB_SYSTEM__SH" [GENERAL_DATA_SESSION_SessionSH7216_E10A-USB_SYSTEM__SH] diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf b/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf index e4912a8f8..8138c0362 100644 --- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf +++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/SessionSH7216_E10A-USB_SYSTEM__SH.hsf @@ -79,7 +79,23 @@ "{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,," "{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_SAMPLING_RATE" "1000" "{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0" -"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersCtrlViews" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersCtrlViews" "1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ColumnWidth" "50,307,118" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_COUNT" "82" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideFLAGs" "1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0HideRadix" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0LastFileName" "" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWnd0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16," +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ColumnWidth" "50,456,35" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_COUNT" "82" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideFLAGs" "1" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0HideRadix" "0" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0LastFileName" "" +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewB0RadixList" "16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16,2,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16," +"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegistersWndViewBInstanceKey0" "{WK_00000001_REGISTERS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SHViewB" "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_ADDRESS_NAME" "" "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0" "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0" @@ -90,8 +106,43 @@ "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_SAMPLEING_RATE" "1000" "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0" "{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0" -"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "4" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth0" "198" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth1" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth12" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000" "pxCurrentTCB, 4, 0, P, Col, Hex, MN" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0000_SCOPE" "Current Scope," +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0001" "*, 11, 0, C0000, Exp, Hex, N" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0002" "pxTopOfStack, 4, 0, C0001, Col, Hex, N" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0003" "xGenericListItem, 11, 0, C0001, Col, Hex, N" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0004" "xEventListItem, 11, 0, C0001, Col, Hex, N" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0005" "uxPriority, 2, 0, C0001, Col, Hex, N" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0006" "pxStack, 4, 0, C0001, Col, Hex, N" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0007" "pcTaskName, 6, 0, C0001, Col, Hex, N" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEM0008" "uxCriticalNesting, 2, 0, C0001, Col, Hex, N" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH_ITEMCnt" "1" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth12" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH_ITEMCnt" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth12" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ECX_WATCH_ITEMCnt" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth0" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth1" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth12" "150" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth2" "120" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth3" "200" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ECX_WATCH_ITEMCnt" "0" "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInitial_Radix" "0" +"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInstanceKey0" "{WK_00000001_WATCH}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndRecentFile_WatchRecord" "" "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndRecentFile_WatchSave" "" "{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndUpdate_Interval" "100" @@ -188,30 +239,30 @@ "{D293FA15-461F-4D9F-B9C9-64724B3409F9}T_TRACE_TRACE_ACQUISITION2" "1,0,1,1,1,1,1,0,0,0,0,0,0" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_EVAL_DENORMAL_MODE" "16777216" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_EVAL_ROUND_MODE" "768" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_0" "00000000FFFF8000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_1" "00000000FFFE3A00" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_10" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_11" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_12" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_13" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_14" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_15" "00000000FFFC0000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_16" "00000000000011EC" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_0" "00000000FFF80AD4" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_1" "0000000000000001" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_10" "000000000000000B" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_11" "000000000000000C" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_12" "000000000000000D" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_13" "000000000000000E" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_14" "0000000000000022" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_15" "00000000FFF801E0" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_16" "0000000000001EF0" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_17" "0000000000000001" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_18" "0000000000000000" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_18" "0000000000000011" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_19" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_2" "00000000FFFFFA00" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_2" "0000000000000003" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_20" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_21" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_22" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_23" "00000000000011E2" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_21" "0000000000000010" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_22" "000000000000000F" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_23" "0000000000000011" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_24" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_25" "0000000000040001" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_26" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_27" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_28" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_29" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_3" "00000000FFFE3A06" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_3" "0000000000000004" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_30" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_31" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_32" "0000000000000000" @@ -222,7 +273,7 @@ "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_37" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_38" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_39" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_4" "0000000000000001" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_4" "0000000000000005" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_40" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_41" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_42" "0000000000000000" @@ -233,11 +284,11 @@ "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_47" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_48" "0000000000000000" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_49" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_5" "00000000FFFFFA00" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_6" "00000000FFFFFA00" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_7" "00000000FFFFFF0F" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_8" "0000000000000000" -"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_9" "0000000000000000" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_5" "0000000000000006" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_6" "0000000000000007" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_7" "0000000000000008" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_8" "0000000000000009" +"{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_9" "000000000000000A" "{D34C8080-5A99-11D5-B1FD-00A0C9E23A58}C_REGISTER_REG_COUNT" "50" "{D595F9C0-EF22-11D5-B7DB-0000E10B3DA9}EventCtrlViews" "0" "{EEDC9300-6FBE-11D5-8613-00A024591A38}LocalsCtrlViews" "0" @@ -270,7 +321,7 @@ "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp23" "0" "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp24" "0" "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp25" "0" -"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp26" "1" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp26" "0" "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp27" "0" "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp28" "0" "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp29" "0" @@ -325,7 +376,7 @@ "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp8" "0" "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0Exp9" "0" "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollHorz" "0" -"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "24" +"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "0" "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth0" "200" "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth1" "100" "{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd1ColWidth2" "100" @@ -349,13 +400,14 @@ 0 [WINDOW_POSITION_STATE_DATA_VD1] "Help" "TOOLBAR 0" 59419 1 5 "0.00" 0 0 0 0 0 17 0 "" "0.0" -"{WK_00000001_CmdLine}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 0 "0.02" 433 0 0 350 200 18 0 "32771|32772|32778|<>|32773|32774|<>|32820|<>|32801|32824" "0.0" +"{WK_00000001_CmdLine}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 1 "0.08" 219 0 0 350 200 18 0 "32771|32772|32778|<>|32773|32774|<>|32820|<>|32801|32824" "0.0" "{WK_00000001_DISASSEMBLY}" "WINDOW" 0 0 0 "0.00" 0 -4 -23 1400 586 9 0 "" "0.0" "{WK_00000001_EVENT}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 0 "0.50" 292 0 0 350 200 2065 0 "32774|32775|32777|<>|32780|<>" "0.0" -"{WK_00000001_IO}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 1 "0.46" 433 0 0 350 200 18 0 "32817|32826|32819|32820|32821" "0.0" -"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 1 "0.98" 433 560 340 350 200 18 0 "36756|36757|36758|36759|<>|36746|36747|<>|39531|<>|39500|39534|<>|36687" "0.0" -"{WK_00000001_REGISTERS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59421 0 0 "1.00" 666 0 0 350 200 2065 0 "" "0.0" -"{WK_00000001_STATUS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 0 "0.50" 433 0 0 350 200 17 0 "" "0.0" +"{WK_00000001_IO}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 3 "0.31" 219 0 0 350 200 17 0 "32817|32826|32819|32820|32821" "0.0" +"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 2 "0.92" 219 560 340 350 200 18 0 "36756|36757|36758|36759|<>|36746|36747|<>|39531|<>|39500|39534|<>|36687" "0.0" +"{WK_00000001_REGISTERS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59421 0 0 "1.00" 293 0 0 350 200 18 0 "" "0.0" +"{WK_00000001_STATUS}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 4 "0.50" 219 0 0 350 200 17 0 "" "0.0" +"{WK_00000001_WATCH}RTOSDemoSessionSH7216_E10A-USB_SYSTEM__SH" "WINDOW" 59422 0 0 "0.50" 219 0 0 350 200 17 0 "32781|32783|<>|32771|32829|32772|32827|32773|<>|32786|<>|32810|32811|32831" "0.0" "{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 340 560 340 350 200 18 0 "" "0.0" "{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0" "{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0" @@ -367,7 +419,7 @@ "{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 1 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" "{WK_TB00000011_CPU}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 18 0 "" "0.0" "{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 1 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" -"{WK_TB00000013_SYMBOL}" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 18 0 "" "0.0" +"{WK_TB00000013_SYMBOL}" "TOOLBAR 0" 59419 2 5 "0.00" 0 0 0 0 0 18 0 "" "0.0" "{WK_TB00000014_CODE}" "TOOLBAR 0" 59419 2 8 "0.00" 0 0 0 0 0 17 0 "" "0.0" "{WK_TB00000015_PERFORMANCE}" "TOOLBAR 0" 59419 2 7 "0.00" 0 0 0 0 0 17 0 "" "0.0" "{WK_TB00000016_GRAPHIC}" "TOOLBAR 0" 59419 2 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" @@ -375,19 +427,16 @@ "{WK_TB00000023_RTOS}" "TOOLBAR 0" 59419 2 9 "0.00" 0 0 0 0 0 17 0 "" "0.0" "{WK_TB00000026_MACRO}" "TOOLBAR 0" 59419 1 6 "0.00" 0 0 0 0 0 17 0 "" "0.0" "{WK_TB00000028_RTOSDEBUG}" "TOOLBAR 0" 59419 2 2 "0.00" 0 0 0 0 0 17 0 "" "0.0" -"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 3 "0.00" 0 0 0 0 0 17 0 "" "0.0" +"{WK_TB00000029_SYSTEMTOOL}" "TOOLBAR 0" 59419 2 4 "0.00" 0 0 0 0 0 17 0 "" "0.0" [WINDOW_POSITION_STATE_DATA_VD2] [WINDOW_POSITION_STATE_DATA_VD3] [WINDOW_POSITION_STATE_DATA_VD4] [WINDOW_Z_ORDER] +"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\regtest.src" +"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portasm.src" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\main.c" "C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\port.c" -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\intprg.c" -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\resetprg.c" -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\portable\Renesas\SH2A_FPU\portmacro.h" "C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\vecttbl.c" -"C:\E\Dev\FreeRTOS\WorkingCopy\Demo\SuperH_SH7216_Renesas\RTOSDemo\FreeRTOSConfig.h" -"C:\E\Dev\FreeRTOS\WorkingCopy\Source\include\list.h" [TARGET_NAME] "SH7216 E10A-USB SYSTEM (SH2A-FPU)" "" 0 [STATUSBAR_STATEINFO_VD1] @@ -434,9 +483,5 @@ [FLASH_DETAILS] "" 0 0 "" 0 "" 0 0 "" 0 0 0 0 0 0 0 "" "" "" "" "" [BREAKPOINTS] -"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\intprg.c" 291 2518 1 "{00000000-0000-0000-C000-000000000046}" "" -"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\intprg.c" 299 2524 1 "{00000000-0000-0000-C000-000000000046}" "" -"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\intprg.c" 307 2530 1 "{00000000-0000-0000-C000-000000000046}" "" -"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\main.c" 139 4690 1 "{00000000-0000-0000-C000-000000000046}" "" -"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\main.c" 154 4710 1 "{00000000-0000-0000-C000-000000000046}" "" +"c:\e\dev\freertos\workingcopy\demo\superh_sh7216_renesas\rtosdemo\regtest.src" 89 7808 1 "{00000000-0000-0000-C000-000000000046}" "" [END] diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c index 5afaa787a..e5fee0dce 100644 --- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c +++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/intprg.c @@ -16,35 +16,35 @@ #pragma section IntPRG // 4 Illegal code -void INT_Illegal_code(void){/* sleep(); */} +void INT_Illegal_code(void){for( ;; ); /* sleep(); */} // 5 Reserved // 6 Illegal slot -void INT_Illegal_slot(void){/* sleep(); */} +void INT_Illegal_slot(void){for( ;; ); /* sleep(); */} // 7 Reserved // 8 Reserved // 9 CPU Address error -void INT_CPU_Address(void){/* sleep(); */} +void INT_CPU_Address(void){for( ;; ); /* sleep(); */} // 10 DMAC Address error -void INT_DMAC_Address(void){/* sleep(); */} +void INT_DMAC_Address(void){for( ;; ); /* sleep(); */} // 11 NMI -void INT_NMI(void){/* sleep(); */} +void INT_NMI(void){for( ;; ); /* sleep(); */} // 12 User breakpoint trap -void INT_User_Break(void){/* sleep(); */} +void INT_User_Break(void){for( ;; ); /* sleep(); */} // 13 Reserved // 14 H-UDI -void INT_HUDI(void){/* sleep(); */} +void INT_HUDI(void){for( ;; ); /* sleep(); */} // 15 Register bank over -void INT_Bank_Overflow(void){/* sleep(); */} +void INT_Bank_Overflow(void){for( ;; ); /* sleep(); */} // 16 Register bank under -void INT_Bank_Underflow(void){/* sleep(); */} +void INT_Bank_Underflow(void){for( ;; ); /* sleep(); */} // 17 ZERO DIV -void INT_Divide_by_Zero(void){/* sleep(); */} +void INT_Divide_by_Zero(void){for( ;; ); /* sleep(); */} // 18 OVER DIV -void INT_Divide_Overflow(void){/* sleep(); */} +void INT_Divide_Overflow(void){for( ;; ); /* sleep(); */} // 19 Reserved // 20 Reserved @@ -72,85 +72,85 @@ void INT_Divide_Overflow(void){/* sleep(); */} // 31 Reserved // 32 TRAPA (User Vecter) -void INT_TRAPA32(void){/* sleep(); */} +void INT_TRAPA32(void){ for( ;; ); /* sleep(); */ } // 33 TRAPA (User Vecter) -void INT_TRAPA33(void){/* sleep(); */} +void INT_TRAPA33(void){for( ;; ); /* sleep(); */} // 34 TRAPA (User Vecter) -void INT_TRAPA34(void){/* sleep(); */} +void INT_TRAPA34(void){for( ;; ); /* sleep(); */} // 35 TRAPA (User Vecter) -void INT_TRAPA35(void){/* sleep(); */} +void INT_TRAPA35(void){for( ;; ); /* sleep(); */} // 36 TRAPA (User Vecter) -void INT_TRAPA36(void){/* sleep(); */} +void INT_TRAPA36(void){for( ;; ); /* sleep(); */} // 37 TRAPA (User Vecter) -void INT_TRAPA37(void){/* sleep(); */} +void INT_TRAPA37(void){for( ;; ); /* sleep(); */} // 38 TRAPA (User Vecter) -void INT_TRAPA38(void){/* sleep(); */} +void INT_TRAPA38(void){for( ;; ); /* sleep(); */} // 39 TRAPA (User Vecter) -void INT_TRAPA39(void){/* sleep(); */} +void INT_TRAPA39(void){for( ;; ); /* sleep(); */} // 40 TRAPA (User Vecter) -void INT_TRAPA40(void){/* sleep(); */} +void INT_TRAPA40(void){for( ;; ); /* sleep(); */} // 41 TRAPA (User Vecter) -void INT_TRAPA41(void){/* sleep(); */} +void INT_TRAPA41(void){for( ;; ); /* sleep(); */} // 42 TRAPA (User Vecter) -void INT_TRAPA42(void){/* sleep(); */} +void INT_TRAPA42(void){for( ;; ); /* sleep(); */} // 43 TRAPA (User Vecter) -void INT_TRAPA43(void){/* sleep(); */} +void INT_TRAPA43(void){for( ;; ); /* sleep(); */} // 44 TRAPA (User Vecter) -void INT_TRAPA44(void){/* sleep(); */} +void INT_TRAPA44(void){for( ;; ); /* sleep(); */} // 45 TRAPA (User Vecter) -void INT_TRAPA45(void){/* sleep(); */} +void INT_TRAPA45(void){for( ;; ); /* sleep(); */} // 46 TRAPA (User Vecter) -void INT_TRAPA46(void){/* sleep(); */} +void INT_TRAPA46(void){for( ;; ); /* sleep(); */} // 47 TRAPA (User Vecter) -void INT_TRAPA47(void){/* sleep(); */} +void INT_TRAPA47(void){for( ;; ); /* sleep(); */} // 48 TRAPA (User Vecter) -void INT_TRAPA48(void){/* sleep(); */} +void INT_TRAPA48(void){for( ;; ); /* sleep(); */} // 49 TRAPA (User Vecter) -void INT_TRAPA49(void){/* sleep(); */} +void INT_TRAPA49(void){for( ;; ); /* sleep(); */} // 50 TRAPA (User Vecter) -void INT_TRAPA50(void){/* sleep(); */} +void INT_TRAPA50(void){for( ;; ); /* sleep(); */} // 51 TRAPA (User Vecter) -void INT_TRAPA51(void){/* sleep(); */} +void INT_TRAPA51(void){for( ;; ); /* sleep(); */} // 52 TRAPA (User Vecter) -void INT_TRAPA52(void){/* sleep(); */} +void INT_TRAPA52(void){for( ;; ); /* sleep(); */} // 53 TRAPA (User Vecter) -void INT_TRAPA53(void){/* sleep(); */} +void INT_TRAPA53(void){for( ;; ); /* sleep(); */} // 54 TRAPA (User Vecter) -void INT_TRAPA54(void){/* sleep(); */} +void INT_TRAPA54(void){for( ;; ); /* sleep(); */} // 55 TRAPA (User Vecter) -void INT_TRAPA55(void){/* sleep(); */} +void INT_TRAPA55(void){for( ;; ); /* sleep(); */} // 56 TRAPA (User Vecter) -void INT_TRAPA56(void){/* sleep(); */} +void INT_TRAPA56(void){for( ;; ); /* sleep(); */} // 57 TRAPA (User Vecter) -void INT_TRAPA57(void){/* sleep(); */} +void INT_TRAPA57(void){for( ;; ); /* sleep(); */} // 58 TRAPA (User Vecter) -void INT_TRAPA58(void){/* sleep(); */} +void INT_TRAPA58(void){for( ;; ); /* sleep(); */} // 59 TRAPA (User Vecter) -void INT_TRAPA59(void){/* sleep(); */} +void INT_TRAPA59(void){for( ;; ); /* sleep(); */} // 60 TRAPA (User Vecter) -void INT_TRAPA60(void){/* sleep(); */} +void INT_TRAPA60(void){for( ;; ); /* sleep(); */} // 61 TRAPA (User Vecter) -void INT_TRAPA61(void){/* sleep(); */} +void INT_TRAPA61(void){for( ;; ); /* sleep(); */} // 62 TRAPA (User Vecter) -void INT_TRAPA62(void){/* sleep(); */} +void INT_TRAPA62(void){for( ;; ); /* sleep(); */} // 63 TRAPA (User Vecter) -void INT_TRAPA63(void){/* sleep(); */} +void INT_TRAPA63(void){for( ;; ); /* sleep(); */} // 64 Interrupt IRQ0 -void INT_IRQ0(void){/* sleep(); */} +void INT_IRQ0(void){for( ;; ); /* sleep(); */} // 65 Interrupt IRQ1 -void INT_IRQ1(void){/* sleep(); */} +void INT_IRQ1(void){for( ;; ); /* sleep(); */} // 66 Interrupt IRQ2 -void INT_IRQ2(void){/* sleep(); */} +void INT_IRQ2(void){for( ;; ); /* sleep(); */} // 67 Interrupt IRQ3 -void INT_IRQ3(void){/* sleep(); */} +void INT_IRQ3(void){for( ;; ); /* sleep(); */} // 68 Interrupt IRQ4 -void INT_IRQ4(void){/* sleep(); */} +void INT_IRQ4(void){for( ;; ); /* sleep(); */} // 69 Interrupt IRQ5 -void INT_IRQ5(void){/* sleep(); */} +void INT_IRQ5(void){for( ;; ); /* sleep(); */} // 70 Interrupt IRQ6 -void INT_IRQ6(void){/* sleep(); */} +void INT_IRQ6(void){for( ;; ); /* sleep(); */} // 71 Interrupt IRQ7 -void INT_IRQ7(void){/* sleep(); */} +void INT_IRQ7(void){for( ;; ); /* sleep(); */} // 72 Reserved // 73 Reserved @@ -168,21 +168,21 @@ void INT_IRQ7(void){/* sleep(); */} // 79 Reserved // 80 Interrupt PINT0 -void INT_PINT0(void){/* sleep(); */} +void INT_PINT0(void){for( ;; ); /* sleep(); */} // 81 Interrupt PINT1 -void INT_PINT1(void){/* sleep(); */} +void INT_PINT1(void){for( ;; ); /* sleep(); */} // 82 Interrupt PINT2 -void INT_PINT2(void){/* sleep(); */} +void INT_PINT2(void){for( ;; ); /* sleep(); */} // 83 Interrupt PINT3 -void INT_PINT3(void){/* sleep(); */} +void INT_PINT3(void){for( ;; ); /* sleep(); */} // 84 Interrupt PINT4 -void INT_PINT4(void){/* sleep(); */} +void INT_PINT4(void){for( ;; ); /* sleep(); */} // 85 Interrupt PINT5 -void INT_PINT5(void){/* sleep(); */} +void INT_PINT5(void){for( ;; ); /* sleep(); */} // 86 Interrupt PINT6 -void INT_PINT6(void){/* sleep(); */} +void INT_PINT6(void){for( ;; ); /* sleep(); */} // 87 Interrupt PINT7 -void INT_PINT7(void){/* sleep(); */} +void INT_PINT7(void){for( ;; ); /* sleep(); */} // 88 Reserved // 89 Reserved @@ -190,9 +190,9 @@ void INT_PINT7(void){/* sleep(); */} // 90 Reserved // 91 ROM FIFE -void INT_ROM_FIFE(void){/* sleep(); */} +void INT_ROM_FIFE(void){for( ;; ); /* sleep(); */} // 92 A/D ADI0 -void INT_AD_ADI0(void){/* sleep(); */} +void INT_AD_ADI0(void){for( ;; ); /* sleep(); */} // 93 Reserved // 94 Reserved @@ -200,7 +200,7 @@ void INT_AD_ADI0(void){/* sleep(); */} // 95 Reserved // 96 A/D ADI1 -void INT_AD_ADI1(void){/* sleep(); */} +void INT_AD_ADI1(void){for( ;; ); /* sleep(); */} // 97 Reserved // 98 Reserved @@ -216,79 +216,79 @@ void INT_AD_ADI1(void){/* sleep(); */} // 103 Reserved // 104 RCANET0 ERS_0 -void INT_RCANET0_ERS_0(void){/* sleep(); */} +void INT_RCANET0_ERS_0(void){for( ;; ); /* sleep(); */} // 105 RCANET0 OVR_0 -void INT_RCANET0_OVR_0(void){/* sleep(); */} +void INT_RCANET0_OVR_0(void){for( ;; ); /* sleep(); */} // 106 RCANET0 RM01_0 -void INT_RCANET0_RM01_0(void){/* sleep(); */} +void INT_RCANET0_RM01_0(void){for( ;; ); /* sleep(); */} // 107 RCANET0 SLE_0 -void INT_RCANET0_SLE_0(void){/* sleep(); */} +void INT_RCANET0_SLE_0(void){for( ;; ); /* sleep(); */} // 108 DMAC0 DEI0 -void INT_DMAC0_DEI0(void){/* sleep(); */} +void INT_DMAC0_DEI0(void){for( ;; ); /* sleep(); */} // 109 DMAC0 HEI0 -void INT_DMAC0_HEI0(void){/* sleep(); */} +void INT_DMAC0_HEI0(void){for( ;; ); /* sleep(); */} // 110 Reserved // 111 Reserved // 112 DMAC1 DEI1 -void INT_DMAC1_DEI1(void){/* sleep(); */} +void INT_DMAC1_DEI1(void){for( ;; ); /* sleep(); */} // 113 DMAC1 HEI1 -void INT_DMAC1_HEI1(void){/* sleep(); */} +void INT_DMAC1_HEI1(void){for( ;; ); /* sleep(); */} // 114 Reserved // 115 Reserved // 116 DMAC2 DEI2 -void INT_DMAC2_DEI2(void){/* sleep(); */} +void INT_DMAC2_DEI2(void){for( ;; ); /* sleep(); */} // 117 DMAC2 HEI2 -void INT_DMAC2_HEI2(void){/* sleep(); */} +void INT_DMAC2_HEI2(void){for( ;; ); /* sleep(); */} // 118 Reserved // 119 Reserved // 120 DMAC3 DEI3 -void INT_DMAC3_DEI3(void){/* sleep(); */} +void INT_DMAC3_DEI3(void){for( ;; ); /* sleep(); */} // 121 DMAC3 HEI3 -void INT_DMAC3_HEI3(void){/* sleep(); */} +void INT_DMAC3_HEI3(void){for( ;; ); /* sleep(); */} // 122 Reserved // 123 Reserved // 124 DMAC4 DEI4 -void INT_DMAC4_DEI4(void){/* sleep(); */} +void INT_DMAC4_DEI4(void){for( ;; ); /* sleep(); */} // 125 DMAC4 HEI4 -void INT_DMAC4_HEI4(void){/* sleep(); */} +void INT_DMAC4_HEI4(void){for( ;; ); /* sleep(); */} // 126 Reserved // 127 Reserved // 128 DMAC5 DEI5 -void INT_DMAC5_DEI5(void){/* sleep(); */} +void INT_DMAC5_DEI5(void){for( ;; ); /* sleep(); */} // 129 DMAC5 HEI5 -void INT_DMAC5_HEI5(void){/* sleep(); */} +void INT_DMAC5_HEI5(void){for( ;; ); /* sleep(); */} // 130 Reserved // 131 Reserved // 132 DMAC6 DEI6 -void INT_DMAC6_DEI6(void){/* sleep(); */} +void INT_DMAC6_DEI6(void){for( ;; ); /* sleep(); */} // 133 DMAC6 HEI6 -void INT_DMAC6_HEI6(void){/* sleep(); */} +void INT_DMAC6_HEI6(void){for( ;; ); /* sleep(); */} // 134 Reserved // 135 Reserved // 136 DMAC7 DEI7 -void INT_DMAC7_DEI7(void){/* sleep(); */} +void INT_DMAC7_DEI7(void){for( ;; ); /* sleep(); */} // 137 DMAC7 HEI7 -void INT_DMAC7_HEI7(void){/* sleep(); */} +void INT_DMAC7_HEI7(void){for( ;; ); /* sleep(); */} // 138 Reserved // 139 Reserved // 140 CMT CMI0 -void INT_CMT_CMI0(void){/* sleep(); */} +//void INT_CMT_CMI0(void){for( ;; ); /* sleep(); */} // 141 Reserved // 142 Reserved @@ -296,7 +296,7 @@ void INT_CMT_CMI0(void){/* sleep(); */} // 143 Reserved // 144 CMT CMI1 -void INT_CMT_CMI1(void){/* sleep(); */} +void INT_CMT_CMI1(void){for( ;; ); /* sleep(); */} // 145 Reserved // 146 Reserved @@ -304,79 +304,79 @@ void INT_CMT_CMI1(void){/* sleep(); */} // 147 Reserved // 148 BSC CMTI -void INT_BSC_CMTI(void){/* sleep(); */} +void INT_BSC_CMTI(void){for( ;; ); /* sleep(); */} // 149 Reserved // 150 USB EP4FULL -void INT_USB_EP4FULL(void){/* sleep(); */} +void INT_USB_EP4FULL(void){for( ;; ); /* sleep(); */} // 151 USB EP5EMPTY -void INT_USB_EP5EMPTY(void){/* sleep(); */} +void INT_USB_EP5EMPTY(void){for( ;; ); /* sleep(); */} // 152 WDT ITI -void INT_WDT_ITI(void){/* sleep(); */} +void INT_WDT_ITI(void){for( ;; ); /* sleep(); */} // 153 E-DMAC EINT0 -void INT_EDMAC_EINT0(void){/* sleep(); */} +void INT_EDMAC_EINT0(void){for( ;; ); /* sleep(); */} // 154 USB EP1FULL -void INT_USB_EP1FULL(void){/* sleep(); */} +void INT_USB_EP1FULL(void){for( ;; ); /* sleep(); */} // 155 USB EP2EMPTY -void INT_USB_EP2EMPTY(void){/* sleep(); */} +void INT_USB_EP2EMPTY(void){for( ;; ); /* sleep(); */} // 156 MTU2 MTU0 TGI0A -void INT_MTU2_MTU0_TGI0A(void){/* sleep(); */} +void INT_MTU2_MTU0_TGI0A(void){for( ;; ); /* sleep(); */} // 157 MTU2 MTU0 TGI0B -void INT_MTU2_MTU0_TGI0B(void){/* sleep(); */} +void INT_MTU2_MTU0_TGI0B(void){for( ;; ); /* sleep(); */} // 158 MTU2 MTU0 TGI0C -void INT_MTU2_MTU0_TGI0C(void){/* sleep(); */} +void INT_MTU2_MTU0_TGI0C(void){for( ;; ); /* sleep(); */} // 159 MTU2 MTU0 TGI0D -void INT_MTU2_MTU0_TGI0D(void){/* sleep(); */} +void INT_MTU2_MTU0_TGI0D(void){for( ;; ); /* sleep(); */} // 160 MTU2 MTU0 TGI0V -void INT_MTU2_MTU0_TGI0V(void){/* sleep(); */} +void INT_MTU2_MTU0_TGI0V(void){for( ;; ); /* sleep(); */} // 161 MTU2 MTU0 TGI0E -void INT_MTU2_MTU0_TGI0E(void){/* sleep(); */} +void INT_MTU2_MTU0_TGI0E(void){for( ;; ); /* sleep(); */} // 162 MTU2 MTU0 TGI0F -void INT_MTU2_MTU0_TGI0F(void){/* sleep(); */} +void INT_MTU2_MTU0_TGI0F(void){for( ;; ); /* sleep(); */} // 163 Reserved // 164 MTU2 MTU1 TGI1A -void INT_MTU2_MTU1_TGI1A(void){/* sleep(); */} +void INT_MTU2_MTU1_TGI1A(void){for( ;; ); /* sleep(); */} // 165 MTU2 MTU1 TGI1B -void INT_MTU2_MTU1_TGI1B(void){/* sleep(); */} +void INT_MTU2_MTU1_TGI1B(void){for( ;; ); /* sleep(); */} // 166 Reserved // 167 Reserved // 168 MTU2 MTU1 TGI1V -void INT_MTU2_MTU1_TGI1V(void){/* sleep(); */} +void INT_MTU2_MTU1_TGI1V(void){for( ;; ); /* sleep(); */} // 169 MTU2 MTU1 TGI1U -void INT_MTU2_MTU1_TGI1U(void){/* sleep(); */} +void INT_MTU2_MTU1_TGI1U(void){for( ;; ); /* sleep(); */} // 170 Reserved // 171 Reserved // 172 MTU2 MTU2 TGI2A -void INT_MTU2_MTU2_TGI2A(void){/* sleep(); */} +void INT_MTU2_MTU2_TGI2A(void){for( ;; ); /* sleep(); */} // 173 MTU2 MTU2 TGI2B -void INT_MTU2_MTU2_TGI2B(void){/* sleep(); */} +void INT_MTU2_MTU2_TGI2B(void){for( ;; ); /* sleep(); */} // 174 Reserved // 175 Reserved // 176 MTU2 MTU2 TGI2V -void INT_MTU2_MTU2_TGI2V(void){/* sleep(); */} +void INT_MTU2_MTU2_TGI2V(void){for( ;; ); /* sleep(); */} // 177 MTU2 MTU2 TGI2U -void INT_MTU2_MTU2_TGI2U(void){/* sleep(); */} +void INT_MTU2_MTU2_TGI2U(void){for( ;; ); /* sleep(); */} // 178 Reserved // 179 Reserved // 180 MTU2 MTU3 TGI3A -void INT_MTU2_MTU3_TGI3A(void){/* sleep(); */} +void INT_MTU2_MTU3_TGI3A(void){for( ;; ); /* sleep(); */} // 181 MTU2 MTU3 TGI3B -void INT_MTU2_MTU3_TGI3B(void){/* sleep(); */} +void INT_MTU2_MTU3_TGI3B(void){for( ;; ); /* sleep(); */} // 182 MTU2 MTU3 TGI3C -void INT_MTU2_MTU3_TGI3C(void){/* sleep(); */} +void INT_MTU2_MTU3_TGI3C(void){for( ;; ); /* sleep(); */} // 183 MTU2 MTU3 TGI3D -void INT_MTU2_MTU3_TGI3D(void){/* sleep(); */} +void INT_MTU2_MTU3_TGI3D(void){for( ;; ); /* sleep(); */} // 184 MTU2 MTU3 TGI3V -void INT_MTU2_MTU3_TGI3V(void){/* sleep(); */} +void INT_MTU2_MTU3_TGI3V(void){for( ;; ); /* sleep(); */} // 185 Reserved // 186 Reserved @@ -384,15 +384,15 @@ void INT_MTU2_MTU3_TGI3V(void){/* sleep(); */} // 187 Reserved // 188 MTU2 MTU4 TGI4A -void INT_MTU2_MTU4_TGI4A(void){/* sleep(); */} +void INT_MTU2_MTU4_TGI4A(void){for( ;; ); /* sleep(); */} // 189 MTU2 MTU4 TGI4B -void INT_MTU2_MTU4_TGI4B(void){/* sleep(); */} +void INT_MTU2_MTU4_TGI4B(void){for( ;; ); /* sleep(); */} // 190 MTU2 MTU4 TGI4C -void INT_MTU2_MTU4_TGI4C(void){/* sleep(); */} +void INT_MTU2_MTU4_TGI4C(void){for( ;; ); /* sleep(); */} // 191 MTU2 MTU4 TGI4D -void INT_MTU2_MTU4_TGI4D(void){/* sleep(); */} +void INT_MTU2_MTU4_TGI4D(void){for( ;; ); /* sleep(); */} // 192 MTU2 MTU4 TGI4V -void INT_MTU2_MTU4_TGI4V(void){/* sleep(); */} +void INT_MTU2_MTU4_TGI4V(void){for( ;; ); /* sleep(); */} // 193 Reserved // 194 Reserved @@ -400,31 +400,31 @@ void INT_MTU2_MTU4_TGI4V(void){/* sleep(); */} // 195 Reserved // 196 MTU2 MTU5 TGI5U -void INT_MTU2_MTU5_TGI5U(void){/* sleep(); */} +void INT_MTU2_MTU5_TGI5U(void){for( ;; ); /* sleep(); */} // 197 MTU2 MTU5 TGI5V -void INT_MTU2_MTU5_TGI5V(void){/* sleep(); */} +void INT_MTU2_MTU5_TGI5V(void){for( ;; ); /* sleep(); */} // 198 MTU2 MTU5 TGI5W -void INT_MTU2_MTU5_TGI5W(void){/* sleep(); */} +void INT_MTU2_MTU5_TGI5W(void){for( ;; ); /* sleep(); */} // 199 Reserved // 200 POE2 OEI1 -void INT_POE2_OEI1(void){/* sleep(); */} +void INT_POE2_OEI1(void){for( ;; ); /* sleep(); */} // 201 POE2 OEI2 -void INT_POE2_OEI2(void){/* sleep(); */} +void INT_POE2_OEI2(void){for( ;; ); /* sleep(); */} // 202 Reserved // 203 Reserved // 204 MTU2S MTU3S TGI3A -void INT_MTU2S_MTU3S_TGI3A(void){/* sleep(); */} +void INT_MTU2S_MTU3S_TGI3A(void){for( ;; ); /* sleep(); */} // 205 MTU2S MTU3S TGI3B -void INT_MTU2S_MTU3S_TGI3B(void){/* sleep(); */} +void INT_MTU2S_MTU3S_TGI3B(void){for( ;; ); /* sleep(); */} // 206 MTU2S MTU3S TGI3C -void INT_MTU2S_MTU3S_TGI3C(void){/* sleep(); */} +void INT_MTU2S_MTU3S_TGI3C(void){for( ;; ); /* sleep(); */} // 207 MTU2S MTU3S TGI3D -void INT_MTU2S_MTU3S_TGI3D(void){/* sleep(); */} +void INT_MTU2S_MTU3S_TGI3D(void){for( ;; ); /* sleep(); */} // 208 MTU2S MTU3S TGI3V -void INT_MTU2S_MTU3S_TGI3V(void){/* sleep(); */} +void INT_MTU2S_MTU3S_TGI3V(void){for( ;; ); /* sleep(); */} // 209 Reserved // 210 Reserved @@ -432,15 +432,15 @@ void INT_MTU2S_MTU3S_TGI3V(void){/* sleep(); */} // 211 Reserved // 212 MTU2S MTU4S TGI4A -void INT_MTU2S_MTU4S_TGI4A(void){/* sleep(); */} +void INT_MTU2S_MTU4S_TGI4A(void){for( ;; ); /* sleep(); */} // 213 MTU2S MTU4S TGI4B -void INT_MTU2S_MTU4S_TGI4B(void){/* sleep(); */} +void INT_MTU2S_MTU4S_TGI4B(void){for( ;; ); /* sleep(); */} // 214 MTU2S MTU4S TGI4C -void INT_MTU2S_MTU4S_TGI4C(void){/* sleep(); */} +void INT_MTU2S_MTU4S_TGI4C(void){for( ;; ); /* sleep(); */} // 215 MTU2S MTU4S TGI4D -void INT_MTU2S_MTU4S_TGI4D(void){/* sleep(); */} +void INT_MTU2S_MTU4S_TGI4D(void){for( ;; ); /* sleep(); */} // 216 MTU2S MTU4S TGI4V -void INT_MTU2S_MTU4S_TGI4V(void){/* sleep(); */} +void INT_MTU2S_MTU4S_TGI4V(void){for( ;; ); /* sleep(); */} // 217 Reserved // 218 Reserved @@ -448,78 +448,78 @@ void INT_MTU2S_MTU4S_TGI4V(void){/* sleep(); */} // 219 Reserved // 220 MTU2S MTU5S TGI5U -void INT_MTU2S_MTU5S_TGI5U(void){/* sleep(); */} +void INT_MTU2S_MTU5S_TGI5U(void){for( ;; ); /* sleep(); */} // 221 MTU2S MTU5S TGI5V -void INT_MTU2S_MTU5S_TGI5V(void){/* sleep(); */} +void INT_MTU2S_MTU5S_TGI5V(void){for( ;; ); /* sleep(); */} // 222 MTU2S MTU5S TGI5W -void INT_MTU2S_MTU5S_TGI5W(void){/* sleep(); */} +void INT_MTU2S_MTU5S_TGI5W(void){for( ;; ); /* sleep(); */} // 223 Reserved // 224 POE2 OEI3 -void INT_POE2_OEI3(void){/* sleep(); */} +void INT_POE2_OEI3(void){for( ;; ); /* sleep(); */} // 225 Reserved // 226 USB USI0 -void INT_USB_USI0(void){/* sleep(); */} +void INT_USB_USI0(void){for( ;; ); /* sleep(); */} // 227 USB USI1 -void INT_USB_USI1(void){/* sleep(); */} +void INT_USB_USI1(void){for( ;; ); /* sleep(); */} // 228 IIC3 STPI -void INT_IIC3_STPI(void){/* sleep(); */} +void INT_IIC3_STPI(void){for( ;; ); /* sleep(); */} // 229 IIC3 NAKI -void INT_IIC3_NAKI(void){/* sleep(); */} +void INT_IIC3_NAKI(void){for( ;; ); /* sleep(); */} // 230 IIC3 RXI -void INT_IIC3_RXI(void){/* sleep(); */} +void INT_IIC3_RXI(void){for( ;; ); /* sleep(); */} // 231 IIC3 TXI -void INT_IIC3_TXI(void){/* sleep(); */} +void INT_IIC3_TXI(void){for( ;; ); /* sleep(); */} // 232 IIC3 TEI -void INT_IIC3_TEI(void){/* sleep(); */} +void INT_IIC3_TEI(void){for( ;; ); /* sleep(); */} // 233 RSPI SPERI -void INT_RSPI_SPERI(void){/* sleep(); */} +void INT_RSPI_SPERI(void){for( ;; ); /* sleep(); */} // 234 RSPI SPRXI -void INT_RSPI_SPRXI(void){/* sleep(); */} +void INT_RSPI_SPRXI(void){for( ;; ); /* sleep(); */} // 235 RSPI SPTXI -void INT_RSPI_SPTXI(void){/* sleep(); */} +void INT_RSPI_SPTXI(void){for( ;; ); /* sleep(); */} // 236 SCI SCI4 ERI4 -void INT_SCI_SCI4_ERI4(void){/* sleep(); */} +void INT_SCI_SCI4_ERI4(void){for( ;; ); /* sleep(); */} // 237 SCI SCI4 RXI4 -void INT_SCI_SCI4_RXI4(void){/* sleep(); */} +void INT_SCI_SCI4_RXI4(void){for( ;; ); /* sleep(); */} // 238 SCI SCI4 TXI4 -void INT_SCI_SCI4_TXI4(void){/* sleep(); */} +void INT_SCI_SCI4_TXI4(void){for( ;; ); /* sleep(); */} // 239 SCI SCI4 TEI4 -void INT_SCI_SCI4_TEI4(void){/* sleep(); */} +void INT_SCI_SCI4_TEI4(void){for( ;; ); /* sleep(); */} // 240 SCI SCI0 ERI0 -void INT_SCI_SCI0_ERI0(void){/* sleep(); */} +void INT_SCI_SCI0_ERI0(void){for( ;; ); /* sleep(); */} // 241 SCI SCI0 RXI0 -void INT_SCI_SCI0_RXI0(void){/* sleep(); */} +void INT_SCI_SCI0_RXI0(void){for( ;; ); /* sleep(); */} // 242 SCI SCI0 TXI0 -void INT_SCI_SCI0_TXI0(void){/* sleep(); */} +void INT_SCI_SCI0_TXI0(void){for( ;; ); /* sleep(); */} // 243 SCI SCI0 TEI0 -void INT_SCI_SCI0_TEI0(void){/* sleep(); */} +void INT_SCI_SCI0_TEI0(void){for( ;; ); /* sleep(); */} // 244 SCI SCI1 ERI1 -void INT_SCI_SCI1_ERI1(void){/* sleep(); */} +void INT_SCI_SCI1_ERI1(void){for( ;; ); /* sleep(); */} // 245 SCI SCI1 RXI1 -void INT_SCI_SCI1_RXI1(void){/* sleep(); */} +void INT_SCI_SCI1_RXI1(void){for( ;; ); /* sleep(); */} // 246 SCI SCI1 TXI1 -void INT_SCI_SCI1_TXI1(void){/* sleep(); */} +void INT_SCI_SCI1_TXI1(void){for( ;; ); /* sleep(); */} // 247 SCI SCI1 TEI1 -void INT_SCI_SCI1_TEI1(void){/* sleep(); */} +void INT_SCI_SCI1_TEI1(void){for( ;; ); /* sleep(); */} // 248 SCI SCI2 ERI2 -void INT_SCI_SCI2_ERI2(void){/* sleep(); */} +void INT_SCI_SCI2_ERI2(void){for( ;; ); /* sleep(); */} // 249 SCI SCI2 RXI2 -void INT_SCI_SCI2_RXI2(void){/* sleep(); */} +void INT_SCI_SCI2_RXI2(void){for( ;; ); /* sleep(); */} // 250 SCI SCI2 TXI2 -void INT_SCI_SCI2_TXI2(void){/* sleep(); */} +void INT_SCI_SCI2_TXI2(void){for( ;; ); /* sleep(); */} // 251 SCI SCI2 TEI2 -void INT_SCI_SCI2_TEI2(void){/* sleep(); */} +void INT_SCI_SCI2_TEI2(void){for( ;; ); /* sleep(); */} // 252 SCIF SCIF3 BRI3 -void INT_SCIF_SCIF3_BRI3(void){/* sleep(); */} +void INT_SCIF_SCIF3_BRI3(void){for( ;; ); /* sleep(); */} // 253 SCIF SCIF3 ERI3 -void INT_SCIF_SCIF3_ERI3(void){/* sleep(); */} +void INT_SCIF_SCIF3_ERI3(void){for( ;; ); /* sleep(); */} // 254 SCIF SCIF3 RXI3 -void INT_SCIF_SCIF3_RXI3(void){/* sleep(); */} +void INT_SCIF_SCIF3_RXI3(void){for( ;; ); /* sleep(); */} // 255 SCIF SCIF3 TXI3 -void INT_SCIF_SCIF3_TXI3(void){/* sleep(); */} +void INT_SCIF_SCIF3_TXI3(void){for( ;; ); /* sleep(); */} // Dummy -void Dummy(void){/* sleep(); */} +void Dummy(void){ for( ;; ); sleep(); } /* End of File */ diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c index bc5e76c36..758a85cac 100644 --- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c +++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/main.c @@ -62,14 +62,22 @@ void vApplicationMallocFailedHook( void ); void vApplicationIdleHook( void ); static void prvSetupHardware( void ); +extern void vRegTest1Task( void *pvParameters ); +extern void vRegTest2Task( void *pvParameters ); + +unsigned long ulRegTest1CycleCount = 0UL, ulRegTest2CycleCount = 0UL; + /*-----------------------------------------------------------*/ void main(void) { prvSetupHardware(); - + + xTaskCreate( vRegTest1Task, "RegTest1", configMINIMAL_STACK_SIZE, ( void * ) 0x12345678UL, 1, NULL ); + xTaskCreate( vRegTest2Task, "RegTest2", configMINIMAL_STACK_SIZE, ( void * ) 0x11223344UL, 1, NULL ); + vTaskStartScheduler(); - taskENABLE_INTERRUPTS(); + for( ;; ); } /*-----------------------------------------------------------*/ @@ -146,15 +154,26 @@ unsigned long ulCompareMatch = ( configPERIPHERAL_CLOCK_HZ / ( configTICK_RATE_H } /*-----------------------------------------------------------*/ -//#pragma interrupt (vTempISR) -//void vTempISR( void ); - -void xINT_CMT_CMI0( void ) +void INT_CMT_CMI0( void ) { - CMT0.CMCSR.BIT.CMF = 0; -} - - +static unsigned long ul = 0; + ul++; + if( ul >= 1000 ) + { + if( PE.DR.WORD & ( 0x01 << 9 ) ) + { + PE.DR.WORD &= ~( 0x01 << 9 ); + } + else + { + PE.DR.WORD |= ( 0x01 << 9 ); + } + + ul = 0; + } + CMT0.CMCSR.BIT.CMF = 0; +} +/*-----------------------------------------------------------*/ diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/regtest.src b/Demo/SuperH_SH7216_Renesas/RTOSDemo/regtest.src new file mode 100644 index 000000000..0cf566dbc --- /dev/null +++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/regtest.src @@ -0,0 +1,176 @@ +;/* +; FreeRTOS V6.0.1 - Copyright (C) 2009 Real Time Engineers Ltd. +; +; *************************************************************************** +; * * +; * If you are: * +; * * +; * + New to FreeRTOS, * +; * + Wanting to learn FreeRTOS or multitasking in general quickly * +; * + Looking for basic training, * +; * + Wanting to improve your FreeRTOS skills and productivity * +; * * +; * then take a look at the FreeRTOS eBook * +; * * +; * "Using the FreeRTOS Real Time Kernel - a Practical Guide" * +; * http://www.FreeRTOS.org/Documentation * +; * * +; * A pdf reference manual is also available. Both are usually delivered * +; * to your inbox within 20 minutes to two hours when purchased between 8am * +; * and 8pm GMT (although please allow up to 24 hours in case of * +; * exceptional circumstances). Thank you for your support! * +; * * +; *************************************************************************** +; +; This file is part of the FreeRTOS distribution. +; +; FreeRTOS is free software; you can redistribute it and/or modify it under +; the terms of the GNU General Public License (version 2) as published by the +; Free Software Foundation AND MODIFIED BY the FreeRTOS exception. +; ***NOTE*** The exception to the GPL is included to allow you to distribute +; a combined work that includes FreeRTOS without being obliged to provide the +; source code for proprietary components outside of the FreeRTOS kernel. +; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT +; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +; more details. You should have received a copy of the GNU General Public +; License and the FreeRTOS license exception along with FreeRTOS; if not it +; can be viewed here: http://www.freertos.org/a00114.html and also obtained +; by writing to Richard Barry, contact details for whom are available on the +; FreeRTOS WEB site. +; +; 1 tab == 4 spaces! +; +; http://www.FreeRTOS.org - Documentation, latest information, license and +; contact details. +; +; http://www.SafeRTOS.com - A version that is certified for use in safety +; critical systems. +; +; http://www.OpenRTOS.com - Commercial support, development, porting, +; licensing and training services. +;*/ + + .import _pxCurrentTCB + .import _vTaskSwitchContext + .import _ulRegTest1CycleCount + .import _ulRegTest2CycleCount + + .export _vRegTest1Task + .export _vRegTest2Task + + .section P + +_vRegTest1Task: + + mov #3, r2 + mov #4, r3 + mov #5, r4 + mov #6, r5 + mov #7, r6 + mov #8, r7 + mov #9, r8 + mov #10, r9 + mov #11, r10 + mov #12, r11 + mov #13, r12 + mov #14, r13 + + mov #15, r0 + lds r0, macl + mov #16, r0 + lds r0, mach + mov #17, r0 + ldc r0, gbr + +_vRegTest1Loop: + + ; Reset r1 which was used in the tests. + mov #2, r1 + + mov #2, r0 + cmp/eq r0, r1 + bf _vRegTestError + + mov #3, r0 + cmp/eq r0, r2 + bf _vRegTestError + + mov #4, r0 + cmp/eq r0, r3 + bf _vRegTestError + + mov #5, r0 + cmp/eq r0, r4 + bf _vRegTestError + + mov #6, r0 + cmp/eq r0, r5 + bf _vRegTestError + + mov #7, r0 + cmp/eq r0, r6 + bf _vRegTestError + + mov #8, r0 + cmp/eq r0, r7 + bf _vRegTestError + + mov #9, r0 + cmp/eq r0, r8 + bf _vRegTestError + + mov #10, r0 + cmp/eq r0, r9 + bf _vRegTestError + + mov #11, r0 + cmp/eq r0, r10 + bf _vRegTestError + + mov #12, r0 + cmp/eq r0, r11 + bf _vRegTestError + + mov #13, r0 + cmp/eq r0, r12 + bf _vRegTestError + + mov #14, r0 + cmp/eq r0, r13 + bf _vRegTestError + + sts macl, r0 + mov #15, r1 + cmp/eq r0, r1 + bf _vRegTestError + + sts mach, r0 + mov #16, r1 + cmp/eq r0, r1 + bf _vRegTestError + + stc gbr, r0 + mov #17, r1 + cmp/eq r0, r1 + bf _vRegTestError + + mov.l #_ulRegTest1CycleCount, r0 + mov.l @r0, r1 + add #1, r1 + mov.l r1, @r0 + + bra _vRegTest1Task + nop + +_vRegTest2Task: + + trapa #33 + bra _vRegTest2Task + nop + +_vRegTestError: + bra _vRegTestError + + .end + diff --git a/Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c b/Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c index 5fb4e35e6..a0f18d465 100644 --- a/Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c +++ b/Demo/SuperH_SH7216_Renesas/RTOSDemo/vecttbl.c @@ -13,6 +13,9 @@ #include "vect.h" +extern void vPortStartFirstTask( void ); +extern void vPortYield( void ); + #pragma section VECTTBL void *RESET_Vectors[] = { @@ -89,9 +92,11 @@ void *INT_Vectors[] = { // 31 Reserved (void*) Dummy, // 32 TRAPA (User Vecter) - (void*) INT_TRAPA32, +// (void*) INT_TRAPA32, + (void*) vPortStartFirstTask, // 33 TRAPA (User Vecter) - (void*) INT_TRAPA33, +// (void*) INT_TRAPA33, + (void*) vPortYield, // 34 TRAPA (User Vecter) (void*) INT_TRAPA34, // 35 TRAPA (User Vecter)