From: Otavio Salvador Date: Tue, 22 Jan 2013 15:01:02 +0000 (+0000) Subject: mxs: mmc: Fix MMC reset on iMX23 X-Git-Tag: v2013.04-rc1~48^2~34^2~5 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8000d8a8260c95727b6357a638a5e80625d7a899;p=u-boot mxs: mmc: Fix MMC reset on iMX23 This does the same reset mask as done in v3.7 Linux kernel code. The block is properly configured for MMC operation that way. Signed-off-by: Otavio Salvador Cc: Marek Vasut Cc: Fabio Estevam Cc: Stefano Babic --- diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 0c4cd54b79..9d71202ef3 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -334,11 +334,17 @@ static int mxsmmc_init(struct mmc *mmc) /* Reset SSP */ mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); - /* 8 bits word length in MMC mode */ - clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1, - SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK | - SSP_CTRL1_DMA_ENABLE, - SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS); + /* Reconfigure the SSP block for MMC operation */ + writel(SSP_CTRL1_SSP_MODE_SD_MMC | + SSP_CTRL1_WORD_LENGTH_EIGHT_BITS | + SSP_CTRL1_DMA_ENABLE | + SSP_CTRL1_POLARITY | + SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | + SSP_CTRL1_DATA_CRC_IRQ_EN | + SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | + SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | + SSP_CTRL1_RESP_ERR_IRQ_EN, + &ssp_regs->hw_ssp_ctrl1_set); /* Set initial bit clock 400 KHz */ mxs_set_ssp_busclock(priv->id, 400);