From: Marc Zyngier <marc.zyngier@arm.com>
Date: Sat, 12 Jul 2014 13:23:59 +0000 (+0100)
Subject: ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
X-Git-Tag: v2014.10-rc1~38^2~9
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=800c83522ca6a7d6fd0b058f423501b4cc52d6d6;p=u-boot

ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
---

diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 6367e09612..12de5c2d17 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -46,6 +46,7 @@ _secure_monitor:
 #endif
 
 	mcr	p15, 0, r1, c1, c1, 0		@ write SCR (with NS bit set)
+	isb
 
 #ifdef CONFIG_ARMV7_VIRT
 	mrceq	p15, 0, r0, c12, c0, 1		@ get MVBAR value