From: rtel Date: Fri, 20 Dec 2019 02:54:30 +0000 (+0000) Subject: Increase test coverage for queue sets. X-Git-Tag: V10.3.0~54 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8024c9c0d50a401b1544e012559cace9cba4fddf;p=freertos Increase test coverage for queue sets. Rename the CORTEX_M0+_LPC51U68_LPCXpresso demo to CORTEX_M0+_LPC51U68_GCC_IAR_KEIL as it supports all three compilers. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2769 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.cproject b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.cproject new file mode 100644 index 000000000..7164d9ef8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.cproject @@ -0,0 +1,797 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + SDK_2.x_LPCXpresso51U68 + 2.6.0 + middleware.baremetal.LPC51U68;platform.drivers.clock.LPC51U68;device.LPC51U68_CMSIS.LPC51U68;platform.Include_common.LPC51U68;platform.Include_core_cm0plus.LPC51U68;platform.drivers.common.LPC51U68;platform.drivers.power.LPC51U68;platform.drivers.reset.LPC51U68;platform.drivers.flexcomm.LPC51U68;platform.drivers.flexcomm_usart.LPC51U68;platform.drivers.lpc_gpio.LPC51U68;platform.drivers.lpc_iocon.LPC51U68;platform.drivers.pint.LPC51U68;component.serial_manager.LPC51U68;component.lists.LPC51U68;component.serial_manager_uart.LPC51U68;component.usart_adapter.LPC51U68;platform.utilities.assert.LPC51U68;utility.debug_console.LPC51U68;device.LPC51U68_startup.LPC51U68;project_template.lpcxpresso51u68.LPC51U68;platform.drivers.ctimer.LPC51U68; + lpcxpresso51u68 + LPC51U68JBD64 + cm0plus + core0_LPC51U68 + + + <?xml version="1.0" encoding="UTF-8"?> +<TargetConfig> +<Properties property_3="NXP" property_4="LPC51U68" property_count="5" version="100300"/> +<infoList vendor="NXP"> +<info chip="LPC51U68" name="LPC51U68"> +<chip> +<name>LPC51U68</name> +<family>LPC51U68</family> +<vendor>NXP</vendor> +<memory can_program="true" id="Flash" is_ro="true" size="256" type="Flash"/> +<memory id="RAM" size="96" type="RAM"/> +<memoryInstance derived_from="Flash" driver="LPC51U6x_256K.cfx" edited="true" id="PROGRAM_FLASH" location="0x0" size="0x40000"/> +<memoryInstance derived_from="RAM" edited="true" id="SRAM_00" location="0x4000000" size="0x8000"/> +<memoryInstance derived_from="RAM" edited="true" id="SRAM0" location="0x20000000" size="0x10000"/> +</chip> +<processor> +<name gcc_name="cortex-m0plus">Cortex-M0+</name> +<family>Cortex-M</family> +</processor> +</info> +</infoList> +</TargetConfig> + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.gitignore b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.gitignore new file mode 100644 index 000000000..555928331 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.gitignore @@ -0,0 +1,13 @@ +# Ignore Xpresso generated files. +/.settings/ +/Debug/ + +# Ignore Keil generated files. +*.uvguix.* +EventRecorderStub.scvd +/Listings/ +/Objects/ + +# Ignore IAR generated files. +/settings/ +/Debug_IAR/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.project b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.project new file mode 100644 index 000000000..21505b1a4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.project @@ -0,0 +1,317 @@ + + + CORTEX_M0+_LPC51U68_LPCXpresso + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + com.nxp.mcuxpresso.core.datamodels.sdkNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + Minimal + 2 + virtual:/virtual + + + Source + 2 + virtual:/virtual + + + Minimal/IntQueue.c + 1 + PARENT-1-PROJECT_LOC/Common/Minimal/IntQueue.c + + + Minimal/blocktim.c + 1 + PARENT-1-PROJECT_LOC/Common/Minimal/blocktim.c + + + Minimal/countsem.c + 1 + PARENT-1-PROJECT_LOC/Common/Minimal/countsem.c + + + Minimal/recmutex.c + 1 + PARENT-1-PROJECT_LOC/Common/Minimal/recmutex.c + + + Source/croutine.c + 1 + PARENT-2-PROJECT_LOC/Source/croutine.c + + + Source/event_groups.c + 1 + PARENT-2-PROJECT_LOC/Source/event_groups.c + + + Source/include + 2 + virtual:/virtual + + + Source/list.c + 1 + PARENT-2-PROJECT_LOC/Source/list.c + + + Source/portable + 2 + virtual:/virtual + + + Source/queue.c + 1 + PARENT-2-PROJECT_LOC/Source/queue.c + + + Source/stream_buffer.c + 1 + PARENT-2-PROJECT_LOC/Source/stream_buffer.c + + + Source/tasks.c + 1 + PARENT-2-PROJECT_LOC/Source/tasks.c + + + Source/timers.c + 1 + PARENT-2-PROJECT_LOC/Source/timers.c + + + Source/include/FreeRTOS.h + 1 + PARENT-2-PROJECT_LOC/Source/include/FreeRTOS.h + + + Source/include/StackMacros.h + 1 + PARENT-2-PROJECT_LOC/Source/include/StackMacros.h + + + Source/include/atomic.h + 1 + PARENT-2-PROJECT_LOC/Source/include/atomic.h + + + Source/include/croutine.h + 1 + PARENT-2-PROJECT_LOC/Source/include/croutine.h + + + Source/include/deprecated_definitions.h + 1 + PARENT-2-PROJECT_LOC/Source/include/deprecated_definitions.h + + + Source/include/event_groups.h + 1 + PARENT-2-PROJECT_LOC/Source/include/event_groups.h + + + Source/include/list.h + 1 + PARENT-2-PROJECT_LOC/Source/include/list.h + + + Source/include/message_buffer.h + 1 + PARENT-2-PROJECT_LOC/Source/include/message_buffer.h + + + Source/include/mpu_prototypes.h + 1 + PARENT-2-PROJECT_LOC/Source/include/mpu_prototypes.h + + + Source/include/mpu_wrappers.h + 1 + PARENT-2-PROJECT_LOC/Source/include/mpu_wrappers.h + + + Source/include/portable.h + 1 + PARENT-2-PROJECT_LOC/Source/include/portable.h + + + Source/include/projdefs.h + 1 + PARENT-2-PROJECT_LOC/Source/include/projdefs.h + + + Source/include/queue.h + 1 + PARENT-2-PROJECT_LOC/Source/include/queue.h + + + Source/include/semphr.h + 1 + PARENT-2-PROJECT_LOC/Source/include/semphr.h + + + Source/include/stack_macros.h + 1 + PARENT-2-PROJECT_LOC/Source/include/stack_macros.h + + + Source/include/stream_buffer.h + 1 + PARENT-2-PROJECT_LOC/Source/include/stream_buffer.h + + + Source/include/task.h + 1 + PARENT-2-PROJECT_LOC/Source/include/task.h + + + Source/include/timers.h + 1 + PARENT-2-PROJECT_LOC/Source/include/timers.h + + + Source/portable/GCC + 2 + virtual:/virtual + + + Source/portable/MemMang + 2 + virtual:/virtual + + + Source/portable/GCC/ARM_CM0 + 2 + virtual:/virtual + + + Source/portable/MemMang/heap_5.c + 1 + PARENT-2-PROJECT_LOC/Source/portable/MemMang/heap_5.c + + + Source/portable/GCC/ARM_CM0/port.c + 1 + PARENT-2-PROJECT_LOC/Source/portable/GCC/ARM_CM0/port.c + + + Source/portable/GCC/ARM_CM0/portmacro.h + 1 + PARENT-2-PROJECT_LOC/Source/portable/GCC/ARM_CM0/portmacro.h + + + + + 1576106451918 + + 30 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-Keil_specific + + + + 1576106451932 + + 30 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-IAR_specific + + + + 1576106451941 + + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-CORTEX_M0+_LPC51U68_Keil* + + + + 1576106451951 + + 30 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-Debug_IAR + + + + 1576106451962 + + 30 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-Listings + + + + 1576106451973 + + 30 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-Objects + + + + 1576106451989 + + 30 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-settings + + + + 1576106452039 + + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-CORTEX_M0+_LPC51U68_IAR* + + + + 1576106452048 + + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-EventRecorderStub.scvd + + + + + + FREERTOS_DEMO_ROOT + $%7BPARENT-2-PROJECT_LOC%7D/Demo + + + FREERTOS_ROOT + $%7BPARENT-2-PROJECT_LOC%7D/Source + + + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.settings/language.settings.xml b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.settings/language.settings.xml new file mode 100644 index 000000000..b9880cafd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/.settings/language.settings.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/arm_common_tables.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/arm_common_tables.h new file mode 100644 index 000000000..233f62357 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/arm_common_tables.h @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) +#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) +#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) +#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) +#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/arm_const_structs.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/arm_const_structs.h new file mode 100644 index 000000000..677073e59 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/arm_const_structs.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_armcc.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_armcc.h new file mode 100644 index 000000000..f204e241c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_armcc.h @@ -0,0 +1,870 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_armclang.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_armclang.h new file mode 100644 index 000000000..f79b4120d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_armclang.h @@ -0,0 +1,1877 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF); + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF); + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF); + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_compiler.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_compiler.h new file mode 100644 index 000000000..79a2cac36 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_compiler.h @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_gcc.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_gcc.h new file mode 100644 index 000000000..a99a35927 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_gcc.h @@ -0,0 +1,2088 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.0.3 + * @date 16. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + register uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + +#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ (uint8_t)__builtin_clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_iccarm.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_iccarm.h new file mode 100644 index 000000000..7b3f7f768 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_iccarm.h @@ -0,0 +1,913 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.0.5 + * @date 10. January 2018 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2018 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_version.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_version.h new file mode 100644 index 000000000..ae3f2e33d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/core_cm0plus.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/core_cm0plus.h new file mode 100644 index 000000000..8fd78500c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CMSIS/core_cm0plus.h @@ -0,0 +1,1023 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.4 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; + +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/CORTEX_M0+_LPC51U68_IAR.ewd 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### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + CORTEX_M0+_LPC51U68_Keil + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + LPC51U68JBD64 + NXP + NXP.LPC51U68_DFP.12.0.0 + http://mcuxpresso.nxp.com/cmsis_pack/repo/ + IRAM(0x20000000,0x010000) IRAM2(0x04000000,0x8000) IROM(0x00000000,0x040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0LPC51U68_256 -FS00 -FL040000 -FP0($$Device:LPC51U68JBD64$arm\LPC51U68_256.FLM)) + 0 + $$Device:LPC51U68JBD64$fsl_device_registers.h + + + + + + + + + + $$Device:LPC51U68JBD64$LPC51U68.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + CORTEX_M0+_LPC51U68_Keil + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + $K/ARM/BIN/ElfDwT.exe !L BASEADDRESS(0x0) + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x10000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x4000000 + 0x8000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + ..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;..\Common\include;.\CMSIS;.\app;.\board\boards;.\component\lists;.\component\serial_manager;.\component\uart;.\device;.\drivers;.\utilities;.\Keil_specific + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x04000000 + + .\Keil_specific\LPC51U68_flash.scf + + + + + + + + + + + Application_Code + + + main_full.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\app\main_full.c + + + main_blinky.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\app\main_blinky.c + + + main.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\app\main.c + + + IntQueueTimer.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\app\IntQueueTimer.h + + + IntQueueTimer.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\app\IntQueueTimer.c + + + FreeRTOSConfig.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\app\FreeRTOSConfig.h + + + RegTest_Keil.s + 2 + .\Keil_specific\RegTest_Keil.s + + + compiler_attributes.h + 5 + .\Keil_specific\compiler_attributes.h + + + + + board + + + board.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\board\boards\board.c + + + board.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\board\boards\board.h + + + clock_config.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\board\boards\clock_config.c + + + clock_config.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\board\boards\clock_config.h + + + peripherals.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\board\boards\peripherals.c + + + peripherals.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\board\boards\peripherals.h + + + pin_mux.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\board\boards\pin_mux.c + + + pin_mux.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\board\boards\pin_mux.h + + + + + component-lists + + + generic_list.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\lists\generic_list.h + + + generic_list.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\lists\generic_list.c + + + + + component-serial-manager + + + serial_manager.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\serial_manager\serial_manager.c + + + serial_manager.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\serial_manager\serial_manager.h + + + serial_port_internal.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\serial_manager\serial_port_internal.h + + + serial_port_uart.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\serial_manager\serial_port_uart.c + + + serial_port_uart.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\serial_manager\serial_port_uart.h + + + + + componnet-uart + + + uart.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\uart\uart.h + + + usart_adapter.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\uart\usart_adapter.c + + + + + device + + + fsl_device_registers.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\device\fsl_device_registers.h + + + LPC51U68.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\device\LPC51U68.h + + + LPC51U68_features.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\device\LPC51U68_features.h + + + system_LPC51U68.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\device\system_LPC51U68.c + + + system_LPC51U68.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\device\system_LPC51U68.h + + + + + drivers + + + fsl_clock.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_clock.c + + + fsl_clock.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_clock.h + + + fsl_common.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_common.c + + + fsl_common.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_common.h + + + fsl_ctimer.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_ctimer.c + + + fsl_ctimer.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_ctimer.h + + + fsl_flexcomm.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_flexcomm.c + + + fsl_flexcomm.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_flexcomm.h + + + fsl_gpio.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_gpio.c + + + fsl_gpio.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_gpio.h + + + fsl_iocon.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_iocon.h + + + fsl_pint.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_pint.c + + + fsl_pint.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_pint.h + + + fsl_power.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_power.c + + + fsl_power.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_power.h + + + fsl_reset.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_reset.c + + + fsl_reset.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_reset.h + + + fsl_usart.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_usart.c + + + fsl_usart.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_usart.h + + + + + startup + + + startup_LPC51U68.s + 2 + .\Keil_specific\startup_LPC51U68.s + + + + + utilities + + + fsl_assert.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_assert.c + + + fsl_debug_console.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_debug_console.c + + + fsl_debug_console.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_debug_console.h + + + fsl_debug_console_conf.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_debug_console_conf.h + + + fsl_str.c + 1 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_str.c + + + fsl_str.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_str.h + + + + + CMSIS + + + arm_common_tables.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\arm_common_tables.h + + + arm_const_structs.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\arm_const_structs.h + + + arm_math.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\arm_math.h + + + cmsis_armcc.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_armcc.h + + + cmsis_armclang.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_armclang.h + + + cmsis_compiler.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_compiler.h + + + cmsis_gcc.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_gcc.h + + + cmsis_iccarm.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_iccarm.h + + + cmsis_version.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_version.h + + + core_cm0plus.h + 5 + ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\core_cm0plus.h + + + + + FreeRTOS_Source + + + croutine.c + 1 + ..\..\Source\croutine.c + + + event_groups.c + 1 + ..\..\Source\event_groups.c + + + list.c + 1 + ..\..\Source\list.c + + + queue.c + 1 + ..\..\Source\queue.c + + + stream_buffer.c + 1 + ..\..\Source\stream_buffer.c + + + tasks.c + 1 + ..\..\Source\tasks.c + + + timers.c + 1 + ..\..\Source\timers.c + + + atomic.h + 5 + ..\..\Source\include\atomic.h + + + croutine.h + 5 + ..\..\Source\include\croutine.h + + + deprecated_definitions.h + 5 + ..\..\Source\include\deprecated_definitions.h + + + event_groups.h + 5 + ..\..\Source\include\event_groups.h + + + FreeRTOS.h + 5 + ..\..\Source\include\FreeRTOS.h + + + list.h + 5 + ..\..\Source\include\list.h + + + message_buffer.h + 5 + ..\..\Source\include\message_buffer.h + + + mpu_prototypes.h + 5 + ..\..\Source\include\mpu_prototypes.h + + + mpu_wrappers.h + 5 + ..\..\Source\include\mpu_wrappers.h + + + portable.h + 5 + ..\..\Source\include\portable.h + + + projdefs.h + 5 + ..\..\Source\include\projdefs.h + + + queue.h + 5 + ..\..\Source\include\queue.h + + + semphr.h + 5 + ..\..\Source\include\semphr.h + + + stack_macros.h + 5 + ..\..\Source\include\stack_macros.h + + + StackMacros.h + 5 + ..\..\Source\include\StackMacros.h + + + stream_buffer.h + 5 + ..\..\Source\include\stream_buffer.h + + + task.h + 5 + ..\..\Source\include\task.h + + + timers.h + 5 + ..\..\Source\include\timers.h + + + port.c + 1 + ..\..\Source\portable\RVDS\ARM_CM0\port.c + + + portmacro.h + 5 + ..\..\Source\portable\RVDS\ARM_CM0\portmacro.h + + + heap_5.c + 1 + ..\..\Source\portable\MemMang\heap_5.c + + + + + Stadard_Demo_Tasks + + + blocktim.h + 5 + ..\Common\include\blocktim.h + + + countsem.h + 5 + ..\Common\include\countsem.h + + + IntQueue.h + 5 + ..\Common\include\IntQueue.h + + + recmutex.h + 5 + ..\Common\include\recmutex.h + + + blocktim.c + 1 + ..\Common\Minimal\blocktim.c + + + IntQueue.c + 1 + ..\Common\Minimal\IntQueue.c + + + recmutex.c + 1 + ..\Common\Minimal\recmutex.c + + + countsem.c + 1 + ..\Common\Minimal\countsem.c + + + + + libs + + + keil_lib_power.lib + 4 + .\Keil_specific\keil_lib_power.lib + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/RegTest.c new file mode 100644 index 000000000..383b8ba82 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/RegTest.c @@ -0,0 +1,195 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +void vRegTest1Task( void ) __attribute__((naked)); +void vRegTest2Task( void ) __attribute__((naked)); + +void vRegTest1Task( void ) +{ + __asm volatile + ( + ".extern ulRegTest1LoopCounter \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r1, #101 \n" + " movs r2, #102 \n" + " movs r3, #103 \n" + " movs r4, #104 \n" + " movs r5, #105 \n" + " movs r6, #106 \n" + " movs r7, #107 \n" + " movs r0, #108 \n" + " mov r8, r0 \n" + " movs r0, #109 \n" + " mov r9, r0 \n" + " movs r0, #110 \n" + " mov r10, r0 \n" + " movs r0, #111 \n" + " mov r11, r0 \n" + " movs r0, #112 \n" + " mov r12, r0 \n" + " movs r0, #100 \n" + " \n" + "reg1_loop: \n" + " \n" + " cmp r0, #100 \n" + " bne reg1_error_loop \n" + " cmp r1, #101 \n" + " bne reg1_error_loop \n" + " cmp r2, #102 \n" + " bne reg1_error_loop \n" + " cmp r3, #103 \n" + " bne reg1_error_loop \n" + " cmp r4, #104 \n" + " bne reg1_error_loop \n" + " cmp r5, #105 \n" + " bne reg1_error_loop \n" + " cmp r6, #106 \n" + " bne reg1_error_loop \n" + " cmp r7, #107 \n" + " bne reg1_error_loop \n" + " movs r0, #108 \n" + " cmp r8, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #109 \n" + " cmp r9, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #110 \n" + " cmp r10, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #111 \n" + " cmp r11, r0 \n" + " bne reg1_error_loop \n" + " movs r0, #112 \n" + " cmp r12, r0 \n" + " bne reg1_error_loop \n" + " \n" + " /* Everything passed, increment the loop counter. */ \n" + " push { r1 } \n" + " ldr r0, =ulRegTest1LoopCounter \n" + " ldr r1, [r0] \n" + " add r1, r1, #1 \n" + " str r1, [r0] \n" + " pop { r1 } \n" + " \n" + " /* Start again. */ \n" + " movs r0, #100 \n" + " b reg1_loop \n" + " \n" + "reg1_error_loop: \n" + " /* If this line is hit then there was an error in a core register value. \n" + " The loop ensures the loop counter stops incrementing. */ \n" + " b reg1_error_loop \n" + " nop \n" + ); +} +/*-----------------------------------------------------------*/ + +void vRegTest2Task( void ) +{ + __asm volatile + ( + ".extern ulRegTest2LoopCounter \n" + " \n" + " /* Fill the core registers with known values. */ \n" + " movs r1, #1 \n" + " movs r2, #2 \n" + " movs r3, #3 \n" + " movs r4, #4 \n" + " movs r5, #5 \n" + " movs r6, #6 \n" + " movs r7, #7 \n" + " movs r0, #8 \n" + " movs r8, r0 \n" + " movs r0, #9 \n" + " mov r9, r0 \n" + " movs r0, #10 \n" + " mov r10, r0 \n" + " movs r0, #11 \n" + " mov r11, r0 \n" + " movs r0, #12 \n" + " mov r12, r0 \n" + " movs r0, #10 \n" + " \n" + "reg2_loop: \n" + " \n" + " cmp r0, #10 \n" + " bne reg2_error_loop \n" + " cmp r1, #1 \n" + " bne reg2_error_loop \n" + " cmp r2, #2 \n" + " bne reg2_error_loop \n" + " cmp r3, #3 \n" + " bne reg2_error_loop \n" + " cmp r4, #4 \n" + " bne reg2_error_loop \n" + " cmp r5, #5 \n" + " bne reg2_error_loop \n" + " cmp r6, #6 \n" + " bne reg2_error_loop \n" + " cmp r7, #7 \n" + " bne reg2_error_loop \n" + " movs r0, #8 \n" + " cmp r8, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #9 \n" + " cmp r9, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #10 \n" + " cmp r10, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #11 \n" + " cmp r11, r0 \n" + " bne reg2_error_loop \n" + " movs r0, #12 \n" + " cmp r12, r0 \n" + " bne reg2_error_loop \n" + " \n" + " /* Everything passed, increment the loop counter. */ \n" + " push { r1 } \n" + " ldr r0, =ulRegTest2LoopCounter \n" + " ldr r1, [r0] \n" + " add r1, r1, #1 \n" + " str r1, [r0] \n" + " pop { r1 } \n" + " \n" + " /* Start again. */ \n" + " movs r0, #10 \n" + " b reg2_loop \n" + " \n" + "reg2_error_loop: \n" + " /* If this line is hit then there was an error in a core register value. \n" + " The loop ensures the loop counter stops incrementing. */ \n" + " b reg2_error_loop \n" + " nop \n" + ); +} +/*-----------------------------------------------------------*/ + + + + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/compiler_attributes.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/compiler_attributes.h new file mode 100644 index 000000000..8abf71e3c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/compiler_attributes.h @@ -0,0 +1,29 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Placing variable at specified address. */ +#define COMPILER_ATTRIBUTE_PLACE_IN_2ND_MEMORY_BANK __attribute__( ( section( ".freertos_heap_2" ) ) ) diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/semihost_hardfault.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/semihost_hardfault.c new file mode 100644 index 000000000..7ce5fadb9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/semihost_hardfault.c @@ -0,0 +1,109 @@ +// **************************************************************************** +// semihost_hardfault.c +// - Provides hard fault handler to allow semihosting code not +// to hang application when debugger not connected. +// +// **************************************************************************** +// Copyright 2017-2019 NXP +// All rights reserved. +// +// Software that is described herein is for illustrative purposes only +// which provides customers with programming information regarding the +// NXP Cortex-M based MCUs. This software is supplied "AS IS" without any +// warranties of any kind, and NXP Semiconductors and its licensor disclaim any +// and all warranties, express or implied, including all implied warranties of +// merchantability, fitness for a particular purpose and non-infringement of +// intellectual property rights. NXP Semiconductors assumes no responsibility +// or liability for the use of the software, conveys no license or rights under +// any patent, copyright, mask work right, or any other intellectual property +// rights in or to any products. NXP Semiconductors reserves the right to make +// changes in the software without notification. NXP Semiconductors also makes +// no representation or warranty that such application will be suitable for the +// specified use without further testing or modification. +// +// Permission to use, copy, modify, and distribute this software and its +// documentation is hereby granted, under NXP Semiconductors' and its +// licensor's relevant copyrights in the software, without fee, provided that it +// is used in conjunction with NXP Semiconductors microcontrollers. This +// copyright, permission, and disclaimer notice must appear in all copies of +// this code. +// **************************************************************************** +// +// ===== DESCRIPTION ===== +// +// One of the issues with applications that make use of semihosting operations +// (such as printf calls) is that the code will not execute correctly when the +// debugger is not connected. Generally this will show up with the application +// appearing to just hang. This may include the application running from reset +// or powering up the board (with the application already in FLASH), and also +// as the application failing to continue to execute after a debug session is +// terminated. +// +// The problem here is that the "bottom layer" of the semihosted variants of +// the C library, semihosting is implemented by a "BKPT 0xAB" instruction. +// When the debug tools are not connected, this instruction triggers a hard +// fault - and the default hard fault handler within an application will +// typically just contains an infinite loop - causing the application to +// appear to have hang when no debugger is connected. +// +// The below code provides an example hard fault handler which instead looks +// to see what the instruction that caused the hard fault was - and if it +// was a "BKPT 0xAB", then it instead returns back to the user application. +// +// In most cases this will allow applications containing semihosting +// operations to execute (to some degree) when the debugger is not connected. +// +// == NOTE == +// +// Correct execution of the application containing semihosted operations +// which are vectored onto this hard fault handler cannot be guaranteed. This +// is because the handler may not return data or return codes that the higher +// level C library code or application code expects. This hard fault handler +// is meant as a development aid, and it is not recommended to leave +// semihosted code in a production build of your application! +// +// **************************************************************************** + +// Allow handler to be removed by setting a define (via command line) +#if !defined (__SEMIHOST_HARDFAULT_DISABLE) + +__attribute__((naked)) +void HardFault_Handler(void){ + __asm( ".syntax unified\n" + // Check which stack is in use + "MOVS R0, #4 \n" + "MOV R1, LR \n" + "TST R0, R1 \n" + "BEQ _MSP \n" + "MRS R0, PSP \n" + "B _process \n" + "_MSP: \n" + "MRS R0, MSP \n" + // Load the instruction that triggered hard fault + "_process: \n" + "LDR R1,[R0,#24] \n" + "LDRH R2,[r1] \n" + // Semihosting instruction is "BKPT 0xAB" (0xBEAB) + "LDR R3,=0xBEAB \n" + "CMP R2,R3 \n" + "BEQ _semihost_return \n" + // Wasn't semihosting instruction so enter infinite loop + "B . \n" + // Was semihosting instruction, so adjust location to + // return to by 1 instruction (2 bytes), then exit function + "_semihost_return: \n" + "ADDS R1,#2 \n" + "STR R1,[R0,#24] \n" + // Set a return value from semihosting operation. + // 32 is slightly arbitrary, but appears to allow most + // C Library IO functions sitting on top of semihosting to + // continue to operate to some degree + "MOVS R1,#32 \n" + "STR R1,[ R0,#0 ] \n" // R0 is at location 0 on stack + // Return from hard fault handler to application + "BX LR \n" + ".syntax divided\n") ; +} + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/startup_lpc51u68.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/startup_lpc51u68.c new file mode 100644 index 000000000..8af5b4aa8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/GCC_specific/startup_lpc51u68.c @@ -0,0 +1,510 @@ +//***************************************************************************** +// LPC51U68 startup code for use with MCUXpresso IDE +// +// Version : 020818 +//***************************************************************************** +// +// Copyright 2016-2018 NXP +// +// SPDX-License-Identifier: BSD-3-Clause +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC push_options +#pragma GCC optimize ("Og") +#endif // (DEBUG) + +#if defined (__cplusplus) +#ifdef __REDLIB__ +#error Redlib does not support C++ +#else +//***************************************************************************** +// +// The entry point for the C++ library startup +// +//***************************************************************************** +extern "C" { + extern void __libc_init_array(void); +} +#endif +#endif + +#define WEAK __attribute__ ((weak)) +#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) +#define ALIAS(f) __attribute__ ((weak, alias (#f))) + +//***************************************************************************** +#if defined (__cplusplus) +extern "C" { +#endif + +//***************************************************************************** +// Variable to store CRP value in. Will be placed automatically +// by the linker when "Enable Code Read Protect" selected. +// See crp.h header for more information +//***************************************************************************** +//***************************************************************************** +// Declaration of external SystemInit function +//***************************************************************************** +#if defined (__USE_CMSIS) +extern void SystemInit(void); +#endif // (__USE_CMSIS) + +//***************************************************************************** +// Forward declaration of the core exception handlers. +// When the application defines a handler (with the same name), this will +// automatically take precedence over these weak definitions. +// If your application is a C++ one, then any interrupt handlers defined +// in C++ files within in your main application will need to have C linkage +// rather than C++ linkage. To do this, make sure that you are using extern "C" +// { .... } around the interrupt handler within your main application code. +//***************************************************************************** + void ResetISR(void); +WEAK void NMI_Handler(void); +WEAK void HardFault_Handler(void); +WEAK void SVC_Handler(void); +WEAK void PendSV_Handler(void); +WEAK void SysTick_Handler(void); +WEAK void IntDefaultHandler(void); + +//***************************************************************************** +// Forward declaration of the application IRQ handlers. When the application +// defines a handler (with the same name), this will automatically take +// precedence over weak definitions below +//***************************************************************************** +WEAK void WDT_BOD_IRQHandler(void); +WEAK void DMA0_IRQHandler(void); +WEAK void GINT0_IRQHandler(void); +WEAK void GINT1_IRQHandler(void); +WEAK void PIN_INT0_IRQHandler(void); +WEAK void PIN_INT1_IRQHandler(void); +WEAK void PIN_INT2_IRQHandler(void); +WEAK void PIN_INT3_IRQHandler(void); +WEAK void UTICK0_IRQHandler(void); +WEAK void MRT0_IRQHandler(void); +WEAK void CTIMER0_IRQHandler(void); +WEAK void CTIMER1_IRQHandler(void); +WEAK void SCT0_IRQHandler(void); +WEAK void CTIMER3_IRQHandler(void); +WEAK void FLEXCOMM0_IRQHandler(void); +WEAK void FLEXCOMM1_IRQHandler(void); +WEAK void FLEXCOMM2_IRQHandler(void); +WEAK void FLEXCOMM3_IRQHandler(void); +WEAK void FLEXCOMM4_IRQHandler(void); +WEAK void FLEXCOMM5_IRQHandler(void); +WEAK void FLEXCOMM6_IRQHandler(void); +WEAK void FLEXCOMM7_IRQHandler(void); +WEAK void ADC0_SEQA_IRQHandler(void); +WEAK void ADC0_SEQB_IRQHandler(void); +WEAK void ADC0_THCMP_IRQHandler(void); +WEAK void Reserved41_IRQHandler(void); +WEAK void Reserved42_IRQHandler(void); +WEAK void USB0_NEEDCLK_IRQHandler(void); +WEAK void USB0_IRQHandler(void); +WEAK void RTC_IRQHandler(void); + +//***************************************************************************** +// Forward declaration of the driver IRQ handlers. These are aliased +// to the IntDefaultHandler, which is a 'forever' loop. When the driver +// defines a handler (with the same name), this will automatically take +// precedence over these weak definitions +//***************************************************************************** +void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC0_SEQA_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC0_SEQB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void ADC0_THCMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved41_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void Reserved42_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); + +//***************************************************************************** +// The entry point for the application. +// __main() is the entry point for Redlib based applications +// main() is the entry point for Newlib based applications +//***************************************************************************** +#if defined (__REDLIB__) +extern void __main(void); +#endif +extern int main(void); + +//***************************************************************************** +// External declaration for the pointer to the stack top from the Linker Script +//***************************************************************************** +extern void _vStackTop(void); +//***************************************************************************** +// External declaration for LPC MCU vector table checksum from Linker Script +//***************************************************************************** +WEAK extern void __valid_user_code_checksum(); + +//***************************************************************************** +//***************************************************************************** +#if defined (__cplusplus) +} // extern "C" +#endif +//***************************************************************************** +// The vector table. +// This relies on the linker script to place at correct location in memory. +//***************************************************************************** +extern void (* const g_pfnVectors[])(void); +extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); + +__attribute__ ((used, section(".isr_vector"))) +void (* const g_pfnVectors[])(void) = { + // Core Level - CM0P + &_vStackTop, // The initial stack pointer + ResetISR, // The reset handler + NMI_Handler, // The NMI handler + HardFault_Handler, // The hard fault handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + __valid_user_code_checksum, // LPC MCU checksum + 0, // ECRP + 0, // Reserved + 0, // Reserved + SVC_Handler, // SVCall handler + 0, // Reserved + 0, // Reserved + PendSV_Handler, // The PendSV handler + SysTick_Handler, // The SysTick handler + + // Chip Level - LPC51U68 + WDT_BOD_IRQHandler, // 16: Windowed watchdog timer, Brownout detect + DMA0_IRQHandler, // 17: DMA controller + GINT0_IRQHandler, // 18: GPIO group 0 + GINT1_IRQHandler, // 19: GPIO group 1 + PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0 + PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1 + PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2 + PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3 + UTICK0_IRQHandler, // 24: Micro-tick Timer + MRT0_IRQHandler, // 25: Multi-rate timer + CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0 + CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1 + SCT0_IRQHandler, // 28: SCTimer/PWM + CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3 + FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART, SPI, I2C) + FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART, SPI, I2C) + FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART, SPI, I2C) + FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART, SPI, I2C) + FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART, SPI, I2C) + FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART, SPI, I2C) + FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S) + FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S) + ADC0_SEQA_IRQHandler, // 38: ADC0 sequence A completion. + ADC0_SEQB_IRQHandler, // 39: ADC0 sequence B completion. + ADC0_THCMP_IRQHandler, // 40: ADC0 threshold compare and error. + Reserved41_IRQHandler, // 41: Reserved interrupt + Reserved42_IRQHandler, // 42: Reserved interrupt + USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt + USB0_IRQHandler, // 44: USB device + RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts +}; /* End of g_pfnVectors */ + +//***************************************************************************** +// Functions to carry out the initialization of RW and BSS data sections. These +// are written as separate functions rather than being inlined within the +// ResetISR() function in order to cope with MCUs with multiple banks of +// memory. +//***************************************************************************** +__attribute__ ((section(".after_vectors.init_data"))) +void data_init(unsigned int romstart, unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int *pulSrc = (unsigned int*) romstart; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = *pulSrc++; +} + +__attribute__ ((section(".after_vectors.init_bss"))) +void bss_init(unsigned int start, unsigned int len) { + unsigned int *pulDest = (unsigned int*) start; + unsigned int loop; + for (loop = 0; loop < len; loop = loop + 4) + *pulDest++ = 0; +} + +//***************************************************************************** +// The following symbols are constructs generated by the linker, indicating +// the location of various points in the "Global Section Table". This table is +// created by the linker via the Code Red managed linker script mechanism. It +// contains the load address, execution address and length of each RW data +// section and the execution and length of each BSS (zero initialized) section. +//***************************************************************************** +extern unsigned int __data_section_table; +extern unsigned int __data_section_table_end; +extern unsigned int __bss_section_table; +extern unsigned int __bss_section_table_end; + +//***************************************************************************** +// Reset entry point for your code. +// Sets up a simple runtime environment and initializes the C/C++ +// library. +//***************************************************************************** +__attribute__ ((section(".after_vectors.reset"))) +void ResetISR(void) { + + // Disable interrupts + __asm volatile ("cpsid i"); + + // Enable SRAM clock used by Stack + __asm volatile ("LDR R0, =0x40000220\n\t" + "MOV R1, #56\n\t" + "STR R1, [R0]"); + +#if defined (__USE_CMSIS) +// If __USE_CMSIS defined, then call CMSIS SystemInit code + SystemInit(); + +#endif // (__USE_CMSIS) + + // + // Copy the data sections from flash to SRAM. + // + unsigned int LoadAddr, ExeAddr, SectionLen; + unsigned int *SectionTableAddr; + + // Load base address of Global Section Table + SectionTableAddr = &__data_section_table; + + // Copy the data sections from flash to SRAM. + while (SectionTableAddr < &__data_section_table_end) { + LoadAddr = *SectionTableAddr++; + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + data_init(LoadAddr, ExeAddr, SectionLen); + } + + // At this point, SectionTableAddr = &__bss_section_table; + // Zero fill the bss segment + while (SectionTableAddr < &__bss_section_table_end) { + ExeAddr = *SectionTableAddr++; + SectionLen = *SectionTableAddr++; + bss_init(ExeAddr, SectionLen); + } + +#if !defined (__USE_CMSIS) +// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code +// will setup the VTOR register + + // Check to see if we are running the code from a non-zero + // address (eg RAM, external flash), in which case we need + // to modify the VTOR register to tell the CPU that the + // vector table is located at a non-0x0 address. + unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; + if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { + *pSCB_VTOR = (unsigned int)g_pfnVectors; + } +#endif // (__USE_CMSIS) + +#if defined (__cplusplus) + // + // Call C++ library initialisation + // + __libc_init_array(); +#endif + + // Reenable interrupts + __asm volatile ("cpsie i"); + +#if defined (__REDLIB__) + // Call the Redlib library, which in turn calls main() + __main(); +#else + main(); +#endif + + // + // main() shouldn't return, but if it does, we'll just enter an infinite loop + // + while (1) { + ; + } +} + +//***************************************************************************** +// Default core exception handlers. Override the ones here by defining your own +// handler routines in your application code. +//***************************************************************************** +WEAK_AV void NMI_Handler(void) +{ while(1) {} +} + +WEAK_AV void HardFault_Handler(void) +{ while(1) {} +} + +WEAK_AV void SVC_Handler(void) +{ while(1) {} +} + +WEAK_AV void PendSV_Handler(void) +{ while(1) {} +} + +WEAK_AV void SysTick_Handler(void) +{ while(1) {} +} + +//***************************************************************************** +// Processor ends up here if an unexpected interrupt occurs or a specific +// handler is not present in the application code. +//***************************************************************************** +WEAK_AV void IntDefaultHandler(void) +{ while(1) {} +} + +//***************************************************************************** +// Default application exception handlers. Override the ones here by defining +// your own handler routines in your application code. These routines call +// driver exception handlers or IntDefaultHandler() if no driver exception +// handler is included. +//***************************************************************************** +WEAK_AV void WDT_BOD_IRQHandler(void) +{ WDT_BOD_DriverIRQHandler(); +} + +WEAK_AV void DMA0_IRQHandler(void) +{ DMA0_DriverIRQHandler(); +} + +WEAK_AV void GINT0_IRQHandler(void) +{ GINT0_DriverIRQHandler(); +} + +WEAK_AV void GINT1_IRQHandler(void) +{ GINT1_DriverIRQHandler(); +} + +WEAK_AV void PIN_INT0_IRQHandler(void) +{ PIN_INT0_DriverIRQHandler(); +} + +WEAK_AV void PIN_INT1_IRQHandler(void) +{ PIN_INT1_DriverIRQHandler(); +} + +WEAK_AV void PIN_INT2_IRQHandler(void) +{ PIN_INT2_DriverIRQHandler(); +} + +WEAK_AV void PIN_INT3_IRQHandler(void) +{ PIN_INT3_DriverIRQHandler(); +} + +WEAK_AV void UTICK0_IRQHandler(void) +{ UTICK0_DriverIRQHandler(); +} + +WEAK_AV void MRT0_IRQHandler(void) +{ MRT0_DriverIRQHandler(); +} + +WEAK_AV void CTIMER0_IRQHandler(void) +{ CTIMER0_DriverIRQHandler(); +} + +WEAK_AV void CTIMER1_IRQHandler(void) +{ CTIMER1_DriverIRQHandler(); +} + +WEAK_AV void SCT0_IRQHandler(void) +{ SCT0_DriverIRQHandler(); +} + +WEAK_AV void CTIMER3_IRQHandler(void) +{ CTIMER3_DriverIRQHandler(); +} + +WEAK_AV void FLEXCOMM0_IRQHandler(void) +{ FLEXCOMM0_DriverIRQHandler(); +} + +WEAK_AV void FLEXCOMM1_IRQHandler(void) +{ FLEXCOMM1_DriverIRQHandler(); +} + +WEAK_AV void FLEXCOMM2_IRQHandler(void) +{ FLEXCOMM2_DriverIRQHandler(); +} + +WEAK_AV void FLEXCOMM3_IRQHandler(void) +{ FLEXCOMM3_DriverIRQHandler(); +} + +WEAK_AV void FLEXCOMM4_IRQHandler(void) +{ FLEXCOMM4_DriverIRQHandler(); +} + +WEAK_AV void FLEXCOMM5_IRQHandler(void) +{ FLEXCOMM5_DriverIRQHandler(); +} + +WEAK_AV void FLEXCOMM6_IRQHandler(void) +{ FLEXCOMM6_DriverIRQHandler(); +} + +WEAK_AV void FLEXCOMM7_IRQHandler(void) +{ FLEXCOMM7_DriverIRQHandler(); +} + +WEAK_AV void ADC0_SEQA_IRQHandler(void) +{ ADC0_SEQA_DriverIRQHandler(); +} + +WEAK_AV void ADC0_SEQB_IRQHandler(void) +{ ADC0_SEQB_DriverIRQHandler(); +} + +WEAK_AV void ADC0_THCMP_IRQHandler(void) +{ ADC0_THCMP_DriverIRQHandler(); +} + +WEAK_AV void Reserved41_IRQHandler(void) +{ Reserved41_DriverIRQHandler(); +} + +WEAK_AV void Reserved42_IRQHandler(void) +{ Reserved42_DriverIRQHandler(); +} + +WEAK_AV void USB0_NEEDCLK_IRQHandler(void) +{ USB0_NEEDCLK_DriverIRQHandler(); +} + +WEAK_AV void USB0_IRQHandler(void) +{ USB0_DriverIRQHandler(); +} + +WEAK_AV void RTC_IRQHandler(void) +{ RTC_DriverIRQHandler(); +} + +//***************************************************************************** + +#if defined (DEBUG) +#pragma GCC pop_options +#endif // (DEBUG) diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/LPC51U68_256.FLM b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/LPC51U68_256.FLM new file mode 100644 index 000000000..517f0be2e Binary files /dev/null and b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/LPC51U68_256.FLM differ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/LPC51U68_flash.icf b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/LPC51U68_flash.icf new file mode 100644 index 000000000..734015f20 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/LPC51U68_flash.icf @@ -0,0 +1,92 @@ +/* +** ################################################################### +** Processors: LPC51U68JBD48 +** LPC51U68JBD64 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 +** Version: rev. 1.0, 2017-12-15 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0400; +} + +define symbol m_interrupts_start = 0x00000000; +define symbol m_interrupts_end = 0x000000DF; + +define symbol m_text_start = 0x000000E0; +define symbol m_text_end = 0x0003FFFF; + +define symbol m_sramx_start = 0x04000000; +define symbol m_sramx_end = 0x04007FFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF - __size_cstack__ - 0x20; + +define symbol m_stack_start = 0x20010000 - __size_cstack__ - 0x20; +define symbol m_stack_end = 0x2000FFFF; + +define symbol __crp_start__ = 0x000002FC; +define symbol __crp_end__ = 0x000002FF; + +define symbol __ram_iap_start__ = 0x2000FFE0; +define symbol __ram_iap_end__ = 0x2000FFFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end] + - mem:[from __crp_start__ to __crp_end__]; +define region DATA_region = mem:[from m_sramx_start to m_sramx_end] + | mem:[from m_data_start to m_data_end]; +define region CSTACK_region = mem:[from m_stack_start to m_stack_end] + - mem:[from __ram_iap_start__ to __ram_iap_end__]; +define region CRP_region = mem:[from __crp_start__ to __crp_end__]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; +place in CRP_region { section .crp }; diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/LPC51U68_ram.icf b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/LPC51U68_ram.icf new file mode 100644 index 000000000..26f773354 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/LPC51U68_ram.icf @@ -0,0 +1,78 @@ +/* +** ################################################################### +** Processors: LPC51U68JBD48 +** LPC51U68JBD64 +** +** Compiler: IAR ANSI C/C++ Compiler for ARM +** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 +** Version: rev. 1.0, 2017-12-15 +** Build: b180801 +** +** Abstract: +** Linker file for the IAR ANSI C/C++ Compiler for ARM +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Stack and Heap Sizes */ +if (isdefinedsymbol(__stack_size__)) { + define symbol __size_cstack__ = __stack_size__; +} else { + define symbol __size_cstack__ = 0x0400; +} + +if (isdefinedsymbol(__heap_size__)) { + define symbol __size_heap__ = __heap_size__; +} else { + define symbol __size_heap__ = 0x0800; +} + +define symbol m_interrupts_start = 0x04000000; +define symbol m_interrupts_end = 0x040000DF; + +define symbol m_text_start = 0x040000E0; +define symbol m_text_end = 0x04007FFF; + +define symbol m_data_start = 0x20000000; +define symbol m_data_end = 0x2000FFFF - __size_cstack__; + +define symbol m_stack_start = 0x20010000 - __size_cstack__; +define symbol m_stack_end = 0x2000FFFF; + +define memory mem with size = 4G; + +define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] + | mem:[from m_text_start to m_text_end]; +define region DATA_region = mem:[from m_data_start to m_data_end]; +define region CSTACK_region = mem:[from m_stack_start to m_stack_end]; + +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block RW { readwrite }; +define block ZI { zi }; + +initialize by copy { readwrite, section .textrw }; + +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + /* Required in a multi-threaded application */ + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +do not initialize { section .noinit }; + +place at address mem: m_interrupts_start { readonly section .intvec }; +place in TEXT_region { readonly }; +place in DATA_region { block RW }; +place in DATA_region { block ZI }; +place in DATA_region { last block HEAP }; +place in CSTACK_region { block CSTACK }; diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/RegTest_IAR.s b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/RegTest_IAR.s new file mode 100644 index 000000000..54fc1a235 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/RegTest_IAR.s @@ -0,0 +1,207 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* + * "Reg test" tasks - These fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ + + RSEG CODE:CODE(2) + thumb + + + EXTERN ulRegTest1LoopCounter + EXTERN ulRegTest2LoopCounter + + PUBLIC vRegTest1Task + PUBLIC vRegTest2Task + +/*-----------------------------------------------------------*/ +vRegTest1Task + + /* Fill the core registers with known values. This is only done once. */ + movs r1, #101 + movs r2, #102 + movs r3, #103 + movs r4, #104 + movs r5, #105 + movs r6, #106 + movs r7, #107 + movs r0, #108 + mov r8, r0 + movs r0, #109 + mov r9, r0 + movs r0, #110 + mov r10, r0 + movs r0, #111 + mov r11, r0 + movs r0, #112 + mov r12, r0 + movs r0, #100 + +reg1_loop + /* Repeatedly check that each register still contains the value written to + it when the task started. */ + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + movs r0, #108 + cmp r8, r0 + bne reg1_error_loop + movs r0, #109 + cmp r9, r0 + bne reg1_error_loop + movs r0, #110 + cmp r10, r0 + bne reg1_error_loop + movs r0, #111 + cmp r11, r0 + bne reg1_error_loop + movs r0, #112 + cmp r12, r0 + bne reg1_error_loop + + /* Everything passed, increment the loop counter. */ + push { r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /* NVIC_INT_CTRL */ + lsls r0 ,r0, #28 /* Shift to PendSV bit */ + str r0, [r1] + dsb + pop { r1 } + + /* Start again. */ + movs r0, #100 + b reg1_loop + +reg1_error_loop + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + nop + + + +vRegTest2Task + + /* Fill the core registers with known values. This is only done once. */ + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + movs r0, #8 + mov r8, r0 + movs r0, #9 + mov r9, r0 + movs r0, #10 + mov r10, r0 + movs r0, #11 + mov r11, r0 + movs r0, #12 + mov r12, r0 + movs r0, #10 + +reg2_loop + /* Repeatedly check that each register still contains the value written to + it when the task started. */ + cmp r0, #10 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + movs r0, #8 + cmp r8, r0 + bne reg2_error_loop + movs r0, #9 + cmp r9, r0 + bne reg2_error_loop + movs r0, #10 + cmp r10, r0 + bne reg2_error_loop + movs r0, #11 + cmp r11, r0 + bne reg2_error_loop + movs r0, #12 + cmp r12, r0 + bne reg2_error_loop + + /* Everything passed, increment the loop counter. */ + push { r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r1 } + + /* Start again. */ + movs r0, #10 + b reg2_loop + +reg2_error_loop + ;/* If this line is hit then there was an error in a core register value. + ;The loop ensures the loop counter stops incrementing. */ + b reg2_error_loop + nop + + END diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/compiler_attributes.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/compiler_attributes.h new file mode 100644 index 000000000..0160d96c4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/compiler_attributes.h @@ -0,0 +1,29 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Placing variable at specified address. */ +#define COMPILER_ATTRIBUTE_PLACE_IN_2ND_MEMORY_BANK @ 0x20000000 diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/startup_LPC51U68.s b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/startup_LPC51U68.s new file mode 100644 index 000000000..a6c41f02c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/IAR_specific/startup_LPC51U68.s @@ -0,0 +1,385 @@ +;/***************************************************************************** +; * @file: startup_LPC51U68.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File +; * LPC51U68 +; * @version: 1.0 +; * @date: 2017-12-15 +; *---------------------------------------------------------------------------- +; * +; Copyright 1997-2016 Freescale Semiconductor, Inc. +; Copyright 2016-2018 NXP +; +; SPDX-License-Identifier: BSD-3-Clause +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ; DMA controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) + DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. + DCD Reserved41_IRQHandler ; Reserved interrupt + DCD Reserved42_IRQHandler ; Reserved interrupt + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ; Reserved interrupt + DCD Reserved47_IRQHandler ; Reserved interrupt +__Vectors_End + +; Code Read Protection Level (CRP) +; <0xFFFFFFFF=> Disabled +; <0x4E697370=> NO_ISP +; <0x12345678=> CRP1 +; <0x87654321=> CRP2 +; <0x43218765=> CRP3 + +#if !defined NO_CRP + SECTION .crp:CODE +__CRP + DCD 0xFFFFFFFF +__CRP_End +#endif + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR r0, =SystemInit + BLX r0 + LDR r0, =__iar_program_start + BX r0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + PUBWEAK ADC0_SEQA_IRQHandler + PUBWEAK ADC0_SEQA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQA_IRQHandler + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + PUBWEAK ADC0_SEQB_IRQHandler + PUBWEAK ADC0_SEQB_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQB_IRQHandler + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + PUBWEAK ADC0_THCMP_IRQHandler + PUBWEAK ADC0_THCMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_THCMP_IRQHandler + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + PUBWEAK Reserved41_IRQHandler + PUBWEAK Reserved41_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved41_IRQHandler + LDR R0, =Reserved41_DriverIRQHandler + BX R0 + PUBWEAK Reserved42_IRQHandler + PUBWEAK Reserved42_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved42_IRQHandler + LDR R0, =Reserved42_DriverIRQHandler + BX R0 + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + PUBWEAK Reserved46_IRQHandler + PUBWEAK Reserved46_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved46_IRQHandler + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + PUBWEAK Reserved47_IRQHandler + PUBWEAK Reserved47_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved47_IRQHandler + LDR R0, =Reserved47_DriverIRQHandler + BX R0 +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +Reserved41_DriverIRQHandler +Reserved42_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +Reserved47_DriverIRQHandler +DefaultISR + B . + + END diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/LPC51U68_256.FLM b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/LPC51U68_256.FLM new file mode 100644 index 000000000..517f0be2e Binary files /dev/null and b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/LPC51U68_256.FLM differ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/LPC51U68_flash.scf b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/LPC51U68_flash.scf new file mode 100644 index 000000000..9dde63b08 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/LPC51U68_flash.scf @@ -0,0 +1,66 @@ +#! armcc -E +/* +** ################################################################### +** Processors: LPC51U68JBD48 +** LPC51U68JBD64 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 +** Version: rev. 1.0, 2017-12-15 +** Build: b180801 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_text_start 0x00000000 +#define m_text_size 0x00040000 + +#define m_sramx_start 0x04000000 +#define m_sramx_size 0x00008000 + +#define m_data_start 0x20000000 +#define m_data_size 0x00010000 + +LR_m_text m_text_start m_text_size { ; load region size_region + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_sramx_start m_sramx_size { ; RW data + .ANY (+RW +ZI) + } + RW_m_data_2 m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP ((ImageLimit(RW_m_data_2) == m_data_start) ? m_data_start : +0) EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/LPC51U68_ram.scf b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/LPC51U68_ram.scf new file mode 100644 index 000000000..91788b9f1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/LPC51U68_ram.scf @@ -0,0 +1,60 @@ +#! armcc -E +/* +** ################################################################### +** Processors: LPC51U68JBD48 +** LPC51U68JBD64 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 +** Version: rev. 1.0, 2017-12-15 +** Build: b180801 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** ################################################################### +*/ + + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +#define m_text_start 0x04000000 +#define m_text_size 0x00008000 + +#define m_data_start 0x20000000 +#define m_data_size 0x00010000 + +LR_m_text m_text_start m_text_size { ; load region size_region + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address + * (RESET,+FIRST) + * (InRoot$$Sections) + .ANY (+RO) + } + + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up + } + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down + } +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/RegTest_Keil.s b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/RegTest_Keil.s new file mode 100644 index 000000000..0374936bb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/RegTest_Keil.s @@ -0,0 +1,212 @@ +;/* +; * FreeRTOS Kernel V10.2.1 +; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. +; * +; * Permission is hereby granted, free of charge, to any person obtaining a copy of +; * this software and associated documentation files (the "Software"), to deal in +; * the Software without restriction, including without limitation the rights to +; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of +; * the Software, and to permit persons to whom the Software is furnished to do so, +; * subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all +; * copies or substantial portions of the Software. +; * +; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS +; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR +; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +; * +; * http://www.FreeRTOS.org +; * http://aws.amazon.com/freertos +; * +; * 1 tab == 4 spaces! +; */ + +;/* +; * "Reg test" tasks - These fill the registers with known values, then check +; * that each register maintains its expected value for the lifetime of the +; * task. Each task uses a different set of values. The reg test tasks execute +; * with a very low priority, so get preempted very frequently. A register +; * containing an unexpected value is indicative of an error in the context +; * switching mechanism. +; */ + + PRESERVE8 + THUMB + + + IMPORT ulRegTest1LoopCounter + IMPORT ulRegTest2LoopCounter + + EXPORT vRegTest1Task + EXPORT vRegTest2Task + + AREA |.text|, CODE, READONLY + +;/*-----------------------------------------------------------*/ +vRegTest1Task PROC + + ;/* Fill the core registers with known values. This is only done once. */ + movs r1, #101 + movs r2, #102 + movs r3, #103 + movs r4, #104 + movs r5, #105 + movs r6, #106 + movs r7, #107 + movs r0, #108 + mov r8, r0 + movs r0, #109 + mov r9, r0 + movs r0, #110 + mov r10, r0 + movs r0, #111 + mov r11, r0 + movs r0, #112 + mov r12, r0 + movs r0, #100 + +reg1_loop + ;/* Repeatedly check that each register still contains the value written to + ;it when the task started. */ + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + movs r0, #108 + cmp r8, r0 + bne reg1_error_loop + movs r0, #109 + cmp r9, r0 + bne reg1_error_loop + movs r0, #110 + cmp r10, r0 + bne reg1_error_loop + movs r0, #111 + cmp r11, r0 + bne reg1_error_loop + movs r0, #112 + cmp r12, r0 + bne reg1_error_loop + + ;/* Everything passed, increment the loop counter. */ + push { r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + ;/* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 ; NVIC_INT_CTRL + lsls r0 ,r0, #28 ; Shift to PendSV bit + str r0, [r1] + dsb + pop { r1 } + + ;/* Start again. */ + movs r0, #100 + + b reg1_loop + +reg1_error_loop + ;/* If this line is hit then there was an error in a core register value. + ;The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + nop + ENDP + + + +vRegTest2Task PROC + + ;/* Fill the core registers with known values. This is only done once. */ + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + movs r0, #8 + mov r8, r0 + movs r0, #9 + mov r9, r0 + movs r0, #10 + mov r10, r0 + movs r0, #11 + mov r11, r0 + movs r0, #12 + mov r12, r0 + movs r0, #10 + +reg2_loop + ;/* Repeatedly check that each register still contains the value written to + ;it when the task started. */ + cmp r0, #10 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + movs r0, #8 + cmp r8, r0 + bne reg2_error_loop + movs r0, #9 + cmp r9, r0 + bne reg2_error_loop + movs r0, #10 + cmp r10, r0 + bne reg2_error_loop + movs r0, #11 + cmp r11, r0 + bne reg2_error_loop + movs r0, #12 + cmp r12, r0 + bne reg2_error_loop + + ;/* Everything passed, increment the loop counter. */ + push { r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r1 } + + ;/* Start again. */ + movs r0, #10 + b reg2_loop + +reg2_error_loop + ;/* If this line is hit then there was an error in a core register value. + ;The loop ensures the loop counter stops incrementing. */ + b reg2_error_loop + nop + ENDP + + END diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/compiler_attributes.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/compiler_attributes.h new file mode 100644 index 000000000..5167987c9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/compiler_attributes.h @@ -0,0 +1,32 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Placing variable at specified address. +todo: +this is commented out intentionally, as it doesn't seem to work. +Clean up is needed*/ +#define COMPILER_ATTRIBUTE_PLACE_IN_2ND_MEMORY_BANK //__attribute__((section("m_data_start"))) diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/keil_lib_power.lib b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/keil_lib_power.lib new file mode 100644 index 000000000..2de428fa3 Binary files /dev/null and b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/keil_lib_power.lib differ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/startup_LPC51U68.s b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/startup_LPC51U68.s new file mode 100644 index 000000000..8ced8b869 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/Keil_specific/startup_LPC51U68.s @@ -0,0 +1,420 @@ +;/***************************************************************************** +; * @file: startup_LPC51U68.s +; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the +; * LPC51U68 +; * @version: 1.0 +; * @date: 2017-12-15 +; * +; * Copyright 1997-2016 Freescale Semiconductor, Inc. +; * Copyright 2016-2018 NXP +; * +; * SPDX-License-Identifier: BSD-3-Clause +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 ; Checksum of the first 7 words + DCD 0 + DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot + DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ; DMA controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) + DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. + DCD Reserved41_IRQHandler ; Reserved interrupt + DCD Reserved42_IRQHandler ; Reserved interrupt + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ; Reserved interrupt + DCD Reserved47_IRQHandler ; Reserved interrupt + + AREA |.text|, CODE, READONLY + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR r0, =SystemInit + BLX r0 + LDR r0, =__main + BX r0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler \ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +WDT_BOD_IRQHandler\ + PROC + EXPORT WDT_BOD_IRQHandler [WEAK] + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + ENDP + +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +GINT0_IRQHandler\ + PROC + EXPORT GINT0_IRQHandler [WEAK] + LDR R0, =GINT0_DriverIRQHandler + BX R0 + ENDP + +GINT1_IRQHandler\ + PROC + EXPORT GINT1_IRQHandler [WEAK] + LDR R0, =GINT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT0_IRQHandler\ + PROC + EXPORT PIN_INT0_IRQHandler [WEAK] + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + ENDP + +PIN_INT1_IRQHandler\ + PROC + EXPORT PIN_INT1_IRQHandler [WEAK] + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT2_IRQHandler\ + PROC + EXPORT PIN_INT2_IRQHandler [WEAK] + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + ENDP + +PIN_INT3_IRQHandler\ + PROC + EXPORT PIN_INT3_IRQHandler [WEAK] + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + ENDP + +UTICK0_IRQHandler\ + PROC + EXPORT UTICK0_IRQHandler [WEAK] + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + ENDP + +MRT0_IRQHandler\ + PROC + EXPORT MRT0_IRQHandler [WEAK] + LDR R0, =MRT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER0_IRQHandler\ + PROC + EXPORT CTIMER0_IRQHandler [WEAK] + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + ENDP + +CTIMER1_IRQHandler\ + PROC + EXPORT CTIMER1_IRQHandler [WEAK] + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + ENDP + +SCT0_IRQHandler\ + PROC + EXPORT SCT0_IRQHandler [WEAK] + LDR R0, =SCT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER3_IRQHandler\ + PROC + EXPORT CTIMER3_IRQHandler [WEAK] + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM0_IRQHandler\ + PROC + EXPORT FLEXCOMM0_IRQHandler [WEAK] + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM1_IRQHandler\ + PROC + EXPORT FLEXCOMM1_IRQHandler [WEAK] + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM2_IRQHandler\ + PROC + EXPORT FLEXCOMM2_IRQHandler [WEAK] + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM3_IRQHandler\ + PROC + EXPORT FLEXCOMM3_IRQHandler [WEAK] + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM4_IRQHandler\ + PROC + EXPORT FLEXCOMM4_IRQHandler [WEAK] + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM5_IRQHandler\ + PROC + EXPORT FLEXCOMM5_IRQHandler [WEAK] + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM6_IRQHandler\ + PROC + EXPORT FLEXCOMM6_IRQHandler [WEAK] + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM7_IRQHandler\ + PROC + EXPORT FLEXCOMM7_IRQHandler [WEAK] + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + ENDP + +ADC0_SEQA_IRQHandler\ + PROC + EXPORT ADC0_SEQA_IRQHandler [WEAK] + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + ENDP + +ADC0_SEQB_IRQHandler\ + PROC + EXPORT ADC0_SEQB_IRQHandler [WEAK] + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + ENDP + +ADC0_THCMP_IRQHandler\ + PROC + EXPORT ADC0_THCMP_IRQHandler [WEAK] + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + ENDP + +Reserved41_IRQHandler\ + PROC + EXPORT Reserved41_IRQHandler [WEAK] + LDR R0, =Reserved41_DriverIRQHandler + BX R0 + ENDP + +Reserved42_IRQHandler\ + PROC + EXPORT Reserved42_IRQHandler [WEAK] + LDR R0, =Reserved42_DriverIRQHandler + BX R0 + ENDP + +USB0_NEEDCLK_IRQHandler\ + PROC + EXPORT USB0_NEEDCLK_IRQHandler [WEAK] + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + ENDP + +USB0_IRQHandler\ + PROC + EXPORT USB0_IRQHandler [WEAK] + LDR R0, =USB0_DriverIRQHandler + BX R0 + ENDP + +RTC_IRQHandler\ + PROC + EXPORT RTC_IRQHandler [WEAK] + LDR R0, =RTC_DriverIRQHandler + BX R0 + ENDP + +Reserved46_IRQHandler\ + PROC + EXPORT Reserved46_IRQHandler [WEAK] + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + ENDP + +Reserved47_IRQHandler\ + PROC + EXPORT Reserved47_IRQHandler [WEAK] + LDR R0, =Reserved47_DriverIRQHandler + BX R0 + ENDP + +Default_Handler PROC + EXPORT WDT_BOD_DriverIRQHandler [WEAK] + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT GINT0_DriverIRQHandler [WEAK] + EXPORT GINT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT0_DriverIRQHandler [WEAK] + EXPORT PIN_INT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT2_DriverIRQHandler [WEAK] + EXPORT PIN_INT3_DriverIRQHandler [WEAK] + EXPORT UTICK0_DriverIRQHandler [WEAK] + EXPORT MRT0_DriverIRQHandler [WEAK] + EXPORT CTIMER0_DriverIRQHandler [WEAK] + EXPORT CTIMER1_DriverIRQHandler [WEAK] + EXPORT SCT0_DriverIRQHandler [WEAK] + EXPORT CTIMER3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] + EXPORT ADC0_SEQA_DriverIRQHandler [WEAK] + EXPORT ADC0_SEQB_DriverIRQHandler [WEAK] + EXPORT ADC0_THCMP_DriverIRQHandler [WEAK] + EXPORT Reserved41_DriverIRQHandler [WEAK] + EXPORT Reserved42_DriverIRQHandler [WEAK] + EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] + EXPORT USB0_DriverIRQHandler [WEAK] + EXPORT RTC_DriverIRQHandler [WEAK] + EXPORT Reserved46_DriverIRQHandler [WEAK] + EXPORT Reserved47_DriverIRQHandler [WEAK] + +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +Reserved41_DriverIRQHandler +Reserved42_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +Reserved47_DriverIRQHandler + + B . + + ENDP + + + ALIGN + + + END + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/FreeRTOSConfig.h new file mode 100644 index 000000000..e2551e7bc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/FreeRTOSConfig.h @@ -0,0 +1,112 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* Prevent C code being included by the IAR assembler. */ +#ifndef __IASMARM__ + #include + extern uint32_t SystemCoreClock; +#endif + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( SystemCoreClock ) +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMAX_TASK_NAME_LEN ( 5 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 + +/* Support various memory allocation. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Heap and stack. + * The bytes specified in configTOTAL_HEAP_SIZE need to fit in to + * the first memory bank, which is of size 64kB in total. This 64kB + * consists of FreeRTOS heap, linker heap and also .bss etc. Thus + * FreeRTOS heap cannot take the entire 64kB. */ +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 256 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 20 * 1024 ) ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( 2 ) +#define configTIMER_QUEUE_LENGTH 2 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) + +/* Enabling tickless. */ +#define configUSE_TICKLESS_IDLE 1 + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 1 + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names - or at least those used in the unmodified vector table. */ +#define vPortSVCHandler SVCall_Handler +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.c new file mode 100644 index 000000000..2bf143344 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.c @@ -0,0 +1,128 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Driver APIs.*/ +#include "fsl_ctimer.h" + +/* The priorities for the two timers. Note that a priority of 0 is the highest +possible on Cortex-M devices. */ +#define tmrMAX_PRIORITY ( 0UL ) +#define trmSECOND_HIGHEST_PRIORITY ( tmrMAX_PRIORITY + 1 ) + +void vInitialiseTimerForIntQueueTest( void ) +{ +ctimer_config_t xConfigTimer0, xConfigTimer1; +ctimer_match_config_t xConfigInterrupt = { 0 }; + + memset( &xConfigTimer0, 0x00, sizeof( xConfigTimer0 ) ); + memset( &xConfigTimer1, 0x00, sizeof( xConfigTimer1 ) ); + + /* Enable peripheral bus clock for CTIMER0 and CTIMER1. */ + CLOCK_EnableClock( kCLOCK_Ctimer0 ); + CLOCK_EnableClock( kCLOCK_Ctimer1 ); + + /* Interrupt settings for timers -- + A timer will generates an interrupt when the count matches the value specified. + Timer will reset itself and restart the count. The interrupt frequency is fairly + arbitrary, in a sense that all we need to make sure is IRQs are triggered so that + queues have items for tasks to process. */ + xConfigInterrupt.enableCounterReset = true; + xConfigInterrupt.enableCounterStop = false; + xConfigInterrupt.enableInterrupt = true; + xConfigInterrupt.matchValue = 0xFFFFF; + xConfigInterrupt.outControl = kCTIMER_Output_NoAction; + xConfigInterrupt.outPinInitState = true; + + /* Configuration settings for timers. */ + CTIMER_GetDefaultConfig( &xConfigTimer0 ); + xConfigTimer0.prescale = 1; + + CTIMER_GetDefaultConfig( &xConfigTimer1 ); + xConfigTimer1.prescale = 2; + + /* Initialize timers. */ + CTIMER_Init( CTIMER0, &xConfigTimer0 ); + CTIMER_SetupMatch( CTIMER0, kCTIMER_Match_0, &xConfigInterrupt ); + + CTIMER_Init( CTIMER1, &xConfigTimer1 ); + CTIMER_SetupMatch( CTIMER1, kCTIMER_Match_0, &xConfigInterrupt ); + + /* Don't generate interrupts until the scheduler has been started. + Interrupts will be automatically enabled when the first task starts + running. */ + taskDISABLE_INTERRUPTS(); + + /* Set the timer interrupts to be above the kernel. The interrupts are + assigned different priorities so they nest with each other. */ + NVIC_SetPriority( CTIMER0_IRQn, trmSECOND_HIGHEST_PRIORITY ); + NVIC_SetPriority( CTIMER1_IRQn, tmrMAX_PRIORITY ); + + /* Enable the timer interrupts. */ + NVIC_EnableIRQ( CTIMER0_IRQn ); + NVIC_EnableIRQ( CTIMER1_IRQn ); + + /* Start timers. */ + CTIMER_StartTimer( CTIMER0 ); + CTIMER_StartTimer( CTIMER1 ); +} +/*-----------------------------------------------------------*/ + +void CTIMER0_IRQHandler( void ) +{ +uint32_t ulInterruptStatus; + + /* Get Interrupt status flags */ + ulInterruptStatus = CTIMER_GetStatusFlags( CTIMER0 ); + + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags( CTIMER0, ulInterruptStatus ); + + portEND_SWITCHING_ISR( xFirstTimerHandler() ); +} +/*-----------------------------------------------------------*/ + +void CTIMER1_IRQHandler(void) +{ +uint32_t ulInterruptStatus; + + /* Get Interrupt status flags */ + ulInterruptStatus = CTIMER_GetStatusFlags( CTIMER1 ); + + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags( CTIMER1, ulInterruptStatus ); + + portEND_SWITCHING_ISR( xSecondTimerHandler() ); +} +/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.h new file mode 100644 index 000000000..d26057f9a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/IntQueueTimer.h @@ -0,0 +1,36 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main.c new file mode 100644 index 000000000..07dd94bc7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main.c @@ -0,0 +1,292 @@ +/* + * Copyright 2016-2019 NXP + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of NXP Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file main.c + * @brief Application entry point. + */ +#include + +/* Board specific includes. */ +#include "board.h" +#include "peripherals.h" +#include "pin_mux.h" +#include "clock_config.h" +#include "LPC51U68.h" +#include "fsl_debug_console.h" + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "task.h" + +#include "compiler_attributes.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to + * 0 -- to run the more comprehensive test and demo application, + * 1 -- to run the simple blinky demo. + */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 + +/*-----------------------------------------------------------*/ +typedef enum LED_STATE { + LED_RED_BLINK_ON = 1, + LED_RED_BLINK_OFF, + LED_GREEN_BLINK_ON, + LED_GREEN_BLINK_OFF, + LED_BLUE_BLINK_ON, + LED_BLUE_BLINK_OFF, +} E_LED_STATE; + +/* Static variable to keep track of LED color. + * red -> green -> blue -> red -> ... + * This variable is not intended for multi-threaded application. + */ +static E_LED_STATE eLedState = LED_RED_BLINK_ON; + +/* Show iteration number in UART. + * This variable is not intended for multi-threaded application. + */ +static int i = 0; + +/* Track how many times tick interrupt has occurred. */ +static unsigned int uTickInterruptCounter = 0; + +/* + * Perform any application specific hardware configuration. The clocks, + * memory, etc. are configured before main() is called. + */ +static void prvSetupHardware( void ); + +/** + * Heap_5 is being used because the RAM is not contiguous, therefore the heap + * needs to be initialized. See http://www.freertos.org/a00111.html + */ +static void prvInitializeHeap( void ); + +/* + * The hardware only has a single LED. Simply toggle it. + */ +void vMainToggleLED( void ); + +/* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. +main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ +void main_blinky( void ); +void main_full( void ); + +/* + * @brief Application entry point. + */ +int main(void) +{ + + /* Prepare the hardware to run this demo. */ + prvSetupHardware(); + + /* Initialize heap regions. */ + prvInitializeHeap(); + + /* Show something on UART. + Serial port setup as baudrate: 115200, data: 8-bit, parity: none, stop bits: 1, flow control: none. + sTerminal setup as receive: auto, transmit: CR+LF.*/ + PRINTF("FreeRTOS demo.\r\n"); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} + +/*-----------------------------------------------------------*/ +void vMainToggleLED( void ) +{ + switch (eLedState) + { + case LED_RED_BLINK_ON: + PRINTF("Iteration %d -- tick interrupt count %d.\r\n", i, uTickInterruptCounter); + i++; + + LED_RED_ON(); + eLedState = LED_RED_BLINK_OFF; + break; + case LED_RED_BLINK_OFF: + LED_RED_OFF(); + eLedState = LED_GREEN_BLINK_ON; + break; + case LED_GREEN_BLINK_ON: + LED_GREEN_ON(); + eLedState = LED_GREEN_BLINK_OFF; + break; + case LED_GREEN_BLINK_OFF: + LED_GREEN_OFF(); + eLedState = LED_BLUE_BLINK_ON; + break; + case LED_BLUE_BLINK_ON: + LED_BLUE_ON(); + eLedState = LED_BLUE_BLINK_OFF; + break; + case LED_BLUE_BLINK_OFF: + LED_BLUE_OFF(); + eLedState = LED_RED_BLINK_ON; + break; + default: + /* Unexpected state. Let's reset to default color. */ + eLedState = LED_RED_BLINK_ON; + } + + return; +} + +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Initialize board hardware. */ + BOARD_InitBootPins(); + BOARD_InitBootClocks(); + BOARD_InitBootPeripherals(); + + /* Enable clock for GPIO. */ + CLOCK_EnableClock(kCLOCK_Gpio0); + CLOCK_EnableClock(kCLOCK_Gpio1); + + /* Initialize FSL debug console. */ + BOARD_InitDebugConsole(); + + /* Initialize tri-color LED. */ + LED_RED_INIT(LOGIC_LED_OFF); + LED_GREEN_INIT(LOGIC_LED_OFF); + LED_BLUE_INIT(LOGIC_LED_OFF); + + return; +} + +/*-----------------------------------------------------------*/ + +static void prvInitializeHeap( void ) +{ + /* Place the first block of the heap memory in the first bank of RAM. */ + static uint8_t ucHeap1[ configTOTAL_HEAP_SIZE ]; + + /* Place the second block of the heap memory in the second bank of RAM. */ + static uint8_t ucHeap2[ 16 * 1024 ] COMPILER_ATTRIBUTE_PLACE_IN_2ND_MEMORY_BANK; + + /* Memory regions are defined in address order, and terminate with NULL. */ + static HeapRegion_t xHeapRegions[] = + { + { ( unsigned char * ) ucHeap1, sizeof( ucHeap1 ) }, + { ( unsigned char * ) ucHeap2, sizeof( ucHeap2 ) }, + { NULL, 0 } + }; + + vPortDefineHeapRegions( xHeapRegions ); + + return; +} + +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* vApplicationMallocFailedHook() will only be called if + configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook + function that will get called if a call to pvPortMalloc() fails. + pvPortMalloc() is called internally by the kernel whenever a task, queue, + timer or semaphore is created. It is also called by various parts of the + demo application. If heap_1.c or heap_2.c are used, then the size of the + heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in + FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used + to query the size of free heap space that remains (although it does not + provide information on how the remaining heap might be fragmented). */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} + +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + task. It is essential that code added to this hook function never attempts + to block in any way (for example, call xQueueReceive() with a block time + specified, or call vTaskDelay()). If the application makes use of the + vTaskDelete() API function (as this demo application does) then it is also + important that vApplicationIdleHook() is permitted to return to its calling + function, because it is the responsibility of the idle task to clean up + memory allocated by the kernel to any task that has since been deleted. */ +} + +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} + +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ +#if mainCHECK_INTERRUPT_STACK == 1 +extern unsigned long _pvHeapStart[]; + + /* This function will be called by each tick interrupt if + configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + added here, but the tick hook is called from an interrupt context, so + code must not attempt to block, and only the interrupt safe FreeRTOS API + functions can be used (those that end in FromISR()). */ + + /* Manually check the last few bytes of the interrupt stack to check they + have not been overwritten. Note - the task stacks are automatically + checked for overflow if configCHECK_FOR_STACK_OVERFLOW is set to 1 or 2 + in FreeRTOSConifg.h, but the interrupt stack is not. */ + configASSERT( memcmp( ( void * ) _pvHeapStart, ucExpectedInterruptStackValues, sizeof( ucExpectedInterruptStackValues ) ) == 0U ); +#endif /* mainCHECK_INTERRUPT_STACK */ + + uTickInterruptCounter++; +} + + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_blinky.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_blinky.c new file mode 100644 index 000000000..1fd2e2635 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_blinky.c @@ -0,0 +1,199 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles the LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" + +/* Hardware specific includes. */ + + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* Values passed to the two tasks just to check the task parameter +functionality. */ +#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) +#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) +/*-----------------------------------------------------------*/ + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/* + * Called by main() to create the simply blinky style application if + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + */ +void main_blinky( void ); + +/* + * The hardware only has a single LED. Simply toggle it. + */ +extern void vMainToggleLED( void ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was insufficient FreeRTOS heap memory available for the idle and/or + timer tasks to be created. See the memory management section on the + FreeRTOS web site for more details. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. + The block time is specified in ticks, the constant used converts ticks + to ms. While in the Blocked state this task will not consume any CPU + time. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; + + /* Check the task parameter is as expected. */ + configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == 100UL ) + { + vMainToggleLED(); + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_full.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_full.c new file mode 100644 index 000000000..286d1be6d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/app/main_full.c @@ -0,0 +1,283 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the comprehensive test and demo version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + ****************************************************************************** + * + * main_full() creates a set of standard demo tasks (including a set of tasks + * that test the interrupt nesting behaviour), some application specific tasks, + * and a timer. It then starts the scheduler. The web documentation provides + * more details of the standard demo application tasks, which provide no + * particular functionality, but do provide a good example of how to use the + * FreeRTOS API. + * + * The interrupt nesting test tasks require that two timers are configured to + * generate interrupts. The interrupt service routines are defined in + * IntQueueTimer.c, and can be used as examples for application writers. They + * do not, however, directly demonstrate the use of FreeRTOS safe API functions + * (those that end in "FromISR"). Therefore, a dummy interrupt implementation + * called Dummy_IRQHandler() is provided at the end of main.c. + * + * In addition to the standard demo tasks, the following tasks and timer are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + * + * "Check" software timer - The check timer period is initially set to three + * seconds. Its callback function checks that all the standard demo tasks, and + * the register check tasks, are not only still executing, but are executing + * without reporting any errors. If the check timer callback discovers that a + * task has either stalled, or reported an error, then it changes the period of + * the check timer from the initial three seconds, to just 200ms. The callback + * function also toggles the LED each time it is called. This provides a visual + * indication of the system status: If the LED toggles every three seconds, + * then no issues have been discovered. If the LED toggles every 200ms, then + * an issue has been discovered with at least one task. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "queue.h" +#include "timers.h" + +/* Common demo includes. */ +#include "blocktim.h" +#include "countsem.h" +#include "recmutex.h" +#include "IntQueue.h" + + +/* The period after which the check timer will expire provided no errors have +been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* Set mainNO_TASK_NO_CHECK to + * 0 -- to include all predefined test tasks and checks, + * 1 -- to exclude all predefined test tasks and checks. + * When set to 1 (with few tasks in system), user could observe how tickless + * idle could minimize tick interrupt. */ +#define mainNO_TASK_NO_CHECK ( 1 ) +/*-----------------------------------------------------------*/ + +/* + * Register check tasks, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly. + */ +extern void vRegTest1Task( void *pvParameters ); +extern void vRegTest2Task( void *pvParameters ); + +/* + * The hardware only has a single LED. Simply toggle it. + */ +extern void vMainToggleLED( void ); + +/* + * The check timer callback function, as described at the top of this file. + */ +static void prvCheckTimerCallback( TimerHandle_t xTimer ); + +/* + * Called by main() to create the comprehensive test/demo application if + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not set to 1. + */ +void main_full( void ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check software timer. If the variables keep +incrementing, then the register check tasks have not discovered any errors. If +a variable stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ +TimerHandle_t xCheckTimer = NULL; + +#if ( mainNO_TASK_NO_CHECK == 0 ) + /* The register test tasks are asm functions that don't use a stack. The + stack allocated just has to be large enough to hold the task context, and + for the additional required for the stack overflow checking to work (if + configured). */ + const size_t xRegTestStackSize = 25U; +#endif /* mainNO_TASK_NO_CHECK */ + +#if ( mainNO_TASK_NO_CHECK == 0 ) + /* Create the standard demo tasks, including the interrupt nesting test + tasks. */ + vStartInterruptQueueTasks(); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartRecursiveMutexTasks(); + + /* Create the register test tasks as described at the top of this file. + These are naked functions that don't use any stack. A stack still has + to be allocated to hold the task context. */ + xTaskCreate( vRegTest1Task, /* Function that implements the task. */ + "Reg1", /* Text name of the task. */ + xRegTestStackSize, /* Stack allocated to the task. */ + NULL, /* The task parameter is not used. */ + tskIDLE_PRIORITY, /* The priority to assign to the task. */ + NULL ); /* Don't receive a handle back, it is not needed. */ + + xTaskCreate( vRegTest2Task, /* Function that implements the task. */ + "Reg2", /* Text name of the task. */ + xRegTestStackSize, /* Stack allocated to the task. */ + NULL, /* The task parameter is not used. */ + tskIDLE_PRIORITY, /* The priority to assign to the task. */ + NULL ); /* Don't receive a handle back, it is not needed. */ +#endif /* mainNO_TASK_NO_CHECK */ + + /* Create the software timer that performs the 'check' functionality, + as described at the top of this file. */ + xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ + ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ + pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ + ( void * ) 0, /* The ID is not used, so can be set to anything. */ + prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ + ); + + /* If the software timer was created successfully, start it. It won't + actually start running until the scheduler starts. A block time of + zero is used in this call, although any value could be used as the block + time will be ignored because the scheduler has not started yet. */ + if( xCheckTimer != NULL ) + { + xTimerStart( xCheckTimer, mainDONT_BLOCK ); + } + + /* Start the kernel. From here on, only tasks and interrupts will run. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then there + was insufficient FreeRTOS heap memory available for the idle and/or timer + tasks to be created. See the memory management section on the FreeRTOS web + site, or the FreeRTOS tutorial books for more details. */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +/* See the description at the top of this file. */ +static void prvCheckTimerCallback( TimerHandle_t xTimer ) +{ +static long lChangedTimerPeriodAlready = pdFALSE; +unsigned long ulErrorFound = pdFALSE; + +#if ( mainNO_TASK_NO_CHECK == 0 ) + static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +#endif /* mainNO_TASK_NO_CHECK */ + +#if ( mainNO_TASK_NO_CHECK == 0 ) + + /* Check all the demo and test tasks to ensure that they are all still + running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 0UL ); + } + + if( xAreBlockTimeTestTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 1UL ); + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 2UL ); + } + + if( xAreRecursiveMutexTasksStillRunning() != pdPASS ) + { + ulErrorFound |= ( 0x01UL << 3UL ); + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= ( 0x01UL << 4UL ); + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= ( 0x01UL << 5UL ); + } + ulLastRegTest2Value = ulRegTest2LoopCounter; +#endif /* mainNO_TASK_NO_CHECK */ + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then + everything is ok. A faster toggle indicates an error. */ + vMainToggleLED(); + + /* Have any errors been latched in ulErrorFound? If so, shorten the + period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. + This will result in an increase in the rate at which mainCHECK_LED + toggles. */ + if( ulErrorFound != pdFALSE ) + { + if( lChangedTimerPeriodAlready == pdFALSE ) + { + lChangedTimerPeriodAlready = pdTRUE; + + /* This call to xTimerChangePeriod() uses a zero block time. + Functions called from inside of a timer callback function must + *never* attempt to block. */ + xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/board.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/board.c new file mode 100644 index 000000000..8806a3936 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/board.c @@ -0,0 +1,35 @@ +/* + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "fsl_common.h" +#include "clock_config.h" +#include "board.h" +#include "fsl_debug_console.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Clock rate on the CLKIN pin */ +const uint32_t ExtClockIn = BOARD_EXTCLKINRATE; + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +status_t BOARD_InitDebugConsole(void) +{ + status_t result; + /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ + CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH); + RESET_PeripheralReset(BOARD_DEBUG_UART_RST); + result = DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, + BOARD_DEBUG_UART_CLK_FREQ); + assert(kStatus_Success == result); + return result; +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/board.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/board.h new file mode 100644 index 000000000..a28ca84d1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/board.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_gpio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "LPCXPRESSO51U68" + +#define BOARD_EXTCLKINRATE (0) + +/*! @brief The UART to use for debug messages. */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0 +#define BOARD_DEBUG_UART_INSTANCE 0U +#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFreq(kCLOCK_Flexcomm0) +#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0 +#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn +#define BOARD_UART_IRQ FLEXCOMM0_IRQn +#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler + +#define BOARD_DEBUG_SPI_CLK_FREQ 12000000 + +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE 115200 +#endif /* BOARD_DEBUG_UART_BAUDRATE */ + +#ifndef BOARD_LED_RED_GPIO +#define BOARD_LED_RED_GPIO GPIO +#endif +#define BOARD_LED_RED_GPIO_PORT 0U +#ifndef BOARD_LED_RED_GPIO_PIN +#define BOARD_LED_RED_GPIO_PIN 29U +#endif +#ifndef BOARD_LED_GREEN_GPIO +#define BOARD_LED_GREEN_GPIO GPIO +#endif +#define BOARD_LED_GREEN_GPIO_PORT 1U +#ifndef BOARD_LED_GREEN_GPIO_PIN +#define BOARD_LED_GREEN_GPIO_PIN 10U +#endif +#ifndef BOARD_LED_BLUE_GPIO +#define BOARD_LED_BLUE_GPIO GPIO +#endif +#define BOARD_LED_BLUE_GPIO_PORT 1U +#ifndef BOARD_LED_BLUE_GPIO_PIN +#define BOARD_LED_BLUE_GPIO_PIN 9U +#endif + +#ifndef BOARD_SW1_GPIO +#define BOARD_SW1_GPIO GPIO +#endif +#define BOARD_SW1_GPIO_PORT 0U +#ifndef BOARD_SW1_GPIO_PIN +#define BOARD_SW1_GPIO_PIN 24U +#endif +#define BOARD_SW1_NAME "SW1" +#define BOARD_SW3_IRQ PIN_INT0_IRQn +#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler + +#ifndef BOARD_SW2_GPIO +#define BOARD_SW2_GPIO GPIO +#endif +#define BOARD_SW2_GPIO_PORT 0U +#ifndef BOARD_SW2_GPIO_PIN +#define BOARD_SW2_GPIO_PIN 31U +#endif +#define BOARD_SW2_NAME "SW2" +#define BOARD_SW3_IRQ PIN_INT0_IRQn +#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler + +#ifndef BOARD_SW3_GPIO +#define BOARD_SW3_GPIO GPIO +#endif +#define BOARD_SW3_GPIO_PORT 0U +#ifndef BOARD_SW3_GPIO_PIN +#define BOARD_SW3_GPIO_PIN 4U +#endif +#define BOARD_SW3_NAME "SW3" +#define BOARD_SW3_IRQ PIN_INT0_IRQn +#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler +#define BOARD_SW3_GPIO_PININT_INDEX 0 + +#define BOARD_ARDUINO_INT_IRQ (GINT0_IRQn) +#define BOARD_ARDUINO_I2C_IRQ (FLEXCOMM4_IRQn) +#define BOARD_ARDUINO_I2C_INDEX (4) +/* Board led color mapping */ +#define LOGIC_LED_ON 0U +#define LOGIC_LED_OFF 1U + +#define LED_RED_INIT(output) \ + GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_RED */ +#define LED_RED_ON() \ + GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ + 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */ +#define LED_RED_OFF() \ + GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ + 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */ +#define LED_RED_TOGGLE() \ + GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ + 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */ + +#define LED_GREEN_INIT(output) \ + GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_GREEN */ +#define LED_GREEN_ON() \ + GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ + 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */ +#define LED_GREEN_OFF() \ + GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ + 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */ +#define LED_GREEN_TOGGLE() \ + GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ + 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */ + +#define LED_BLUE_INIT(output) \ + GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_BLUE */ +#define LED_BLUE_ON() \ + GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ + 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */ +#define LED_BLUE_OFF() \ + GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ + 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */ +#define LED_BLUE_TOGGLE() \ + GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ + 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +status_t BOARD_InitDebugConsole(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/clock_config.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/clock_config.c new file mode 100644 index 000000000..82f4749e9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/clock_config.c @@ -0,0 +1,253 @@ +/* + * Copyright 2018 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Setup voltage for the fastest of the clock outputs + * + * 3. Set up wait states of the flash. + * + * 4. Set up all dividers. + * + * 5. Set up all selectors to provide selected clocks. + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v4.1 +processor: LPC51U68 +package_id: LPC51U68JBD64 +mcu_data: ksdk2_0 +processor_version: 3.0.1 +board: LPCXpresso51u68 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockRUN(); +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: PLL_clock.outFreq, value: 12 MHz} +- {id: SYSTICK_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 12 MHz} +settings: +- {id: SYSCON.M_MULT.scale, value: '0', locked: true} +- {id: SYSCON.N_DIV.scale, value: '3', locked: true} +- {id: SYSCON.PLL_BYPASS.sel, value: SYSCON.SYSPLLCLKSEL} +- {id: SYSCON.SYSPLLCLKSEL.sel, value: SYSCON.fro_12m} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockRUN configuration + ******************************************************************************/ +void BOARD_BootClockRUN(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without + accidentally being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Switch PLL clock source selector to FRO12M */ + const pll_setup_t pllSetup = {.syspllctrl = SYSCON_SYSPLLCTRL_UPLIMOFF_MASK | SYSCON_SYSPLLCTRL_BYPASS_MASK, + .syspllndec = SYSCON_SYSPLLNDEC_NDEC(1U), + .syspllpdec = SYSCON_SYSPLLPDEC_PDEC(2U), + .syspllssctrl = {0x0U, (SYSCON_SYSPLLSSCTRL1_MD(0U) | (uint32_t)(kSS_MF_512) | + (uint32_t)(kSS_MR_K0) | (uint32_t)(kSS_MC_NOC))}, + .pllRate = 12000000U, + .flags = PLL_SETUPFLAG_POWERUP}; + CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired values */ + + /* PLL in Fractional/Spread spectrum mode */ + /* SYSTICK is used for waiting for PLL stabilization */ + + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SysTick divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 3U, false); /*!< Set SysTick divider to value 3 */ + SysTick->LOAD = 27999UL; /*!< Set SysTick count value */ + SysTick->VAL = 0UL; /*!< Reset current count value */ + SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; /*!< Enable SYSTICK */ + while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != SysTick_CTRL_COUNTFLAG_Msk) + { + } /*!< Waiting for PLL stabilization */ + SysTick->CTRL = 0UL; /*!< Stop SYSTICK */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: SYSTICK_clock.outFreq, value: 12 MHz} +- {id: System_clock.outFreq, value: 12 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without + accidentally being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF48M ********************* + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF48M +outputs: +- {id: SYSTICK_clock.outFreq, value: 48 MHz} +- {id: System_clock.outFreq, value: 48 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF48M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without + accidentally being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: SYSTICK_clock.outFreq, value: 96 MHz} +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} +sources: +- {id: SYSCON.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without + accidentally being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/clock_config.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/clock_config.h new file mode 100644 index 000000000..e1a03275c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/clock_config.h @@ -0,0 +1,137 @@ +/* + * Copyright 2018 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockRUN *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockRUN configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockRUN configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockRUN(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF48M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/peripherals.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/peripherals.c new file mode 100644 index 000000000..27ee68aa3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/peripherals.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v1.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Included files + ******************************************************************************/ +#include "peripherals.h" + +/******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/peripherals.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/peripherals.h new file mode 100644 index 000000000..08ae55e42 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/peripherals.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ +/******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ + +#endif /* _PERIPHERALS_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/pin_mux.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/pin_mux.c new file mode 100644 index 000000000..adb4296e0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/pin_mux.c @@ -0,0 +1,535 @@ +/* + * Copyright 2018 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.1 +processor: LPC51U68 +package_id: LPC51U68JBD64 +mcu_data: ksdk2_0 +processor_version: 3.0.1 +board: LPCXpresso51u68 +pin_labels: +- {pin_num: '1', pin_signal: PIO0_23/FC1_RTS_SCL_SSEL1/CTIMER0_CAP0/UTICK_CAP1, label: 'J4[9]/JS3[1]/JS4[3]/U10[7]/U12[D6]/BRIDGE_SCL', identifier: BRIDGE_SCL;LINK2MCU_SCL} +- {pin_num: '2', pin_signal: PIO0_24/FC1_CTS_SDA_SSEL0/CTIMER0_CAP1/CTIMER0_MAT0, label: 'J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP', identifier: SW1;BRIDGE_SDA_WAKEUP;LINK2MCU_SDA} +- {pin_num: '13', pin_signal: PIO0_31/FC2_CTS_SDA_SSEL0/CTIMER0_CAP3/CTIMER0_MAT3/ADC0_2, label: 'J2[17]/J3[2]/P1[7]/U3[4]/SW2/P0_31-PDM0_CLK-ISP0_EN', identifier: SW2} +- {pin_num: '38', pin_signal: PIO0_4/FC0_SCK/FC3_SSEL2/CTIMER0_CAP2, label: 'J4[7]/U9[12]/SW3/BRIDGE_T_INTR-ISP1', identifier: SW3;BRIDGE_T_INTR} +- {pin_num: '29', pin_signal: PIO1_9/FC3_RXD_SDA_MOSI/CTIMER0_CAP2/USB0_UP_LED, label: 'J9[5]/D2[3]/P1_9-BLUE_LED', identifier: LED_BLUE} +- {pin_num: '30', pin_signal: PIO1_10/FC6_TXD_SCL_MISO_WS/SCT0_OUT4/FC1_SCK/USB0_FRAME, label: 'J9[8]/D2[4]/P1_10-SCT4-LED_GREEN', identifier: LED_GREEN} +- {pin_num: '11', pin_signal: PIO0_29/FC1_RXD_SDA_MOSI/SCT0_OUT2/CTIMER0_MAT3/CTIMER0_CAP1/CTIMER0_MAT1/ADC0_0, label: 'J2[5]/D2[1]/P0_29-CT32B0_MAT3-RED', identifier: LED_RED} +- {pin_num: '3', pin_signal: PIO0_25/FC4_RTS_SCL_SSEL1/FC6_CTS_SDA_SSEL0/CTIMER0_CAP2/CTIMER1_CAP1, label: 'J1[1]/JS4[1]/U10[7]/P0_25-FC4_SCLX', identifier: FC4_SCLX} +- {pin_num: '4', pin_signal: PIO0_26/FC4_CTS_SDA_SSEL0/CTIMER0_CAP3, label: 'J1[3]/JS5[1]/U10[5]/P0_26-FC4_SDAX', identifier: FC4_SDAX} +- {pin_num: '58', pin_signal: PIO0_18/FC5_TXD_SCL_MISO/SCT0_OUT0/CTIMER0_MAT0, label: 'J1[11]/U5[2]/P0_18-FC5_TXD_SCL_MISO', identifier: SPI_FLASH_MISO} +- {pin_num: '59', pin_signal: PIO0_19/FC5_SCK/SCT0_OUT1/CTIMER0_MAT1, label: 'J1[9]/J2[8]/U5[6]/P0_19-FC5_SCK-SPIFI_CSn', identifier: SPI_FLASH_SCK} +- {pin_num: '60', pin_signal: PIO0_20/FC5_RXD_SDA_MOSI/FC0_SCK/CTIMER3_CAP0, label: 'J1[13]/U5[5]/P0_20-FC5_RXD_SDA_MOSI', identifier: SPI_FLASH_MOSI} +- {pin_num: '16', pin_signal: PIO1_2/MCLK/FC7_SSEL3/SCT0_OUT5/FC5_SSEL3/FC4_RXD_SDA_MOSI/ADC0_5, label: 'J9[7]/JS8[1]/U5[1]/P1_2-FC5_SSEL3', identifier: FC5_SSEL3} +- {pin_num: '46', pin_signal: PIO0_11/FC3_SCK/FC6_RXD_SDA_MOSI_DATA, label: 'J4[4]/U9[13]/BRIDGE_T_SCK', identifier: BRIDGE_T_SCK} +- {pin_num: '47', pin_signal: PIO0_12/FC3_RXD_SDA_MOSI/FC6_TXD_SCL_MISO_WS, label: 'J4[2]/U9[11]/BRIDGE_T_MOSI', identifier: BRIDGE_T_MOSI} +- {pin_num: '48', pin_signal: PIO0_13/FC3_TXD_SCL_MISO/SCT0_OUT4, label: 'J4[3]/U15[4]/BRIDGE_T_MISO', identifier: BRIDGE_T_MISO} +- {pin_num: '63', pin_signal: PIO0_22/CLKIN/FC0_RXD_SDA_MOSI/CTIMER3_MAT3, label: 'J4[8]/P0_22-BRIDGE_GPIO', identifier: BRIDGE_GPIO} +- {pin_num: '31', pin_signal: PIO0_0/FC0_RXD_SDA_MOSI/FC3_CTS_SDA_SSEL0/CTIMER0_CAP0/SCT0_OUT3, label: 'U18[4]/TO_MUX_P0_0-ISP_RX', identifier: DEBUG_UART_RX} +- {pin_num: '5', pin_signal: USB0_DP, label: 'J5[3]/U7[2]/USB_DP', identifier: USB_DP} +- {pin_num: '6', pin_signal: USB0_DM, label: 'J5[2]/U7[3]/USB_DM', identifier: USB_DM} +- {pin_num: '32', pin_signal: PIO0_1/FC0_TXD_SCL_MISO/FC3_RTS_SCL_SSEL1/CTIMER0_CAP1/SCT0_OUT1, label: 'U6[4]/U22[3]/P0_1-ISP_TX', identifier: DEBUG_UART_TX} +- {pin_num: '53', pin_signal: PIO0_17/FC3_SSEL3/FC6_RTS_SCL_SSEL1/CTIMER3_MAT2/SWDIO, label: 'J2[6]/P1[2]/U2[5]/U14[4]/IF_TMS_SWDIO-SPIFI_IO0', identifier: DEBUG_SWD_SWDIO} +- {pin_num: '52', pin_signal: PIO0_16/FC3_SSEL2/FC6_CTS_SDA_SSEL0/CTIMER3_MAT1/SWCLK, label: 'J2[4]/JS28/U4[4]/TCK-SWDCLK_TRGT-SPIFI_IO1', identifier: DEBUG_SWD_SWDCLK} +- {pin_num: '50', pin_signal: PIO0_15/FC3_RTS_SCL_SSEL1/FC4_SCK, label: 'J2[10]/JS30/U4[12]/TDO-SWO_TRGT-SPIFI_IO2', identifier: DEBUG_SWD_SWO} +- {pin_num: '49', pin_signal: PIO0_14/FC3_CTS_SDA_SSEL0/SCT0_OUT5/FC1_SCK, label: 'J2[12]/J4[1]/U9[14]/BRIDGE_T_SSEL-SPIFI_IO3', identifier: BRIDGE_T_SSEL} +- {pin_num: '26', pin_signal: PIO1_6/FC7_SCK/CTIMER1_CAP2/CTIMER1_MAT2/USB0_VBUS/ADC0_9, label: 'J1[14]/J5[1]/JP10[2]/P1_6-FC7_SCK-USB_VBUS', identifier: USB_VBUS} +- {pin_num: '7', pin_signal: PIO1_16/CTIMER0_MAT0/CTIMER0_CAP0/FC7_RTS_SCL_SSEL1, label: 'J1[19]/P1_16-CT32B0_MAT0-GYRO_INT1'} +- {pin_num: '8', pin_signal: VDD8, label: VDD_LPC54u68_IC} +- {pin_num: '9', pin_signal: VSS9, label: GND} +- {pin_num: '10', pin_signal: PIO1_17/MCLK/UTICK_CAP3, label: 'J9[9]/P1_17-IR_LEARN_EN'} +- {pin_num: '12', pin_signal: PIO0_30/FC1_TXD_SCL_MISO/SCT0_OUT3/CTIMER0_MAT2/CTIMER0_CAP2/ADC0_1, label: 'J9[2]/P0_30-ADC1'} +- {pin_num: '14', pin_signal: PIO1_0/FC2_RTS_SCL_SSEL1/CTIMER3_MAT1/CTIMER0_CAP0/ADC0_3, label: 'J2[3]/P1_0-PDM0_DATA-CT32B3_MAT1'} +- {pin_num: '15', pin_signal: PIO1_1/SCT0_OUT4/FC5_SSEL2/FC4_TXD_SCL_MISO/ADC0_4, label: 'J1[15]/P1_1-FC5_SSEL2'} +- {pin_num: '17', pin_signal: PIO1_3/FC7_SSEL2/SCT0_OUT6/FC3_SCK/CTIMER0_CAP1/USB0_UP_LED/ADC0_6, label: 'J2[20]/P1_3-FC7_SSEL2-CT32B0_CAP1'} +- {pin_num: '18', pin_signal: PIO1_4/FC7_RTS_SCL_SSEL1/SCT0_OUT7/FC3_TXD_SCL_MISO/CTIMER0_MAT1/ADC0_7, label: 'J2[18]/J9[10]/P1_4-ADC7-PDM1_CLK-FC7_RTS-FC3_TXD'} +- {pin_num: '19', pin_signal: PIO1_5/FC7_CTS_SDA_SSEL0/CTIMER1_CAP0/CTIMER1_MAT3/USB0_FRAME/ADC0_8, label: 'J2[16]/J9[12]/P1_5-ADC8-PDM1_DAT-FC7_CTS'} +- {pin_num: '20', pin_signal: VSSA, label: GND} +- {pin_num: '21', pin_signal: VREFN, label: 'SJ1[2]/P4[3]/GND'} +- {pin_num: '22', pin_signal: VREFP, label: 'SJ2[2]/P4[1]/VDD_LPC541u68_IC'} +- {pin_num: '23', pin_signal: VDDA, label: VDD_LPC54u68_IC} +- {pin_num: '24', pin_signal: VDD24, label: VDD_LPC54u68_IC} +- {pin_num: '25', pin_signal: VSS25, label: GND} +- {pin_num: '27', pin_signal: PIO1_7/FC7_RXD_SDA_MOSI_DATA/CTIMER1_MAT2/CTIMER1_CAP2/ADC0_10, label: 'J1[10]/P1_7-FC7_RXD_SDA_MOSI_DATA'} +- {pin_num: '28', pin_signal: PIO1_8/FC7_TXD_SCL_MISO_WS/CTIMER1_MAT3/CTIMER1_CAP3/ADC0_11, label: 'J1[12]/J9[6]/P1_8-ADC11-FC7_TXD_SCL_MISO_FRAME'} +- {pin_num: '33', pin_signal: RTCXIN, label: 'JS18[2]/Y1/RTCXIN'} +- {pin_num: '34', pin_signal: VDD34, label: VDD_LPC54u68_IC} +- {pin_num: '35', pin_signal: RTCXOUT, label: JS17/Y1/RTCXOUT} +- {pin_num: '36', pin_signal: PIO0_2/FC0_CTS_SDA_SSEL0/FC2_SSEL3, label: 'J9[1]/P0_2-GPIO_SPI_CS'} +- {pin_num: '37', pin_signal: PIO0_3/FC0_RTS_SCL_SSEL1/FC2_SSEL2/CTIMER1_MAT3, label: 'J9[3]/P0_3-GPIO_SPI_CS'} +- {pin_num: '39', pin_signal: PIO0_5/FC6_RXD_SDA_MOSI_DATA/SCT0_OUT6/CTIMER0_MAT0, label: 'J1[20]/P0_5-FC6_RXD_SDA_MOSI_DATA'} +- {pin_num: '40', pin_signal: PIO0_6/FC6_TXD_SCL_MISO_WS/CTIMER0_MAT1/UTICK_CAP0, label: 'J1[18]/P0_6-FC6_TXD_SCL_MISO_FRAME'} +- {pin_num: '41', pin_signal: PIO0_7/FC6_SCK/SCT0_OUT0/CTIMER0_MAT2/CTIMER0_CAP2, label: 'J1[16]/P0_7-FC6_SCK'} +- {pin_num: '42', pin_signal: PIO1_11/FC6_RTS_SCL_SSEL1/CTIMER1_CAP0/FC4_SCK/USB0_VBUS, label: 'J2[19]/P1_11-FC6_RTS_SSEL1-MAG_DRDY'} +- {pin_num: '43', pin_signal: PIO0_8/FC2_RXD_SDA_MOSI/SCT0_OUT1/CTIMER0_MAT3, label: 'J2[15]/P0_8-FC2_RXD_SDA_MOSI'} +- {pin_num: '44', pin_signal: PIO0_9/FC2_TXD_SCL_MISO/SCT0_OUT2/CTIMER3_CAP0/FC3_CTS_SDA_SSEL0, label: 'J2[13]/P0_9-FC2_TXD_SCL_MISO'} +- {pin_num: '45', pin_signal: PIO0_10/FC2_SCK/SCT0_OUT3/CTIMER3_MAT0, label: 'J2[11]/P0_10-FC2_SCK-CT32B3_MAT0'} +- {pin_num: '51', pin_signal: PIO1_12/FC5_RXD_SDA_MOSI/CTIMER1_MAT0/FC7_SCK/UTICK_CAP2, label: 'J2[9]/P1_12-CT32B1_MAT0-ACCl_INT1'} +- {pin_num: '54', pin_signal: PIO1_13/FC5_TXD_SCL_MISO/CTIMER1_MAT1/FC7_RXD_SDA_MOSI_DATA, label: 'J2[7]/P1_13-CT32B1_MAT1'} +- {pin_num: '55', pin_signal: VSS55, label: GND} +- {pin_num: '56', pin_signal: VDD56, label: VDD_LPC54u68_IC} +- {pin_num: '57', pin_signal: PIO1_14/FC2_RXD_SDA_MOSI/SCT0_OUT7/FC7_TXD_SCL_MISO_WS, label: 'J2[1]/P1_14-SCTO7'} +- {pin_num: '61', pin_signal: PIO0_21/CLKOUT/FC0_TXD_SCL_MISO/CTIMER3_MAT0, label: 'J2[2]/P0_21-CLKOUT-SPIFI_CLK'} +- {pin_num: '62', pin_signal: PIO1_15/SCT0_OUT5/CTIMER1_CAP3/FC7_CTS_SDA_SSEL0, label: 'J1[17]/P1_15-SCTO5-FC7_CTS'} +- {pin_num: '64', pin_signal: RESET, label: 'J3[1]/J8[9]/J8[10]/JP7[1]/JS9[1]/JS12[1]/JS29/D4[1]/U4[8]/U5[7]/U10[22]/SW4/nRESET_TRGT', identifier: RESET} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +#include "fsl_common.h" +#include "pin_mux.h" + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + *END**************************************************************************/ +void BOARD_InitBootPins(void) { + BOARD_InitPins(); + BOARD_InitDEBUG_UARTPins(); +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + *END**************************************************************************/ +void BOARD_InitPins(void) { /* Function assigned for the Cortex-M0P */ +} + + +#define PIO023_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO023_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO023_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ +#define PIO024_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO024_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO024_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLink2MCUPins: +- options: {prefix: BOARD_, coreID: core0, enableClock: 'false'} +- pin_list: + - {pin_num: '1', peripheral: FLEXCOMM1, signal: RTS_SCL_SSEL1, pin_signal: PIO0_23/FC1_RTS_SCL_SSEL1/CTIMER0_CAP0/UTICK_CAP1, identifier: LINK2MCU_SCL, i2c_slew: i2c} + - {pin_num: '2', peripheral: FLEXCOMM1, signal: CTS_SDA_SSEL0, pin_signal: PIO0_24/FC1_CTS_SDA_SSEL0/CTIMER0_CAP1/CTIMER0_MAT0, identifier: LINK2MCU_SDA, i2c_slew: i2c} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_InitLink2MCUPins + * Description : Configures pin routing and optionally pin electrical features. + * + *END**************************************************************************/ +void BOARD_InitLink2MCUPins(void) { /* Function assigned for the Cortex-M0P */ + IOCON->PIO[0][23] = ((IOCON->PIO[0][23] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO023_FUNC_ALT1) /* Selects pin function.: PORT023 (pin 1) is configured as FC1_RTS_SCL_SSEL1 */ + | IOCON_PIO_I2CSLEW(PIO023_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ + | IOCON_PIO_DIGIMODE(PIO023_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][24] = ((IOCON->PIO[0][24] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO024_FUNC_ALT1) /* Selects pin function.: PORT024 (pin 2) is configured as FC1_CTS_SDA_SSEL0 */ + | IOCON_PIO_I2CSLEW(PIO024_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ + | IOCON_PIO_DIGIMODE(PIO024_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); +} + + +#define PIO024_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO024_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ +#define PIO031_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO031_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ +#define PIO04_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO04_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitBUTTONsPins: +- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '2', peripheral: GPIO, signal: 'PIO0, 24', pin_signal: PIO0_24/FC1_CTS_SDA_SSEL0/CTIMER0_CAP1/CTIMER0_MAT0, identifier: SW1, direction: INPUT} + - {pin_num: '13', peripheral: GPIO, signal: 'PIO0, 31', pin_signal: PIO0_31/FC2_CTS_SDA_SSEL0/CTIMER0_CAP3/CTIMER0_MAT3/ADC0_2, direction: INPUT} + - {pin_num: '38', peripheral: GPIO, signal: 'PIO0, 4', pin_signal: PIO0_4/FC0_SCK/FC3_SSEL2/CTIMER0_CAP2, identifier: SW3, direction: INPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_InitBUTTONsPins + * Description : Configures pin routing and optionally pin electrical features. + * + *END**************************************************************************/ +void BOARD_InitBUTTONsPins(void) { /* Function assigned for the Cortex-M0P */ + CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + + IOCON->PIO[0][24] = ((IOCON->PIO[0][24] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO024_FUNC_ALT0) /* Selects pin function.: PORT024 (pin 2) is configured as PIO0_24 */ + | IOCON_PIO_DIGIMODE(PIO024_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][31] = ((IOCON->PIO[0][31] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO031_FUNC_ALT0) /* Selects pin function.: PORT031 (pin 13) is configured as PIO0_31 */ + | IOCON_PIO_DIGIMODE(PIO031_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][4] = ((IOCON->PIO[0][4] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO04_FUNC_ALT0) /* Selects pin function.: PORT04 (pin 38) is configured as PIO0_4 */ + | IOCON_PIO_DIGIMODE(PIO04_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); +} + + +#define PIO029_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO029_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ +#define PIO110_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO110_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ +#define PIO19_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO19_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitLEDsPins: +- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '29', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC3_RXD_SDA_MOSI/CTIMER0_CAP2/USB0_UP_LED, direction: OUTPUT} + - {pin_num: '30', peripheral: GPIO, signal: 'PIO1, 10', pin_signal: PIO1_10/FC6_TXD_SCL_MISO_WS/SCT0_OUT4/FC1_SCK/USB0_FRAME, direction: OUTPUT} + - {pin_num: '11', peripheral: GPIO, signal: 'PIO0, 29', pin_signal: PIO0_29/FC1_RXD_SDA_MOSI/SCT0_OUT2/CTIMER0_MAT3/CTIMER0_CAP1/CTIMER0_MAT1/ADC0_0, direction: OUTPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_InitLEDsPins + * Description : Configures pin routing and optionally pin electrical features. + * + *END**************************************************************************/ +void BOARD_InitLEDsPins(void) { /* Function assigned for the Cortex-M0P */ + CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + + IOCON->PIO[0][29] = ((IOCON->PIO[0][29] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO029_FUNC_ALT0) /* Selects pin function.: PORT029 (pin 11) is configured as PIO0_29 */ + | IOCON_PIO_DIGIMODE(PIO029_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[1][10] = ((IOCON->PIO[1][10] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO110_FUNC_ALT0) /* Selects pin function.: PORT110 (pin 30) is configured as PIO1_10 */ + | IOCON_PIO_DIGIMODE(PIO110_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[1][9] = ((IOCON->PIO[1][9] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO19_FUNC_ALT0) /* Selects pin function.: PORT19 (pin 29) is configured as PIO1_9 */ + | IOCON_PIO_DIGIMODE(PIO19_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); +} + + +#define PIO025_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO025_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO025_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ +#define PIO026_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO026_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO026_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSecureMCUPins: +- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '3', peripheral: FLEXCOMM4, signal: RTS_SCL_SSEL1, pin_signal: PIO0_25/FC4_RTS_SCL_SSEL1/FC6_CTS_SDA_SSEL0/CTIMER0_CAP2/CTIMER1_CAP1, i2c_slew: i2c} + - {pin_num: '4', peripheral: FLEXCOMM4, signal: CTS_SDA_SSEL0, pin_signal: PIO0_26/FC4_CTS_SDA_SSEL0/CTIMER0_CAP3, i2c_slew: i2c} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_InitSecureMCUPins + * Description : Configures pin routing and optionally pin electrical features. + * + *END**************************************************************************/ +void BOARD_InitSecureMCUPins(void) { /* Function assigned for the Cortex-M0P */ + CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + + IOCON->PIO[0][25] = ((IOCON->PIO[0][25] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO025_FUNC_ALT1) /* Selects pin function.: PORT025 (pin 3) is configured as FC4_RTS_SCL_SSEL1 */ + | IOCON_PIO_I2CSLEW(PIO025_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ + | IOCON_PIO_DIGIMODE(PIO025_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][26] = ((IOCON->PIO[0][26] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO026_FUNC_ALT1) /* Selects pin function.: PORT026 (pin 4) is configured as FC4_CTS_SDA_SSEL0 */ + | IOCON_PIO_I2CSLEW(PIO026_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ + | IOCON_PIO_DIGIMODE(PIO026_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); +} + + +#define PIO018_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO018_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO019_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO019_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO020_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO020_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO12_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO12_FUNC_ALT4 0x04u /*!< Selects pin function.: Alternative connection 4. */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSPI_FLASHPins: +- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '58', peripheral: FLEXCOMM5, signal: TXD_SCL_MISO, pin_signal: PIO0_18/FC5_TXD_SCL_MISO/SCT0_OUT0/CTIMER0_MAT0} + - {pin_num: '59', peripheral: FLEXCOMM5, signal: SCK, pin_signal: PIO0_19/FC5_SCK/SCT0_OUT1/CTIMER0_MAT1} + - {pin_num: '60', peripheral: FLEXCOMM5, signal: RXD_SDA_MOSI, pin_signal: PIO0_20/FC5_RXD_SDA_MOSI/FC0_SCK/CTIMER3_CAP0} + - {pin_num: '16', peripheral: FLEXCOMM5, signal: SSEL3, pin_signal: PIO1_2/MCLK/FC7_SSEL3/SCT0_OUT5/FC5_SSEL3/FC4_RXD_SDA_MOSI/ADC0_5} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_InitSPI_FLASHPins + * Description : Configures pin routing and optionally pin electrical features. + * + *END**************************************************************************/ +void BOARD_InitSPI_FLASHPins(void) { /* Function assigned for the Cortex-M0P */ + CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + + IOCON->PIO[0][18] = ((IOCON->PIO[0][18] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO018_FUNC_ALT1) /* Selects pin function.: PORT018 (pin 58) is configured as FC5_TXD_SCL_MISO */ + | IOCON_PIO_DIGIMODE(PIO018_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][19] = ((IOCON->PIO[0][19] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO019_FUNC_ALT1) /* Selects pin function.: PORT019 (pin 59) is configured as FC5_SCK */ + | IOCON_PIO_DIGIMODE(PIO019_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][20] = ((IOCON->PIO[0][20] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO020_FUNC_ALT1) /* Selects pin function.: PORT020 (pin 60) is configured as FC5_RXD_SDA_MOSI */ + | IOCON_PIO_DIGIMODE(PIO020_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[1][2] = ((IOCON->PIO[1][2] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO12_FUNC_ALT4) /* Selects pin function.: PORT12 (pin 16) is configured as FC5_SSEL3 */ + | IOCON_PIO_DIGIMODE(PIO12_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); +} + + +#define PIO011_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO011_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO012_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO012_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO013_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO013_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO014_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO014_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO022_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO022_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ +#define PIO023_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO023_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO023_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ +#define PIO024_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO024_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO024_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ +#define PIO04_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO04_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPMod_SPI_I2C_BRIDGEPins: +- options: {coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '38', peripheral: GPIO, signal: 'PIO0, 4', pin_signal: PIO0_4/FC0_SCK/FC3_SSEL2/CTIMER0_CAP2, identifier: BRIDGE_T_INTR} + - {pin_num: '46', peripheral: FLEXCOMM3, signal: SCK, pin_signal: PIO0_11/FC3_SCK/FC6_RXD_SDA_MOSI_DATA, direction: OUTPUT} + - {pin_num: '47', peripheral: FLEXCOMM3, signal: RXD_SDA_MOSI, pin_signal: PIO0_12/FC3_RXD_SDA_MOSI/FC6_TXD_SCL_MISO_WS, direction: OUTPUT} + - {pin_num: '48', peripheral: FLEXCOMM3, signal: TXD_SCL_MISO, pin_signal: PIO0_13/FC3_TXD_SCL_MISO/SCT0_OUT4, direction: INPUT} + - {pin_num: '49', peripheral: FLEXCOMM3, signal: CTS_SDA_SSEL0, pin_signal: PIO0_14/FC3_CTS_SDA_SSEL0/SCT0_OUT5/FC1_SCK, direction: OUTPUT} + - {pin_num: '63', peripheral: GPIO, signal: 'PIO0, 22', pin_signal: PIO0_22/CLKIN/FC0_RXD_SDA_MOSI/CTIMER3_MAT3} + - {pin_num: '1', peripheral: FLEXCOMM1, signal: RTS_SCL_SSEL1, pin_signal: PIO0_23/FC1_RTS_SCL_SSEL1/CTIMER0_CAP0/UTICK_CAP1, identifier: BRIDGE_SCL, i2c_slew: i2c} + - {pin_num: '2', peripheral: FLEXCOMM1, signal: CTS_SDA_SSEL0, pin_signal: PIO0_24/FC1_CTS_SDA_SSEL0/CTIMER0_CAP1/CTIMER0_MAT0, identifier: BRIDGE_SDA_WAKEUP, i2c_slew: i2c} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_InitPMod_SPI_I2C_BRIDGEPins + * Description : Configures pin routing and optionally pin electrical features. + * + *END**************************************************************************/ +void BOARD_InitPMod_SPI_I2C_BRIDGEPins(void) { /* Function assigned for the Cortex-M0P */ + CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + + IOCON->PIO[0][11] = ((IOCON->PIO[0][11] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO011_FUNC_ALT1) /* Selects pin function.: PORT011 (pin 46) is configured as FC3_SCK */ + | IOCON_PIO_DIGIMODE(PIO011_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][12] = ((IOCON->PIO[0][12] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO012_FUNC_ALT1) /* Selects pin function.: PORT012 (pin 47) is configured as FC3_RXD_SDA_MOSI */ + | IOCON_PIO_DIGIMODE(PIO012_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][13] = ((IOCON->PIO[0][13] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO013_FUNC_ALT1) /* Selects pin function.: PORT013 (pin 48) is configured as FC3_TXD_SCL_MISO */ + | IOCON_PIO_DIGIMODE(PIO013_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][14] = ((IOCON->PIO[0][14] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO014_FUNC_ALT1) /* Selects pin function.: PORT014 (pin 49) is configured as FC3_CTS_SDA_SSEL0 */ + | IOCON_PIO_DIGIMODE(PIO014_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][22] = ((IOCON->PIO[0][22] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO022_FUNC_ALT0) /* Selects pin function.: PORT022 (pin 63) is configured as PIO0_22 */ + | IOCON_PIO_DIGIMODE(PIO022_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][23] = ((IOCON->PIO[0][23] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO023_FUNC_ALT1) /* Selects pin function.: PORT023 (pin 1) is configured as FC1_RTS_SCL_SSEL1 */ + | IOCON_PIO_I2CSLEW(PIO023_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ + | IOCON_PIO_DIGIMODE(PIO023_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][24] = ((IOCON->PIO[0][24] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO024_FUNC_ALT1) /* Selects pin function.: PORT024 (pin 2) is configured as FC1_CTS_SDA_SSEL0 */ + | IOCON_PIO_I2CSLEW(PIO024_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ + | IOCON_PIO_DIGIMODE(PIO024_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][4] = ((IOCON->PIO[0][4] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO04_FUNC_ALT0) /* Selects pin function.: PORT04 (pin 38) is configured as PIO0_4 */ + | IOCON_PIO_DIGIMODE(PIO04_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); +} + + +#define PIO16_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO16_FUNC_ALT7 0x07u /*!< Selects pin function.: Alternative connection 7. */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitUSBPins: +- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '5', peripheral: USB0, signal: USB_DP, pin_signal: USB0_DP} + - {pin_num: '6', peripheral: USB0, signal: USB_DM, pin_signal: USB0_DM} + - {pin_num: '26', peripheral: USB0, signal: USB_VBUS, pin_signal: PIO1_6/FC7_SCK/CTIMER1_CAP2/CTIMER1_MAT2/USB0_VBUS/ADC0_9} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_InitUSBPins + * Description : Configures pin routing and optionally pin electrical features. + * + *END**************************************************************************/ +void BOARD_InitUSBPins(void) { /* Function assigned for the Cortex-M0P */ + CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + + IOCON->PIO[1][6] = ((IOCON->PIO[1][6] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO16_FUNC_ALT7) /* Selects pin function.: PORT16 (pin 26) is configured as USB0_VBUS */ + | IOCON_PIO_DIGIMODE(PIO16_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); +} + + +#define PIO00_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO00_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ +#define PIO01_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO01_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'false'} +- pin_list: + - {pin_num: '32', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO, pin_signal: PIO0_1/FC0_TXD_SCL_MISO/FC3_RTS_SCL_SSEL1/CTIMER0_CAP1/SCT0_OUT1, direction: OUTPUT} + - {pin_num: '31', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI, pin_signal: PIO0_0/FC0_RXD_SDA_MOSI/FC3_CTS_SDA_SSEL0/CTIMER0_CAP0/SCT0_OUT3, direction: INPUT} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + *END**************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { /* Function assigned for the Cortex-M0P */ + CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + + IOCON->PIO[0][0] = ((IOCON->PIO[0][0] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO00_FUNC_ALT1) /* Selects pin function.: PORT00 (pin 31) is configured as FC0_RXD_SDA_MOSI */ + | IOCON_PIO_DIGIMODE(PIO00_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][1] = ((IOCON->PIO[0][1] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO01_FUNC_ALT1) /* Selects pin function.: PORT01 (pin 32) is configured as FC0_TXD_SCL_MISO */ + | IOCON_PIO_DIGIMODE(PIO01_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); +} + + +#define PIO016_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO016_FUNC_ALT5 0x05u /*!< Selects pin function.: Alternative connection 5. */ +#define PIO017_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ +#define PIO017_FUNC_ALT5 0x05u /*!< Selects pin function.: Alternative connection 5. */ + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitSWD_DEBUGPins: +- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '53', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_17/FC3_SSEL3/FC6_RTS_SCL_SSEL1/CTIMER3_MAT2/SWDIO} + - {pin_num: '52', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_16/FC3_SSEL2/FC6_CTS_SDA_SSEL0/CTIMER3_MAT1/SWCLK} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/*FUNCTION********************************************************************** + * + * Function Name : BOARD_InitSWD_DEBUGPins + * Description : Configures pin routing and optionally pin electrical features. + * + *END**************************************************************************/ +void BOARD_InitSWD_DEBUGPins(void) { /* Function assigned for the Cortex-M0P */ + CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ + + IOCON->PIO[0][16] = ((IOCON->PIO[0][16] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO016_FUNC_ALT5) /* Selects pin function.: PORT016 (pin 52) is configured as SWCLK */ + | IOCON_PIO_DIGIMODE(PIO016_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); + IOCON->PIO[0][17] = ((IOCON->PIO[0][17] & + (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ + | IOCON_PIO_FUNC(PIO017_FUNC_ALT5) /* Selects pin function.: PORT017 (pin 53) is configured as SWDIO */ + | IOCON_PIO_DIGIMODE(PIO017_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ + ); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/pin_mux.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/pin_mux.h new file mode 100644 index 000000000..9a24068b5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/board/boards/pin_mux.h @@ -0,0 +1,337 @@ +/* + * Copyright 2018 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Direction type */ +typedef enum _pin_mux_direction +{ + kPIN_MUX_DirectionInput = 0U, /* Input direction */ + kPIN_MUX_DirectionOutput = 1U, /* Output direction */ + kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ +} pin_mux_direction_t; + +/*! + * @addtogroup pin_mux + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); /* Function assigned for the Cortex-M0P */ + +/* FC1_RTS_SCL_SSEL1 (number 1), J4[9]/JS3[1]/JS4[3]/U10[7]/U12[D6]/BRIDGE_SCL */ +#define BOARD_LINK2MCU_SCL_PERIPHERAL FLEXCOMM1 /*!< Device name: FLEXCOMM1 */ +#define BOARD_LINK2MCU_SCL_SIGNAL RTS_SCL_SSEL1 /*!< FLEXCOMM1 signal: RTS_SCL_SSEL1 */ +#define BOARD_LINK2MCU_SCL_PIN_NAME FC1_RTS_SCL_SSEL1 /*!< Pin name */ +#define BOARD_LINK2MCU_SCL_LABEL "J4[9]/JS3[1]/JS4[3]/U10[7]/U12[D6]/BRIDGE_SCL" /*!< Label */ +#define BOARD_LINK2MCU_SCL_NAME "LINK2MCU_SCL" /*!< Identifier name */ + +/* FC1_CTS_SDA_SSEL0 (number 2), J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP */ +#define BOARD_LINK2MCU_SDA_PERIPHERAL FLEXCOMM1 /*!< Device name: FLEXCOMM1 */ +#define BOARD_LINK2MCU_SDA_SIGNAL CTS_SDA_SSEL0 /*!< FLEXCOMM1 signal: CTS_SDA_SSEL0 */ +#define BOARD_LINK2MCU_SDA_PIN_NAME FC1_CTS_SDA_SSEL0 /*!< Pin name */ +#define BOARD_LINK2MCU_SDA_LABEL "J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP" /*!< Label */ +#define BOARD_LINK2MCU_SDA_NAME "LINK2MCU_SDA" /*!< Identifier name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLink2MCUPins(void); /* Function assigned for the Cortex-M0P */ + +/* PIO0_24 (number 2), J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP */ +#define BOARD_SW1_GPIO GPIO /*!< GPIO device name: GPIO */ +#define BOARD_SW1_PORT 0U /*!< PORT device index: 0 */ +#define BOARD_SW1_GPIO_PIN 24U /*!< PIO0 pin index: 24 */ +#define BOARD_SW1_PIN_NAME PIO0_24 /*!< Pin name */ +#define BOARD_SW1_LABEL "J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP" /*!< Label */ +#define BOARD_SW1_NAME "SW1" /*!< Identifier name */ +#define BOARD_SW1_DIRECTION kPIN_MUX_DirectionInput /*!< Direction */ + +/* PIO0_31 (number 13), J2[17]/J3[2]/P1[7]/U3[4]/SW2/P0_31-PDM0_CLK-ISP0_EN */ +#define BOARD_SW2_GPIO GPIO /*!< GPIO device name: GPIO */ +#define BOARD_SW2_PORT 0U /*!< PORT device index: 0 */ +#define BOARD_SW2_GPIO_PIN 31U /*!< PIO0 pin index: 31 */ +#define BOARD_SW2_PIN_NAME PIO0_31 /*!< Pin name */ +#define BOARD_SW2_LABEL "J2[17]/J3[2]/P1[7]/U3[4]/SW2/P0_31-PDM0_CLK-ISP0_EN" /*!< Label */ +#define BOARD_SW2_NAME "SW2" /*!< Identifier name */ +#define BOARD_SW2_DIRECTION kPIN_MUX_DirectionInput /*!< Direction */ + +/* PIO0_4 (number 38), J4[7]/U9[12]/SW3/BRIDGE_T_INTR-ISP1 */ +#define BOARD_SW3_GPIO GPIO /*!< GPIO device name: GPIO */ +#define BOARD_SW3_PORT 0U /*!< PORT device index: 0 */ +#define BOARD_SW3_GPIO_PIN 4U /*!< PIO0 pin index: 4 */ +#define BOARD_SW3_PIN_NAME PIO0_4 /*!< Pin name */ +#define BOARD_SW3_LABEL "J4[7]/U9[12]/SW3/BRIDGE_T_INTR-ISP1" /*!< Label */ +#define BOARD_SW3_NAME "SW3" /*!< Identifier name */ +#define BOARD_SW3_DIRECTION kPIN_MUX_DirectionInput /*!< Direction */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M0P */ + +/* PIO1_9 (number 29), J9[5]/D2[3]/P1_9-BLUE_LED */ +#define BOARD_LED_BLUE_GPIO GPIO /*!< GPIO device name: GPIO */ +#define BOARD_LED_BLUE_PORT 1U /*!< PORT device index: 1 */ +#define BOARD_LED_BLUE_GPIO_PIN 9U /*!< PIO1 pin index: 9 */ +#define BOARD_LED_BLUE_PIN_NAME PIO1_9 /*!< Pin name */ +#define BOARD_LED_BLUE_LABEL "J9[5]/D2[3]/P1_9-BLUE_LED" /*!< Label */ +#define BOARD_LED_BLUE_NAME "LED_BLUE" /*!< Identifier name */ +#define BOARD_LED_BLUE_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ + +/* PIO1_10 (number 30), J9[8]/D2[4]/P1_10-SCT4-LED_GREEN */ +#define BOARD_LED_GREEN_GPIO GPIO /*!< GPIO device name: GPIO */ +#define BOARD_LED_GREEN_PORT 1U /*!< PORT device index: 1 */ +#define BOARD_LED_GREEN_GPIO_PIN 10U /*!< PIO1 pin index: 10 */ +#define BOARD_LED_GREEN_PIN_NAME PIO1_10 /*!< Pin name */ +#define BOARD_LED_GREEN_LABEL "J9[8]/D2[4]/P1_10-SCT4-LED_GREEN" /*!< Label */ +#define BOARD_LED_GREEN_NAME "LED_GREEN" /*!< Identifier name */ +#define BOARD_LED_GREEN_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ + +/* PIO0_29 (number 11), J2[5]/D2[1]/P0_29-CT32B0_MAT3-RED */ +#define BOARD_LED_RED_GPIO GPIO /*!< GPIO device name: GPIO */ +#define BOARD_LED_RED_PORT 0U /*!< PORT device index: 0 */ +#define BOARD_LED_RED_GPIO_PIN 29U /*!< PIO0 pin index: 29 */ +#define BOARD_LED_RED_PIN_NAME PIO0_29 /*!< Pin name */ +#define BOARD_LED_RED_LABEL "J2[5]/D2[1]/P0_29-CT32B0_MAT3-RED" /*!< Label */ +#define BOARD_LED_RED_NAME "LED_RED" /*!< Identifier name */ +#define BOARD_LED_RED_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M0P */ + +/* FC4_RTS_SCL_SSEL1 (number 3), J1[1]/JS4[1]/U10[7]/P0_25-FC4_SCLX */ +#define BOARD_FC4_SCLX_PERIPHERAL FLEXCOMM4 /*!< Device name: FLEXCOMM4 */ +#define BOARD_FC4_SCLX_SIGNAL RTS_SCL_SSEL1 /*!< FLEXCOMM4 signal: RTS_SCL_SSEL1 */ +#define BOARD_FC4_SCLX_PIN_NAME FC4_RTS_SCL_SSEL1 /*!< Pin name */ +#define BOARD_FC4_SCLX_LABEL "J1[1]/JS4[1]/U10[7]/P0_25-FC4_SCLX" /*!< Label */ +#define BOARD_FC4_SCLX_NAME "FC4_SCLX" /*!< Identifier name */ + +/* FC4_CTS_SDA_SSEL0 (number 4), J1[3]/JS5[1]/U10[5]/P0_26-FC4_SDAX */ +#define BOARD_FC4_SDAX_PERIPHERAL FLEXCOMM4 /*!< Device name: FLEXCOMM4 */ +#define BOARD_FC4_SDAX_SIGNAL CTS_SDA_SSEL0 /*!< FLEXCOMM4 signal: CTS_SDA_SSEL0 */ +#define BOARD_FC4_SDAX_PIN_NAME FC4_CTS_SDA_SSEL0 /*!< Pin name */ +#define BOARD_FC4_SDAX_LABEL "J1[3]/JS5[1]/U10[5]/P0_26-FC4_SDAX" /*!< Label */ +#define BOARD_FC4_SDAX_NAME "FC4_SDAX" /*!< Identifier name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSecureMCUPins(void); /* Function assigned for the Cortex-M0P */ + +/* FC5_TXD_SCL_MISO (number 58), J1[11]/U5[2]/P0_18-FC5_TXD_SCL_MISO */ +#define BOARD_SPI_FLASH_MISO_PERIPHERAL FLEXCOMM5 /*!< Device name: FLEXCOMM5 */ +#define BOARD_SPI_FLASH_MISO_SIGNAL TXD_SCL_MISO /*!< FLEXCOMM5 signal: TXD_SCL_MISO */ +#define BOARD_SPI_FLASH_MISO_PIN_NAME FC5_TXD_SCL_MISO /*!< Pin name */ +#define BOARD_SPI_FLASH_MISO_LABEL "J1[11]/U5[2]/P0_18-FC5_TXD_SCL_MISO" /*!< Label */ +#define BOARD_SPI_FLASH_MISO_NAME "SPI_FLASH_MISO" /*!< Identifier name */ + +/* FC5_SCK (number 59), J1[9]/J2[8]/U5[6]/P0_19-FC5_SCK-SPIFI_CSn */ +#define BOARD_SPI_FLASH_SCK_PERIPHERAL FLEXCOMM5 /*!< Device name: FLEXCOMM5 */ +#define BOARD_SPI_FLASH_SCK_SIGNAL SCK /*!< FLEXCOMM5 signal: SCK */ +#define BOARD_SPI_FLASH_SCK_PIN_NAME FC5_SCK /*!< Pin name */ +#define BOARD_SPI_FLASH_SCK_LABEL "J1[9]/J2[8]/U5[6]/P0_19-FC5_SCK-SPIFI_CSn" /*!< Label */ +#define BOARD_SPI_FLASH_SCK_NAME "SPI_FLASH_SCK" /*!< Identifier name */ + +/* FC5_RXD_SDA_MOSI (number 60), J1[13]/U5[5]/P0_20-FC5_RXD_SDA_MOSI */ +#define BOARD_SPI_FLASH_MOSI_PERIPHERAL FLEXCOMM5 /*!< Device name: FLEXCOMM5 */ +#define BOARD_SPI_FLASH_MOSI_SIGNAL RXD_SDA_MOSI /*!< FLEXCOMM5 signal: RXD_SDA_MOSI */ +#define BOARD_SPI_FLASH_MOSI_PIN_NAME FC5_RXD_SDA_MOSI /*!< Pin name */ +#define BOARD_SPI_FLASH_MOSI_LABEL "J1[13]/U5[5]/P0_20-FC5_RXD_SDA_MOSI" /*!< Label */ +#define BOARD_SPI_FLASH_MOSI_NAME "SPI_FLASH_MOSI" /*!< Identifier name */ + +/* FC5_SSEL3 (number 16), J9[7]/JS8[1]/U5[1]/P1_2-FC5_SSEL3 */ +#define BOARD_FC5_SSEL3_PERIPHERAL FLEXCOMM5 /*!< Device name: FLEXCOMM5 */ +#define BOARD_FC5_SSEL3_SIGNAL SSEL3 /*!< FLEXCOMM5 signal: SSEL3 */ +#define BOARD_FC5_SSEL3_PIN_NAME FC5_SSEL3 /*!< Pin name */ +#define BOARD_FC5_SSEL3_LABEL "J9[7]/JS8[1]/U5[1]/P1_2-FC5_SSEL3" /*!< Label */ +#define BOARD_FC5_SSEL3_NAME "FC5_SSEL3" /*!< Identifier name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSPI_FLASHPins(void); /* Function assigned for the Cortex-M0P */ + +/* PIO0_4 (number 38), J4[7]/U9[12]/SW3/BRIDGE_T_INTR-ISP1 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_GPIO GPIO /*!< GPIO device name: GPIO */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_PORT 0U /*!< PORT device index: 0 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_GPIO_PIN 4U /*!< PIO0 pin index: 4 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_PIN_NAME PIO0_4 /*!< Pin name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_LABEL "J4[7]/U9[12]/SW3/BRIDGE_T_INTR-ISP1" /*!< Label */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_NAME "BRIDGE_T_INTR" /*!< Identifier name */ + +/* FC3_SCK (number 46), J4[4]/U9[13]/BRIDGE_T_SCK */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_PERIPHERAL FLEXCOMM3 /*!< Device name: FLEXCOMM3 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_SIGNAL SCK /*!< FLEXCOMM3 signal: SCK */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_PIN_NAME FC3_SCK /*!< Pin name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_LABEL "J4[4]/U9[13]/BRIDGE_T_SCK" /*!< Label */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_NAME "BRIDGE_T_SCK" /*!< Identifier name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ + +/* FC3_RXD_SDA_MOSI (number 47), J4[2]/U9[11]/BRIDGE_T_MOSI */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_PERIPHERAL FLEXCOMM3 /*!< Device name: FLEXCOMM3 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_SIGNAL RXD_SDA_MOSI /*!< FLEXCOMM3 signal: RXD_SDA_MOSI */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_PIN_NAME FC3_RXD_SDA_MOSI /*!< Pin name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_LABEL "J4[2]/U9[11]/BRIDGE_T_MOSI" /*!< Label */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_NAME "BRIDGE_T_MOSI" /*!< Identifier name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ + +/* FC3_TXD_SCL_MISO (number 48), J4[3]/U15[4]/BRIDGE_T_MISO */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_PERIPHERAL FLEXCOMM3 /*!< Device name: FLEXCOMM3 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_SIGNAL TXD_SCL_MISO /*!< FLEXCOMM3 signal: TXD_SCL_MISO */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_PIN_NAME FC3_TXD_SCL_MISO /*!< Pin name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_LABEL "J4[3]/U15[4]/BRIDGE_T_MISO" /*!< Label */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_NAME "BRIDGE_T_MISO" /*!< Identifier name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_DIRECTION kPIN_MUX_DirectionInput /*!< Direction */ + +/* FC3_CTS_SDA_SSEL0 (number 49), J2[12]/J4[1]/U9[14]/BRIDGE_T_SSEL-SPIFI_IO3 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_PERIPHERAL FLEXCOMM3 /*!< Device name: FLEXCOMM3 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_SIGNAL CTS_SDA_SSEL0 /*!< FLEXCOMM3 signal: CTS_SDA_SSEL0 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_PIN_NAME FC3_CTS_SDA_SSEL0 /*!< Pin name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_LABEL "J2[12]/J4[1]/U9[14]/BRIDGE_T_SSEL-SPIFI_IO3" /*!< Label */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_NAME "BRIDGE_T_SSEL" /*!< Identifier name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ + +/* PIO0_22 (number 63), J4[8]/P0_22-BRIDGE_GPIO */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_GPIO GPIO /*!< GPIO device name: GPIO */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_PORT 0U /*!< PORT device index: 0 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_GPIO_PIN 22U /*!< PIO0 pin index: 22 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_PIN_NAME PIO0_22 /*!< Pin name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_LABEL "J4[8]/P0_22-BRIDGE_GPIO" /*!< Label */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_NAME "BRIDGE_GPIO" /*!< Identifier name */ + +/* FC1_RTS_SCL_SSEL1 (number 1), J4[9]/JS3[1]/JS4[3]/U10[7]/U12[D6]/BRIDGE_SCL */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SCL_PERIPHERAL FLEXCOMM1 /*!< Device name: FLEXCOMM1 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SCL_SIGNAL RTS_SCL_SSEL1 /*!< FLEXCOMM1 signal: RTS_SCL_SSEL1 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SCL_PIN_NAME FC1_RTS_SCL_SSEL1 /*!< Pin name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SCL_LABEL "J4[9]/JS3[1]/JS4[3]/U10[7]/U12[D6]/BRIDGE_SCL" /*!< Label */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SCL_NAME "BRIDGE_SCL" /*!< Identifier name */ + +/* FC1_CTS_SDA_SSEL0 (number 2), J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SDA_WAKEUP_PERIPHERAL FLEXCOMM1 /*!< Device name: FLEXCOMM1 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SDA_WAKEUP_SIGNAL CTS_SDA_SSEL0 /*!< FLEXCOMM1 signal: CTS_SDA_SSEL0 */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SDA_WAKEUP_PIN_NAME FC1_CTS_SDA_SSEL0 /*!< Pin name */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SDA_WAKEUP_LABEL "J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP" /*!< Label */ +#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SDA_WAKEUP_NAME "BRIDGE_SDA_WAKEUP" /*!< Identifier name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPMod_SPI_I2C_BRIDGEPins(void); /* Function assigned for the Cortex-M0P */ + +/* USB0_DP (number 5), J5[3]/U7[2]/USB_DP */ +#define BOARD_USB_DP_PERIPHERAL USB0 /*!< Device name: USB0 */ +#define BOARD_USB_DP_SIGNAL USB_DP /*!< USB0 signal: USB_DP */ +#define BOARD_USB_DP_PIN_NAME USB0_DP /*!< Pin name */ +#define BOARD_USB_DP_LABEL "J5[3]/U7[2]/USB_DP" /*!< Label */ +#define BOARD_USB_DP_NAME "USB_DP" /*!< Identifier name */ + +/* USB0_DM (number 6), J5[2]/U7[3]/USB_DM */ +#define BOARD_USB_DM_PERIPHERAL USB0 /*!< Device name: USB0 */ +#define BOARD_USB_DM_SIGNAL USB_DM /*!< USB0 signal: USB_DM */ +#define BOARD_USB_DM_PIN_NAME USB0_DM /*!< Pin name */ +#define BOARD_USB_DM_LABEL "J5[2]/U7[3]/USB_DM" /*!< Label */ +#define BOARD_USB_DM_NAME "USB_DM" /*!< Identifier name */ + +/* USB0_VBUS (number 26), J1[14]/J5[1]/JP10[2]/P1_6-FC7_SCK-USB_VBUS */ +#define BOARD_USB_VBUS_PERIPHERAL USB0 /*!< Device name: USB0 */ +#define BOARD_USB_VBUS_SIGNAL USB_VBUS /*!< USB0 signal: USB_VBUS */ +#define BOARD_USB_VBUS_PIN_NAME USB0_VBUS /*!< Pin name */ +#define BOARD_USB_VBUS_LABEL "J1[14]/J5[1]/JP10[2]/P1_6-FC7_SCK-USB_VBUS" /*!< Label */ +#define BOARD_USB_VBUS_NAME "USB_VBUS" /*!< Identifier name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M0P */ + +/* FC0_TXD_SCL_MISO (number 32), U6[4]/U22[3]/P0_1-ISP_TX */ +#define BOARD_DEBUG_UART_TX_PERIPHERAL FLEXCOMM0 /*!< Device name: FLEXCOMM0 */ +#define BOARD_DEBUG_UART_TX_SIGNAL TXD_SCL_MISO /*!< FLEXCOMM0 signal: TXD_SCL_MISO */ +#define BOARD_DEBUG_UART_TX_PIN_NAME FC0_TXD_SCL_MISO /*!< Pin name */ +#define BOARD_DEBUG_UART_TX_LABEL "U6[4]/U22[3]/P0_1-ISP_TX" /*!< Label */ +#define BOARD_DEBUG_UART_TX_NAME "DEBUG_UART_TX" /*!< Identifier name */ +#define BOARD_DEBUG_UART_TX_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ + +/* FC0_RXD_SDA_MOSI (number 31), U18[4]/TO_MUX_P0_0-ISP_RX */ +#define BOARD_DEBUG_UART_RX_PERIPHERAL FLEXCOMM0 /*!< Device name: FLEXCOMM0 */ +#define BOARD_DEBUG_UART_RX_SIGNAL RXD_SDA_MOSI /*!< FLEXCOMM0 signal: RXD_SDA_MOSI */ +#define BOARD_DEBUG_UART_RX_PIN_NAME FC0_RXD_SDA_MOSI /*!< Pin name */ +#define BOARD_DEBUG_UART_RX_LABEL "U18[4]/TO_MUX_P0_0-ISP_RX" /*!< Label */ +#define BOARD_DEBUG_UART_RX_NAME "DEBUG_UART_RX" /*!< Identifier name */ +#define BOARD_DEBUG_UART_RX_DIRECTION kPIN_MUX_DirectionInput /*!< Direction */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M0P */ + +/* SWDIO (number 53), J2[6]/P1[2]/U2[5]/U14[4]/IF_TMS_SWDIO-SPIFI_IO0 */ +#define BOARD_DEBUG_SWD_SWDIO_PERIPHERAL SWD /*!< Device name: SWD */ +#define BOARD_DEBUG_SWD_SWDIO_SIGNAL SWDIO /*!< SWD signal: SWDIO */ +#define BOARD_DEBUG_SWD_SWDIO_PIN_NAME SWDIO /*!< Pin name */ +#define BOARD_DEBUG_SWD_SWDIO_LABEL "J2[6]/P1[2]/U2[5]/U14[4]/IF_TMS_SWDIO-SPIFI_IO0" /*!< Label */ +#define BOARD_DEBUG_SWD_SWDIO_NAME "DEBUG_SWD_SWDIO" /*!< Identifier name */ + +/* SWCLK (number 52), J2[4]/JS28/U4[4]/TCK-SWDCLK_TRGT-SPIFI_IO1 */ +#define BOARD_DEBUG_SWD_SWDCLK_PERIPHERAL SWD /*!< Device name: SWD */ +#define BOARD_DEBUG_SWD_SWDCLK_SIGNAL SWCLK /*!< SWD signal: SWCLK */ +#define BOARD_DEBUG_SWD_SWDCLK_PIN_NAME SWCLK /*!< Pin name */ +#define BOARD_DEBUG_SWD_SWDCLK_LABEL "J2[4]/JS28/U4[4]/TCK-SWDCLK_TRGT-SPIFI_IO1" /*!< Label */ +#define BOARD_DEBUG_SWD_SWDCLK_NAME "DEBUG_SWD_SWDCLK" /*!< Identifier name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M0P */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/lists/generic_list.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/lists/generic_list.c new file mode 100644 index 000000000..8224c8ef8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/lists/generic_list.c @@ -0,0 +1,423 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "fsl_common.h" +#include "generic_list.h" + +static list_status_t LIST_Scan(list_handle_t list, list_element_handle_t newElement) +{ + list_element_handle_t element = list->head; + + while (element != NULL) + { + if (element == newElement) + { + return kLIST_DuplicateError; + } + element = element->next; + } + return kLIST_Ok; +} + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*! ********************************************************************************* + * \brief Initialises the list descriptor. + * + * \param[in] list - LIST_ handle to init. + * max - Maximum number of elements in list. 0 for unlimited. + * + * \return void. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +void LIST_Init(list_handle_t list, uint32_t max) +{ + list->head = NULL; + list->tail = NULL; + list->max = (uint16_t)max; + list->size = 0; +} + +/*! ********************************************************************************* + * \brief Gets the list that contains the given element. + * + * \param[in] element - Handle of the element. + * + * \return NULL if element is orphan. + * Handle of the list the element is inserted into. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_handle_t LIST_GetList(list_element_handle_t element) +{ + return element->list; +} + +/*! ********************************************************************************* + * \brief Links element to the tail of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element) +{ + uint32_t regPrimask = DisableGlobalIRQ(); + + if ((list->max != 0U) && (list->max == list->size)) + { + EnableGlobalIRQ(regPrimask); + return kLIST_Full; + } + + if (kLIST_DuplicateError == LIST_Scan(list, element)) + { + EnableGlobalIRQ(regPrimask); + return kLIST_DuplicateError; + } + + if (list->size == 0U) + { + list->head = element; + } + else + { + list->tail->next = element; + } + element->prev = list->tail; + element->next = NULL; + element->list = list; + list->tail = element; + list->size++; + + EnableGlobalIRQ(regPrimask); + return kLIST_Ok; +} + +/*! ********************************************************************************* + * \brief Links element to the head of the list. + * + * \param[in] list - ID of list to insert into. + * element - element to add + * + * \return kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element) +{ + uint32_t regPrimask = DisableGlobalIRQ(); + + if ((list->max != 0U) && (list->max == list->size)) + { + EnableGlobalIRQ(regPrimask); + return kLIST_Full; + } + + if (kLIST_DuplicateError == LIST_Scan(list, element)) + { + EnableGlobalIRQ(regPrimask); + return kLIST_DuplicateError; + } + + if (list->size == 0U) + { + list->tail = element; + } + else + { + list->head->prev = element; + } + element->next = list->head; + element->prev = NULL; + element->list = list; + list->head = element; + list->size++; + + EnableGlobalIRQ(regPrimask); + return kLIST_Ok; +} + +/*! ********************************************************************************* + * \brief Unlinks element from the head of the list. + * + * \param[in] list - ID of list to remove from. + * + * \return NULL if list is empty. + * ID of removed element(pointer) if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_RemoveHead(list_handle_t list) +{ + list_element_handle_t element; + + uint32_t regPrimask = DisableGlobalIRQ(); + + if ((NULL == list) || (list->size == 0U)) + { + EnableGlobalIRQ(regPrimask); + return NULL; /*LIST_ is empty*/ + } + + element = list->head; + list->size--; + if (list->size == 0U) + { + list->tail = NULL; + } + else + { + element->next->prev = NULL; + } + list->head = element->next; /*Is NULL if element is head*/ + element->list = NULL; + + EnableGlobalIRQ(regPrimask); + return element; +} + +/*! ********************************************************************************* + * \brief Gets head element ID. + * + * \param[in] list - ID of list. + * + * \return NULL if list is empty. + * ID of head element if list is not empty. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetHead(list_handle_t list) +{ + return list->head; +} + +/*! ********************************************************************************* + * \brief Gets next element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is tail. + * ID of next element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetNext(list_element_handle_t element) +{ + return element->next; +} + +/*! ********************************************************************************* + * \brief Gets previous element ID. + * + * \param[in] element - ID of the element. + * + * \return NULL if element is head. + * ID of previous element if exists. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_element_handle_t LIST_GetPrev(list_element_handle_t element) +{ + return element->prev; +} + +/*! ********************************************************************************* + * \brief Unlinks an element from its list. + * + * \param[in] element - ID of the element to remove. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Ok if removal was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_RemoveElement(list_element_handle_t element) +{ + if (element->list == NULL) + { + return kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + + uint32_t regPrimask = DisableGlobalIRQ(); + + if (element->prev == NULL) /*Element is head or solo*/ + { + element->list->head = element->next; /*is null if solo*/ + } + if (element->next == NULL) /*Element is tail or solo*/ + { + element->list->tail = element->prev; /*is null if solo*/ + } + if (element->prev != NULL) /*Element is not head*/ + { + element->prev->next = element->next; + } + if (element->next != NULL) /*Element is not tail*/ + { + element->next->prev = element->prev; + } + element->list->size--; + element->list = NULL; + + EnableGlobalIRQ(regPrimask); + return kLIST_Ok; +} + +/*! ********************************************************************************* + * \brief Links an element in the previous position relative to a given member + * of a list. + * + * \param[in] element - ID of a member of a list. + * newElement - new element to insert before the given member. + * + * \return kLIST_OrphanElement if element is not part of any list. + * kLIST_Full if list is full. + * kLIST_Ok if insertion was successful. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement) +{ + if (element->list == NULL) + { + return kLIST_OrphanElement; /*Element was previusly removed or never added*/ + } + uint32_t regPrimask = DisableGlobalIRQ(); + + if ((element->list->max != 0U) && (element->list->max == element->list->size)) + { + EnableGlobalIRQ(regPrimask); + return kLIST_Full; + } + + if (kLIST_DuplicateError == LIST_Scan(element->list, newElement)) + { + EnableGlobalIRQ(regPrimask); + return kLIST_DuplicateError; + } + + if (element->prev == NULL) /*Element is list head*/ + { + element->list->head = newElement; + } + else + { + element->prev->next = newElement; + } + newElement->list = element->list; + element->list->size++; + newElement->next = element; + newElement->prev = element->prev; + element->prev = newElement; + + EnableGlobalIRQ(regPrimask); + return kLIST_Ok; +} + +/*! ********************************************************************************* + * \brief Gets the current size of a list. + * + * \param[in] list - ID of the list. + * + * \return Current size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetSize(list_handle_t list) +{ + return list->size; +} + +/*! ********************************************************************************* + * \brief Gets the number of free places in the list. + * + * \param[in] list - ID of the list. + * + * \return Available size of the list. + * + * \pre + * + * \post + * + * \remarks + * + ********************************************************************************** */ +uint32_t LIST_GetAvailableSize(list_handle_t list) +{ + return ((uint32_t)list->max - (uint32_t)list->size); +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/lists/generic_list.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/lists/generic_list.h new file mode 100644 index 000000000..ebcbe2717 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/lists/generic_list.h @@ -0,0 +1,191 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _GENERIC_LIST_H_ +#define _GENERIC_LIST_H_ + +/*! + * @addtogroup GenericList + * @{ + */ + +/*!********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public macro definitions +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public type definitions +************************************************************************************* +********************************************************************************** */ +/*! @brief The list status */ +typedef enum _list_status +{ + kLIST_Ok = kStatus_Success, /*!< Success */ + kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */ + kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */ + kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */ + kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */ +} list_status_t; + +/*! @brief The list structure*/ +typedef struct list_tag +{ + struct list_element_tag *head; /*!< list head */ + struct list_element_tag *tail; /*!< list tail */ + uint16_t size; /*!< list size */ + uint16_t max; /*!< list max number of elements */ +} list_t, *list_handle_t; + +/*! @brief The list element*/ +typedef struct list_element_tag +{ + struct list_element_tag *next; /*!< next list element */ + struct list_element_tag *prev; /*!< previous list element */ + struct list_tag *list; /*!< pointer to the list */ +} list_element_t, *list_element_handle_t; + +/*! ********************************************************************************* +************************************************************************************* +* Public prototypes +************************************************************************************* +********************************************************************************** */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ +/*! + * @brief Initialize the list. + * + * This function initialize the list. + * + * @param list - List handle to initialize. + * @param max - Maximum number of elements in list. 0 for unlimited. + */ +void LIST_Init(list_handle_t list, uint32_t max); + +/*! + * @brief Gets the list that contains the given element. + * + * + * @param element - Handle of the element. + * @retval NULL if element is orphan, Handle of the list the element is inserted into. + */ +list_handle_t LIST_GetList(list_element_handle_t element); + +/*! + * @brief Links element to the head of the list. + * + * @param list - Handle of the list. + * @param element - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element); + +/*! + * @brief Links element to the tail of the list. + * + * @param list - Handle of the list. + * @param element - Handle of the element. + * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. + */ +list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element); + +/*! + * @brief Unlinks element from the head of the list. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_RemoveHead(list_handle_t list); + +/*! + * @brief Gets head element handle. + * + * @param list - Handle of the list. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetHead(list_handle_t list); + +/*! + * @brief Gets next element handle for given element handle. + * + * @param element - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetNext(list_element_handle_t element); + +/*! + * @brief Gets previous element handle for given element handle. + * + * @param element - Handle of the element. + * + * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. + */ +list_element_handle_t LIST_GetPrev(list_element_handle_t element); + +/*! + * @brief Unlinks an element from its list. + * + * @param element - Handle of the element. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_RemoveElement(list_element_handle_t element); + +/*! + * @brief Links an element in the previous position relative to a given member of a list. + * + * @param element - Handle of the element. + * @param newElement - New element to insert before the given member. + * + * @retval kLIST_OrphanElement if element is not part of any list. + * @retval kLIST_Ok if removal was successful. + */ +list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement); + +/*! + * @brief Gets the current size of a list. + * + * @param list - Handle of the list. + * + * @retval Current size of the list. + */ +uint32_t LIST_GetSize(list_handle_t list); + +/*! + * @brief Gets the number of free places in the list. + * + * @param list - Handle of the list. + * + * @retval Available size of the list. + */ +uint32_t LIST_GetAvailableSize(list_handle_t list); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /*_GENERIC_LIST_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_manager.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_manager.c new file mode 100644 index 000000000..eca551541 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_manager.c @@ -0,0 +1,1299 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include + +#include "serial_manager.h" +#include "serial_port_internal.h" +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#include "generic_list.h" + +/* + * The OSA_USED macro can only be defined when the OSA component is used. + * If the source code of the OSA component does not exist, the OSA_USED cannot be defined. + * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED + * also cannot be defined. + * The source code path of the OSA component is /components/osa. + * + */ +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#include "common_task.h" +#else +#include "fsl_os_abstraction.h" +#endif + +#endif + +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#endif +#endif + +#define SERIAL_EVENT_DATA_RECEIVED (1U << 0) +#define SERIAL_EVENT_DATA_SENT (1U << 1) + +#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U +#define SERIAL_MANAGER_READ_TAG 0xBBAA5244U + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +typedef enum _serial_manager_transmission_mode +{ + kSerialManager_TransmissionBlocking = 0x0U, /*!< Blocking transmission*/ + kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/ +} serial_manager_transmission_mode_t; + +/* TX transfer structure */ +typedef struct _serial_manager_transfer +{ + uint8_t *buffer; + volatile uint32_t length; + volatile uint32_t soFar; + serial_manager_transmission_mode_t mode; + serial_manager_status_t status; +} serial_manager_transfer_t; +#endif + +/* write handle structure */ +typedef struct _serial_manager_send_handle +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + list_element_t link; /*!< list element of the link */ + serial_manager_transfer_t transfer; +#endif + struct _serial_manager_handle *serialManagerHandle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_manager_callback_t callback; + void *callbackParam; + uint32_t tag; +#endif +} serial_manager_write_handle_t; + +typedef serial_manager_write_handle_t serial_manager_read_handle_t; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +/* receive state structure */ +typedef struct _serial_manager_read_ring_buffer +{ + uint8_t *ringBuffer; + uint32_t ringBufferSize; + volatile uint32_t ringHead; + volatile uint32_t ringTail; +} serial_manager_read_ring_buffer_t; +#endif + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/* The serial manager handle structure */ +typedef struct _serial_manager_handle +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + list_t runningWriteHandleHead; /*!< The queue of running write handle */ + list_t completedWriteHandleHead; /*!< The queue of completed write handle */ +#endif + serial_manager_read_handle_t *openedReadHandleHead; + uint32_t openedWriteHandleCount; + union + { + uint8_t lowLevelhandleBuffer[1]; +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE]; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + uint8_t usbcdcVirtualHandleBuffer[SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE]; +#endif + }; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_manager_read_ring_buffer_t ringBuffer; +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + common_task_message_t commontaskMsg; +#else + uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */ + uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */ +#endif + +#endif + +#endif + + serial_port_type_t type; +} serial_manager_handle_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_Task(void *param); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + +#else + /* + * \brief Defines the serial manager task's stack + */ +OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false); +#endif + +#endif + +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_AddTail(list_t *queue, serial_manager_write_handle_t *node) +{ + (void)LIST_AddTail(queue, &node->link); +} + +static void SerialManager_RemoveHead(list_t *queue) +{ + (void)LIST_RemoveHead(queue); +} +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + serial_manager_write_handle_t *writeHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead); + + if (writeHandle != NULL) + { + switch (handle->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + case kSerialPort_UsbCdcVirtual: + status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + writeHandle->transfer.buffer, writeHandle->transfer.length); + break; +#endif + default: + status = kStatus_SerialManager_Error; + break; + } + } + return status; +} + +static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle, + serial_manager_read_handle_t *readHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + + if (readHandle != NULL) + { +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + if (handle->type == kSerialPort_UsbCdc) + { + status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + if (handle->type == kSerialPort_UsbCdcVirtual) + { + status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + } +#endif + } + return status; +} + +#else + +static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle, + serial_manager_write_handle_t *writeHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + + if (writeHandle != NULL) + { + switch (handle->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + case kSerialPort_UsbCdcVirtual: + status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + break; +#endif + default: + status = kStatus_SerialManager_Error; + break; + } + } + return status; +} + +static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle, + serial_manager_read_handle_t *readHandle, + uint8_t *buffer, + uint32_t length) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + + if (readHandle != NULL) + { + switch (handle->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + status = Serial_SwoRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + case kSerialPort_UsbCdcVirtual: + status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); + break; +#endif + default: + status = kStatus_SerialManager_Error; + break; + } + } + return status; +} +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_IsrFunction(serial_manager_handle_t *handle) +{ + uint32_t regPrimask = DisableGlobalIRQ(); + switch (handle->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + Serial_UartIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + Serial_UsbCdcIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + Serial_SwoIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + case kSerialPort_UsbCdcVirtual: + Serial_UsbCdcVirtualIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + EnableGlobalIRQ(regPrimask); +} + +static void SerialManager_Task(void *param) +{ + serial_manager_handle_t *handle = (serial_manager_handle_t *)param; + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_read_handle_t *serialReadHandle; + serial_manager_callback_message_t msg; + if (NULL != handle) + { +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + osa_event_flags_t ev = 0; + + do + { + if (KOSA_StatusSuccess == + OSA_EventWait((osa_event_handle_t)handle->event, osaEventFlagsAll_c, false, osaWaitForever_c, &ev)) + { + if (ev & SERIAL_EVENT_DATA_SENT) +#endif + +#endif + { + serialWriteHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead); + while (NULL != serialWriteHandle) + { + SerialManager_RemoveHead(&handle->completedWriteHandleHead); + msg.buffer = serialWriteHandle->transfer.buffer; + msg.length = serialWriteHandle->transfer.soFar; + serialWriteHandle->transfer.buffer = NULL; + if (serialWriteHandle->callback != NULL) + { + serialWriteHandle->callback(serialWriteHandle->callbackParam, &msg, + serialWriteHandle->transfer.status); + } + serialWriteHandle = + (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead); + } + } +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + if (ev & SERIAL_EVENT_DATA_RECEIVED) +#endif + +#endif + { + serialReadHandle = handle->openedReadHandleHead; + if (serialReadHandle != NULL) + { + if (serialReadHandle->transfer.buffer != NULL) + { + if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length) + { + msg.buffer = serialReadHandle->transfer.buffer; + msg.length = serialReadHandle->transfer.soFar; + serialReadHandle->transfer.buffer = NULL; + if (serialReadHandle->callback != NULL) + { + serialReadHandle->callback(serialReadHandle->callbackParam, &msg, + serialReadHandle->transfer.status); + } + } + } + } + } +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + } + } while (gUseRtos_c); +#endif + +#endif + } +} +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +static void SerialManager_TxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + serial_manager_handle_t *handle; + serial_manager_write_handle_t *writeHandle; + + assert(callbackParam); + assert(message); + + handle = (serial_manager_handle_t *)callbackParam; + + writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead); + + if (NULL != writeHandle) + { + SerialManager_RemoveHead(&handle->runningWriteHandleHead); + (void)SerialManager_StartWriting(handle); + writeHandle->transfer.soFar = message->length; + writeHandle->transfer.status = status; + if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode) + { + SerialManager_AddTail(&handle->completedWriteHandleHead, writeHandle); +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + handle->commontaskMsg.callback = SerialManager_Task; + handle->commontaskMsg.callbackParam = handle; + COMMON_TASK_post_message(&handle->commontaskMsg); +#else + (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_SENT); +#endif + +#else + SerialManager_Task(handle); +#endif + } + else + { + writeHandle->transfer.buffer = NULL; + } + } +} + +static void SerialManager_RxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + serial_manager_handle_t *handle; + uint32_t ringBufferLength; + + assert(callbackParam); + assert(message); + + handle = (serial_manager_handle_t *)callbackParam; + + status = kStatus_SerialManager_Notify; + + for (uint32_t i = 0; i < message->length; i++) + { + handle->ringBuffer.ringBuffer[handle->ringBuffer.ringHead++] = message->buffer[i]; + if (handle->ringBuffer.ringHead >= handle->ringBuffer.ringBufferSize) + { + handle->ringBuffer.ringHead = 0U; + } + if (handle->ringBuffer.ringHead == handle->ringBuffer.ringTail) + { + status = kStatus_SerialManager_RingBufferOverflow; + handle->ringBuffer.ringTail++; + if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) + { + handle->ringBuffer.ringTail = 0U; + } + } + } + + ringBufferLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; + ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize; + + if ((handle->openedReadHandleHead != NULL) && (handle->openedReadHandleHead->transfer.buffer != NULL)) + { + if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar) + { + uint32_t remainLength = + handle->openedReadHandleHead->transfer.length - handle->openedReadHandleHead->transfer.soFar; + for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++) + { + handle->openedReadHandleHead->transfer.buffer[handle->openedReadHandleHead->transfer.soFar] = + handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail]; + handle->ringBuffer.ringTail++; + handle->openedReadHandleHead->transfer.soFar++; + if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) + { + handle->ringBuffer.ringTail = 0U; + } + } + ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength); + } + + if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar) + { + } + else + { + if (kSerialManager_TransmissionBlocking == handle->openedReadHandleHead->transfer.mode) + { + handle->openedReadHandleHead->transfer.buffer = NULL; + } + else + { + handle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success; + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + handle->commontaskMsg.callback = SerialManager_Task; + handle->commontaskMsg.callbackParam = handle; + COMMON_TASK_post_message(&handle->commontaskMsg); +#else + (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_RECEIVED); +#endif + +#else + SerialManager_Task(handle); +#endif + } + } + } + + if (ringBufferLength != 0U) + { + message->buffer = NULL; + message->length = ringBufferLength; + if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->callback)) + { + handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, message, status); + } + } + + ringBufferLength = handle->ringBuffer.ringBufferSize - 1U - ringBufferLength; + + if (NULL != handle->openedReadHandleHead) + { + (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, ringBufferLength); + } +} + +static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length, + serial_manager_transmission_mode_t mode) +{ + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_handle_t *handle; + serial_manager_status_t status = kStatus_SerialManager_Success; + uint32_t primask; + uint8_t isEmpty = 0U; + + assert(writeHandle); + assert(buffer); + assert(length); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + handle = serialWriteHandle->serialManagerHandle; + + assert(handle); + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback))); + + primask = DisableGlobalIRQ(); + if (serialWriteHandle->transfer.buffer != NULL) + { + EnableGlobalIRQ(primask); + return kStatus_SerialManager_Busy; + } + serialWriteHandle->transfer.buffer = buffer; + serialWriteHandle->transfer.length = length; + serialWriteHandle->transfer.soFar = 0U; + serialWriteHandle->transfer.mode = mode; + + if (NULL == LIST_GetHead(&handle->runningWriteHandleHead)) + { + isEmpty = 1U; + } + SerialManager_AddTail(&handle->runningWriteHandleHead, serialWriteHandle); + EnableGlobalIRQ(primask); + + if (isEmpty != 0U) + { + status = SerialManager_StartWriting(handle); + if ((serial_manager_status_t)kStatus_SerialManager_Success != status) + { + return status; + } + } + + if (kSerialManager_TransmissionBlocking == mode) + { + while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar) + { +#if defined(__GIC_PRIO_BITS) + if ((__get_CPSR() & CPSR_M_Msk) == 0x13) +#else + if (__get_IPSR() != 0U) +#endif + { + SerialManager_IsrFunction(handle); + } + } + } + return kStatus_SerialManager_Success; +} + +static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + serial_manager_transmission_mode_t mode, + uint32_t *receivedLength) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_handle_t *handle; + uint32_t dataLength; + uint32_t primask; + + assert(readHandle); + assert(buffer); + assert(length); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + handle = serialReadHandle->serialManagerHandle; + + assert(handle); + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback))); + + primask = DisableGlobalIRQ(); + if (serialReadHandle->transfer.buffer != NULL) + { + EnableGlobalIRQ(primask); + return kStatus_SerialManager_Busy; + } + serialReadHandle->transfer.buffer = buffer; + serialReadHandle->transfer.length = length; + serialReadHandle->transfer.soFar = 0U; + serialReadHandle->transfer.mode = mode; + + dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; + dataLength = dataLength % handle->ringBuffer.ringBufferSize; + + for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length); + serialReadHandle->transfer.soFar++) + { + buffer[serialReadHandle->transfer.soFar] = handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail]; + handle->ringBuffer.ringTail++; + if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) + { + handle->ringBuffer.ringTail = 0U; + } + } + + dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; + dataLength = dataLength % handle->ringBuffer.ringBufferSize; + dataLength = handle->ringBuffer.ringBufferSize - 1U - dataLength; + + (void)SerialManager_StartReading(handle, readHandle, NULL, dataLength); + + if (receivedLength != NULL) + { + *receivedLength = serialReadHandle->transfer.soFar; + serialReadHandle->transfer.buffer = NULL; + EnableGlobalIRQ(primask); + } + else + { + if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length) + { + serialReadHandle->transfer.buffer = NULL; + EnableGlobalIRQ(primask); + if (kSerialManager_TransmissionNonBlocking == mode) + { + if (serialReadHandle->callback != NULL) + { + serial_manager_callback_message_t msg; + msg.buffer = buffer; + msg.length = serialReadHandle->transfer.soFar; + serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Success); + } + } + } + else + { + EnableGlobalIRQ(primask); + } + + if (kSerialManager_TransmissionBlocking == mode) + { + while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar) + { + } + } + } + + return kStatus_SerialManager_Success; +} + +#else + +static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length) +{ + serial_manager_write_handle_t *serialWriteHandle; + serial_manager_handle_t *handle; + + assert(writeHandle); + assert(buffer); + assert(length); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + handle = serialWriteHandle->serialManagerHandle; + + assert(handle); + + return SerialManager_StartWriting(handle, serialWriteHandle, buffer, length); +} + +static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_handle_t *handle; + + assert(readHandle); + assert(buffer); + assert(length); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + handle = serialReadHandle->serialManagerHandle; + + assert(handle); + + return SerialManager_StartReading(handle, serialReadHandle, buffer, length); +} +#endif + +serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config) +{ + serial_manager_handle_t *handle; + serial_manager_status_t status = kStatus_SerialManager_Error; + + assert(config); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + assert(config->ringBuffer); + assert(config->ringBufferSize); +#endif + assert(serialHandle); + assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t)); + + handle = (serial_manager_handle_t *)serialHandle; + + (void)memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + + COMMON_TASK_init(); + +#else + if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)handle->event, true)) + { + return kStatus_SerialManager_Error; + } + + if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)handle->taskId, OSA_TASK(SerialManager_Task), handle)) + { + return kStatus_SerialManager_Error; + } +#endif + +#endif + +#endif + + handle->type = config->type; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + handle->ringBuffer.ringBuffer = config->ringBuffer; + handle->ringBuffer.ringBufferSize = config->ringBufferSize; +#endif + + switch (config->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + status = Serial_UartInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if ((serial_manager_status_t)kStatus_SerialManager_Success == status) + { + status = Serial_UartInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, handle); + if ((serial_manager_status_t)kStatus_SerialManager_Success == status) + { + status = Serial_UartInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, handle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + status = Serial_UsbCdcInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, handle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, handle); + } + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + status = Serial_SwoInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_SwoInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, handle); + } +#endif + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + case kSerialPort_UsbCdcVirtual: + status = Serial_UsbCdcVirtualInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + if (kStatus_SerialManager_Success == status) + { + status = Serial_UsbCdcVirtualInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_TxCallback, handle); + if (kStatus_SerialManager_Success == status) + { + status = Serial_UsbCdcVirtualInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), + SerialManager_RxCallback, handle); + } + } +#endif + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + + return status; +} + +serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle) +{ + serial_manager_handle_t *handle; + + assert(serialHandle); + + handle = (serial_manager_handle_t *)serialHandle; + + if ((handle->openedReadHandleHead != NULL) || (handle->openedWriteHandleCount != 0U)) + { + return kStatus_SerialManager_Busy; + } + + switch (handle->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + (void)Serial_UartDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + (void)Serial_UsbCdcDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + (void)Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + case kSerialPort_UsbCdcVirtual: + Serial_UsbCdcVirtualDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + (void)Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) +#else + OSA_EventDestroy((osa_event_handle_t)handle->event); + OSA_TaskDestroy((osa_task_handle_t)handle->taskId); +#endif + +#endif + +#endif + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle) +{ + serial_manager_handle_t *handle; + serial_manager_write_handle_t *serialWriteHandle; + + assert(serialHandle); + assert(writeHandle); + assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t)); + + handle = (serial_manager_handle_t *)serialHandle; + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); + + handle->openedWriteHandleCount++; + + serialWriteHandle->serialManagerHandle = handle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG; +#endif + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle) +{ + serial_manager_handle_t *handle; + serial_manager_write_handle_t *serialWriteHandle; + + assert(writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + handle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle; + + assert(handle); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + (void)SerialManager_CancelWriting(writeHandle); +#endif + + handle->openedWriteHandleCount--; + (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle) +{ + serial_manager_handle_t *handle; + serial_manager_read_handle_t *serialReadHandle; + + assert(serialHandle); + assert(readHandle); + assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t)); + + handle = (serial_manager_handle_t *)serialHandle; + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + if (handle->openedReadHandleHead != NULL) + { + return kStatus_SerialManager_Busy; + } + (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); + + handle->openedReadHandleHead = serialReadHandle; + + serialReadHandle->serialManagerHandle = handle; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialReadHandle->tag = SERIAL_MANAGER_READ_TAG; +#endif + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle) +{ + serial_manager_handle_t *handle; + serial_manager_read_handle_t *serialReadHandle; + + assert(readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + handle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle; + + assert(handle); +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + (void)SerialManager_CancelReading(readHandle); +#endif + + handle->openedReadHandleHead = NULL; + (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length) +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking); +#else + return SerialManager_Write(writeHandle, buffer, length); +#endif +} + +serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL); +#else + return SerialManager_Read(readHandle, buffer, length); +#endif +} + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length) +{ + return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking); +} + +serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) +{ + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL); +} + +serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle) +{ + serial_manager_write_handle_t *serialWriteHandle; + uint32_t primask; + uint8_t isNotUsed = 0; + + assert(writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + assert(serialWriteHandle->serialManagerHandle); + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + + if ((serialWriteHandle->transfer.buffer != NULL) && + (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode)) + { + return kStatus_SerialManager_Error; + } + + primask = DisableGlobalIRQ(); + if (serialWriteHandle != (serial_manager_write_handle_t *)(void *)LIST_GetHead( + &serialWriteHandle->serialManagerHandle->runningWriteHandleHead)) + { + (void)LIST_RemoveElement(&serialWriteHandle->link); + isNotUsed = 1; + } + EnableGlobalIRQ(primask); + + if (isNotUsed != 0U) + { + serialWriteHandle->transfer.soFar = 0; + serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled; + + SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle); +#if defined(OSA_USED) + +#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) + serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task; + serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam = serialWriteHandle->serialManagerHandle; + COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg); +#else + (void)OSA_EventSet((osa_event_handle_t)serialWriteHandle->serialManagerHandle->event, SERIAL_EVENT_DATA_SENT); +#endif + +#else + SerialManager_Task(serialWriteHandle->serialManagerHandle); +#endif + } + else + { + switch (serialWriteHandle->serialManagerHandle->type) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + case kSerialPort_Uart: + (void)Serial_UartCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + case kSerialPort_UsbCdc: + (void)Serial_UsbCdcCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + case kSerialPort_Swo: + (void)Serial_SwoCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + case kSerialPort_UsbCdcVirtual: + Serial_UsbCdcVirtualCancelWrite( + (void)Serial_SwoCancelWrite( + ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); + break; +#endif + default: + /*MISRA rule 16.4*/ + break; + } + } + + (void)SerialManager_StartWriting(serialWriteHandle->serialManagerHandle); + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle) +{ + serial_manager_read_handle_t *serialReadHandle; + serial_manager_callback_message_t msg; + uint8_t *buffer; + uint32_t primask; + + assert(readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + + if ((serialReadHandle->transfer.buffer != NULL) && + (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode)) + { + return kStatus_SerialManager_Error; + } + + primask = DisableGlobalIRQ(); + buffer = serialReadHandle->transfer.buffer; + serialReadHandle->transfer.buffer = NULL; + serialReadHandle->transfer.length = 0; + msg.buffer = buffer; + msg.length = serialReadHandle->transfer.soFar; + EnableGlobalIRQ(primask); + + if (buffer != NULL) + { + if (serialReadHandle->callback != NULL) + { + serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Canceled); + } + } + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + uint32_t *receivedLength) +{ + assert(receivedLength); + + return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength); +} + +serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_manager_write_handle_t *serialWriteHandle; + + assert(writeHandle); + + serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; + + assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); + + serialWriteHandle->callbackParam = callbackParam; + serialWriteHandle->callback = callback; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_manager_read_handle_t *serialReadHandle; + + assert(readHandle); + + serialReadHandle = (serial_manager_read_handle_t *)readHandle; + + assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); + + serialReadHandle->callbackParam = callbackParam; + serialReadHandle->callback = callback; + + return kStatus_SerialManager_Success; +} +#endif + +serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle) +{ + assert(serialHandle); + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle) +{ + assert(serialHandle); + + return kStatus_SerialManager_Success; +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_manager.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_manager.h new file mode 100644 index 000000000..14af2c07c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_manager.h @@ -0,0 +1,548 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_MANAGER_H__ +#define __SERIAL_MANAGER_H__ + +/*! + * @addtogroup serialmanager + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */ +#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U) +#else +#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE +#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U) +#endif +#endif + +/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_UART +#define SERIAL_PORT_TYPE_UART (1U) +#endif + +/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_USBCDC +#define SERIAL_PORT_TYPE_USBCDC (0U) +#endif + +/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_SWO +#define SERIAL_PORT_TYPE_SWO (0U) +#endif + +/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */ +#ifndef SERIAL_PORT_TYPE_USBCDC_VIRTUAL +#define SERIAL_PORT_TYPE_USBCDC_VIRTUAL (0U) +#endif + +/*! @brief Set serial manager write handle size */ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U) +#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U) +#else +#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U) +#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U) +#endif + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +#include "serial_port_uart.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#error The serial manager blocking mode cannot be supported for USB CDC. +#endif + +#include "serial_port_usb.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) +#include "serial_port_swo.h" +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#error The serial manager blocking mode cannot be supported for USB CDC. +#endif + +#include "serial_port_usb_virtual.h" +#endif + +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + +#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + +#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + +#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + +#if (SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) +#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP +#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE +#endif + +#endif + +/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */ +#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U))) +#else +#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_USBCDC_VIRTUAL should not be cleared at same time. +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U) +#else +#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U) +#endif + +#define SERIAL_MANAGER_USE_COMMON_TASK (1U) +#define SERIAL_MANAGER_TASK_PRIORITY (2U) +#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U) + +typedef void *serial_handle_t; +typedef void *serial_write_handle_t; +typedef void *serial_read_handle_t; + +/*! @brief serial port type*/ +typedef enum _serial_port_type +{ + kSerialPort_Uart = 1U, /*!< Serial port UART */ + kSerialPort_UsbCdc, /*!< Serial port USB CDC */ + kSerialPort_Swo, /*!< Serial port SWO */ + kSerialPort_UsbCdcVirtual, /*!< Serial port USB CDC Virtual */ +} serial_port_type_t; + +/*! @brief serial manager config structure*/ +typedef struct _serial_manager_config +{ + uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware. + Besides, the memory space cannot be free during the lifetime of the serial + manager module. */ + uint32_t ringBufferSize; /*!< The size of the ring buffer */ + serial_port_type_t type; /*!< Serial port type */ + void *portConfig; /*!< Serial port configuration */ +} serial_manager_config_t; + +/*! @brief serial manager error code*/ +typedef enum _serial_manager_status +{ + kStatus_SerialManager_Success = kStatus_Success, /*!< Success */ + kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */ + kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */ + kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */ + kStatus_SerialManager_Canceled = + MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */ + kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */ + kStatus_SerialManager_RingBufferOverflow = + MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */ +} serial_manager_status_t; + +/*! @brief Callback message structure */ +typedef struct _serial_manager_callback_message +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ +} serial_manager_callback_message_t; + +/*! @brief callback function */ +typedef void (*serial_manager_callback_t)(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status); + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure. + * + * This function configures the Serial Manager module with user-defined settings. The user can configure the + * configuration + * structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE + * allocated by the caller. + * The Serial Manager module supports two types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc) and USB + * CDC. + * Please refer to #serial_port_type_t for serial port setting. These two types can be set by using + * #serial_manager_config_t. + * + * Example below shows how to use this API to configure the Serial Manager. + * For UART, + * @code + * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U) + * static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE]; + * static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0]; + * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE]; + * + * serial_manager_config_t config; + * serial_port_uart_config_t uartConfig; + * config.type = kSerialPort_Uart; + * config.ringBuffer = &s_ringBuffer[0]; + * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE; + * uartConfig.instance = 0; + * uartConfig.clockRate = 24000000; + * uartConfig.baudRate = 115200; + * uartConfig.parityMode = kSerialManager_UartParityDisabled; + * uartConfig.stopBitCount = kSerialManager_UartOneStopBit; + * uartConfig.enableRx = 1; + * uartConfig.enableTx = 1; + * config.portConfig = &uartConfig; + * SerialManager_Init(s_serialHandle, &config); + * @endcode + * For USB CDC, + * @code + * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U) + * static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE]; + * static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0]; + * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE]; + * + * serial_manager_config_t config; + * serial_port_usb_cdc_config_t usbCdcConfig; + * config.type = kSerialPort_UsbCdc; + * config.ringBuffer = &s_ringBuffer[0]; + * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE; + * usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0; + * config.portConfig = &usbCdcConfig; + * SerialManager_Init(s_serialHandle, &config); + * @endcode + * + * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller. + * @param config Pointer to user-defined configuration structure. + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed. + */ +serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config); + +/*! + * @brief De-initializes the serial manager module instance. + * + * This function de-initializes the serial manager module instance. If the opened writing or + * reading handle is not closed, the function will return kStatus_SerialManager_Busy. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed. + * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed. + */ +serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle); + +/*! + * @brief Opens a writing handle for the serial manager module. + * + * This function Opens a writing handle for the serial manager module. If the serial manager needs to + * be used in different tasks, the task should open a dedicated write handle for itself by calling + * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing + * handle at the same time, multiple writing handles need to be opened when the multiple transmission + * is needed for a task. + * + * @param serialHandle The serial manager module handle pointer. + * @param writeHandle The serial manager module writing handle pointer. + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_HandleConflict The writing handle was opened. + * @retval kStatus_SerialManager_Success The writing handle is opened. + * + * Example below shows how to use this API to write data. + * For task 1, + * @code + * static uint8_t s_serialWriteHandleBuffer1[SERIAL_MANAGER_WRITE_HANDLE_SIZE]; + * static serial_write_handle_t s_serialWriteHandle1 = &s_serialWriteHandleBuffer1[0]; + * static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n"; + * SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1); + * SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1); + * SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1); + * @endcode + * For task 2, + * @code + * static uint8_t s_serialWriteHandleBuffer2[SERIAL_MANAGER_WRITE_HANDLE_SIZE]; + * static serial_write_handle_t s_serialWriteHandle2 = &s_serialWriteHandleBuffer2[0]; + * static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n"; + * SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2); + * SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2); + * SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1); + * @endcode + */ +serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle); + +/*! + * @brief Closes a writing handle for the serial manager module. + * + * This function Closes a writing handle for the serial manager module. + * + * @param writeHandle The serial manager module writing handle pointer. + * @retval kStatus_SerialManager_Success The writing handle is closed. + */ +serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle); + +/*! + * @brief Opens a reading handle for the serial manager module. + * + * This function Opens a reading handle for the serial manager module. The reading handle can not be + * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when + * the previous reading handle is not closed. And There can only be one buffer for receiving for the + * reading handle at the same time. + * + * @param serialHandle The serial manager module handle pointer. + * @param readHandle The serial manager module reading handle pointer. + * @retval kStatus_SerialManager_Error An error occurred. + * @retval kStatus_SerialManager_Success The reading handle is opened. + * @retval kStatus_SerialManager_Busy Previous reading handle is not closed. + * + * Example below shows how to use this API to read data. + * @code + * static uint8_t s_serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE]; + * static serial_read_handle_t s_serialReadHandle = &s_serialReadHandleBuffer[0]; + * SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle); + * static uint8_t s_nonBlockingBuffer[64]; + * SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle); + * SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer)); + * @endcode + */ +serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle); + +/*! + * @brief Closes a reading for the serial manager module. + * + * This function Closes a reading for the serial manager module. + * + * @param readHandle The serial manager module reading handle pointer. + * @retval kStatus_SerialManager_Success The reading handle is closed. + */ +serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle); + +/*! + * @brief Transmits data with the blocking mode. + * + * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty. + * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for transmission for the writing handle at the same time. + * + * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking + * cannot be used at the same time. + * And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function. + * + * @param writeHandle The serial manager module handle pointer. + * @param buffer Start address of the data to write. + * @param length Length of the data to write. + * @retval kStatus_SerialManager_Success Successfully sent all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Reads data with the blocking mode. + * + * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full. + * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking + * cannot be used at the same time. + * And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +/*! + * @brief Transmits data with the non-blocking mode. + * + * This is a non-blocking function, which returns directly without waiting for all data to be sent. + * When all data is sent, the module notifies the upper layer through a TX callback function and passes + * the status parameter @ref kStatus_SerialManager_Success. + * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for transmission for the writing handle at the same time. + * + * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking + * cannot be used at the same time. And, the TX callback is mandatory before the function could be used. + * + * @param writeHandle The serial manager module handle pointer. + * @param buffer Start address of the data to write. + * @param length Length of the data to write. + * @retval kStatus_SerialManager_Success Successfully sent all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Reads data with the non-blocking mode. + * + * This is a non-blocking function, which returns directly without waiting for all data to be received. + * When all data is received, the module driver notifies the upper layer + * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success. + * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking + * cannot be used at the same time. And, the RX callback is mandatory before the function could be used. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Tries to read data. + * + * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be + * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length. + * After the data is copied, the actual data length is passed by the parameter length. + * And There can only one buffer for receiving for the reading handle at the same time. + * + * @param readHandle The serial manager module handle pointer. + * @param buffer Start address of the data to store the received data. + * @param length The length of the data to be received. + * @param receivedLength Length received from the ring buffer directly. + * @retval kStatus_SerialManager_Success Successfully received all data. + * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle, + uint8_t *buffer, + uint32_t length, + uint32_t *receivedLength); + +/*! + * @brief Cancels unfinished send transmission. + * + * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer + * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled. + * + * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of + * the function #SerialManager_WriteBlocking. + * + * @param writeHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Get successfully abort the sending. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle); + +/*! + * @brief Cancels unfinished receive transmission. + * + * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper + * layer + * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled. + * + * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of + * the function #SerialManager_ReadBlocking. + * + * @param readHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Get successfully abort the receiving. + * @retval kStatus_SerialManager_Error An error occurred. + */ +serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle); + +/*! + * @brief Installs a TX callback and callback parameter. + * + * This function is used to install the TX callback and callback parameter for the serial manager module. + * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param writeHandle The serial manager module handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_SerialManager_Success Successfully install the callback. + */ +serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle, + serial_manager_callback_t callback, + void *callbackParam); + +/*! + * @brief Installs a RX callback and callback parameter. + * + * This function is used to install the RX callback and callback parameter for the serial manager module. + * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param readHandle The serial manager module handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_SerialManager_Success Successfully install the callback. + */ +serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle, + serial_manager_callback_t callback, + void *callbackParam); + +#endif + +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Successful operation. + */ +serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @param serialHandle The serial manager module handle pointer. + * @retval kStatus_SerialManager_Success Successful operation. + */ +serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle); + +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* __SERIAL_MANAGER_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_port_internal.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_port_internal.h new file mode 100644 index 000000000..0534363a0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_port_internal.h @@ -0,0 +1,98 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_PORT_INTERNAL_H__ +#define __SERIAL_PORT_INTERNAL_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig); +serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_UartIsrFunction(serial_handle_t serialHandle); +#endif + +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) +serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle); +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) +serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +#endif +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_SwoIsrFunction(serial_handle_t serialHandle); +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) +serial_manager_status_t Serial_UsbCdcVirtualInit(serial_handle_t serialHandle, void *config); +serial_manager_status_t Serial_UsbCdcVirtualDeinit(serial_handle_t serialHandle); +serial_manager_status_t Serial_UsbCdcVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UsbCdcVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); +serial_manager_status_t Serial_UsbCdcVirtualCancelWrite(serial_handle_t serialHandle); +serial_manager_status_t Serial_UsbCdcVirtualInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +serial_manager_status_t Serial_UsbCdcVirtualInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam); +void Serial_UsbCdcVirtualIsrFunction(serial_handle_t serialHandle); +#endif + +#if defined(__cplusplus) +} +#endif + +#endif /* __SERIAL_PORT_INTERNAL_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_port_uart.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_port_uart.c new file mode 100644 index 000000000..30ee298de --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_port_uart.c @@ -0,0 +1,371 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "serial_manager.h" +#include "serial_port_internal.h" + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +#include "uart.h" + +#include "serial_port_uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#endif +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U + +typedef struct _serial_uart_send_state +{ + serial_manager_callback_t callback; + void *callbackParam; + uint8_t *buffer; + uint32_t length; + volatile uint8_t busy; +} serial_uart_send_state_t; + +typedef struct _serial_uart_recv_state +{ + serial_manager_callback_t callback; + void *callbackParam; + volatile uint8_t busy; + uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH]; +} serial_uart_recv_state_t; +#endif + +typedef struct _serial_uart_state +{ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serial_uart_send_state_t tx; + serial_uart_recv_state_t rx; +#endif + uint8_t usartHandleBuffer[HAL_UART_HANDLE_SIZE]; +} serial_uart_state_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +/* UART user callback */ +static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData) +{ + serial_uart_state_t *serialUartHandle; + serial_manager_callback_message_t msg; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + hal_uart_transfer_t transfer; +#endif + + if (NULL == userData) + { + return; + } + + serialUartHandle = (serial_uart_state_t *)userData; + + if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status) + { + if ((NULL != serialUartHandle->rx.callback)) + { + msg.buffer = &serialUartHandle->rx.readBuffer[0]; + msg.length = sizeof(serialUartHandle->rx.readBuffer); + serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &msg, kStatus_SerialManager_Success); + } +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + transfer.data = &serialUartHandle->rx.readBuffer[0]; + transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer); + if (kStatus_HAL_UartSuccess == + HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer)) +#else + if ((hal_uart_status_t)kStatus_HAL_UartSuccess == + HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer))) +#endif + { + serialUartHandle->rx.busy = 1U; + } + else + { + serialUartHandle->rx.busy = 0U; + } + } + else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status) + { + if (serialUartHandle->tx.busy != 0U) + { + serialUartHandle->tx.busy = 0U; + if ((NULL != serialUartHandle->tx.callback)) + { + msg.buffer = serialUartHandle->tx.buffer; + msg.length = serialUartHandle->tx.length; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Success); + } + } + } + else + { + } +} +#endif + +serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig) +{ + serial_uart_state_t *serialUartHandle; + serial_port_uart_config_t *uartConfig; + hal_uart_config_t config; +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + hal_uart_transfer_t transfer; +#endif +#endif + + assert(serialConfig); + assert(serialHandle); + assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t)); + + uartConfig = (serial_port_uart_config_t *)serialConfig; + serialUartHandle = (serial_uart_state_t *)serialHandle; + + config.baudRate_Bps = uartConfig->baudRate; + config.parityMode = (hal_uart_parity_mode_t)uartConfig->parityMode; + config.stopBitCount = (hal_uart_stop_bit_count_t)uartConfig->stopBitCount; + config.enableRx = uartConfig->enableRx; + config.enableTx = uartConfig->enableTx; + config.srcClock_Hz = uartConfig->clockRate; + config.instance = uartConfig->instance; + + if (kStatus_HAL_UartSuccess != HAL_UartInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &config)) + { + return kStatus_SerialManager_Error; + } + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + if (kStatus_HAL_UartSuccess != + HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + Serial_UartCallback, serialUartHandle)) +#else + if (kStatus_HAL_UartSuccess != HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + Serial_UartCallback, serialUartHandle)) +#endif + { + return kStatus_SerialManager_Error; + } + + if (uartConfig->enableRx != 0U) + { + serialUartHandle->rx.busy = 1U; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + transfer.data = &serialUartHandle->rx.readBuffer[0]; + transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer); + if (kStatus_HAL_UartSuccess != + HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer)) +#else + if (kStatus_HAL_UartSuccess != + HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer))) +#endif + { + serialUartHandle->rx.busy = 0U; + return kStatus_SerialManager_Error; + } + } +#endif + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#else + (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#endif +#endif + (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + serialUartHandle->tx.busy = 0U; + serialUartHandle->rx.busy = 0U; +#endif + + return kStatus_SerialManager_Success; +} + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) + +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + hal_uart_transfer_t transfer; +#endif + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + if (serialUartHandle->tx.busy != 0U) + { + return kStatus_SerialManager_Busy; + } + serialUartHandle->tx.busy = 1U; + + serialUartHandle->tx.buffer = buffer; + serialUartHandle->tx.length = length; + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + transfer.data = buffer; + transfer.dataSize = length; + if (kStatus_HAL_UartSuccess != + HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer)) +#else + if (kStatus_HAL_UartSuccess != + HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length)) +#endif + { + serialUartHandle->tx.busy = 0U; + return kStatus_SerialManager_Error; + } + return kStatus_SerialManager_Success; +} + +#else + +serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), + buffer, length); +} + +serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + assert(buffer); + assert(length); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + return (serial_manager_status_t)HAL_UartReceiveBlocking( + ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); +} + +#endif + +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + serial_manager_callback_message_t msg; + uint32_t primask; + uint8_t isBusy = 0U; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + primask = DisableGlobalIRQ(); + isBusy = serialUartHandle->tx.busy; + serialUartHandle->tx.busy = 0U; + EnableGlobalIRQ(primask); + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#else + (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +#endif + if (isBusy != 0U) + { + if ((NULL != serialUartHandle->tx.callback)) + { + msg.buffer = serialUartHandle->tx.buffer; + msg.length = serialUartHandle->tx.length; + serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Canceled); + } + } + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + serialUartHandle->tx.callback = callback; + serialUartHandle->tx.callbackParam = callbackParam; + + return kStatus_SerialManager_Success; +} + +serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle, + serial_manager_callback_t callback, + void *callbackParam) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + serialUartHandle->rx.callback = callback; + serialUartHandle->rx.callbackParam = callbackParam; + + return kStatus_SerialManager_Success; +} + +void Serial_UartIsrFunction(serial_handle_t serialHandle) +{ + serial_uart_state_t *serialUartHandle; + + assert(serialHandle); + + serialUartHandle = (serial_uart_state_t *)serialHandle; + + HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_port_uart.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_port_uart.h new file mode 100644 index 000000000..24a717009 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/serial_manager/serial_port_uart.h @@ -0,0 +1,55 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SERIAL_PORT_UART_H__ +#define __SERIAL_PORT_UART_H__ + +/*! + * @addtogroup serial_port_uart + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief serial port uart handle size*/ +#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) +#define SERIAL_PORT_UART_HANDLE_SIZE (166U) +#else +#define SERIAL_PORT_UART_HANDLE_SIZE (4U) +#endif + +/*! @brief serial port uart parity mode*/ +typedef enum _serial_port_uart_parity_mode +{ + kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */ + kSerialManager_UartParityEven = 0x1U, /*!< Parity even enabled */ + kSerialManager_UartParityOdd = 0x2U, /*!< Parity odd enabled */ +} serial_port_uart_parity_mode_t; + +/*! @brief serial port uart stop bit count*/ +typedef enum _serial_port_uart_stop_bit_count +{ + kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */ + kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */ +} serial_port_uart_stop_bit_count_t; + +/*! @brief serial port uart config struct*/ +typedef struct _serial_port_uart_config +{ + uint32_t clockRate; /*!< clock rate */ + uint32_t baudRate; /*!< baud rate */ + serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information + please refer to the SOC corresponding RM. */ + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ +} serial_port_uart_config_t; +/*! @} */ +#endif /* __SERIAL_PORT_UART_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/uart/uart.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/uart/uart.h new file mode 100644 index 000000000..8fe377790 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/uart/uart.h @@ -0,0 +1,475 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __HAL_UART_ADAPTER_H__ +#define __HAL_UART_ADAPTER_H__ + +#if defined(FSL_RTOS_FREE_RTOS) +#include "FreeRTOS.h" +#endif + +/*! + * @addtogroup UART_Adapter + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define UART_ADAPTER_NON_BLOCKING_MODE (1U) +#else +#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE +#define UART_ADAPTER_NON_BLOCKING_MODE (0U) +#else +#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE +#endif +#endif + +#if defined(__GIC_PRIO_BITS) +#define HAL_UART_ISR_PRIORITY (25U) +#else +#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) +#else +/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc. + * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum + * priority is 3 (2^2 - 1). So, the default value is 3. + */ +#define HAL_UART_ISR_PRIORITY (3U) +#endif +#endif + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#define HAL_UART_HANDLE_SIZE (90U) +#else +#define HAL_UART_HANDLE_SIZE (4U) +#endif + +/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */ +#define HAL_UART_TRANSFER_MODE (0U) + +typedef void *hal_uart_handle_t; + +/*! @brief UART status */ +typedef enum _hal_uart_status +{ + kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */ + kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */ + kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */ + kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */ + kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */ + kStatus_HAL_UartBaudrateNotSupport = + MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */ + kStatus_HAL_UartProtocolError = MAKE_STATUS( + kStatusGroup_HAL_UART, + 6), /*!< Error occurs for Noise, Framing, Parity, etc. + For transactional transfer, The up layer needs to abort the transfer and then starts again */ + kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */ +} hal_uart_status_t; + +/*! @brief UART parity mode. */ +typedef enum _hal_uart_parity_mode +{ + kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */ + kHAL_UartParityEven = 0x1U, /*!< Parity even enabled */ + kHAL_UartParityOdd = 0x2U, /*!< Parity odd enabled */ +} hal_uart_parity_mode_t; + +/*! @brief UART stop bit count. */ +typedef enum _hal_uart_stop_bit_count +{ + kHAL_UartOneStopBit = 0U, /*!< One stop bit */ + kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */ +} hal_uart_stop_bit_count_t; + +/*! @brief UART configuration structure. */ +typedef struct _hal_uart_config +{ + uint32_t srcClock_Hz; /*!< Source clock */ + uint32_t baudRate_Bps; /*!< Baud rate */ + hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + uint8_t enableRx; /*!< Enable RX */ + uint8_t enableTx; /*!< Enable TX */ + uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the + SOC corresponding RM. + Invalid instance value will cause initialization failure. */ +} hal_uart_config_t; + +/*! @brief UART transfer callback function. */ +typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam); + +/*! @brief UART transfer structure. */ +typedef struct _hal_uart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} hal_uart_transfer_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a UART instance with the UART handle and the user configuration structure. + * + * This function configures the UART module with user-defined settings. The user can configure the configuration + * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by + * the caller. Example below shows how to use this API to configure the UART. + * @code + * uint8_t g_UartHandleBuffer[HAL_UART_HANDLE_SIZE]; + * hal_uart_handle_t g_UartHandle = &g_UartHandleBuffer[0]; + * hal_uart_config_t config; + * config.srcClock_Hz = 48000000; + * config.baudRate_Bps = 115200U; + * config.parityMode = kHAL_UartParityDisabled; + * config.stopBitCount = kHAL_UartOneStopBit; + * config.enableRx = 1; + * config.enableTx = 1; + * config.instance = 0; + * HAL_UartInit(g_UartHandle, &config); + * @endcode + * + * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller. + * @param config Pointer to user-defined configuration structure. + * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_HAL_UartSuccess UART initialization succeed + */ +hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config); + +/*! + * @brief Deinitializes a UART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the UART clock. + * + * @param handle UART handle pointer. + * @retval kStatus_HAL_UartSuccess UART de-initialization succeed + */ +hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle); + +/*! @}*/ + +/*! + * @name Blocking bus Operations + * @{ + */ + +/*! + * @brief Reads RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data, and reads data from the RX register. + * + * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking + * cannot be used at the same time. + * And, the function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function. + * + * @param handle UART handle pointer. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_HAL_UartError An error occurred while receiving data. + * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data. + * @retval kStatus_HAL_UartSuccess Successfully received all data. + */ +hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking + * cannot be used at the same time. + * And, the function #HAL_UartTransferAbortSend cannot be used to abort the transmission of this function. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully sent all data. + */ +hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length); + +/*! @}*/ + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +/*! + * @name Transactional + * @note The transactional API and the functional API cannot be used at the same time. The macro + * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the + * functional API with non-blocking mode will be used. Otherwise, transactional API will be used. + * @{ + */ + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for UART module. + * When any status of the UART changed, the driver will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param handle UART handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_HAL_UartSuccess Successfully install the callback. + */ +hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be received. + * The receive request is saved by the UART driver. + * When the new data arrives, the receive request is serviced first. + * When all data is received, the UART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * + * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param transfer UART transfer structure, see #hal_uart_transfer_t. + * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue. + * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * + * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param transfer UART transfer structure. See #hal_uart_transfer_t. + * @retval kStatus_HAL_UartSuccess Successfully start the data transmission. + * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of + * the function #HAL_UartReceiveBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the receiving. + */ +hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle); + +/*! + * @brief Aborts the interrupt-driven data sending. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of + * the function #HAL_UartSendBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the sending. + */ +hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle); + +/*! @}*/ + +#else + +/*! + * @name Functional API with non-blocking mode. + * @note The functional API and the transactional API cannot be used at the same time. The macro + * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the + * functional API with non-blocking mode will be used. Otherwise, transactional API will be used. + * @{ + */ + +/*! + * @brief Installs a callback and callback parameter. + * + * This function is used to install the callback and callback parameter for UART module. + * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback + * function. And the status is also passed as status parameter when the callback is called. + * + * @param handle UART handle pointer. + * @param callback The callback function. + * @param callbackParam The parameter of the callback function. + * @retval kStatus_HAL_UartSuccess Successfully install the callback. + */ +hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be received. + * The receive request is saved by the UART adapter. + * When the new data arrives, the receive request is serviced first. + * When all data is received, the UART adapter notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. + * + * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue. + * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the ISR, the UART driver calls the callback + * function and passes the @ref kStatus_UART_TxIdle as status parameter. + * + * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking + * cannot be used at the same time. + * + * @param handle UART handle pointer. + * @param data Start address of the data to write. + * @param length Size of the data to write. + * @retval kStatus_HAL_UartSuccess Successfully start the data transmission. + * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet. + * @retval kStatus_HAL_UartError An error occurred. + */ +hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); + +/*! + * @brief Gets the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param handle UART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount); + +/*! + * @brief Gets the number of bytes written to the UART TX register. + * + * This function gets the number of bytes written to the UART TX + * register by using the interrupt method. + * + * @param handle UART handle pointer. + * @param count Send bytes count. + * @retval kStatus_HAL_UartError An error occurred. + * @retval kStatus_Success Get successfully through the parameter \p count. + */ +hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know + * how many bytes are not received yet. + * + * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of + * the function #HAL_UartReceiveBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the receiving. + */ +hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle); + +/*! + * @brief Aborts the interrupt-driven data sending. + * + * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out + * how many bytes are not sent out. + * + * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of + * the function #HAL_UartSendBlocking. + * + * @param handle UART handle pointer. + * @retval kStatus_Success Get successfully abort the sending. + */ +hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle); + +/*! @}*/ + +#endif +#endif + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +/*! + * @brief UART IRQ handle function. + * + * This function handles the UART transmit and receive IRQ request. + * + * @param handle UART handle pointer. + */ +void HAL_UartIsrFunction(hal_uart_handle_t handle); +#endif + +#if defined(__cplusplus) +} +#endif +/*! @}*/ +#endif /* __HAL_UART_ADAPTER_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/uart/usart_adapter.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/uart/usart_adapter.c new file mode 100644 index 000000000..a53fa0e32 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/component/uart/usart_adapter.c @@ -0,0 +1,629 @@ +/* + * Copyright 2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_usart.h" +#include "fsl_flexcomm.h" + +#include "uart.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#endif +#endif + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) +/*! @brief uart RX state structure. */ +typedef struct _hal_uart_receive_state +{ + volatile uint8_t *buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; +} hal_uart_receive_state_t; + +/*! @brief uart TX state structure. */ +typedef struct _hal_uart_send_state +{ + volatile uint8_t *buffer; + volatile uint32_t bufferLength; + volatile uint32_t bufferSofar; +} hal_uart_send_state_t; +#endif +/*! @brief uart state structure. */ +typedef struct _hal_uart_state +{ +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + hal_uart_transfer_callback_t callback; + void *callbackParam; +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + usart_handle_t hardwareHandle; +#endif + hal_uart_receive_state_t rx; + hal_uart_send_state_t tx; +#endif + uint8_t instance; +} hal_uart_state_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +/* Array of USART IRQ number. */ +static const IRQn_Type s_UsartIRQ[] = USART_IRQS; +#endif + +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +static hal_uart_status_t HAL_UartGetStatus(status_t status) +{ + hal_uart_status_t uartStatus = kStatus_HAL_UartError; + switch (status) + { + case kStatus_Success: + uartStatus = kStatus_HAL_UartSuccess; + break; + case kStatus_USART_TxBusy: + uartStatus = kStatus_HAL_UartTxBusy; + break; + case kStatus_USART_RxBusy: + uartStatus = kStatus_HAL_UartRxBusy; + break; + case kStatus_USART_TxIdle: + uartStatus = kStatus_HAL_UartTxIdle; + break; + case kStatus_USART_RxIdle: + uartStatus = kStatus_HAL_UartRxIdle; + break; + case kStatus_USART_BaudrateNotSupport: + uartStatus = kStatus_HAL_UartBaudrateNotSupport; + break; + case kStatus_USART_NoiseError: + case kStatus_USART_FramingError: + case kStatus_USART_ParityError: + uartStatus = kStatus_HAL_UartProtocolError; + break; + default: + break; + } + return uartStatus; +} +#else +static hal_uart_status_t HAL_UartGetStatus(status_t status) +{ + if (kStatus_Success == status) + { + return kStatus_HAL_UartSuccess; + } + else + { + return kStatus_HAL_UartError; + } +} +#endif + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) +static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam) +{ + hal_uart_state_t *uartHandle; + hal_uart_status_t uartStatus = HAL_UartGetStatus(status); + assert(callbackParam); + + uartHandle = (hal_uart_state_t *)callbackParam; + + if (kStatus_HAL_UartProtocolError == uartStatus) + { + if (uartHandle->hardwareHandle.rxDataSize) + { + uartStatus = kStatus_HAL_UartError; + } + } + + if (uartHandle->callback) + { + uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam); + } +} + +#else + +static void HAL_UartInterruptHandle(USART_Type *base, void *handle) +{ + hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle; + uint32_t status; + uint8_t instance; + + if (NULL == uartHandle) + { + return; + } + instance = uartHandle->instance; + + status = USART_GetStatusFlags(s_UsartAdapterBase[instance]); + + /* Receive data register full */ + if ((USART_FIFOSTAT_RXNOTEMPTY_MASK & status) && + (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK)) + { + if (uartHandle->rx.buffer) + { + uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]); + if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength) + { + USART_DisableInterrupts(s_UsartAdapterBase[instance], + USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK); + uartHandle->rx.buffer = NULL; + if (uartHandle->callback) + { + uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam); + } + } + } + } + + /* Send data register empty and the interrupt is enabled. */ + if ((USART_FIFOSTAT_TXNOTFULL_MASK & status) && + (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK)) + { + if (uartHandle->tx.buffer) + { + USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]); + if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength) + { + USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK); + uartHandle->tx.buffer = NULL; + if (uartHandle->callback) + { + uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam); + } + } + } + } + +#if 1 + USART_ClearStatusFlags(s_UsartAdapterBase[instance], status); +#endif +} +#endif + +#endif + +hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config) +{ + hal_uart_state_t *uartHandle; + usart_config_t usartConfig; + status_t status; + assert(handle); + assert(config); + assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *))); + assert(s_UsartAdapterBase[config->instance]); + + if (HAL_UART_HANDLE_SIZE < sizeof(hal_uart_state_t)) + { + return kStatus_HAL_UartError; + } + + USART_GetDefaultConfig(&usartConfig); + usartConfig.baudRate_Bps = config->baudRate_Bps; + + if (kHAL_UartParityEven == config->parityMode) + { + usartConfig.parityMode = kUSART_ParityEven; + } + else if (kHAL_UartParityOdd == config->parityMode) + { + usartConfig.parityMode = kUSART_ParityOdd; + } + else + { + usartConfig.parityMode = kUSART_ParityDisabled; + } + + if (kHAL_UartTwoStopBit == config->stopBitCount) + { + usartConfig.stopBitCount = kUSART_TwoStopBit; + } + else + { + usartConfig.stopBitCount = kUSART_OneStopBit; + } + usartConfig.enableRx = config->enableRx; + usartConfig.enableTx = config->enableTx; + usartConfig.txWatermark = kUSART_TxFifo0; + usartConfig.rxWatermark = kUSART_RxFifo1; + + status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz); + + if (kStatus_Success != status) + { + return HAL_UartGetStatus(status); + } + + uartHandle = (hal_uart_state_t *)handle; + uartHandle->instance = config->instance; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle, + (usart_transfer_callback_t)HAL_UartCallback, handle); +#else + /* Enable interrupt in NVIC. */ + FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], (flexcomm_irq_handler_t)HAL_UartInterruptHandle, + handle); + NVIC_SetPriority((IRQn_Type)s_UsartIRQ[config->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_UsartIRQ[config->instance]); +#endif + +#endif + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + + uartHandle = (hal_uart_state_t *)handle; + + USART_Deinit(s_UsartAdapterBase[uartHandle->instance]); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(data); + assert(length); + + uartHandle = (hal_uart_state_t *)handle; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + if (uartHandle->rx.buffer) + { + return kStatus_HAL_UartRxBusy; + } +#endif + + status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(data); + assert(length); + + uartHandle = (hal_uart_state_t *)handle; + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + if (uartHandle->tx.buffer) + { + return kStatus_HAL_UartTxBusy; + } +#endif + + USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length); + + return kStatus_HAL_UartSuccess; +} + +#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + assert(HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + uartHandle->callbackParam = callbackParam; + uartHandle->callback = callback; + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(transfer); + assert(HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, + (usart_transfer_t *)transfer, NULL); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(transfer); + assert(HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, + (usart_transfer_t *)transfer); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(count); + assert(HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = + USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count) +{ + hal_uart_state_t *uartHandle; + status_t status; + assert(handle); + assert(count); + assert(HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); + + return HAL_UartGetStatus(status); +} + +hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); + + return kStatus_HAL_UartSuccess; +} + +#else + +/* None transactional API with non-blocking mode. */ +hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, + hal_uart_transfer_callback_t callback, + void *callbackParam) +{ + hal_uart_state_t *uartHandle; + + assert(handle); + assert(!HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + uartHandle->callbackParam = callbackParam; + uartHandle->callback = callback; + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(data); + assert(length); + assert(!HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (uartHandle->rx.buffer) + { + return kStatus_HAL_UartRxBusy; + } + + uartHandle->rx.bufferLength = length; + uartHandle->rx.bufferSofar = 0; + uartHandle->rx.buffer = data; + USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK); + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(data); + assert(length); + assert(!HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (uartHandle->tx.buffer) + { + return kStatus_HAL_UartTxBusy; + } + uartHandle->tx.bufferLength = length; + uartHandle->tx.bufferSofar = 0; + uartHandle->tx.buffer = (volatile uint8_t *)data; + USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK); + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(reCount); + assert(!HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (uartHandle->rx.buffer) + { + *reCount = uartHandle->rx.bufferSofar; + return kStatus_HAL_UartSuccess; + } + return kStatus_HAL_UartError; +} + +hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(seCount); + assert(!HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (uartHandle->tx.buffer) + { + *seCount = uartHandle->tx.bufferSofar; + return kStatus_HAL_UartSuccess; + } + return kStatus_HAL_UartError; +} + +hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(!HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (uartHandle->rx.buffer) + { + USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], + USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK); + uartHandle->rx.buffer = NULL; + } + + return kStatus_HAL_UartSuccess; +} + +hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(!HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + + if (uartHandle->tx.buffer) + { + USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK); + uartHandle->tx.buffer = NULL; + } + + return kStatus_HAL_UartSuccess; +} + +#endif + +#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) + +void HAL_UartIsrFunction(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + +#if 0 + DisableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif + USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); +#if 0 + NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif +} + +#else + +void HAL_UartIsrFunction(hal_uart_handle_t handle) +{ + hal_uart_state_t *uartHandle; + assert(handle); + assert(!HAL_UART_TRANSFER_MODE); + + uartHandle = (hal_uart_state_t *)handle; + +#if 0 + DisableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif + HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle); +#if 0 + NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); + EnableIRQ(s_UsartIRQ[uartHandle->instance]); +#endif +} + +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/LPC51U68.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/LPC51U68.h new file mode 100644 index 000000000..6f4e969fb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/LPC51U68.h @@ -0,0 +1,8088 @@ +/* +** ################################################################### +** Processors: LPC51U68JBD48 +** LPC51U68JBD64 +** +** Compilers: GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** Keil ARM C/C++ Compiler +** MCUXpresso Compiler +** +** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 +** Version: rev. 1.0, 2017-12-15 +** Build: b190114 +** +** Abstract: +** CMSIS Peripheral Access Layer for LPC51U68 +** +** Copyright 1997-2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2017-12-15) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file LPC51U68.h + * @version 1.0 + * @date 2017-12-15 + * @brief CMSIS Peripheral Access Layer for LPC51U68 + * + * CMSIS Peripheral Access Layer for LPC51U68 + */ + +#ifndef _LPC51U68_H_ +#define _LPC51U68_H_ /**< Symbol preventing repeated inclusion */ + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100U +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ + + /* Device specific interrupts */ + WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ + DMA0_IRQn = 1, /**< DMA controller */ + GINT0_IRQn = 2, /**< GPIO group 0 */ + GINT1_IRQn = 3, /**< GPIO group 1 */ + PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ + PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ + PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ + PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ + UTICK0_IRQn = 8, /**< Micro-tick Timer */ + MRT0_IRQn = 9, /**< Multi-rate timer */ + CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ + CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ + SCT0_IRQn = 12, /**< SCTimer/PWM */ + CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ + FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C) */ + FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C) */ + FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C) */ + FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C) */ + FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C) */ + FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C) */ + FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ + FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ + ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ + ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ + ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ + Reserved41_IRQn = 25, /**< Reserved interrupt */ + Reserved42_IRQn = 26, /**< Reserved interrupt */ + USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ + USB0_IRQn = 28, /**< USB device */ + RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ + Reserved46_IRQn = 30, /**< Reserved interrupt */ + Reserved47_IRQn = 31 /**< Reserved interrupt */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + + +/* ---------------------------------------------------------------------------- + -- Cortex M0 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration + * @{ + */ + +#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ +#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ +#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ +#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ + +#include "core_cm0plus.h" /* Core Peripheral Access Layer */ +#include "system_LPC51U68.h" /* Device specific configuration file */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Mapping Information + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Mapping_Information Mapping Information + * @{ + */ + +/** Mapping Information */ +/*! + * @addtogroup dma_request + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Enumeration for the DMA hardware request + * + * Defines the enumeration for the DMA hardware request collections. + */ +typedef enum _dma_request_source +{ + kFlexcomm_Interface0_RX_I2C_Slave = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */ + kFlexcomm_Interface0_TX_I2C_Master = 1U, /**< Flexcomm Interface 0 TX/I2C Master */ + kFlexcomm_Interface1_RX_I2C_Slave = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */ + kFlexcomm_Interface1_TX_I2C_Master = 3U, /**< Flexcomm Interface 1 TX/I2C Master */ + kFlexcomm_Interface2_RX_I2C_Slave = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kFlexcomm_Interface2_TX_I2C_Master = 5U, /**< Flexcomm Interface 2 TX/I2C Master */ + kFlexcomm_Interface3_RX_I2C_Slave = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */ + kFlexcomm_Interface3_TX_I2C_Master = 7U, /**< Flexcomm Interface 3 TX/I2C Master */ + kFlexcomm_Interface4_RX_I2C_Slave = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */ + kFlexcomm_Interface4_TX_I2C_Master = 9U, /**< Flexcomm Interface 4 TX/I2C Master */ + kFlexcomm_Interface5_RX_I2C_Slave = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */ + kFlexcomm_Interface5_TX_I2C_Master = 11U, /**< Flexcomm Interface 5 TX/I2C Master */ + kFlexcomm_Interface6_RX_I2C_Slave = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */ + kFlexcomm_Interface6_TX_I2C_Master = 13U, /**< Flexcomm Interface 6 TX/I2C Master */ + kFlexcomm_Interface7_RX_I2C_Slave = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */ + kFlexcomm_Interface7_TX_I2C_Master = 15U, /**< Flexcomm Interface 7 TX/I2C Master */ + kDmaRequestNoDMARequest18 = 18U, /**< No DMA request 18 */ + kDmaRequestNoDMARequest19 = 19U, /**< No DMA request 19 */ +} dma_request_source_t; + +/* @} */ + + +/*! + * @} + */ /* end of group Mapping_Information */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #else + #pragma push + #pragma anon_unions + #endif +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ + __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ + __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ + __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ + uint8_t RESERVED_0[8]; + __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ + __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ + __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ + __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ + __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ + __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ + __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ + __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ + __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ + __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ +} ADC_Type; + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ +/*! @{ */ +#define ADC_CTRL_CLKDIV_MASK (0xFFU) +#define ADC_CTRL_CLKDIV_SHIFT (0U) +#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) +#define ADC_CTRL_ASYNMODE_MASK (0x100U) +#define ADC_CTRL_ASYNMODE_SHIFT (8U) +/*! ASYNMODE - Select clock mode. + * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse. + * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block. + */ +#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) +#define ADC_CTRL_RESOL_MASK (0x600U) +#define ADC_CTRL_RESOL_SHIFT (9U) +/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher conversion rates. A single conversion (including one conversion in a burst or sequence) requires the selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution + * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field. + * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field. + * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field. + * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field. + */ +#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) +#define ADC_CTRL_BYPASSCAL_MASK (0x800U) +#define ADC_CTRL_BYPASSCAL_SHIFT (11U) +/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset error is not a concern in the application. + * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may be warranted periodically - especially if operating conditions have changed. + * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC - particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set. + */ +#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) +#define ADC_CTRL_TSAMP_MASK (0x7000U) +#define ADC_CTRL_TSAMP_SHIFT (12U) +#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) +/*! @} */ + +/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ +/*! @{ */ +#define ADC_INSEL_SEL_MASK (0x3U) +#define ADC_INSEL_SEL_SHIFT (0U) +/*! SEL - Selects the input source for channel 0. All other values are reserved. + * 0b00..ADC0_IN0 function. + * 0b11..Internal temperature sensor. + */ +#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) +/*! @} */ + +/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ +/*! @{ */ +#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) +#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) +#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) +#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) +#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) +#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) +#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) +#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) +/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. + * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input. + * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input. + */ +#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) +#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) +#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) +/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period. + * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled. + * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled. + */ +#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) +#define ADC_SEQ_CTRL_START_MASK (0x4000000U) +#define ADC_SEQ_CTRL_START_SHIFT (26U) +#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) +#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) +#define ADC_SEQ_CTRL_BURST_SHIFT (27U) +#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) +#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) +#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) +#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) +#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) +#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) +/*! LOWPRIO - Set priority for sequence A. + * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. + * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point. + */ +#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) +#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) +#define ADC_SEQ_CTRL_MODE_SHIFT (30U) +/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below. + * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled. + * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode. + */ +#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) +#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) +#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) +/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. + * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. + * 0b1..Enabled. Sequence n is enabled. + */ +#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) +/*! @} */ + +/* The count of ADC_SEQ_CTRL */ +#define ADC_SEQ_CTRL_COUNT (2U) + +/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ +/*! @{ */ +#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) +#define ADC_SEQ_GDAT_RESULT_SHIFT (4U) +#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) +#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) +#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) +#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) +#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) +#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) +#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) +#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) +#define ADC_SEQ_GDAT_CHN_SHIFT (26U) +#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) +#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) +#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) +#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) +#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) +#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) +#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) +/*! @} */ + +/* The count of ADC_SEQ_GDAT */ +#define ADC_SEQ_GDAT_COUNT (2U) + +/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ +/*! @{ */ +#define ADC_DAT_RESULT_MASK (0xFFF0U) +#define ADC_DAT_RESULT_SHIFT (4U) +#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) +#define ADC_DAT_THCMPRANGE_MASK (0x30000U) +#define ADC_DAT_THCMPRANGE_SHIFT (16U) +#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) +#define ADC_DAT_THCMPCROSS_MASK (0xC0000U) +#define ADC_DAT_THCMPCROSS_SHIFT (18U) +#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) +#define ADC_DAT_CHANNEL_MASK (0x3C000000U) +#define ADC_DAT_CHANNEL_SHIFT (26U) +#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) +#define ADC_DAT_OVERRUN_MASK (0x40000000U) +#define ADC_DAT_OVERRUN_SHIFT (30U) +#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) +#define ADC_DAT_DATAVALID_MASK (0x80000000U) +#define ADC_DAT_DATAVALID_SHIFT (31U) +#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) +/*! @} */ + +/* The count of ADC_DAT */ +#define ADC_DAT_COUNT (12U) + +/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +/*! @{ */ +#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) +#define ADC_THR0_LOW_THRLOW_SHIFT (4U) +#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) +/*! @} */ + +/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +/*! @{ */ +#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) +#define ADC_THR1_LOW_THRLOW_SHIFT (4U) +#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) +/*! @} */ + +/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ +/*! @{ */ +#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) +#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) +#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) +/*! @} */ + +/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ +/*! @{ */ +#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) +#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) +#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) +/*! @} */ + +/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ +/*! @{ */ +#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) +#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) +/*! CH0_THRSEL - Threshold select for channel 0. + * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers. + * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers. + */ +#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) +#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) +#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) +#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) +#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) +#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) +#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) +#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) +#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) +#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) +#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) +#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) +#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) +#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) +#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) +#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) +#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) +#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) +#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) +#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) +#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) +#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) +#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) +#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) +/*! @} */ + +/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ +/*! @{ */ +#define ADC_INTEN_SEQA_INTEN_MASK (0x1U) +#define ADC_INTEN_SEQA_INTEN_SHIFT (0U) +/*! SEQA_INTEN - Sequence A interrupt enable. + * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled. + * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register. + */ +#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) +#define ADC_INTEN_SEQB_INTEN_MASK (0x2U) +#define ADC_INTEN_SEQB_INTEN_SHIFT (1U) +/*! SEQB_INTEN - Sequence B interrupt enable. + * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled. + * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register. + */ +#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) +#define ADC_INTEN_OVR_INTEN_MASK (0x4U) +#define ADC_INTEN_OVR_INTEN_SHIFT (2U) +/*! OVR_INTEN - Overrun interrupt enable. + * 0b0..Disabled. The overrun interrupt is disabled. + * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted. + */ +#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) +#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) +#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) +/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0. + * 0b00..Disabled. + * 0b01..Outside threshold. + * 0b10..Crossing threshold. + * 0b11..Reserved + */ +#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) +#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) +#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) +#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) +#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) +#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) +#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) +#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) +#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) +#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) +#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) +#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) +#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) +#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) +#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) +#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) +#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) +#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) +#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) +#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) +#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) +#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) +#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) +#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) +#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) +#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) +#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) +#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) +#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) +#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) +#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) +#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) +#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) +#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) +/*! @} */ + +/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ +/*! @{ */ +#define ADC_FLAGS_THCMP0_MASK (0x1U) +#define ADC_FLAGS_THCMP0_SHIFT (0U) +#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) +#define ADC_FLAGS_THCMP1_MASK (0x2U) +#define ADC_FLAGS_THCMP1_SHIFT (1U) +#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) +#define ADC_FLAGS_THCMP2_MASK (0x4U) +#define ADC_FLAGS_THCMP2_SHIFT (2U) +#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) +#define ADC_FLAGS_THCMP3_MASK (0x8U) +#define ADC_FLAGS_THCMP3_SHIFT (3U) +#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) +#define ADC_FLAGS_THCMP4_MASK (0x10U) +#define ADC_FLAGS_THCMP4_SHIFT (4U) +#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) +#define ADC_FLAGS_THCMP5_MASK (0x20U) +#define ADC_FLAGS_THCMP5_SHIFT (5U) +#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) +#define ADC_FLAGS_THCMP6_MASK (0x40U) +#define ADC_FLAGS_THCMP6_SHIFT (6U) +#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) +#define ADC_FLAGS_THCMP7_MASK (0x80U) +#define ADC_FLAGS_THCMP7_SHIFT (7U) +#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) +#define ADC_FLAGS_THCMP8_MASK (0x100U) +#define ADC_FLAGS_THCMP8_SHIFT (8U) +#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) +#define ADC_FLAGS_THCMP9_MASK (0x200U) +#define ADC_FLAGS_THCMP9_SHIFT (9U) +#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) +#define ADC_FLAGS_THCMP10_MASK (0x400U) +#define ADC_FLAGS_THCMP10_SHIFT (10U) +#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) +#define ADC_FLAGS_THCMP11_MASK (0x800U) +#define ADC_FLAGS_THCMP11_SHIFT (11U) +#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) +#define ADC_FLAGS_OVERRUN0_MASK (0x1000U) +#define ADC_FLAGS_OVERRUN0_SHIFT (12U) +#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) +#define ADC_FLAGS_OVERRUN1_MASK (0x2000U) +#define ADC_FLAGS_OVERRUN1_SHIFT (13U) +#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) +#define ADC_FLAGS_OVERRUN2_MASK (0x4000U) +#define ADC_FLAGS_OVERRUN2_SHIFT (14U) +#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) +#define ADC_FLAGS_OVERRUN3_MASK (0x8000U) +#define ADC_FLAGS_OVERRUN3_SHIFT (15U) +#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) +#define ADC_FLAGS_OVERRUN4_MASK (0x10000U) +#define ADC_FLAGS_OVERRUN4_SHIFT (16U) +#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) +#define ADC_FLAGS_OVERRUN5_MASK (0x20000U) +#define ADC_FLAGS_OVERRUN5_SHIFT (17U) +#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) +#define ADC_FLAGS_OVERRUN6_MASK (0x40000U) +#define ADC_FLAGS_OVERRUN6_SHIFT (18U) +#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) +#define ADC_FLAGS_OVERRUN7_MASK (0x80000U) +#define ADC_FLAGS_OVERRUN7_SHIFT (19U) +#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) +#define ADC_FLAGS_OVERRUN8_MASK (0x100000U) +#define ADC_FLAGS_OVERRUN8_SHIFT (20U) +#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) +#define ADC_FLAGS_OVERRUN9_MASK (0x200000U) +#define ADC_FLAGS_OVERRUN9_SHIFT (21U) +#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) +#define ADC_FLAGS_OVERRUN10_MASK (0x400000U) +#define ADC_FLAGS_OVERRUN10_SHIFT (22U) +#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) +#define ADC_FLAGS_OVERRUN11_MASK (0x800000U) +#define ADC_FLAGS_OVERRUN11_SHIFT (23U) +#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) +#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) +#define ADC_FLAGS_SEQA_OVR_SHIFT (24U) +#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) +#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) +#define ADC_FLAGS_SEQB_OVR_SHIFT (25U) +#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) +#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) +#define ADC_FLAGS_SEQA_INT_SHIFT (28U) +#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) +#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) +#define ADC_FLAGS_SEQB_INT_SHIFT (29U) +#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) +#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) +#define ADC_FLAGS_THCMP_INT_SHIFT (30U) +#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) +#define ADC_FLAGS_OVR_INT_MASK (0x80000000U) +#define ADC_FLAGS_OVR_INT_SHIFT (31U) +#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) +/*! @} */ + +/*! @name STARTUP - ADC Startup register. */ +/*! @{ */ +#define ADC_STARTUP_ADC_ENA_MASK (0x1U) +#define ADC_STARTUP_ADC_ENA_SHIFT (0U) +#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) +#define ADC_STARTUP_ADC_INIT_MASK (0x2U) +#define ADC_STARTUP_ADC_INIT_SHIFT (1U) +#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) +/*! @} */ + +/*! @name CALIB - ADC Calibration register. */ +/*! @{ */ +#define ADC_CALIB_CALIB_MASK (0x1U) +#define ADC_CALIB_CALIB_SHIFT (0U) +#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) +#define ADC_CALIB_CALREQD_MASK (0x2U) +#define ADC_CALIB_CALREQD_SHIFT (1U) +#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) +#define ADC_CALIB_CALVALUE_MASK (0x1FCU) +#define ADC_CALIB_CALVALUE_SHIFT (2U) +#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ADC_Register_Masks */ + + +/* ADC - Peripheral instance base addresses */ +/** Peripheral ADC0 base address */ +#define ADC0_BASE (0x400A0000u) +/** Peripheral ADC0 base pointer */ +#define ADC0 ((ADC_Type *)ADC0_BASE) +/** Array initializer of ADC peripheral base addresses */ +#define ADC_BASE_ADDRS { ADC0_BASE } +/** Array initializer of ADC peripheral base pointers */ +#define ADC_BASE_PTRS { ADC0 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } +#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } + +/*! + * @} + */ /* end of group ADC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- ASYNC_SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer + * @{ + */ + +/** ASYNC_SYSCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ + __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ + __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ + __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ + __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ + uint8_t RESERVED_1[4]; + __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ +} ASYNC_SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- ASYNC_SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks + * @{ + */ + +/*! @name ASYNCPRESETCTRL - Async peripheral reset control */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) +#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) +/*! @} */ + +/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) +/*! @} */ + +/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) +#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) +/*! @} */ + +/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ +/*! @{ */ +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) +/*! SEL - Clock source for asynchronous clock source selector A + * 0b00..Main clock + * 0b01..FRO 12 MHz + * 0b10..Reserved setting + * 0b11..Reserved setting + */ +#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group ASYNC_SYSCON_Register_Masks */ + + +/* ASYNC_SYSCON - Peripheral instance base addresses */ +/** Peripheral ASYNC_SYSCON base address */ +#define ASYNC_SYSCON_BASE (0x40040000u) +/** Peripheral ASYNC_SYSCON base pointer */ +#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) +/** Array initializer of ASYNC_SYSCON peripheral base addresses */ +#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } +/** Array initializer of ASYNC_SYSCON peripheral base pointers */ +#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } + +/*! + * @} + */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CRC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer + * @{ + */ + +/** CRC - Register Layout Typedef */ +typedef struct { + __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ + __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ + union { /* offset: 0x8 */ + __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ + __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ + }; +} CRC_Type; + +/* ---------------------------------------------------------------------------- + -- CRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CRC_Register_Masks CRC Register Masks + * @{ + */ + +/*! @name MODE - CRC mode register */ +/*! @{ */ +#define CRC_MODE_CRC_POLY_MASK (0x3U) +#define CRC_MODE_CRC_POLY_SHIFT (0U) +#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) +#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) +#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) +#define CRC_MODE_CMPL_WR_MASK (0x8U) +#define CRC_MODE_CMPL_WR_SHIFT (3U) +#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) +#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) +#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) +#define CRC_MODE_CMPL_SUM_MASK (0x20U) +#define CRC_MODE_CMPL_SUM_SHIFT (5U) +#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) +/*! @} */ + +/*! @name SEED - CRC seed register */ +/*! @{ */ +#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) +#define CRC_SEED_CRC_SEED_SHIFT (0U) +#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) +/*! @} */ + +/*! @name SUM - CRC checksum register */ +/*! @{ */ +#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) +#define CRC_SUM_CRC_SUM_SHIFT (0U) +#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) +/*! @} */ + +/*! @name WR_DATA - CRC data register */ +/*! @{ */ +#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) +#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CRC_Register_Masks */ + + +/* CRC - Peripheral instance base addresses */ +/** Peripheral CRC_ENGINE base address */ +#define CRC_ENGINE_BASE (0x40095000u) +/** Peripheral CRC_ENGINE base pointer */ +#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) +/** Array initializer of CRC peripheral base addresses */ +#define CRC_BASE_ADDRS { CRC_ENGINE_BASE } +/** Array initializer of CRC peripheral base pointers */ +#define CRC_BASE_PTRS { CRC_ENGINE } + +/*! + * @} + */ /* end of group CRC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CTIMER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer + * @{ + */ + +/** CTIMER - Register Layout Typedef */ +typedef struct { + __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ + __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ + __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */ + __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */ + __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */ + __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */ + __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ + __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ + __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ + __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ + uint8_t RESERVED_0[48]; + __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ + __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ +} CTIMER_Type; + +/* ---------------------------------------------------------------------------- + -- CTIMER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CTIMER_Register_Masks CTIMER Register Masks + * @{ + */ + +/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ +/*! @{ */ +#define CTIMER_IR_MR0INT_MASK (0x1U) +#define CTIMER_IR_MR0INT_SHIFT (0U) +#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) +#define CTIMER_IR_MR1INT_MASK (0x2U) +#define CTIMER_IR_MR1INT_SHIFT (1U) +#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) +#define CTIMER_IR_MR2INT_MASK (0x4U) +#define CTIMER_IR_MR2INT_SHIFT (2U) +#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) +#define CTIMER_IR_MR3INT_MASK (0x8U) +#define CTIMER_IR_MR3INT_SHIFT (3U) +#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) +#define CTIMER_IR_CR0INT_MASK (0x10U) +#define CTIMER_IR_CR0INT_SHIFT (4U) +#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) +#define CTIMER_IR_CR1INT_MASK (0x20U) +#define CTIMER_IR_CR1INT_SHIFT (5U) +#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) +#define CTIMER_IR_CR2INT_MASK (0x40U) +#define CTIMER_IR_CR2INT_SHIFT (6U) +#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) +#define CTIMER_IR_CR3INT_MASK (0x80U) +#define CTIMER_IR_CR3INT_SHIFT (7U) +#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) +/*! @} */ + +/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ +/*! @{ */ +#define CTIMER_TCR_CEN_MASK (0x1U) +#define CTIMER_TCR_CEN_SHIFT (0U) +/*! CEN - Counter enable. + * 0b0..Disabled.The counters are disabled. + * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. + */ +#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) +#define CTIMER_TCR_CRST_MASK (0x2U) +#define CTIMER_TCR_CRST_SHIFT (1U) +/*! CRST - Counter reset. + * 0b0..Disabled. Do nothing. + * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. + */ +#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) +/*! @} */ + +/*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ +/*! @{ */ +#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_TC_TCVAL_SHIFT (0U) +#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) +/*! @} */ + +/*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ +/*! @{ */ +#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PR_PRVAL_SHIFT (0U) +#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) +/*! @} */ + +/*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ +/*! @{ */ +#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) +#define CTIMER_PC_PCVAL_SHIFT (0U) +#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) +/*! @} */ + +/*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ +/*! @{ */ +#define CTIMER_MCR_MR0I_MASK (0x1U) +#define CTIMER_MCR_MR0I_SHIFT (0U) +#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) +#define CTIMER_MCR_MR0R_MASK (0x2U) +#define CTIMER_MCR_MR0R_SHIFT (1U) +#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) +#define CTIMER_MCR_MR0S_MASK (0x4U) +#define CTIMER_MCR_MR0S_SHIFT (2U) +#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) +#define CTIMER_MCR_MR1I_MASK (0x8U) +#define CTIMER_MCR_MR1I_SHIFT (3U) +#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) +#define CTIMER_MCR_MR1R_MASK (0x10U) +#define CTIMER_MCR_MR1R_SHIFT (4U) +#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) +#define CTIMER_MCR_MR1S_MASK (0x20U) +#define CTIMER_MCR_MR1S_SHIFT (5U) +#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) +#define CTIMER_MCR_MR2I_MASK (0x40U) +#define CTIMER_MCR_MR2I_SHIFT (6U) +#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) +#define CTIMER_MCR_MR2R_MASK (0x80U) +#define CTIMER_MCR_MR2R_SHIFT (7U) +#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) +#define CTIMER_MCR_MR2S_MASK (0x100U) +#define CTIMER_MCR_MR2S_SHIFT (8U) +#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) +#define CTIMER_MCR_MR3I_MASK (0x200U) +#define CTIMER_MCR_MR3I_SHIFT (9U) +#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) +#define CTIMER_MCR_MR3R_MASK (0x400U) +#define CTIMER_MCR_MR3R_SHIFT (10U) +#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) +#define CTIMER_MCR_MR3S_MASK (0x800U) +#define CTIMER_MCR_MR3S_SHIFT (11U) +#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) +/*! @} */ + +/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ +/*! @{ */ +#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) +#define CTIMER_MR_MATCH_SHIFT (0U) +#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) +/*! @} */ + +/* The count of CTIMER_MR */ +#define CTIMER_MR_COUNT (4U) + +/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ +/*! @{ */ +#define CTIMER_CCR_CAP0RE_MASK (0x1U) +#define CTIMER_CCR_CAP0RE_SHIFT (0U) +#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) +#define CTIMER_CCR_CAP0FE_MASK (0x2U) +#define CTIMER_CCR_CAP0FE_SHIFT (1U) +#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) +#define CTIMER_CCR_CAP0I_MASK (0x4U) +#define CTIMER_CCR_CAP0I_SHIFT (2U) +#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) +#define CTIMER_CCR_CAP1RE_MASK (0x8U) +#define CTIMER_CCR_CAP1RE_SHIFT (3U) +#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) +#define CTIMER_CCR_CAP1FE_MASK (0x10U) +#define CTIMER_CCR_CAP1FE_SHIFT (4U) +#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) +#define CTIMER_CCR_CAP1I_MASK (0x20U) +#define CTIMER_CCR_CAP1I_SHIFT (5U) +#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) +#define CTIMER_CCR_CAP2RE_MASK (0x40U) +#define CTIMER_CCR_CAP2RE_SHIFT (6U) +#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) +#define CTIMER_CCR_CAP2FE_MASK (0x80U) +#define CTIMER_CCR_CAP2FE_SHIFT (7U) +#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) +#define CTIMER_CCR_CAP2I_MASK (0x100U) +#define CTIMER_CCR_CAP2I_SHIFT (8U) +#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) +#define CTIMER_CCR_CAP3RE_MASK (0x200U) +#define CTIMER_CCR_CAP3RE_SHIFT (9U) +#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) +#define CTIMER_CCR_CAP3FE_MASK (0x400U) +#define CTIMER_CCR_CAP3FE_SHIFT (10U) +#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) +#define CTIMER_CCR_CAP3I_MASK (0x800U) +#define CTIMER_CCR_CAP3I_SHIFT (11U) +#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) +/*! @} */ + +/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ +/*! @{ */ +#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) +#define CTIMER_CR_CAP_SHIFT (0U) +#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) +/*! @} */ + +/* The count of CTIMER_CR */ +#define CTIMER_CR_COUNT (4U) + +/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ +/*! @{ */ +#define CTIMER_EMR_EM0_MASK (0x1U) +#define CTIMER_EMR_EM0_SHIFT (0U) +#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) +#define CTIMER_EMR_EM1_MASK (0x2U) +#define CTIMER_EMR_EM1_SHIFT (1U) +#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) +#define CTIMER_EMR_EM2_MASK (0x4U) +#define CTIMER_EMR_EM2_SHIFT (2U) +#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) +#define CTIMER_EMR_EM3_MASK (0x8U) +#define CTIMER_EMR_EM3_SHIFT (3U) +#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) +#define CTIMER_EMR_EMC0_MASK (0x30U) +#define CTIMER_EMR_EMC0_SHIFT (4U) +/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) +#define CTIMER_EMR_EMC1_MASK (0xC0U) +#define CTIMER_EMR_EMC1_SHIFT (6U) +/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) +#define CTIMER_EMR_EMC2_MASK (0x300U) +#define CTIMER_EMR_EMC2_SHIFT (8U) +/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) +#define CTIMER_EMR_EMC3_MASK (0xC00U) +#define CTIMER_EMR_EMC3_SHIFT (10U) +/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. + * 0b00..Do Nothing. + * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). + * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). + * 0b11..Toggle. Toggle the corresponding External Match bit/output. + */ +#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) +/*! @} */ + +/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ +/*! @{ */ +#define CTIMER_CTCR_CTMODE_MASK (0x3U) +#define CTIMER_CTCR_CTMODE_SHIFT (0U) +/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. + * 0b00..Timer Mode. Incremented every rising APB bus clock edge. + * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. + * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. + * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. + */ +#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) +#define CTIMER_CTCR_CINSEL_MASK (0xCU) +#define CTIMER_CTCR_CINSEL_SHIFT (2U) +/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. + * 0b00..Channel 0. CAPn.0 for CTIMERn + * 0b01..Channel 1. CAPn.1 for CTIMERn + * 0b10..Channel 2. CAPn.2 for CTIMERn + * 0b11..Channel 3. CAPn.3 for CTIMERn + */ +#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) +#define CTIMER_CTCR_ENCC_MASK (0x10U) +#define CTIMER_CTCR_ENCC_SHIFT (4U) +#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) +#define CTIMER_CTCR_SELCC_MASK (0xE0U) +#define CTIMER_CTCR_SELCC_SHIFT (5U) +/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. + * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). + * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). + * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). + */ +#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) +/*! @} */ + +/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ +/*! @{ */ +#define CTIMER_PWMC_PWMEN0_MASK (0x1U) +#define CTIMER_PWMC_PWMEN0_SHIFT (0U) +/*! PWMEN0 - PWM mode enable for channel0. + * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. + */ +#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) +#define CTIMER_PWMC_PWMEN1_MASK (0x2U) +#define CTIMER_PWMC_PWMEN1_SHIFT (1U) +/*! PWMEN1 - PWM mode enable for channel1. + * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. + */ +#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) +#define CTIMER_PWMC_PWMEN2_MASK (0x4U) +#define CTIMER_PWMC_PWMEN2_SHIFT (2U) +/*! PWMEN2 - PWM mode enable for channel2. + * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. + * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. + */ +#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) +#define CTIMER_PWMC_PWMEN3_MASK (0x8U) +#define CTIMER_PWMC_PWMEN3_SHIFT (3U) +/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. + * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. + * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. + */ +#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CTIMER_Register_Masks */ + + +/* CTIMER - Peripheral instance base addresses */ +/** Peripheral CTIMER0 base address */ +#define CTIMER0_BASE (0x40008000u) +/** Peripheral CTIMER0 base pointer */ +#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) +/** Peripheral CTIMER1 base address */ +#define CTIMER1_BASE (0x40009000u) +/** Peripheral CTIMER1 base pointer */ +#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) +/** Peripheral CTIMER3 base address */ +#define CTIMER3_BASE (0x40048000u) +/** Peripheral CTIMER3 base pointer */ +#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) +/** Array initializer of CTIMER peripheral base addresses */ +#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER3_BASE } +/** Array initializer of CTIMER peripheral base pointers */ +#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER3 } +/** Interrupt vectors for the CTIMER peripheral type */ +#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER3_IRQn } + +/*! + * @} + */ /* end of group CTIMER_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ + __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ + __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ + uint8_t RESERVED_0[20]; + struct { /* offset: 0x20, array step: 0x5C */ + __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ + uint8_t RESERVED_0[4]; + __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ + uint8_t RESERVED_1[4]; + __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ + uint8_t RESERVED_2[4]; + __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ + uint8_t RESERVED_4[4]; + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ + uint8_t RESERVED_5[4]; + __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ + uint8_t RESERVED_6[4]; + __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ + uint8_t RESERVED_7[4]; + __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ + uint8_t RESERVED_8[4]; + __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ + uint8_t RESERVED_9[4]; + __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ + uint8_t RESERVED_10[4]; + __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ + } COMMON[1]; + uint8_t RESERVED_1[900]; + struct { /* offset: 0x400, array step: 0x10 */ + __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ + __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ + __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ + uint8_t RESERVED_0[4]; + } CHANNEL[20]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CTRL - DMA control. */ +/*! @{ */ +#define DMA_CTRL_ENABLE_MASK (0x1U) +#define DMA_CTRL_ENABLE_SHIFT (0U) +/*! ENABLE - DMA controller master enable. + * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. + * 0b1..Enabled. The DMA controller is enabled. + */ +#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status. */ +/*! @{ */ +#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) +#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) +/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. + * 0b0..Not pending. No enabled interrupts are pending. + * 0b1..Pending. At least one enabled interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) +#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) +#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) +/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. + * 0b0..Not pending. No error interrupts are pending. + * 0b1..Pending. At least one error interrupt is pending. + */ +#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) +/*! @} */ + +/*! @name SRAMBASE - SRAM address of the channel configuration table. */ +/*! @{ */ +#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) +#define DMA_SRAMBASE_OFFSET_SHIFT (9U) +#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) +/*! @} */ + +/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLESET */ +#define DMA_COMMON_ENABLESET_COUNT (1U) + +/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ENABLECLR */ +#define DMA_COMMON_ENABLECLR_COUNT (1U) + +/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ACTIVE */ +#define DMA_COMMON_ACTIVE_COUNT (1U) + +/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) +#define DMA_COMMON_BUSY_BSY_SHIFT (0U) +#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) +/*! @} */ + +/* The count of DMA_COMMON_BUSY */ +#define DMA_COMMON_BUSY_COUNT (1U) + +/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ERRINT */ +#define DMA_COMMON_ERRINT_COUNT (1U) + +/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENSET */ +#define DMA_COMMON_INTENSET_COUNT (1U) + +/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTENCLR */ +#define DMA_COMMON_INTENCLR_COUNT (1U) + +/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTA_IA_SHIFT (0U) +#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTA */ +#define DMA_COMMON_INTA_COUNT (1U) + +/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) +#define DMA_COMMON_INTB_IB_SHIFT (0U) +#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) +/*! @} */ + +/* The count of DMA_COMMON_INTB */ +#define DMA_COMMON_INTB_COUNT (1U) + +/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETVALID_SV_SHIFT (0U) +#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETVALID */ +#define DMA_COMMON_SETVALID_COUNT (1U) + +/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) +#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) +/*! @} */ + +/* The count of DMA_COMMON_SETTRIG */ +#define DMA_COMMON_SETTRIG_COUNT (1U) + +/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ +/*! @{ */ +#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) +#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) +/*! @} */ + +/* The count of DMA_COMMON_ABORT */ +#define DMA_COMMON_ABORT_COUNT (1U) + +/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) +#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) +/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. + * 0b0..Disabled. Peripheral DMA requests are disabled. + * 0b1..Enabled. Peripheral DMA requests are enabled. + */ +#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) +#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) +#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) +/*! HWTRIGEN - Hardware Triggering Enable for this channel. + * 0b0..Disabled. Hardware triggering is not used. + * 0b1..Enabled. Use hardware triggering. + */ +#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) +#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) +#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) +/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. + * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. + * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. + */ +#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) +#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) +#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) +/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. + * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. + * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. + */ +#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) +#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) +#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) +/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. + * 0b0..Single transfer. Hardware trigger causes a single transfer. + * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. + */ +#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) +#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) +#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) +#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) +/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. + * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) +#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) +/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. + * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. + * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. + */ +#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) +#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) +#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CFG */ +#define DMA_CHANNEL_CFG_COUNT (20U) + +/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) +/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. + * 0b0..No effect. No effect on DMA operation. + * 0b1..Valid pending. + */ +#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) +#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) +#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) +/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. + * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. + * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. + */ +#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_CTLSTAT */ +#define DMA_CHANNEL_CTLSTAT_COUNT (20U) + +/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ +/*! @{ */ +#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) +#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) +/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. + * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. + * 0b1..Valid. The current channel descriptor is considered valid. + */ +#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) +#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) +#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) +/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. + * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. + * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) +#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) +#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) +/*! SWTRIG - Software Trigger. + * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. + * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. + */ +#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) +#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) +/*! CLRTRIG - Clear Trigger. + * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. + * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted + */ +#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) +#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) +/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) +#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) +#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) +/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. + * 0b0..No effect. + * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. + */ +#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) +#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) +#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) +/*! WIDTH - Transfer width used for this DMA channel. + * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). + * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). + * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). + * 0b11..Reserved. Reserved setting, do not use. + */ +#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) +#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) +#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) +/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. + * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. + * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. + * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) +#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) +#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) +/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. + * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. + * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. + * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. + * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. + */ +#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) +/*! @} */ + +/* The count of DMA_CHANNEL_XFERCFG */ +#define DMA_CHANNEL_XFERCFG_COUNT (20U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40082000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_IRQS { DMA0_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer + * @{ + */ + +/** FLEXCOMM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[4088]; + __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ + __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ +} FLEXCOMM_Type; + +/* ---------------------------------------------------------------------------- + -- FLEXCOMM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks + * @{ + */ + +/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ +/*! @{ */ +#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) +#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) +/*! PERSEL - Peripheral Select. This field is writable by software. + * 0b000..No peripheral selected. + * 0b001..USART function selected. + * 0b010..SPI function selected. + * 0b011..I2C function selected. + * 0b100..I2S transmit function selected. + * 0b101..I2S receive function selected. + * 0b110..Reserved + * 0b111..Reserved + */ +#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) +#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) +#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) +/*! LOCK - Lock the peripheral select. This field is writable by software. + * 0b0..Peripheral select can be changed by software. + * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. + */ +#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) +#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) +#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) +/*! USARTPRESENT - USART present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the USART function. + * 0b1..This Flexcomm includes the USART function. + */ +#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) +#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) +#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) +/*! SPIPRESENT - SPI present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the SPI function. + * 0b1..This Flexcomm includes the SPI function. + */ +#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) +#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) +#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) +/*! I2CPRESENT - I2C present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2C function. + * 0b1..This Flexcomm includes the I2C function. + */ +#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) +#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) +#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) +/*! I2SPRESENT - I 2S present indicator. This field is Read-only. + * 0b0..This Flexcomm does not include the I2S function. + * 0b1..This Flexcomm includes the I2S function. + */ +#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) +#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) +#define FLEXCOMM_PSELID_ID_SHIFT (12U) +#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) +/*! @} */ + +/*! @name PID - Peripheral identification register. */ +/*! @{ */ +#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) +#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) +#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) +#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) +#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) +#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) +#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) +#define FLEXCOMM_PID_ID_SHIFT (16U) +#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FLEXCOMM_Register_Masks */ + + +/* FLEXCOMM - Peripheral instance base addresses */ +/** Peripheral FLEXCOMM0 base address */ +#define FLEXCOMM0_BASE (0x40086000u) +/** Peripheral FLEXCOMM0 base pointer */ +#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) +/** Peripheral FLEXCOMM1 base address */ +#define FLEXCOMM1_BASE (0x40087000u) +/** Peripheral FLEXCOMM1 base pointer */ +#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) +/** Peripheral FLEXCOMM2 base address */ +#define FLEXCOMM2_BASE (0x40088000u) +/** Peripheral FLEXCOMM2 base pointer */ +#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) +/** Peripheral FLEXCOMM3 base address */ +#define FLEXCOMM3_BASE (0x40089000u) +/** Peripheral FLEXCOMM3 base pointer */ +#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) +/** Peripheral FLEXCOMM4 base address */ +#define FLEXCOMM4_BASE (0x4008A000u) +/** Peripheral FLEXCOMM4 base pointer */ +#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) +/** Peripheral FLEXCOMM5 base address */ +#define FLEXCOMM5_BASE (0x40096000u) +/** Peripheral FLEXCOMM5 base pointer */ +#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) +/** Peripheral FLEXCOMM6 base address */ +#define FLEXCOMM6_BASE (0x40097000u) +/** Peripheral FLEXCOMM6 base pointer */ +#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) +/** Peripheral FLEXCOMM7 base address */ +#define FLEXCOMM7_BASE (0x40098000u) +/** Peripheral FLEXCOMM7 base pointer */ +#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) +/** Array initializer of FLEXCOMM peripheral base addresses */ +#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE } +/** Array initializer of FLEXCOMM peripheral base pointers */ +#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7 } +/** Interrupt vectors for the FLEXCOMM peripheral type */ +#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- FMC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer + * @{ + */ + +/** FMC - Register Layout Typedef */ +typedef struct { + __IO uint32_t FCTR; /**< Control register, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t FBWST; /**< Wait state register, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t FMSSTART; /**< Signature start address register, offset: 0x20 */ + __IO uint32_t FMSSTOP; /**< Signature stop-address register, offset: 0x24 */ + uint8_t RESERVED_2[4]; + __I uint32_t FMSW[4]; /**< Words of 128-bit signature word, array offset: 0x2C, array step: 0x4 */ + uint8_t RESERVED_3[4004]; + __I uint32_t FMSTAT; /**< Signature generation status register, offset: 0xFE0 */ + uint8_t RESERVED_4[4]; + __O uint32_t FMSTATCLR; /**< Signature generation status clear register, offset: 0xFE8 */ +} FMC_Type; + +/* ---------------------------------------------------------------------------- + -- FMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FMC_Register_Masks FMC Register Masks + * @{ + */ + +/*! @name FCTR - Control register */ +/*! @{ */ +#define FMC_FCTR_FS_RD0_MASK (0x8U) +#define FMC_FCTR_FS_RD0_SHIFT (3U) +#define FMC_FCTR_FS_RD0(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK) +#define FMC_FCTR_FS_RD1_MASK (0x10U) +#define FMC_FCTR_FS_RD1_SHIFT (4U) +#define FMC_FCTR_FS_RD1(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK) +/*! @} */ + +/*! @name FBWST - Wait state register */ +/*! @{ */ +#define FMC_FBWST_WAITSTATES_MASK (0xFFU) +#define FMC_FBWST_WAITSTATES_SHIFT (0U) +#define FMC_FBWST_WAITSTATES(x) (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK) +/*! @} */ + +/*! @name FMSSTART - Signature start address register */ +/*! @{ */ +#define FMC_FMSSTART_START_MASK (0x1FFFFU) +#define FMC_FMSSTART_START_SHIFT (0U) +#define FMC_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK) +/*! @} */ + +/*! @name FMSSTOP - Signature stop-address register */ +/*! @{ */ +#define FMC_FMSSTOP_STOP_MASK (0x1FFFFU) +#define FMC_FMSSTOP_STOP_SHIFT (0U) +#define FMC_FMSSTOP_STOP(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK) +#define FMC_FMSSTOP_SIG_START_MASK (0x20000U) +#define FMC_FMSSTOP_SIG_START_SHIFT (17U) +#define FMC_FMSSTOP_SIG_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK) +/*! @} */ + +/*! @name FMSW - Words of 128-bit signature word */ +/*! @{ */ +#define FMC_FMSW_SW_MASK (0xFFFFFFFFU) +#define FMC_FMSW_SW_SHIFT (0U) +#define FMC_FMSW_SW(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK) +/*! @} */ + +/* The count of FMC_FMSW */ +#define FMC_FMSW_COUNT (4U) + +/*! @name FMSTAT - Signature generation status register */ +/*! @{ */ +#define FMC_FMSTAT_SIG_DONE_MASK (0x4U) +#define FMC_FMSTAT_SIG_DONE_SHIFT (2U) +#define FMC_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK) +/*! @} */ + +/*! @name FMSTATCLR - Signature generation status clear register */ +/*! @{ */ +#define FMC_FMSTATCLR_SIG_DONE_CLR_MASK (0x4U) +#define FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT (2U) +#define FMC_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group FMC_Register_Masks */ + + +/* FMC - Peripheral instance base addresses */ +/** Peripheral FMC base address */ +#define FMC_BASE (0x40034000u) +/** Peripheral FMC base pointer */ +#define FMC ((FMC_Type *)FMC_BASE) +/** Array initializer of FMC peripheral base addresses */ +#define FMC_BASE_ADDRS { FMC_BASE } +/** Array initializer of FMC peripheral base pointers */ +#define FMC_BASE_PTRS { FMC } + +/*! + * @} + */ /* end of group FMC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer + * @{ + */ + +/** GINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ + uint8_t RESERVED_0[28]; + __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ + uint8_t RESERVED_1[24]; + __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ +} GINT_Type; + +/* ---------------------------------------------------------------------------- + -- GINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GINT_Register_Masks GINT Register Masks + * @{ + */ + +/*! @name CTRL - GPIO grouped interrupt control register */ +/*! @{ */ +#define GINT_CTRL_INT_MASK (0x1U) +#define GINT_CTRL_INT_SHIFT (0U) +/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. + * 0b0..No request. No interrupt request is pending. + * 0b1..Request active. Interrupt request is active. + */ +#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) +#define GINT_CTRL_COMB_MASK (0x2U) +#define GINT_CTRL_COMB_SHIFT (1U) +/*! COMB - Combine enabled inputs for group interrupt + * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). + * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). + */ +#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) +#define GINT_CTRL_TRIG_MASK (0x4U) +#define GINT_CTRL_TRIG_SHIFT (2U) +/*! TRIG - Group interrupt trigger + * 0b0..Edge-triggered. + * 0b1..Level-triggered. + */ +#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) +/*! @} */ + +/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ +/*! @{ */ +#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) +#define GINT_PORT_POL_POL_SHIFT (0U) +#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) +/*! @} */ + +/* The count of GINT_PORT_POL */ +#define GINT_PORT_POL_COUNT (2U) + +/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ +/*! @{ */ +#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) +#define GINT_PORT_ENA_ENA_SHIFT (0U) +#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) +/*! @} */ + +/* The count of GINT_PORT_ENA */ +#define GINT_PORT_ENA_COUNT (2U) + + +/*! + * @} + */ /* end of group GINT_Register_Masks */ + + +/* GINT - Peripheral instance base addresses */ +/** Peripheral GINT0 base address */ +#define GINT0_BASE (0x40002000u) +/** Peripheral GINT0 base pointer */ +#define GINT0 ((GINT_Type *)GINT0_BASE) +/** Peripheral GINT1 base address */ +#define GINT1_BASE (0x40003000u) +/** Peripheral GINT1 base pointer */ +#define GINT1 ((GINT_Type *)GINT1_BASE) +/** Array initializer of GINT peripheral base addresses */ +#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } +/** Array initializer of GINT peripheral base pointers */ +#define GINT_BASE_PTRS { GINT0, GINT1 } +/** Interrupt vectors for the GINT peripheral type */ +#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } + +/*! + * @} + */ /* end of group GINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- GPIO Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer + * @{ + */ + +/** GPIO - Register Layout Typedef */ +typedef struct { + __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[4032]; + __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3840]; + __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[120]; + __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[120]; + __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[120]; + __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[120]; + __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[120]; + __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[120]; + __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[120]; + __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ +} GPIO_Type; + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ +/*! @{ */ +#define GPIO_B_PBYTE_MASK (0x1U) +#define GPIO_B_PBYTE_SHIFT (0U) +#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) +/*! @} */ + +/* The count of GPIO_B */ +#define GPIO_B_COUNT (2U) + +/* The count of GPIO_B */ +#define GPIO_B_COUNT2 (32U) + +/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ +/*! @{ */ +#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) +#define GPIO_W_PWORD_SHIFT (0U) +#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) +/*! @} */ + +/* The count of GPIO_W */ +#define GPIO_W_COUNT (2U) + +/* The count of GPIO_W */ +#define GPIO_W_COUNT2 (32U) + +/*! @name DIR - Direction registers */ +/*! @{ */ +#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) +#define GPIO_DIR_DIRP_SHIFT (0U) +#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) +/*! @} */ + +/* The count of GPIO_DIR */ +#define GPIO_DIR_COUNT (2U) + +/*! @name MASK - Mask register */ +/*! @{ */ +#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) +#define GPIO_MASK_MASKP_SHIFT (0U) +#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) +/*! @} */ + +/* The count of GPIO_MASK */ +#define GPIO_MASK_COUNT (2U) + +/*! @name PIN - Port pin register */ +/*! @{ */ +#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) +#define GPIO_PIN_PORT_SHIFT (0U) +#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) +/*! @} */ + +/* The count of GPIO_PIN */ +#define GPIO_PIN_COUNT (2U) + +/*! @name MPIN - Masked port register */ +/*! @{ */ +#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) +#define GPIO_MPIN_MPORTP_SHIFT (0U) +#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) +/*! @} */ + +/* The count of GPIO_MPIN */ +#define GPIO_MPIN_COUNT (2U) + +/*! @name SET - Write: Set register for port Read: output bits for port */ +/*! @{ */ +#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) +#define GPIO_SET_SETP_SHIFT (0U) +#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) +/*! @} */ + +/* The count of GPIO_SET */ +#define GPIO_SET_COUNT (2U) + +/*! @name CLR - Clear port */ +/*! @{ */ +#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) +#define GPIO_CLR_CLRP_SHIFT (0U) +#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) +/*! @} */ + +/* The count of GPIO_CLR */ +#define GPIO_CLR_COUNT (2U) + +/*! @name NOT - Toggle port */ +/*! @{ */ +#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) +#define GPIO_NOT_NOTP_SHIFT (0U) +#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) +/*! @} */ + +/* The count of GPIO_NOT */ +#define GPIO_NOT_COUNT (2U) + +/*! @name DIRSET - Set pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) +#define GPIO_DIRSET_DIRSETP_SHIFT (0U) +#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) +/*! @} */ + +/* The count of GPIO_DIRSET */ +#define GPIO_DIRSET_COUNT (2U) + +/*! @name DIRCLR - Clear pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) +#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) +/*! @} */ + +/* The count of GPIO_DIRCLR */ +#define GPIO_DIRCLR_COUNT (2U) + +/*! @name DIRNOT - Toggle pin direction bits for port */ +/*! @{ */ +#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) +#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) +/*! @} */ + +/* The count of GPIO_DIRNOT */ +#define GPIO_DIRNOT_COUNT (2U) + + +/*! + * @} + */ /* end of group GPIO_Register_Masks */ + + +/* GPIO - Peripheral instance base addresses */ +/** Peripheral GPIO base address */ +#define GPIO_BASE (0x4008C000u) +/** Peripheral GPIO base pointer */ +#define GPIO ((GPIO_Type *)GPIO_BASE) +/** Array initializer of GPIO peripheral base addresses */ +#define GPIO_BASE_ADDRS { GPIO_BASE } +/** Array initializer of GPIO peripheral base pointers */ +#define GPIO_BASE_PTRS { GPIO } + +/*! + * @} + */ /* end of group GPIO_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2C Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer + * @{ + */ + +/** I2C - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2048]; + __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ + __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ + __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ + __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ + __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ + __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ + uint8_t RESERVED_1[4]; + __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ + __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ + __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ + uint8_t RESERVED_2[20]; + __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ + __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ + __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ + __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ + uint8_t RESERVED_3[36]; + __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ + uint8_t RESERVED_4[1912]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} I2C_Type; + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/*! @name CFG - Configuration for shared functions. */ +/*! @{ */ +#define I2C_CFG_MSTEN_MASK (0x1U) +#define I2C_CFG_MSTEN_SHIFT (0U) +/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. + * 0b0..Disabled. The I2C Master function is disabled. + * 0b1..Enabled. The I2C Master function is enabled. + */ +#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) +#define I2C_CFG_SLVEN_MASK (0x2U) +#define I2C_CFG_SLVEN_SHIFT (1U) +/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. + * 0b0..Disabled. The I2C slave function is disabled. + * 0b1..Enabled. The I2C slave function is enabled. + */ +#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) +#define I2C_CFG_MONEN_MASK (0x4U) +#define I2C_CFG_MONEN_SHIFT (2U) +/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. + * 0b0..Disabled. The I2C Monitor function is disabled. + * 0b1..Enabled. The I2C Monitor function is enabled. + */ +#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) +#define I2C_CFG_TIMEOUTEN_MASK (0x8U) +#define I2C_CFG_TIMEOUTEN_SHIFT (3U) +/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. + * 0b0..Disabled. Time-out function is disabled. + * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. + */ +#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) +#define I2C_CFG_MONCLKSTR_MASK (0x10U) +#define I2C_CFG_MONCLKSTR_SHIFT (4U) +/*! MONCLKSTR - Monitor function Clock Stretching. + * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. + * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. + */ +#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) +#define I2C_CFG_HSCAPABLE_MASK (0x20U) +#define I2C_CFG_HSCAPABLE_SHIFT (5U) +/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. + * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, + * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. + */ +#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) +/*! @} */ + +/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_STAT_MSTPENDING_MASK (0x1U) +#define I2C_STAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. + * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. + * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. + */ +#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) +#define I2C_STAT_MSTSTATE_MASK (0xEU) +#define I2C_STAT_MSTSTATE_SHIFT (1U) +/*! MSTSTATE - Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. + * 0b000..Idle. The Master function is available to be used for a new transaction. + * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. + * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. + * 0b011..NACK Address. Slave NACKed address. + * 0b100..NACK Data. Slave NACKed transmitted data. + */ +#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) +#define I2C_STAT_MSTARBLOSS_MASK (0x10U) +#define I2C_STAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Arbitration Loss has occurred. + * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. + */ +#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) +#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. + * 0b0..No Start/Stop Error has occurred. + * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. + */ +#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) +#define I2C_STAT_SLVPENDING_MASK (0x100U) +#define I2C_STAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. + * 0b0..In progress. The Slave function does not currently need service. + * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. + */ +#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) +#define I2C_STAT_SLVSTATE_MASK (0x600U) +#define I2C_STAT_SLVSTATE_SHIFT (9U) +/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. + * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. + * 0b01..Slave receive. Received data is available (Slave Receiver mode). + * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). + */ +#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) +#define I2C_STAT_SLVNOTSTR_MASK (0x800U) +#define I2C_STAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. + * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. + * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. + */ +#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) +#define I2C_STAT_SLVIDX_MASK (0x3000U) +#define I2C_STAT_SLVIDX_SHIFT (12U) +/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. + * 0b00..Address 0. Slave address 0 was matched. + * 0b01..Address 1. Slave address 1 was matched. + * 0b10..Address 2. Slave address 2 was matched. + * 0b11..Address 3. Slave address 3 was matched. + */ +#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) +#define I2C_STAT_SLVSEL_MASK (0x4000U) +#define I2C_STAT_SLVSEL_SHIFT (14U) +/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. + * 0b0..Not selected. The Slave function is not currently selected. + * 0b1..Selected. The Slave function is currently selected. + */ +#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) +#define I2C_STAT_SLVDESEL_MASK (0x8000U) +#define I2C_STAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. + * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. + * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. + */ +#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) +#define I2C_STAT_MONRDY_MASK (0x10000U) +#define I2C_STAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. + * 0b0..No data. The Monitor function does not currently have data available. + * 0b1..Data waiting. The Monitor function has data waiting to be read. + */ +#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) +#define I2C_STAT_MONOV_MASK (0x20000U) +#define I2C_STAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + * 0b0..No overrun. Monitor data has not overrun. + * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. + */ +#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) +#define I2C_STAT_MONACTIVE_MASK (0x40000U) +#define I2C_STAT_MONACTIVE_SHIFT (18U) +/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. + * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. + * 0b1..Active. The Monitor function considers the I2C bus to be active. + */ +#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) +#define I2C_STAT_MONIDLE_MASK (0x80000U) +#define I2C_STAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. + * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. + * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. + */ +#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) +#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. + * 0b0..No time-out. I2C bus events have not caused a time-out. + * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. + */ +#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) +#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. + * 0b0..No time-out. SCL low time has not caused a time-out. + * 0b1..Time-out. SCL low time has caused a time-out. + */ +#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable Set and read register. */ +/*! @{ */ +#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) +#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) +/*! MSTPENDINGEN - Master Pending interrupt Enable. + * 0b0..Disabled. The MstPending interrupt is disabled. + * 0b1..Enabled. The MstPending interrupt is enabled. + */ +#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) +#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) +#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) +/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. + * 0b0..Disabled. The MstArbLoss interrupt is disabled. + * 0b1..Enabled. The MstArbLoss interrupt is enabled. + */ +#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) +#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) +#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) +/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. + * 0b0..Disabled. The MstStStpErr interrupt is disabled. + * 0b1..Enabled. The MstStStpErr interrupt is enabled. + */ +#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) +#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) +#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) +/*! SLVPENDINGEN - Slave Pending interrupt Enable. + * 0b0..Disabled. The SlvPending interrupt is disabled. + * 0b1..Enabled. The SlvPending interrupt is enabled. + */ +#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) +#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) +#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) +/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. + * 0b0..Disabled. The SlvNotStr interrupt is disabled. + * 0b1..Enabled. The SlvNotStr interrupt is enabled. + */ +#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) +#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) +#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) +/*! SLVDESELEN - Slave Deselect interrupt Enable. + * 0b0..Disabled. The SlvDeSel interrupt is disabled. + * 0b1..Enabled. The SlvDeSel interrupt is enabled. + */ +#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) +#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) +#define I2C_INTENSET_MONRDYEN_SHIFT (16U) +/*! MONRDYEN - Monitor data Ready interrupt Enable. + * 0b0..Disabled. The MonRdy interrupt is disabled. + * 0b1..Enabled. The MonRdy interrupt is enabled. + */ +#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) +#define I2C_INTENSET_MONOVEN_MASK (0x20000U) +#define I2C_INTENSET_MONOVEN_SHIFT (17U) +/*! MONOVEN - Monitor Overrun interrupt Enable. + * 0b0..Disabled. The MonOv interrupt is disabled. + * 0b1..Enabled. The MonOv interrupt is enabled. + */ +#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) +#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) +#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) +/*! MONIDLEEN - Monitor Idle interrupt Enable. + * 0b0..Disabled. The MonIdle interrupt is disabled. + * 0b1..Enabled. The MonIdle interrupt is enabled. + */ +#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) +#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) +#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) +/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. + * 0b0..Disabled. The Event time-out interrupt is disabled. + * 0b1..Enabled. The Event time-out interrupt is enabled. + */ +#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) +#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) +#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) +/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. + * 0b0..Disabled. The SCL time-out interrupt is disabled. + * 0b1..Enabled. The SCL time-out interrupt is enabled. + */ +#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. */ +/*! @{ */ +#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) +#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) +#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) +#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) +#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) +#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) +#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) +#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) +#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) +#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) +#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) +#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) +#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) +#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) +#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) +#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) +#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) +#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) +#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) +#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) +/*! @} */ + +/*! @name TIMEOUT - Time-out value register. */ +/*! @{ */ +#define I2C_TIMEOUT_TOMIN_MASK (0xFU) +#define I2C_TIMEOUT_TOMIN_SHIFT (0U) +#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) +#define I2C_TIMEOUT_TO_MASK (0xFFF0U) +#define I2C_TIMEOUT_TO_SHIFT (4U) +#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) +/*! @} */ + +/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ +/*! @{ */ +#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) +#define I2C_CLKDIV_DIVVAL_SHIFT (0U) +#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ +/*! @{ */ +#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) +#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) +#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) +#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) +#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) +#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) +#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) +#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) +#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) +#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) +#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) +#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) +#define I2C_INTSTAT_MONRDY_MASK (0x10000U) +#define I2C_INTSTAT_MONRDY_SHIFT (16U) +#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) +#define I2C_INTSTAT_MONOV_MASK (0x20000U) +#define I2C_INTSTAT_MONOV_SHIFT (17U) +#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) +#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) +#define I2C_INTSTAT_MONIDLE_SHIFT (19U) +#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) +#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) +#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) +#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) +#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) +/*! @} */ + +/*! @name MSTCTL - Master control register. */ +/*! @{ */ +#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) +#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) +/*! MSTCONTINUE - Master Continue. This bit is write-only. + * 0b0..No effect. + * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. + */ +#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) +#define I2C_MSTCTL_MSTSTART_MASK (0x2U) +#define I2C_MSTCTL_MSTSTART_SHIFT (1U) +/*! MSTSTART - Master Start control. This bit is write-only. + * 0b0..No effect. + * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. + */ +#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) +#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) +#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) +/*! MSTSTOP - Master Stop control. This bit is write-only. + * 0b0..No effect. + * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). + */ +#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) +#define I2C_MSTCTL_MSTDMA_MASK (0x8U) +#define I2C_MSTCTL_MSTDMA_SHIFT (3U) +/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. + * 0b0..Disable. No DMA requests are generated for master operation. + * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. + */ +#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) +/*! @} */ + +/*! @name MSTTIME - Master timing configuration. */ +/*! @{ */ +#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) +#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) +/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. + * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. + * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) +#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) +#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) +/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. + * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. + * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . + * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. + * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. + * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. + * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. + * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. + * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. + */ +#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) +/*! @} */ + +/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ +/*! @{ */ +#define I2C_MSTDAT_DATA_MASK (0xFFU) +#define I2C_MSTDAT_DATA_SHIFT (0U) +#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVCTL - Slave control register. */ +/*! @{ */ +#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) +#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) +/*! SLVCONTINUE - Slave Continue. + * 0b0..No effect. + * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. + */ +#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) +#define I2C_SLVCTL_SLVNACK_MASK (0x2U) +#define I2C_SLVCTL_SLVNACK_SHIFT (1U) +/*! SLVNACK - Slave NACK. + * 0b0..No effect. + * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). + */ +#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) +#define I2C_SLVCTL_SLVDMA_MASK (0x8U) +#define I2C_SLVCTL_SLVDMA_SHIFT (3U) +/*! SLVDMA - Slave DMA enable. + * 0b0..Disabled. No DMA requests are issued for Slave mode operation. + * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. + */ +#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) +#define I2C_SLVCTL_AUTOACK_MASK (0x100U) +#define I2C_SLVCTL_AUTOACK_SHIFT (8U) +/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. + * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). + * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. + */ +#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) +#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) +#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) +/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. + * 0b0..The expected next operation in Automatic Mode is an I2C write. + * 0b1..The expected next operation in Automatic Mode is an I2C read. + */ +#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) +/*! @} */ + +/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ +/*! @{ */ +#define I2C_SLVDAT_DATA_MASK (0xFFU) +#define I2C_SLVDAT_DATA_SHIFT (0U) +#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) +/*! @} */ + +/*! @name SLVADR - Slave address register. */ +/*! @{ */ +#define I2C_SLVADR_SADISABLE_MASK (0x1U) +#define I2C_SLVADR_SADISABLE_SHIFT (0U) +/*! SADISABLE - Slave Address n Disable. + * 0b0..Enabled. Slave Address n is enabled. + * 0b1..Ignored Slave Address n is ignored. + */ +#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) +#define I2C_SLVADR_SLVADR_MASK (0xFEU) +#define I2C_SLVADR_SLVADR_SHIFT (1U) +#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) +#define I2C_SLVADR_AUTONACK_MASK (0x8000U) +#define I2C_SLVADR_AUTONACK_SHIFT (15U) +/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. + * 0b0..Normal operation, matching I2C addresses are not ignored. + * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. + */ +#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) +/*! @} */ + +/* The count of I2C_SLVADR */ +#define I2C_SLVADR_COUNT (4U) + +/*! @name SLVQUAL0 - Slave Qualification for address 0. */ +/*! @{ */ +#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) +#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) +/*! QUALMODE0 - Qualify mode for slave address 0. + * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. + * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. + */ +#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) +#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) +#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) +/*! @} */ + +/*! @name MONRXDAT - Monitor receiver data register. */ +/*! @{ */ +#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) +#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) +#define I2C_MONRXDAT_MONSTART_MASK (0x100U) +#define I2C_MONRXDAT_MONSTART_SHIFT (8U) +/*! MONSTART - Monitor Received Start. + * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. + * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) +#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) +#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) +/*! MONRESTART - Monitor Received Repeated Start. + * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. + * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. + */ +#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) +#define I2C_MONRXDAT_MONNACK_MASK (0x400U) +#define I2C_MONRXDAT_MONNACK_SHIFT (10U) +/*! MONNACK - Monitor Received NACK. + * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. + * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. + */ +#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define I2C_ID_APERTURE_MASK (0xFFU) +#define I2C_ID_APERTURE_SHIFT (0U) +#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) +#define I2C_ID_MINOR_REV_MASK (0xF00U) +#define I2C_ID_MINOR_REV_SHIFT (8U) +#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) +#define I2C_ID_MAJOR_REV_MASK (0xF000U) +#define I2C_ID_MAJOR_REV_SHIFT (12U) +#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) +#define I2C_ID_ID_MASK (0xFFFF0000U) +#define I2C_ID_ID_SHIFT (16U) +#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2C_Register_Masks */ + + +/* I2C - Peripheral instance base addresses */ +/** Peripheral I2C0 base address */ +#define I2C0_BASE (0x40086000u) +/** Peripheral I2C0 base pointer */ +#define I2C0 ((I2C_Type *)I2C0_BASE) +/** Peripheral I2C1 base address */ +#define I2C1_BASE (0x40087000u) +/** Peripheral I2C1 base pointer */ +#define I2C1 ((I2C_Type *)I2C1_BASE) +/** Peripheral I2C2 base address */ +#define I2C2_BASE (0x40088000u) +/** Peripheral I2C2 base pointer */ +#define I2C2 ((I2C_Type *)I2C2_BASE) +/** Peripheral I2C3 base address */ +#define I2C3_BASE (0x40089000u) +/** Peripheral I2C3 base pointer */ +#define I2C3 ((I2C_Type *)I2C3_BASE) +/** Peripheral I2C4 base address */ +#define I2C4_BASE (0x4008A000u) +/** Peripheral I2C4 base pointer */ +#define I2C4 ((I2C_Type *)I2C4_BASE) +/** Peripheral I2C5 base address */ +#define I2C5_BASE (0x40096000u) +/** Peripheral I2C5 base pointer */ +#define I2C5 ((I2C_Type *)I2C5_BASE) +/** Peripheral I2C6 base address */ +#define I2C6_BASE (0x40097000u) +/** Peripheral I2C6 base pointer */ +#define I2C6 ((I2C_Type *)I2C6_BASE) +/** Peripheral I2C7 base address */ +#define I2C7_BASE (0x40098000u) +/** Peripheral I2C7 base pointer */ +#define I2C7 ((I2C_Type *)I2C7_BASE) +/** Array initializer of I2C peripheral base addresses */ +#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } +/** Array initializer of I2C peripheral base pointers */ +#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } +/** Interrupt vectors for the I2C peripheral type */ +#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2C_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- I2S Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer + * @{ + */ + +/** I2S - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[3072]; + __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ + __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ + __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ + uint8_t RESERVED_2[480]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ + uint8_t RESERVED_5[8]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ + uint8_t RESERVED_6[8]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ + uint8_t RESERVED_7[436]; + __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ +} I2S_Type; + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG1_MAINENABLE_MASK (0x1U) +#define I2S_CFG1_MAINENABLE_SHIFT (0U) +/*! MAINENABLE - Main enable for I 2S function in this Flexcomm + * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. + * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. + */ +#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) +#define I2S_CFG1_DATAPAUSE_MASK (0x2U) +#define I2S_CFG1_DATAPAUSE_SHIFT (1U) +/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. + * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. + * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. + */ +#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) +#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) +#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) +/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. + * 0b00..1 I2S channel pairs in this flexcomm + * 0b01..2 I2S channel pairs in this flexcomm + * 0b10..3 I2S channel pairs in this flexcomm + * 0b11..4 I2S channel pairs in this flexcomm + */ +#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) +#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) +#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) +/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. + * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. + * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. + * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. + * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. + */ +#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) +#define I2S_CFG1_MODE_MASK (0xC0U) +#define I2S_CFG1_MODE_SHIFT (6U) +/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. + * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. + * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. + * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. + * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. + */ +#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) +#define I2S_CFG1_RIGHTLOW_MASK (0x100U) +#define I2S_CFG1_RIGHTLOW_SHIFT (8U) +/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. + * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. + * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. + */ +#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) +#define I2S_CFG1_LEFTJUST_MASK (0x200U) +#define I2S_CFG1_LEFTJUST_SHIFT (9U) +/*! LEFTJUST - Left Justify data. + * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. + * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. + */ +#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) +#define I2S_CFG1_ONECHANNEL_MASK (0x400U) +#define I2S_CFG1_ONECHANNEL_SHIFT (10U) +/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. + * 0b0..I2S data for this channel pair is treated as left and right channels. + * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. + */ +#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) +#define I2S_CFG1_SCK_POL_MASK (0x1000U) +#define I2S_CFG1_SCK_POL_SHIFT (12U) +/*! SCK_POL - SCK polarity. + * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). + * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. + */ +#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) +#define I2S_CFG1_WS_POL_MASK (0x2000U) +#define I2S_CFG1_WS_POL_SHIFT (13U) +/*! WS_POL - WS polarity. + * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). + * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). + */ +#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) +#define I2S_CFG1_DATALEN_MASK (0x1F0000U) +#define I2S_CFG1_DATALEN_SHIFT (16U) +#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) +/*! @} */ + +/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ +/*! @{ */ +#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) +#define I2S_CFG2_FRAMELEN_SHIFT (0U) +#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) +#define I2S_CFG2_POSITION_MASK (0x1FF0000U) +#define I2S_CFG2_POSITION_SHIFT (16U) +#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) +/*! @} */ + +/*! @name STAT - Status register for the primary channel pair. */ +/*! @{ */ +#define I2S_STAT_BUSY_MASK (0x1U) +#define I2S_STAT_BUSY_SHIFT (0U) +/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. + * 0b0..The transmitter/receiver for channel pair is currently idle. + * 0b1..The transmitter/receiver for channel pair is currently processing data. + */ +#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) +#define I2S_STAT_SLVFRMERR_MASK (0x2U) +#define I2S_STAT_SLVFRMERR_SHIFT (1U) +/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. + * 0b0..No error has been recorded. + * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. + */ +#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) +#define I2S_STAT_LR_MASK (0x4U) +#define I2S_STAT_LR_SHIFT (2U) +/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. + * 0b0..Left channel. + * 0b1..Right channel. + */ +#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) +#define I2S_STAT_DATAPAUSED_MASK (0x8U) +#define I2S_STAT_DATAPAUSED_SHIFT (3U) +/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels + * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. + * 0b1..A data pause has been requested and is now in force. + */ +#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) +/*! @} */ + +/*! @name DIV - Clock divider, used by all channel pairs. */ +/*! @{ */ +#define I2S_DIV_DIV_MASK (0xFFFU) +#define I2S_DIV_DIV_SHIFT (0U) +#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) +#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) +#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) +#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) +#define I2S_FIFOCFG_TXI2SSE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SSE0_SHIFT (2U) +/*! TXI2SSE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. + * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. + * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. + */ +#define I2S_FIFOCFG_TXI2SSE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SSE0_SHIFT)) & I2S_FIFOCFG_TXI2SSE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. + * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. + * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. + */ +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) +#define I2S_FIFOCFG_SIZE_MASK (0x30U) +#define I2S_FIFOCFG_SIZE_SHIFT (4U) +#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) +#define I2S_FIFOCFG_DMATX_MASK (0x1000U) +#define I2S_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) +#define I2S_FIFOCFG_DMARX_MASK (0x2000U) +#define I2S_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) +#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) +#define I2S_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) +#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) +#define I2S_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) +#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) +#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define I2S_FIFOSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) +#define I2S_FIFOSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) +#define I2S_FIFOSTAT_PERINT_MASK (0x8U) +#define I2S_FIFOSTAT_PERINT_SHIFT (3U) +#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) +#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) +#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) +#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) +#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) +#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) +#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) +#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) +#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) +#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) +#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) +#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) +#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) +#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) +#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) +#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) +#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) +#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) +#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) +#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) +#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) +#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) +#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) +#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) +#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) +#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) +#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) +#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) +#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFOWR_TXDATA_SHIFT (0U) +#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) +#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORD_RXDATA_SHIFT (0U) +#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48H_RXDATA_SHIFT (0U) +#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) +#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ +/*! @{ */ +#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) +#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) +/*! @} */ + +/*! @name ID - I2S Module identification */ +/*! @{ */ +#define I2S_ID_Aperture_MASK (0xFFU) +#define I2S_ID_Aperture_SHIFT (0U) +#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK) +#define I2S_ID_Minor_Rev_MASK (0xF00U) +#define I2S_ID_Minor_Rev_SHIFT (8U) +#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK) +#define I2S_ID_Major_Rev_MASK (0xF000U) +#define I2S_ID_Major_Rev_SHIFT (12U) +#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK) +#define I2S_ID_ID_MASK (0xFFFF0000U) +#define I2S_ID_ID_SHIFT (16U) +#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group I2S_Register_Masks */ + + +/* I2S - Peripheral instance base addresses */ +/** Peripheral I2S0 base address */ +#define I2S0_BASE (0x40097000u) +/** Peripheral I2S0 base pointer */ +#define I2S0 ((I2S_Type *)I2S0_BASE) +/** Peripheral I2S1 base address */ +#define I2S1_BASE (0x40098000u) +/** Peripheral I2S1 base pointer */ +#define I2S1 ((I2S_Type *)I2S1_BASE) +/** Array initializer of I2S peripheral base addresses */ +#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } +/** Array initializer of I2S peripheral base pointers */ +#define I2S_BASE_PTRS { I2S0, I2S1 } +/** Interrupt vectors for the I2S peripheral type */ +#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group I2S_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer + * @{ + */ + +/** INPUTMUX - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[192]; + __IO uint32_t PINTSEL[4]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DMA_ITRIG_INMUX[22]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */ + uint8_t RESERVED_2[40]; + __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */ + uint8_t RESERVED_3[16]; + __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ + __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ +} INPUTMUX_Type; + +/* ---------------------------------------------------------------------------- + -- INPUTMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks + * @{ + */ + +/*! @name PINTSEL - Pin interrupt select register */ +/*! @{ */ +#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) +#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) +/*! @} */ + +/* The count of INPUTMUX_PINTSEL */ +#define INPUTMUX_PINTSEL_COUNT (4U) + +/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ +/*! @{ */ +#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA_ITRIG_INMUX */ +#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U) + +/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ +/*! @{ */ +#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) +#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) +#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) +/*! @} */ + +/* The count of INPUTMUX_DMA_OTRIG_INMUX */ +#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) + +/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) +/*! @} */ + +/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ +/*! @{ */ +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group INPUTMUX_Register_Masks */ + + +/* INPUTMUX - Peripheral instance base addresses */ +/** Peripheral INPUTMUX base address */ +#define INPUTMUX_BASE (0x40005000u) +/** Peripheral INPUTMUX base pointer */ +#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) +/** Array initializer of INPUTMUX peripheral base addresses */ +#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } +/** Array initializer of INPUTMUX peripheral base pointers */ +#define INPUTMUX_BASE_PTRS { INPUTMUX } + +/*! + * @} + */ /* end of group INPUTMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- IOCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer + * @{ + */ + +/** IOCON - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ +} IOCON_Type; + +/* ---------------------------------------------------------------------------- + -- IOCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOCON_Register_Masks IOCON Register Masks + * @{ + */ + +/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ +/*! @{ */ +#define IOCON_PIO_FUNC_MASK (0x7U) +#define IOCON_PIO_FUNC_SHIFT (0U) +/*! FUNC - Selects pin function. + * 0b000..Alternative connection 0. + * 0b001..Alternative connection 1. + * 0b010..Alternative connection 2. + * 0b011..Alternative connection 3. + * 0b100..Alternative connection 4. + * 0b101..Alternative connection 5. + * 0b110..Alternative connection 6. + * 0b111..Alternative connection 7. + */ +#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) +#define IOCON_PIO_MODE_MASK (0x18U) +#define IOCON_PIO_MODE_SHIFT (3U) +/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). + * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). + * 0b01..Pull-down. Pull-down resistor enabled. + * 0b10..Pull-up. Pull-up resistor enabled. + * 0b11..Repeater. Repeater mode. + */ +#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) +#define IOCON_PIO_I2CSLEW_MASK (0x20U) +#define IOCON_PIO_I2CSLEW_SHIFT (5U) +/*! I2CSLEW - Controls slew rate of I2C pin. + * 0b0..I2C mode. + * 0b1..GPIO mode. + */ +#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK) +#define IOCON_PIO_INVERT_MASK (0x40U) +#define IOCON_PIO_INVERT_SHIFT (6U) +/*! INVERT - Input polarity. + * 0b0..Disabled. Input function is not inverted. + * 0b1..Enabled. Input is function inverted. + */ +#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) +#define IOCON_PIO_DIGIMODE_MASK (0x80U) +#define IOCON_PIO_DIGIMODE_SHIFT (7U) +/*! DIGIMODE - Select Analog/Digital mode. + * 0b0..Analog mode. + * 0b1..Digital mode. + */ +#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) +#define IOCON_PIO_FILTEROFF_MASK (0x100U) +#define IOCON_PIO_FILTEROFF_SHIFT (8U) +/*! FILTEROFF - Controls input glitch filter. + * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out. + * 0b1..Filter disabled. No input filtering is done. + */ +#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) +#define IOCON_PIO_I2CDRIVE_MASK (0x200U) +#define IOCON_PIO_I2CDRIVE_SHIFT (9U) +/*! I2CDRIVE - Controls the current sink capability of the pin. + * 0b0..Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. + * 0b1..High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details. + */ +#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK) +#define IOCON_PIO_SLEW_MASK (0x200U) +#define IOCON_PIO_SLEW_SHIFT (9U) +/*! SLEW - Driver slew rate. + * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + */ +#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) +#define IOCON_PIO_I2CFILTER_MASK (0x400U) +#define IOCON_PIO_I2CFILTER_SHIFT (10U) +/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. + * 0b0..Enabled. I2C 50 ns glitch filter enabled. + * 0b1..Disabled. I2C 50 ns glitch filter disabled. + */ +#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) +#define IOCON_PIO_OD_MASK (0x400U) +#define IOCON_PIO_OD_SHIFT (10U) +/*! OD - Controls open-drain mode. + * 0b0..Normal. Normal push-pull output + * 0b1..Open-drain. Simulated open-drain output (high drive disabled). + */ +#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) +/*! @} */ + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT (2U) + +/* The count of IOCON_PIO */ +#define IOCON_PIO_COUNT2 (32U) + + +/*! + * @} + */ /* end of group IOCON_Register_Masks */ + + +/* IOCON - Peripheral instance base addresses */ +/** Peripheral IOCON base address */ +#define IOCON_BASE (0x40001000u) +/** Peripheral IOCON base pointer */ +#define IOCON ((IOCON_Type *)IOCON_BASE) +/** Array initializer of IOCON peripheral base addresses */ +#define IOCON_BASE_ADDRS { IOCON_BASE } +/** Array initializer of IOCON peripheral base pointers */ +#define IOCON_BASE_PTRS { IOCON } + +/*! + * @} + */ /* end of group IOCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- MRT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer + * @{ + */ + +/** MRT - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ + __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ + __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ + __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ + } CHANNEL[4]; + uint8_t RESERVED_0[176]; + __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ + __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ + __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ +} MRT_Type; + +/* ---------------------------------------------------------------------------- + -- MRT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MRT_Register_Masks MRT Register Masks + * @{ + */ + +/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ +/*! @{ */ +#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) +#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) +#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) +/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. + * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. + * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. + */ +#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_INTVAL */ +#define MRT_CHANNEL_INTVAL_COUNT (4U) + +/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ +/*! @{ */ +#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) +#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_TIMER */ +#define MRT_CHANNEL_TIMER_COUNT (4U) + +/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ +/*! @{ */ +#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) +#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) +/*! INTEN - Enable the TIMERn interrupt. + * 0b0..Disabled. TIMERn interrupt is disabled. + * 0b1..Enabled. TIMERn interrupt is enabled. + */ +#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) +#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) +#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) +/*! MODE - Selects timer mode. + * 0b00..Repeat interrupt mode. + * 0b01..One-shot interrupt mode. + * 0b10..One-shot stall mode. + * 0b11..Reserved. + */ +#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_CTRL */ +#define MRT_CHANNEL_CTRL_COUNT (4U) + +/*! @name CHANNEL_STAT - MRT Status register. */ +/*! @{ */ +#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) +#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) +/*! INTFLAG - Monitors the interrupt flag. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) +#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) +#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) +/*! RUN - Indicates the state of TIMERn. This bit is read-only. + * 0b0..Idle state. TIMERn is stopped. + * 0b1..Running. TIMERn is running. + */ +#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) +#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) +#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) +/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. + * 0b0..This channel is not in use. + * 0b1..This channel is in use. + */ +#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) +/*! @} */ + +/* The count of MRT_CHANNEL_STAT */ +#define MRT_CHANNEL_STAT_COUNT (4U) + +/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ +/*! @{ */ +#define MRT_MODCFG_NOC_MASK (0xFU) +#define MRT_MODCFG_NOC_SHIFT (0U) +#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) +#define MRT_MODCFG_NOB_MASK (0x1F0U) +#define MRT_MODCFG_NOB_SHIFT (4U) +#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) +#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) +#define MRT_MODCFG_MULTITASK_SHIFT (31U) +/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. + * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. + * 0b1..Multi-task mode. + */ +#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) +/*! @} */ + +/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ +/*! @{ */ +#define MRT_IDLE_CH_CHAN_MASK (0xF0U) +#define MRT_IDLE_CH_CHAN_SHIFT (4U) +#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) +/*! @} */ + +/*! @name IRQ_FLAG - Global interrupt flag register */ +/*! @{ */ +#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) +#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) +/*! GFLAG0 - Monitors the interrupt flag of TIMER0. + * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. + * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. + */ +#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) +#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) +#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) +#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) +#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) +#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) +#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group MRT_Register_Masks */ + + +/* MRT - Peripheral instance base addresses */ +/** Peripheral MRT0 base address */ +#define MRT0_BASE (0x4000D000u) +/** Peripheral MRT0 base pointer */ +#define MRT0 ((MRT_Type *)MRT0_BASE) +/** Array initializer of MRT peripheral base addresses */ +#define MRT_BASE_ADDRS { MRT0_BASE } +/** Array initializer of MRT peripheral base pointers */ +#define MRT_BASE_PTRS { MRT0 } +/** Interrupt vectors for the MRT peripheral type */ +#define MRT_IRQS { MRT0_IRQn } + +/*! + * @} + */ /* end of group MRT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- PINT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer + * @{ + */ + +/** PINT - Register Layout Typedef */ +typedef struct { + __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ + __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ + __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ + __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ + __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ + __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ + __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ + __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ + __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ + __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ + __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ + __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ + __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ +} PINT_Type; + +/* ---------------------------------------------------------------------------- + -- PINT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PINT_Register_Masks PINT Register Masks + * @{ + */ + +/*! @name ISEL - Pin Interrupt Mode register */ +/*! @{ */ +#define PINT_ISEL_PMODE_MASK (0xFFU) +#define PINT_ISEL_PMODE_SHIFT (0U) +#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) +/*! @} */ + +/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ +/*! @{ */ +#define PINT_IENR_ENRL_MASK (0xFFU) +#define PINT_IENR_ENRL_SHIFT (0U) +#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) +/*! @} */ + +/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ +/*! @{ */ +#define PINT_SIENR_SETENRL_MASK (0xFFU) +#define PINT_SIENR_SETENRL_SHIFT (0U) +#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) +/*! @} */ + +/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ +/*! @{ */ +#define PINT_CIENR_CENRL_MASK (0xFFU) +#define PINT_CIENR_CENRL_SHIFT (0U) +#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) +/*! @} */ + +/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ +/*! @{ */ +#define PINT_IENF_ENAF_MASK (0xFFU) +#define PINT_IENF_ENAF_SHIFT (0U) +#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) +/*! @} */ + +/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ +/*! @{ */ +#define PINT_SIENF_SETENAF_MASK (0xFFU) +#define PINT_SIENF_SETENAF_SHIFT (0U) +#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) +/*! @} */ + +/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ +/*! @{ */ +#define PINT_CIENF_CENAF_MASK (0xFFU) +#define PINT_CIENF_CENAF_SHIFT (0U) +#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) +/*! @} */ + +/*! @name RISE - Pin interrupt rising edge register */ +/*! @{ */ +#define PINT_RISE_RDET_MASK (0xFFU) +#define PINT_RISE_RDET_SHIFT (0U) +#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) +/*! @} */ + +/*! @name FALL - Pin interrupt falling edge register */ +/*! @{ */ +#define PINT_FALL_FDET_MASK (0xFFU) +#define PINT_FALL_FDET_SHIFT (0U) +#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) +/*! @} */ + +/*! @name IST - Pin interrupt status register */ +/*! @{ */ +#define PINT_IST_PSTAT_MASK (0xFFU) +#define PINT_IST_PSTAT_SHIFT (0U) +#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) +/*! @} */ + +/*! @name PMCTRL - Pattern match interrupt control register */ +/*! @{ */ +#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) +#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) +/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. + * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. + * 0b1..Pattern match. Interrupts are driven in response to pattern matches. + */ +#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) +#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) +#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) +/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. + * 0b0..Disabled. RXEV output to the CPU is disabled. + * 0b1..Enabled. RXEV output to the CPU is enabled. + */ +#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) +#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) +#define PINT_PMCTRL_PMAT_SHIFT (24U) +#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) +/*! @} */ + +/*! @name PMSRC - Pattern match interrupt bit-slice source register */ +/*! @{ */ +#define PINT_PMSRC_SRC0_MASK (0x700U) +#define PINT_PMSRC_SRC0_SHIFT (8U) +/*! SRC0 - Selects the input source for bit slice 0 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. + */ +#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) +#define PINT_PMSRC_SRC1_MASK (0x3800U) +#define PINT_PMSRC_SRC1_SHIFT (11U) +/*! SRC1 - Selects the input source for bit slice 1 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. + */ +#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) +#define PINT_PMSRC_SRC2_MASK (0x1C000U) +#define PINT_PMSRC_SRC2_SHIFT (14U) +/*! SRC2 - Selects the input source for bit slice 2 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. + */ +#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) +#define PINT_PMSRC_SRC3_MASK (0xE0000U) +#define PINT_PMSRC_SRC3_SHIFT (17U) +/*! SRC3 - Selects the input source for bit slice 3 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. + */ +#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) +#define PINT_PMSRC_SRC4_MASK (0x700000U) +#define PINT_PMSRC_SRC4_SHIFT (20U) +/*! SRC4 - Selects the input source for bit slice 4 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. + */ +#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) +#define PINT_PMSRC_SRC5_MASK (0x3800000U) +#define PINT_PMSRC_SRC5_SHIFT (23U) +/*! SRC5 - Selects the input source for bit slice 5 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. + */ +#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) +#define PINT_PMSRC_SRC6_MASK (0x1C000000U) +#define PINT_PMSRC_SRC6_SHIFT (26U) +/*! SRC6 - Selects the input source for bit slice 6 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. + */ +#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) +#define PINT_PMSRC_SRC7_MASK (0xE0000000U) +#define PINT_PMSRC_SRC7_SHIFT (29U) +/*! SRC7 - Selects the input source for bit slice 7 + * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. + * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. + * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. + * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. + * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. + * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. + * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. + * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. + */ +#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) +/*! @} */ + +/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ +/*! @{ */ +#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) +#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) +/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. + * 0b0..No effect. Slice 0 is not an endpoint. + * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) +#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) +#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) +/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. + * 0b0..No effect. Slice 1 is not an endpoint. + * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) +#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) +#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) +/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. + * 0b0..No effect. Slice 2 is not an endpoint. + * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) +#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) +#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) +/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. + * 0b0..No effect. Slice 3 is not an endpoint. + * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) +#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) +#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) +/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. + * 0b0..No effect. Slice 4 is not an endpoint. + * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) +#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) +#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) +/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. + * 0b0..No effect. Slice 5 is not an endpoint. + * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) +#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) +#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) +/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. + * 0b0..No effect. Slice 6 is not an endpoint. + * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. + */ +#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) +#define PINT_PMCFG_CFG0_MASK (0x700U) +#define PINT_PMCFG_CFG0_SHIFT (8U) +/*! CFG0 - Specifies the match contribution condition for bit slice 0. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) +#define PINT_PMCFG_CFG1_MASK (0x3800U) +#define PINT_PMCFG_CFG1_SHIFT (11U) +/*! CFG1 - Specifies the match contribution condition for bit slice 1. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) +#define PINT_PMCFG_CFG2_MASK (0x1C000U) +#define PINT_PMCFG_CFG2_SHIFT (14U) +/*! CFG2 - Specifies the match contribution condition for bit slice 2. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) +#define PINT_PMCFG_CFG3_MASK (0xE0000U) +#define PINT_PMCFG_CFG3_SHIFT (17U) +/*! CFG3 - Specifies the match contribution condition for bit slice 3. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) +#define PINT_PMCFG_CFG4_MASK (0x700000U) +#define PINT_PMCFG_CFG4_SHIFT (20U) +/*! CFG4 - Specifies the match contribution condition for bit slice 4. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) +#define PINT_PMCFG_CFG5_MASK (0x3800000U) +#define PINT_PMCFG_CFG5_SHIFT (23U) +/*! CFG5 - Specifies the match contribution condition for bit slice 5. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) +#define PINT_PMCFG_CFG6_MASK (0x1C000000U) +#define PINT_PMCFG_CFG6_SHIFT (26U) +/*! CFG6 - Specifies the match contribution condition for bit slice 6. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) +#define PINT_PMCFG_CFG7_MASK (0xE0000000U) +#define PINT_PMCFG_CFG7_SHIFT (29U) +/*! CFG7 - Specifies the match contribution condition for bit slice 7. + * 0b000..Constant HIGH. This bit slice always contributes to a product term match. + * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. + * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. + * 0b101..Low level. Match occurs when there is a low level on the specified input. + * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). + * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. + */ +#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group PINT_Register_Masks */ + + +/* PINT - Peripheral instance base addresses */ +/** Peripheral PINT base address */ +#define PINT_BASE (0x40004000u) +/** Peripheral PINT base pointer */ +#define PINT ((PINT_Type *)PINT_BASE) +/** Array initializer of PINT peripheral base addresses */ +#define PINT_BASE_ADDRS { PINT_BASE } +/** Array initializer of PINT peripheral base pointers */ +#define PINT_BASE_PTRS { PINT } +/** Interrupt vectors for the PINT peripheral type */ +#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn } + +/*! + * @} + */ /* end of group PINT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- RTC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer + * @{ + */ + +/** RTC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ + __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ + __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ + __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ +} RTC_Type; + +/* ---------------------------------------------------------------------------- + -- RTC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RTC_Register_Masks RTC Register Masks + * @{ + */ + +/*! @name CTRL - RTC control register */ +/*! @{ */ +#define RTC_CTRL_SWRESET_MASK (0x1U) +#define RTC_CTRL_SWRESET_SHIFT (0U) +/*! SWRESET - Software reset control + * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. + * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. + */ +#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) +#define RTC_CTRL_ALARM1HZ_MASK (0x4U) +#define RTC_CTRL_ALARM1HZ_SHIFT (2U) +/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. + * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. + * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) +#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) +#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) +/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. + * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. + * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. + */ +#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) +#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) +#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) +/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. + * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) +#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) +#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) +/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. + */ +#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) +#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) +#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) +/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). + * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. + * 0b1..Enable. The 1 kHz RTC timer is enabled. + */ +#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) +#define RTC_CTRL_RTC_EN_MASK (0x80U) +#define RTC_CTRL_RTC_EN_SHIFT (7U) +/*! RTC_EN - RTC enable. + * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. + * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. + */ +#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) +#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) +#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) +/*! RTC_OSC_PD - RTC oscillator power-down control. + * 0b0..RTC oscillator is powered-up and can output a clock if a crystal is correctly connected externally + * 0b1..RTC oscillator is powered-down. + */ +#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) +/*! @} */ + +/*! @name MATCH - RTC match register */ +/*! @{ */ +#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) +#define RTC_MATCH_MATVAL_SHIFT (0U) +#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) +/*! @} */ + +/*! @name COUNT - RTC counter register */ +/*! @{ */ +#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) +#define RTC_COUNT_VAL_SHIFT (0U) +#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) +/*! @} */ + +/*! @name WAKE - High-resolution/wake-up timer control register */ +/*! @{ */ +#define RTC_WAKE_VAL_MASK (0xFFFFU) +#define RTC_WAKE_VAL_SHIFT (0U) +#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group RTC_Register_Masks */ + + +/* RTC - Peripheral instance base addresses */ +/** Peripheral RTC base address */ +#define RTC_BASE (0x4002C000u) +/** Peripheral RTC base pointer */ +#define RTC ((RTC_Type *)RTC_BASE) +/** Array initializer of RTC peripheral base addresses */ +#define RTC_BASE_ADDRS { RTC_BASE } +/** Array initializer of RTC peripheral base pointers */ +#define RTC_BASE_PTRS { RTC } +/** Interrupt vectors for the RTC peripheral type */ +#define RTC_IRQS { RTC_IRQn } + +/*! + * @} + */ /* end of group RTC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SCT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer + * @{ + */ + +/** SCT - Register Layout Typedef */ +typedef struct { + __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + uint8_t RESERVED_0[40]; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ + __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ + __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ + __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ + uint8_t RESERVED_1[140]; + __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ + __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ + __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ + __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ + union { /* offset: 0x100 */ + __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; + uint8_t RESERVED_2[216]; + union { /* offset: 0x200 */ + __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; + uint8_t RESERVED_3[216]; + struct { /* offset: 0x300, array step: 0x8 */ + __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ + __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ + } EVENT[10]; + uint8_t RESERVED_4[432]; + struct { /* offset: 0x500, array step: 0x8 */ + __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ + __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ + } OUT[8]; +} SCT_Type; + +/* ---------------------------------------------------------------------------- + -- SCT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SCT_Register_Masks SCT Register Masks + * @{ + */ + +/*! @name CONFIG - SCT configuration register */ +/*! @{ */ +#define SCT_CONFIG_UNIFY_MASK (0x1U) +#define SCT_CONFIG_UNIFY_SHIFT (0U) +/*! UNIFY - SCT operation + * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. + * 0b1..The SCT operates as a unified 32-bit counter. + */ +#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) +#define SCT_CONFIG_CLKMODE_MASK (0x6U) +#define SCT_CONFIG_CLKMODE_SHIFT (1U) +/*! CLKMODE - SCT clock mode + * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. + * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. + * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. + * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. + */ +#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) +#define SCT_CONFIG_CKSEL_MASK (0x78U) +#define SCT_CONFIG_CKSEL_SHIFT (3U) +/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. + * 0b0000..Rising edges on input 0. + * 0b0001..Falling edges on input 0. + * 0b0010..Rising edges on input 1. + * 0b0011..Falling edges on input 1. + * 0b0100..Rising edges on input 2. + * 0b0101..Falling edges on input 2. + * 0b0110..Rising edges on input 3. + * 0b0111..Falling edges on input 3. + */ +#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) +#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) +#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) +#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) +#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) +#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) +#define SCT_CONFIG_INSYNC_MASK (0x1E00U) +#define SCT_CONFIG_INSYNC_SHIFT (9U) +#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) +#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) +#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) +#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) +#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) +/*! @} */ + +/*! @name CTRL - SCT control register */ +/*! @{ */ +#define SCT_CTRL_DOWN_L_MASK (0x1U) +#define SCT_CTRL_DOWN_L_SHIFT (0U) +#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) +#define SCT_CTRL_STOP_L_MASK (0x2U) +#define SCT_CTRL_STOP_L_SHIFT (1U) +#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) +#define SCT_CTRL_HALT_L_MASK (0x4U) +#define SCT_CTRL_HALT_L_SHIFT (2U) +#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) +#define SCT_CTRL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRL_CLRCTR_L_SHIFT (3U) +#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) +#define SCT_CTRL_BIDIR_L_MASK (0x10U) +#define SCT_CTRL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) +#define SCT_CTRL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRL_PRE_L_SHIFT (5U) +#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) +#define SCT_CTRL_DOWN_H_MASK (0x10000U) +#define SCT_CTRL_DOWN_H_SHIFT (16U) +#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) +#define SCT_CTRL_STOP_H_MASK (0x20000U) +#define SCT_CTRL_STOP_H_SHIFT (17U) +#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) +#define SCT_CTRL_HALT_H_MASK (0x40000U) +#define SCT_CTRL_HALT_H_SHIFT (18U) +#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) +#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) +#define SCT_CTRL_CLRCTR_H_SHIFT (19U) +#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) +#define SCT_CTRL_BIDIR_H_MASK (0x100000U) +#define SCT_CTRL_BIDIR_H_SHIFT (20U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) +#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) +#define SCT_CTRL_PRE_H_SHIFT (21U) +#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) +/*! @} */ + +/*! @name LIMIT - SCT limit event select register */ +/*! @{ */ +#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) +#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) +#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) +#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) +/*! @} */ + +/*! @name HALT - SCT halt event select register */ +/*! @{ */ +#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) +#define SCT_HALT_HALTMSK_L_SHIFT (0U) +#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) +#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) +#define SCT_HALT_HALTMSK_H_SHIFT (16U) +#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) +/*! @} */ + +/*! @name STOP - SCT stop event select register */ +/*! @{ */ +#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) +#define SCT_STOP_STOPMSK_L_SHIFT (0U) +#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) +#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) +#define SCT_STOP_STOPMSK_H_SHIFT (16U) +#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) +/*! @} */ + +/*! @name START - SCT start event select register */ +/*! @{ */ +#define SCT_START_STARTMSK_L_MASK (0xFFFFU) +#define SCT_START_STARTMSK_L_SHIFT (0U) +#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) +#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) +#define SCT_START_STARTMSK_H_SHIFT (16U) +#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) +/*! @} */ + +/*! @name COUNT - SCT counter register */ +/*! @{ */ +#define SCT_COUNT_CTR_L_MASK (0xFFFFU) +#define SCT_COUNT_CTR_L_SHIFT (0U) +#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) +#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) +#define SCT_COUNT_CTR_H_SHIFT (16U) +#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) +/*! @} */ + +/*! @name STATE - SCT state register */ +/*! @{ */ +#define SCT_STATE_STATE_L_MASK (0x1FU) +#define SCT_STATE_STATE_L_SHIFT (0U) +#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) +#define SCT_STATE_STATE_H_MASK (0x1F0000U) +#define SCT_STATE_STATE_H_SHIFT (16U) +#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) +/*! @} */ + +/*! @name INPUT - SCT input register */ +/*! @{ */ +#define SCT_INPUT_AIN0_MASK (0x1U) +#define SCT_INPUT_AIN0_SHIFT (0U) +#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) +#define SCT_INPUT_AIN1_MASK (0x2U) +#define SCT_INPUT_AIN1_SHIFT (1U) +#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) +#define SCT_INPUT_AIN2_MASK (0x4U) +#define SCT_INPUT_AIN2_SHIFT (2U) +#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) +#define SCT_INPUT_AIN3_MASK (0x8U) +#define SCT_INPUT_AIN3_SHIFT (3U) +#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) +#define SCT_INPUT_AIN4_MASK (0x10U) +#define SCT_INPUT_AIN4_SHIFT (4U) +#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) +#define SCT_INPUT_AIN5_MASK (0x20U) +#define SCT_INPUT_AIN5_SHIFT (5U) +#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) +#define SCT_INPUT_AIN6_MASK (0x40U) +#define SCT_INPUT_AIN6_SHIFT (6U) +#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) +#define SCT_INPUT_AIN7_MASK (0x80U) +#define SCT_INPUT_AIN7_SHIFT (7U) +#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) +#define SCT_INPUT_AIN8_MASK (0x100U) +#define SCT_INPUT_AIN8_SHIFT (8U) +#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) +#define SCT_INPUT_AIN9_MASK (0x200U) +#define SCT_INPUT_AIN9_SHIFT (9U) +#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) +#define SCT_INPUT_AIN10_MASK (0x400U) +#define SCT_INPUT_AIN10_SHIFT (10U) +#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) +#define SCT_INPUT_AIN11_MASK (0x800U) +#define SCT_INPUT_AIN11_SHIFT (11U) +#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) +#define SCT_INPUT_AIN12_MASK (0x1000U) +#define SCT_INPUT_AIN12_SHIFT (12U) +#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) +#define SCT_INPUT_AIN13_MASK (0x2000U) +#define SCT_INPUT_AIN13_SHIFT (13U) +#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) +#define SCT_INPUT_AIN14_MASK (0x4000U) +#define SCT_INPUT_AIN14_SHIFT (14U) +#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) +#define SCT_INPUT_AIN15_MASK (0x8000U) +#define SCT_INPUT_AIN15_SHIFT (15U) +#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) +#define SCT_INPUT_SIN0_MASK (0x10000U) +#define SCT_INPUT_SIN0_SHIFT (16U) +#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) +#define SCT_INPUT_SIN1_MASK (0x20000U) +#define SCT_INPUT_SIN1_SHIFT (17U) +#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) +#define SCT_INPUT_SIN2_MASK (0x40000U) +#define SCT_INPUT_SIN2_SHIFT (18U) +#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) +#define SCT_INPUT_SIN3_MASK (0x80000U) +#define SCT_INPUT_SIN3_SHIFT (19U) +#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) +#define SCT_INPUT_SIN4_MASK (0x100000U) +#define SCT_INPUT_SIN4_SHIFT (20U) +#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) +#define SCT_INPUT_SIN5_MASK (0x200000U) +#define SCT_INPUT_SIN5_SHIFT (21U) +#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) +#define SCT_INPUT_SIN6_MASK (0x400000U) +#define SCT_INPUT_SIN6_SHIFT (22U) +#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) +#define SCT_INPUT_SIN7_MASK (0x800000U) +#define SCT_INPUT_SIN7_SHIFT (23U) +#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) +#define SCT_INPUT_SIN8_MASK (0x1000000U) +#define SCT_INPUT_SIN8_SHIFT (24U) +#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) +#define SCT_INPUT_SIN9_MASK (0x2000000U) +#define SCT_INPUT_SIN9_SHIFT (25U) +#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) +#define SCT_INPUT_SIN10_MASK (0x4000000U) +#define SCT_INPUT_SIN10_SHIFT (26U) +#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) +#define SCT_INPUT_SIN11_MASK (0x8000000U) +#define SCT_INPUT_SIN11_SHIFT (27U) +#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) +#define SCT_INPUT_SIN12_MASK (0x10000000U) +#define SCT_INPUT_SIN12_SHIFT (28U) +#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) +#define SCT_INPUT_SIN13_MASK (0x20000000U) +#define SCT_INPUT_SIN13_SHIFT (29U) +#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) +#define SCT_INPUT_SIN14_MASK (0x40000000U) +#define SCT_INPUT_SIN14_SHIFT (30U) +#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) +#define SCT_INPUT_SIN15_MASK (0x80000000U) +#define SCT_INPUT_SIN15_SHIFT (31U) +#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) +/*! @} */ + +/*! @name REGMODE - SCT match/capture mode register */ +/*! @{ */ +#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) +#define SCT_REGMODE_REGMOD_L_SHIFT (0U) +#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) +#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) +#define SCT_REGMODE_REGMOD_H_SHIFT (16U) +#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) +/*! @} */ + +/*! @name OUTPUT - SCT output register */ +/*! @{ */ +#define SCT_OUTPUT_OUT_MASK (0xFFFFU) +#define SCT_OUTPUT_OUT_SHIFT (0U) +#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) +/*! @} */ + +/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ +/*! @{ */ +#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) +#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) +/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) +#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) +/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) +#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) +/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) +#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) +/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) +#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) +/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) +#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) +/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) +#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) +/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) +#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) +/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) +#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) +/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) +#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) +/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) +#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) +/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) +#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) +/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) +/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) +/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) +/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) +#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) +#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) +/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. + * 0b00..Set and clear do not depend on the direction of any counter. + * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. + * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. + */ +#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) +/*! @} */ + +/*! @name RES - SCT conflict resolution register */ +/*! @{ */ +#define SCT_RES_O0RES_MASK (0x3U) +#define SCT_RES_O0RES_SHIFT (0U) +/*! O0RES - Effect of simultaneous set and clear on output 0. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR0 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) +#define SCT_RES_O1RES_MASK (0xCU) +#define SCT_RES_O1RES_SHIFT (2U) +/*! O1RES - Effect of simultaneous set and clear on output 1. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR1 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) +#define SCT_RES_O2RES_MASK (0x30U) +#define SCT_RES_O2RES_SHIFT (4U) +/*! O2RES - Effect of simultaneous set and clear on output 2. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR2 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) +#define SCT_RES_O3RES_MASK (0xC0U) +#define SCT_RES_O3RES_SHIFT (6U) +/*! O3RES - Effect of simultaneous set and clear on output 3. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR3 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) +#define SCT_RES_O4RES_MASK (0x300U) +#define SCT_RES_O4RES_SHIFT (8U) +/*! O4RES - Effect of simultaneous set and clear on output 4. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR4 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) +#define SCT_RES_O5RES_MASK (0xC00U) +#define SCT_RES_O5RES_SHIFT (10U) +/*! O5RES - Effect of simultaneous set and clear on output 5. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR5 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) +#define SCT_RES_O6RES_MASK (0x3000U) +#define SCT_RES_O6RES_SHIFT (12U) +/*! O6RES - Effect of simultaneous set and clear on output 6. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR6 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) +#define SCT_RES_O7RES_MASK (0xC000U) +#define SCT_RES_O7RES_SHIFT (14U) +/*! O7RES - Effect of simultaneous set and clear on output 7. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output n (or set based on the SETCLR7 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) +#define SCT_RES_O8RES_MASK (0x30000U) +#define SCT_RES_O8RES_SHIFT (16U) +/*! O8RES - Effect of simultaneous set and clear on output 8. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR8 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) +#define SCT_RES_O9RES_MASK (0xC0000U) +#define SCT_RES_O9RES_SHIFT (18U) +/*! O9RES - Effect of simultaneous set and clear on output 9. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR9 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) +#define SCT_RES_O10RES_MASK (0x300000U) +#define SCT_RES_O10RES_SHIFT (20U) +/*! O10RES - Effect of simultaneous set and clear on output 10. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR10 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) +#define SCT_RES_O11RES_MASK (0xC00000U) +#define SCT_RES_O11RES_SHIFT (22U) +/*! O11RES - Effect of simultaneous set and clear on output 11. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR11 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) +#define SCT_RES_O12RES_MASK (0x3000000U) +#define SCT_RES_O12RES_SHIFT (24U) +/*! O12RES - Effect of simultaneous set and clear on output 12. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR12 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) +#define SCT_RES_O13RES_MASK (0xC000000U) +#define SCT_RES_O13RES_SHIFT (26U) +/*! O13RES - Effect of simultaneous set and clear on output 13. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR13 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) +#define SCT_RES_O14RES_MASK (0x30000000U) +#define SCT_RES_O14RES_SHIFT (28U) +/*! O14RES - Effect of simultaneous set and clear on output 14. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR14 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) +#define SCT_RES_O15RES_MASK (0xC0000000U) +#define SCT_RES_O15RES_SHIFT (30U) +/*! O15RES - Effect of simultaneous set and clear on output 15. + * 0b00..No change. + * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). + * 0b10..Clear output (or set based on the SETCLR15 field). + * 0b11..Toggle output. + */ +#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) +/*! @} */ + +/*! @name DMA0REQUEST - SCT DMA request 0 register */ +/*! @{ */ +#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) +#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) +#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) +#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) +#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) +#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) +#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) +#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) +#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) +/*! @} */ + +/*! @name DMA1REQUEST - SCT DMA request 1 register */ +/*! @{ */ +#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) +#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) +#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) +#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) +#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) +#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) +#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) +#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) +#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) +/*! @} */ + +/*! @name EVEN - SCT event interrupt enable register */ +/*! @{ */ +#define SCT_EVEN_IEN_MASK (0xFFFFU) +#define SCT_EVEN_IEN_SHIFT (0U) +#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) +/*! @} */ + +/*! @name EVFLAG - SCT event flag register */ +/*! @{ */ +#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) +#define SCT_EVFLAG_FLAG_SHIFT (0U) +#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) +/*! @} */ + +/*! @name CONEN - SCT conflict interrupt enable register */ +/*! @{ */ +#define SCT_CONEN_NCEN_MASK (0xFFFFU) +#define SCT_CONEN_NCEN_SHIFT (0U) +#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) +/*! @} */ + +/*! @name CONFLAG - SCT conflict flag register */ +/*! @{ */ +#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) +#define SCT_CONFLAG_NCFLAG_SHIFT (0U) +#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) +#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) +#define SCT_CONFLAG_BUSERRL_SHIFT (30U) +#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) +#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) +#define SCT_CONFLAG_BUSERRH_SHIFT (31U) +#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) +/*! @} */ + +/*! @name SCTCAP - SCT capture register of capture channel */ +/*! @{ */ +#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) +#define SCT_SCTCAP_CAPn_L_SHIFT (0U) +#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) +#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAP_CAPn_H_SHIFT (16U) +#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTCAP */ +#define SCT_SCTCAP_COUNT (10U) + +/*! @name SCTMATCH - SCT match value register of match channels */ +/*! @{ */ +#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) +#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) +#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) +#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTMATCH */ +#define SCT_SCTMATCH_COUNT (10U) + +/*! @name SCTCAPCTRL - SCT capture control register */ +/*! @{ */ +#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) +#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) +#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) +#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTCAPCTRL */ +#define SCT_SCTCAPCTRL_COUNT (10U) + +/*! @name SCTMATCHREL - SCT match reload value register */ +/*! @{ */ +#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) +#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) +#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) +#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_SCTMATCHREL */ +#define SCT_SCTMATCHREL_COUNT (10U) + +/*! @name EVENT_STATE - SCT event state register 0 */ +/*! @{ */ +#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) +#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EVENT_STATE */ +#define SCT_EVENT_STATE_COUNT (10U) + +/*! @name EVENT_CTRL - SCT event control register 0 */ +/*! @{ */ +#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) +#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) +#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) +#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) +/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. + * 0b0..Selects the L state and the L match register selected by MATCHSEL. + * 0b1..Selects the H state and the H match register selected by MATCHSEL. + */ +#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) +#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) +/*! OUTSEL - Input/output select + * 0b0..Selects the inputs selected by IOSEL. + * 0b1..Selects the outputs selected by IOSEL. + */ +#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) +#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) +#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) +#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) +/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . + * 0b00..LOW + * 0b01..Rise + * 0b10..Fall + * 0b11..HIGH + */ +#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) +#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) +/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. + * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. + * 0b01..MATCH. Uses the specified match only. + * 0b10..IO. Uses the specified I/O condition only. + * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. + */ +#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) +#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) +#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) +/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. + * 0b0..STATEV value is added into STATE (the carry-out is ignored). + * 0b1..STATEV value is loaded into STATE. + */ +#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) +#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) +#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) +#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) +#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) +#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) +/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. + * 0b00..Direction independent. This event is triggered regardless of the count direction. + * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. + * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. + */ +#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) +/*! @} */ + +/* The count of SCT_EVENT_CTRL */ +#define SCT_EVENT_CTRL_COUNT (10U) + +/*! @name OUT_SET - SCT output 0 set register */ +/*! @{ */ +#define SCT_OUT_SET_SET_MASK (0xFFFFU) +#define SCT_OUT_SET_SET_SHIFT (0U) +#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) +/*! @} */ + +/* The count of SCT_OUT_SET */ +#define SCT_OUT_SET_COUNT (8U) + +/*! @name OUT_CLR - SCT output 0 clear register */ +/*! @{ */ +#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) +#define SCT_OUT_CLR_CLR_SHIFT (0U) +#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) +/*! @} */ + +/* The count of SCT_OUT_CLR */ +#define SCT_OUT_CLR_COUNT (8U) + + +/*! + * @} + */ /* end of group SCT_Register_Masks */ + + +/* SCT - Peripheral instance base addresses */ +/** Peripheral SCT0 base address */ +#define SCT0_BASE (0x40085000u) +/** Peripheral SCT0 base pointer */ +#define SCT0 ((SCT_Type *)SCT0_BASE) +/** Array initializer of SCT peripheral base addresses */ +#define SCT_BASE_ADDRS { SCT0_BASE } +/** Array initializer of SCT peripheral base pointers */ +#define SCT_BASE_PTRS { SCT0 } +/** Interrupt vectors for the SCT peripheral type */ +#define SCT_IRQS { SCT0_IRQn } + +/*! + * @} + */ /* end of group SCT_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer + * @{ + */ + +/** SPI - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[1024]; + __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ + __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ + __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ + __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ + __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ + uint8_t RESERVED_1[16]; + __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ + __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ + uint8_t RESERVED_2[2516]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_3[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_4[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_6[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_7[440]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} SPI_Type; + +/* ---------------------------------------------------------------------------- + -- SPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPI_Register_Masks SPI Register Masks + * @{ + */ + +/*! @name CFG - SPI Configuration register */ +/*! @{ */ +#define SPI_CFG_ENABLE_MASK (0x1U) +#define SPI_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - SPI enable. + * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. + * 0b1..Enabled. The SPI is enabled for operation. + */ +#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) +#define SPI_CFG_MASTER_MASK (0x4U) +#define SPI_CFG_MASTER_SHIFT (2U) +/*! MASTER - Master mode select. + * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. + * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. + */ +#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) +#define SPI_CFG_LSBF_MASK (0x8U) +#define SPI_CFG_LSBF_SHIFT (3U) +/*! LSBF - LSB First mode enable. + * 0b0..Standard. Data is transmitted and received in standard MSB first order. + * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). + */ +#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) +#define SPI_CFG_CPHA_MASK (0x10U) +#define SPI_CFG_CPHA_SHIFT (4U) +/*! CPHA - Clock Phase select. + * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. + * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. + */ +#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) +#define SPI_CFG_CPOL_MASK (0x20U) +#define SPI_CFG_CPOL_SHIFT (5U) +/*! CPOL - Clock Polarity select. + * 0b0..Low. The rest state of the clock (between transfers) is low. + * 0b1..High. The rest state of the clock (between transfers) is high. + */ +#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) +#define SPI_CFG_LOOP_MASK (0x80U) +#define SPI_CFG_LOOP_SHIFT (7U) +/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. + * 0b0..Disabled. + * 0b1..Enabled. + */ +#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) +#define SPI_CFG_SPOL0_MASK (0x100U) +#define SPI_CFG_SPOL0_SHIFT (8U) +/*! SPOL0 - SSEL0 Polarity select. + * 0b0..Low. The SSEL0 pin is active low. + * 0b1..High. The SSEL0 pin is active high. + */ +#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) +#define SPI_CFG_SPOL1_MASK (0x200U) +#define SPI_CFG_SPOL1_SHIFT (9U) +/*! SPOL1 - SSEL1 Polarity select. + * 0b0..Low. The SSEL1 pin is active low. + * 0b1..High. The SSEL1 pin is active high. + */ +#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) +#define SPI_CFG_SPOL2_MASK (0x400U) +#define SPI_CFG_SPOL2_SHIFT (10U) +/*! SPOL2 - SSEL2 Polarity select. + * 0b0..Low. The SSEL2 pin is active low. + * 0b1..High. The SSEL2 pin is active high. + */ +#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) +#define SPI_CFG_SPOL3_MASK (0x800U) +#define SPI_CFG_SPOL3_SHIFT (11U) +/*! SPOL3 - SSEL3 Polarity select. + * 0b0..Low. The SSEL3 pin is active low. + * 0b1..High. The SSEL3 pin is active high. + */ +#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) +/*! @} */ + +/*! @name DLY - SPI Delay register */ +/*! @{ */ +#define SPI_DLY_PRE_DELAY_MASK (0xFU) +#define SPI_DLY_PRE_DELAY_SHIFT (0U) +#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) +#define SPI_DLY_POST_DELAY_MASK (0xF0U) +#define SPI_DLY_POST_DELAY_SHIFT (4U) +#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) +#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) +#define SPI_DLY_FRAME_DELAY_SHIFT (8U) +#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) +#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) +#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) +/*! @} */ + +/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ +/*! @{ */ +#define SPI_STAT_SSA_MASK (0x10U) +#define SPI_STAT_SSA_SHIFT (4U) +#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) +#define SPI_STAT_SSD_MASK (0x20U) +#define SPI_STAT_SSD_SHIFT (5U) +#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) +#define SPI_STAT_STALLED_MASK (0x40U) +#define SPI_STAT_STALLED_SHIFT (6U) +#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) +#define SPI_STAT_ENDTRANSFER_MASK (0x80U) +#define SPI_STAT_ENDTRANSFER_SHIFT (7U) +#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) +#define SPI_STAT_MSTIDLE_MASK (0x100U) +#define SPI_STAT_MSTIDLE_SHIFT (8U) +#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define SPI_INTENSET_SSAEN_MASK (0x10U) +#define SPI_INTENSET_SSAEN_SHIFT (4U) +/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. + * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. + * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. + */ +#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) +#define SPI_INTENSET_SSDEN_MASK (0x20U) +#define SPI_INTENSET_SSDEN_SHIFT (5U) +/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. + * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. + * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. + */ +#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) +#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) +#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) +/*! MSTIDLEEN - Master idle interrupt enable. + * 0b0..No interrupt will be generated when the SPI master function is idle. + * 0b1..An interrupt will be generated when the SPI master function is fully idle. + */ +#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) +/*! @} */ + +/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ +/*! @{ */ +#define SPI_INTENCLR_SSAEN_MASK (0x10U) +#define SPI_INTENCLR_SSAEN_SHIFT (4U) +#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) +#define SPI_INTENCLR_SSDEN_MASK (0x20U) +#define SPI_INTENCLR_SSDEN_SHIFT (5U) +#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) +#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) +#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) +/*! @} */ + +/*! @name DIV - SPI clock Divider */ +/*! @{ */ +#define SPI_DIV_DIVVAL_MASK (0xFFFFU) +#define SPI_DIV_DIVVAL_SHIFT (0U) +#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - SPI Interrupt Status */ +/*! @{ */ +#define SPI_INTSTAT_SSA_MASK (0x10U) +#define SPI_INTSTAT_SSA_SHIFT (4U) +#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) +#define SPI_INTSTAT_SSD_MASK (0x20U) +#define SPI_INTSTAT_SSD_SHIFT (5U) +#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) +#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) +#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) +#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) +#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) +#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) +#define SPI_FIFOCFG_SIZE_MASK (0x30U) +#define SPI_FIFOCFG_SIZE_SHIFT (4U) +#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) +#define SPI_FIFOCFG_DMATX_MASK (0x1000U) +#define SPI_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) +#define SPI_FIFOCFG_DMARX_MASK (0x2000U) +#define SPI_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) +#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) +#define SPI_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) +#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) +#define SPI_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) +#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) +#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define SPI_FIFOSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) +#define SPI_FIFOSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) +#define SPI_FIFOSTAT_PERINT_MASK (0x8U) +#define SPI_FIFOSTAT_PERINT_SHIFT (3U) +#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) +#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) +#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) +#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) +#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) +#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) +#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) +#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) +#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) +#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) +#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) +#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) +#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) +#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) +#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) +#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) +#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) +#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) +#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) +#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) +#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) +#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) +#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) +#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) +#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) +#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) +#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) +#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) +#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) +#define SPI_FIFOWR_TXDATA_SHIFT (0U) +#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) +#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) +#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) +/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL0 asserted. + * 0b1..SSEL0 not asserted. + */ +#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) +#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) +#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) +/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL1 asserted. + * 0b1..SSEL1 not asserted. + */ +#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) +#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) +#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) +/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL2 asserted. + * 0b1..SSEL2 not asserted. + */ +#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) +#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) +#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) +/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. + * 0b0..SSEL3 asserted. + * 0b1..SSEL3 not asserted. + */ +#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) +#define SPI_FIFOWR_EOT_MASK (0x100000U) +#define SPI_FIFOWR_EOT_SHIFT (20U) +/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. + * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. + * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. + */ +#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) +#define SPI_FIFOWR_EOF_MASK (0x200000U) +#define SPI_FIFOWR_EOF_SHIFT (21U) +/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. + * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. + * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. + */ +#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) +#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) +#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) +/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. + * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. + * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. + */ +#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) +#define SPI_FIFOWR_LEN_MASK (0xF000000U) +#define SPI_FIFOWR_LEN_SHIFT (24U) +#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORD_RXDATA_SHIFT (0U) +#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) +#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) +#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) +#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) +#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) +#define SPI_FIFORD_SOT_MASK (0x100000U) +#define SPI_FIFORD_SOT_SHIFT (20U) +#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) +#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) +#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) +#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) +#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) +#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) +#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) +#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) +#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) +#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define SPI_ID_APERTURE_MASK (0xFFU) +#define SPI_ID_APERTURE_SHIFT (0U) +#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) +#define SPI_ID_MINOR_REV_MASK (0xF00U) +#define SPI_ID_MINOR_REV_SHIFT (8U) +#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) +#define SPI_ID_MAJOR_REV_MASK (0xF000U) +#define SPI_ID_MAJOR_REV_SHIFT (12U) +#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) +#define SPI_ID_ID_MASK (0xFFFF0000U) +#define SPI_ID_ID_SHIFT (16U) +#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SPI_Register_Masks */ + + +/* SPI - Peripheral instance base addresses */ +/** Peripheral SPI0 base address */ +#define SPI0_BASE (0x40086000u) +/** Peripheral SPI0 base pointer */ +#define SPI0 ((SPI_Type *)SPI0_BASE) +/** Peripheral SPI1 base address */ +#define SPI1_BASE (0x40087000u) +/** Peripheral SPI1 base pointer */ +#define SPI1 ((SPI_Type *)SPI1_BASE) +/** Peripheral SPI2 base address */ +#define SPI2_BASE (0x40088000u) +/** Peripheral SPI2 base pointer */ +#define SPI2 ((SPI_Type *)SPI2_BASE) +/** Peripheral SPI3 base address */ +#define SPI3_BASE (0x40089000u) +/** Peripheral SPI3 base pointer */ +#define SPI3 ((SPI_Type *)SPI3_BASE) +/** Peripheral SPI4 base address */ +#define SPI4_BASE (0x4008A000u) +/** Peripheral SPI4 base pointer */ +#define SPI4 ((SPI_Type *)SPI4_BASE) +/** Peripheral SPI5 base address */ +#define SPI5_BASE (0x40096000u) +/** Peripheral SPI5 base pointer */ +#define SPI5 ((SPI_Type *)SPI5_BASE) +/** Peripheral SPI6 base address */ +#define SPI6_BASE (0x40097000u) +/** Peripheral SPI6 base pointer */ +#define SPI6 ((SPI_Type *)SPI6_BASE) +/** Peripheral SPI7 base address */ +#define SPI7_BASE (0x40098000u) +/** Peripheral SPI7 base pointer */ +#define SPI7 ((SPI_Type *)SPI7_BASE) +/** Array initializer of SPI peripheral base addresses */ +#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE } +/** Array initializer of SPI peripheral base pointers */ +#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7 } +/** Interrupt vectors for the SPI peripheral type */ +#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group SPI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- SYSCON Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer + * @{ + */ + +/** SYSCON - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[16]; + __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ + uint8_t RESERVED_1[44]; + __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */ + uint8_t RESERVED_2[4]; + __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ + __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */ + uint8_t RESERVED_3[112]; + __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */ + uint8_t RESERVED_5[40]; + __IO uint32_t PRESETCTRL[2]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */ + uint8_t RESERVED_6[24]; + __O uint32_t PRESETCTRLSET[2]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */ + uint8_t RESERVED_7[24]; + __O uint32_t PRESETCTRLCLR[2]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */ + uint8_t RESERVED_8[168]; + __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */ + uint8_t RESERVED_9[12]; + __IO uint32_t AHBCLKCTRL[2]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_10[24]; + __O uint32_t AHBCLKCTRLSET[2]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */ + uint8_t RESERVED_11[24]; + __O uint32_t AHBCLKCTRLCLR[2]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */ + uint8_t RESERVED_12[56]; + __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ + __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ + __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */ + uint8_t RESERVED_13[4]; + __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */ + uint8_t RESERVED_14[16]; + __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ + __IO uint32_t USBCLKSEL; /**< USB clock source select, offset: 0x2A8 */ + uint8_t RESERVED_15[4]; + __IO uint32_t FXCOMCLKSEL[8]; /**< Flexcomm0 clock source select..Flexcomm7 clock source select, array offset: 0x2B0, array step: 0x4 */ + uint8_t RESERVED_16[16]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_17[4]; + __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */ + uint8_t RESERVED_18[20]; + __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */ + uint8_t RESERVED_19[124]; + __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */ + __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ + uint8_t RESERVED_20[12]; + __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ + __IO uint32_t USBCLKDIV; /**< USB clock divider, offset: 0x398 */ + uint8_t RESERVED_21[4]; + __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */ + uint8_t RESERVED_22[8]; + __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ + uint8_t RESERVED_23[80]; + __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */ + uint8_t RESERVED_24[8]; + __IO uint32_t USBCLKCTRL; /**< USB clock control, offset: 0x40C */ + __IO uint32_t USBCLKSTAT; /**< USB clock status, offset: 0x410 */ + uint8_t RESERVED_25[4]; + __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */ + uint8_t RESERVED_26[4]; + __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */ + uint8_t RESERVED_27[220]; + __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */ + uint8_t RESERVED_28[4]; + __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */ + __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */ + uint8_t RESERVED_29[112]; + __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x580 */ + __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */ + __IO uint32_t SYSPLLNDEC; /**< PLL N decoder, offset: 0x588 */ + __IO uint32_t SYSPLLPDEC; /**< PLL P decoder, offset: 0x58C */ + __IO uint32_t SYSPLLSSCTRL0; /**< PLL spread spectrum control 0, offset: 0x590 */ + __IO uint32_t SYSPLLSSCTRL1; /**< PLL spread spectrum control 1, offset: 0x594 */ + uint8_t RESERVED_30[104]; + __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register n, array offset: 0x600, array step: 0x4 */ + uint8_t RESERVED_31[8]; + __IO uint32_t PDRUNCFG[1]; /**< Power configuration register 0, array offset: 0x610, array step: 0x4 */ + uint8_t RESERVED_32[12]; + __O uint32_t PDRUNCFGSET[1]; /**< Set bits in PDRUNCFGn, array offset: 0x620, array step: 0x4 */ + uint8_t RESERVED_33[12]; + __O uint32_t PDRUNCFGCLR[1]; /**< Clear bits in PDRUNCFGn, array offset: 0x630, array step: 0x4 */ + uint8_t RESERVED_34[76]; + __IO uint32_t STARTER[1]; /**< Start logic n wake-up enable register, array offset: 0x680, array step: 0x4 */ + uint8_t RESERVED_35[28]; + __O uint32_t STARTERSET[1]; /**< Set bits in STARTERn, array offset: 0x6A0, array step: 0x4 */ + uint8_t RESERVED_36[28]; + __O uint32_t STARTERCLR[1]; /**< Clear bits in STARTERn, array offset: 0x6C0, array step: 0x4 */ + uint8_t RESERVED_37[188]; + __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ + uint8_t RESERVED_38[2160]; + __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */ + __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */ + __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */ + uint8_t RESERVED_39[127044]; + __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */ +} SYSCON_Type; + +/* ---------------------------------------------------------------------------- + -- SYSCON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SYSCON_Register_Masks SYSCON Register Masks + * @{ + */ + +/*! @name AHBMATPRIO - AHB multilayer matrix priority control */ +/*! @{ */ +#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) +#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) +#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U) +#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK) +#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U) +#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK) +#define SYSCON_AHBMATPRIO_PRI_M0_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_M0_SHIFT (6U) +#define SYSCON_AHBMATPRIO_PRI_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_M0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_M0_MASK) +#define SYSCON_AHBMATPRIO_PRI_USB_MASK (0x300U) +#define SYSCON_AHBMATPRIO_PRI_USB_SHIFT (8U) +#define SYSCON_AHBMATPRIO_PRI_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_MASK) +#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC00U) +#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (10U) +#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) +/*! @} */ + +/*! @name SYSTCKCAL - System tick counter calibration */ +/*! @{ */ +#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) +#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) +#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) +#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U) +#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK) +#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) +#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) +/*! @} */ + +/*! @name NMISRC - NMI Source Select */ +/*! @{ */ +#define SYSCON_NMISRC_IRQM4_MASK (0x3FU) +#define SYSCON_NMISRC_IRQM4_SHIFT (0U) +#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) +#define SYSCON_NMISRC_IRQM0_MASK (0x3F00U) +#define SYSCON_NMISRC_IRQM0_SHIFT (8U) +#define SYSCON_NMISRC_IRQM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM0_SHIFT)) & SYSCON_NMISRC_IRQM0_MASK) +#define SYSCON_NMISRC_NMIENM0_MASK (0x40000000U) +#define SYSCON_NMISRC_NMIENM0_SHIFT (30U) +#define SYSCON_NMISRC_NMIENM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM0_SHIFT)) & SYSCON_NMISRC_NMIENM0_MASK) +#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) +#define SYSCON_NMISRC_NMIENM4_SHIFT (31U) +#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) +/*! @} */ + +/*! @name ASYNCAPBCTRL - Asynchronous APB Control */ +/*! @{ */ +#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) +#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) +/*! ENABLE - Enables the asynchronous APB bridge and subsystem. + * 0b0..Disabled. Asynchronous APB bridge is disabled. + * 0b1..Enabled. Asynchronous APB bridge is enabled. + */ +#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) +/*! @} */ + +/*! @name PIOPORCAP - POR captured value of port n */ +/*! @{ */ +#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) +#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) +#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) +/*! @} */ + +/* The count of SYSCON_PIOPORCAP */ +#define SYSCON_PIOPORCAP_COUNT (2U) + +/*! @name PIORESCAP - Reset captured value of port n */ +/*! @{ */ +#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) +#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) +#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) +/*! @} */ + +/* The count of SYSCON_PIORESCAP */ +#define SYSCON_PIORESCAP_COUNT (2U) + +/*! @name PRESETCTRL - Peripheral reset control n */ +/*! @{ */ +#define SYSCON_PRESETCTRL_MRT0_RST_MASK (0x1U) +#define SYSCON_PRESETCTRL_MRT0_RST_SHIFT (0U) +#define SYSCON_PRESETCTRL_MRT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK) +#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U) +#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK) +#define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U) +#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U) +#define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK) +#define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U) +#define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U) +#define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK) +#define SYSCON_PRESETCTRL_UTICK0_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT (10U) +#define SYSCON_PRESETCTRL_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK) +#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) +#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) +#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) +#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) +#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) +#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) +#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) +#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U) +#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK) +#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U) +#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U) +#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK) +#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U) +#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U) +#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U) +#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK) +#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U) +#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK) +#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U) +#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK) +#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U) +#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U) +#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK) +#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U) +#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U) +#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK) +#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U) +#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK) +#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) +#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) +#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) +#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) +#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) +#define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) +#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) +#define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) +#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U) +#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U) +#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK) +#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U) +#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U) +#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK) +#define SYSCON_PRESETCTRL_USB0_RST_MASK (0x2000000U) +#define SYSCON_PRESETCTRL_USB0_RST_SHIFT (25U) +#define SYSCON_PRESETCTRL_USB0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) +#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) +#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) +#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) +#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) +#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) +#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) +#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRL */ +#define SYSCON_PRESETCTRL_COUNT (2U) + +/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ +/*! @{ */ +#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) +#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLSET */ +#define SYSCON_PRESETCTRLSET_COUNT (2U) + +/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ +/*! @{ */ +#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) +#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_PRESETCTRLCLR */ +#define SYSCON_PRESETCTRLCLR_COUNT (2U) + +/*! @name SYSRSTSTAT - System reset status register */ +/*! @{ */ +#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) +#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) +/*! POR - POR reset status + * 0b0..No POR detected + * 0b1..POR detected. Writing a one clears this reset. + */ +#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) +#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) +#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) +/*! EXTRST - Status of the external RESET pin. External reset status + * 0b0..No reset event detected. + * 0b1..Reset detected. Writing a one clears this reset. + */ +#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) +#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) +#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) +/*! WDT - Status of the Watchdog reset + * 0b0..No WDT reset detected + * 0b1..WDT reset detected. Writing a one clears this reset. + */ +#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) +#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) +#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) +/*! BOD - Status of the Brown-out detect reset + * 0b0..No BOD reset detected + * 0b1..BOD reset detected. Writing a one clears this reset. + */ +#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) +#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) +#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) +/*! SYSRST - Status of the software system reset + * 0b0..No System reset detected + * 0b1..System reset detected. Writing a one clears this reset. + */ +#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) +/*! @} */ + +/*! @name AHBCLKCTRL - AHB Clock control n */ +/*! @{ */ +#define SYSCON_AHBCLKCTRL_MRT0_MASK (0x1U) +#define SYSCON_AHBCLKCTRL_MRT0_SHIFT (0U) +#define SYSCON_AHBCLKCTRL_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK) +#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U) +#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U) +#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK) +#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U) +#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U) +#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK) +#define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U) +#define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U) +#define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK) +#define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U) +#define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U) +#define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK) +#define SYSCON_AHBCLKCTRL_UTICK0_MASK (0x400U) +#define SYSCON_AHBCLKCTRL_UTICK0_SHIFT (10U) +#define SYSCON_AHBCLKCTRL_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK0_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK) +#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U) +#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) +#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) +#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) +#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) +#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) +#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) +#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) +#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U) +#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U) +#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK) +#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) +#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) +#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) +#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) +#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) +#define SYSCON_AHBCLKCTRL_DMA0_MASK (0x100000U) +#define SYSCON_AHBCLKCTRL_DMA0_SHIFT (20U) +#define SYSCON_AHBCLKCTRL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK) +#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U) +#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U) +#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK) +#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U) +#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U) +#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK) +#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U) +#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U) +#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK) +#define SYSCON_AHBCLKCTRL_USB0_MASK (0x2000000U) +#define SYSCON_AHBCLKCTRL_USB0_SHIFT (25U) +#define SYSCON_AHBCLKCTRL_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0_SHIFT)) & SYSCON_AHBCLKCTRL_USB0_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U) +#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U) +#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK) +#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) +#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) +#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) +#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) +#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRL */ +#define SYSCON_AHBCLKCTRL_COUNT (2U) + +/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) +#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLSET */ +#define SYSCON_AHBCLKCTRLSET_COUNT (2U) + +/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ +/*! @{ */ +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) +#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_AHBCLKCTRLCLR */ +#define SYSCON_AHBCLKCTRLCLR_COUNT (2U) + +/*! @name MAINCLKSELA - Main clock source select A */ +/*! @{ */ +#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) +#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) +/*! SEL - Clock source for main clock source selector A + * 0b00..FRO 12 MHz (fro_12m) + * 0b01..CLKIN (clk_in) + * 0b10..Watchdog oscillator (wdt_clk) + * 0b11..FRO 96 or 48 MHz (fro_hf) + */ +#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) +/*! @} */ + +/*! @name MAINCLKSELB - Main clock source select B */ +/*! @{ */ +#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) +#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) +/*! SEL - Clock source for main clock source selector B. Selects the clock source for the main clock. + * 0b00..MAINCLKSELA. Use the clock source selected in MAINCLKSELA register. + * 0b01..Reserved setting + * 0b10..System PLL output (pll_clk) + * 0b11..RTC oscillator 32 kHz output (32k_clk) + */ +#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) +/*! @} */ + +/*! @name CLKOUTSELA - CLKOUT clock source select A */ +/*! @{ */ +#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) +#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) +/*! SEL - CLKOUT clock source selection + * 0b000..Main clock (main_clk) + * 0b001..CLKIN (clk_in) + * 0b010..Watchdog oscillator (wdt_clk) + * 0b011..FRO 96 or 48 MHz (fro_hf) + * 0b100..PLL output (pll_clk) + * 0b101..FRO 12 MHz (fro_12m) + * 0b110..RTC oscillator 32 kHz output (32k_clk) + * 0b111..None, this may be selected in order to reduce power when no output is needed. + */ +#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) +/*! @} */ + +/*! @name SYSPLLCLKSEL - PLL clock source select */ +/*! @{ */ +#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) +#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) +/*! SEL - System PLL clock source selection + * 0b000..FRO 12 MHz (fro_12m) + * 0b001..CLKIN (clk_in) + * 0b011..RTC 32 kHz clock (32k_clk) + * 0b111..None, this may be selected in order to reduce power when no output is needed. + */ +#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name ADCCLKSEL - ADC clock source select */ +/*! @{ */ +#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) +#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) +/*! SEL - ADC clock source selection + * 0b000..Main clock (main_clk) + * 0b001..System PLL output (pll_clk) + * 0b010..FRO 96 or 48 MHz (fro_hf) + * 0b111..None, this may be selected in order to reduce power when no output is needed. + */ +#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name USBCLKSEL - USB clock source select */ +/*! @{ */ +#define SYSCON_USBCLKSEL_SEL_MASK (0x7U) +#define SYSCON_USBCLKSEL_SEL_SHIFT (0U) +/*! SEL - USB device clock source selection + * 0b000..FRO 96 or 48 MHz (fro_hf) + * 0b001..System PLL output (pll_clk) + * 0b010..Main clock (main_clk) + * 0b111..None, this may be selected in order to reduce power when no output is needed. + */ +#define SYSCON_USBCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FXCOMCLKSEL - Flexcomm0 clock source select..Flexcomm7 clock source select */ +/*! @{ */ +#define SYSCON_FXCOMCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FXCOMCLKSEL_SEL_SHIFT (0U) +/*! SEL - Flexcomm clock source selection. One per Flexcomm. + * 0b000..FRO 12 MHz (fro_12m) + * 0b001..FRO 96 or 48 MHz (fro_hf) + * 0b010..System PLL output (pll_clk) + * 0b011..MCLK pin input, when selected in IOCON (mclk_in) + * 0b100..FRG clock, the output of the fractional rate generator (frg_clk) + * 0b111..None, this may be selected in order to reduce power when no output is needed. + */ +#define SYSCON_FXCOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK) +/*! @} */ + +/* The count of SYSCON_FXCOMCLKSEL */ +#define SYSCON_FXCOMCLKSEL_COUNT (8U) + +/*! @name MCLKCLKSEL - MCLK clock source select */ +/*! @{ */ +#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) +#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) +/*! SEL - MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem. + * 0b000..FRO 96 or 48 MHz (fro_hf) + * 0b001..System PLL output (pll_clk) + * 0b010..Main clock (main_clk) + * 0b111..None, this may be selected in order to reduce power when no output is needed. + */ +#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ +/*! @{ */ +#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) +#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) +/*! SEL - Fractional Rate Generator clock source select. + * 0b000..Main clock (main_clk) + * 0b001..System PLL output (pll_clk) + * 0b010..FRO 12 MHz (fro_12m) + * 0b011..FRO 96 or 48 MHz (fro_hf) + * 0b111..None, this may be selected in order to reduce power when no output is needed. + */ +#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) +/*! @} */ + +/*! @name SYSTICKCLKDIV - SYSTICK clock divider */ +/*! @{ */ +#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) +#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) +/*! @} */ + +/*! @name AHBCLKDIV - AHB clock divider */ +/*! @{ */ +#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) +/*! @} */ + +/*! @name CLKOUTDIV - CLKOUT clock divider */ +/*! @{ */ +#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) +#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) +/*! @} */ + +/*! @name ADCCLKDIV - ADC clock divider */ +/*! @{ */ +#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) +/*! @} */ + +/*! @name USBCLKDIV - USB clock divider */ +/*! @{ */ +#define SYSCON_USBCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_USBCLKDIV_DIV_SHIFT (0U) +#define SYSCON_USBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK) +/*! @} */ + +/*! @name FRGCTRL - Fractional rate divider */ +/*! @{ */ +#define SYSCON_FRGCTRL_DIV_MASK (0xFFU) +#define SYSCON_FRGCTRL_DIV_SHIFT (0U) +#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) +#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) +#define SYSCON_FRGCTRL_MULT_SHIFT (8U) +#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) +/*! @} */ + +/*! @name MCLKDIV - I2S MCLK clock divider */ +/*! @{ */ +#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) +#define SYSCON_MCLKDIV_DIV_SHIFT (0U) +#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) +/*! @} */ + +/*! @name FLASHCFG - Flash wait states configuration */ +/*! @{ */ +#define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) +#define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) +/*! FETCHCFG - Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches. + * 0b00..Instruction fetches from flash are not buffered. Every fetch request from the CPU results in a read of the flash memory. This setting may use significantly more power than when buffering is enabled. + * 0b01..One buffer is used for all instruction fetches. + * 0b10..All buffers may be used for instruction fetches. + * 0b11..Reserved setting, do not use. + */ +#define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) +#define SYSCON_FLASHCFG_DATACFG_MASK (0xCU) +#define SYSCON_FLASHCFG_DATACFG_SHIFT (2U) +/*! DATACFG - Data read configuration. This field determines how flash accelerator buffers are used for data accesses. + * 0b00..Data accesses from flash are not buffered. Every data access from the CPU results in a read of the flash memory. + * 0b01..One buffer is used for all data accesses. + * 0b10..All buffers may be used for data accesses. + * 0b11..Reserved setting, do not use. + */ +#define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK) +#define SYSCON_FLASHCFG_ACCEL_MASK (0x10U) +#define SYSCON_FLASHCFG_ACCEL_SHIFT (4U) +/*! ACCEL - Acceleration enable. + * 0b0..Flash acceleration is disabled. Every flash read (including those fulfilled from a buffer) takes FLASHTIM + 1 system clocks. This allows more determinism at a cost of performance. + * 0b1..Flash acceleration is enabled. Performance is enhanced, dependent on other FLASHCFG settings. + */ +#define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK) +#define SYSCON_FLASHCFG_PREFEN_MASK (0x20U) +#define SYSCON_FLASHCFG_PREFEN_SHIFT (5U) +/*! PREFEN - Prefetch enable. + * 0b0..No instruction prefetch is performed. + * 0b1..If the FETCHCFG field is not 0, the next flash line following the current execution address is automatically prefetched if it is not already buffered. + */ +#define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK) +#define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U) +#define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U) +/*! PREFOVR - Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched. + * 0b0..Any previously initiated prefetch will be completed. + * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered. + */ +#define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK) +#define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) +#define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) +/*! FLASHTIM - Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1. + * 0b0000..1 system clock flash access time (for system clock rates up to 12 MHz). + * 0b0001..2 system clocks flash access time (for system clock rates up to 30 MHz). + * 0b0010..3 system clocks flash access time (for system clock rates up to 60 MHz). + * 0b0011..4 system clocks flash access time (for system clock rates up to 85 MHz). + * 0b0100..5 system clocks flash access time (for system clock rates up to 100 MHz). + */ +#define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) +/*! @} */ + +/*! @name USBCLKCTRL - USB clock control */ +/*! @{ */ +#define SYSCON_USBCLKCTRL_POL_CLK_MASK (0x2U) +#define SYSCON_USBCLKCTRL_POL_CLK_SHIFT (1U) +/*! POL_CLK - USB_NEED_CLK polarity for triggering the USB wake-up interrupt + * 0b0..Falling edge of the USB_NEED_CLK triggers the USB wake-up (default). + * 0b1..Rising edge of the USB_NEED_CLK triggers the USB wake-up. + */ +#define SYSCON_USBCLKCTRL_POL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK) +/*! @} */ + +/*! @name USBCLKSTAT - USB clock status */ +/*! @{ */ +#define SYSCON_USBCLKSTAT_NEED_CLKST_MASK (0x1U) +#define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT (0U) +/*! NEED_CLKST - USB_NEED_CLK signal status + * 0b0..Low + * 0b1..High + */ +#define SYSCON_USBCLKSTAT_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK) +/*! @} */ + +/*! @name FREQMECTRL - Frequency measure register */ +/*! @{ */ +#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) +#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) +#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) +#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) +#define SYSCON_FREQMECTRL_PROG_SHIFT (31U) +#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) +/*! @} */ + +/*! @name MCLKIO - MCLK input/output control */ +/*! @{ */ +#define SYSCON_MCLKIO_DIR_MASK (0x1U) +#define SYSCON_MCLKIO_DIR_SHIFT (0U) +/*! DIR - MCLK direction control. + * 0b0..The MCLK function is an input. + * 0b1..The MCLK function is an output. + */ +#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) +/*! @} */ + +/*! @name FROCTRL - FRO oscillator control */ +/*! @{ */ +#define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) +#define SYSCON_FROCTRL_TRIM_SHIFT (0U) +#define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) +#define SYSCON_FROCTRL_SEL_MASK (0x4000U) +#define SYSCON_FROCTRL_SEL_SHIFT (14U) +/*! SEL - Select the fro_hf output frequency. This bit can only be changed by software when the WRTRIM bit = 1. Note that the factory trim values are for the 96 MHz FRO only. + * 0b0..48 MHz + * 0b1..96 MHz + */ +#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK) +#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U) +#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U) +#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK) +#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U) +#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U) +/*! USBCLKADJ - USB clock adjust mode. + * 0b0..Normal operation. + * 0b1..Automatic USB rate adjustment mode. If the USB FS device peripheral is enabled and connected to a USB host, it provides clock adjustment information to the FRO based on SOF packets. USB rate adjustment requires a number of cycles to take place. the USBMODCHG bit (see below) indicates when initial adjustment is complete, and when later adjustments are in progress. software must not alter TRIM and FREQTRIM while USBCLKADJ = 1. see USBCLKADJ usage notes below this table. + */ +#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK) +#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U) +#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U) +#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK) +#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U) +#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U) +/*! HSPDCLK - High speed clock enable. Allows disabling the highs-speed FRO output if it is not needed. + * 0b0..The high-speed FRO output is disabled. + * 0b1..The selected high-speed FRO output (48 MHz or 96 MHz) is enabled. + */ +#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK) +#define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) +#define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) +#define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) +/*! @} */ + +/*! @name WDTOSCCTRL - Watchdog oscillator control */ +/*! @{ */ +#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) +#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) +#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) +#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) +#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) +#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) +/*! @} */ + +/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ +/*! @{ */ +#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) +#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) +/*! EN - RTC 32 kHz clock enable. + * 0b0..Disabled. RTC clock off. + * 0b1..Enabled. RTC clock on. + */ +#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) +/*! @} */ + +/*! @name SYSPLLCTRL - PLL control */ +/*! @{ */ +#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) +#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) +#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) +#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U) +#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U) +#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK) +#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U) +#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U) +#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK) +#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U) +#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U) +/*! BYPASS - PLL bypass control. + * 0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers. + * 0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default). + */ +#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK) +#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK (0x10000U) +#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT (16U) +/*! BYPASSCCODIV2 - Bypass feedback clock divide by 2. + * 0b0..Divide by 2. The CCO feedback clock is divided by 2 in addition to the programmed M divide. + * 0b1..Bypass. The CCO feedback clock is divided only by the programmed M divide. + */ +#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) +#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U) +#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U) +/*! UPLIMOFF - Disable upper frequency limiter. + * 0b0..Normal mode. + * 0b1..Upper frequency limiter disabled. + */ +#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK) +#define SYSCON_SYSPLLCTRL_BANDSEL_MASK (0x40000U) +#define SYSCON_SYSPLLCTRL_BANDSEL_SHIFT (18U) +/*! BANDSEL - PLL filter control. Set this bit to one when the spread spectrum controller is disabled or at low frequencies. For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. + * 0b0..SSCG control. The PLL filter uses the parameters derived from the spread spectrum controller. + * 0b1..MDEC control. The PLL filter uses the programmable fields SELP, SELR, and SELI in this register to control the filter constants. + */ +#define SYSCON_SYSPLLCTRL_BANDSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT)) & SYSCON_SYSPLLCTRL_BANDSEL_MASK) +#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U) +#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U) +/*! DIRECTI - PLL0 direct input enable + * 0b0..Disabled. The PLL input divider (N divider) output is used to drive the PLL CCO. + * 0b1..Enabled. The PLL input divider (N divider) is bypassed. the PLL input clock is used directly to drive the PLL CCO input. + */ +#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK) +#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) +#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) +/*! DIRECTO - PLL0 direct output enable. + * 0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output. + * 0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output. + */ +#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) +/*! @} */ + +/*! @name SYSPLLSTAT - PLL status */ +/*! @{ */ +#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) +#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) +#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) +/*! @} */ + +/*! @name SYSPLLNDEC - PLL N decoder */ +/*! @{ */ +#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) +#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) +#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) +#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) +#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) +#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) +/*! @} */ + +/*! @name SYSPLLPDEC - PLL P decoder */ +/*! @{ */ +#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) +#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) +#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) +#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) +#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) +#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) +/*! @} */ + +/*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */ +/*! @{ */ +#define SYSCON_SYSPLLSSCTRL0_MDEC_MASK (0x1FFFFU) +#define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT (0U) +#define SYSCON_SYSPLLSSCTRL0_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK) +#define SYSCON_SYSPLLSSCTRL0_MREQ_MASK (0x20000U) +#define SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT (17U) +#define SYSCON_SYSPLLSSCTRL0_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MREQ_MASK) +#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK (0x40000U) +#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT (18U) +#define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) +/*! @} */ + +/*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */ +/*! @{ */ +#define SYSCON_SYSPLLSSCTRL1_MD_MASK (0x7FFFFU) +#define SYSCON_SYSPLLSSCTRL1_MD_SHIFT (0U) +#define SYSCON_SYSPLLSSCTRL1_MD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK) +#define SYSCON_SYSPLLSSCTRL1_MDREQ_MASK (0x80000U) +#define SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT (19U) +#define SYSCON_SYSPLLSSCTRL1_MDREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MDREQ_MASK) +#define SYSCON_SYSPLLSSCTRL1_MF_MASK (0x700000U) +#define SYSCON_SYSPLLSSCTRL1_MF_SHIFT (20U) +#define SYSCON_SYSPLLSSCTRL1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MF_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MF_MASK) +#define SYSCON_SYSPLLSSCTRL1_MR_MASK (0x3800000U) +#define SYSCON_SYSPLLSSCTRL1_MR_SHIFT (23U) +#define SYSCON_SYSPLLSSCTRL1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MR_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MR_MASK) +#define SYSCON_SYSPLLSSCTRL1_MC_MASK (0xC000000U) +#define SYSCON_SYSPLLSSCTRL1_MC_SHIFT (26U) +#define SYSCON_SYSPLLSSCTRL1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MC_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MC_MASK) +#define SYSCON_SYSPLLSSCTRL1_PD_MASK (0x10000000U) +#define SYSCON_SYSPLLSSCTRL1_PD_SHIFT (28U) +/*! PD - Spread spectrum power-down. + * 0b0..Enabled. Spread spectrum controller is enabled + * 0b1..Disabled. Spread spectrum controller is disabled. + */ +#define SYSCON_SYSPLLSSCTRL1_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_PD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_PD_MASK) +#define SYSCON_SYSPLLSSCTRL1_DITHER_MASK (0x20000000U) +#define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT (29U) +/*! DITHER - Select modulation frequency. + * 0b0..Fixed. Fixed modulation frequency. + * 0b1..Dither. Randomly dither between two modulation frequencies. + */ +#define SYSCON_SYSPLLSSCTRL1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK) +/*! @} */ + +/*! @name PDSLEEPCFG - Sleep configuration register n */ +/*! @{ */ +#define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK (0xFFFFFFFFU) +#define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT (0U) +#define SYSCON_PDSLEEPCFG_PD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK) +/*! @} */ + +/* The count of SYSCON_PDSLEEPCFG */ +#define SYSCON_PDSLEEPCFG_COUNT (2U) + +/*! @name PDRUNCFG - Power configuration register 0 */ +/*! @{ */ +#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) +#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) +#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) +#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U) +#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U) +#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U) +#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U) +#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK) +#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U) +#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U) +#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x2000U) +#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (13U) +#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK) +#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x10000U) +#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (16U) +#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK) +#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U) +#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U) +#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK) +#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U) +#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U) +#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U) +#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) +#define SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK (0x200000U) +#define SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT (21U) +#define SYSCON_PDRUNCFG_PDEN_USB_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) +#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) +#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U) +#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U) +#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK) +/*! @} */ + +/* The count of SYSCON_PDRUNCFG */ +#define SYSCON_PDRUNCFG_COUNT (1U) + +/*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */ +/*! @{ */ +#define SYSCON_PDRUNCFGSET_PD_SET_MASK (0xFFFFFFFFU) +#define SYSCON_PDRUNCFGSET_PD_SET_SHIFT (0U) +#define SYSCON_PDRUNCFGSET_PD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK) +/*! @} */ + +/* The count of SYSCON_PDRUNCFGSET */ +#define SYSCON_PDRUNCFGSET_COUNT (1U) + +/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */ +/*! @{ */ +#define SYSCON_PDRUNCFGCLR_PD_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT (0U) +#define SYSCON_PDRUNCFGCLR_PD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_PDRUNCFGCLR */ +#define SYSCON_PDRUNCFGCLR_COUNT (1U) + +/*! @name STARTER - Start logic n wake-up enable register */ +/*! @{ */ +#define SYSCON_STARTER_WDT_BOD_MASK (0x1U) +#define SYSCON_STARTER_WDT_BOD_SHIFT (0U) +#define SYSCON_STARTER_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK) +#define SYSCON_STARTER_DMA0_MASK (0x2U) +#define SYSCON_STARTER_DMA0_SHIFT (1U) +#define SYSCON_STARTER_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA0_SHIFT)) & SYSCON_STARTER_DMA0_MASK) +#define SYSCON_STARTER_GINT0_MASK (0x4U) +#define SYSCON_STARTER_GINT0_SHIFT (2U) +#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) +#define SYSCON_STARTER_GINT1_MASK (0x8U) +#define SYSCON_STARTER_GINT1_SHIFT (3U) +#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) +#define SYSCON_STARTER_PIN_INT0_MASK (0x10U) +#define SYSCON_STARTER_PIN_INT0_SHIFT (4U) +#define SYSCON_STARTER_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK) +#define SYSCON_STARTER_PIN_INT1_MASK (0x20U) +#define SYSCON_STARTER_PIN_INT1_SHIFT (5U) +#define SYSCON_STARTER_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK) +#define SYSCON_STARTER_PIN_INT2_MASK (0x40U) +#define SYSCON_STARTER_PIN_INT2_SHIFT (6U) +#define SYSCON_STARTER_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK) +#define SYSCON_STARTER_PIN_INT3_MASK (0x80U) +#define SYSCON_STARTER_PIN_INT3_SHIFT (7U) +#define SYSCON_STARTER_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK) +#define SYSCON_STARTER_UTICK0_MASK (0x100U) +#define SYSCON_STARTER_UTICK0_SHIFT (8U) +#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK) +#define SYSCON_STARTER_MRT0_MASK (0x200U) +#define SYSCON_STARTER_MRT0_SHIFT (9U) +#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK) +#define SYSCON_STARTER_CTIMER0_MASK (0x400U) +#define SYSCON_STARTER_CTIMER0_SHIFT (10U) +#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) +#define SYSCON_STARTER_CTIMER1_MASK (0x800U) +#define SYSCON_STARTER_CTIMER1_SHIFT (11U) +#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) +#define SYSCON_STARTER_SCT0_MASK (0x1000U) +#define SYSCON_STARTER_SCT0_SHIFT (12U) +#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) +#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) +#define SYSCON_STARTER_CTIMER3_SHIFT (13U) +#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) +#define SYSCON_STARTER_FLEXCOMM0_MASK (0x4000U) +#define SYSCON_STARTER_FLEXCOMM0_SHIFT (14U) +#define SYSCON_STARTER_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK) +#define SYSCON_STARTER_FLEXCOMM1_MASK (0x8000U) +#define SYSCON_STARTER_FLEXCOMM1_SHIFT (15U) +#define SYSCON_STARTER_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK) +#define SYSCON_STARTER_FLEXCOMM2_MASK (0x10000U) +#define SYSCON_STARTER_FLEXCOMM2_SHIFT (16U) +#define SYSCON_STARTER_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK) +#define SYSCON_STARTER_FLEXCOMM3_MASK (0x20000U) +#define SYSCON_STARTER_FLEXCOMM3_SHIFT (17U) +#define SYSCON_STARTER_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK) +#define SYSCON_STARTER_FLEXCOMM4_MASK (0x40000U) +#define SYSCON_STARTER_FLEXCOMM4_SHIFT (18U) +#define SYSCON_STARTER_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK) +#define SYSCON_STARTER_FLEXCOMM5_MASK (0x80000U) +#define SYSCON_STARTER_FLEXCOMM5_SHIFT (19U) +#define SYSCON_STARTER_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK) +#define SYSCON_STARTER_FLEXCOMM6_MASK (0x100000U) +#define SYSCON_STARTER_FLEXCOMM6_SHIFT (20U) +#define SYSCON_STARTER_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK) +#define SYSCON_STARTER_FLEXCOMM7_MASK (0x200000U) +#define SYSCON_STARTER_FLEXCOMM7_SHIFT (21U) +#define SYSCON_STARTER_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK) +#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) +#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) +#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) +#define SYSCON_STARTER_USB0_MASK (0x10000000U) +#define SYSCON_STARTER_USB0_SHIFT (28U) +#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) +#define SYSCON_STARTER_RTC_MASK (0x20000000U) +#define SYSCON_STARTER_RTC_SHIFT (29U) +#define SYSCON_STARTER_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK) +/*! @} */ + +/* The count of SYSCON_STARTER */ +#define SYSCON_STARTER_COUNT (1U) + +/*! @name STARTERSET - Set bits in STARTERn */ +/*! @{ */ +#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) +#define SYSCON_STARTERSET_START_SET_SHIFT (0U) +#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERSET */ +#define SYSCON_STARTERSET_COUNT (1U) + +/*! @name STARTERCLR - Clear bits in STARTERn */ +/*! @{ */ +#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) +#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) +#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) +/*! @} */ + +/* The count of SYSCON_STARTERCLR */ +#define SYSCON_STARTERCLR_COUNT (1U) + +/*! @name HWWAKE - Configures special cases of hardware wake-up */ +/*! @{ */ +#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) +#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) +#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) +#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U) +#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U) +#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK) +#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) +#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) +#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) +/*! @} */ + +/*! @name JTAGIDCODE - JTAG ID code register */ +/*! @{ */ +#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) +#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) +#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) +/*! @} */ + +/*! @name DEVICE_ID0 - Part ID register */ +/*! @{ */ +#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) +#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) +/*! @} */ + +/*! @name DEVICE_ID1 - Boot ROM and die revision register */ +/*! @{ */ +#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) +#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) +#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) +/*! @} */ + +/*! @name BODCTRL - Brown-Out Detect control */ +/*! @{ */ +#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) +#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) +/*! BODRSTLEV - BOD reset level + * 0b00..Level 0: 1.5 V + * 0b01..Level 1: 1.85 V + * 0b10..Level 2: 2.0 V + * 0b11..Level 3: 2.3 V + */ +#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) +#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U) +#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U) +/*! BODRSTENA - BOD reset enable + * 0b0..Disable reset function. + * 0b1..Enable reset function. + */ +#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) +#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U) +#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U) +/*! BODINTLEV - BOD interrupt level + * 0b00..Level 0: 2.05 V + * 0b01..Level 1: 2.45 V + * 0b10..Level 2: 2.75 V + * 0b11..Level 3: 3.05 V + */ +#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK) +#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U) +#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U) +/*! BODINTENA - BOD interrupt enable + * 0b0..Disable interrupt function. + * 0b1..Enable interrupt function. + */ +#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK) +#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U) +#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U) +#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK) +#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) +#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) +#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SYSCON_Register_Masks */ + + +/* SYSCON - Peripheral instance base addresses */ +/** Peripheral SYSCON base address */ +#define SYSCON_BASE (0x40000000u) +/** Peripheral SYSCON base pointer */ +#define SYSCON ((SYSCON_Type *)SYSCON_BASE) +/** Array initializer of SYSCON peripheral base addresses */ +#define SYSCON_BASE_ADDRS { SYSCON_BASE } +/** Array initializer of SYSCON peripheral base pointers */ +#define SYSCON_BASE_PTRS { SYSCON } + +/*! + * @} + */ /* end of group SYSCON_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USART Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer + * @{ + */ + +/** USART - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ + __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ + __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ + __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ + __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ + uint8_t RESERVED_0[12]; + __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ + __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ + __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ + __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ + uint8_t RESERVED_1[3536]; + __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ + __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ + __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ + uint8_t RESERVED_2[4]; + __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ + __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ + __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ + uint8_t RESERVED_3[4]; + __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ + uint8_t RESERVED_4[12]; + __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ + uint8_t RESERVED_5[12]; + __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ + uint8_t RESERVED_6[440]; + __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ +} USART_Type; + +/* ---------------------------------------------------------------------------- + -- USART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USART_Register_Masks USART Register Masks + * @{ + */ + +/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ +/*! @{ */ +#define USART_CFG_ENABLE_MASK (0x1U) +#define USART_CFG_ENABLE_SHIFT (0U) +/*! ENABLE - USART Enable. + * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. + * 0b1..Enabled. The USART is enabled for operation. + */ +#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) +#define USART_CFG_DATALEN_MASK (0xCU) +#define USART_CFG_DATALEN_SHIFT (2U) +/*! DATALEN - Selects the data size for the USART. + * 0b00..7 bit Data length. + * 0b01..8 bit Data length. + * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. + * 0b11..Reserved. + */ +#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) +#define USART_CFG_PARITYSEL_MASK (0x30U) +#define USART_CFG_PARITYSEL_SHIFT (4U) +/*! PARITYSEL - Selects what type of parity is used by the USART. + * 0b00..No parity. + * 0b01..Reserved. + * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. + * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. + */ +#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) +#define USART_CFG_STOPLEN_MASK (0x40U) +#define USART_CFG_STOPLEN_SHIFT (6U) +/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. + * 0b0..1 stop bit. + * 0b1..2 stop bits. This setting should only be used for asynchronous communication. + */ +#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) +#define USART_CFG_MODE32K_MASK (0x80U) +#define USART_CFG_MODE32K_SHIFT (7U) +/*! MODE32K - Selects standard or 32 kHz clocking mode. + * 0b0..Disabled. USART uses standard clocking. + * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. + */ +#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) +#define USART_CFG_LINMODE_MASK (0x100U) +#define USART_CFG_LINMODE_SHIFT (8U) +/*! LINMODE - LIN break mode enable. + * 0b0..Disabled. Break detect and generate is configured for normal operation. + * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. + */ +#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) +#define USART_CFG_CTSEN_MASK (0x200U) +#define USART_CFG_CTSEN_SHIFT (9U) +/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. + * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. + * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. + */ +#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) +#define USART_CFG_SYNCEN_MASK (0x800U) +#define USART_CFG_SYNCEN_SHIFT (11U) +/*! SYNCEN - Selects synchronous or asynchronous operation. + * 0b0..Asynchronous mode. + * 0b1..Synchronous mode. + */ +#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) +#define USART_CFG_CLKPOL_MASK (0x1000U) +#define USART_CFG_CLKPOL_SHIFT (12U) +/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. + * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. + * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. + */ +#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) +#define USART_CFG_SYNCMST_MASK (0x4000U) +#define USART_CFG_SYNCMST_SHIFT (14U) +/*! SYNCMST - Synchronous mode Master select. + * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. + * 0b1..Master. When synchronous mode is enabled, the USART is a master. + */ +#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) +#define USART_CFG_LOOP_MASK (0x8000U) +#define USART_CFG_LOOP_SHIFT (15U) +/*! LOOP - Selects data loopback mode. + * 0b0..Normal operation. + * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. + */ +#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) +#define USART_CFG_OETA_MASK (0x40000U) +#define USART_CFG_OETA_SHIFT (18U) +/*! OETA - Output Enable Turnaround time enable for RS-485 operation. + * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. + * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. + */ +#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) +#define USART_CFG_AUTOADDR_MASK (0x80000U) +#define USART_CFG_AUTOADDR_SHIFT (19U) +/*! AUTOADDR - Automatic Address matching enable. + * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). + * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. + */ +#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) +#define USART_CFG_OESEL_MASK (0x100000U) +#define USART_CFG_OESEL_SHIFT (20U) +/*! OESEL - Output Enable Select. + * 0b0..Standard. The RTS signal is used as the standard flow control function. + * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. + */ +#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) +#define USART_CFG_OEPOL_MASK (0x200000U) +#define USART_CFG_OEPOL_SHIFT (21U) +/*! OEPOL - Output Enable Polarity. + * 0b0..Low. If selected by OESEL, the output enable is active low. + * 0b1..High. If selected by OESEL, the output enable is active high. + */ +#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) +#define USART_CFG_RXPOL_MASK (0x400000U) +#define USART_CFG_RXPOL_SHIFT (22U) +/*! RXPOL - Receive data polarity. + * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) +#define USART_CFG_TXPOL_MASK (0x800000U) +#define USART_CFG_TXPOL_SHIFT (23U) +/*! TXPOL - Transmit data polarity. + * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. + * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. + */ +#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) +/*! @} */ + +/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ +/*! @{ */ +#define USART_CTL_TXBRKEN_MASK (0x2U) +#define USART_CTL_TXBRKEN_SHIFT (1U) +/*! TXBRKEN - Break Enable. + * 0b0..Normal operation. + * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. + */ +#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) +#define USART_CTL_ADDRDET_MASK (0x4U) +#define USART_CTL_ADDRDET_SHIFT (2U) +/*! ADDRDET - Enable address detect mode. + * 0b0..Disabled. The USART presents all incoming data. + * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. + */ +#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) +#define USART_CTL_TXDIS_MASK (0x40U) +#define USART_CTL_TXDIS_SHIFT (6U) +/*! TXDIS - Transmit Disable. + * 0b0..Not disabled. USART transmitter is not disabled. + * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. + */ +#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) +#define USART_CTL_CC_MASK (0x100U) +#define USART_CTL_CC_SHIFT (8U) +/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. + * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. + * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). + */ +#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) +#define USART_CTL_CLRCCONRX_MASK (0x200U) +#define USART_CTL_CLRCCONRX_SHIFT (9U) +/*! CLRCCONRX - Clear Continuous Clock. + * 0b0..No effect. No effect on the CC bit. + * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. + */ +#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) +#define USART_CTL_AUTOBAUD_MASK (0x10000U) +#define USART_CTL_AUTOBAUD_SHIFT (16U) +/*! AUTOBAUD - Autobaud enable. + * 0b0..Disabled. USART is in normal operating mode. + * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. + */ +#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) +/*! @} */ + +/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ +/*! @{ */ +#define USART_STAT_RXIDLE_MASK (0x2U) +#define USART_STAT_RXIDLE_SHIFT (1U) +#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) +#define USART_STAT_TXIDLE_MASK (0x8U) +#define USART_STAT_TXIDLE_SHIFT (3U) +#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) +#define USART_STAT_CTS_MASK (0x10U) +#define USART_STAT_CTS_SHIFT (4U) +#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) +#define USART_STAT_DELTACTS_MASK (0x20U) +#define USART_STAT_DELTACTS_SHIFT (5U) +#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) +#define USART_STAT_TXDISSTAT_MASK (0x40U) +#define USART_STAT_TXDISSTAT_SHIFT (6U) +#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) +#define USART_STAT_RXBRK_MASK (0x400U) +#define USART_STAT_RXBRK_SHIFT (10U) +#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) +#define USART_STAT_DELTARXBRK_MASK (0x800U) +#define USART_STAT_DELTARXBRK_SHIFT (11U) +#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) +#define USART_STAT_START_MASK (0x1000U) +#define USART_STAT_START_SHIFT (12U) +#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) +#define USART_STAT_FRAMERRINT_MASK (0x2000U) +#define USART_STAT_FRAMERRINT_SHIFT (13U) +#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) +#define USART_STAT_PARITYERRINT_MASK (0x4000U) +#define USART_STAT_PARITYERRINT_SHIFT (14U) +#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) +#define USART_STAT_RXNOISEINT_MASK (0x8000U) +#define USART_STAT_RXNOISEINT_SHIFT (15U) +#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) +#define USART_STAT_ABERR_MASK (0x10000U) +#define USART_STAT_ABERR_SHIFT (16U) +#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) +/*! @} */ + +/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ +/*! @{ */ +#define USART_INTENSET_TXIDLEEN_MASK (0x8U) +#define USART_INTENSET_TXIDLEEN_SHIFT (3U) +#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) +#define USART_INTENSET_DELTACTSEN_MASK (0x20U) +#define USART_INTENSET_DELTACTSEN_SHIFT (5U) +#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) +#define USART_INTENSET_TXDISEN_MASK (0x40U) +#define USART_INTENSET_TXDISEN_SHIFT (6U) +#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) +#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) +#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) +#define USART_INTENSET_STARTEN_MASK (0x1000U) +#define USART_INTENSET_STARTEN_SHIFT (12U) +#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) +#define USART_INTENSET_FRAMERREN_MASK (0x2000U) +#define USART_INTENSET_FRAMERREN_SHIFT (13U) +#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) +#define USART_INTENSET_PARITYERREN_MASK (0x4000U) +#define USART_INTENSET_PARITYERREN_SHIFT (14U) +#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) +#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) +#define USART_INTENSET_RXNOISEEN_SHIFT (15U) +#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) +#define USART_INTENSET_ABERREN_MASK (0x10000U) +#define USART_INTENSET_ABERREN_SHIFT (16U) +#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) +/*! @} */ + +/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ +/*! @{ */ +#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) +#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) +#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) +#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) +#define USART_INTENCLR_TXDISCLR_MASK (0x40U) +#define USART_INTENCLR_TXDISCLR_SHIFT (6U) +#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) +#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) +#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) +#define USART_INTENCLR_STARTCLR_MASK (0x1000U) +#define USART_INTENCLR_STARTCLR_SHIFT (12U) +#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) +#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) +#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) +#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) +#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) +#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) +#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) +#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) +#define USART_INTENCLR_ABERRCLR_SHIFT (16U) +#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) +/*! @} */ + +/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ +/*! @{ */ +#define USART_BRG_BRGVAL_MASK (0xFFFFU) +#define USART_BRG_BRGVAL_SHIFT (0U) +#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) +/*! @} */ + +/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ +/*! @{ */ +#define USART_INTSTAT_TXIDLE_MASK (0x8U) +#define USART_INTSTAT_TXIDLE_SHIFT (3U) +#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) +#define USART_INTSTAT_DELTACTS_MASK (0x20U) +#define USART_INTSTAT_DELTACTS_SHIFT (5U) +#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) +#define USART_INTSTAT_TXDISINT_MASK (0x40U) +#define USART_INTSTAT_TXDISINT_SHIFT (6U) +#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) +#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) +#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) +#define USART_INTSTAT_START_MASK (0x1000U) +#define USART_INTSTAT_START_SHIFT (12U) +#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) +#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) +#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) +#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) +#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) +#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) +#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) +#define USART_INTSTAT_ABERRINT_MASK (0x10000U) +#define USART_INTSTAT_ABERRINT_SHIFT (16U) +#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) +/*! @} */ + +/*! @name OSR - Oversample selection register for asynchronous communication. */ +/*! @{ */ +#define USART_OSR_OSRVAL_MASK (0xFU) +#define USART_OSR_OSRVAL_SHIFT (0U) +#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) +/*! @} */ + +/*! @name ADDR - Address register for automatic address matching. */ +/*! @{ */ +#define USART_ADDR_ADDRESS_MASK (0xFFU) +#define USART_ADDR_ADDRESS_SHIFT (0U) +#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) +/*! @} */ + +/*! @name FIFOCFG - FIFO configuration and enable register. */ +/*! @{ */ +#define USART_FIFOCFG_ENABLETX_MASK (0x1U) +#define USART_FIFOCFG_ENABLETX_SHIFT (0U) +/*! ENABLETX - Enable the transmit FIFO. + * 0b0..The transmit FIFO is not enabled. + * 0b1..The transmit FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) +#define USART_FIFOCFG_ENABLERX_MASK (0x2U) +#define USART_FIFOCFG_ENABLERX_SHIFT (1U) +/*! ENABLERX - Enable the receive FIFO. + * 0b0..The receive FIFO is not enabled. + * 0b1..The receive FIFO is enabled. + */ +#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) +#define USART_FIFOCFG_SIZE_MASK (0x30U) +#define USART_FIFOCFG_SIZE_SHIFT (4U) +#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) +#define USART_FIFOCFG_DMATX_MASK (0x1000U) +#define USART_FIFOCFG_DMATX_SHIFT (12U) +/*! DMATX - DMA configuration for transmit. + * 0b0..DMA is not used for the transmit function. + * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) +#define USART_FIFOCFG_DMARX_MASK (0x2000U) +#define USART_FIFOCFG_DMARX_SHIFT (13U) +/*! DMARX - DMA configuration for receive. + * 0b0..DMA is not used for the receive function. + * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. + */ +#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) +#define USART_FIFOCFG_WAKETX_MASK (0x4000U) +#define USART_FIFOCFG_WAKETX_SHIFT (14U) +/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) +#define USART_FIFOCFG_WAKERX_MASK (0x8000U) +#define USART_FIFOCFG_WAKERX_SHIFT (15U) +/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. + * 0b0..Only enabled interrupts will wake up the device form reduced power modes. + * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. + */ +#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) +#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) +#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) +#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) +#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) +/*! @} */ + +/*! @name FIFOSTAT - FIFO status register. */ +/*! @{ */ +#define USART_FIFOSTAT_TXERR_MASK (0x1U) +#define USART_FIFOSTAT_TXERR_SHIFT (0U) +#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) +#define USART_FIFOSTAT_RXERR_MASK (0x2U) +#define USART_FIFOSTAT_RXERR_SHIFT (1U) +#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) +#define USART_FIFOSTAT_PERINT_MASK (0x8U) +#define USART_FIFOSTAT_PERINT_SHIFT (3U) +#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) +#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) +#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) +#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) +#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) +#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) +#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) +#define USART_FIFOSTAT_RXFULL_MASK (0x80U) +#define USART_FIFOSTAT_RXFULL_SHIFT (7U) +#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) +#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) +#define USART_FIFOSTAT_TXLVL_SHIFT (8U) +#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) +#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) +#define USART_FIFOSTAT_RXLVL_SHIFT (16U) +#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ +/*! @{ */ +#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) +#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) +/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. + * 0b0..Transmit FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. + */ +#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) +#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) +#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) +/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. + * 0b0..Receive FIFO level does not generate a FIFO level trigger. + * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. + */ +#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) +#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) +#define USART_FIFOTRIG_TXLVL_SHIFT (8U) +#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) +#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) +#define USART_FIFOTRIG_RXLVL_SHIFT (16U) +#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENSET_TXERR_MASK (0x1U) +#define USART_FIFOINTENSET_TXERR_SHIFT (0U) +/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a transmit error. + * 0b1..An interrupt will be generated when a transmit error occurs. + */ +#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) +#define USART_FIFOINTENSET_RXERR_MASK (0x2U) +#define USART_FIFOINTENSET_RXERR_SHIFT (1U) +/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. + * 0b0..No interrupt will be generated for a receive error. + * 0b1..An interrupt will be generated when a receive error occurs. + */ +#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) +#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) +#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) +/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the TX FIFO level. + * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) +#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) +#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) +/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. + * 0b0..No interrupt will be generated based on the RX FIFO level. + * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. + */ +#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ +/*! @{ */ +#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) +#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) +#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) +#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) +#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) +#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) +#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) +#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) +/*! @} */ + +/*! @name FIFOINTSTAT - FIFO interrupt status register. */ +/*! @{ */ +#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) +#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) +#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) +#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) +#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) +#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) +#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) +#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) +#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) +#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) +/*! @} */ + +/*! @name FIFOWR - FIFO write data. */ +/*! @{ */ +#define USART_FIFOWR_TXDATA_MASK (0x1FFU) +#define USART_FIFOWR_TXDATA_SHIFT (0U) +#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) +/*! @} */ + +/*! @name FIFORD - FIFO read data. */ +/*! @{ */ +#define USART_FIFORD_RXDATA_MASK (0x1FFU) +#define USART_FIFORD_RXDATA_SHIFT (0U) +#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) +#define USART_FIFORD_FRAMERR_MASK (0x2000U) +#define USART_FIFORD_FRAMERR_SHIFT (13U) +#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) +#define USART_FIFORD_PARITYERR_MASK (0x4000U) +#define USART_FIFORD_PARITYERR_SHIFT (14U) +#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) +#define USART_FIFORD_RXNOISE_MASK (0x8000U) +#define USART_FIFORD_RXNOISE_SHIFT (15U) +#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) +/*! @} */ + +/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ +/*! @{ */ +#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) +#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) +#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) +#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) +#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) +#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) +#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) +#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) +/*! @} */ + +/*! @name ID - Peripheral identification register. */ +/*! @{ */ +#define USART_ID_APERTURE_MASK (0xFFU) +#define USART_ID_APERTURE_SHIFT (0U) +#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) +#define USART_ID_MINOR_REV_MASK (0xF00U) +#define USART_ID_MINOR_REV_SHIFT (8U) +#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) +#define USART_ID_MAJOR_REV_MASK (0xF000U) +#define USART_ID_MAJOR_REV_SHIFT (12U) +#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) +#define USART_ID_ID_MASK (0xFFFF0000U) +#define USART_ID_ID_SHIFT (16U) +#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USART_Register_Masks */ + + +/* USART - Peripheral instance base addresses */ +/** Peripheral USART0 base address */ +#define USART0_BASE (0x40086000u) +/** Peripheral USART0 base pointer */ +#define USART0 ((USART_Type *)USART0_BASE) +/** Peripheral USART1 base address */ +#define USART1_BASE (0x40087000u) +/** Peripheral USART1 base pointer */ +#define USART1 ((USART_Type *)USART1_BASE) +/** Peripheral USART2 base address */ +#define USART2_BASE (0x40088000u) +/** Peripheral USART2 base pointer */ +#define USART2 ((USART_Type *)USART2_BASE) +/** Peripheral USART3 base address */ +#define USART3_BASE (0x40089000u) +/** Peripheral USART3 base pointer */ +#define USART3 ((USART_Type *)USART3_BASE) +/** Peripheral USART4 base address */ +#define USART4_BASE (0x4008A000u) +/** Peripheral USART4 base pointer */ +#define USART4 ((USART_Type *)USART4_BASE) +/** Peripheral USART5 base address */ +#define USART5_BASE (0x40096000u) +/** Peripheral USART5 base pointer */ +#define USART5 ((USART_Type *)USART5_BASE) +/** Peripheral USART6 base address */ +#define USART6_BASE (0x40097000u) +/** Peripheral USART6 base pointer */ +#define USART6 ((USART_Type *)USART6_BASE) +/** Peripheral USART7 base address */ +#define USART7_BASE (0x40098000u) +/** Peripheral USART7 base pointer */ +#define USART7 ((USART_Type *)USART7_BASE) +/** Array initializer of USART peripheral base addresses */ +#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } +/** Array initializer of USART peripheral base pointers */ +#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } +/** Interrupt vectors for the USART peripheral type */ +#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } + +/*! + * @} + */ /* end of group USART_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- USB Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer + * @{ + */ + +/** USB - Register Layout Typedef */ +typedef struct { + __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ + __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ + __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ + __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ + __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ + __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ + __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ + __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ + __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ + __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ + __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ + uint8_t RESERVED_0[8]; + __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ +} USB_Type; + +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/*! @name DEVCMDSTAT - USB Device Command/Status register */ +/*! @{ */ +#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) +#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) +#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) +#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) +#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) +#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) +#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: + * 0b0..USB_NEEDCLK has normal function. + * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. + */ +#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) +#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) +#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported: + * 0b0..LPM not supported. + * 0b1..LPM supported. + */ +#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) +#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) +#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) +#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) +#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) +#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP + * 0b0..Only acknowledged packets generate an interrupt + * 0b1..Both acknowledged and NAKed packets generate interrupts. + */ +#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) +#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) +#define USB_DEVCMDSTAT_DCON_SHIFT (16U) +#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) +#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) +#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) +#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) +#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) +#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) +#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) +#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) +#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) +#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) +#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) +#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) +#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) +/*! @} */ + +/*! @name INFO - USB Info register */ +/*! @{ */ +#define USB_INFO_FRAME_NR_MASK (0x7FFU) +#define USB_INFO_FRAME_NR_SHIFT (0U) +#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) +#define USB_INFO_ERR_CODE_MASK (0x7800U) +#define USB_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred: + * 0b0000..No error + * 0b0001..PID encoding error + * 0b0010..PID unknown + * 0b0011..Packet unexpected + * 0b0100..Token CRC error + * 0b0101..Data CRC error + * 0b0110..Time out + * 0b0111..Babble + * 0b1000..Truncated EOP + * 0b1001..Sent/Received NAK + * 0b1010..Sent Stall + * 0b1011..Overrun + * 0b1100..Sent empty packet + * 0b1101..Bitstuff error + * 0b1110..Sync error + * 0b1111..Wrong data toggle + */ +#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) +/*! @} */ + +/*! @name EPLISTSTART - USB EP Command/Status List start address */ +/*! @{ */ +#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) +#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) +/*! @} */ + +/*! @name DATABUFSTART - USB Data buffer start address */ +/*! @{ */ +#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) +#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) +/*! @} */ + +/*! @name LPM - USB Link Power Management register */ +/*! @{ */ +#define USB_LPM_HIRD_HW_MASK (0xFU) +#define USB_LPM_HIRD_HW_SHIFT (0U) +#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) +#define USB_LPM_HIRD_SW_MASK (0xF0U) +#define USB_LPM_HIRD_SW_SHIFT (4U) +#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) +#define USB_LPM_DATA_PENDING_MASK (0x100U) +#define USB_LPM_DATA_PENDING_SHIFT (8U) +#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) +/*! @} */ + +/*! @name EPSKIP - USB Endpoint skip */ +/*! @{ */ +#define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU) +#define USB_EPSKIP_SKIP_SHIFT (0U) +#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) +/*! @} */ + +/*! @name EPINUSE - USB Endpoint Buffer in use */ +/*! @{ */ +#define USB_EPINUSE_BUF_MASK (0x3FCU) +#define USB_EPINUSE_BUF_SHIFT (2U) +#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) +/*! @} */ + +/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ +/*! @{ */ +#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) +#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) +/*! @} */ + +/*! @name INTSTAT - USB interrupt status register */ +/*! @{ */ +#define USB_INTSTAT_EP0OUT_MASK (0x1U) +#define USB_INTSTAT_EP0OUT_SHIFT (0U) +#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) +#define USB_INTSTAT_EP0IN_MASK (0x2U) +#define USB_INTSTAT_EP0IN_SHIFT (1U) +#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) +#define USB_INTSTAT_EP1OUT_MASK (0x4U) +#define USB_INTSTAT_EP1OUT_SHIFT (2U) +#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) +#define USB_INTSTAT_EP1IN_MASK (0x8U) +#define USB_INTSTAT_EP1IN_SHIFT (3U) +#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) +#define USB_INTSTAT_EP2OUT_MASK (0x10U) +#define USB_INTSTAT_EP2OUT_SHIFT (4U) +#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) +#define USB_INTSTAT_EP2IN_MASK (0x20U) +#define USB_INTSTAT_EP2IN_SHIFT (5U) +#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) +#define USB_INTSTAT_EP3OUT_MASK (0x40U) +#define USB_INTSTAT_EP3OUT_SHIFT (6U) +#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) +#define USB_INTSTAT_EP3IN_MASK (0x80U) +#define USB_INTSTAT_EP3IN_SHIFT (7U) +#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) +#define USB_INTSTAT_EP4OUT_MASK (0x100U) +#define USB_INTSTAT_EP4OUT_SHIFT (8U) +#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) +#define USB_INTSTAT_EP4IN_MASK (0x200U) +#define USB_INTSTAT_EP4IN_SHIFT (9U) +#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) +#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) +#define USB_INTSTAT_FRAME_INT_SHIFT (30U) +#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) +#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) +#define USB_INTSTAT_DEV_INT_SHIFT (31U) +#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) +/*! @} */ + +/*! @name INTEN - USB interrupt enable register */ +/*! @{ */ +#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) +#define USB_INTEN_EP_INT_EN_SHIFT (0U) +#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) +#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) +#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) +#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) +#define USB_INTEN_DEV_INT_EN_SHIFT (31U) +#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) +/*! @} */ + +/*! @name INTSETSTAT - USB set interrupt status register */ +/*! @{ */ +#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) +#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) +#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) +#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) +#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) +#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) +/*! @} */ + +/*! @name EPTOGGLE - USB Endpoint toggle register */ +/*! @{ */ +#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) +#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group USB_Register_Masks */ + + +/* USB - Peripheral instance base addresses */ +/** Peripheral USB0 base address */ +#define USB0_BASE (0x40084000u) +/** Peripheral USB0 base pointer */ +#define USB0 ((USB_Type *)USB0_BASE) +/** Array initializer of USB peripheral base addresses */ +#define USB_BASE_ADDRS { USB0_BASE } +/** Array initializer of USB peripheral base pointers */ +#define USB_BASE_PTRS { USB0 } +/** Interrupt vectors for the USB peripheral type */ +#define USB_IRQS { USB0_IRQn } +#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } + +/*! + * @} + */ /* end of group USB_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- UTICK Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer + * @{ + */ + +/** UTICK - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ + __IO uint32_t STAT; /**< Status register., offset: 0x4 */ + __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ + __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ + __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ +} UTICK_Type; + +/* ---------------------------------------------------------------------------- + -- UTICK Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UTICK_Register_Masks UTICK Register Masks + * @{ + */ + +/*! @name CTRL - Control register. */ +/*! @{ */ +#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) +#define UTICK_CTRL_DELAYVAL_SHIFT (0U) +#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) +#define UTICK_CTRL_REPEAT_MASK (0x80000000U) +#define UTICK_CTRL_REPEAT_SHIFT (31U) +#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) +/*! @} */ + +/*! @name STAT - Status register. */ +/*! @{ */ +#define UTICK_STAT_INTR_MASK (0x1U) +#define UTICK_STAT_INTR_SHIFT (0U) +#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) +#define UTICK_STAT_ACTIVE_MASK (0x2U) +#define UTICK_STAT_ACTIVE_SHIFT (1U) +#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) +/*! @} */ + +/*! @name CFG - Capture configuration register. */ +/*! @{ */ +#define UTICK_CFG_CAPEN0_MASK (0x1U) +#define UTICK_CFG_CAPEN0_SHIFT (0U) +#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) +#define UTICK_CFG_CAPEN1_MASK (0x2U) +#define UTICK_CFG_CAPEN1_SHIFT (1U) +#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) +#define UTICK_CFG_CAPEN2_MASK (0x4U) +#define UTICK_CFG_CAPEN2_SHIFT (2U) +#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) +#define UTICK_CFG_CAPEN3_MASK (0x8U) +#define UTICK_CFG_CAPEN3_SHIFT (3U) +#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) +#define UTICK_CFG_CAPPOL0_MASK (0x100U) +#define UTICK_CFG_CAPPOL0_SHIFT (8U) +#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) +#define UTICK_CFG_CAPPOL1_MASK (0x200U) +#define UTICK_CFG_CAPPOL1_SHIFT (9U) +#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) +#define UTICK_CFG_CAPPOL2_MASK (0x400U) +#define UTICK_CFG_CAPPOL2_SHIFT (10U) +#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) +#define UTICK_CFG_CAPPOL3_MASK (0x800U) +#define UTICK_CFG_CAPPOL3_SHIFT (11U) +#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) +/*! @} */ + +/*! @name CAPCLR - Capture clear register. */ +/*! @{ */ +#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) +#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) +#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) +#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) +#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) +#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) +#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) +#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) +/*! @} */ + +/*! @name CAP - Capture register . */ +/*! @{ */ +#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) +#define UTICK_CAP_CAP_VALUE_SHIFT (0U) +#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) +#define UTICK_CAP_VALID_MASK (0x80000000U) +#define UTICK_CAP_VALID_SHIFT (31U) +#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) +/*! @} */ + +/* The count of UTICK_CAP */ +#define UTICK_CAP_COUNT (4U) + + +/*! + * @} + */ /* end of group UTICK_Register_Masks */ + + +/* UTICK - Peripheral instance base addresses */ +/** Peripheral UTICK0 base address */ +#define UTICK0_BASE (0x4000E000u) +/** Peripheral UTICK0 base pointer */ +#define UTICK0 ((UTICK_Type *)UTICK0_BASE) +/** Array initializer of UTICK peripheral base addresses */ +#define UTICK_BASE_ADDRS { UTICK0_BASE } +/** Array initializer of UTICK peripheral base pointers */ +#define UTICK_BASE_PTRS { UTICK0 } +/** Interrupt vectors for the UTICK peripheral type */ +#define UTICK_IRQS { UTICK0_IRQn } + +/*! + * @} + */ /* end of group UTICK_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- WWDT Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer + * @{ + */ + +/** WWDT - Register Layout Typedef */ +typedef struct { + __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ + __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ + __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ + __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ + uint8_t RESERVED_0[4]; + __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ + __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ +} WWDT_Type; + +/* ---------------------------------------------------------------------------- + -- WWDT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WWDT_Register_Masks WWDT Register Masks + * @{ + */ + +/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ +/*! @{ */ +#define WWDT_MOD_WDEN_MASK (0x1U) +#define WWDT_MOD_WDEN_SHIFT (0U) +/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. + * 0b0..Stop. The watchdog timer is stopped. + * 0b1..Run. The watchdog timer is running. + */ +#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) +#define WWDT_MOD_WDRESET_MASK (0x2U) +#define WWDT_MOD_WDRESET_SHIFT (1U) +/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. + * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. + * 0b1..Reset. A watchdog time-out will cause a chip reset. + */ +#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) +#define WWDT_MOD_WDTOF_MASK (0x4U) +#define WWDT_MOD_WDTOF_SHIFT (2U) +#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) +#define WWDT_MOD_WDINT_MASK (0x8U) +#define WWDT_MOD_WDINT_SHIFT (3U) +#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) +#define WWDT_MOD_WDPROTECT_MASK (0x10U) +#define WWDT_MOD_WDPROTECT_SHIFT (4U) +/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. + * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. + * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. + */ +#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) +#define WWDT_MOD_LOCK_MASK (0x20U) +#define WWDT_MOD_LOCK_SHIFT (5U) +#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) +/*! @} */ + +/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ +/*! @{ */ +#define WWDT_TC_COUNT_MASK (0xFFFFFFU) +#define WWDT_TC_COUNT_SHIFT (0U) +#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) +/*! @} */ + +/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ +/*! @{ */ +#define WWDT_FEED_FEED_MASK (0xFFU) +#define WWDT_FEED_FEED_SHIFT (0U) +#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) +/*! @} */ + +/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ +/*! @{ */ +#define WWDT_TV_COUNT_MASK (0xFFFFFFU) +#define WWDT_TV_COUNT_SHIFT (0U) +#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) +/*! @} */ + +/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ +/*! @{ */ +#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) +#define WWDT_WARNINT_WARNINT_SHIFT (0U) +#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) +/*! @} */ + +/*! @name WINDOW - Watchdog Window compare value. */ +/*! @{ */ +#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) +#define WWDT_WINDOW_WINDOW_SHIFT (0U) +#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group WWDT_Register_Masks */ + + +/* WWDT - Peripheral instance base addresses */ +/** Peripheral WWDT base address */ +#define WWDT_BASE (0x4000C000u) +/** Peripheral WWDT base pointer */ +#define WWDT ((WWDT_Type *)WWDT_BASE) +/** Array initializer of WWDT peripheral base addresses */ +#define WWDT_BASE_ADDRS { WWDT_BASE } +/** Array initializer of WWDT peripheral base pointers */ +#define WWDT_BASE_PTRS { WWDT } +/** Interrupt vectors for the WWDT peripheral type */ +#define WWDT_IRQS { WDT_BOD_IRQn } + +/*! + * @} + */ /* end of group WWDT_Peripheral_Access_Layer */ + + +/* +** End of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop + #else + #pragma pop + #endif +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +/*! + * @} + */ /* end of group Peripheral_access_layer */ + + +/* ---------------------------------------------------------------------------- + -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). + * @{ + */ + +#if defined(__ARMCC_VERSION) + #if (__ARMCC_VERSION >= 6010050) + #pragma clang system_header + #endif +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma system_include +#endif + +/** + * @brief Mask and left-shift a bit field value for use in a register bit range. + * @param field Name of the register bit field. + * @param value Value of the bit field. + * @return Masked and shifted value. + */ +#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +/** + * @brief Mask and right-shift a register value to extract a bit field value. + * @param field Name of the register bit field. + * @param value Value of the register. + * @return Masked and shifted bit field value. + */ +#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) + +/*! + * @} + */ /* end of group Bit_Field_Generic_Macros */ + + +/* ---------------------------------------------------------------------------- + -- SDK Compatibility + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDK_Compatibility_Symbols SDK Compatibility + * @{ + */ + +/* No SDK compatibility issues. */ + +/*! + * @} + */ /* end of group SDK_Compatibility_Symbols */ + + +#endif /* _LPC51U68_H_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/LPC51U68_features.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/LPC51U68_features.h new file mode 100644 index 000000000..ac3633f58 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/LPC51U68_features.h @@ -0,0 +1,236 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2017-12-15 +** Build: b190225 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP +** All rights reserved. +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2017-12-15) +** Initial version. +** +** ################################################################### +*/ + +#ifndef _LPC51U68_FEATURES_H_ +#define _LPC51U68_FEATURES_H_ + +/* SOC module features */ + +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) +/* @brief ASYNC_SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (3) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (1) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (8) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (8) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (8) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (8) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) + +/* ADC module features */ + +/* @brief Do not has input select (register INSEL). */ +#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) +/* @brief Has startup register. */ +#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) +/* @brief Has ADTrim register */ +#define FSL_FEATURE_ADC_HAS_TRIM_REG (0) +/* @brief Has Calibration register. */ +#define FSL_FEATURE_ADC_HAS_CALIB_REG (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (18) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) + +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM7 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) + +/* I2S module features */ + +/* @brief I2S support dual channel transfer */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4) + +/* RTC module features */ + +/* @brief RTC has no reset control */ +#define FSL_FEATURE_RTC_HAS_NO_RESET (1) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8) + +/* SYSCON module features */ + +/* @brief Pointer to ROM IAP entry functions */ +#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144) +/* @brief IAP has Flash read & write function */ +#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) +/* @brief IAP has read Flash signature function */ +#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (1) +/* @brief IAP has read extended Flash signature function */ +#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (0) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* USB module features */ + +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) + +#endif /* _LPC51U68_FEATURES_H_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/fsl_device_registers.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/fsl_device_registers.h new file mode 100644 index 000000000..54354b263 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/fsl_device_registers.h @@ -0,0 +1,34 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef __FSL_DEVICE_REGISTERS_H__ +#define __FSL_DEVICE_REGISTERS_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if (defined(CPU_LPC51U68JBD48) || defined(CPU_LPC51U68JBD64)) + +#define LPC51U68_SERIES + +/* CMSIS-style register definitions */ +#include "LPC51U68.h" +/* CPU specific feature definitions */ +#include "LPC51U68_features.h" + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __FSL_DEVICE_REGISTERS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/system_LPC51U68.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/system_LPC51U68.c new file mode 100644 index 000000000..ce0256636 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/system_LPC51U68.c @@ -0,0 +1,343 @@ +/* +** ################################################################### +** Processors: LPC51U68JBD48 +** LPC51U68JBD64 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 +** Version: rev. 1.0, 2017-12-15 +** Build: b180802 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2017-12-15) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file LPC51U68 + * @version 1.0 + * @date 2017-12-15 + * @brief Device specific configuration file for LPC51U68 (implementation file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#include +#include "fsl_device_registers.h" + +#define NVALMAX (0x100) +#define PVALMAX (0x20) +#define MVALMAX (0x8000) +#define PLL_SSCG0_MDEC_VAL_P (0) /* MDEC is in bits 16 downto 0 */ +#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ +#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P) + +extern void *__Vectors; + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + + +static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, + 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; + +static uint32_t GetWdtOscFreq(void) +{ + uint8_t freq_sel, div_sel; + div_sel = ((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1) << 1; + freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; + return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); +} + +/* Find decoded N value for raw NDEC value */ +static uint32_t pllDecodeN(uint32_t NDEC) +{ + uint32_t n, x, i; + + /* Find NDec */ + switch (NDEC) + { + case 0xFFF: + n = 0; + break; + case 0x302: + n = 1; + break; + case 0x202: + n = 2; + break; + default: + x = 0x080; + n = 0xFFFFFFFF; + for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--) + { + x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); + if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) + { + /* Decoded value of NDEC */ + n = i; + } + } + break; + } + return n; +} + +/* Find decoded P value for raw PDEC value */ +static uint32_t pllDecodeP(uint32_t PDEC) +{ + uint32_t p, x, i; + /* Find PDec */ + switch (PDEC) + { + case 0xFF: + p = 0; + break; + case 0x62: + p = 1; + break; + case 0x42: + p = 2; + break; + default: + x = 0x10; + p = 0xFFFFFFFF; + for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--) + { + x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF); + if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) + { + /* Decoded value of PDEC */ + p = i; + } + } + break; + } + return p; +} + +/* Find decoded M value for raw MDEC value */ +static uint32_t pllDecodeM(uint32_t MDEC) +{ + uint32_t m, i, x; + + /* Find MDec */ + switch (MDEC) + { + case 0xFFFFF: + m = 0; + break; + case 0x18003: + m = 1; + break; + case 0x10003: + m = 2; + break; + default: + x = 0x04000; + m = 0xFFFFFFFF; + for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--) + { + x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); + if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) + { + /* Decoded value of MDEC */ + m = i; + } + } + break; + } + return m; +} + +/* Get predivider (N) from PLL NDEC setting */ +static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0) + { + /* Decode NDEC value to get (N) pre divider */ + preDiv = pllDecodeN(nDecReg & 0x3FF); + if (preDiv == 0) + { + preDiv = 1; + } + } + /* Adjusted by 1, directi is used to bypass */ + return preDiv; +} + +/* Get postdivider (P) from PLL PDEC setting */ +static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) +{ + uint32_t postDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0) + { + /* Decode PDEC value to get (P) post divider */ + postDiv = 2 * pllDecodeP(pDecReg & 0x7F); + if (postDiv == 0) + { + postDiv = 2; + } + } + /* Adjusted by 1, directo is used to bypass */ + return postDiv; +} + +/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ +static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) +{ + uint32_t mMult = 1; + + /* Decode MDEC value to get (M) multiplier */ + mMult = pllDecodeM(mDecReg & 0x1FFFF); + /* Extra multiply by 2 needed? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) == 0) + { + mMult = mMult << 1; + } + if (mMult == 0) + { + mMult = 1; + } + return mMult; +} + + + +/* ---------------------------------------------------------------------------- + -- Core clock + ---------------------------------------------------------------------------- */ + +uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; + +/* ---------------------------------------------------------------------------- + -- SystemInit() + ---------------------------------------------------------------------------- */ + +void SystemInit (void) { + +#if defined(__CODE_RED) + extern void(*const g_pfnVectors[]) (void); + SCB->VTOR = (uint32_t) &g_pfnVectors; +#else + extern void *__Vectors; + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +} + +/* ---------------------------------------------------------------------------- + -- SystemCoreClockUpdate() + ---------------------------------------------------------------------------- */ + +void SystemCoreClockUpdate (void) { + uint32_t clkRate = 0; + uint32_t prediv, postdiv; + uint64_t workRate; + + switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) + { + case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ + switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLK_FRO_12MHZ; + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLK_CLK_IN; + break; + case 0x02: /* Watchdog oscillator (wdt_clk) */ + clkRate = GetWdtOscFreq(); + break; + default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */ + if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) + { + clkRate = CLK_FRO_96MHZ; + } + else + { + clkRate = CLK_FRO_48MHZ; + } + break; + } + break; + case 0x02: /* System PLL clock (pll_clk)*/ + switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) + { + case 0x00: /* FRO 12 MHz (fro_12m) */ + clkRate = CLK_FRO_12MHZ; + break; + case 0x01: /* CLKIN (clk_in) */ + clkRate = CLK_CLK_IN; + break; + case 0x02: /* Watchdog oscillator (wdt_clk) */ + clkRate = GetWdtOscFreq(); + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLK_RTC_32K_CLK; + break; + default: + break; + } + if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0) + { + /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ + prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC); + postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC); + /* Adjust input clock */ + clkRate = clkRate / prediv; + /* If using the SS, use the multiplier */ + if (SYSCON->SYSPLLSSCTRL1 & SYSCON_SYSPLLSSCTRL1_PD_MASK) + { + /* MDEC used for rate */ + workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLSSCTRL0); + } + else + { + /* SS multipler used for rate */ + workRate = 0; + /* Adjust by fractional */ + workRate = workRate + ((clkRate * (uint64_t)((SYSCON->SYSPLLSSCTRL1 & 0x7FF) >> 0)) / 0x800); + } + clkRate = workRate / ((uint64_t)postdiv); + } + break; + case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ + clkRate = CLK_RTC_32K_CLK; + break; + default: + break; + } + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); + +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/system_LPC51U68.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/system_LPC51U68.h new file mode 100644 index 000000000..23a14cc72 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/device/system_LPC51U68.h @@ -0,0 +1,97 @@ +/* +** ################################################################### +** Processors: LPC51U68JBD48 +** LPC51U68JBD64 +** +** Compilers: Keil ARM C/C++ Compiler +** GNU C Compiler +** IAR ANSI C/C++ Compiler for ARM +** MCUXpresso Compiler +** +** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 +** Version: rev. 1.0, 2017-12-15 +** Build: b180802 +** +** Abstract: +** Provides a system configuration function and a global variable that +** contains the system frequency. It configures the device and initializes +** the oscillator (PLL) that is part of the microcontroller device. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2018 NXP +** +** SPDX-License-Identifier: BSD-3-Clause +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2017-12-15) +** Initial version. +** +** ################################################################### +*/ + +/*! + * @file LPC51U68 + * @version 1.0 + * @date 2017-12-15 + * @brief Device specific configuration file for LPC51U68 (header file) + * + * Provides a system configuration function and a global variable that contains + * the system frequency. It configures the device and initializes the oscillator + * (PLL) that is part of the microcontroller device. + */ + +#ifndef _SYSTEM_LPC51U68_H_ +#define _SYSTEM_LPC51U68_H_ /**< Symbol preventing repeated inclusion */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + + +#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ +#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ +#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ +#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ +#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ +#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */ + + +/** + * @brief System clock frequency (core clock) + * + * The system clock frequency supplied to the SysTick timer and the processor + * core clock. This variable can be used by the user application to setup the + * SysTick timer or configure other parameters. It may also be used by debugger to + * query the frequency of the debug timer or configure the trace clock speed + * SystemCoreClock is initialized with a correct predefined value. + */ +extern uint32_t SystemCoreClock; + +/** + * @brief Setup the microcontroller system. + * + * Typically this function configures the oscillator (PLL) that is part of the + * microcontroller device. For systems with variable clock speed it also updates + * the variable SystemCoreClock. SystemInit is called from startup_device file. + */ +void SystemInit (void); + +/** + * @brief Updates the SystemCoreClock variable. + * + * It must be called whenever the core clock is changed during program + * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates + * the current core clock. + */ +void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_LPC51U68_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_clock.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_clock.c new file mode 100644 index 000000000..96d1ec02e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_clock.c @@ -0,0 +1,1672 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2019 , NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +#include "fsl_power.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif +#define NVALMAX (0x100U) +#define PVALMAX (0x20U) +#define MVALMAX (0x8000U) + +#define PLL_MAX_N_DIV 0x100U + +#define INDEX_SECTOR_TRIM48 ((uint32_t *)0x01000444U) +#define INDEX_SECTOR_TRIM96 ((uint32_t *)0x01000430U) +/*-------------------------------------------------------------------------- +!!! If required these #defines can be moved to chip library file +----------------------------------------------------------------------------*/ + +#define PLL_SSCG0_MDEC_VAL_P (0U) /* MDEC is in bits 16 downto 0 */ +#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ +#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P) + +#define PLL_MIN_CCO_FREQ_MHZ (75000000U) +#define PLL_MAX_CCO_FREQ_MHZ (150000000U) +#define PLL_LOWER_IN_LIMIT (4000U) /*!< Minimum PLL input rate */ +#define PLL_MIN_IN_SSMODE (2000000U) +#define PLL_MAX_IN_SSMODE (4000000U) + +/* Middle of the range values for spread-spectrum */ +#define PLL_SSCG_MF_FREQ_VALUE 4U +#define PLL_SSCG_MC_COMP_VALUE 2U +#define PLL_SSCG_MR_DEPTH_VALUE 4U +#define PLL_SSCG_DITHER_VALUE 0U + +/* PLL NDEC reg */ +#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) +/* PLL PDEC reg */ +#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) +/* SSCG control0 */ +#define PLL_SSCG0_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_SSCG0_MDEC_VAL_P) & PLL_SSCG0_MDEC_VAL_M) + +/* SSCG control1 */ +#define PLL_SSCG1_MD_FRACT_P 0U +#define PLL_SSCG1_MD_INT_P 11U +#define PLL_SSCG1_MD_FRACT_M (0x7FFUL << PLL_SSCG1_MD_FRACT_P) +#define PLL_SSCG1_MD_INT_M (0xFFUL << PLL_SSCG1_MD_INT_P) + +#define PLL_SSCG1_MD_FRACT_SET(value) (((unsigned long)(value) << PLL_SSCG1_MD_FRACT_P) & PLL_SSCG1_MD_FRACT_M) +#define PLL_SSCG1_MD_INT_SET(value) (((unsigned long)(value) << PLL_SSCG1_MD_INT_P) & PLL_SSCG1_MD_INT_M) + +/* Saved value of PLL output rate, computed whenever needed to save run-time + computation on each call to retrive the PLL rate. */ +static uint32_t s_Pll_Freq; + +uint32_t g_I2S_Mclk_Freq = 0U; + +/** External clock rate on the CLKIN pin in Hz. If not used, + set this to 0. Otherwise, set it to the exact rate in Hz this pin is + being driven at. */ +const uint32_t g_Ext_Clk_Freq = 0U; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/* Find encoded NDEC value for raw N value, max N = NVALMAX */ +static uint32_t pllEncodeN(uint32_t N); +/* Find decoded N value for raw NDEC value */ +static uint32_t pllDecodeN(uint32_t NDEC); +/* Find encoded PDEC value for raw P value, max P = PVALMAX */ +static uint32_t pllEncodeP(uint32_t P); +/* Find decoded P value for raw PDEC value */ +static uint32_t pllDecodeP(uint32_t PDEC); +/* Find encoded MDEC value for raw M value, max M = MVALMAX */ +static uint32_t pllEncodeM(uint32_t M); +/* Find decoded M value for raw MDEC value */ +static uint32_t pllDecodeM(uint32_t MDEC); +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); +/* Get predivider (N) from PLL NDEC setting */ +static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg); +/* Get postdivider (P) from PLL PDEC setting */ +static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg); +/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ +static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg); +/* Get the greatest common divisor */ +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); +/* Set PLL output based on desired output rate */ +static pll_error_t CLOCK_GetPllConfig( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS); +/* Update local PLL rate variable */ +static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup); + +static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, + 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; +/******************************************************************************* + * Code + ******************************************************************************/ + +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection) +{ + uint8_t mux; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; + uint32_t i; + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->MAINCLKSELA); + + if (kNONE_to_NONE != connection) + { + for (i = 0U; i < 2U; i++) + { + if (tmp32 == 0U) + { + break; + } + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item) + { + mux = GET_ID_ITEM_MUX(item); + sel = GET_ID_ITEM_SEL(item); + if (mux == CM_ASYNCAPB) + { + ASYNC_SYSCON->ASYNCAPBCLKSELA = sel; + } + else + { + pClkSel[mux] = sel; + } + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ + } + } +} + +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint8_t mux; + uint8_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->MAINCLKSELA); + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = GET_ID_ITEM_MUX(tmp32); + if (tmp32) + { + if (mux == CM_ASYNCAPB) + { + actualSel = ASYNC_SYSCON->ASYNCAPBCLKSELA; + } + else + { + actualSel = pClkSel[mux]; + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * param reset : Whether to reset the divider counter. + * return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) +{ + volatile uint32_t *pClkDiv; + + pClkDiv = &(SYSCON->SYSTICKCLKDIV); + if (reset) + { + pClkDiv[div_name] = 1U << 29U; + } + if (divided_by_value == 0U) /* halt */ + { + pClkDiv[div_name] = 1U << 30U; + } + else + { + pClkDiv[div_name] = (divided_by_value - 1U); + } +} + +/* Set FRO Clocking */ +/** + * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) + * return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq) +{ + uint32_t usb_adj; + if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) + { + return kStatus_Fail; + } + /* Power up the FRO and set this as the base clock */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); + /* back up the value of whether USB adj is selected, in which case we will have a value of 1 else 0 */ + usb_adj = ((SYSCON->FROCTRL) & SYSCON_FROCTRL_USBCLKADJ_MASK) >> SYSCON_FROCTRL_USBCLKADJ_SHIFT; + if (iFreq > 12000000U) + { + if (iFreq == 96000000U) + { + SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM96) | + SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | + SYSCON_FROCTRL_HSPDCLK(1); + } + else + { + SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM48) | + SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | + SYSCON_FROCTRL_HSPDCLK(1); + } + } + else + { + SYSCON->FROCTRL &= ~SYSCON_FROCTRL_HSPDCLK(1); + } + + return 0U; +} + +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void) +{ + return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U; +} + +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void) +{ + return (g_Ext_Clk_Freq); +} +/*! brief Return Frequency of Watchdog Oscillator + * return Frequency of Watchdog Oscillator + */ +uint32_t CLOCK_GetWdtOscFreq(void) +{ + uint8_t freq_sel, div_sel; + if (SYSCON->PDRUNCFG[0] & (1UL << (kPDRUNCFG_PD_WDT_OSC & 0xffU))) + { + return 0U; + } + else + { + div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1; + freq_sel = + wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; + return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel); + } +} + +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void) +{ + return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? + 0 : + !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ? + 0 : + (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ? 96000000U : 48000000U; +} + +/*! brief Return Frequency of PLL + * return Frequency of PLL + */ +uint32_t CLOCK_GetPllOutFreq(void) +{ + return s_Pll_Freq; +} + +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void) +{ + return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */ +} +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void) +{ + return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ? + CLOCK_GetFro12MFreq() : + ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ? + CLOCK_GetExtClkFreq() : + ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ? + CLOCK_GetWdtOscFreq() : + ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ? + CLOCK_GetFroHfFreq() : + (SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() : + (SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U; +} +/*! brief Return Frequency of I2S MCLK Clock + * return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void) +{ + return g_I2S_Mclk_Freq; +} + +/*! brief Return Frequency of Asynchronous APB Clock + * return Frequency of Asynchronous APB Clock Clock + */ +uint32_t CLOCK_GetAsyncApbClkFreq(void) +{ + async_clock_src_t clkSrc; + uint32_t clkRate; + + clkSrc = CLOCK_GetAsyncApbClkSrc(); + + switch (clkSrc) + { + case kCLOCK_AsyncMainClk: + clkRate = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_AsyncFro12Mhz: + clkRate = CLK_FRO_12MHZ; + break; + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/*! brief Return Frequency of Flexcomm functional Clock + * return Frequency of Flexcomm functional Clock + */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) +{ + return (SYSCON->FXCOMCLKSEL[id] == 0U) ? + CLOCK_GetFro12MFreq() : + (SYSCON->FXCOMCLKSEL[id] == 1U) ? + CLOCK_GetFroHfFreq() : + (SYSCON->FXCOMCLKSEL[id] == 2U) ? + CLOCK_GetPllOutFreq() : + (SYSCON->FXCOMCLKSEL[id] == 3U) ? CLOCK_GetI2SMClkFreq() : + (SYSCON->FXCOMCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U; +} + +/* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc Clock. + */ +uint32_t CLOCK_GetAdcClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->ADCCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 7U: + freq = 0U; + break; + default: + break; + } + + return freq / ((SYSCON->ADCCLKDIV & 0xffU) + 1U); +} + +/*! brief Return Input frequency for the Fractional baud rate generator + * return Input Frequency for FRG + */ +uint32_t CLOCK_GetFRGInputClock(void) +{ + return (SYSCON->FRGCLKSEL == 0U) ? + CLOCK_GetCoreSysClkFreq() : + (SYSCON->FRGCLKSEL == 1U) ? + CLOCK_GetPllOutFreq() : + (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : + (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U; +} + +/*! brief Set output of the Fractional baud rate generator + * param freq : Desired output frequency + * return Error Code 0 - fail 1 - success + */ +uint32_t CLOCK_SetFRGClock(uint32_t freq) +{ + uint32_t input = CLOCK_GetFRGInputClock(); + uint32_t mul; + + if ((freq > 48000000) || (freq > input) || (input / freq >= 2)) + { + /* FRG output frequency should be less than equal to 48MHz */ + return 0; + } + else + { + mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); + SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK; + return 1; + } +} + +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName) +{ + uint32_t freq; + switch (clockName) + { + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case kCLOCK_BusClk: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_FroHf: + freq = CLOCK_GetFroHfFreq(); + break; + case kCLOCK_Fro12M: + freq = CLOCK_GetFro12MFreq(); + break; + case kCLOCK_PllOut: + freq = CLOCK_GetPllOutFreq(); + break; + case kCLOCK_UsbClk: + freq = (SYSCON->USBCLKSEL == 0U) ? CLOCK_GetFroHfFreq() : + (SYSCON->USBCLKSEL == 1) ? CLOCK_GetPllOutFreq() : 0U; + freq = freq / ((SYSCON->USBCLKDIV & 0xffU) + 1U); + break; + case kCLOCK_WdtOsc: + freq = CLOCK_GetWdtOscFreq(); + break; + case kCLOCK_Frg: + freq = ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK) ? + ((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) / + ((SYSCON_FRGCTRL_DIV_MASK + 1) + + ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)) : + 0; + break; + + case kCLOCK_AsyncApbClk: + freq = CLOCK_GetAsyncApbClkFreq(); + break; + + case kCLOCK_FlexI2S: + freq = CLOCK_GetI2SMClkFreq(); + break; + + case kCLOCK_Flexcomm0: + freq = CLOCK_GetFlexCommClkFreq(0U); + break; + case kCLOCK_Flexcomm1: + freq = CLOCK_GetFlexCommClkFreq(1U); + break; + case kCLOCK_Flexcomm2: + freq = CLOCK_GetFlexCommClkFreq(2U); + break; + case kCLOCK_Flexcomm3: + freq = CLOCK_GetFlexCommClkFreq(3U); + break; + case kCLOCK_Flexcomm4: + freq = CLOCK_GetFlexCommClkFreq(4U); + break; + case kCLOCK_Flexcomm5: + freq = CLOCK_GetFlexCommClkFreq(5U); + break; + case kCLOCK_Flexcomm6: + freq = CLOCK_GetFlexCommClkFreq(6U); + break; + case kCLOCK_Flexcomm7: + freq = CLOCK_GetFlexCommClkFreq(7U); + break; + default: + freq = 0U; + break; + } + + return freq; +} + +/* Set the FLASH wait states for the passed frequency */ +/** + * brief Set the flash wait states for the input freuqency. + * param iFreq : Input frequency + * return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) +{ + if (iFreq <= 12000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash1Cycle); + } + else if (iFreq <= 24000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash2Cycle); + } + else if (iFreq <= 48000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash3Cycle); + } + else if (iFreq <= 72000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash4Cycle); + } + else if (iFreq <= 84000000U) + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash5Cycle); + } + else + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash6Cycle); + } +} + +/* Find encoded NDEC value for raw N value, max N = NVALMAX */ +static uint32_t pllEncodeN(uint32_t N) +{ + uint32_t x, i; + + /* Find NDec */ + switch (N) + { + case 0U: + x = 0x3FFU; + break; + + case 1U: + x = 0x302U; + break; + + case 2U: + x = 0x202U; + break; + + default: + x = 0x080U; + for (i = N; i <= NVALMAX; i++) + { + x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); + } + break; + } + + return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P); +} + +/* Find decoded N value for raw NDEC value */ +static uint32_t pllDecodeN(uint32_t NDEC) +{ + uint32_t n, x, i; + + /* Find NDec */ + switch (NDEC) + { + case 0x3FFU: + n = 0U; + break; + + case 0x302U: + n = 1U; + break; + + case 0x202U: + n = 2U; + break; + + default: + x = 0x080U; + n = 0xFFFFFFFFU; + for (i = NVALMAX; ((i >= 3U) && (n == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); + if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) + { + /* Decoded value of NDEC */ + n = i; + } + } + break; + } + + return n; +} + +/* Find encoded PDEC value for raw P value, max P = PVALMAX */ +static uint32_t pllEncodeP(uint32_t P) +{ + uint32_t x, i; + + /* Find PDec */ + switch (P) + { + case 0U: + x = 0x7FU; + break; + + case 1U: + x = 0x62U; + break; + + case 2U: + x = 0x42U; + break; + + default: + x = 0x10U; + for (i = P; i <= PVALMAX; i++) + { + x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); + } + break; + } + + return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P); +} + +/* Find decoded P value for raw PDEC value */ +static uint32_t pllDecodeP(uint32_t PDEC) +{ + uint32_t p, x, i; + + /* Find PDec */ + switch (PDEC) + { + case 0x7FU: + p = 0U; + break; + + case 0x62U: + p = 1U; + break; + + case 0x42U: + p = 2U; + break; + + default: + x = 0x10U; + p = 0xFFFFFFFFU; + for (i = PVALMAX; ((i >= 3U) && (p == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); + if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) + { + /* Decoded value of PDEC */ + p = i; + } + } + break; + } + + return p; +} + +/* Find encoded MDEC value for raw M value, max M = MVALMAX */ +static uint32_t pllEncodeM(uint32_t M) +{ + uint32_t i, x; + + /* Find MDec */ + switch (M) + { + case 0U: + x = 0x1FFFFU; + break; + + case 1U: + x = 0x18003U; + break; + + case 2U: + x = 0x10003U; + break; + + default: + x = 0x04000U; + for (i = M; i <= MVALMAX; i++) + { + x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU); + } + break; + } + + return x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P); +} + +/* Find decoded M value for raw MDEC value */ +static uint32_t pllDecodeM(uint32_t MDEC) +{ + uint32_t m, i, x; + + /* Find MDec */ + switch (MDEC) + { + case 0x1FFFFU: + m = 0U; + break; + + case 0x18003U: + m = 1U; + break; + + case 0x10003U: + m = 2U; + break; + + default: + x = 0x04000U; + m = 0xFFFFFFFFU; + for (i = MVALMAX; ((i >= 3U) && (m == 0xFFFFFFFFU)); i--) + { + x = (((x ^ (x >> 1U)) & 1) << 14U) | ((x >> 1U) & 0x3FFFU); + if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) + { + /* Decoded value of MDEC */ + m = i; + } + } + break; + } + + return m; +} + +/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ +static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) +{ + /* bandwidth: compute selP from Multiplier */ + if (M < 60U) + { + *pSelP = (M >> 1U) + 1U; + } + else + { + *pSelP = PVALMAX - 1U; + } + + /* bandwidth: compute selI from Multiplier */ + if (M > 16384U) + { + *pSelI = 1U; + } + else if (M > 8192U) + { + *pSelI = 2U; + } + else if (M > 2048U) + { + *pSelI = 4U; + } + else if (M >= 501U) + { + *pSelI = 8U; + } + else if (M >= 60U) + { + *pSelI = 4U * (1024U / (M + 9U)); + } + else + { + *pSelI = (M & 0x3CU) + 4U; + } + + if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT)) + { + *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT); + } + + *pSelR = 0U; +} + +/* Get predivider (N) from PLL NDEC setting */ +static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) +{ + uint32_t preDiv = 1; + + /* Direct input is not used? */ + if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U) + { + /* Decode NDEC value to get (N) pre divider */ + preDiv = pllDecodeN(nDecReg & 0x3FFU); + if (preDiv == 0U) + { + preDiv = 1U; + } + } + + /* Adjusted by 1, directi is used to bypass */ + return preDiv; +} + +/* Get postdivider (P) from PLL PDEC setting */ +static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) +{ + uint32_t postDiv = 1U; + + /* Direct input is not used? */ + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U) + { + /* Decode PDEC value to get (P) post divider */ + postDiv = 2U * pllDecodeP(pDecReg & 0x7FU); + if (postDiv == 0U) + { + postDiv = 2U; + } + } + + /* Adjusted by 1, directo is used to bypass */ + return postDiv; +} + +/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ +static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) +{ + uint32_t mMult = 1U; + + /* Decode MDEC value to get (M) multiplier */ + mMult = pllDecodeM(mDecReg & 0x1FFFFU); + + /* Extra multiply by 2 needed? */ + if ((ctrlReg & (SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK)) == 0U) + { + mMult = mMult << 1U; + } + + if (mMult == 0U) + { + mMult = 1U; + } + + return mMult; +} + +static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) +{ + uint32_t tmp; + + while (n != 0U) + { + tmp = n; + n = m % n; + m = tmp; + } + + return m; +} + +/* + * Set PLL output based on desired output rate. + * In this function, the it calculates the PLL setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPllConfigInternal( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) +{ + uint32_t nDivOutHz, fccoHz, multFccoDiv; + uint32_t pllPreDivider, pllMultiplier, pllBypassFBDIV2, pllPostDivider; + uint32_t pllDirectInput, pllDirectOutput; + uint32_t pllSelP, pllSelI, pllSelR, bandsel, uplimoff; + + /* Baseline parameters (no input or output dividers) */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 0U; /* 0 implies post-divider will be disabled */ + pllDirectOutput = 1U; + if (useFeedbackDiv2) + { + /* Using feedback divider for M, so disable bypass */ + pllBypassFBDIV2 = 0U; + } + else + { + pllBypassFBDIV2 = 1U; + } + multFccoDiv = (2U - pllBypassFBDIV2); + + /* Verify output rate parameter */ + if (foutHz > PLL_MAX_CCO_FREQ_MHZ) + { + /* Maximum PLL output with post divider=1 cannot go above this frequency */ + return kStatus_PLL_OutputTooHigh; + } + if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) + { + /* Minmum PLL output with maximum post divider cannot go below this frequency */ + return kStatus_PLL_OutputTooLow; + } + + /* If using SS mode, input clock needs to be between 2MHz and 4MHz */ + if (useSS) + { + /* Verify input rate parameter */ + if (finHz < PLL_MIN_IN_SSMODE) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + /* PLL input in SS mode must be under 4MHz */ + pllPreDivider = finHz / ((PLL_MIN_IN_SSMODE + PLL_MAX_IN_SSMODE) / 2); + if (pllPreDivider > NVALMAX) + { + return kStatus_PLL_InputTooHigh; + } + } + else + { + /* Verify input rate parameter */ + if (finHz < PLL_LOWER_IN_LIMIT) + { + /* Input clock into the PLL cannot be lower than this */ + return kStatus_PLL_InputTooLow; + } + } + + /* Find the optimal CCO frequency for the output and input that + will keep it inside the PLL CCO range. This may require + tweaking the post-divider for the PLL. */ + fccoHz = foutHz; + while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) + { + /* CCO output is less than minimum CCO range, so the CCO output + needs to be bumped up and the post-divider is used to bring + the PLL output back down. */ + pllPostDivider++; + if (pllPostDivider > PVALMAX) + { + return kStatus_PLL_OutsideIntLimit; + } + + /* Target CCO goes up, PLL output goes down */ + fccoHz = foutHz * (pllPostDivider * 2U); + pllDirectOutput = 0U; + } + + /* Determine if a pre-divider is needed to get the best frequency */ + if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) + { + uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz)); + + if (a > 20000U) + { + a = (multFccoDiv * finHz) / a; + if ((a != 0U) && (a < PLL_MAX_N_DIV)) + { + pllPreDivider = a; + } + } + } + + /* Bypass pre-divider hardware if pre-divider is 1 */ + if (pllPreDivider > 1U) + { + pllDirectInput = 0U; + } + else + { + pllDirectInput = 1U; + } + + /* Determine PLL multipler */ + nDivOutHz = (finHz / pllPreDivider); + pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv; + + /* Find optimal values for filter */ + if (useSS == false) + { + /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ + if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) + { + pllMultiplier++; + } + + /* Setup filtering */ + pllFindSel(pllMultiplier, pllBypassFBDIV2, &pllSelP, &pllSelI, &pllSelR); + bandsel = 1U; + uplimoff = 0U; + + /* Get encoded value for M (mult) and use manual filter, disable SS mode */ + pSetup->syspllssctrl[0] = + (PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) | (1U << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)); + + /* Power down SSC, not used */ + pSetup->syspllssctrl[1] = (1U << SYSCON_SYSPLLSSCTRL1_PD_SHIFT); + } + else + { + uint64_t fc; + + /* Filtering will be handled by SSC */ + pllSelR = pllSelI = pllSelP = 0U; + bandsel = 0U; + uplimoff = 1U; + + /* The PLL multiplier will get very close and slightly under the + desired target frequency. A small fractional component can be + added to fine tune the frequency upwards to the target. */ + fc = ((uint64_t)(fccoHz % (multFccoDiv * nDivOutHz)) << 11U) / (multFccoDiv * nDivOutHz); + + /* MDEC set by SSC */ + pSetup->syspllssctrl[0U] = 0U; + + /* Set multiplier */ + pSetup->syspllssctrl[1] = PLL_SSCG1_MD_INT_SET(pllMultiplier) | PLL_SSCG1_MD_FRACT_SET((uint32_t)fc); + } + + /* Get encoded values for N (prediv) and P (postdiv) */ + pSetup->syspllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider)); + pSetup->syspllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider)); + + /* PLL control */ + pSetup->syspllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) | /* Filter coefficient */ + (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) | /* PLL bypass mode disabled */ + (pllBypassFBDIV2 << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT) | /* Extra M / 2 divider? */ + (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) | /* SS/fractional mode disabled */ + (bandsel << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT) | /* Manual bandwidth selection enabled */ + (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */ + + return kStatus_PLL_Success; +} + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +bool gUseFeedbackDiv2Cache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +bool gUseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +uint32_t gPllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPllConfig( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]) && (useFeedbackDiv2 == gUseFeedbackDiv2Cache[i]) && + (useSS == gUseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->syspllctrl = gPllSetupCacheStruct[i].syspllctrl; + pSetup->syspllndec = gPllSetupCacheStruct[i].syspllndec; + pSetup->syspllpdec = gPllSetupCacheStruct[i].syspllpdec; + pSetup->syspllssctrl[0] = gPllSetupCacheStruct[i].syspllssctrl[0]; + pSetup->syspllssctrl[1] = gPllSetupCacheStruct[i].syspllssctrl[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup, useFeedbackDiv2, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + gFinHzCache[gPllSetupCacheIdx] = finHz; + gFoutHzCache[gPllSetupCacheIdx] = foutHz; + gUseFeedbackDiv2Cache[gPllSetupCacheIdx] = useFeedbackDiv2; + gUseSSCache[gPllSetupCacheIdx] = useSS; + + gPllSetupCacheStruct[gPllSetupCacheIdx].syspllctrl = pSetup->syspllctrl; + gPllSetupCacheStruct[gPllSetupCacheIdx].syspllndec = pSetup->syspllndec; + gPllSetupCacheStruct[gPllSetupCacheIdx].syspllpdec = pSetup->syspllpdec; + gPllSetupCacheStruct[gPllSetupCacheIdx].syspllssctrl[0] = pSetup->syspllssctrl[0]; + gPllSetupCacheStruct[gPllSetupCacheIdx].syspllssctrl[1] = pSetup->syspllssctrl[1]; + /* Update the index for next available buffer. */ + gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + +/* Update local PLL rate variable */ +static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup) +{ + s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup); +} + +/* Return System PLL input clock rate */ +/*! brief Return System PLL input clock rate + * return System PLL input clock rate + */ +uint32_t CLOCK_GetSystemPLLInClockRate(void) +{ + uint32_t clkRate = 0U; + + switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)) + { + case 0x00U: + clkRate = CLK_FRO_12MHZ; + break; + + case 0x01U: + clkRate = CLOCK_GetExtClkFreq(); + break; + + case 0x02U: + clkRate = CLOCK_GetWdtOscFreq(); + break; + + case 0x03U: + clkRate = CLOCK_GetOsc32KFreq(); + break; + + default: + clkRate = 0U; + break; + } + + return clkRate; +} + +/* Return System PLL output clock rate from setup structure */ +/*! brief Return System PLL output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return System PLL output clock rate calculated from the setup structure + */ +uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) +{ + uint32_t prediv, postdiv, mMult, inPllRate; + uint64_t workRate; + + /* Get the input clock frequency of PLL. */ + inPllRate = CLOCK_GetSystemPLLInClockRate(); + + /* + * If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock. + */ + if ((pSetup->syspllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U) + { + /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */ + /* + * 1. Pre-divider + * Pre-divider is only available when the DIRECTI is disabled. + */ + if (0U == (pSetup->syspllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK)) + { + prediv = findPllPreDiv(pSetup->syspllctrl, pSetup->syspllndec); + } + else + { + prediv = 1U; /* The pre-divider is bypassed. */ + } + /* Adjust input clock */ + inPllRate = inPllRate / prediv; + + /* + * 2. M divider + * If using the SS, use the multiplier. + */ + if (pSetup->syspllssctrl[1] & (SYSCON_SYSPLLSSCTRL1_PD_MASK)) + { + /* MDEC used for rate */ + mMult = findPllMMult(pSetup->syspllctrl, pSetup->syspllssctrl[0]); + workRate = (uint64_t)inPllRate * (uint64_t)mMult; + } + else + { + uint64_t fract; + + /* SS multipler used for rate */ + mMult = (pSetup->syspllssctrl[1] & PLL_SSCG1_MD_INT_M) >> PLL_SSCG1_MD_INT_P; + workRate = (uint64_t)inPllRate * (uint64_t)mMult; + + /* Adjust by fractional */ + fract = (uint64_t)(pSetup->syspllssctrl[1] & PLL_SSCG1_MD_FRACT_M) >> PLL_SSCG1_MD_FRACT_P; + workRate = workRate + ((inPllRate * fract) / 0x800U); + } + + /* + * 3. Post-divider + * Post-divider is only available when the DIRECTO is disabled. + */ + if (0U == (pSetup->syspllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK)) + { + postdiv = findPllPostDiv(pSetup->syspllctrl, pSetup->syspllpdec); + } + else + { + postdiv = 1U; /* The post-divider is bypassed. */ + } + workRate = workRate / ((uint64_t)postdiv); + } + else + { + /* In bypass mode */ + workRate = (uint64_t)inPllRate; + } + + return (uint32_t)workRate; +} + +/* Set the current PLL Rate */ +/*! brief Store the current PLL rate + * param rate: Current rate of the PLL + * return Nothing + **/ +void CLOCK_SetStoredPLLClockRate(uint32_t rate) +{ + s_Pll_Freq = rate; +} + +/* Return System PLL output clock rate */ +/*! brief Return System PLL output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return System PLL output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) +{ + pll_setup_t Setup; + uint32_t rate; + + if ((recompute) || (s_Pll_Freq == 0U)) + { + Setup.syspllctrl = SYSCON->SYSPLLCTRL; + Setup.syspllndec = SYSCON->SYSPLLNDEC; + Setup.syspllpdec = SYSCON->SYSPLLPDEC; + Setup.syspllssctrl[0] = SYSCON->SYSPLLSSCTRL0; + Setup.syspllssctrl[1] = SYSCON->SYSPLLSSCTRL1; + + CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup); + } + + rate = s_Pll_Freq; + + return rate; +} + +/* Set PLL output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) +{ + uint32_t inRate; + bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); + bool useFbDiv2; + + pll_error_t pllError; + + /* Determine input rate for the PLL */ + if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) + { + inRate = pControl->inputRate; + } + else + { + inRate = CLOCK_GetSystemPLLInClockRate(); + } + + if ((pSetup->flags & PLL_SETUPFLAG_USEFEEDBACKDIV2) != 0U) + { + useFbDiv2 = true; + } + else + { + useFbDiv2 = false; + } + + /* PLL flag options */ + pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup, useFbDiv2, useSS); + if ((useSS) && (pllError == kStatus_PLL_Success)) + { + /* If using SS mode, then some tweaks are made to the generated setup */ + pSetup->syspllssctrl[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; + if (pControl->mfDither) + { + pSetup->syspllssctrl[1] |= (1U << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT); + } + } + + return pllError; +} + +/* Set PLL output from PLL setup structure */ +/*! brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) +{ + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); + + pSetup->flags = flagcfg; + + /* Write PLL setup data */ + SYSCON->SYSPLLCTRL = pSetup->syspllctrl; + SYSCON->SYSPLLNDEC = pSetup->syspllndec; + SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->SYSPLLPDEC = pSetup->syspllpdec; + SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0]; + SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */ + SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1]; + SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1] | (1U << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT); /* latch */ + + /* Flags for lock or power on */ + if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U) + { + /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ + volatile uint32_t delayX; + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U); + + /* Initialize and power up PLL */ + SYSCON->SYSPLLSSCTRL0 = maxCCO; + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + + /* Set mreq to activate */ + SYSCON->SYSPLLSSCTRL0 = maxCCO | (1U << 17U); + + /* Delay for 72 uSec @ 12Mhz */ + for (delayX = 0U; delayX < 172U; ++delayX) + { + } + + /* clear mreq to prepare for restoring mreq */ + SYSCON->SYSPLLSSCTRL0 = curSSCTRL; + + /* set original value back and activate */ + SYSCON->SYSPLLSSCTRL0 = curSSCTRL | (1U << 17U); + + /* Enable peripheral states by setting low */ + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + } + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + while (CLOCK_IsSystemPLLLocked() == false) + { + } + } + + /* Update current programmed PLL rate var */ + CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup); + + /* System voltage adjustment, occurs prior to setting main system clock */ + if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) + { + POWER_SetVoltageForFreq(s_Pll_Freq); + } + + return kStatus_PLL_Success; +} + +/* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) +{ + /* Power off PLL during setup changes */ + POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); + + /* Write PLL setup data */ + SYSCON->SYSPLLCTRL = pSetup->syspllctrl; + SYSCON->SYSPLLNDEC = pSetup->syspllndec; + SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->SYSPLLPDEC = pSetup->syspllpdec; + SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0]; + SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */ + SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1]; + SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1] | (1U << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT); /* latch */ + + /* Flags for lock or power on */ + if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) + { + /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ + volatile uint32_t delayX; + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U); + + /* Initialize and power up PLL */ + SYSCON->SYSPLLSSCTRL0 = maxCCO; + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + + /* Set mreq to activate */ + SYSCON->SYSPLLSSCTRL0 = maxCCO | (1U << 17U); + + /* Delay for 72 uSec @ 12Mhz */ + for (delayX = 0U; delayX < 172U; ++delayX) + { + } + + /* clear mreq to prepare for restoring mreq */ + SYSCON->SYSPLLSSCTRL0 = curSSCTRL; + + /* set original value back and activate */ + SYSCON->SYSPLLSSCTRL0 = curSSCTRL | (1U << 17U); + + /* Enable peripheral states by setting low */ + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); + } + if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) + { + while (CLOCK_IsSystemPLLLocked() == false) + { + } + } + + /* Update current programmed PLL rate var */ + s_Pll_Freq = pSetup->pllRate; + + return kStatus_PLL_Success; +} + +/* Set System PLL clock based on the input frequency and multiplier */ +/*! brief Set PLL output based on the multiplier and input frequency + * param multiply_by : multiplier + * param input_freq : Clock input frequency of the PLL + * return Nothing + * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ +void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) +{ + uint32_t cco_freq = input_freq * multiply_by; + uint32_t pdec = 1U; + uint32_t selr; + uint32_t seli; + uint32_t selp; + uint32_t mdec, ndec; + + uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1); + + while (cco_freq < 75000000U) + { + multiply_by <<= 1U; /* double value in each iteration */ + pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ + cco_freq = input_freq * multiply_by; + } + selr = 0U; + if (multiply_by < 60U) + { + seli = (multiply_by & 0x3cU) + 4U; + selp = (multiply_by >> 1U) + 1U; + } + else + { + selp = 31U; + if (multiply_by > 16384U) + { + seli = 1U; + } + else if (multiply_by > 8192U) + { + seli = 2U; + } + else if (multiply_by > 2048U) + { + seli = 4U; + } + else if (multiply_by >= 501U) + { + seli = 8U; + } + else + { + seli = 4U * (1024U / (multiply_by + 9U)); + } + } + + if (pdec > 1U) + { + directo = 0U; /* use post divider */ + pdec = pdec / 2U; /* Account for minus 1 encoding */ + /* Translate P value */ + switch (pdec) + { + case 1U: + pdec = 0x62U; /* 1 * 2 */ + break; + case 2U: + pdec = 0x42U; /* 2 * 2 */ + break; + case 4U: + pdec = 0x02U; /* 4 * 2 */ + break; + case 8U: + pdec = 0x0bU; /* 8 * 2 */ + break; + case 16U: + pdec = 0x11U; /* 16 * 2 */ + break; + case 32U: + pdec = 0x08U; /* 32 * 2 */ + break; + default: + pdec = 0x08U; + break; + } + } + + mdec = PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(multiply_by)); + ndec = 0x302U; /* pre divide by 1 (hardcoded) */ + + SYSCON->SYSPLLCTRL = SYSCON_SYSPLLCTRL_BANDSEL(1) | directo | SYSCON_SYSPLLCTRL_BYPASSCCODIV2(1) | + (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) | + (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT); + SYSCON->SYSPLLPDEC = pdec | (1U << 7U); /* set Pdec value and assert preq */ + SYSCON->SYSPLLNDEC = ndec | (1U << 10U); /* set Pdec value and assert preq */ + SYSCON->SYSPLLSSCTRL0 = + (1U << 18U) | (1U << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */ +} +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) +{ + bool ret = true; + + CLOCK_DisableClock(kCLOCK_Usbd0); + + if (kCLOCK_UsbSrcFro == src) + { + switch (freq) + { + case 96000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsbClk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ + break; + case 48000000U: + CLOCK_SetClkDiv(kCLOCK_DivUsbClk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ + break; + default: + ret = false; + break; + } + /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ + SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | + SYSCON_FROCTRL_USBCLKADJ_MASK; + /* select FRO 96 or 48 MHz */ + CLOCK_AttachClk(kFRO_HF_to_USB_CLK); + } + else + { + /*TODO , we only implement FRO as usb clock source*/ + ret = false; + } + + CLOCK_EnableClock(kCLOCK_Usbd0); + + return ret; +} + +/*! + * brief Delay at least for several microseconds. + * Please note that, this API will calculate the microsecond period with the maximum devices + * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise + * delay count was needed, please implement a new timer count to achieve this function. + * + * param delay_us Delay time in unit of microsecond. + */ +__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us) +{ + assert(0U != delay_us); + + uint32_t count = (uint32_t)USEC_TO_COUNT(delay_us, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* + * Calculate the real delay count depend on the excute instructions cycles, + * users can change the divider value to adapt to the real IDE optimise level. + */ + count = (count / 4U); + + for (; count > 0UL; count--) + { + __NOP(); + } +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_clock.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_clock.h new file mode 100644 index 000000000..697440948 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_clock.h @@ -0,0 +1,850 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2019 , NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.2.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (96000000UL) +#endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/*! @brief Clock ip name array for FLEXCOMM. */ +#define FLEXCOMM_CLOCKS \ + { \ + kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ + kCLOCK_FlexComm6, kCLOCK_FlexComm7 \ + } +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ + kCLOCK_MinUart6, kCLOCK_MinUart7 \ + } + +/*! @brief Clock ip name array for BI2C. */ +#define BI2C_CLOCKS \ + { \ + kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ + } +/*! @brief Clock ip name array for LSPI. */ +#define LPSI_CLOCKS \ + { \ + kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ + } +/*! @brief Clock ip name array for FLEXI2S. */ +#define FLEXI2S_CLOCKS \ + { \ + kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ + kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ + } +/*! @brief Clock ip name array for UTICK. */ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick \ + } +/*! @brief Clock ip name array for DMA. */ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma \ + } +/*! @brief Clock ip name array for CT32B. */ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Ctimer0, kCLOCK_Ctimer1, kCLOCK_Ctimer3 \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1 \ + } +/*! @brief Clock ip name array for ADC. */ +#define ADC_CLOCKS \ + { \ + kCLOCK_Adc0 \ + } +/*! @brief Clock ip name array for MRT. */ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ + } +/*! @brief Clock ip name array for MRT. */ +#define SCT_CLOCKS \ + { \ + kCLOCK_Sct0 \ + } +/*! @brief Clock ip name array for RTC. */ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc \ + } +/*! @brief Clock ip name array for WWDT. */ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt \ + } +/*! @brief Clock ip name array for CRC. */ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc \ + } +/*! @brief Clock ip name array for USBD. */ +#define USBD_CLOCKS \ + { \ + kCLOCK_Usbd0 \ + } + +/*! @brief Clock ip name array for GINT. GINT0 & GINT1 share same slot */ +#define GINT_CLOCKS \ + { \ + kCLOCK_Gint, kCLOCK_Gint \ + } + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +/*------------------------------------------------------------------------------ + clock_ip_name_t definition: +------------------------------------------------------------------------------*/ + +#define CLK_GATE_REG_OFFSET_SHIFT 8U +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU + +#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ + ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ + (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) + +#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) +#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) + +#define AHB_CLK_CTRL0 0 +#define AHB_CLK_CTRL1 1 +#define ASYNC_CLK_CTRL0 2 + +/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ +typedef enum _clock_ip_name +{ + kCLOCK_IpInvalid = 0U, + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot */ + kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), + kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), + kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), + kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), + kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), + kCLOCK_Ctimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), + kCLOCK_Ctimer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), + + kCLOCK_Ctimer3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13), +} clock_ip_name_t; + +/*! @brief Clock name used to get clock frequency. */ +typedef enum _clock_name +{ + kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ + kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ + kCLOCK_FroHf, /*!< FRO48/96 */ + kCLOCK_Fro12M, /*!< FRO12M */ + kCLOCK_ExtClk, /*!< External Clock */ + kCLOCK_PllOut, /*!< PLL Output */ + kCLOCK_UsbClk, /*!< USB input */ + kCLOCK_WdtOsc, /*!< Watchdog Oscillator */ + kCLOCK_Frg, /*!< Frg Clock */ + kCLOCK_AsyncApbClk, /*!< Async APB clock */ + kCLOCK_FlexI2S, /*!< FlexI2S clock */ + kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */ + kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */ + kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */ + kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */ + kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */ + kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */ + kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */ + kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */ +} clock_name_t; + +/** + * Clock source selections for the asynchronous APB clock + */ +typedef enum _async_clock_src +{ + kCLOCK_AsyncMainClk = 0, /*!< Main System clock */ + kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */ +} async_clock_src_t; + +/*! @brief Clock Mux Switches + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ + +#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) +#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU) +#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) + +#define CM_MAINCLKSELA 0 +#define CM_MAINCLKSELB 1 +#define CM_CLKOUTCLKSELA 2 +#define CM_CLKOUTCLKSELB 3 +#define CM_SYSPLLCLKSEL 4 +#define CM_USBPLLCLKSEL 5 +#define CM_AUDPLLCLKSEL 6 +#define CM_SCTPLLCLKSEL 7 +#define CM_ADCASYNCCLKSEL 9 +#define CM_USBCLKSEL 10 +#define CM_USB1CLKSEL 11 +#define CM_FXCOMCLKSEL0 12 +#define CM_FXCOMCLKSEL1 13 +#define CM_FXCOMCLKSEL2 14 +#define CM_FXCOMCLKSEL3 15 +#define CM_FXCOMCLKSEL4 16 +#define CM_FXCOMCLKSEL5 17 +#define CM_FXCOMCLKSEL6 18 +#define CM_FXCOMCLKSEL7 19 +#define CM_FXCOMCLKSEL8 20 +#define CM_FXCOMCLKSEL9 21 +#define CM_FXCOMCLKSEL10 22 +#define CM_FXCOMCLKSEL11 23 +#define CM_FXI2S0MCLKCLKSEL 24 +#define CM_FXI2S1MCLKCLKSEL 25 +#define CM_FRGCLKSEL 26 + +#define CM_ASYNCAPB 28 + +typedef enum _clock_attach_id +{ + + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), + kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), + kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), + + kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), + kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), + kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), + kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), + kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), + + kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), + kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), + + kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), + kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), + kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), + kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), + + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), + kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), + kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), + kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), + kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), + + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), + kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), + kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), + kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), + kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), + + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), + kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), + kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), + kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), + kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), + + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), + kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), + kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), + kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), + kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), + + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), + kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), + kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), + kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), + kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), + + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), + kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), + kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), + kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), + kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), + + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), + kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), + kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), + kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), + kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), + + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), + kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), + kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), + kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), + kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), + + kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), + kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), + kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), + kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), + kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), + + kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0), + kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1), + kMAIN_CLK_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 2), + kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7), + + kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0), + kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1), + kMAIN_CLK_to_USB_CLK = MUX_A(CM_USBCLKSEL, 2), + kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7), + + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), + kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), + kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), + kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), + kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), + kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), + kNONE_to_NONE = (int)0x80000000U, +} clock_attach_id_t; + +/* Clock dividers */ +typedef enum _clock_div_name +{ + kCLOCK_DivSystickClk = 0, + kCLOCK_DivTraceClk = 1, + kCLOCK_DivAhbClk = 32, + kCLOCK_DivClkOut = 33, + kCLOCK_DivAdcAsyncClk = 37, + kCLOCK_DivUsbClk = 38, + kCLOCK_DivFrg = 40, + kCLOCK_DivFxI2s0MClk = 43 +} clock_div_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +static inline void CLOCK_EnableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + if (index < 2) + { + SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + } + else + { + ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + } +} + +static inline void CLOCK_DisableClock(clock_ip_name_t clk) +{ + uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); + if (index < 2) + { + SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + } + else + { + ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + } +} +/** + * @brief FLASH Access time definitions + */ +typedef enum _clock_flashtim +{ + kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clock */ + kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */ + kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */ + kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */ + kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */ + kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */ +} clock_flashtim_t; + +/** + * @brief Set FLASH memory access time in clocks + * @param clks : Clock cycles for FLASH access + * @return Nothing + */ +static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks) +{ + uint32_t tmp; + + tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK); + + /* Don't alter lower bits */ + SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT); +} + +/** + * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) + * @return returns success or fail status. + */ +status_t CLOCK_SetupFROClocking(uint32_t iFreq); +/** + * @brief Configure the clock selection muxes. + * @param connection : Clock to be configured. + * @return Nothing + */ +void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); +/** + * @brief Setup peripheral clock dividers. + * @param div_name : Clock divider name + * @param divided_by_value: Value to be divided + * @param reset : Whether to reset the divider counter. + * @return Nothing + */ +void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); +/** + * @brief Set the flash wait states for the input freuqency. + * @param iFreq : Input frequency + * @return Nothing + */ +void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); +/*! @brief Return Frequency of selected clock + * @return Frequency of selected clock + */ +uint32_t CLOCK_GetFreq(clock_name_t clockName); + +/*! @brief Return Input frequency for the Fractional baud rate generator + * @return Input Frequency for FRG + */ +uint32_t CLOCK_GetFRGInputClock(void); + +/*! @brief Set output of the Fractional baud rate generator + * @param freq : Desired output frequency + * @return Error Code 0 - fail 1 - success + */ +uint32_t CLOCK_SetFRGClock(uint32_t freq); + +/*! @brief Return Frequency of FRO 12MHz + * @return Frequency of FRO 12MHz + */ +uint32_t CLOCK_GetFro12MFreq(void); +/*! @brief Return Frequency of External Clock + * @return Frequency of External Clock. If no external clock is used returns 0. + */ +uint32_t CLOCK_GetExtClkFreq(void); +/*! @brief Return Frequency of Watchdog Oscillator + * @return Frequency of Watchdog Oscillator + */ +uint32_t CLOCK_GetWdtOscFreq(void); +/*! @brief Return Frequency of High-Freq output of FRO + * @return Frequency of High-Freq output of FRO + */ +uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of PLL + * @return Frequency of PLL + */ +uint32_t CLOCK_GetPllOutFreq(void); +/*! @brief Return Frequency of 32kHz osc + * @return Frequency of 32kHz osc + */ +uint32_t CLOCK_GetOsc32KFreq(void); +/*! @brief Return Frequency of Core System + * @return Frequency of Core System + */ +uint32_t CLOCK_GetCoreSysClkFreq(void); +/*! @brief Return Frequency of I2S MCLK Clock + * @return Frequency of I2S MCLK Clock + */ +uint32_t CLOCK_GetI2SMClkFreq(void); +/*! @brief Return Frequency of Flexcomm functional Clock + * @return Frequency of Flexcomm functional Clock + */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc Clock. + */ +uint32_t CLOCK_GetAdcClkFreq(void); +/*! @brief Return Asynchronous APB Clock source + * @return Asynchronous APB CLock source + */ +__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void) +{ + return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3); +} +/*! @brief Return Frequency of Asynchronous APB Clock + * @return Frequency of Asynchronous APB Clock Clock + */ +uint32_t CLOCK_GetAsyncApbClkFreq(void); +/*! @brief Return System PLL input clock rate + * @return System PLL input clock rate + */ +uint32_t CLOCK_GetSystemPLLInClockRate(void); + +/*! @brief Return System PLL output clock rate + * @param recompute : Forces a PLL rate recomputation if true + * @return System PLL output clock rate + * @note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ +uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute); + +/*! @brief Enables and disables PLL bypass mode + * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass + * @return System PLL output clock rate + */ +__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass) +{ + if (bypass) + { + SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); + } + else + { + SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); + } +} + +/*! @brief Check if PLL is locked or not + * @return true if the PLL is locked, false if not locked + */ +__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void) +{ + return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0); +} + +/*! @brief Store the current PLL rate + * @param rate: Current rate of the PLL + * @return Nothing + **/ +void CLOCK_SetStoredPLLClockRate(uint32_t rate); + +/*! @brief PLL configuration structure flags for 'flags' field + * These flags control how the PLL configuration function sets up the PLL setup structure.
+ * + * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the + * configuration structure must be assigned with the expected PLL frequency. If the + * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration + * function and the driver will determine the PLL rate from the currently selected + * PLL source. This flag might be used to configure the PLL input clock more accurately + * when using the WDT oscillator or a more dyanmic CLKIN source.
+ * + * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the + * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider + * are not used.
+ */ +#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ +#define PLL_CONFIGFLAG_FORCENOFRACT \ + (1 \ + << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \ + \ \ \ \ + \ \ \ \ \ \ + \ \ \ \ \ \ \ \ + \ \ \ \ \ \ \ \ \ \ + \ \ \ \ \ \ \ \ \ \ \ \ + hardware */ + +/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency + * See (MF) field in the SYSPLLSSCTRL1 register in the UM. + */ +typedef enum _ss_progmodfm +{ + kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ + kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ + kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ + kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ + kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ + kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ + kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ +} ss_progmodfm_t; + +/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth + * See (MR) field in the SYSPLLSSCTRL1 register in the UM. + */ +typedef enum _ss_progmoddp +{ + kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1 << 23), /*!< k = 1 */ + kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ + kSS_MR_K2 = (3 << 23), /*!< k = 2 */ + kSS_MR_K3 = (4 << 23), /*!< k = 3 */ + kSS_MR_K4 = (5 << 23), /*!< k = 4 */ + kSS_MR_K6 = (6 << 23), /*!< k = 6 */ + kSS_MR_K8 = (7 << 23) /*!< k = 8 */ +} ss_progmoddp_t; + +/*! @brief PLL Spread Spectrum (SS) Modulation waveform control + * See (MC) field in the SYSPLLSSCTRL1 register in the UM.
+ * Compensation for low pass filtering of the PLL to get a triangular + * modulation at the output of the PLL, giving a flat frequency spectrum. + */ +typedef enum _ss_modwvctrl +{ + kSS_MC_NOC = (0 << 26), /*!< no compensation */ + kSS_MC_RECC = (2 << 26), /*!< recommended setting */ + kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ +} ss_modwvctrl_t; + +/*! @brief PLL configuration structure + * + * This structure can be used to configure the settings for a PLL + * setup structure. Fill in the desired configuration for the PLL + * and call the PLL setup function to fill in a PLL setup structure. + */ +typedef struct _pll_config +{ + uint32_t desiredRate; /*!< Desired PLL rate in Hz */ + uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ + uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ + ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + ss_modwvctrl_t + ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ + bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using + PLL_CONFIGFLAG_FORCENOFRACT flag */ + +} pll_config_t; + +/*! @brief PLL setup structure flags for 'flags' field + * These flags control how the PLL setup function sets up the PLL + */ +#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ +#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */ + +/*! @brief PLL setup structure + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ +typedef struct _pll_setup +{ + uint32_t syspllctrl; /*!< PLL control register SYSPLLCTRL */ + uint32_t syspllndec; /*!< PLL NDEC register SYSPLLNDEC */ + uint32_t syspllpdec; /*!< PLL PDEC register SYSPLLPDEC */ + uint32_t syspllssctrl[2]; /*!< PLL SSCTL registers SYSPLLSSCTRL */ + uint32_t pllRate; /*!< Acutal PLL rate */ + uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ +} pll_setup_t; + +/*! @brief PLL status definitions + */ +typedef enum _pll_error +{ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */ +} pll_error_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */ + kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */ + kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ + kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL( + 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */ +} clock_usb_src_t; + +/*! @brief Return System PLL output clock rate from setup structure + * @param pSetup : Pointer to a PLL setup structure + * @return System PLL output clock rate calculated from the setup structure + */ +uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup); + +/*! @brief Set PLL output based on the passed PLL setup data + * @param pControl : Pointer to populated PLL control structure to generate setup with + * @param pSetup : Pointer to PLL setup structure to be filled + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ +pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup); + +/*! @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @param flagcfg : Flag configuration for PLL config structure + * @return PLL_ERROR_SUCCESS on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); + +/** + * @brief Set PLL output from PLL setup structure (precise frequency) + * @param pSetup : Pointer to populated PLL setup structure + * @return kStatus_PLL_Success on success, or PLL setup error code + * @note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ +pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup); + +/*! @brief Set PLL output based on the multiplier and input frequency + * @param multiply_by : multiplier + * @param input_freq : Clock input frequency of the PLL + * @return Nothing + * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ +void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq); + +/*! @brief Disable USB FS clock. + * + * Disable USB FS clock. + */ +static inline void CLOCK_DisableUsbfs0Clock(void) +{ + CLOCK_DisableClock(kCLOCK_Usbd0); +} +bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! + * @brief Use DWT to delay at least for some time. + * Please note that, this API will calculate the microsecond period with the maximum devices + * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise + * delay count was needed, please implement a new timer count to achieve this function. + * + * @param delay_us Delay time in unit of microsecond. + */ +void SDK_DelayAtLeastUs(uint32_t delay_us); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_common.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_common.c new file mode 100644 index 000000000..9ecb8385d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_common.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#define SDK_MEM_MAGIC_NUMBER 12345U + +typedef struct _mem_align_control_block +{ + uint16_t identifier; /*!< Identifier for the memory control block. */ + uint16_t offset; /*!< offset from aligned address to real address */ +} mem_align_cb_t; + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1u << intNumber; + EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1u << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +void *SDK_Malloc(size_t size, size_t alignbytes) +{ + mem_align_cb_t *p_cb = NULL; + uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); + void *p_align_addr, *p_addr = malloc(alignedsize); + + if (!p_addr) + { + return NULL; + } + + p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U); + p_cb->identifier = SDK_MEM_MAGIC_NUMBER; + p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; + + return (void *)p_align_addr; +} + +void SDK_Free(void *ptr) +{ + mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U); + + if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) + { + return; + } + + free((void *)((uint32_t)ptr - p_cb->offset)); +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_common.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_common.h new file mode 100644 index 000000000..a29c9e78c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_common.h @@ -0,0 +1,597 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_H_ +#define _FSL_COMMON_H_ + +#include +#include +#include +#include +#include + +#if defined(__ICCARM__) +#include +#endif + +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Construct a status code value from a group and code number. */ +#define MAKE_STATUS(group, code) ((((group)*100) + (code))) + +/*! @brief Construct the version number for drivers. */ +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @name Driver version */ +/*@{*/ +/*! @brief common driver version 2.0.1. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/* Debug console type definition. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ + +/*! @brief Status group numbers. */ +enum _status_groups +{ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ +}; + +/*! @brief Generic status return codes. */ +enum _generic_status +{ + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), + kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), +}; + +/*! @brief Type used for all status and error return values. */ +typedef int32_t status_t; + +/* + * Macro guard for whether to use default weak IRQ implementation in drivers + */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + +/*! @name Min/max macros */ +/* @{ */ +#if !defined(MIN) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#if !defined(MAX) +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif +/* @} */ + +/*! @brief Computes the number of elements in an array. */ +#if !defined(ARRAY_SIZE) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/*! @name UINT16_MAX/UINT32_MAX value */ +/* @{ */ +#if !defined(UINT16_MAX) +#define UINT16_MAX ((uint16_t)-1) +#endif + +#if !defined(UINT32_MAX) +#define UINT32_MAX ((uint32_t)-1) +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/** + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http://supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var +#endif +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var +#endif +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) +#endif +#else +#error Toolchain not supported +#define SDK_ALIGN(var, alignbytes) var +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) var +#endif +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) var +#endif +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, + * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables + * will be initialized to zero in system startup. + */ +/* @{ */ +#if (defined(__ICCARM__)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#endif +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var +#endif +#elif(defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) +#endif +#else +#error Toolchain not supported. +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#endif +/* @} */ + +/*! @name Time sensitive region */ +/* @{ */ +#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func +#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +#else +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#elif(defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func +#define AT_QUICKACCESS_SECTION_DATA(func) func +#else +#error Toolchain not supported. +#endif +#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ +/* @} */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif(defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif + + /*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ + static inline status_t EnableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ + static inline status_t DisableIRQ(IRQn_Type interrupt) + { + if (NotAvail_IRQn == interrupt) + { + return kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + return kStatus_Fail; + } +#endif + +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + return kStatus_Success; + } + + /*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ + static inline uint32_t DisableGlobalIRQ(void) + { +#if defined (__XCC__) + return 0; +#else +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +#endif + } + + /*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ + static inline void EnableGlobalIRQ(uint32_t primask) + { +#if defined (__XCC__) +#else +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +#endif + } + +#if defined(ENABLE_RAM_VECTOR_TABLE) + /*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ + uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + /*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void EnableDeepSleepIRQ(IRQn_Type interrupt); + + /*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ + void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + + /*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ + void *SDK_Malloc(size_t size, size_t alignbytes); + + /*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ + void SDK_Free(void *ptr); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_COMMON_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_ctimer.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_ctimer.c new file mode 100644 index 000000000..96e997253 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_ctimer.c @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_ctimer.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.ctimer" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Gets the instance from the base address + * + * @param base Ctimer peripheral base address + * + * @return The Timer instance + */ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief Pointers to Timer bases for each instance. */ +static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Pointers to Timer clocks for each instance. */ +static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET +/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; +#else +/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ +static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; +#endif +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/*! @brief Pointers real ISRs installed by drivers for each instance. */ +static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0}; + +/*! @brief Callback type installed by drivers for each instance. */ +static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback}; + +/*! @brief Array to map timer instance to IRQ number. */ +static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; + +/******************************************************************************* + * Code + ******************************************************************************/ +static uint32_t CTIMER_GetInstance(CTIMER_Type *base) +{ + uint32_t instance; + uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ctimerArrayCount; instance++) + { + if (s_ctimerBases[instance] == base) + { + break; + } + } + + assert(instance < ctimerArrayCount); + + return instance; +} + +/*! + * brief Ungates the clock and configures the peripheral for basic operation. + * + * note This API should be called at the beginning of the application before using the driver. + * + * param base Ctimer peripheral base address + * param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) +{ + assert(config); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the timer clock*/ + CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +/* Reset the module. */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) + RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); +#endif +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +/* Setup the cimer mode and count select */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); +#endif + /* Setup the timer prescale value */ + base->PR = CTIMER_PR_PRVAL(config->prescale); +} + +/*! + * brief Gates the timer clock. + * + * param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base) +{ + uint32_t index = CTIMER_GetInstance(base); + /* Stop the timer */ + base->TCR &= ~CTIMER_TCR_CEN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the timer clock*/ + CLOCK_DisableClock(s_ctimerClocks[index]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + /* Disable IRQ at NVIC Level */ + DisableIRQ(s_ctimerIRQ[index]); +} + +/*! + * brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * endcode + * param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + /* Run as a timer */ + config->mode = kCTIMER_TimerMode; + /* This field is ignored when mode is timer */ + config->input = kCTIMER_Capture_0; + /* Timer counter is incremented on every APB bus clock */ + config->prescale = 0; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * param pwmFreq_Hz PWM signal frequency in Hz + * param srcClock_Hz Timer counter clock in Hz + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt) +{ + assert(pwmFreq_Hz > 0); + + uint32_t reg; + uint32_t period, pulsePeriod = 0; + uint32_t timerClock = srcClock_Hz / (base->PR + 1); + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == kCTIMER_Match_3) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the channel */ + base->PWMC |= (1U << matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + } + + /* Reset the counter when match on channel 3 */ + reg |= CTIMER_MCR_MR3R_MASK; + + base->MCR = reg; + + /* Calculate PWM period match value */ + period = (timerClock / pwmFreq_Hz) - 1; + + /* Calculate pulse width match value */ + if (dutyCyclePercent == 0) + { + pulsePeriod = period + 1; + } + else + { + pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; + } + + /* Match on channel 3 will define the PWM period */ + base->MR[kCTIMER_Match_3] = period; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param pwmPeriod PWM period match value + * param pulsePeriod Pulse width match value + * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod( + CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); +#endif + + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + if (matchChannel == kCTIMER_Match_3) + { + return kStatus_Fail; + } + + /* Enable PWM mode on the channel */ + base->PWMC |= (1U << matchChannel); + + /* Clear the stop, reset and interrupt bits for this channel */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + + /* If call back function is valid then enable match interrupt for the channel */ + if (enableInt) + { + reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + } + + /* Reset the counter when match on channel 3 */ + reg |= CTIMER_MCR_MR3R_MASK; + + base->MCR = reg; + + /* Match on channel 3 will define the PWM period */ + base->MR[kCTIMER_Match_3] = pwmPeriod; + + /* This will define the PWM pulse period */ + base->MR[matchChannel] = pulsePeriod; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If call back function is valid then enable interrupt and update the call back function */ + if (enableInt) + { + EnableIRQ(s_ctimerIRQ[index]); + } + + return kStatus_Success; +} + +/*! + * brief Updates the duty cycle of an active PWM signal. + * + * note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. + * + * param base Ctimer peripheral base address + * param matchChannel Match pin to be used to output the PWM signal + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent) +{ + uint32_t pulsePeriod = 0, period; + + /* Match channel 3 defines the PWM period */ + period = base->MR[kCTIMER_Match_3]; + + /* Calculate pulse width match value */ + pulsePeriod = (period * dutyCyclePercent) / 100; + + /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ + if (dutyCyclePercent == 0) + { + pulsePeriod = period + 1; + } + else + { + pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; + } + + /* Update dutycycle */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * param base Ctimer peripheral base address + * param matchChannel Match register to configure + * param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) +{ +/* Some CTimers only have 16bits , so the value is limited*/ +#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B + assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); +#endif + uint32_t reg; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the counter operation when a match on this channel occurs */ + reg = base->MCR; + reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3))); + reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3))); + reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + base->MCR = reg; + + reg = base->EMR; + /* Set the match output operation when a match on this channel occurs */ + reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2)); + reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2)); + + /* Set the initial state of the EM bit/output */ + reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel); + reg |= (uint32_t)config->outPinInitState << matchChannel; + base->EMR = reg; + + /* Set the match value */ + base->MR[matchChannel] = config->matchValue; + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + /* If interrupt is enabled then enable interrupt and update the call back function */ + if (config->enableInterrupt) + { + EnableIRQ(s_ctimerIRQ[index]); + } +} + +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) +/*! + * brief Setup the capture. + * + * param base Ctimer peripheral base address + * param capture Capture channel to configure + * param edge Edge on the channel that will trigger a capture + * param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt) +{ + uint32_t reg = base->CCR; + uint32_t index = CTIMER_GetInstance(base); + + /* Set the capture edge */ + reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3)); + reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3)); + /* Clear status flags */ + CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture)); + /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ + if (enableInt) + { + reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3); + EnableIRQ(s_ctimerIRQ[index]); + } + base->CCR = reg; +} +#endif + +/*! + * brief Register callback. + * + * param base Ctimer peripheral base address + * param cb_func callback function + * param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) +{ + uint32_t index = CTIMER_GetInstance(base); + s_ctimerCallback[index] = cb_func; + ctimerCallbackType[index] = cb_type; +} + +void CTIMER_GenericIRQHandler(uint32_t index) +{ + uint32_t int_stat, i, mask; + /* Get Interrupt status flags */ + int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); + /* Clear the status flags that were set */ + CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); + if (ctimerCallbackType[index] == kCTIMER_SingleCallback) + { + if (s_ctimerCallback[index][0]) + { + s_ctimerCallback[index][0](int_stat); + } + } + else + { +#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE + for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) +#else +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif + { + mask = 0x01 << i; + /* For each status flag bit that was set call the callback function if it is valid */ + if ((int_stat & mask) && (s_ctimerCallback[index][i])) + { + s_ctimerCallback[index][i](int_stat); + } + } + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(0); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(1); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(2); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(3); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void) +{ + CTIMER_GenericIRQHandler(4); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_ctimer.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_ctimer.h new file mode 100644 index 000000000..7ad216855 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_ctimer.h @@ -0,0 +1,488 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_CTIMER_H_ +#define _FSL_CTIMER_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup ctimer + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ +/*@}*/ + +/*! @brief List of Timer capture channels */ +typedef enum _ctimer_capture_channel +{ + kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ + kCTIMER_Capture_1, /*!< Timer capture channel 1 */ + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture_3 /*!< Timer capture channel 3 */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +} ctimer_capture_channel_t; + +/*! @brief List of capture edge options */ +typedef enum _ctimer_capture_edge +{ + kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ + kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ + kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ +} ctimer_capture_edge_t; + +/*! @brief List of Timer match registers */ +typedef enum _ctimer_match +{ + kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ + kCTIMER_Match_1, /*!< Timer match register 1 */ + kCTIMER_Match_2, /*!< Timer match register 2 */ + kCTIMER_Match_3 /*!< Timer match register 3 */ +} ctimer_match_t; + +/*! @brief List of output control options */ +typedef enum _ctimer_match_output_control +{ + kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ + kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ + kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ + kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ +} ctimer_match_output_control_t; + +/*! @brief List of Timer modes */ +typedef enum _ctimer_timer_mode +{ + kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ + kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ + kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ + kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ +} ctimer_timer_mode_t; + +/*! @brief List of Timer interrupts */ +typedef enum _ctimer_interrupt_enable +{ + kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ + kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ + kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ + kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ + kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ + kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ +#endif +} ctimer_interrupt_enable_t; + +/*! @brief List of Timer flags */ +typedef enum _ctimer_status_flags +{ + kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ + kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ + kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ + kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ + kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ + kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT + kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif +} ctimer_status_flags_t; + +typedef void (*ctimer_callback_t)(uint32_t flags); + +/*! @brief Callback type when registering for a callback. When registering a callback + * an array of function pointers is passed the size could be 1 or 8, the callback + * type will tell that. + */ +typedef enum +{ + kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. + based on the status flags different channels needs to be handled differently */ + kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. + for both match/capture */ +} ctimer_callback_type_t; + +/*! + * @brief Match configuration + * + * This structure holds the configuration settings for each match register. + */ +typedef struct _ctimer_match_config +{ + uint32_t matchValue; /*!< This is stored in the match register */ + bool enableCounterReset; /*!< true: Match will reset the counter + false: Match will not reser the counter */ + bool enableCounterStop; /*!< true: Match will stop the counter + false: Match will not stop the counter */ + ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ + bool outPinInitState; /*!< Initial value of the EM bit/output */ + bool enableInterrupt; /*!< true: Generate interrupt upon match + false: Do not generate interrupt on match */ + +} ctimer_match_config_t; + +/*! + * @brief Timer configuration structure + * + * This structure holds the configuration settings for the Timer peripheral. To initialize this + * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a + * pointer to the configuration structure instance. + * + * The configuration structure can be made constant so as to reside in flash. + */ +typedef struct _ctimer_config +{ + ctimer_timer_mode_t mode; /*!< Timer mode */ + ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer + modes that rely on this input signal to increment TC */ + uint32_t prescale; /*!< Prescale value */ +} ctimer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Ungates the clock and configures the peripheral for basic operation. + * + * @note This API should be called at the beginning of the application before using the driver. + * + * @param base Ctimer peripheral base address + * @param config Pointer to the user configuration structure. + */ +void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); + +/*! + * @brief Gates the timer clock. + * + * @param base Ctimer peripheral base address + */ +void CTIMER_Deinit(CTIMER_Type *base); + +/*! + * @brief Fills in the timers configuration structure with the default settings. + * + * The default values are: + * @code + * config->mode = kCTIMER_TimerMode; + * config->input = kCTIMER_Capture_0; + * config->prescale = 0; + * @endcode + * @param config Pointer to the user configuration structure. + */ +void CTIMER_GetDefaultConfig(ctimer_config_t *config); + +/*! @}*/ + +/*! + * @name PWM setup operations + * @{ + */ + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * period + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pwmPeriod PWM period match value + * @param pulsePeriod Pulse width match value + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * @return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period + */ +status_t CTIMER_SetupPwmPeriod( + CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt); + +/*! + * @brief Configures the PWM signal parameters. + * + * Enables PWM mode on the match channel passed in and will then setup the match value + * and other match parameters to generate a PWM signal. + * This function will assign match channel 3 to set the PWM cycle. + * + * @note When setting PWM output from multiple output pins, all should use the same PWM + * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 + * @param pwmFreq_Hz PWM signal frequency in Hz + * @param srcClock_Hz Timer counter clock in Hz + * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, + * if it is 0 then no interrupt is generated + * + * @return kStatus_Success on success + * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle + */ +status_t CTIMER_SetupPwm(CTIMER_Type *base, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent, + uint32_t pwmFreq_Hz, + uint32_t srcClock_Hz, + bool enableInt); + +/*! + * @brief Updates the pulse period of an active PWM signal. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param pulsePeriod New PWM pulse width match value + */ +static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) +{ + /* Update PWM pulse period match value */ + base->MR[matchChannel] = pulsePeriod; +} + +/*! + * @brief Updates the duty cycle of an active PWM signal. + * + * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match pin to be used to output the PWM signal + * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 + */ +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent); + +/*! @}*/ + +/*! + * @brief Setup the match register. + * + * User configuration is used to setup the match value and action to be taken when a match occurs. + * + * @param base Ctimer peripheral base address + * @param matchChannel Match register to configure + * @param config Pointer to the match configuration structure + */ +void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); + +/*! + * @brief Setup the capture. + * + * @param base Ctimer peripheral base address + * @param capture Capture channel to configure + * @param edge Edge on the channel that will trigger a capture + * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back + * is called upon capture + */ +void CTIMER_SetupCapture(CTIMER_Type *base, + ctimer_capture_channel_t capture, + ctimer_capture_edge_t edge, + bool enableInt); + +/*! + * @brief Get the timer count value from TC register. + * + * @param base Ctimer peripheral base address. + * @return return the timer count value. + */ +static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) +{ + return (base->TC); +} + +/*! + * @brief Register callback. + * + * @param base Ctimer peripheral base address + * @param cb_func callback function + * @param cb_type callback function type, singular or multiple + */ +void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); + +/*! + * @name Interrupt Interface + * @{ + */ + +/*! + * @brief Enables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Enable match interrupts */ + base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Enable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif +} + +/*! + * @brief Disables the selected Timer interrupts. + * + * @param base Ctimer peripheral base address + * @param mask The interrupts to enable. This is a logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) +{ + /* Disable match interrupts */ + base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); + +/* Disable capture interrupts */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + )); +#endif +} + +/*! + * @brief Gets the enabled Timer interrupts. + * + * @param base Ctimer peripheral base address + * + * @return The enabled interrupts. This is the logical OR of members of the + * enumeration ::ctimer_interrupt_enable_t + */ +static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) +{ + uint32_t enabledIntrs = 0; + + /* Get all the match interrupts enabled */ + enabledIntrs = + base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); + +/* Get all the capture interrupts enabled */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK +#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 + | CTIMER_CCR_CAP3I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ + ); +#endif + + return enabledIntrs; +} + +/*! @}*/ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Gets the Timer status flags. + * + * @param base Ctimer peripheral base address + * + * @return The status flags. This is the logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) +{ + return base->IR; +} + +/*! + * @brief Clears the Timer status flags. + * + * @param base Ctimer peripheral base address + * @param mask The status flags to clear. This is a logical OR of members of the + * enumeration ::ctimer_status_flags_t + */ +static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) +{ + base->IR = mask; +} + +/*! @}*/ + +/*! + * @name Counter Start and Stop + * @{ + */ + +/*! + * @brief Starts the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StartTimer(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CEN_MASK; +} + +/*! + * @brief Stops the Timer counter. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_StopTimer(CTIMER_Type *base) +{ + base->TCR &= ~CTIMER_TCR_CEN_MASK; +} + +/*! @}*/ + +/*! + * @brief Reset the counter. + * + * The timer counter and prescale counter are reset on the next positive edge of the APB clock. + * + * @param base Ctimer peripheral base address + */ +static inline void CTIMER_Reset(CTIMER_Type *base) +{ + base->TCR |= CTIMER_TCR_CRST_MASK; + base->TCR &= ~CTIMER_TCR_CRST_MASK; +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CTIMER_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_flexcomm.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_flexcomm.c new file mode 100644 index 000000000..8c3754493 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_flexcomm.c @@ -0,0 +1,400 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_flexcomm.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! @brief Set the FLEXCOMM mode . */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); + +/*! @brief check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ +static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; + +/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ +static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; + +/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ +IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; + +/*! @brief Array to map FLEXCOMM instance number to base address. */ +static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief IDs of clock for each FLEXCOMM module */ +static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) +/*! @brief Pointers to FLEXCOMM resets for each instance. */ +static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* check whether flexcomm supports peripheral type */ +static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) +{ + if (periph == FLEXCOMM_PERIPH_NONE) + { + return true; + } + else if (periph <= FLEXCOMM_PERIPH_I2S_TX) + { + return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false; + } + else if (periph == FLEXCOMM_PERIPH_I2S_RX) + { + return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false; + } + else + { + return false; + } +} + +/* Get the index corresponding to the FLEXCOMM */ +/*! brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base) +{ + int i; + + for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) + { + if ((uint32_t)base == s_flexcommBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0; +} + +/* Changes FLEXCOMM mode */ +static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) +{ + /* Check whether peripheral type is present */ + if (!FLEXCOMM_PeripheralIsPresent(base, periph)) + { + return kStatus_OutOfRange; + } + + /* Flexcomm is locked to different peripheral type than expected */ + if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph)) + { + return kStatus_Fail; + } + + /* Check if we are asked to lock */ + if (lock) + { + base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; + } + else + { + base->PSELID = (uint32_t)periph; + } + + return kStatus_Success; +} + +/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) +{ + int idx = FLEXCOMM_GetInstance(base); + + if (idx < 0) + { + return kStatus_InvalidArgument; + } + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the peripheral clock */ + CLOCK_EnableClock(s_flexcommClocks[idx]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) + /* Reset the FLEXCOMM module */ + RESET_PeripheralReset(s_flexcommResets[idx]); +#endif + + /* Set the FLEXCOMM to given peripheral */ + return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); +} + +/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(base); + + /* Clear handler first to avoid execution of the handler with wrong handle */ + s_flexcommIrqHandler[instance] = NULL; + s_flexcommHandle[instance] = handle; + s_flexcommIrqHandler[instance] = handler; +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +/* IRQ handler functions overloading weak symbols in the startup */ +#if defined(FLEXCOMM0) +void FLEXCOMM0_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[0]); + s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM1) +void FLEXCOMM1_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[1]); + s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM2) +void FLEXCOMM2_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[2]); + s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM3) +void FLEXCOMM3_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[3]); + s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM4) +void FLEXCOMM4_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[4]); + s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#endif + +#if defined(FLEXCOMM5) +void FLEXCOMM5_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[5]); + s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM6) +void FLEXCOMM6_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[6]); + s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM7) +void FLEXCOMM7_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[7]); + s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM8) +void FLEXCOMM8_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[8]); + s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM9) +void FLEXCOMM9_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[9]); + s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM10) +void FLEXCOMM10_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[10]); + s_flexcommIrqHandler[10]((void *)s_flexcommBaseAddrs[10], s_flexcommHandle[10]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM11) +void FLEXCOMM11_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[11]); + s_flexcommIrqHandler[11]((void *)s_flexcommBaseAddrs[11], s_flexcommHandle[11]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM12) +void FLEXCOMM12_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[12]); + s_flexcommIrqHandler[12]((void *)s_flexcommBaseAddrs[12], s_flexcommHandle[12]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM13) +void FLEXCOMM13_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[13]); + s_flexcommIrqHandler[13]((void *)s_flexcommBaseAddrs[13], s_flexcommHandle[13]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM14) +void FLEXCOMM14_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM14); + assert(s_flexcommIrqHandler[instance]); + s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM15) +void FLEXCOMM15_DriverIRQHandler(void) +{ + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM14); + assert(s_flexcommIrqHandler[instance]); + s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if defined(FLEXCOMM16) +void FLEXCOMM16_DriverIRQHandler(void) +{ + assert(s_flexcommIrqHandler[16]); + s_flexcommIrqHandler[16]((void *)s_flexcommBaseAddrs[16], s_flexcommHandle[16]); +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_flexcomm.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_flexcomm.h new file mode 100644 index 000000000..7018e8c32 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_flexcomm.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXCOMM_H_ +#define _FSL_FLEXCOMM_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcomm_driver + * @{ + */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCOMM driver version 2.0.1. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! @brief FLEXCOMM peripheral modes. */ +typedef enum +{ + FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ + FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ + FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ + FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ + FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ + FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ +} FLEXCOMM_PERIPH_T; + +/*! @brief Typedef for interrupt handler. */ +typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); + +/*! @brief Array with IRQ number for each FLEXCOMM module. */ +extern IRQn_Type const kFlexcommIrqs[]; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @brief Returns instance number for FLEXCOMM module with given base address. */ +uint32_t FLEXCOMM_GetInstance(void *base); + +/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ +status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); + +/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM + * mode */ +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle); + +#if defined(__cplusplus) +} +#endif + +/*@}*/ + +#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_gpio.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_gpio.c new file mode 100644 index 000000000..dca3c291b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_gpio.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpio.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! @brief Array to map FGPIO instance number to clock name. */ +static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) +/*! @brief Pointers to GPIO resets for each instance. */ +static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; +#endif +/******************************************************************************* + * Prototypes + ************ ******************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * param base GPIO peripheral base pointer. + * param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) + /* Reset the GPIO module */ + RESET_PeripheralReset(s_gpioResets[port]); +#endif +} + +/*! + * brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * endcode + * + * param base GPIO peripheral base pointer(Typically GPIO) + * param port GPIO port number + * param pin GPIO pin number + * param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) +{ + if (config->pinDirection == kGPIO_DigitalInput) + { +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRCLR[port] = 1U << pin; +#else + base->DIR[port] &= ~(1U << pin); +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } + else + { + /* Set default output value */ + if (config->outputLogic == 0U) + { + base->CLR[port] = (1U << pin); + } + else + { + base->SET[port] = (1U << pin); + } +/* Set pin direction */ +#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) + base->DIRSET[port] = 1U << pin; +#else + base->DIR[port] |= 1U << pin; +#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ + } +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Configures the gpio pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) +{ + base->INTEDG[port] = base->INTEDG[port] | (config->mode << pin); + + base->INTPOL[port] = base->INTPOL[port] | (config->polarity << pin); +} + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if (kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | mask; + } + else if (kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if (kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~mask; + } + else if (kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears multiple pins interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) +{ + if (kGPIO_InterruptA == index) + { + base->INTSTATA[port] = mask; + } + else if (kGPIO_InterruptB == index) + { + base->INTSTATB[port] = mask; + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) +{ + uint32_t status = 0U; + + if (kGPIO_InterruptA == index) + { + status = base->INTSTATA[port]; + } + else if (kGPIO_InterruptB == index) + { + status = base->INTSTATB[port]; + } + else + { + /*Should not enter here*/ + } + return status; + +} + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if (kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] | (1U << pin); + } + else if (kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] | (1U << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if (kGPIO_InterruptA == index) + { + base->INTENA[port] = base->INTENA[port] & ~(1U << pin); + } + else if (kGPIO_InterruptB == index) + { + base->INTENB[port] = base->INTENB[port] & ~(1U << pin); + } + else + { + /*Should not enter here*/ + } +} + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) +{ + if (kGPIO_InterruptA == index) + { + base->INTSTATA[port] = 1U << pin; + } + else if (kGPIO_InterruptB == index) + { + base->INTSTATB[port] = 1U << pin; + } + else + { + /*Should not enter here*/ + } +} +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_gpio.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_gpio.h new file mode 100644 index 000000000..c2935292a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_gpio.h @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _LPC_GPIO_H_ +#define _LPC_GPIO_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_gpio + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief LPC GPIO driver version 2.1.3. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*@}*/ + +/*! @brief LPC GPIO direction definition */ +typedef enum _gpio_pin_direction +{ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/*! + * @brief The GPIO pin configuration structure. + * + * Every pin can only be configured as either output pin or input pin at a time. + * If configured as a input pin, then leave the outputConfig unused. + */ +typedef struct _gpio_pin_config +{ + gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ + /* Output configurations, please ignore if configured as a input one */ + uint8_t outputLogic; /*!< Set default output logic, no use in input */ +} gpio_pin_config_t; + +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) +#define GPIO_PIN_INT_LEVEL 0x00U +#define GPIO_PIN_INT_EDGE 0x01U + +#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U +#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U + +/*! @brief GPIO Pin Interrupt enable mode */ +typedef enum _gpio_pin_enable_mode +{ + kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ + kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ +} gpio_pin_enable_mode_t; + +/*! @brief GPIO Pin Interrupt enable polarity */ +typedef enum _gpio_pin_enable_polarity +{ + kGPIO_PinIntEnableHighOrRise = + PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ + kGPIO_PinIntEnableLowOrFall = + PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ +} gpio_pin_enable_polarity_t; + +/*! @brief LPC GPIO interrupt index definition */ +typedef enum _gpio_interrupt_index +{ + kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ + kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ +} gpio_interrupt_index_t; + +/*! @brief Configures the interrupt generation condition. */ +typedef struct _gpio_interrupt_config +{ + uint8_t mode; /* The trigger mode of GPIO interrupts */ + uint8_t polarity; /* The polarity of GPIO interrupts */ +} gpio_interrupt_config_t; +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" +{ +#endif + +/*! @name GPIO Configuration */ +/*@{*/ + +/*! + * @brief Initializes the GPIO peripheral. + * + * This function ungates the GPIO clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +void GPIO_PortInit(GPIO_Type *base, uint32_t port); + +/*! + * @brief Initializes a GPIO pin used by the board. + * + * To initialize the GPIO, define a pin configuration, either input or output, in the user file. + * Then, call the GPIO_PinInit() function. + * + * This is an example to define an input pin or output pin configuration: + * @code + * // Define a digital input pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalInput, + * 0, + * } + * //Define a digital output pin configuration, + * gpio_pin_config_t config = + * { + * kGPIO_DigitalOutput, + * 0, + * } + * @endcode + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param config GPIO pin configuration pointer + */ +void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); + +/*@}*/ + +/*! @name GPIO Output Operations */ +/*@{*/ + +/*! + * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @param output GPIO pin output logic level. + * - 0: corresponding pin output low-logic level. + * - 1: corresponding pin output high-logic level. + */ +static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) +{ + base->B[port][pin] = output; +} + +/*@}*/ +/*! @name GPIO Input Operations */ +/*@{*/ + +/*! + * @brief Reads the current input value of the GPIO PIN. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param pin GPIO pin number + * @retval GPIO port input value + * - 0: corresponding pin input low-logic level. + * - 1: corresponding pin input high-logic level. + */ +static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) +{ + return (uint32_t)base->B[port][pin]; +} + +/*@}*/ + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 1. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->SET[port] = mask; +} + +/*! + * @brief Sets the output level of the multiple GPIO pins to the logic 0. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->CLR[port] = mask; +} + +/*! + * @brief Reverses current output logic of the multiple GPIO pins. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->NOT[port] = mask; +} + +/*@}*/ + +/*! + * @brief Reads the current input value of the whole GPIO port. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + */ +static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->PIN[port]; +} + +/*@}*/ +/*! @name GPIO Mask Operations */ +/*@{*/ + +/*! + * @brief Sets port mask, 0 - enable pin, 1 - disable pin. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param mask GPIO pin number macro + */ +static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) +{ + base->MASK[port] = mask; +} + +/*! + * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @param output GPIO port output value. + */ +static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) +{ + base->MPIN[port] = output; +} + +/*! + * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be + * affected. + * + * @param base GPIO peripheral base pointer(Typically GPIO) + * @param port GPIO port number + * @retval masked GPIO port value + */ +static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) +{ + return (uint32_t)base->MPIN[port]; +} + +#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT +/*! + * @brief Configures the gpio pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param pin GPIO pin number. + * @param config GPIO pin interrupt configuration.. + */ +void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); + +/*! + * @brief Enables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Disables multiple pins interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @brief Clears pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param index GPIO interrupt number. + * @param mask GPIO pin number macro. + */ +void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); + +/*! + * @ Read port interrupt status. + * + * @param base GPIO base pointer. + * @param port GPIO port number + * @param index GPIO interrupt number. + * @retval masked GPIO status value + */ +uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); + +/*! + * @brief Enables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Disables the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +/*! + * @brief Clears the specific pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param port GPIO port number. + * @param pin GPIO pin number. + * @param index GPIO interrupt number. + */ +void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); + +#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* _LPC_GPIO_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_iocon.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_iocon.h new file mode 100644 index 000000000..ec9709371 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_iocon.h @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IOCON_H_ +#define _FSL_IOCON_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup lpc_iocon + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOCON driver version 2.1.1. */ +#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +/** + * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format + */ +typedef struct _iocon_group +{ + uint32_t port : 8; /* Pin port */ + uint32_t pin : 8; /* Pin number */ + uint32_t ionumber : 8; /* IO number */ + uint32_t modefunc : 16; /* Function and mode */ +} iocon_group_t; + +/** + * @brief IOCON function and mode selection definitions + * @note See the User Manual for specific modes and functions supported by the various pins. + */ +#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ +#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ +#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ +#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ +#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ +#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#if defined(IOCON_PIO_MODE_SHIFT) +#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ +#endif + +#if defined(IOCON_PIO_I2CSLEW_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_EGP_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_SLEW_SHIFT) +#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_INVERT_SHIFT) +#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ +#endif + +#if defined(IOCON_PIO_DIGIMODE_SHIFT) +#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN \ + (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ +#endif + +#if defined(IOCON_PIO_FILTEROFF_SHIFT) +#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ +#endif + +#if defined(IOCON_PIO_I2CDRIVE_SHIFT) +#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ +#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ +#endif + +#if defined(IOCON_PIO_OD_SHIFT) +#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ +#endif + +#if defined(IOCON_PIO_I2CFILTER_SHIFT) +#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ +#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ +#endif + +#if defined(IOCON_PIO_ASW_SHIFT) +#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ +#endif + +#if defined(IOCON_PIO_SSEL_SHIFT) +#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ +#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ +#endif + +#if defined(IOCON_PIO_ECS_SHIFT) +#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ +#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ +#endif + +#if defined(IOCON_PIO_S_MODE_SHIFT) +#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK \ + (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_2CLK \ + (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_3CLK \ + (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ +#endif + +#if defined(IOCON_PIO_CLK_DIV_SHIFT) +#define IOCON_CLKDIV(div) \ + ((div) \ + << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif + +#else +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ + +#if defined(IOCON_PIO_MODE_SHIFT) +#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ +#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ +#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ +#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ +#endif + +#if defined(IOCON_PIO_I2CSLEW_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_EGP_SHIFT) +#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ +#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#endif + +#if defined(IOCON_PIO_INVERT_SHIFT) +#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ +#endif + +#if defined(IOCON_PIO_DIGIMODE_SHIFT) +#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ +#define IOCON_DIGITAL_EN \ + (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ +#endif + +#if defined(IOCON_PIO_FILTEROFF_SHIFT) +#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ +#endif + +#if defined(IOCON_PIO_I2CDRIVE_SHIFT) +#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ +#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ +#endif + +#if defined(IOCON_PIO_OD_SHIFT) +#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ +#endif + +#if defined(IOCON_PIO_I2CFILTER_SHIFT) +#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ +#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */ +#endif + +#if defined(IOCON_PIO_S_MODE_SHIFT) +#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ +#define IOCON_S_MODE_1CLK \ + (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_2CLK \ + (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE_3CLK \ + (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ + */ +#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ +#endif + +#if defined(IOCON_PIO_CLK_DIV_SHIFT) +#define IOCON_CLKDIV(div) \ + ((div) \ + << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ +#endif + +#endif +#if defined(__cplusplus) +extern "C" { +#endif + +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param ionumber : GPIO number to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) +{ + base->PIO[ionumber] = modefunc; +} +#else +/** + * @brief Sets I/O Control pin mux + * @param base : The base of IOCON peripheral on the chip + * @param port : GPIO port to mux + * @param pin : GPIO pin to mux + * @param modefunc : OR'ed values of type IOCON_* + * @return Nothing + */ +__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) +{ + base->PIO[port][pin] = modefunc; +} +#endif + +/** + * @brief Set all I/O Control pin muxing + * @param base : The base of IOCON peripheral on the chip + * @param pinArray : Pointer to array of pin mux selections + * @param arrayLength : Number of entries in pinArray + * @return Nothing + */ +__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) +{ + uint32_t i; + + for (i = 0; i < arrayLength; i++) + { +#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) + IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); +#else + IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); +#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ + } +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +#endif /* _FSL_IOCON_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_pint.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_pint.c new file mode 100644 index 000000000..ae9db698b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_pint.c @@ -0,0 +1,855 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pint.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pint" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; + +/*! @brief Callback function array for PINT(s). */ +static pint_cb_t + s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; +#else +/*! @brief Irq number array */ +static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; + +/*! @brief Callback function array for PINT(s). */ +static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_Init(PINT_Type *base) +{ + uint32_t i; + uint32_t pmcfg; + uint8_t pintcount; + assert(base); + pmcfg = 0; + +#if defined(SECPINT) + pintcount = SEC_PINT_PIN_INT_COUNT; +#else + pintcount = PINT_PIN_INT_COUNT; +#endif /* SECPINT */ + + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + + /* Disable all bit slices for pint*/ + for (i = 0; i < pintcount; i++) + { + pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if defined(SECPINT) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio_Sec); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* SECPINT */ +#else + /* if need config SECURE PINT device,then enable secure pint interrupt clock */ + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } +#if defined(SECPINT) + else if (base == SECPINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio_sec_Int); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } +#endif /* SECPINT */ +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ + + /* Disable all pattern match bit slices */ + base->PMCFG = pmcfg; +} + +/*! + * brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param intr Pin interrupt. + * param enable Selects detection logic. + * param callback Callback. + * + * retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) +{ + assert(base); + + /* Clear Rise and Fall flags first */ + PINT_PinInterruptClrRiseFlag(base, intr); + PINT_PinInterruptClrFallFlag(base, intr); + + /* select level or edge sensitive */ + base->ISEL = + (base->ISEL & ~(1UL << (uint32_t)intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1UL << (uint32_t)intr) : 0U); + + /* enable rising or level interrupt */ + if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) + { + base->SIENR = 1UL << (uint32_t)intr; + } + else + { + base->CIENR = 1UL << (uint32_t)intr; + } + + /* Enable falling or select high level */ + if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + { + base->SIENF = 1UL << (uint32_t)intr; + } + else + { + base->CIENF = 1UL << (uint32_t)intr; + } + + s_pintCallback[intr] = callback; +} + +/*! + * brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * param base Base address of the PINT peripheral. + * param pintr Pin interrupt. + * param enable Pointer to store the detection logic. + * param callback Callback. + * + * retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) +{ + uint32_t mask; + bool level; + + assert(base); + + *enable = kPINT_PinIntEnableNone; + level = false; + + mask = 1UL << (uint32_t)pintr; + if ((base->ISEL & mask) != 0U) + { + /* Pin interrupt is level sensitive */ + level = true; + } + + if ((base->IENR & mask) != 0U) + { + if (level) + { + /* Level interrupt is enabled */ + *enable = kPINT_PinIntEnableLowLevel; + } + else + { + /* Rising edge interrupt */ + *enable = kPINT_PinIntEnableRiseEdge; + } + } + + if ((base->IENF & mask) != 0U) + { + if (level) + { + /* Level interrupt is active high */ + *enable = kPINT_PinIntEnableHighLevel; + } + else + { + /* Either falling or both edge */ + if (*enable == kPINT_PinIntEnableRiseEdge) + { + /* Rising and faling edge */ + *enable = kPINT_PinIntEnableBothEdges; + } + else + { + /* Falling edge */ + *enable = kPINT_PinIntEnableFallEdge; + } + } + } + + *callback = s_pintCallback[pintr]; +} + +/*! + * brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t pmcfg; + uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; + uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + + assert(base); + + src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); + cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); + + /* Input source selection for selected bit slice */ + base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | (cfg->bs_src << src_shift); + + /* Bit slice configuration */ + pmcfg = base->PMCFG; + pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | (cfg->bs_cfg << cfg_shift); + + /* If end point is true, enable the bits */ + if ((uint32_t)bslice != 7UL) + { + if (cfg->end_point) + { + pmcfg |= (1UL << (uint32_t)bslice); + } + else + { + pmcfg &= ~(1UL << (uint32_t)bslice); + } + } + + base->PMCFG = pmcfg; + + /* Save callback pointer */ + s_pintCallback[bslice] = cfg->callback; +} + +/*! + * brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * param base Base address of the PINT peripheral. + * param bslice Pattern match bit slice number. + * param cfg Pointer to bit slice configuration. + * + * retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) +{ + uint32_t src_shift; + uint32_t cfg_shift; + uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; + uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; + + assert(base); + + src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); + cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); + + cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); + cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); + + if ((uint32_t)bslice == 7U) + { + cfg->end_point = true; + } + else + { + cfg->end_point = ((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice); + } + cfg->callback = s_pintCallback[bslice]; +} + +/*! + * brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * param base Base address of the PINT peripheral. + * + * retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) +{ + uint32_t pmctrl; + uint32_t pmstatus; + uint32_t pmsrc; + + pmctrl = base->PMCTRL; + pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; + if (pmstatus != 0UL) + { + /* Reset Pattern match engine detection logic */ + pmsrc = base->PMSRC; + base->PMSRC = pmsrc; + } + return (pmstatus); +} + +/*! + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr); + uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr); + + /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ + if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) + { + base->IST = (1UL << (uint32_t)pintr); + } +} + +/*! + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_PinInterruptClrStatusAll(PINT_Type *base) +{ + uint32_t pinIntMode = 0; + uint32_t pinIntStatus = 0; + uint32_t mask = 0; + uint32_t i; + + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + pinIntMode = base->ISEL & (1UL << i); + pinIntStatus = base->IST & (1UL << i); + + /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ + if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) + { + mask |= 1UL << i; + } + } + + base->IST = mask; +} + +/*! + * brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_EnableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + (void)EnableIRQ(s_pintIRQ[i]); + } +} + +/*! + * brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base); + + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + (void)EnableIRQ(s_pintIRQ[pintIdx]); +} + +/*! + * brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * param base Base address of the peripheral. + * + * retval None. + */ +void PINT_DisableCallback(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + (void)DisableIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + } +} + +/*! + * brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * param base Base address of the peripheral. + * param pinIdx pin index. + * + * retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) +{ + assert(base); + + (void)DisableIRQ(s_pintIRQ[pintIdx]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); +} + +/*! + * brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * param base Base address of the PINT peripheral. + * + * retval None. + */ +void PINT_Deinit(PINT_Type *base) +{ + uint32_t i; + + assert(base); + + /* Cleanup */ + PINT_DisableCallback(base); + for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + +#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(SECPINT) +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_Sec); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* SECPINT */ +#else + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +#if defined(SECPINT) + else if (base == SECPINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_sec_Int); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + } +#endif /* SECPINT */ +#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ +} +#if defined(SECPINT) +/* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) +{ + uint32_t pmstatus = 0; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + /* Call user function */ + if (s_pintCallback[kPINT_SecPinInt0] != NULL) + { + s_pintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); + } + if ((SECPINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +/* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); + /* Call user function */ + if (s_pintCallback[kPINT_SecPinInt1] != NULL) + { + s_pintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); + } + if ((SECPINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ +#endif /* SECPINT */ + +/* IRQ handler functions overloading weak symbols in the startup */ +void PIN_INT0_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt0] != NULL) + { + s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); + } + if ((PINT->ISEL & 0x1U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +void PIN_INT1_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt1] != NULL) + { + s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); + } + if ((PINT->ISEL & 0x2U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) +void PIN_INT2_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt2] != NULL) + { + s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); + } + if ((PINT->ISEL & 0x4U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) +void PIN_INT3_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt3] != NULL) + { + s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); + } + if ((PINT->ISEL & 0x8U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) +void PIN_INT4_DriverIRQHandler(void) +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt4] != NULL) + { + s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); + } + if ((PINT->ISEL & 0x10U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT5_DAC1_IRQHandler(void) +#else +void PIN_INT5_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt5] != NULL) + { + s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); + } + if ((PINT->ISEL & 0x20U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT6_USART3_IRQHandler(void) +#else +void PIN_INT6_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt6] != NULL) + { + s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); + } + if ((PINT->ISEL & 0x40U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif + +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) +#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT7_USART4_IRQHandler(void) +#else +void PIN_INT7_DriverIRQHandler(void) +#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ +{ + uint32_t pmstatus; + + /* Reset pattern match detection */ + pmstatus = PINT_PatternMatchResetDetectLogic(PINT); + /* Call user function */ + if (s_pintCallback[kPINT_PinInt7] != NULL) + { + s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); + } + if ((PINT->ISEL & 0x80U) == 0x0U) + { + /* Edge sensitive: clear Pin interrupt after callback */ + PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); + } +/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + exception return operation might vector to incorrect interrupt */ +#if defined __CORTEX_M && (__CORTEX_M == 4U) + __DSB(); +#endif +} +#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_pint.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_pint.h new file mode 100644 index 000000000..0e31210ec --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_pint.h @@ -0,0 +1,579 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_PINT_H_ +#define _FSL_PINT_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pint_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*!< Version 2.1.3 */ +/*@}*/ + +/* Number of interrupt line supported by PINT */ +#define PINT_PIN_INT_COUNT 8U + +/* Number of interrupt line supported by SECURE PINT */ +#define SEC_PINT_PIN_INT_COUNT 2U + +/* Number of input sources supported by PINT */ +#define PINT_INPUT_COUNT 8U + +/* PININT Bit slice source register bits */ +#define PININT_BITSLICE_SRC_START 8U +#define PININT_BITSLICE_SRC_MASK 7U + +/* PININT Bit slice configuration register bits */ +#define PININT_BITSLICE_CFG_START 8U +#define PININT_BITSLICE_CFG_MASK 7U +#define PININT_BITSLICE_ENDP_MASK 7U + +#define PINT_PIN_INT_LEVEL 0x10U +#define PINT_PIN_INT_EDGE 0x00U +#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U +#define PINT_PIN_INT_RISE 0x01U +#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) +#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) +#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + +/*! @brief PINT Pin Interrupt enable type */ +typedef enum _pint_pin_enable +{ + kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ + kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ + kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ + kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ + kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ + kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ +} pint_pin_enable_t; + +/*! @brief PINT Pin Interrupt type */ +typedef enum _pint_int +{ + kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ +#endif +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kPINT_SecPinInt0 = 8U, /*!< Secure Pin Interrupt 0 */ +#endif +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_SecPinInt1 = 9U, /*!< Secure Pin Interrupt 1 */ +#endif +} pint_pin_int_t; + +/*! @brief PINT Pattern Match bit slice input source type */ +typedef enum _pint_pmatch_input_src +{ + kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ + kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ + kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ + kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ + kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ + kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ + kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ +} pint_pmatch_input_src_t; + +/*! @brief PINT Pattern Match bit slice type */ +typedef enum _pint_pmatch_bslice +{ + kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) + kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) + kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) + kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) + kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) + kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ +#endif +#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) + kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ +#endif +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kSECPINT_PatternMatchBSlice0 = 8U, /*!< Bit slice 0 */ +#endif +#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kSECPINT_PatternMatchBSlice1 = 9U, /*!< Bit slice 1 */ +#endif +} pint_pmatch_bslice_t; + +/*! @brief PINT Pattern Match configuration type */ +typedef enum _pint_pmatch_bslice_cfg +{ + kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ + kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ + kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ + kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ + kPINT_PatternMatchHigh = 4U, /*!< High level */ + kPINT_PatternMatchLow = 5U, /*!< Low level */ + kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ + kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ +} pint_pmatch_bslice_cfg_t; + +/*! @brief PINT Callback function. */ +typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); + +typedef struct _pint_pmatch_cfg +{ + pint_pmatch_input_src_t bs_src; + pint_pmatch_bslice_cfg_t bs_cfg; + bool end_point; + pint_cb_t callback; +} pint_pmatch_cfg_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize PINT peripheral. + + * This function initializes the PINT peripheral and enables the clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Init(PINT_Type *base); + +/*! + * @brief Configure PINT peripheral pin interrupt. + + * This function configures a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param intr Pin interrupt. + * @param enable Selects detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); + +/*! + * @brief Get PINT peripheral pin interrupt configuration. + + * This function returns the configuration of a given pin interrupt. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * @param enable Pointer to store the detection logic. + * @param callback Callback. + * + * @retval None. + */ +void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); + +/*! + * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. + + * This function clears the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); + +/*! + * @brief Get Selected pin interrupt status. + + * This function returns the selected pin interrupt status. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->IST & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. + + * This function clears the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_PinInterruptClrStatusAll(PINT_Type *base); + +/*! + * @brief Get all pin interrupts status. + + * This function returns the status of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the status of corresponding pin interrupt. + * = 0 No pin interrupt request. = 1 Pin interrupt request active. + */ +static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) +{ + return (base->IST); +} + +/*! + * @brief Clear Selected pin interrupt fall flag. + + * This function clears the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->FALL = (1UL << (uint32_t)pintr); +} + +/*! + * @brief Get selected pin interrupt fall flag. + + * This function returns the selected pin interrupt fall flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->FALL & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt fall flags. + + * This function clears the fall flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) +{ + base->FALL = PINT_FALL_FDET_MASK; +} + +/*! + * @brief Get all pin interrupt fall flags. + + * This function returns the fall flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. + * 0 Falling edge has not been detected. = 1 Falling edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) +{ + return (base->FALL); +} + +/*! + * @brief Clear Selected pin interrupt rise flag. + + * This function clears the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + base->RISE = (1UL << (uint32_t)pintr); +} + +/*! + * @brief Get selected pin interrupt rise flag. + + * This function returns the selected pin interrupt rise flag. + * + * @param base Base address of the PINT peripheral. + * @param pintr Pin interrupt. + * + * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) +{ + return ((base->RISE & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); +} + +/*! + * @brief Clear all pin interrupt rise flags. + + * This function clears the rise flag for all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) +{ + base->RISE = PINT_RISE_RDET_MASK; +} + +/*! + * @brief Get all pin interrupt rise flags. + + * This function returns the rise flag of all pin interrupts. + * + * @param base Base address of the PINT peripheral. + * + * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. + * 0 Rising edge has not been detected. = 1 Rising edge has been detected. + */ +static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) +{ + return (base->RISE); +} + +/*! + * @brief Configure PINT pattern match. + + * This function configures a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get PINT pattern match configuration. + + * This function returns the configuration of a given pattern match bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * @param cfg Pointer to bit slice configuration. + * + * @retval None. + */ +void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); + +/*! + * @brief Get pattern match bit slice status. + + * This function returns the status of selected bit slice. + * + * @param base Base address of the PINT peripheral. + * @param bslice Pattern match bit slice number. + * + * @retval status = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) +{ + return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice; +} + +/*! + * @brief Get status of all pattern match bit slices. + + * This function returns the status of all bit slices. + * + * @param base Base address of the PINT peripheral. + * + * @retval status Each bit position indicates the match status of corresponding bit slice. + * = 0 Match has not been detected. = 1 Match has been detected. + */ +static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) +{ + return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; +} + +/*! + * @brief Reset pattern match detection logic. + + * This function resets the pattern match detection logic if any of the product term is matching. + * + * @param base Base address of the PINT peripheral. + * + * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. + * = 0 Match was detected. = 1 Match was not detected. + */ +uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); + +/*! + * @brief Enable pattern match function. + + * This function enables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Disable pattern match function. + + * This function disables the pattern match function. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisable(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; +} + +/*! + * @brief Enable RXEV output. + + * This function enables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Disable RXEV output. + + * This function disables the pattern match RXEV output. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) +{ + base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; +} + +/*! + * @brief Enable callback. + + * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored + * as soon as they are enabled, the callback function is not enabled until this function is called. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_EnableCallback(PINT_Type *base); + +/*! + * @brief Disable callback. + + * This function disables the interrupt for the selected PINT peripheral. Although the pins are still + * being monitored but the callback function is not called. + * + * @param base Base address of the peripheral. + * + * @retval None. + */ +void PINT_DisableCallback(PINT_Type *base); + +/*! + * @brief Deinitialize PINT peripheral. + + * This function disables the PINT clock. + * + * @param base Base address of the PINT peripheral. + * + * @retval None. + */ +void PINT_Deinit(PINT_Type *base); + +/*! + * @brief enable callback by pin index. + + * This function enables callback by pin index instead of enabling all pins. + * + * @param base Base address of the peripheral. + * @param pinIdx pin index. + * + * @retval None. + */ +void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + +/*! + * @brief disable callback by pin index. + + * This function disables callback by pin index instead of disabling all pins. + * + * @param base Base address of the peripheral. + * @param pinIdx pin index. + * + * @retval None. + */ +void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _FSL_PINT_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_power.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_power.c new file mode 100644 index 000000000..79266e66e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_power.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_common.h" +#include "fsl_power.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.power" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Empty file since implementation is in header file and power library */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_power.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_power.h new file mode 100644 index 000000000..0417a7fff --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_power.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_POWER_H_ +#define _FSL_POWER_H_ + +#include "fsl_common.h" + +/*! @addtogroup power */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief power driver version 2.0.0. */ +#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot) +#define PDRCFG0 0x0U +#define PDRCFG1 0x1U + +typedef enum pd_bits +{ + kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U), + kPDRUNCFG_PD_FLASH = MAKE_PD_BITS(PDRCFG0, 5U), + kPDRUNCFG_PD_TEMPS = MAKE_PD_BITS(PDRCFG0, 6U), + kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U), + kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U), + kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U), + kPDRUNCFG_PD_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 11U), + kPDRUNCFG_LP_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 12U), + kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U), + kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U), + kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U), + kPDRUNCFG_PD_RAMX = MAKE_PD_BITS(PDRCFG0, 16U), + kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U), + kPDRUNCFG_PD_VDDHV_ENA = MAKE_PD_BITS(PDRCFG0, 18U), + kPDRUNCFG_PD_VD7_ENA = MAKE_PD_BITS(PDRCFG0, 19U), + kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U), + kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U), + kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U), + kPDRUNCFG_PD_VREFP_SW = MAKE_PD_BITS(PDRCFG0, 23U), + kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U), + + kPDRUNCFG_PD_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 28U), + kPDRUNCFG_SEL_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 29U), + + kPDRUNCFG_ForceUnsigned = (int)0x80000000U +} pd_bit_t; + +/* Power mode configuration API parameter */ +typedef enum _power_mode_config +{ + kPmu_Sleep = 0U, + kPmu_Deep_Sleep = 1U, + kPmu_Deep_PowerDown = 2U, +} power_mode_cfg_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! +* @name Power Configuration +* @{ +*/ + +/*! + * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral + * + * @param en peripheral for which to enable the PDRUNCFG bit + * @return none + */ +static inline void POWER_EnablePD(pd_bit_t en) +{ + /* PDRUNCFGSET */ + SYSCON->PDRUNCFGSET[(en >> 8UL)] = (1UL << (en & 0xffU)); +} + +/*! + * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral + * + * @param en peripheral for which to disable the PDRUNCFG bit + * @return none + */ +static inline void POWER_DisablePD(pd_bit_t en) +{ + /* PDRUNCFGCLR */ + SYSCON->PDRUNCFGCLR[(en >> 8UL)] = (1UL << (en & 0xffU)); +} + +/*! + * @brief API to enable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_EnableDeepSleep(void) +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to disable deep sleep bit in the ARM Core. + * + * @return none + */ +static inline void POWER_DisableDeepSleep(void) +{ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; +} + +/*! + * @brief API to power down flash controller. + * + * @return none + */ +static inline void POWER_PowerDownFlash(void) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* TURN OFF clock for Flash Controller (only needed for FLASH programming, will be turned on by ROM API) */ + CLOCK_DisableClock(kCLOCK_Flash); + + /* TURN OFF clock for Flash Accelerator */ + CLOCK_DisableClock(kCLOCK_Fmc); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief API to power up flash controller. + * + * @return none + */ +static inline void POWER_PowerUpFlash(void) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* TURN ON clock for flash Accelerator */ + CLOCK_EnableClock(kCLOCK_Fmc); + + /* TURN ON clock for flash Controller */ + CLOCK_EnableClock(kCLOCK_Flash); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * @brief Power Library API to enter different power mode. + * + * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep + * @return none + */ +void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd); + +/*! + * @brief Power Library API to enter sleep mode. + * + * @return none + */ +void POWER_EnterSleep(void); + +/*! + * @brief Power Library API to enter deep sleep mode. + * + * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep + * @return none + */ +void POWER_EnterDeepSleep(uint64_t exclude_from_pd); + +/*! + * @brief Power Library API to enter deep power down mode. + * + * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep power down mode, + * but this is has no effect as the voltages are cut off. + * @return none + */ +void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd); + +/*! + * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. + * + * @param freq - The desired frequency at which the part would like to operate, + * note that the voltage and flash wait states should be set before changing frequency + * @return none + */ +void POWER_SetVoltageForFreq(uint32_t freq); + +/*! + * @brief Power Library API to choose low power regulation and set the voltage for the desired operating frequency. + * + * @param freq - The desired frequency at which the part would like to operate, + * note only 12MHz and 48Mhz are supported + * @return none + */ +void POWER_SetLowPowerVoltageForFreq(uint32_t freq); + +/*! + * @brief Power Library API to return the library version. + * + * @return version number of the power library + */ +uint32_t POWER_GetLibVersion(void); + +/* @} */ + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /* _FSL_POWER_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_reset.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_reset.c new file mode 100644 index 000000000..29bbc5b97 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_reset.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_reset.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.reset" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) + +/*! + * brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1u << bitPos; + + assert(bitPos < 32u); + + /* ASYNC_SYSCON registers have offset 1024 */ + if (regIndex >= SYSCON_PRESETCTRL_COUNT) + { + /* reset register is in ASYNC_SYSCON */ + + /* set bit */ + ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask; + /* wait until it reads 0b1 */ + while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) + { + } + } + else + { + /* reset register is in SYSCON */ + + /* set bit */ + SYSCON->PRESETCTRLSET[regIndex] = bitMask; + /* wait until it reads 0b1 */ + while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask)) + { + } + } +} + +/*! + * brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) +{ + const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1u << bitPos; + + assert(bitPos < 32u); + + /* ASYNC_SYSCON registers have offset 1024 */ + if (regIndex >= SYSCON_PRESETCTRL_COUNT) + { + /* reset register is in ASYNC_SYSCON */ + + /* clear bit */ + ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) + { + } + } + else + { + /* reset register is in SYSCON */ + + /* clear bit */ + SYSCON->PRESETCTRLCLR[regIndex] = bitMask; + /* wait until it reads 0b0 */ + while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask)) + { + } + } +} + +/*! + * brief Reset peripheral module. + * + * Reset peripheral module. + * + * param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral) +{ + RESET_SetPeripheralReset(peripheral); + RESET_ClearPeripheralReset(peripheral); +} + +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_reset.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_reset.h new file mode 100644 index 000000000..43b498729 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_reset.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_RESET_H_ +#define _FSL_RESET_H_ + +#include +#include +#include +#include +#include "fsl_device_registers.h" + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief reset driver version 2.0.1. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/*! + * @brief Enumeration for peripheral reset control bits + * + * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers + */ +typedef enum _SYSCON_RSTn +{ + kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ + kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ + kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */ + kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ + kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ + kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ + kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ + kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kUSB_RST_SHIFT_RSTn = 65536 | 25U, /**< USB reset control */ + kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer1 reset control */ + kCTIMER3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CTimer3 reset control */ +} SYSCON_RSTn_t; + +/** Array initializers with peripheral reset bits **/ +#define ADC_RSTS \ + { \ + kADC0_RST_SHIFT_RSTn \ + } /* Reset bits for ADC peripheral */ +#define CRC_RSTS \ + { \ + kCRC_RST_SHIFT_RSTn \ + } /* Reset bits for CRC peripheral */ +#define DMA_RSTS_N \ + { \ + kDMA_RST_SHIFT_RSTn \ + } /* Reset bits for DMA peripheral */ +#define FLEXCOMM_RSTS \ + { \ + kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ + kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \ + } /* Reset bits for FLEXCOMM peripheral */ +#define GINT_RSTS \ + { \ + kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ + } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ +#define GPIO_RSTS_N \ + { \ + kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \ + } /* Reset bits for GPIO peripheral */ +#define INPUTMUX_RSTS \ + { \ + kMUX_RST_SHIFT_RSTn \ + } /* Reset bits for INPUTMUX peripheral */ +#define IOCON_RSTS \ + { \ + kIOCON_RST_SHIFT_RSTn \ + } /* Reset bits for IOCON peripheral */ +#define FLASH_RSTS \ + { \ + kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ + } /* Reset bits for Flash peripheral */ +#define MRT_RSTS \ + { \ + kMRT_RST_SHIFT_RSTn \ + } /* Reset bits for MRT peripheral */ +#define PINT_RSTS \ + { \ + kPINT_RST_SHIFT_RSTn \ + } /* Reset bits for PINT peripheral */ +#define SCT_RSTS \ + { \ + kSCT0_RST_SHIFT_RSTn \ + } /* Reset bits for SCT peripheral */ +#define CTIMER_RSTS \ + { \ + kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn \ + } /* Reset bits for TIMER peripheral */ +#define USB_RSTS \ + { \ + kUSB_RST_SHIFT_RSTn \ + } /* Reset bits for USB peripheral */ +#define UTICK_RSTS \ + { \ + kUTICK_RST_SHIFT_RSTn \ + } /* Reset bits for UTICK peripheral */ +#define WWDT_RSTS \ + { \ + kWWDT_RST_SHIFT_RSTn \ + } /* Reset bits for WWDT peripheral */ + +typedef SYSCON_RSTn_t reset_ip_name_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Assert reset to peripheral. + * + * Asserts reset signal to specified peripheral module. + * + * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_SetPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Clear reset to peripheral. + * + * Clears reset signal to specified peripheral module, allows it to operate. + * + * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); + +/*! + * @brief Reset peripheral module. + * + * Reset peripheral module. + * + * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register + * and reset bit position in the reset register. + */ +void RESET_PeripheralReset(reset_ip_name_t peripheral); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* _FSL_RESET_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_usart.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_usart.c new file mode 100644 index 000000000..ce643d1e9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_usart.c @@ -0,0 +1,939 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart.h" +#include "fsl_device_registers.h" +#include "fsl_flexcomm.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" +#endif + +enum _usart_transfer_states +{ + kUSART_TxIdle, /* TX idle. */ + kUSART_TxBusy, /* TX busy. */ + kUSART_RxIdle, /* RX idle. */ + kUSART_RxBusy /* RX busy. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief IRQ name array */ +static const IRQn_Type s_usartIRQ[] = USART_IRQS; + +/*! @brief Array to map USART instance number to base address. */ +static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/* Get the index corresponding to the USART */ +/*! brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base) +{ + int i; + + for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++) + { + if ((uint32_t)base == s_usartBaseAddrs[i]) + { + return i; + } + } + + assert(false); + return 0; +} + +/*! + * brief Get the length of received data in RX ring buffer. + * + * param handle USART handle pointer. + * return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) +{ + size_t size; + + /* Check arguments */ + assert(NULL != handle); + + if (handle->rxRingBufferTail > handle->rxRingBufferHead) + { + size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + } + else + { + size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + } + return size; +} + +static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) +{ + bool full; + + /* Check arguments */ + assert(NULL != handle); + + if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) + { + full = true; + } + else + { + full = false; + } + return full; +} + +/*! + * brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + assert(NULL != ringBuffer); + + /* Setup the ringbuffer address */ + handle->rxRingBuffer = ringBuffer; + handle->rxRingBufferSize = ringBufferSize; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; + /* ring buffer is ready we can start receiving data */ + base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +} + +/*! + * brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert(NULL != base); + assert(NULL != handle); + + if (handle->rxState == kUSART_RxIdle) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; + } + handle->rxRingBuffer = NULL; + handle->rxRingBufferSize = 0U; + handle->rxRingBufferHead = 0U; + handle->rxRingBufferTail = 0U; +} + +/*! + * brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param config Pointer to user-defined configuration structure. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_InvalidArgument USART base address is not valid + * retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) +{ + int result; + + /* check arguments */ + assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* initialize flexcomm to USART mode */ + result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); + if (kStatus_Success != result) + { + return result; + } + + if (config->enableTx) + { + /* empty and enable txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; + } + + /* empty and enable rxFIFO */ + if (config->enableRx) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; + /* setup trigger level */ + base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); + base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); + /* enable trigger interrupt */ + base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; + } + /* setup configuration and enable USART */ + base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | + USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | + USART_CFG_SYNCEN(config->syncMode >> 1) | USART_CFG_SYNCMST(config->syncMode) | + USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_ENABLE_MASK; + + /* Setup baudrate */ + result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + /* Setting continuous Clock configuration. used for synchronous mode. */ + USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); + + return kStatus_Success; +} + +/*! + * brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base) +{ + /* Check arguments */ + assert(NULL != base); + while (!(base->STAT & USART_STAT_TXIDLE_MASK)) + { + } + /* Disable interrupts, disable dma requests, disable peripheral */ + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | + USART_FIFOINTENCLR_RXLVL_MASK; + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); + base->CFG &= ~(USART_CFG_ENABLE_MASK); +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config) +{ + /* Check arguments */ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + /* Set always all members ! */ + config->baudRate_Bps = 115200U; + config->parityMode = kUSART_ParityDisabled; + config->stopBitCount = kUSART_OneStopBit; + config->bitCountPerChar = kUSART_8BitsPerChar; + config->loopback = false; + config->enableRx = false; + config->enableTx = false; + config->txWatermark = kUSART_TxFifo0; + config->rxWatermark = kUSART_RxFifo1; + config->syncMode = kUSART_SyncModeDisabled; + config->enableContinuousSCLK = false; + config->clockPolarity = kUSART_RxSampleOnFallingEdge; +} + +/*! + * brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * endcode + * + * param base USART peripheral base address. + * param baudrate_Bps USART baudrate to be set. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) +{ + uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; + uint32_t osrval, brgval, diff, baudrate; + + /* check arguments */ + assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); + if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) + { + return kStatus_InvalidArgument; + } + + /* If synchronous master mode is enabled, only configure the BRG value. */ + if (base->CFG & USART_CFG_SYNCEN_MASK) + { + if (base->CFG & USART_CFG_SYNCMST_MASK) + { + brgval = srcClock_Hz / baudrate_Bps; + base->BRG = brgval - 1; + } + } + else + { + /* + * Smaller values of OSR can make the sampling position within a data bit less accurate and may + * potentially cause more noise errors or incorrect data. + */ + for (osrval = best_osrval; osrval >= 8; osrval--) + { + brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1; + if (brgval > 0xFFFF) + { + continue; + } + baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1)); + diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate; + if (diff < best_diff) + { + best_diff = diff; + best_osrval = osrval; + best_brgval = brgval; + } + } + + /* value over range */ + if (best_brgval > 0xFFFF) + { + return kStatus_USART_BaudrateNotSupport; + } + + base->OSR = best_osrval; + base->BRG = best_brgval; + } + + return kStatus_Success; +} + +/*! + * brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * param base USART peripheral base address. + * param data Start address of the data to write. + * param length Size of the data to write. + */ +void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return; + } + /* Check whether txFIFO is enabled */ + if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) + { + return; + } + for (; length > 0; length--) + { + /* Loop until txFIFO get some space for new data */ + while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) + { + } + base->FIFOWR = *data; + data++; + } + /* Wait to finish transfer */ + while (!(base->STAT & USART_STAT_TXIDLE_MASK)) + { + } +} + +/*! + * brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * param base USART peripheral base address. + * param data Start address of the buffer to store the received data. + * param length Size of the buffer. + * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * retval kStatus_USART_ParityError Noise error happened while receiving data. + * retval kStatus_USART_NoiseError Framing error happened while receiving data. + * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) +{ + uint32_t status; + + /* check arguments */ + assert(!((NULL == base) || (NULL == data))); + if ((NULL == base) || (NULL == data)) + { + return kStatus_InvalidArgument; + } + + /* Check whether rxFIFO is enabled */ + if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK)) + { + return kStatus_Fail; + } + for (; length > 0; length--) + { + /* loop until rxFIFO have some data to read */ + while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) + { + } + /* check receive status */ + status = base->STAT; + if (status & USART_STAT_FRAMERRINT_MASK) + { + base->STAT |= USART_STAT_FRAMERRINT_MASK; + return kStatus_USART_FramingError; + } + if (status & USART_STAT_PARITYERRINT_MASK) + { + base->STAT |= USART_STAT_PARITYERRINT_MASK; + return kStatus_USART_ParityError; + } + if (status & USART_STAT_RXNOISEINT_MASK) + { + base->STAT |= USART_STAT_RXNOISEINT_MASK; + return kStatus_USART_NoiseError; + } + /* check rxFIFO status */ + if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) + { + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + return kStatus_USART_RxError; + } + + *data = base->FIFORD; + data++; + } + return kStatus_Success; +} + +/*! + * brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData) +{ + int32_t instance = 0; + + /* Check 'base' */ + assert(!((NULL == base) || (NULL == handle))); + if ((NULL == base) || (NULL == handle)) + { + return kStatus_InvalidArgument; + } + + instance = USART_GetInstance(base); + + memset(handle, 0, sizeof(*handle)); + /* Set the TX/RX state. */ + handle->rxState = kUSART_RxIdle; + handle->txState = kUSART_TxIdle; + /* Set the callback and user data. */ + handle->callback = callback; + handle->userData = userData; + handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base); + handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base); + + FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)USART_TransferHandleIRQ, handle); + + /* Enable interrupt in NVIC. */ + EnableIRQ(s_usartIRQ[instance]); + + return kStatus_Success; +} + +/*! + * brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the ref kStatus_USART_TxIdle as status parameter. + * + * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure. See #usart_transfer_t. + * retval kStatus_Success Successfully start the data transmission. + * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) +{ + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); + if ((0 == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* Return error if current TX busy. */ + if (kUSART_TxBusy == handle->txState) + { + return kStatus_USART_TxBusy; + } + else + { + handle->txData = xfer->data; + handle->txDataSize = xfer->dataSize; + handle->txDataSizeAll = xfer->dataSize; + handle->txState = kUSART_TxBusy; + /* Enable transmiter interrupt. */ + base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK; + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Disable interrupts */ + USART_DisableInterrupts(base, kUSART_TxLevelInterruptEnable); + /* Empty txFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; + + handle->txDataSize = 0; + handle->txState = kUSART_TxIdle; +} + +/*! + * brief Get the number of bytes that have been written to USART TX register. + * + * This function gets the number of bytes that have been written to USART TX + * register by interrupt method. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Send bytes count. + * retval kStatus_NoTransferInProgress No send in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if (kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - handle->txDataSize; + + return kStatus_Success; +} + +/*! + * brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param xfer USART transfer structure, see #usart_transfer_t. + * param receivedBytes Bytes received from the ring buffer directly. + * retval kStatus_Success Successfully queue the transfer into transmit queue. + * retval kStatus_USART_RxBusy Previous receive request is not finished. + * retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes) +{ + uint32_t i; + /* How many bytes to copy from ring buffer to user memory. */ + size_t bytesToCopy = 0U; + /* How many bytes to receive. */ + size_t bytesToReceive; + /* How many bytes currently have received. */ + size_t bytesCurrentReceived; + uint32_t regPrimask = 0U; + + /* Check arguments */ + assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); + if ((NULL == base) || (NULL == handle) || (NULL == xfer)) + { + return kStatus_InvalidArgument; + } + /* Check xfer members */ + assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); + if ((0 == xfer->dataSize) || (NULL == xfer->data)) + { + return kStatus_InvalidArgument; + } + + /* How to get data: + 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize + to uart handle, enable interrupt to store received data to xfer->data. When + all data received, trigger callback. + 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. + If there are enough data in ring buffer, copy them to xfer->data and return. + If there are not enough data in ring buffer, copy all of them to xfer->data, + save the xfer->data remained empty space to uart handle, receive data + to this empty space and trigger callback when finished. */ + if (kUSART_RxBusy == handle->rxState) + { + return kStatus_USART_RxBusy; + } + else + { + bytesToReceive = xfer->dataSize; + bytesCurrentReceived = 0U; + /* If RX ring buffer is used. */ + if (handle->rxRingBuffer) + { + /* Disable IRQ, protect ring buffer. */ + regPrimask = DisableGlobalIRQ(); + /* How many bytes in RX ring buffer currently. */ + bytesToCopy = USART_TransferGetRxRingBufferLength(handle); + if (bytesToCopy) + { + bytesToCopy = MIN(bytesToReceive, bytesToCopy); + bytesToReceive -= bytesToCopy; + /* Copy data from ring buffer to user memory. */ + for (i = 0U; i < bytesToCopy; i++) + { + xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + } + /* If ring buffer does not have enough data, still need to read more data. */ + if (bytesToReceive) + { + /* No data in ring buffer, save the request to UART handle. */ + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUSART_RxBusy; + } + /* Enable IRQ if previously enabled. */ + EnableGlobalIRQ(regPrimask); + /* Call user callback since all data are received. */ + if (0 == bytesToReceive) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Ring buffer not used. */ + else + { + handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxDataSize = bytesToReceive; + handle->rxDataSizeAll = bytesToReceive; + handle->rxState = kUSART_RxBusy; + + /* Enable RX interrupt. */ + base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK; + } + /* Return the how many bytes have read. */ + if (receivedBytes) + { + *receivedBytes = bytesCurrentReceived; + } + } + return kStatus_Success; +} + +/*! + * brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) +{ + assert(NULL != handle); + + /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ + if (!handle->rxRingBuffer) + { + /* Disable interrupts */ + USART_DisableInterrupts(base, kUSART_RxLevelInterruptEnable); + /* Empty rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + } + + handle->rxDataSize = 0U; + handle->rxState = kUSART_RxIdle; +} + +/*! + * brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Receive bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != count); + + if (kUSART_RxIdle == handle->rxState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->rxDataSizeAll - handle->rxDataSize; + + return kStatus_Success; +} + +/*! + * brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer); + bool sendEnabled = handle->txDataSize; + + /* If RX overrun. */ + if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) + { + /* Clear rx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxError, handle->userData); + } + } + while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) || + (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))) + { + /* Receive data */ + if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) + { + /* Receive to app bufffer if app buffer is present */ + if (handle->rxDataSize) + { + *handle->rxData = base->FIFORD; + handle->rxDataSize--; + handle->rxData++; + receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer)); + if (!handle->rxDataSize) + { + if (!handle->rxRingBuffer) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; + } + handle->rxState = kUSART_RxIdle; + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); + } + } + } + /* Otherwise receive to ring buffer if ring buffer is present */ + else + { + if (handle->rxRingBuffer) + { + /* If RX ring buffer is full, trigger callback to notify over run. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); + } + } + /* If ring buffer is still full after callback function, the oldest data is overridden. */ + if (USART_TransferIsRxRingBufferFull(handle)) + { + /* Increase handle->rxRingBufferTail to make room for new data. */ + if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferTail = 0U; + } + else + { + handle->rxRingBufferTail++; + } + } + /* Read data. */ + handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD; + /* Increase handle->rxRingBufferHead. */ + if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + { + handle->rxRingBufferHead = 0U; + } + else + { + handle->rxRingBufferHead++; + } + } + } + } + /* Send data */ + if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) + { + base->FIFOWR = *handle->txData; + handle->txDataSize--; + handle->txData++; + sendEnabled = handle->txDataSize != 0; + if (!sendEnabled) + { + base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; + handle->txState = kUSART_TxIdle; + if (handle->callback) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } + } + } + } + + /* ring buffer is not used */ + if (NULL == handle->rxRingBuffer) + { + /* restore if rx transfer ends and rxLevel is different from default value */ + if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); + } + /* decrease level if rx transfer is bellow */ + if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1))) + { + base->FIFOTRIG = + (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1)); + } + } +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_usart.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_usart.h new file mode 100644 index 000000000..c0d64285e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/drivers/fsl_usart.h @@ -0,0 +1,718 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_USART_H_ +#define _FSL_USART_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup usart_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART driver version 2.1.0. */ +#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) +#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) + +/*! @brief Error codes for the USART driver. */ +enum _usart_status +{ + kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ + kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ + kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ + kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ + kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ + kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ + kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ + kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ + kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ + kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ + kStatus_USART_BaudrateNotSupport = + MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ +}; + +/*! @brief USART synchronous mode. */ +typedef enum _usart_sync_mode +{ + kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ + kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ + kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ +} usart_sync_mode_t; + +/*! @brief USART parity mode. */ +typedef enum _usart_parity_mode +{ + kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ + kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ + kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ +} usart_parity_mode_t; + +/*! @brief USART stop bit count. */ +typedef enum _usart_stop_bit_count +{ + kUSART_OneStopBit = 0U, /*!< One stop bit */ + kUSART_TwoStopBit = 1U, /*!< Two stop bits */ +} usart_stop_bit_count_t; + +/*! @brief USART data size. */ +typedef enum _usart_data_len +{ + kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ + kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ +} usart_data_len_t; + +/*! @brief USART clock polarity configuration, used in sync mode.*/ +typedef enum _usart_clock_polarity +{ + kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ + kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ +} usart_clock_polarity_t; + +/*! @brief txFIFO watermark values */ +typedef enum _usart_txfifo_watermark +{ + kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ + kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ + kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ + kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ + kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ + kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ + kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ + kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ +} usart_txfifo_watermark_t; + +/*! @brief rxFIFO watermark values */ +typedef enum _usart_rxfifo_watermark +{ + kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ + kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ + kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ + kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ + kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ + kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ + kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ + kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ +} usart_rxfifo_watermark_t; + +/*! + * @brief USART interrupt configuration structure, default settings all disabled. + */ +enum _usart_interrupt_enable +{ + kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), + kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), + kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), + kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), +}; + +/*! + * @brief USART status flags. + * + * This provides constants for the USART status flags for use in the USART functions. + */ +enum _usart_flags +{ + kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ + kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ + kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ + kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ + kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ + kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ +}; + +/*! @brief USART configuration structure. */ +typedef struct _usart_config +{ + uint32_t baudRate_Bps; /*!< USART baud rate */ + usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ + usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ + usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ + bool loopback; /*!< Enable peripheral loopback */ + bool enableRx; /*!< Enable RX */ + bool enableTx; /*!< Enable TX */ + bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ + usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ +} usart_config_t; + +/*! @brief USART transfer structure. */ +typedef struct _usart_transfer +{ + uint8_t *data; /*!< The buffer of data to be transfer.*/ + size_t dataSize; /*!< The byte count to be transfer. */ +} usart_transfer_t; + +/* Forward declaration of the handle typedef. */ +typedef struct _usart_handle usart_handle_t; + +/*! @brief USART transfer callback function. */ +typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); + +/*! @brief USART handle structure. */ +struct _usart_handle +{ + uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ + + uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ + size_t rxRingBufferSize; /*!< Size of the ring buffer. */ + volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ + volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ + + usart_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< USART callback function parameter.*/ + + volatile uint8_t txState; /*!< TX transfer state. */ + volatile uint8_t rxState; /*!< RX transfer state */ + + usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ + usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* _cplusplus */ + +/*! @brief Returns instance number for USART peripheral base address. */ +uint32_t USART_GetInstance(USART_Type *base); + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Initializes a USART instance with user configuration structure and peripheral clock. + * + * This function configures the USART module with the user-defined settings. The user can configure the configuration + * structure and also get the default configuration by using the USART_GetDefaultConfig() function. + * Example below shows how to use this API to configure USART. + * @code + * usart_config_t usartConfig; + * usartConfig.baudRate_Bps = 115200U; + * usartConfig.parityMode = kUSART_ParityDisabled; + * usartConfig.stopBitCount = kUSART_OneStopBit; + * USART_Init(USART1, &usartConfig, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param config Pointer to user-defined configuration structure. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_InvalidArgument USART base address is not valid + * @retval kStatus_Success Status USART initialize succeed + */ +status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes a USART instance. + * + * This function waits for TX complete, disables TX and RX, and disables the USART clock. + * + * @param base USART peripheral base address. + */ +void USART_Deinit(USART_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the USART configuration structure to a default value. The default + * values are: + * usartConfig->baudRate_Bps = 115200U; + * usartConfig->parityMode = kUSART_ParityDisabled; + * usartConfig->stopBitCount = kUSART_OneStopBit; + * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; + * usartConfig->loopback = false; + * usartConfig->enableTx = false; + * usartConfig->enableRx = false; + * + * @param config Pointer to configuration structure. + */ +void USART_GetDefaultConfig(usart_config_t *config); + +/*! + * @brief Sets the USART instance baud rate. + * + * This function configures the USART module baud rate. This function is used to update + * the USART module baud rate after the USART module is initialized by the USART_Init. + * @code + * USART_SetBaudRate(USART1, 115200U, 20000000U); + * @endcode + * + * @param base USART peripheral base address. + * @param baudrate_Bps USART baudrate to be set. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Get USART status flags. + * + * This function get all USART status flags, the flags are returned as the logical + * OR value of the enumerators @ref _usart_flags. To check a specific status, + * compare the return value with enumerators in @ref _usart_flags. + * For example, to check whether the TX is empty: + * @code + * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) + * { + * ... + * } + * @endcode + * + * @param base USART peripheral base address. + * @return USART status flags which are ORed by the enumerators in the _usart_flags. + */ +static inline uint32_t USART_GetStatusFlags(USART_Type *base) +{ + return base->FIFOSTAT; +} + +/*! + * @brief Clear USART status flags. + * + * This function clear supported USART status flags + * Flags that can be cleared or set are: + * kUSART_TxError + * kUSART_RxError + * For example: + * @code + * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) + * @endcode + * + * @param base USART peripheral base address. + * @param mask status flags to be cleared. + */ +static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) +{ + /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ + base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); +} + +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables USART interrupts according to the provided mask. + * + * This function enables the USART interrupts according to the provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * For example, to enable TX empty interrupt and RX full interrupt: + * @code + * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENSET = mask & 0xF; +} + +/*! + * @brief Disables USART interrupts according to a provided mask. + * + * This function disables the USART interrupts according to a provided mask. The mask + * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. + * This example shows how to disable the TX empty interrupt and RX full interrupt: + * @code + * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); + * @endcode + * + * @param base USART peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. + */ +static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) +{ + base->FIFOINTENCLR = mask & 0xF; +} + +/*! + * @brief Returns enabled USART interrupts. + * + * This function returns the enabled USART interrupts. + * + * @param base USART peripheral base address. + */ +static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) +{ + return base->FIFOINTENSET; +} + +/*! + * @brief Enable DMA for Tx + */ +static inline void USART_EnableTxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); + } +} + +/*! + * @brief Enable DMA for Rx + */ +static inline void USART_EnableRxDMA(USART_Type *base, bool enable) +{ + if (enable) + { + base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; + } + else + { + base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); + } +} + +/*! + * @brief Enable CTS. + * This function will determine whether CTS is used for flow control. + * + * @param base USART peripheral base address. + * @param enable Enable CTS or not, true for enable and false for disable. + */ +static inline void USART_EnableCTS(USART_Type *base, bool enable) +{ + if (enable) + { + base->CFG |= USART_CFG_CTSEN_MASK; + } + else + { + base->CFG &= ~USART_CFG_CTSEN_MASK; + } +} + +/*! + * @brief Continuous Clock generation. + * By default, SCLK is only output while data is being transmitted in synchronous mode. + * Enable this funciton, SCLK will run continuously in synchronous mode, allowing + * characters to be received on Un_RxD independently from transmission on Un_TXD). + * + * @param base USART peripheral base address. + * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. + */ +static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CC_MASK; + } + else + { + base->CTL &= ~USART_CTL_CC_MASK; + } +} + +/*! + * @brief Enable Continuous Clock generation bit auto clear. + * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete + * character has been received. This bit is cleared at the same time. + * + * @param base USART peripheral base address. + * @param enable Enable auto clear or not, true for enable and false for disable. + */ +static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) +{ + if (enable) + { + base->CTL |= USART_CTL_CLRCCONRX_MASK; + } + else + { + base->CTL &= ~USART_CTL_CLRCCONRX_MASK; + } +} +/* @} */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Writes to the FIFOWR register. + * + * This function writes data to the txFIFO directly. The upper layer must ensure + * that txFIFO has space for data to write before calling this function. + * + * @param base USART peripheral base address. + * @param data The byte to write. + */ +static inline void USART_WriteByte(USART_Type *base, uint8_t data) +{ + base->FIFOWR = data; +} + +/*! + * @brief Reads the FIFORD register directly. + * + * This function reads data from the rxFIFO directly. The upper layer must + * ensure that the rxFIFO is not empty before calling this function. + * + * @param base USART peripheral base address. + * @return The byte read from USART data register. + */ +static inline uint8_t USART_ReadByte(USART_Type *base) +{ + return base->FIFORD; +} + +/*! + * @brief Writes to the TX register using a blocking method. + * + * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO + * to have room and writes data to the TX buffer. + * + * @param base USART peripheral base address. + * @param data Start address of the data to write. + * @param length Size of the data to write. + */ +void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); + +/*! + * @brief Read RX data register using a blocking method. + * + * This function polls the RX register, waits for the RX register to be full or for RX FIFO to + * have data and read data from the TX register. + * + * @param base USART peripheral base address. + * @param data Start address of the buffer to store the received data. + * @param length Size of the buffer. + * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. + * @retval kStatus_USART_ParityError Noise error happened while receiving data. + * @retval kStatus_USART_NoiseError Framing error happened while receiving data. + * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * @retval kStatus_Success Successfully received all data. + */ +status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); + +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +/*! + * @brief Initializes the USART handle. + * + * This function initializes the USART handle which can be used for other USART + * transactional APIs. Usually, for a specified USART instance, + * call this API once to get the initialized handle. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +status_t USART_TransferCreateHandle(USART_Type *base, + usart_handle_t *handle, + usart_transfer_callback_t callback, + void *userData); + +/*! + * @brief Transmits a buffer of data using the interrupt method. + * + * This function sends data using an interrupt method. This is a non-blocking function, which + * returns directly without waiting for all data to be written to the TX register. When + * all data is written to the TX register in the IRQ handler, the USART driver calls the callback + * function and passes the @ref kStatus_USART_TxIdle as status parameter. + * + * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written + * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, + * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure. See #usart_transfer_t. + * @retval kStatus_Success Successfully start the data transmission. + * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); + +/*! + * @brief Sets up the RX ring buffer. + * + * This function sets up the RX ring buffer to a specific USART handle. + * + * When the RX ring buffer is used, data received are stored into the ring buffer even when the + * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received + * in the ring buffer, the user can get the received data from the ring buffer directly. + * + * @note When using the RX ring buffer, one byte is reserved for internal use. In other + * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. + * @param ringBufferSize size of the ring buffer. + */ +void USART_TransferStartRingBuffer(USART_Type *base, + usart_handle_t *handle, + uint8_t *ringBuffer, + size_t ringBufferSize); + +/*! + * @brief Aborts the background transfer and uninstalls the ring buffer. + * + * This function aborts the background transfer and uninstalls the ring buffer. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the length of received data in RX ring buffer. + * + * @param handle USART handle pointer. + * @return Length of received data in RX ring buffer. + */ +size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); + +/*! + * @brief Aborts the interrupt-driven data transmit. + * + * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out + * how many bytes are still not sent out. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been written to USART TX register. + * + * This function gets the number of bytes that have been written to USART TX + * register by interrupt method. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Send bytes count. + * @retval kStatus_NoTransferInProgress No send in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief Receives a buffer of data using an interrupt method. + * + * This function receives data using an interrupt method. This is a non-blocking function, which + * returns without waiting for all data to be received. + * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and + * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. + * After copying, if the data in the ring buffer is not enough to read, the receive + * request is saved by the USART driver. When the new data arrives, the receive request + * is serviced first. When all data is received, the USART driver notifies the upper layer + * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. + * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. + * The 5 bytes are copied to the xfer->data and this function returns with the + * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is + * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. + * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt + * to receive data to the xfer->data. When all data is received, the upper layer is notified. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param xfer USART transfer structure, see #usart_transfer_t. + * @param receivedBytes Bytes received from the ring buffer directly. + * @retval kStatus_Success Successfully queue the transfer into transmit queue. + * @retval kStatus_USART_RxBusy Previous receive request is not finished. + * @retval kStatus_InvalidArgument Invalid argument. + */ +status_t USART_TransferReceiveNonBlocking(USART_Type *base, + usart_handle_t *handle, + usart_transfer_t *xfer, + size_t *receivedBytes); + +/*! + * @brief Aborts the interrupt-driven data receiving. + * + * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out + * how many bytes not received yet. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); + +/*! + * @brief Get the number of bytes that have been received. + * + * This function gets the number of bytes that have been received. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Receive bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); + +/*! + * @brief USART IRQ handle function. + * + * This function handles the USART transmit and receive IRQ request. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + */ +void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_USART_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/readme.txt b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/readme.txt new file mode 100644 index 000000000..fb06ed3a5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/readme.txt @@ -0,0 +1,6 @@ +This directory contains projects for GCC/IAR/Keil compilers. The targeted MCU is NXP LPC51U68, which is CM0+. + +todo: +- clean up IAR compiler warnings. (Though the warnings are in vendor's driver code, see if we can clean it up. ) +- finalize Keil linker script.(Two heap blocks shall be placed in intended RAM banks. Currently, both goes to a same RAM bank.) +- GCC project folder directory name is not consistent with the other two. diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_assert.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_assert.c new file mode 100644 index 000000000..c07b55c6b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_assert.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); + for (;;) + { + __BKPT(0); + } +} +#elif (defined(__GNUC__)) +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); + for (;;) + { + __BKPT(0); + } +} +#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ +#endif /* NDEBUG */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_debug_console.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_debug_console.c new file mode 100644 index 000000000..b6d628a09 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_debug_console.c @@ -0,0 +1,1123 @@ +/* + * This is a modified version of the file printf.c, which was distributed + * by Motorola as part of the M5407C3BOOT.zip package used to initialize + * the M5407C3 evaluation board. + * + * Copyright: + * 1999-2000 MOTOROLA, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Motorola, Inc. This + * software is provided on an "AS IS" basis and without warranty. + * + * To the maximum extent permitted by applicable law, MOTOROLA + * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR + * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE + * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY + * ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING + * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS + * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY + * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Motorola assumes no responsibility for the maintenance and support + * of this software + + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#include +#endif + +#ifdef FSL_RTOS_FREE_RTOS +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" +#endif + +#include "fsl_debug_console_conf.h" +#include "fsl_str.h" + +#include "fsl_common.h" +#include "serial_manager.h" + +#include "fsl_debug_console.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#endif +#endif + +#if SDK_DEBUGCONSOLE +#define DEBUG_CONSOLE_FUNCTION_PREFIX +#else +#define DEBUG_CONSOLE_FUNCTION_PREFIX static +#endif + +/*! @brief character backspace ASCII value */ +#define DEBUG_CONSOLE_BACKSPACE 127U + +/* lock definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +static SemaphoreHandle_t s_debugConsoleReadSemaphore; +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore; +#endif + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static volatile uint8_t s_debugConsoleReadWaitSemaphore; +#endif + +#else + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +/*! @brief get current runing environment is ISR or not */ +#ifdef __CA7_REV +#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel() +#else +#define IS_RUNNING_IN_ISR() __get_IPSR() +#endif /* __CA7_REV */ + +/* semaphore definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +/* mutex semaphore */ +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex()) + +/* clang-format off */ +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreGive(mutex); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreTake(mutex, portMAX_DELAY); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + result = xSemaphoreTake(mutex, 0U); \ + } \ + else \ + { \ + result = 1U; \ + } \ +} +/* clang-format on */ + +/* Binary semaphore */ +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary()) +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake(binary, portMAX_DELAY)) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR(binary, NULL)) + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE) + +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) + +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \ + { \ + while (!binary) \ + { \ + } \ + binary = false; \ + } +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true) +#else +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/* add other implementation here + *such as : + * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx) + */ + +#else + +#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE. + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/* receive state structure */ +typedef struct _debug_console_write_ring_buffer +{ + uint32_t ringBufferSize; + volatile uint32_t ringHead; + volatile uint32_t ringTail; + uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; +} debug_console_write_ring_buffer_t; +#endif + +typedef struct _debug_console_state_struct +{ + uint8_t serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE]; + serial_handle_t serialHandle; /*!< serial manager handle */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + debug_console_write_ring_buffer_t writeRingBuffer; + uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; +#endif + uint8_t serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE]; + uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE]; +} debug_console_state_struct_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Debug console state information. */ +static debug_console_state_struct_t s_debugConsoleState; +serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief This is a printf call back function which is used to relocate the log to buffer + * or print the log immediately when the local buffer is full. + * + * @param[in] buf Buffer to store log. + * @param[in] indicator Buffer index. + * @param[in] val Target character to store. + * @param[in] len length of the character + * + */ +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len); +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch); +int DbgConsole_SendData(uint8_t *ch, size_t size); +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size); +int DbgConsole_ReadLine(uint8_t *buf, size_t size); +int DbgConsole_ReadCharacter(uint8_t *ch); + +#if ((SDK_DEBUGCONSOLE > 0U) || \ + ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +static void DbgConsole_SerialManagerTxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + debug_console_state_struct_t *ioState; + uint32_t sendDataLength; + + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + ioState = (debug_console_state_struct_t *)callbackParam; + + ioState->writeRingBuffer.ringTail += message->length; + if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize) + { + ioState->writeRingBuffer.ringTail = 0U; + } + + if (kStatus_SerialManager_Success == status) + { + if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead) + { + if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail) + { + sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail; + } + else + { + sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail; + } + + (void)SerialManager_WriteNonBlocking( + ((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]), + &ioState->writeRingBuffer.ringBuffer[ioState->writeRingBuffer.ringTail], sendDataLength); + } + } + else if (kStatus_SerialManager_Canceled == status) + { + ioState->writeRingBuffer.ringTail = 0U; + ioState->writeRingBuffer.ringHead = 0U; + } + else + { + /*MISRA rule 16.4*/ + } +} + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +static void DbgConsole_SerialManagerRxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + if (kStatus_SerialManager_Notify == status) + { + } + else if (kStatus_SerialManager_Success == status) + { + /* release s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore); + } + else + { + /*MISRA rule 16.4*/ + } +} +#endif + +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + return kStatus_Fail; +#else + status_t status = (status_t)kStatus_SerialManager_Error; + +/* recieve one char every time */ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + status = (status_t)SerialManager_ReadNonBlocking( + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#else + status = (status_t)SerialManager_ReadBlocking( + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#endif + if ((status_t)kStatus_SerialManager_Success != status) + { + return (status_t)kStatus_Fail; + } + /* wait s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore); + + return (status_t)kStatus_Success; +#endif + +#else + + return (status_t)kStatus_Fail; + +#endif +} + +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION +static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index) +{ + /* Due to scanf take \n and \r as end of string,should not echo */ + if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar)) + { + /* recieve one char every time */ + if (1 != DbgConsole_SendDataReliable(ch, 1U)) + { + return (status_t)kStatus_Fail; + } + } + + if ((!isGetChar) && (index != NULL)) + { + if (DEBUG_CONSOLE_BACKSPACE == *ch) + { + if ((*index >= 2)) + { + *index -= 2; + } + else + { + *index = 0; + } + } + } + + return (status_t)kStatus_Success; +} +#endif + +int DbgConsole_SendData(uint8_t *ch, size_t size) +{ + status_t status = (status_t)kStatus_SerialManager_Error; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t sendDataLength; + int txBusy = 0; +#endif + assert(NULL != ch); + assert(0 != size); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + txBusy = 1; + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1; + if (sendDataLength <= size) + { + EnableGlobalIRQ(regPrimask); + return -1; + } + for (int i = 0; i < (int)size; i++) + { + s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i]; + if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize) + { + s_debugConsoleState.writeRingBuffer.ringHead = 0U; + } + } + + status = (status_t)kStatus_SerialManager_Success; + + if (txBusy == 0) + { + if (s_debugConsoleState.writeRingBuffer.ringHead > s_debugConsoleState.writeRingBuffer.ringTail) + { + sendDataLength = + s_debugConsoleState.writeRingBuffer.ringHead - s_debugConsoleState.writeRingBuffer.ringTail; + } + else + { + sendDataLength = + s_debugConsoleState.writeRingBuffer.ringBufferSize - s_debugConsoleState.writeRingBuffer.ringTail; + } + + status = (status_t)SerialManager_WriteNonBlocking( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + &s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringTail], + sendDataLength); + } + EnableGlobalIRQ(regPrimask); +#else + status = (status_t)SerialManager_WriteBlocking( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); +#endif + return (((status_t)kStatus_Success == status) ? (int)size : -1); +} + +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + status_t status = kStatus_SerialManager_Error; + uint32_t sendDataLength; + uint32_t totalLength = size; + int sentLength; +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ +#else + status_t status = kStatus_SerialManager_Error; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + + assert(NULL != ch); + assert(0 != size); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + do + { + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U; + + if (sendDataLength > 0U) + { + if (sendDataLength > totalLength) + { + sendDataLength = totalLength; + } + + sentLength = DbgConsole_SendData(&ch[size - totalLength], sendDataLength); + if (sentLength > 0) + { + totalLength = totalLength - (uint32_t)sentLength; + } + } + EnableGlobalIRQ(regPrimask); + + if (totalLength != 0U) + { + status = DbgConsole_Flush(); + if ((status_t)kStatus_Success != status) + { + break; + } + } + } while (totalLength != 0U); + return (status_t)(uint32_t)((uint32_t)size - totalLength); +#else + return DbgConsole_SendData(ch, size); +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + +#else + status = (status_t)SerialManager_WriteBlocking( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); + return (((status_t)kStatus_Success == status) ? (int)size : -1); +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +} + +int DbgConsole_ReadLine(uint8_t *buf, size_t size) +{ + int i = 0; + + assert(buf != NULL); + + /* take mutex lock function */ + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); + + do + { + /* recieve one char every time */ + if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i])) + { + /* release mutex lock function */ + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); + i = -1; + break; + } +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(&buf[i], false, &i); +#endif + /* analysis data */ + if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i])) + { + /* End of Line. */ + if (0 == i) + { + buf[i] = (uint8_t)'\0'; + continue; + } + else + { + break; + } + } + i++; + } while (i < (int)size); + + /* get char should not add '\0'*/ + if (i == (int)size) + { + buf[i] = (uint8_t)'\0'; + } + else + { + buf[i + 1] = (uint8_t)'\0'; + } + + /* release mutex lock function */ + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); + + return i; +} + +int DbgConsole_ReadCharacter(uint8_t *ch) +{ + int ret; + + assert(ch); + + /* take mutex lock function */ + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); + /* read one character */ + if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch)) + { + ret = 1; +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(ch, true, NULL); +#endif + } + else + { + ret = -1; + } + + /* release mutex lock function */ + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); + + return ret; +} + +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len) +{ + int i = 0; + + for (i = 0; i < len; i++) + { + if (((uint32_t)*indicator + 1UL) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN) + { + (void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator)); + *indicator = 0; + } + + buf[*indicator] = dbgVal; + (*indicator)++; + } +} +#endif + +/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq) +{ + serial_manager_config_t serialConfig; + status_t status = (status_t)kStatus_SerialManager_Error; + +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + serial_port_uart_config_t uartConfig = { + .instance = instance, + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .parityMode = kSerialManager_UartParityDisabled, + .stopBitCount = kSerialManager_UartOneStopBit, + .enableRx = 1, + .enableTx = 1, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serial_port_usb_cdc_config_t usbCdcConfig = { + .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serial_port_swo_config_t swoConfig = { + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .port = instance, + .protocol = kSerialManager_SwoProtocolNrz, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + serial_port_usb_cdc_virtual_config_t usbCdcVirtualConfig = { + .controllerIndex = (serial_port_usb_cdc_virtual_controller_index_t)instance, + }; +#endif + serialConfig.type = device; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0]; + serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN; +#endif + + if (kSerialPort_Uart == device) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + serialConfig.portConfig = &uartConfig; +#else + return status; +#endif + } + else if (kSerialPort_UsbCdc == device) + { +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serialConfig.portConfig = &usbCdcConfig; +#else + return status; +#endif + } + else if (kSerialPort_Swo == device) + { +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serialConfig.portConfig = &swoConfig; +#else + return status; +#endif + } + else if (kSerialPort_UsbCdcVirtual == device) + { +#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) + serialConfig.portConfig = &usbCdcVirtualConfig; +#else + return status; +#endif + } + else + { + return status; + } + + (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState)); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; +#endif + + s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0]; + status = (status_t)SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig); + + assert(kStatus_SerialManager_Success == status); + + DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore); +#endif + + { + status = (status_t)SerialManager_OpenWriteHandle( + s_debugConsoleState.serialHandle, ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallTxCallback(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + DbgConsole_SerialManagerTxCallback, &s_debugConsoleState); +#endif + } + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + status = (status_t)SerialManager_OpenReadHandle( + s_debugConsoleState.serialHandle, ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallRxCallback(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), + DbgConsole_SerialManagerRxCallback, &s_debugConsoleState); +#endif + } +#endif + + g_serialHandle = s_debugConsoleState.serialHandle; + + return kStatus_Success; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Deinit(void) +{ + { + if (s_debugConsoleState.serialHandle != NULL) + { + (void)SerialManager_CloseWriteHandle( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + } + } +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + if (s_debugConsoleState.serialHandle != NULL) + { + (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + } + } +#endif + return (status_t)kStatus_Success; +} + +#if ((SDK_DEBUGCONSOLE > 0U) || \ + ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + return (status_t)kStatus_Fail; + } + +#else + + while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + if (0U == IS_RUNNING_IN_ISR()) + { + if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState()) + { + vTaskDelay(1); + } + } + else + { + return (status_t)kStatus_Fail; + } +#endif + } + +#endif + +#endif + return (status_t)kStatus_Success; +} +#endif + +#if SDK_DEBUGCONSOLE +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Printf(const char *formatString, ...) +{ + va_list ap; + int logLength = 0, dbgResult = 0; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'}; + + if (NULL == g_serialHandle) + { + return 0; + } + + va_start(ap, formatString); + /* format print log first */ + logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback); + /* print log */ + dbgResult = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength); + + va_end(ap); + + return dbgResult; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Putchar(int ch) +{ + /* print char */ + return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U); +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Scanf(char *formatString, ...) +{ + va_list ap; + int formatResult; + char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'}; + + /* scanf log */ + (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN); + /* get va_list */ + va_start(ap, formatString); + /* format scanf log */ + formatResult = StrFormatScanf(scanfBuf, formatString, ap); + + va_end(ap); + + return formatResult; +} + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +status_t DbgConsole_TryGetchar(char *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + uint32_t length = 0; + status_t status = (status_t)kStatus_Fail; + + assert(ch); + + /* take mutex lock function */ + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); + + if (kStatus_SerialManager_Success == + SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1, + &length)) + { + if (length != 0U) + { +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL); +#endif + status = (status_t)kStatus_Success; + } + } + /* release mutex lock function */ + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); + return status; +#else + return (status_t)kStatus_Fail; +#endif +} +#endif + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Getchar(void) +{ + uint8_t ch = 0U; + + /* Get char */ + (void)DbgConsole_ReadCharacter(&ch); + + return (int)ch; +} + +#endif /* SDK_DEBUGCONSOLE */ + +/*************Code to support toolchain's printf, scanf *******************************/ +/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ +#if (defined(__ICCARM__)) +#if defined(SDK_DEBUGCONSOLE_UART) +#pragma weak __write +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + if (buffer == 0) + { + /* + * This means that we should flush internal buffers. Since we don't we just return. + * (Remember, "handle" == -1 means that all handles should be flushed.) + */ + return 0; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return ((size_t)-1); + } + + /* Send data. */ + DbgConsole_SendDataReliable((uint8_t *)buffer, size); + + return size; +} + +#pragma weak __read +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + uint8_t ch = 0U; + int actualSize = 0U; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return ((size_t)-1); + } + + /* Receive data.*/ + for (; size > 0; size--) + { + DbgConsole_ReadCharacter(&ch); + if (ch == 0) + { + break; + } + + *buffer++ = ch; + actualSize++; + } + + return actualSize; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* support LPC Xpresso with RedLib */ +#elif (defined(__REDLIB__)) + +#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)) +int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) +{ + if (buffer == 0) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + DbgConsole_SendDataReliable((uint8_t *)buffer, size); + + return 0; +} + +int __attribute__((weak)) __sys_readc(void) +{ + char tmp; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&tmp); + + return tmp; +} +#endif + +/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if defined(SDK_DEBUGCONSOLE_UART) +#if defined(__CC_ARM) +struct __FILE +{ + int handle; + /* + * Whatever you require here. If the only file you are using is standard output using printf() for debugging, + * no file handling is required. + */ +}; +#endif + +/* FILE is typedef in stdio.h. */ +#pragma weak __stdout +#pragma weak __stdin +FILE __stdout; +FILE __stdin; + +#pragma weak fputc +int fputc(int ch, FILE *f) +{ + /* Send data. */ + return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1); +} + +#pragma weak fgetc +int fgetc(FILE *f) +{ + char ch; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&ch); + + return ch; +} + +/* + * Terminate the program, passing a return code back to the user. + * This function may not return. + */ +void _sys_exit(int returncode) +{ + while (1) + { + } +} + +/* + * Writes a character to the output channel. This function is used + * for last-resort error message output. + */ +void _ttywrch(int ch) +{ + char ench = ch; + DbgConsole_SendDataReliable((uint8_t *)(&ench), 1); +} + +char *_sys_command_string(char *cmd, int len) +{ + return (cmd); +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ +#elif (defined(__GNUC__)) + +#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ + (defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)))) +int __attribute__((weak)) _write(int handle, char *buffer, int size); +int __attribute__((weak)) _write(int handle, char *buffer, int size) +{ + if (buffer == NULL) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size); + + return size; +} + +int __attribute__((weak)) _read(int handle, char *buffer, int size); +int __attribute__((weak)) _read(int handle, char *buffer, int size) +{ + uint8_t ch = 0U; + int actualSize = 0; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Receive data. */ + for (; size > 0; size--) + { + if (DbgConsole_ReadCharacter(&ch) < 0) + { + break; + } + + *buffer++ = (char)ch; + actualSize++; + + if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r')) + { + break; + } + } + + return (actualSize > 0) ? actualSize : -1; +} +#endif + +#endif /* __ICCARM__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_debug_console.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_debug_console.h new file mode 100644 index 000000000..500bb7bf4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_debug_console.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Debug console shall provide input and output functions to scan and print formatted data. + * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" + * - [flags] :'-', '+', '#', ' ', '0' + * - [width]: number (0,1...) + * - [.precision]: number (0,1...) + * - [length]: do not support + * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' + * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" + * - [*]: is supported. + * - [width]: number (0,1...) + * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') + * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' + */ + +#ifndef _FSL_DEBUGCONSOLE_H_ +#define _FSL_DEBUGCONSOLE_H_ + +#include "fsl_common.h" +#include "serial_manager.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +extern serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */ +#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */ +#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */ +#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */ + +/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support + * to be redefined in project setting. + */ +#ifndef SDK_DEBUGCONSOLE +#define SDK_DEBUGCONSOLE 1U +#endif + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. */ +#ifndef SDK_DEBUGCONSOLE_UART +/* mcux will handle this macro, not define it here */ +#if (!defined(__MCUXPRESSO)) +#define SDK_DEBUGCONSOLE_UART +#endif +#endif + +#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) +#include +#endif + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. + * + * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf. + * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf. + * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function. + */ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */ +#define PRINTF +#define SCANF +#define PUTCHAR +#define GETCHAR +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */ +#define PRINTF DbgConsole_Printf +#define SCANF DbgConsole_Scanf +#define PUTCHAR DbgConsole_Putchar +#define GETCHAR DbgConsole_Getchar +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \ + */ +#define PRINTF printf +#define SCANF scanf +#define PUTCHAR putchar +#define GETCHAR getchar +#endif /* SDK_DEBUGCONSOLE */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + +/*! + * @brief Initializes the peripheral used for debug messages. + * + * Call this function to enable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * After this function has returned, stdout and stdin are connected to the selected peripheral. + * + * @param instance The instance of the module. + * @param baudRate The desired baud rate in bits per second. + * @param device Low level device type for the debug console, can be one of the following. + * @arg kSerialPort_Uart, + * @arg kSerialPort_UsbCdc + * @arg kSerialPort_UsbCdcVirtual. + * @param clkSrcFreq Frequency of peripheral source clock. + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq); + +/*! + * @brief De-initializes the peripheral used for debug messages. + * + * Call this function to disable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_Deinit(void); + +#if SDK_DEBUGCONSOLE +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param formatString Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Printf(const char *formatString, ...); + +/*! + * @brief Writes a character to stdout. + * + * Call this function to write a character to stdout. + * + * @param ch Character to be written. + * @return Returns the character written. + */ +int DbgConsole_Putchar(int ch); + +/*! + * @brief Reads formatted data from the standard input stream. + * + * Call this function to read formatted data from the standard input stream. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @param formatString Format control string. + * @return Returns the number of fields successfully converted and assigned. + */ +int DbgConsole_Scanf(char *formatString, ...); + +/*! + * @brief Reads a character from standard input. + * + * Call this function to read a character from standard input. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @return Returns the character read. + */ +int DbgConsole_Getchar(void); + +/*! + * @brief Debug console flush. + * + * Call this function to wait the tx buffer empty. + * If interrupt transfer is using, make sure the global IRQ is enable before call this function + * This function should be called when + * 1, before enter power down mode + * 2, log is required to print to terminal immediately + * @return Indicates whether wait idle was successful or not. + */ +status_t DbgConsole_Flush(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief Debug console try to get char + * This function provides a API which will not block current task, if character is + * available return it, otherwise return fail. + * @param ch the address of char to receive + * @return Indicates get char was successful or not. + */ +status_t DbgConsole_TryGetchar(char *ch); +#endif + +#endif /* SDK_DEBUGCONSOLE */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_debug_console_conf.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_debug_console_conf.h new file mode 100644 index 000000000..4c36a7dd8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_debug_console_conf.h @@ -0,0 +1,158 @@ +/* + * Copyright 2017 - 2019 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ +#define _FSL_DEBUG_CONSOLE_CONF_H_ + +/****************Debug console configuration********************/ + +/*! @brief If Non-blocking mode is needed, please define it at project setting, + * otherwise blocking mode is the default transfer mode. + * Warning: If you want to use non-blocking transfer,please make sure the corresponding + * IO interrupt is enable, otherwise there is no output. + * And non-blocking is combine with buffer, no matter bare-metal or rtos. + * Below shows how to configure in your project if you want to use non-blocking mode. + * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols". + * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define". + * For ARMGCC, open CmakeLists.txt and add the following lines, + * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target. + * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target. + * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C + * Complier->Preprocessor". + * + */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically + * when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed , because the log will not be + * buffered if the buffer is full, and the print will return immediately with -1. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN +#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) +#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ + +/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN +#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U) +#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ + +/*!@ brief Whether enable the reliable TX function + * If the macro is zero, the reliable TX function of the debug console is disabled. + * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full. + */ +#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE +#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U) +#endif /* DEBUG_CONSOLE_RX_ENABLE */ + +#else +#define DEBUG_CONSOLE_TRANSFER_BLOCKING +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/*!@ brief Whether enable the RX function + * If the macro is zero, the receive function of the debug console is disabled. + */ +#ifndef DEBUG_CONSOLE_RX_ENABLE +#define DEBUG_CONSOLE_RX_ENABLE (1U) +#endif /* DEBUG_CONSOLE_RX_ENABLE */ + +/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log + * length can not bigger than this value. + * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if + * the buffer is too big and current task stack size not big enough. + */ +#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN +#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) +#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ + +/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log + * length can not bigger than this value. + * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. + */ +#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN +#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) +#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ + +/*! @brief Debug console synchronization + * User should not change these macro for synchronization mode, but add the + * corresponding synchronization mechanism per different software environment. + * Such as, if another RTOS is used, + * add: + * #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 + * in this configuration file and implement the synchronization in fsl.log.c. + */ +/*! @brief synchronization for baremetal software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 +/*! @brief synchronization for freertos software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 + +/*! @brief RTOS synchronization mechanism disable + * If not defined, default is enable, to avoid multitask log print mess. + * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c + * If synchronization is disabled, log maybe messed on terminal. + */ +#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#ifdef FSL_RTOS_FREE_RTOS +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* FSL_RTOS_FREE_RTOS */ +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ + +/*! @brief echo function support + * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO + * at your project setting. + */ +#ifndef DEBUG_CONSOLE_ENABLE_ECHO +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 +#else +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 +#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ + +/*********************************************************************/ + +/***************Debug console other configuration*********************/ +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ +#ifndef BOARD_USE_VIRTUALCOM +#define BOARD_USE_VIRTUALCOM 0U +#endif +/*******************************************************************/ + +#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_str.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_str.c new file mode 100644 index 000000000..1a49a45e9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_str.c @@ -0,0 +1,1324 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include +#include +#include +#include "fsl_str.h" +#include "fsl_debug_console_conf.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The overflow value.*/ +#ifndef HUGE_VAL +#define HUGE_VAL (99.e99) +#endif /* HUGE_VAL */ + +#if PRINTF_ADVANCED_ENABLE +/*! @brief Specification modifier flags for printf. */ +enum _debugconsole_printf_flag +{ + kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ + kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ + kPRINTF_Space = 0x04U, /*!< Space Flag. */ + kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ + kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ + kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ + kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ + kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ + kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ +}; +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Specification modifier flags for scanf. */ +enum _debugconsole_scanf_flag +{ + kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ + kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ + kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ + kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ + kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ + kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ + kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ + kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ +#if SCANF_ADVANCED_ENABLE + kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ + kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ + kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ + kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ +#endif /*PRINTF_FLOAT_ENABLE */ + kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ +}; + +/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ +#if defined(__CC_ARM) +#pragma diag_suppress 1256 +#endif /* __CC_ARM */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Scanline function which ignores white spaces. + * + * @param[in] s The address of the string pointer to update. + * @return String without white spaces. + */ +static uint32_t ScanIgnoreWhiteSpace(const char **s); + +/*! + * @brief Converts a radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] neg Polarity of the number. + * @param[in] radix The radix to be converted to. + * @param[in] use_caps Used to identify %x/X output format. + + * @return Length of the converted string. + */ +static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps); + +#if PRINTF_FLOAT_ENABLE +/*! + * @brief Converts a floating radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] radix The radix to be converted to. + * @param[in] precision_width Specify the precision width. + + * @return Length of the converted string. + */ +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width); +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! + * + */ +double modf(double input_dbl, double *intpart_ptr); + +/*************Code for process formatted data*******************************/ + +static uint32_t ScanIgnoreWhiteSpace(const char **s) +{ + uint8_t count = 0; + uint8_t c; + + c = **s; + while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) + { + count++; + (*s)++; + c = **s; + } + return count; +} + +static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps) +{ +#if PRINTF_ADVANCED_ENABLE + int64_t a; + int64_t b; + int64_t c; + + uint64_t ua; + uint64_t ub; + uint64_t uc; +#else + int32_t a; + int32_t b; + int32_t c; + + uint32_t ua; + uint32_t ub; + uint32_t uc; +#endif /* PRINTF_ADVANCED_ENABLE */ + + int32_t nlen; + char *nstrp; + + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + + if (neg) + { +#if PRINTF_ADVANCED_ENABLE + a = *(int64_t *)nump; +#else + a = *(int32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (a == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (a != 0) + { +#if PRINTF_ADVANCED_ENABLE + b = (int64_t)a / (int64_t)radix; + c = (int64_t)a - ((int64_t)b * (int64_t)radix); + if (c < 0) + { + uc = (uint64_t)c; + c = (int64_t)(~uc) + 1 + '0'; + } +#else + b = a / radix; + c = a - (b * radix); + if (c < 0) + { + uc = (uint32_t)c; + c = (uint32_t)(~uc) + 1 + '0'; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + else + { +#if PRINTF_ADVANCED_ENABLE + ua = *(uint64_t *)nump; +#else + ua = *(uint32_t *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (ua == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (ua != 0) + { +#if PRINTF_ADVANCED_ENABLE + ub = (uint64_t)ua / (uint64_t)radix; + uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix); +#else + ub = ua / (uint32_t)radix; + uc = ua - (ub * (uint32_t)radix); +#endif /* PRINTF_ADVANCED_ENABLE */ + + if (uc < 10) + { + uc = uc + '0'; + } + else + { + uc = uc - 10 + (use_caps ? 'A' : 'a'); + } + ua = ub; + *nstrp++ = (char)uc; + ++nlen; + } + } + return nlen; +} + +#if PRINTF_FLOAT_ENABLE +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width) +{ + int32_t a; + int32_t b; + int32_t c; + int32_t i; + uint32_t uc; + double fa; + double dc; + double fb; + double r; + double fractpart; + double intpart; + + int32_t nlen; + char *nstrp; + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + r = *(double *)nump; + if (!r) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + fractpart = modf((double)r, (double *)&intpart); + /* Process fractional part. */ + for (i = 0; i < precision_width; i++) + { + fractpart *= radix; + } + if (r >= 0) + { + fa = fractpart + (double)0.5; + if (fa >= pow(10, precision_width)) + { + intpart++; + } + } + else + { + fa = fractpart - (double)0.5; + if (fa <= -pow(10, precision_width)) + { + intpart--; + } + } + for (i = 0; i < precision_width; i++) + { + fb = fa / (int32_t)radix; + dc = (fa - (int64_t)fb * (int32_t)radix); + c = (int32_t)dc; + if (c < 0) + { + uc = (uint32_t)c; + c = (int32_t)(~uc) + 1 + '0'; + } + else + { + c = c + '0'; + } + fa = fb; + *nstrp++ = (char)c; + ++nlen; + } + *nstrp++ = (char)'.'; + ++nlen; + a = (int32_t)intpart; + if (a == 0) + { + *nstrp++ = '0'; + ++nlen; + } + else + { + while (a != 0) + { + b = (int32_t)a / (int32_t)radix; + c = (int32_t)a - ((int32_t)b * (int32_t)radix); + if (c < 0) + { + uc = (uint32_t)c; + c = (int32_t)(~uc) + 1 + '0'; + } + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + return nlen; +} +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! + * brief This function outputs its parameters according to a formatted string. + * + * note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * param[in] fmt_ptr Format string for printf. + * param[in] args_ptr Arguments to printf. + * param[in] buf pointer to the buffer + * param cb print callback function pointer + * + * return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb) +{ + /* va_list ap; */ + char *p; + int32_t c; + + char vstr[33]; + char *vstrp = NULL; + int32_t vlen = 0; + + int32_t done; + int32_t count = 0; + + uint32_t field_width; + uint32_t precision_width; + char *sval; + int32_t cval; + bool use_caps; + uint8_t radix = 0; + +#if PRINTF_ADVANCED_ENABLE + uint32_t flags_used; + int32_t schar, dschar; + int64_t ival; + uint64_t uval = 0; + bool valid_precision_width; +#else + int32_t ival; + uint32_t uval = 0; +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_FLOAT_ENABLE + double fval; +#endif /* PRINTF_FLOAT_ENABLE */ + + /* Start parsing apart the format string and display appropriate formats and data. */ + for (p = (char *)fmt; (c = *p) != 0; p++) + { + /* + * All formats begin with a '%' marker. Special chars like + * '\n' or '\t' are normally converted to the appropriate + * character by the __compiler__. Thus, no need for this + * routine to account for the '\' character. + */ + if (c != '%') + { + cb(buf, &count, c, 1); + /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ + continue; + } + + use_caps = true; + +#if PRINTF_ADVANCED_ENABLE + /* First check for specification modifier flags. */ + flags_used = 0; + done = false; + while (!done) + { + switch (*++p) + { + case '-': + flags_used |= kPRINTF_Minus; + break; + case '+': + flags_used |= kPRINTF_Plus; + break; + case ' ': + flags_used |= kPRINTF_Space; + break; + case '0': + flags_used |= kPRINTF_Zero; + break; + case '#': + flags_used |= kPRINTF_Pound; + break; + default: + /* We've gone one char too far. */ + --p; + done = true; + break; + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + + /* Next check for minimum field width. */ + field_width = 0; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + field_width = (field_width * 10) + (c - '0'); + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + field_width = (uint32_t)va_arg(ap, uint32_t); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + /* Next check for the width and precision field separator. */ + precision_width = 6; +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = false; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (*++p == '.') + { + /* Must get precision field width, if present. */ + precision_width = 0; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + precision_width = (precision_width * 10) + (c - '0'); +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = true; +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + precision_width = (uint32_t)va_arg(ap, uint32_t); + valid_precision_width = true; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + } + else + { + /* We've gone one char too far. */ + --p; + } +#if PRINTF_ADVANCED_ENABLE + /* + * Check for the length modifier. + */ + switch (/* c = */ *++p) + { + case 'h': + if (*++p != 'h') + { + flags_used |= kPRINTF_LengthShortInt; + --p; + } + else + { + flags_used |= kPRINTF_LengthChar; + } + break; + case 'l': + if (*++p != 'l') + { + flags_used |= kPRINTF_LengthLongInt; + --p; + } + else + { + flags_used |= kPRINTF_LengthLongLongInt; + } + break; + default: + /* we've gone one char too far */ + --p; + break; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + /* Now we're ready to examine the format. */ + c = *++p; + { + if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') || + (c == 'b') || (c == 'p') || (c == 'u')) + { + if ((c == 'd') || (c == 'i')) + { +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + ival = (int64_t)va_arg(ap, int64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + ival = (int32_t)va_arg(ap, int32_t); + } + vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (ival < 0) + { + schar = '-'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Plus) + { + schar = '+'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Space) + { + schar = ' '; + ++vlen; + } + else + { + schar = 0; + } + } + } + dschar = false; + /* Do the ZERO pad. */ + if (flags_used & kPRINTF_Zero) + { + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + } + } + /* The string was built in reverse order, now display in correct order. */ + if ((!dschar) && schar) + { + cb(buf, &count, schar, 1); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + +#if PRINTF_FLOAT_ENABLE + if ((c == 'f') || (c == 'F')) + { + fval = (double)va_arg(ap, double); + vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + if (fval < 0) + { + schar = '-'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Plus) + { + schar = '+'; + ++vlen; + } + else + { + if (flags_used & kPRINTF_Space) + { + schar = ' '; + ++vlen; + } + else + { + schar = 0; + } + } + } + dschar = false; + if (flags_used & kPRINTF_Zero) + { + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + if (schar) + { + cb(buf, &count, schar, 1); + } + dschar = true; + } + } + if ((!dschar) && schar) + { + cb(buf, &count, schar, 1); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#endif /* PRINTF_FLOAT_ENABLE */ + if ((c == 'X') || (c == 'x')) + { + if (c == 'x') + { + use_caps = false; + } +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + dschar = false; + if (flags_used & kPRINTF_Zero) + { + if (flags_used & kPRINTF_Pound) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + dschar = true; + } + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + if (flags_used & kPRINTF_Pound) + { + vlen += 2; + } + cb(buf, &count, ' ', field_width - vlen); + if (flags_used & kPRINTF_Pound) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + dschar = true; + } + } + } + + if ((flags_used & kPRINTF_Pound) && (!dschar)) + { + cb(buf, &count, '0', 1); + cb(buf, &count, (use_caps ? 'X' : 'x'), 1); + vlen += 2; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) + { +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_LengthLongLongInt) + { + uval = (uint64_t)va_arg(ap, uint64_t); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (uint32_t)va_arg(ap, uint32_t); + } + + if (c == 'o') + { + radix = 8; + } + else if (c == 'b') + { + radix = 2; + } + else if (c == 'p') + { + radix = 16; + } + else + { + radix = 10; + } + + vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Zero) + { + cb(buf, &count, '0', field_width - vlen); + vlen = field_width; + } + else + { + if (!(flags_used & kPRINTF_Minus)) + { + cb(buf, &count, ' ', field_width - vlen); + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if !PRINTF_ADVANCED_ENABLE + cb(buf, &count, ' ', field_width - vlen); +#endif /* !PRINTF_ADVANCED_ENABLE */ + if (vstrp != NULL) + { + while (*vstrp) + { + cb(buf, &count, *vstrp--, 1); + } + } +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Minus) + { + cb(buf, &count, ' ', field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + else if (c == 'c') + { + cval = (char)va_arg(ap, uint32_t); + cb(buf, &count, cval, 1); + } + else if (c == 's') + { + sval = (char *)va_arg(ap, char *); + if (sval) + { +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + vlen = precision_width; + } + else + { + vlen = strlen(sval); + } +#else + vlen = strlen(sval); +#endif /* PRINTF_ADVANCED_ENABLE */ +#if PRINTF_ADVANCED_ENABLE + if (!(flags_used & kPRINTF_Minus)) +#endif /* PRINTF_ADVANCED_ENABLE */ + { + cb(buf, &count, ' ', field_width - vlen); + } + +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + while ((*sval) && (vlen > 0)) + { + cb(buf, &count, *sval++, 1); + vlen--; + } + /* In case that vlen sval is shorter than vlen */ + vlen = precision_width - vlen; + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + while (*sval) + { + cb(buf, &count, *sval++, 1); + } +#if PRINTF_ADVANCED_ENABLE + } +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE + if (flags_used & kPRINTF_Minus) + { + cb(buf, &count, ' ', field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + } + else + { + cb(buf, &count, c, 1); + } + } + } + + return count; +} + +/*! + * brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * param[in] line_ptr The input line of ASCII data. + * param[in] format Format first points to the format string. + * param[in] args_ptr The list of parameters. + * + * return Number of input items converted and assigned. + * retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) +{ + uint8_t base; + int8_t neg; + /* Identifier for the format string. */ + char *c = format; + char temp; + char *buf; + /* Flag telling the conversion specification. */ + uint32_t flag = 0; + /* Filed width for the matching input streams. */ + uint32_t field_width; + /* How many arguments are assigned except the suppress. */ + uint32_t nassigned = 0; + /* How many characters are read from the input streams. */ + uint32_t n_decode = 0; + + int32_t val; + + const char *s; + /* Identifier for the input string. */ + const char *p = line_ptr; + +#if SCANF_FLOAT_ENABLE + double fnum = 0.0; +#endif /* SCANF_FLOAT_ENABLE */ + /* Return EOF error before any conversion. */ + if (*p == '\0') + { + return -1; + } + + /* Decode directives. */ + while ((*c) && (*p)) + { + /* Ignore all white-spaces in the format strings. */ + if (ScanIgnoreWhiteSpace((const char **)&c)) + { + n_decode += ScanIgnoreWhiteSpace(&p); + } + else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%'))) + { + /* Ordinary characters. */ + c++; + if (*p == *c) + { + n_decode++; + p++; + c++; + } + else + { + /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. + * However, it is deserted now. */ + break; + } + } + else + { + /* convernsion specification */ + c++; + /* Reset. */ + flag = 0; + field_width = 0; + base = 0; + + /* Loop to get full conversion specification. */ + while ((*c) && (!(flag & kSCANF_DestMask))) + { + switch (*c) + { +#if SCANF_ADVANCED_ENABLE + case '*': + if (flag & kSCANF_Suppress) + { + /* Match failure. */ + return nassigned; + } + flag |= kSCANF_Suppress; + c++; + break; + case 'h': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + + if (c[1] == 'h') + { + flag |= kSCANF_LengthChar; + c++; + } + else + { + flag |= kSCANF_LengthShortInt; + } + c++; + break; + case 'l': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + + if (c[1] == 'l') + { + flag |= kSCANF_LengthLongLongInt; + c++; + } + else + { + flag |= kSCANF_LengthLongInt; + } + c++; + break; +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + case 'L': + if (flag & kSCANF_LengthMask) + { + /* Match failure. */ + return nassigned; + } + flag |= kSCANF_LengthLongLongDouble; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if (field_width) + { + /* Match failure. */ + return nassigned; + } + do + { + field_width = field_width * 10 + *c - '0'; + c++; + } while ((*c >= '0') && (*c <= '9')); + break; + case 'd': + base = 10; + flag |= kSCANF_TypeSinged; + flag |= kSCANF_DestInt; + c++; + break; + case 'u': + base = 10; + flag |= kSCANF_DestInt; + c++; + break; + case 'o': + base = 8; + flag |= kSCANF_DestInt; + c++; + break; + case 'x': + case 'X': + base = 16; + flag |= kSCANF_DestInt; + c++; + break; + case 'i': + base = 0; + flag |= kSCANF_DestInt; + c++; + break; +#if SCANF_FLOAT_ENABLE + case 'a': + case 'A': + case 'e': + case 'E': + case 'f': + case 'F': + case 'g': + case 'G': + flag |= kSCANF_DestFloat; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case 'c': + flag |= kSCANF_DestChar; + if (!field_width) + { + field_width = 1; + } + c++; + break; + case 's': + flag |= kSCANF_DestString; + c++; + break; + default: + return nassigned; + } + } + + if (!(flag & kSCANF_DestMask)) + { + /* Format strings are exhausted. */ + return nassigned; + } + + if (!field_width) + { + /* Large than length of a line. */ + field_width = 99; + } + + /* Matching strings in input streams and assign to argument. */ + switch (flag & kSCANF_DestMask) + { + case kSCANF_DestChar: + s = (const char *)p; + buf = va_arg(args_ptr, char *); + while ((field_width--) && (*p)) + { + if (!(flag & kSCANF_Suppress)) + { + *buf++ = *p++; + } + else + { + p++; + } + n_decode++; + } + + if ((!(flag & kSCANF_Suppress)) && (s != p)) + { + nassigned++; + } + break; + case kSCANF_DestString: + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + buf = va_arg(args_ptr, char *); + while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') && + (*p != '\r') && (*p != '\v') && (*p != '\f')) + { + if (flag & kSCANF_Suppress) + { + p++; + } + else + { + *buf++ = *p++; + } + n_decode++; + } + + if ((!(flag & kSCANF_Suppress)) && (s != p)) + { + /* Add NULL to end of string. */ + *buf = '\0'; + nassigned++; + } + break; + case kSCANF_DestInt: + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + val = 0; + if ((base == 0) || (base == 16)) + { + if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) + { + base = 16; + if (field_width >= 1) + { + p += 2; + n_decode += 2; + field_width -= 2; + } + } + } + + if (base == 0) + { + if (s[0] == '0') + { + base = 8; + } + else + { + base = 10; + } + } + + neg = 1; + switch (*p) + { + case '-': + neg = -1; + n_decode++; + p++; + field_width--; + break; + case '+': + neg = 1; + n_decode++; + p++; + field_width--; + break; + default: + break; + } + + while ((*p) && (field_width--)) + { + if ((*p <= '9') && (*p >= '0')) + { + temp = *p - '0'; + } + else if ((*p <= 'f') && (*p >= 'a')) + { + temp = *p - 'a' + 10; + } + else if ((*p <= 'F') && (*p >= 'A')) + { + temp = *p - 'A' + 10; + } + else + { + temp = base; + } + + if (temp >= base) + { + break; + } + else + { + val = base * val + temp; + } + p++; + n_decode++; + } + val *= neg; + if (!(flag & kSCANF_Suppress)) + { +#if SCANF_ADVANCED_ENABLE + switch (flag & kSCANF_LengthMask) + { + case kSCANF_LengthChar: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed char *) = (signed char)val; + } + else + { + *va_arg(args_ptr, unsigned char *) = (unsigned char)val; + } + break; + case kSCANF_LengthShortInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed short *) = (signed short)val; + } + else + { + *va_arg(args_ptr, unsigned short *) = (unsigned short)val; + } + break; + case kSCANF_LengthLongInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed long int *) = (signed long int)val; + } + else + { + *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val; + } + break; + case kSCANF_LengthLongLongInt: + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed long long int *) = (signed long long int)val; + } + else + { + *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val; + } + break; + default: + /* The default type is the type int. */ + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } + break; + } +#else + /* The default type is the type int. */ + if (flag & kSCANF_TypeSinged) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } +#endif /* SCANF_ADVANCED_ENABLE */ + nassigned++; + } + break; +#if SCANF_FLOAT_ENABLE + case kSCANF_DestFloat: + n_decode += ScanIgnoreWhiteSpace(&p); + fnum = strtod(p, (char **)&s); + + if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL)) + { + break; + } + + n_decode += (int)(s) - (int)(p); + p = s; + if (!(flag & kSCANF_Suppress)) + { + if (flag & kSCANF_LengthLongLongDouble) + { + *va_arg(args_ptr, double *) = fnum; + } + else + { + *va_arg(args_ptr, float *) = (float)fnum; + } + nassigned++; + } + break; +#endif /* SCANF_FLOAT_ENABLE */ + default: + return nassigned; + } + } + } + return nassigned; +} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_str.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_str.h new file mode 100644 index 000000000..8255aec40 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_GCC_IAR_KEIL/utilities/fsl_str.h @@ -0,0 +1,66 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_STR_H +#define _FSL_STR_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief A function pointer which is used when format printf log. + */ +typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len); + +/*! + * @brief This function outputs its parameters according to a formatted string. + * + * @note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * @param[in] fmt Format string for printf. + * @param[in] ap Arguments to printf. + * @param[in] buf pointer to the buffer + * @param cb print callbck function pointer + * + * @return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb); + +/*! + * @brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * @param[in] line_ptr The input line of ASCII data. + * @param[in] format Format first points to the format string. + * @param[in] args_ptr The list of parameters. + * + * @return Number of input items converted and assigned. + * @retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_STR_H */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.cproject b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.cproject deleted file mode 100644 index 7164d9ef8..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.cproject +++ /dev/null @@ -1,797 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - SDK_2.x_LPCXpresso51U68 - 2.6.0 - middleware.baremetal.LPC51U68;platform.drivers.clock.LPC51U68;device.LPC51U68_CMSIS.LPC51U68;platform.Include_common.LPC51U68;platform.Include_core_cm0plus.LPC51U68;platform.drivers.common.LPC51U68;platform.drivers.power.LPC51U68;platform.drivers.reset.LPC51U68;platform.drivers.flexcomm.LPC51U68;platform.drivers.flexcomm_usart.LPC51U68;platform.drivers.lpc_gpio.LPC51U68;platform.drivers.lpc_iocon.LPC51U68;platform.drivers.pint.LPC51U68;component.serial_manager.LPC51U68;component.lists.LPC51U68;component.serial_manager_uart.LPC51U68;component.usart_adapter.LPC51U68;platform.utilities.assert.LPC51U68;utility.debug_console.LPC51U68;device.LPC51U68_startup.LPC51U68;project_template.lpcxpresso51u68.LPC51U68;platform.drivers.ctimer.LPC51U68; - lpcxpresso51u68 - LPC51U68JBD64 - cm0plus - core0_LPC51U68 - - - <?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_3="NXP" property_4="LPC51U68" property_count="5" version="100300"/> -<infoList vendor="NXP"> -<info chip="LPC51U68" name="LPC51U68"> -<chip> -<name>LPC51U68</name> -<family>LPC51U68</family> -<vendor>NXP</vendor> -<memory can_program="true" id="Flash" is_ro="true" size="256" type="Flash"/> -<memory id="RAM" size="96" type="RAM"/> -<memoryInstance derived_from="Flash" driver="LPC51U6x_256K.cfx" edited="true" id="PROGRAM_FLASH" location="0x0" size="0x40000"/> -<memoryInstance derived_from="RAM" edited="true" id="SRAM_00" location="0x4000000" size="0x8000"/> -<memoryInstance derived_from="RAM" edited="true" id="SRAM0" location="0x20000000" size="0x10000"/> -</chip> -<processor> -<name gcc_name="cortex-m0plus">Cortex-M0+</name> -<family>Cortex-M</family> -</processor> -</info> -</infoList> -</TargetConfig> - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.gitignore b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.gitignore deleted file mode 100644 index 555928331..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.gitignore +++ /dev/null @@ -1,13 +0,0 @@ -# Ignore Xpresso generated files. -/.settings/ -/Debug/ - -# Ignore Keil generated files. -*.uvguix.* -EventRecorderStub.scvd -/Listings/ -/Objects/ - -# Ignore IAR generated files. -/settings/ -/Debug_IAR/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.project b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.project deleted file mode 100644 index 21505b1a4..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.project +++ /dev/null @@ -1,317 +0,0 @@ - - - CORTEX_M0+_LPC51U68_LPCXpresso - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - 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- 6 - - org.eclipse.ui.ide.multiFilter - 1.0-name-matches-true-false-EventRecorderStub.scvd - - - - - - FREERTOS_DEMO_ROOT - $%7BPARENT-2-PROJECT_LOC%7D/Demo - - - FREERTOS_ROOT - $%7BPARENT-2-PROJECT_LOC%7D/Source - - - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.settings/language.settings.xml b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.settings/language.settings.xml deleted file mode 100644 index b9880cafd..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/.settings/language.settings.xml +++ /dev/null @@ -1,25 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/arm_common_tables.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/arm_common_tables.h deleted file mode 100644 index 233f62357..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/arm_common_tables.h +++ /dev/null @@ -1,121 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_common_tables.h - * Description: Extern declaration for common tables - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) -#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) -#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) -#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) -#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) -#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) -#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) -#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/arm_const_structs.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/arm_const_structs.h deleted file mode 100644 index 677073e59..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/arm_const_structs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_const_structs.h - * Description: Constant structs that are initialized for user convenience. - * For example, some can be given as arguments to the arm_cfft_f32() function. - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_armcc.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_armcc.h deleted file mode 100644 index f204e241c..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_armcc.h +++ /dev/null @@ -1,870 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use Arm Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 -#endif - - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ - - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE static __forceinline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return result; -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_armclang.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_armclang.h deleted file mode 100644 index f79b4120d..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_armclang.h +++ /dev/null @@ -1,1877 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for Arm Compiler 5 intrinsics */ -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF); - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF); - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF); - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ (uint8_t)__builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_compiler.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_compiler.h deleted file mode 100644 index 79a2cac36..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_compiler.h +++ /dev/null @@ -1,266 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_gcc.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_gcc.h deleted file mode 100644 index a99a35927..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_gcc.h +++ /dev/null @@ -1,2088 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.0.3 - * @date 16. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ (uint8_t)__builtin_clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ - __extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_iccarm.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_iccarm.h deleted file mode 100644 index 7b3f7f768..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_iccarm.h +++ /dev/null @@ -1,913 +0,0 @@ -/**************************************************************************//** - * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.5 - * @date 10. January 2018 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2018 IAR Systems -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ - - -#ifndef __CMSIS_ICCARM_H__ -#define __CMSIS_ICCARM_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if __ICCARM_V8 - #define __NO_RETURN __attribute__((__noreturn__)) - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #define __RESTRICT restrict -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#endif /* __CMSIS_ICCARM_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_version.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_version.h deleted file mode 100644 index ae3f2e33d..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/core_cm0plus.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/core_cm0plus.h deleted file mode 100644 index 8fd78500c..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CMSIS/core_cm0plus.h +++ /dev/null @@ -1,1023 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0+ */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0+ */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; - -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CORTEX_M0+_LPC51U68_IAR.ewd b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CORTEX_M0+_LPC51U68_IAR.ewd deleted file mode 100644 index a11dc5906..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CORTEX_M0+_LPC51U68_IAR.ewd +++ /dev/null @@ -1,2974 +0,0 @@ - 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- - $PROJ_DIR$\utilities\fsl_debug_console_conf.h - - - $PROJ_DIR$\utilities\fsl_str.c - - - $PROJ_DIR$\utilities\fsl_str.h - - - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CORTEX_M0+_LPC51U68_IAR.eww b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CORTEX_M0+_LPC51U68_IAR.eww deleted file mode 100644 index 933340ba7..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CORTEX_M0+_LPC51U68_IAR.eww +++ /dev/null @@ -1,7 +0,0 @@ - - - - $WS_DIR$\CORTEX_M0+_LPC51U68_IAR.ewp - - - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CORTEX_M0+_LPC51U68_Keil.uvoptx b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CORTEX_M0+_LPC51U68_Keil.uvoptx deleted file mode 100644 index abb0d2d3d..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/CORTEX_M0+_LPC51U68_Keil.uvoptx +++ /dev/null @@ -1,1551 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - CORTEX_M0+_LPC51U68_Keil - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 8 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 3 - - - - - - - - - - - BIN\CMSIS_AGDI.dll - - - - 0 - ARMRTXEVENTFLAGS - -L70 -Z18 -C0 -M0 -T1 - - - 0 - DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - CMSIS_AGDI - -X"" -O206 -S8 -C0 -P01 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0LPC51U68_256.FLM -FS00 -FL040000 -FP0($$Device:LPC51U68JBD64$arm\LPC51U68_256.FLM) - - - 0 - DLGUARM - - - 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1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\serial_manager\serial_port_uart.c - - - serial_port_uart.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\serial_manager\serial_port_uart.h - - - - - componnet-uart - - - uart.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\uart\uart.h - - - usart_adapter.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\component\uart\usart_adapter.c - - - - - device - - - fsl_device_registers.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\device\fsl_device_registers.h - - - LPC51U68.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\device\LPC51U68.h - - - LPC51U68_features.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\device\LPC51U68_features.h - - - system_LPC51U68.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\device\system_LPC51U68.c - - - system_LPC51U68.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\device\system_LPC51U68.h - - - - - drivers - - - fsl_clock.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_clock.c - - - fsl_clock.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_clock.h - - - fsl_common.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_common.c - - - fsl_common.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_common.h - - - fsl_ctimer.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_ctimer.c - - - fsl_ctimer.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_ctimer.h - - - fsl_flexcomm.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_flexcomm.c - - - fsl_flexcomm.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_flexcomm.h - - - fsl_gpio.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_gpio.c - - - fsl_gpio.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_gpio.h - - - fsl_iocon.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_iocon.h - - - fsl_pint.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_pint.c - - - fsl_pint.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_pint.h - - - fsl_power.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_power.c - - - fsl_power.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_power.h - - - fsl_reset.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_reset.c - - - fsl_reset.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_reset.h - - - fsl_usart.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_usart.c - - - fsl_usart.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\drivers\fsl_usart.h - - - - - startup - - - startup_LPC51U68.s - 2 - .\Keil_specific\startup_LPC51U68.s - - - - - utilities - - - fsl_assert.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_assert.c - - - fsl_debug_console.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_debug_console.c - - - fsl_debug_console.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_debug_console.h - - - fsl_debug_console_conf.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_debug_console_conf.h - - - fsl_str.c - 1 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_str.c - - - fsl_str.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\utilities\fsl_str.h - - - - - CMSIS - - - arm_common_tables.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\arm_common_tables.h - - - arm_const_structs.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\arm_const_structs.h - - - arm_math.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\arm_math.h - - - cmsis_armcc.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_armcc.h - - - cmsis_armclang.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_armclang.h - - - cmsis_compiler.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_compiler.h - - - cmsis_gcc.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_gcc.h - - - cmsis_iccarm.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_iccarm.h - - - cmsis_version.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\cmsis_version.h - - - core_cm0plus.h - 5 - ..\CORTEX_M0+_LPC51U68_LPCXpresso\CMSIS\core_cm0plus.h - - - - - FreeRTOS_Source - - - croutine.c - 1 - ..\..\Source\croutine.c - - - event_groups.c - 1 - ..\..\Source\event_groups.c - - - list.c - 1 - ..\..\Source\list.c - - - queue.c - 1 - ..\..\Source\queue.c - - - stream_buffer.c - 1 - ..\..\Source\stream_buffer.c - - - tasks.c - 1 - ..\..\Source\tasks.c - - - timers.c - 1 - ..\..\Source\timers.c - - - atomic.h - 5 - ..\..\Source\include\atomic.h - - - croutine.h - 5 - ..\..\Source\include\croutine.h - - - deprecated_definitions.h - 5 - ..\..\Source\include\deprecated_definitions.h - - - event_groups.h - 5 - ..\..\Source\include\event_groups.h - - - FreeRTOS.h - 5 - ..\..\Source\include\FreeRTOS.h - - - list.h - 5 - ..\..\Source\include\list.h - - - message_buffer.h - 5 - ..\..\Source\include\message_buffer.h - - - mpu_prototypes.h - 5 - ..\..\Source\include\mpu_prototypes.h - - - mpu_wrappers.h - 5 - ..\..\Source\include\mpu_wrappers.h - - - portable.h - 5 - ..\..\Source\include\portable.h - - - projdefs.h - 5 - ..\..\Source\include\projdefs.h - - - queue.h - 5 - ..\..\Source\include\queue.h - - - semphr.h - 5 - ..\..\Source\include\semphr.h - - - stack_macros.h - 5 - ..\..\Source\include\stack_macros.h - - - StackMacros.h - 5 - ..\..\Source\include\StackMacros.h - - - stream_buffer.h - 5 - ..\..\Source\include\stream_buffer.h - - - task.h - 5 - ..\..\Source\include\task.h - - - timers.h - 5 - ..\..\Source\include\timers.h - - - port.c - 1 - ..\..\Source\portable\RVDS\ARM_CM0\port.c - - - portmacro.h - 5 - ..\..\Source\portable\RVDS\ARM_CM0\portmacro.h - - - heap_5.c - 1 - ..\..\Source\portable\MemMang\heap_5.c - - - - - Stadard_Demo_Tasks - - - blocktim.h - 5 - ..\Common\include\blocktim.h - - - countsem.h - 5 - ..\Common\include\countsem.h - - - IntQueue.h - 5 - ..\Common\include\IntQueue.h - - - recmutex.h - 5 - ..\Common\include\recmutex.h - - - blocktim.c - 1 - ..\Common\Minimal\blocktim.c - - - IntQueue.c - 1 - ..\Common\Minimal\IntQueue.c - - - recmutex.c - 1 - ..\Common\Minimal\recmutex.c - - - countsem.c - 1 - ..\Common\Minimal\countsem.c - - - - - libs - - - keil_lib_power.lib - 4 - .\Keil_specific\keil_lib_power.lib - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/RegTest.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/RegTest.c deleted file mode 100644 index 383b8ba82..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/RegTest.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -void vRegTest1Task( void ) __attribute__((naked)); -void vRegTest2Task( void ) __attribute__((naked)); - -void vRegTest1Task( void ) -{ - __asm volatile - ( - ".extern ulRegTest1LoopCounter \n" - " \n" - " /* Fill the core registers with known values. */ \n" - " movs r1, #101 \n" - " movs r2, #102 \n" - " movs r3, #103 \n" - " movs r4, #104 \n" - " movs r5, #105 \n" - " movs r6, #106 \n" - " movs r7, #107 \n" - " movs r0, #108 \n" - " mov r8, r0 \n" - " movs r0, #109 \n" - " mov r9, r0 \n" - " movs r0, #110 \n" - " mov r10, r0 \n" - " movs r0, #111 \n" - " mov r11, r0 \n" - " movs r0, #112 \n" - " mov r12, r0 \n" - " movs r0, #100 \n" - " \n" - "reg1_loop: \n" - " \n" - " cmp r0, #100 \n" - " bne reg1_error_loop \n" - " cmp r1, #101 \n" - " bne reg1_error_loop \n" - " cmp r2, #102 \n" - " bne reg1_error_loop \n" - " cmp r3, #103 \n" - " bne reg1_error_loop \n" - " cmp r4, #104 \n" - " bne reg1_error_loop \n" - " cmp r5, #105 \n" - " bne reg1_error_loop \n" - " cmp r6, #106 \n" - " bne reg1_error_loop \n" - " cmp r7, #107 \n" - " bne reg1_error_loop \n" - " movs r0, #108 \n" - " cmp r8, r0 \n" - " bne reg1_error_loop \n" - " movs r0, #109 \n" - " cmp r9, r0 \n" - " bne reg1_error_loop \n" - " movs r0, #110 \n" - " cmp r10, r0 \n" - " bne reg1_error_loop \n" - " movs r0, #111 \n" - " cmp r11, r0 \n" - " bne reg1_error_loop \n" - " movs r0, #112 \n" - " cmp r12, r0 \n" - " bne reg1_error_loop \n" - " \n" - " /* Everything passed, increment the loop counter. */ \n" - " push { r1 } \n" - " ldr r0, =ulRegTest1LoopCounter \n" - " ldr r1, [r0] \n" - " add r1, r1, #1 \n" - " str r1, [r0] \n" - " pop { r1 } \n" - " \n" - " /* Start again. */ \n" - " movs r0, #100 \n" - " b reg1_loop \n" - " \n" - "reg1_error_loop: \n" - " /* If this line is hit then there was an error in a core register value. \n" - " The loop ensures the loop counter stops incrementing. */ \n" - " b reg1_error_loop \n" - " nop \n" - ); -} -/*-----------------------------------------------------------*/ - -void vRegTest2Task( void ) -{ - __asm volatile - ( - ".extern ulRegTest2LoopCounter \n" - " \n" - " /* Fill the core registers with known values. */ \n" - " movs r1, #1 \n" - " movs r2, #2 \n" - " movs r3, #3 \n" - " movs r4, #4 \n" - " movs r5, #5 \n" - " movs r6, #6 \n" - " movs r7, #7 \n" - " movs r0, #8 \n" - " movs r8, r0 \n" - " movs r0, #9 \n" - " mov r9, r0 \n" - " movs r0, #10 \n" - " mov r10, r0 \n" - " movs r0, #11 \n" - " mov r11, r0 \n" - " movs r0, #12 \n" - " mov r12, r0 \n" - " movs r0, #10 \n" - " \n" - "reg2_loop: \n" - " \n" - " cmp r0, #10 \n" - " bne reg2_error_loop \n" - " cmp r1, #1 \n" - " bne reg2_error_loop \n" - " cmp r2, #2 \n" - " bne reg2_error_loop \n" - " cmp r3, #3 \n" - " bne reg2_error_loop \n" - " cmp r4, #4 \n" - " bne reg2_error_loop \n" - " cmp r5, #5 \n" - " bne reg2_error_loop \n" - " cmp r6, #6 \n" - " bne reg2_error_loop \n" - " cmp r7, #7 \n" - " bne reg2_error_loop \n" - " movs r0, #8 \n" - " cmp r8, r0 \n" - " bne reg2_error_loop \n" - " movs r0, #9 \n" - " cmp r9, r0 \n" - " bne reg2_error_loop \n" - " movs r0, #10 \n" - " cmp r10, r0 \n" - " bne reg2_error_loop \n" - " movs r0, #11 \n" - " cmp r11, r0 \n" - " bne reg2_error_loop \n" - " movs r0, #12 \n" - " cmp r12, r0 \n" - " bne reg2_error_loop \n" - " \n" - " /* Everything passed, increment the loop counter. */ \n" - " push { r1 } \n" - " ldr r0, =ulRegTest2LoopCounter \n" - " ldr r1, [r0] \n" - " add r1, r1, #1 \n" - " str r1, [r0] \n" - " pop { r1 } \n" - " \n" - " /* Start again. */ \n" - " movs r0, #10 \n" - " b reg2_loop \n" - " \n" - "reg2_error_loop: \n" - " /* If this line is hit then there was an error in a core register value. \n" - " The loop ensures the loop counter stops incrementing. */ \n" - " b reg2_error_loop \n" - " nop \n" - ); -} -/*-----------------------------------------------------------*/ - - - - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/compiler_attributes.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/compiler_attributes.h deleted file mode 100644 index 8abf71e3c..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/compiler_attributes.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Placing variable at specified address. */ -#define COMPILER_ATTRIBUTE_PLACE_IN_2ND_MEMORY_BANK __attribute__( ( section( ".freertos_heap_2" ) ) ) diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/semihost_hardfault.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/semihost_hardfault.c deleted file mode 100644 index 7ce5fadb9..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/semihost_hardfault.c +++ /dev/null @@ -1,109 +0,0 @@ -// **************************************************************************** -// semihost_hardfault.c -// - Provides hard fault handler to allow semihosting code not -// to hang application when debugger not connected. -// -// **************************************************************************** -// Copyright 2017-2019 NXP -// All rights reserved. -// -// Software that is described herein is for illustrative purposes only -// which provides customers with programming information regarding the -// NXP Cortex-M based MCUs. This software is supplied "AS IS" without any -// warranties of any kind, and NXP Semiconductors and its licensor disclaim any -// and all warranties, express or implied, including all implied warranties of -// merchantability, fitness for a particular purpose and non-infringement of -// intellectual property rights. NXP Semiconductors assumes no responsibility -// or liability for the use of the software, conveys no license or rights under -// any patent, copyright, mask work right, or any other intellectual property -// rights in or to any products. NXP Semiconductors reserves the right to make -// changes in the software without notification. NXP Semiconductors also makes -// no representation or warranty that such application will be suitable for the -// specified use without further testing or modification. -// -// Permission to use, copy, modify, and distribute this software and its -// documentation is hereby granted, under NXP Semiconductors' and its -// licensor's relevant copyrights in the software, without fee, provided that it -// is used in conjunction with NXP Semiconductors microcontrollers. This -// copyright, permission, and disclaimer notice must appear in all copies of -// this code. -// **************************************************************************** -// -// ===== DESCRIPTION ===== -// -// One of the issues with applications that make use of semihosting operations -// (such as printf calls) is that the code will not execute correctly when the -// debugger is not connected. Generally this will show up with the application -// appearing to just hang. This may include the application running from reset -// or powering up the board (with the application already in FLASH), and also -// as the application failing to continue to execute after a debug session is -// terminated. -// -// The problem here is that the "bottom layer" of the semihosted variants of -// the C library, semihosting is implemented by a "BKPT 0xAB" instruction. -// When the debug tools are not connected, this instruction triggers a hard -// fault - and the default hard fault handler within an application will -// typically just contains an infinite loop - causing the application to -// appear to have hang when no debugger is connected. -// -// The below code provides an example hard fault handler which instead looks -// to see what the instruction that caused the hard fault was - and if it -// was a "BKPT 0xAB", then it instead returns back to the user application. -// -// In most cases this will allow applications containing semihosting -// operations to execute (to some degree) when the debugger is not connected. -// -// == NOTE == -// -// Correct execution of the application containing semihosted operations -// which are vectored onto this hard fault handler cannot be guaranteed. This -// is because the handler may not return data or return codes that the higher -// level C library code or application code expects. This hard fault handler -// is meant as a development aid, and it is not recommended to leave -// semihosted code in a production build of your application! -// -// **************************************************************************** - -// Allow handler to be removed by setting a define (via command line) -#if !defined (__SEMIHOST_HARDFAULT_DISABLE) - -__attribute__((naked)) -void HardFault_Handler(void){ - __asm( ".syntax unified\n" - // Check which stack is in use - "MOVS R0, #4 \n" - "MOV R1, LR \n" - "TST R0, R1 \n" - "BEQ _MSP \n" - "MRS R0, PSP \n" - "B _process \n" - "_MSP: \n" - "MRS R0, MSP \n" - // Load the instruction that triggered hard fault - "_process: \n" - "LDR R1,[R0,#24] \n" - "LDRH R2,[r1] \n" - // Semihosting instruction is "BKPT 0xAB" (0xBEAB) - "LDR R3,=0xBEAB \n" - "CMP R2,R3 \n" - "BEQ _semihost_return \n" - // Wasn't semihosting instruction so enter infinite loop - "B . \n" - // Was semihosting instruction, so adjust location to - // return to by 1 instruction (2 bytes), then exit function - "_semihost_return: \n" - "ADDS R1,#2 \n" - "STR R1,[R0,#24] \n" - // Set a return value from semihosting operation. - // 32 is slightly arbitrary, but appears to allow most - // C Library IO functions sitting on top of semihosting to - // continue to operate to some degree - "MOVS R1,#32 \n" - "STR R1,[ R0,#0 ] \n" // R0 is at location 0 on stack - // Return from hard fault handler to application - "BX LR \n" - ".syntax divided\n") ; -} - -#endif - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/startup_lpc51u68.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/startup_lpc51u68.c deleted file mode 100644 index 8af5b4aa8..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/GCC_specific/startup_lpc51u68.c +++ /dev/null @@ -1,510 +0,0 @@ -//***************************************************************************** -// LPC51U68 startup code for use with MCUXpresso IDE -// -// Version : 020818 -//***************************************************************************** -// -// Copyright 2016-2018 NXP -// -// SPDX-License-Identifier: BSD-3-Clause -//***************************************************************************** - -#if defined (DEBUG) -#pragma GCC push_options -#pragma GCC optimize ("Og") -#endif // (DEBUG) - -#if defined (__cplusplus) -#ifdef __REDLIB__ -#error Redlib does not support C++ -#else -//***************************************************************************** -// -// The entry point for the C++ library startup -// -//***************************************************************************** -extern "C" { - extern void __libc_init_array(void); -} -#endif -#endif - -#define WEAK __attribute__ ((weak)) -#define WEAK_AV __attribute__ ((weak, section(".after_vectors"))) -#define ALIAS(f) __attribute__ ((weak, alias (#f))) - -//***************************************************************************** -#if defined (__cplusplus) -extern "C" { -#endif - -//***************************************************************************** -// Variable to store CRP value in. Will be placed automatically -// by the linker when "Enable Code Read Protect" selected. -// See crp.h header for more information -//***************************************************************************** -//***************************************************************************** -// Declaration of external SystemInit function -//***************************************************************************** -#if defined (__USE_CMSIS) -extern void SystemInit(void); -#endif // (__USE_CMSIS) - -//***************************************************************************** -// Forward declaration of the core exception handlers. -// When the application defines a handler (with the same name), this will -// automatically take precedence over these weak definitions. -// If your application is a C++ one, then any interrupt handlers defined -// in C++ files within in your main application will need to have C linkage -// rather than C++ linkage. To do this, make sure that you are using extern "C" -// { .... } around the interrupt handler within your main application code. -//***************************************************************************** - void ResetISR(void); -WEAK void NMI_Handler(void); -WEAK void HardFault_Handler(void); -WEAK void SVC_Handler(void); -WEAK void PendSV_Handler(void); -WEAK void SysTick_Handler(void); -WEAK void IntDefaultHandler(void); - -//***************************************************************************** -// Forward declaration of the application IRQ handlers. When the application -// defines a handler (with the same name), this will automatically take -// precedence over weak definitions below -//***************************************************************************** -WEAK void WDT_BOD_IRQHandler(void); -WEAK void DMA0_IRQHandler(void); -WEAK void GINT0_IRQHandler(void); -WEAK void GINT1_IRQHandler(void); -WEAK void PIN_INT0_IRQHandler(void); -WEAK void PIN_INT1_IRQHandler(void); -WEAK void PIN_INT2_IRQHandler(void); -WEAK void PIN_INT3_IRQHandler(void); -WEAK void UTICK0_IRQHandler(void); -WEAK void MRT0_IRQHandler(void); -WEAK void CTIMER0_IRQHandler(void); -WEAK void CTIMER1_IRQHandler(void); -WEAK void SCT0_IRQHandler(void); -WEAK void CTIMER3_IRQHandler(void); -WEAK void FLEXCOMM0_IRQHandler(void); -WEAK void FLEXCOMM1_IRQHandler(void); -WEAK void FLEXCOMM2_IRQHandler(void); -WEAK void FLEXCOMM3_IRQHandler(void); -WEAK void FLEXCOMM4_IRQHandler(void); -WEAK void FLEXCOMM5_IRQHandler(void); -WEAK void FLEXCOMM6_IRQHandler(void); -WEAK void FLEXCOMM7_IRQHandler(void); -WEAK void ADC0_SEQA_IRQHandler(void); -WEAK void ADC0_SEQB_IRQHandler(void); -WEAK void ADC0_THCMP_IRQHandler(void); -WEAK void Reserved41_IRQHandler(void); -WEAK void Reserved42_IRQHandler(void); -WEAK void USB0_NEEDCLK_IRQHandler(void); -WEAK void USB0_IRQHandler(void); -WEAK void RTC_IRQHandler(void); - -//***************************************************************************** -// Forward declaration of the driver IRQ handlers. These are aliased -// to the IntDefaultHandler, which is a 'forever' loop. When the driver -// defines a handler (with the same name), this will automatically take -// precedence over these weak definitions -//***************************************************************************** -void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ADC0_SEQA_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ADC0_SEQB_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void ADC0_THCMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved41_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void Reserved42_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler); - -//***************************************************************************** -// The entry point for the application. -// __main() is the entry point for Redlib based applications -// main() is the entry point for Newlib based applications -//***************************************************************************** -#if defined (__REDLIB__) -extern void __main(void); -#endif -extern int main(void); - -//***************************************************************************** -// External declaration for the pointer to the stack top from the Linker Script -//***************************************************************************** -extern void _vStackTop(void); -//***************************************************************************** -// External declaration for LPC MCU vector table checksum from Linker Script -//***************************************************************************** -WEAK extern void __valid_user_code_checksum(); - -//***************************************************************************** -//***************************************************************************** -#if defined (__cplusplus) -} // extern "C" -#endif -//***************************************************************************** -// The vector table. -// This relies on the linker script to place at correct location in memory. -//***************************************************************************** -extern void (* const g_pfnVectors[])(void); -extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); - -__attribute__ ((used, section(".isr_vector"))) -void (* const g_pfnVectors[])(void) = { - // Core Level - CM0P - &_vStackTop, // The initial stack pointer - ResetISR, // The reset handler - NMI_Handler, // The NMI handler - HardFault_Handler, // The hard fault handler - 0, // Reserved - 0, // Reserved - 0, // Reserved - __valid_user_code_checksum, // LPC MCU checksum - 0, // ECRP - 0, // Reserved - 0, // Reserved - SVC_Handler, // SVCall handler - 0, // Reserved - 0, // Reserved - PendSV_Handler, // The PendSV handler - SysTick_Handler, // The SysTick handler - - // Chip Level - LPC51U68 - WDT_BOD_IRQHandler, // 16: Windowed watchdog timer, Brownout detect - DMA0_IRQHandler, // 17: DMA controller - GINT0_IRQHandler, // 18: GPIO group 0 - GINT1_IRQHandler, // 19: GPIO group 1 - PIN_INT0_IRQHandler, // 20: Pin interrupt 0 or pattern match engine slice 0 - PIN_INT1_IRQHandler, // 21: Pin interrupt 1or pattern match engine slice 1 - PIN_INT2_IRQHandler, // 22: Pin interrupt 2 or pattern match engine slice 2 - PIN_INT3_IRQHandler, // 23: Pin interrupt 3 or pattern match engine slice 3 - UTICK0_IRQHandler, // 24: Micro-tick Timer - MRT0_IRQHandler, // 25: Multi-rate timer - CTIMER0_IRQHandler, // 26: Standard counter/timer CTIMER0 - CTIMER1_IRQHandler, // 27: Standard counter/timer CTIMER1 - SCT0_IRQHandler, // 28: SCTimer/PWM - CTIMER3_IRQHandler, // 29: Standard counter/timer CTIMER3 - FLEXCOMM0_IRQHandler, // 30: Flexcomm Interface 0 (USART, SPI, I2C) - FLEXCOMM1_IRQHandler, // 31: Flexcomm Interface 1 (USART, SPI, I2C) - FLEXCOMM2_IRQHandler, // 32: Flexcomm Interface 2 (USART, SPI, I2C) - FLEXCOMM3_IRQHandler, // 33: Flexcomm Interface 3 (USART, SPI, I2C) - FLEXCOMM4_IRQHandler, // 34: Flexcomm Interface 4 (USART, SPI, I2C) - FLEXCOMM5_IRQHandler, // 35: Flexcomm Interface 5 (USART, SPI, I2C) - FLEXCOMM6_IRQHandler, // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S) - FLEXCOMM7_IRQHandler, // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S) - ADC0_SEQA_IRQHandler, // 38: ADC0 sequence A completion. - ADC0_SEQB_IRQHandler, // 39: ADC0 sequence B completion. - ADC0_THCMP_IRQHandler, // 40: ADC0 threshold compare and error. - Reserved41_IRQHandler, // 41: Reserved interrupt - Reserved42_IRQHandler, // 42: Reserved interrupt - USB0_NEEDCLK_IRQHandler, // 43: USB Activity Wake-up Interrupt - USB0_IRQHandler, // 44: USB device - RTC_IRQHandler, // 45: RTC alarm and wake-up interrupts -}; /* End of g_pfnVectors */ - -//***************************************************************************** -// Functions to carry out the initialization of RW and BSS data sections. These -// are written as separate functions rather than being inlined within the -// ResetISR() function in order to cope with MCUs with multiple banks of -// memory. -//***************************************************************************** -__attribute__ ((section(".after_vectors.init_data"))) -void data_init(unsigned int romstart, unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int *pulSrc = (unsigned int*) romstart; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = *pulSrc++; -} - -__attribute__ ((section(".after_vectors.init_bss"))) -void bss_init(unsigned int start, unsigned int len) { - unsigned int *pulDest = (unsigned int*) start; - unsigned int loop; - for (loop = 0; loop < len; loop = loop + 4) - *pulDest++ = 0; -} - -//***************************************************************************** -// The following symbols are constructs generated by the linker, indicating -// the location of various points in the "Global Section Table". This table is -// created by the linker via the Code Red managed linker script mechanism. It -// contains the load address, execution address and length of each RW data -// section and the execution and length of each BSS (zero initialized) section. -//***************************************************************************** -extern unsigned int __data_section_table; -extern unsigned int __data_section_table_end; -extern unsigned int __bss_section_table; -extern unsigned int __bss_section_table_end; - -//***************************************************************************** -// Reset entry point for your code. -// Sets up a simple runtime environment and initializes the C/C++ -// library. -//***************************************************************************** -__attribute__ ((section(".after_vectors.reset"))) -void ResetISR(void) { - - // Disable interrupts - __asm volatile ("cpsid i"); - - // Enable SRAM clock used by Stack - __asm volatile ("LDR R0, =0x40000220\n\t" - "MOV R1, #56\n\t" - "STR R1, [R0]"); - -#if defined (__USE_CMSIS) -// If __USE_CMSIS defined, then call CMSIS SystemInit code - SystemInit(); - -#endif // (__USE_CMSIS) - - // - // Copy the data sections from flash to SRAM. - // - unsigned int LoadAddr, ExeAddr, SectionLen; - unsigned int *SectionTableAddr; - - // Load base address of Global Section Table - SectionTableAddr = &__data_section_table; - - // Copy the data sections from flash to SRAM. - while (SectionTableAddr < &__data_section_table_end) { - LoadAddr = *SectionTableAddr++; - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - data_init(LoadAddr, ExeAddr, SectionLen); - } - - // At this point, SectionTableAddr = &__bss_section_table; - // Zero fill the bss segment - while (SectionTableAddr < &__bss_section_table_end) { - ExeAddr = *SectionTableAddr++; - SectionLen = *SectionTableAddr++; - bss_init(ExeAddr, SectionLen); - } - -#if !defined (__USE_CMSIS) -// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code -// will setup the VTOR register - - // Check to see if we are running the code from a non-zero - // address (eg RAM, external flash), in which case we need - // to modify the VTOR register to tell the CPU that the - // vector table is located at a non-0x0 address. - unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08; - if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) { - *pSCB_VTOR = (unsigned int)g_pfnVectors; - } -#endif // (__USE_CMSIS) - -#if defined (__cplusplus) - // - // Call C++ library initialisation - // - __libc_init_array(); -#endif - - // Reenable interrupts - __asm volatile ("cpsie i"); - -#if defined (__REDLIB__) - // Call the Redlib library, which in turn calls main() - __main(); -#else - main(); -#endif - - // - // main() shouldn't return, but if it does, we'll just enter an infinite loop - // - while (1) { - ; - } -} - -//***************************************************************************** -// Default core exception handlers. Override the ones here by defining your own -// handler routines in your application code. -//***************************************************************************** -WEAK_AV void NMI_Handler(void) -{ while(1) {} -} - -WEAK_AV void HardFault_Handler(void) -{ while(1) {} -} - -WEAK_AV void SVC_Handler(void) -{ while(1) {} -} - -WEAK_AV void PendSV_Handler(void) -{ while(1) {} -} - -WEAK_AV void SysTick_Handler(void) -{ while(1) {} -} - -//***************************************************************************** -// Processor ends up here if an unexpected interrupt occurs or a specific -// handler is not present in the application code. -//***************************************************************************** -WEAK_AV void IntDefaultHandler(void) -{ while(1) {} -} - -//***************************************************************************** -// Default application exception handlers. Override the ones here by defining -// your own handler routines in your application code. These routines call -// driver exception handlers or IntDefaultHandler() if no driver exception -// handler is included. -//***************************************************************************** -WEAK_AV void WDT_BOD_IRQHandler(void) -{ WDT_BOD_DriverIRQHandler(); -} - -WEAK_AV void DMA0_IRQHandler(void) -{ DMA0_DriverIRQHandler(); -} - -WEAK_AV void GINT0_IRQHandler(void) -{ GINT0_DriverIRQHandler(); -} - -WEAK_AV void GINT1_IRQHandler(void) -{ GINT1_DriverIRQHandler(); -} - -WEAK_AV void PIN_INT0_IRQHandler(void) -{ PIN_INT0_DriverIRQHandler(); -} - -WEAK_AV void PIN_INT1_IRQHandler(void) -{ PIN_INT1_DriverIRQHandler(); -} - -WEAK_AV void PIN_INT2_IRQHandler(void) -{ PIN_INT2_DriverIRQHandler(); -} - -WEAK_AV void PIN_INT3_IRQHandler(void) -{ PIN_INT3_DriverIRQHandler(); -} - -WEAK_AV void UTICK0_IRQHandler(void) -{ UTICK0_DriverIRQHandler(); -} - -WEAK_AV void MRT0_IRQHandler(void) -{ MRT0_DriverIRQHandler(); -} - -WEAK_AV void CTIMER0_IRQHandler(void) -{ CTIMER0_DriverIRQHandler(); -} - -WEAK_AV void CTIMER1_IRQHandler(void) -{ CTIMER1_DriverIRQHandler(); -} - -WEAK_AV void SCT0_IRQHandler(void) -{ SCT0_DriverIRQHandler(); -} - -WEAK_AV void CTIMER3_IRQHandler(void) -{ CTIMER3_DriverIRQHandler(); -} - -WEAK_AV void FLEXCOMM0_IRQHandler(void) -{ FLEXCOMM0_DriverIRQHandler(); -} - -WEAK_AV void FLEXCOMM1_IRQHandler(void) -{ FLEXCOMM1_DriverIRQHandler(); -} - -WEAK_AV void FLEXCOMM2_IRQHandler(void) -{ FLEXCOMM2_DriverIRQHandler(); -} - -WEAK_AV void FLEXCOMM3_IRQHandler(void) -{ FLEXCOMM3_DriverIRQHandler(); -} - -WEAK_AV void FLEXCOMM4_IRQHandler(void) -{ FLEXCOMM4_DriverIRQHandler(); -} - -WEAK_AV void FLEXCOMM5_IRQHandler(void) -{ FLEXCOMM5_DriverIRQHandler(); -} - -WEAK_AV void FLEXCOMM6_IRQHandler(void) -{ FLEXCOMM6_DriverIRQHandler(); -} - -WEAK_AV void FLEXCOMM7_IRQHandler(void) -{ FLEXCOMM7_DriverIRQHandler(); -} - -WEAK_AV void ADC0_SEQA_IRQHandler(void) -{ ADC0_SEQA_DriverIRQHandler(); -} - -WEAK_AV void ADC0_SEQB_IRQHandler(void) -{ ADC0_SEQB_DriverIRQHandler(); -} - -WEAK_AV void ADC0_THCMP_IRQHandler(void) -{ ADC0_THCMP_DriverIRQHandler(); -} - -WEAK_AV void Reserved41_IRQHandler(void) -{ Reserved41_DriverIRQHandler(); -} - -WEAK_AV void Reserved42_IRQHandler(void) -{ Reserved42_DriverIRQHandler(); -} - -WEAK_AV void USB0_NEEDCLK_IRQHandler(void) -{ USB0_NEEDCLK_DriverIRQHandler(); -} - -WEAK_AV void USB0_IRQHandler(void) -{ USB0_DriverIRQHandler(); -} - -WEAK_AV void RTC_IRQHandler(void) -{ RTC_DriverIRQHandler(); -} - -//***************************************************************************** - -#if defined (DEBUG) -#pragma GCC pop_options -#endif // (DEBUG) diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/LPC51U68_256.FLM b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/LPC51U68_256.FLM deleted file mode 100644 index 517f0be2e..000000000 Binary files a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/LPC51U68_256.FLM and /dev/null differ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/LPC51U68_flash.icf b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/LPC51U68_flash.icf deleted file mode 100644 index 734015f20..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/LPC51U68_flash.icf +++ /dev/null @@ -1,92 +0,0 @@ -/* -** ################################################################### -** Processors: LPC51U68JBD48 -** LPC51U68JBD64 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 -** Version: rev. 1.0, 2017-12-15 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0400; -} - -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000000DF; - -define symbol m_text_start = 0x000000E0; -define symbol m_text_end = 0x0003FFFF; - -define symbol m_sramx_start = 0x04000000; -define symbol m_sramx_end = 0x04007FFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF - __size_cstack__ - 0x20; - -define symbol m_stack_start = 0x20010000 - __size_cstack__ - 0x20; -define symbol m_stack_end = 0x2000FFFF; - -define symbol __crp_start__ = 0x000002FC; -define symbol __crp_end__ = 0x000002FF; - -define symbol __ram_iap_start__ = 0x2000FFE0; -define symbol __ram_iap_end__ = 0x2000FFFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end] - - mem:[from __crp_start__ to __crp_end__]; -define region DATA_region = mem:[from m_sramx_start to m_sramx_end] - | mem:[from m_data_start to m_data_end]; -define region CSTACK_region = mem:[from m_stack_start to m_stack_end] - - mem:[from __ram_iap_start__ to __ram_iap_end__]; -define region CRP_region = mem:[from __crp_start__ to __crp_end__]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; -place in CRP_region { section .crp }; diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/LPC51U68_ram.icf b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/LPC51U68_ram.icf deleted file mode 100644 index 26f773354..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/LPC51U68_ram.icf +++ /dev/null @@ -1,78 +0,0 @@ -/* -** ################################################################### -** Processors: LPC51U68JBD48 -** LPC51U68JBD64 -** -** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 -** Version: rev. 1.0, 2017-12-15 -** Build: b180801 -** -** Abstract: -** Linker file for the IAR ANSI C/C++ Compiler for ARM -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* Stack and Heap Sizes */ -if (isdefinedsymbol(__stack_size__)) { - define symbol __size_cstack__ = __stack_size__; -} else { - define symbol __size_cstack__ = 0x0400; -} - -if (isdefinedsymbol(__heap_size__)) { - define symbol __size_heap__ = __heap_size__; -} else { - define symbol __size_heap__ = 0x0800; -} - -define symbol m_interrupts_start = 0x04000000; -define symbol m_interrupts_end = 0x040000DF; - -define symbol m_text_start = 0x040000E0; -define symbol m_text_end = 0x04007FFF; - -define symbol m_data_start = 0x20000000; -define symbol m_data_end = 0x2000FFFF - __size_cstack__; - -define symbol m_stack_start = 0x20010000 - __size_cstack__; -define symbol m_stack_end = 0x2000FFFF; - -define memory mem with size = 4G; - -define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end] - | mem:[from m_text_start to m_text_end]; -define region DATA_region = mem:[from m_data_start to m_data_end]; -define region CSTACK_region = mem:[from m_stack_start to m_stack_end]; - -define block CSTACK with alignment = 8, size = __size_cstack__ { }; -define block HEAP with alignment = 8, size = __size_heap__ { }; -define block RW { readwrite }; -define block ZI { zi }; - -initialize by copy { readwrite, section .textrw }; - -if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) -{ - /* Required in a multi-threaded application */ - initialize by copy with packing = none { section __DLIB_PERTHREAD }; -} - -do not initialize { section .noinit }; - -place at address mem: m_interrupts_start { readonly section .intvec }; -place in TEXT_region { readonly }; -place in DATA_region { block RW }; -place in DATA_region { block ZI }; -place in DATA_region { last block HEAP }; -place in CSTACK_region { block CSTACK }; diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/RegTest_IAR.s b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/RegTest_IAR.s deleted file mode 100644 index 54fc1a235..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/RegTest_IAR.s +++ /dev/null @@ -1,207 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* - * "Reg test" tasks - These fill the registers with known values, then check - * that each register maintains its expected value for the lifetime of the - * task. Each task uses a different set of values. The reg test tasks execute - * with a very low priority, so get preempted very frequently. A register - * containing an unexpected value is indicative of an error in the context - * switching mechanism. - */ - - RSEG CODE:CODE(2) - thumb - - - EXTERN ulRegTest1LoopCounter - EXTERN ulRegTest2LoopCounter - - PUBLIC vRegTest1Task - PUBLIC vRegTest2Task - -/*-----------------------------------------------------------*/ -vRegTest1Task - - /* Fill the core registers with known values. This is only done once. */ - movs r1, #101 - movs r2, #102 - movs r3, #103 - movs r4, #104 - movs r5, #105 - movs r6, #106 - movs r7, #107 - movs r0, #108 - mov r8, r0 - movs r0, #109 - mov r9, r0 - movs r0, #110 - mov r10, r0 - movs r0, #111 - mov r11, r0 - movs r0, #112 - mov r12, r0 - movs r0, #100 - -reg1_loop - /* Repeatedly check that each register still contains the value written to - it when the task started. */ - cmp r0, #100 - bne reg1_error_loop - cmp r1, #101 - bne reg1_error_loop - cmp r2, #102 - bne reg1_error_loop - cmp r3, #103 - bne reg1_error_loop - cmp r4, #104 - bne reg1_error_loop - cmp r5, #105 - bne reg1_error_loop - cmp r6, #106 - bne reg1_error_loop - cmp r7, #107 - bne reg1_error_loop - movs r0, #108 - cmp r8, r0 - bne reg1_error_loop - movs r0, #109 - cmp r9, r0 - bne reg1_error_loop - movs r0, #110 - cmp r10, r0 - bne reg1_error_loop - movs r0, #111 - cmp r11, r0 - bne reg1_error_loop - movs r0, #112 - cmp r12, r0 - bne reg1_error_loop - - /* Everything passed, increment the loop counter. */ - push { r1 } - ldr r0, =ulRegTest1LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - - /* Yield to increase test coverage. */ - movs r0, #0x01 - ldr r1, =0xe000ed04 /* NVIC_INT_CTRL */ - lsls r0 ,r0, #28 /* Shift to PendSV bit */ - str r0, [r1] - dsb - pop { r1 } - - /* Start again. */ - movs r0, #100 - b reg1_loop - -reg1_error_loop - /* If this line is hit then there was an error in a core register value. - The loop ensures the loop counter stops incrementing. */ - b reg1_error_loop - nop - - - -vRegTest2Task - - /* Fill the core registers with known values. This is only done once. */ - movs r1, #1 - movs r2, #2 - movs r3, #3 - movs r4, #4 - movs r5, #5 - movs r6, #6 - movs r7, #7 - movs r0, #8 - mov r8, r0 - movs r0, #9 - mov r9, r0 - movs r0, #10 - mov r10, r0 - movs r0, #11 - mov r11, r0 - movs r0, #12 - mov r12, r0 - movs r0, #10 - -reg2_loop - /* Repeatedly check that each register still contains the value written to - it when the task started. */ - cmp r0, #10 - bne reg2_error_loop - cmp r1, #1 - bne reg2_error_loop - cmp r2, #2 - bne reg2_error_loop - cmp r3, #3 - bne reg2_error_loop - cmp r4, #4 - bne reg2_error_loop - cmp r5, #5 - bne reg2_error_loop - cmp r6, #6 - bne reg2_error_loop - cmp r7, #7 - bne reg2_error_loop - movs r0, #8 - cmp r8, r0 - bne reg2_error_loop - movs r0, #9 - cmp r9, r0 - bne reg2_error_loop - movs r0, #10 - cmp r10, r0 - bne reg2_error_loop - movs r0, #11 - cmp r11, r0 - bne reg2_error_loop - movs r0, #12 - cmp r12, r0 - bne reg2_error_loop - - /* Everything passed, increment the loop counter. */ - push { r1 } - ldr r0, =ulRegTest2LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r1 } - - /* Start again. */ - movs r0, #10 - b reg2_loop - -reg2_error_loop - ;/* If this line is hit then there was an error in a core register value. - ;The loop ensures the loop counter stops incrementing. */ - b reg2_error_loop - nop - - END diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/compiler_attributes.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/compiler_attributes.h deleted file mode 100644 index 0160d96c4..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/compiler_attributes.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Placing variable at specified address. */ -#define COMPILER_ATTRIBUTE_PLACE_IN_2ND_MEMORY_BANK @ 0x20000000 diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/startup_LPC51U68.s b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/startup_LPC51U68.s deleted file mode 100644 index a6c41f02c..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/IAR_specific/startup_LPC51U68.s +++ /dev/null @@ -1,385 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC51U68.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File -; * LPC51U68 -; * @version: 1.0 -; * @date: 2017-12-15 -; *---------------------------------------------------------------------------- -; * -; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2018 NXP -; -; SPDX-License-Identifier: BSD-3-Clause -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect - DCD DMA0_IRQHandler ; DMA controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) - DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. - DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. - DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD Reserved47_IRQHandler ; Reserved interrupt -__Vectors_End - -; Code Read Protection Level (CRP) -; <0xFFFFFFFF=> Disabled -; <0x4E697370=> NO_ISP -; <0x12345678=> CRP1 -; <0x87654321=> CRP2 -; <0x43218765=> CRP3 - -#if !defined NO_CRP - SECTION .crp:CODE -__CRP - DCD 0xFFFFFFFF -__CRP_End -#endif - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR r0, =SystemInit - BLX r0 - LDR r0, =__iar_program_start - BX r0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_SEQA_IRQHandler - PUBWEAK ADC0_SEQA_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_SEQA_IRQHandler - LDR R0, =ADC0_SEQA_DriverIRQHandler - BX R0 - PUBWEAK ADC0_SEQB_IRQHandler - PUBWEAK ADC0_SEQB_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_SEQB_IRQHandler - LDR R0, =ADC0_SEQB_DriverIRQHandler - BX R0 - PUBWEAK ADC0_THCMP_IRQHandler - PUBWEAK ADC0_THCMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_THCMP_IRQHandler - LDR R0, =ADC0_THCMP_DriverIRQHandler - BX R0 - PUBWEAK Reserved41_IRQHandler - PUBWEAK Reserved41_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved41_IRQHandler - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - PUBWEAK Reserved42_IRQHandler - PUBWEAK Reserved42_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved42_IRQHandler - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - PUBWEAK USB0_NEEDCLK_IRQHandler - PUBWEAK USB0_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_NEEDCLK_IRQHandler - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK USB0_IRQHandler - PUBWEAK USB0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_IRQHandler - LDR R0, =USB0_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK Reserved46_IRQHandler - PUBWEAK Reserved46_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved46_IRQHandler - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - PUBWEAK Reserved47_IRQHandler - PUBWEAK Reserved47_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved47_IRQHandler - LDR R0, =Reserved47_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_SEQA_DriverIRQHandler -ADC0_SEQB_DriverIRQHandler -ADC0_THCMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -Reserved47_DriverIRQHandler -DefaultISR - B . - - END diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/LPC51U68_256.FLM b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/LPC51U68_256.FLM deleted file mode 100644 index 517f0be2e..000000000 Binary files a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/LPC51U68_256.FLM and /dev/null differ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/LPC51U68_flash.scf b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/LPC51U68_flash.scf deleted file mode 100644 index 9dde63b08..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/LPC51U68_flash.scf +++ /dev/null @@ -1,66 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processors: LPC51U68JBD48 -** LPC51U68JBD64 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 -** Version: rev. 1.0, 2017-12-15 -** Build: b180801 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_text_start 0x00000000 -#define m_text_size 0x00040000 - -#define m_sramx_start 0x04000000 -#define m_sramx_size 0x00008000 - -#define m_data_start 0x20000000 -#define m_data_size 0x00010000 - -LR_m_text m_text_start m_text_size { ; load region size_region - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (RESET,+FIRST) - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_sramx_start m_sramx_size { ; RW data - .ANY (+RW +ZI) - } - RW_m_data_2 m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP ((ImageLimit(RW_m_data_2) == m_data_start) ? m_data_start : +0) EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/LPC51U68_ram.scf b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/LPC51U68_ram.scf deleted file mode 100644 index 91788b9f1..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/LPC51U68_ram.scf +++ /dev/null @@ -1,60 +0,0 @@ -#! armcc -E -/* -** ################################################################### -** Processors: LPC51U68JBD48 -** LPC51U68JBD64 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 -** Version: rev. 1.0, 2017-12-15 -** Build: b180801 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - - -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x0400 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x0400 -#endif - -#define m_text_start 0x04000000 -#define m_text_size 0x00008000 - -#define m_data_start 0x20000000 -#define m_data_size 0x00010000 - -LR_m_text m_text_start m_text_size { ; load region size_region - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (RESET,+FIRST) - * (InRoot$$Sections) - .ANY (+RO) - } - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - .ANY (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/RegTest_Keil.s b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/RegTest_Keil.s deleted file mode 100644 index 0374936bb..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/RegTest_Keil.s +++ /dev/null @@ -1,212 +0,0 @@ -;/* -; * FreeRTOS Kernel V10.2.1 -; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. -; * -; * Permission is hereby granted, free of charge, to any person obtaining a copy of -; * this software and associated documentation files (the "Software"), to deal in -; * the Software without restriction, including without limitation the rights to -; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of -; * the Software, and to permit persons to whom the Software is furnished to do so, -; * subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all -; * copies or substantial portions of the Software. -; * -; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS -; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR -; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER -; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -; * -; * http://www.FreeRTOS.org -; * http://aws.amazon.com/freertos -; * -; * 1 tab == 4 spaces! -; */ - -;/* -; * "Reg test" tasks - These fill the registers with known values, then check -; * that each register maintains its expected value for the lifetime of the -; * task. Each task uses a different set of values. The reg test tasks execute -; * with a very low priority, so get preempted very frequently. A register -; * containing an unexpected value is indicative of an error in the context -; * switching mechanism. -; */ - - PRESERVE8 - THUMB - - - IMPORT ulRegTest1LoopCounter - IMPORT ulRegTest2LoopCounter - - EXPORT vRegTest1Task - EXPORT vRegTest2Task - - AREA |.text|, CODE, READONLY - -;/*-----------------------------------------------------------*/ -vRegTest1Task PROC - - ;/* Fill the core registers with known values. This is only done once. */ - movs r1, #101 - movs r2, #102 - movs r3, #103 - movs r4, #104 - movs r5, #105 - movs r6, #106 - movs r7, #107 - movs r0, #108 - mov r8, r0 - movs r0, #109 - mov r9, r0 - movs r0, #110 - mov r10, r0 - movs r0, #111 - mov r11, r0 - movs r0, #112 - mov r12, r0 - movs r0, #100 - -reg1_loop - ;/* Repeatedly check that each register still contains the value written to - ;it when the task started. */ - cmp r0, #100 - bne reg1_error_loop - cmp r1, #101 - bne reg1_error_loop - cmp r2, #102 - bne reg1_error_loop - cmp r3, #103 - bne reg1_error_loop - cmp r4, #104 - bne reg1_error_loop - cmp r5, #105 - bne reg1_error_loop - cmp r6, #106 - bne reg1_error_loop - cmp r7, #107 - bne reg1_error_loop - movs r0, #108 - cmp r8, r0 - bne reg1_error_loop - movs r0, #109 - cmp r9, r0 - bne reg1_error_loop - movs r0, #110 - cmp r10, r0 - bne reg1_error_loop - movs r0, #111 - cmp r11, r0 - bne reg1_error_loop - movs r0, #112 - cmp r12, r0 - bne reg1_error_loop - - ;/* Everything passed, increment the loop counter. */ - push { r1 } - ldr r0, =ulRegTest1LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - - ;/* Yield to increase test coverage. */ - movs r0, #0x01 - ldr r1, =0xe000ed04 ; NVIC_INT_CTRL - lsls r0 ,r0, #28 ; Shift to PendSV bit - str r0, [r1] - dsb - pop { r1 } - - ;/* Start again. */ - movs r0, #100 - - b reg1_loop - -reg1_error_loop - ;/* If this line is hit then there was an error in a core register value. - ;The loop ensures the loop counter stops incrementing. */ - b reg1_error_loop - nop - ENDP - - - -vRegTest2Task PROC - - ;/* Fill the core registers with known values. This is only done once. */ - movs r1, #1 - movs r2, #2 - movs r3, #3 - movs r4, #4 - movs r5, #5 - movs r6, #6 - movs r7, #7 - movs r0, #8 - mov r8, r0 - movs r0, #9 - mov r9, r0 - movs r0, #10 - mov r10, r0 - movs r0, #11 - mov r11, r0 - movs r0, #12 - mov r12, r0 - movs r0, #10 - -reg2_loop - ;/* Repeatedly check that each register still contains the value written to - ;it when the task started. */ - cmp r0, #10 - bne reg2_error_loop - cmp r1, #1 - bne reg2_error_loop - cmp r2, #2 - bne reg2_error_loop - cmp r3, #3 - bne reg2_error_loop - cmp r4, #4 - bne reg2_error_loop - cmp r5, #5 - bne reg2_error_loop - cmp r6, #6 - bne reg2_error_loop - cmp r7, #7 - bne reg2_error_loop - movs r0, #8 - cmp r8, r0 - bne reg2_error_loop - movs r0, #9 - cmp r9, r0 - bne reg2_error_loop - movs r0, #10 - cmp r10, r0 - bne reg2_error_loop - movs r0, #11 - cmp r11, r0 - bne reg2_error_loop - movs r0, #12 - cmp r12, r0 - bne reg2_error_loop - - ;/* Everything passed, increment the loop counter. */ - push { r1 } - ldr r0, =ulRegTest2LoopCounter - ldr r1, [r0] - adds r1, r1, #1 - str r1, [r0] - pop { r1 } - - ;/* Start again. */ - movs r0, #10 - b reg2_loop - -reg2_error_loop - ;/* If this line is hit then there was an error in a core register value. - ;The loop ensures the loop counter stops incrementing. */ - b reg2_error_loop - nop - ENDP - - END diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/compiler_attributes.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/compiler_attributes.h deleted file mode 100644 index 5167987c9..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/compiler_attributes.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Placing variable at specified address. -todo: -this is commented out intentionally, as it doesn't seem to work. -Clean up is needed*/ -#define COMPILER_ATTRIBUTE_PLACE_IN_2ND_MEMORY_BANK //__attribute__((section("m_data_start"))) diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/keil_lib_power.lib b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/keil_lib_power.lib deleted file mode 100644 index 2de428fa3..000000000 Binary files a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/keil_lib_power.lib and /dev/null differ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/startup_LPC51U68.s b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/startup_LPC51U68.s deleted file mode 100644 index 8ced8b869..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/Keil_specific/startup_LPC51U68.s +++ /dev/null @@ -1,420 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC51U68.s -; * @purpose: CMSIS Cortex-M0 Core Device Startup File for the -; * LPC51U68 -; * @version: 1.0 -; * @date: 2017-12-15 -; * -; * Copyright 1997-2016 Freescale Semiconductor, Inc. -; * Copyright 2016-2018 NXP -; * -; * SPDX-License-Identifier: BSD-3-Clause -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 ; Checksum of the first 7 words - DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect - DCD DMA0_IRQHandler ; DMA controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S) - DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. - DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. - DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD Reserved47_IRQHandler ; Reserved interrupt - - AREA |.text|, CODE, READONLY - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR r0, =SystemInit - BLX r0 - LDR r0, =__main - BX r0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler \ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -WDT_BOD_IRQHandler\ - PROC - EXPORT WDT_BOD_IRQHandler [WEAK] - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - ENDP - -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -GINT0_IRQHandler\ - PROC - EXPORT GINT0_IRQHandler [WEAK] - LDR R0, =GINT0_DriverIRQHandler - BX R0 - ENDP - -GINT1_IRQHandler\ - PROC - EXPORT GINT1_IRQHandler [WEAK] - LDR R0, =GINT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT0_IRQHandler\ - PROC - EXPORT PIN_INT0_IRQHandler [WEAK] - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - ENDP - -PIN_INT1_IRQHandler\ - PROC - EXPORT PIN_INT1_IRQHandler [WEAK] - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT2_IRQHandler\ - PROC - EXPORT PIN_INT2_IRQHandler [WEAK] - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - ENDP - -PIN_INT3_IRQHandler\ - PROC - EXPORT PIN_INT3_IRQHandler [WEAK] - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - ENDP - -UTICK0_IRQHandler\ - PROC - EXPORT UTICK0_IRQHandler [WEAK] - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - ENDP - -MRT0_IRQHandler\ - PROC - EXPORT MRT0_IRQHandler [WEAK] - LDR R0, =MRT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER0_IRQHandler\ - PROC - EXPORT CTIMER0_IRQHandler [WEAK] - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - ENDP - -CTIMER1_IRQHandler\ - PROC - EXPORT CTIMER1_IRQHandler [WEAK] - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - ENDP - -SCT0_IRQHandler\ - PROC - EXPORT SCT0_IRQHandler [WEAK] - LDR R0, =SCT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER3_IRQHandler\ - PROC - EXPORT CTIMER3_IRQHandler [WEAK] - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM0_IRQHandler\ - PROC - EXPORT FLEXCOMM0_IRQHandler [WEAK] - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM1_IRQHandler\ - PROC - EXPORT FLEXCOMM1_IRQHandler [WEAK] - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM2_IRQHandler\ - PROC - EXPORT FLEXCOMM2_IRQHandler [WEAK] - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM3_IRQHandler\ - PROC - EXPORT FLEXCOMM3_IRQHandler [WEAK] - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM4_IRQHandler\ - PROC - EXPORT FLEXCOMM4_IRQHandler [WEAK] - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM5_IRQHandler\ - PROC - EXPORT FLEXCOMM5_IRQHandler [WEAK] - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM6_IRQHandler\ - PROC - EXPORT FLEXCOMM6_IRQHandler [WEAK] - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM7_IRQHandler\ - PROC - EXPORT FLEXCOMM7_IRQHandler [WEAK] - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - ENDP - -ADC0_SEQA_IRQHandler\ - PROC - EXPORT ADC0_SEQA_IRQHandler [WEAK] - LDR R0, =ADC0_SEQA_DriverIRQHandler - BX R0 - ENDP - -ADC0_SEQB_IRQHandler\ - PROC - EXPORT ADC0_SEQB_IRQHandler [WEAK] - LDR R0, =ADC0_SEQB_DriverIRQHandler - BX R0 - ENDP - -ADC0_THCMP_IRQHandler\ - PROC - EXPORT ADC0_THCMP_IRQHandler [WEAK] - LDR R0, =ADC0_THCMP_DriverIRQHandler - BX R0 - ENDP - -Reserved41_IRQHandler\ - PROC - EXPORT Reserved41_IRQHandler [WEAK] - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - ENDP - -Reserved42_IRQHandler\ - PROC - EXPORT Reserved42_IRQHandler [WEAK] - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - ENDP - -USB0_NEEDCLK_IRQHandler\ - PROC - EXPORT USB0_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -USB0_IRQHandler\ - PROC - EXPORT USB0_IRQHandler [WEAK] - LDR R0, =USB0_DriverIRQHandler - BX R0 - ENDP - -RTC_IRQHandler\ - PROC - EXPORT RTC_IRQHandler [WEAK] - LDR R0, =RTC_DriverIRQHandler - BX R0 - ENDP - -Reserved46_IRQHandler\ - PROC - EXPORT Reserved46_IRQHandler [WEAK] - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - ENDP - -Reserved47_IRQHandler\ - PROC - EXPORT Reserved47_IRQHandler [WEAK] - LDR R0, =Reserved47_DriverIRQHandler - BX R0 - ENDP - -Default_Handler PROC - EXPORT WDT_BOD_DriverIRQHandler [WEAK] - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT GINT0_DriverIRQHandler [WEAK] - EXPORT GINT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT0_DriverIRQHandler [WEAK] - EXPORT PIN_INT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT2_DriverIRQHandler [WEAK] - EXPORT PIN_INT3_DriverIRQHandler [WEAK] - EXPORT UTICK0_DriverIRQHandler [WEAK] - EXPORT MRT0_DriverIRQHandler [WEAK] - EXPORT CTIMER0_DriverIRQHandler [WEAK] - EXPORT CTIMER1_DriverIRQHandler [WEAK] - EXPORT SCT0_DriverIRQHandler [WEAK] - EXPORT CTIMER3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] - EXPORT ADC0_SEQA_DriverIRQHandler [WEAK] - EXPORT ADC0_SEQB_DriverIRQHandler [WEAK] - EXPORT ADC0_THCMP_DriverIRQHandler [WEAK] - EXPORT Reserved41_DriverIRQHandler [WEAK] - EXPORT Reserved42_DriverIRQHandler [WEAK] - EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT USB0_DriverIRQHandler [WEAK] - EXPORT RTC_DriverIRQHandler [WEAK] - EXPORT Reserved46_DriverIRQHandler [WEAK] - EXPORT Reserved47_DriverIRQHandler [WEAK] - -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_SEQA_DriverIRQHandler -ADC0_SEQB_DriverIRQHandler -ADC0_THCMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -Reserved47_DriverIRQHandler - - B . - - ENDP - - - ALIGN - - - END - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/FreeRTOSConfig.h deleted file mode 100644 index e2551e7bc..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/FreeRTOSConfig.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -#ifndef FREERTOS_CONFIG_H -#define FREERTOS_CONFIG_H - -/*----------------------------------------------------------- - * Application specific definitions. - * - * These definitions should be adjusted for your particular hardware and - * application requirements. - * - * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. - * - * See http://www.freertos.org/a00110.html - *----------------------------------------------------------*/ - -/* Prevent C code being included by the IAR assembler. */ -#ifndef __IASMARM__ - #include - extern uint32_t SystemCoreClock; -#endif - -#define configUSE_PREEMPTION 1 -#define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 1 -#define configCPU_CLOCK_HZ ( SystemCoreClock ) -#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) -#define configMAX_PRIORITIES ( 5 ) -#define configMAX_TASK_NAME_LEN ( 5 ) -#define configUSE_TRACE_FACILITY 1 -#define configUSE_16_BIT_TICKS 0 -#define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 1 -#define configQUEUE_REGISTRY_SIZE 8 -#define configCHECK_FOR_STACK_OVERFLOW 2 -#define configUSE_RECURSIVE_MUTEXES 1 -#define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 -#define configUSE_COUNTING_SEMAPHORES 1 -#define configGENERATE_RUN_TIME_STATS 0 - -/* Support various memory allocation. */ -#define configSUPPORT_STATIC_ALLOCATION 0 -#define configSUPPORT_DYNAMIC_ALLOCATION 1 - -/* Heap and stack. - * The bytes specified in configTOTAL_HEAP_SIZE need to fit in to - * the first memory bank, which is of size 64kB in total. This 64kB - * consists of FreeRTOS heap, linker heap and also .bss etc. Thus - * FreeRTOS heap cannot take the entire 64kB. */ -#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 256 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 20 * 1024 ) ) - -/* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY ( 2 ) -#define configTIMER_QUEUE_LENGTH 2 -#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE ) - -/* Enabling tickless. */ -#define configUSE_TICKLESS_IDLE 1 - -/* Set the following definitions to 1 to include the API function, or zero -to exclude the API function. */ -#define INCLUDE_vTaskPrioritySet 1 -#define INCLUDE_uxTaskPriorityGet 1 -#define INCLUDE_vTaskDelete 1 -#define INCLUDE_vTaskCleanUpResources 1 -#define INCLUDE_vTaskSuspend 1 -#define INCLUDE_vTaskDelayUntil 1 -#define INCLUDE_vTaskDelay 1 -#define INCLUDE_eTaskGetState 1 - -/* Normal assert() semantics without relying on the provision of an assert.h -header file. */ -#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } - -/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS -standard names - or at least those used in the unmodified vector table. */ -#define vPortSVCHandler SVCall_Handler -#define xPortPendSVHandler PendSV_Handler -#define xPortSysTickHandler SysTick_Handler - -#endif /* FREERTOS_CONFIG_H */ - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/IntQueueTimer.c deleted file mode 100644 index 2bf143344..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/IntQueueTimer.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "IntQueueTimer.h" -#include "IntQueue.h" - -/* Driver APIs.*/ -#include "fsl_ctimer.h" - -/* The priorities for the two timers. Note that a priority of 0 is the highest -possible on Cortex-M devices. */ -#define tmrMAX_PRIORITY ( 0UL ) -#define trmSECOND_HIGHEST_PRIORITY ( tmrMAX_PRIORITY + 1 ) - -void vInitialiseTimerForIntQueueTest( void ) -{ -ctimer_config_t xConfigTimer0, xConfigTimer1; -ctimer_match_config_t xConfigInterrupt = { 0 }; - - memset( &xConfigTimer0, 0x00, sizeof( xConfigTimer0 ) ); - memset( &xConfigTimer1, 0x00, sizeof( xConfigTimer1 ) ); - - /* Enable peripheral bus clock for CTIMER0 and CTIMER1. */ - CLOCK_EnableClock( kCLOCK_Ctimer0 ); - CLOCK_EnableClock( kCLOCK_Ctimer1 ); - - /* Interrupt settings for timers -- - A timer will generates an interrupt when the count matches the value specified. - Timer will reset itself and restart the count. The interrupt frequency is fairly - arbitrary, in a sense that all we need to make sure is IRQs are triggered so that - queues have items for tasks to process. */ - xConfigInterrupt.enableCounterReset = true; - xConfigInterrupt.enableCounterStop = false; - xConfigInterrupt.enableInterrupt = true; - xConfigInterrupt.matchValue = 0xFFFFF; - xConfigInterrupt.outControl = kCTIMER_Output_NoAction; - xConfigInterrupt.outPinInitState = true; - - /* Configuration settings for timers. */ - CTIMER_GetDefaultConfig( &xConfigTimer0 ); - xConfigTimer0.prescale = 1; - - CTIMER_GetDefaultConfig( &xConfigTimer1 ); - xConfigTimer1.prescale = 2; - - /* Initialize timers. */ - CTIMER_Init( CTIMER0, &xConfigTimer0 ); - CTIMER_SetupMatch( CTIMER0, kCTIMER_Match_0, &xConfigInterrupt ); - - CTIMER_Init( CTIMER1, &xConfigTimer1 ); - CTIMER_SetupMatch( CTIMER1, kCTIMER_Match_0, &xConfigInterrupt ); - - /* Don't generate interrupts until the scheduler has been started. - Interrupts will be automatically enabled when the first task starts - running. */ - taskDISABLE_INTERRUPTS(); - - /* Set the timer interrupts to be above the kernel. The interrupts are - assigned different priorities so they nest with each other. */ - NVIC_SetPriority( CTIMER0_IRQn, trmSECOND_HIGHEST_PRIORITY ); - NVIC_SetPriority( CTIMER1_IRQn, tmrMAX_PRIORITY ); - - /* Enable the timer interrupts. */ - NVIC_EnableIRQ( CTIMER0_IRQn ); - NVIC_EnableIRQ( CTIMER1_IRQn ); - - /* Start timers. */ - CTIMER_StartTimer( CTIMER0 ); - CTIMER_StartTimer( CTIMER1 ); -} -/*-----------------------------------------------------------*/ - -void CTIMER0_IRQHandler( void ) -{ -uint32_t ulInterruptStatus; - - /* Get Interrupt status flags */ - ulInterruptStatus = CTIMER_GetStatusFlags( CTIMER0 ); - - /* Clear the status flags that were set */ - CTIMER_ClearStatusFlags( CTIMER0, ulInterruptStatus ); - - portEND_SWITCHING_ISR( xFirstTimerHandler() ); -} -/*-----------------------------------------------------------*/ - -void CTIMER1_IRQHandler(void) -{ -uint32_t ulInterruptStatus; - - /* Get Interrupt status flags */ - ulInterruptStatus = CTIMER_GetStatusFlags( CTIMER1 ); - - /* Clear the status flags that were set */ - CTIMER_ClearStatusFlags( CTIMER1, ulInterruptStatus ); - - portEND_SWITCHING_ISR( xSecondTimerHandler() ); -} -/*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/IntQueueTimer.h deleted file mode 100644 index d26057f9a..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/IntQueueTimer.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef INT_QUEUE_TIMER_H -#define INT_QUEUE_TIMER_H - -void vInitialiseTimerForIntQueueTest( void ); -portBASE_TYPE xTimer0Handler( void ); -portBASE_TYPE xTimer1Handler( void ); - -#endif - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/main.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/main.c deleted file mode 100644 index 07dd94bc7..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/main.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright 2016-2019 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of NXP Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file main.c - * @brief Application entry point. - */ -#include - -/* Board specific includes. */ -#include "board.h" -#include "peripherals.h" -#include "pin_mux.h" -#include "clock_config.h" -#include "LPC51U68.h" -#include "fsl_debug_console.h" - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" - -#include "compiler_attributes.h" - -/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to - * 0 -- to run the more comprehensive test and demo application, - * 1 -- to run the simple blinky demo. - */ -#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 0 - -/*-----------------------------------------------------------*/ -typedef enum LED_STATE { - LED_RED_BLINK_ON = 1, - LED_RED_BLINK_OFF, - LED_GREEN_BLINK_ON, - LED_GREEN_BLINK_OFF, - LED_BLUE_BLINK_ON, - LED_BLUE_BLINK_OFF, -} E_LED_STATE; - -/* Static variable to keep track of LED color. - * red -> green -> blue -> red -> ... - * This variable is not intended for multi-threaded application. - */ -static E_LED_STATE eLedState = LED_RED_BLINK_ON; - -/* Show iteration number in UART. - * This variable is not intended for multi-threaded application. - */ -static int i = 0; - -/* Track how many times tick interrupt has occurred. */ -static unsigned int uTickInterruptCounter = 0; - -/* - * Perform any application specific hardware configuration. The clocks, - * memory, etc. are configured before main() is called. - */ -static void prvSetupHardware( void ); - -/** - * Heap_5 is being used because the RAM is not contiguous, therefore the heap - * needs to be initialized. See http://www.freertos.org/a00111.html - */ -static void prvInitializeHeap( void ); - -/* - * The hardware only has a single LED. Simply toggle it. - */ -void vMainToggleLED( void ); - -/* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. -main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ -void main_blinky( void ); -void main_full( void ); - -/* - * @brief Application entry point. - */ -int main(void) -{ - - /* Prepare the hardware to run this demo. */ - prvSetupHardware(); - - /* Initialize heap regions. */ - prvInitializeHeap(); - - /* Show something on UART. - Serial port setup as baudrate: 115200, data: 8-bit, parity: none, stop bits: 1, flow control: none. - sTerminal setup as receive: auto, transmit: CR+LF.*/ - PRINTF("FreeRTOS demo.\r\n"); - - /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top - of this file. */ - #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 - { - main_blinky(); - } - #else - { - main_full(); - } - #endif - - return 0; -} - -/*-----------------------------------------------------------*/ -void vMainToggleLED( void ) -{ - switch (eLedState) - { - case LED_RED_BLINK_ON: - PRINTF("Iteration %d -- tick interrupt count %d.\r\n", i, uTickInterruptCounter); - i++; - - LED_RED_ON(); - eLedState = LED_RED_BLINK_OFF; - break; - case LED_RED_BLINK_OFF: - LED_RED_OFF(); - eLedState = LED_GREEN_BLINK_ON; - break; - case LED_GREEN_BLINK_ON: - LED_GREEN_ON(); - eLedState = LED_GREEN_BLINK_OFF; - break; - case LED_GREEN_BLINK_OFF: - LED_GREEN_OFF(); - eLedState = LED_BLUE_BLINK_ON; - break; - case LED_BLUE_BLINK_ON: - LED_BLUE_ON(); - eLedState = LED_BLUE_BLINK_OFF; - break; - case LED_BLUE_BLINK_OFF: - LED_BLUE_OFF(); - eLedState = LED_RED_BLINK_ON; - break; - default: - /* Unexpected state. Let's reset to default color. */ - eLedState = LED_RED_BLINK_ON; - } - - return; -} - -/*-----------------------------------------------------------*/ - -static void prvSetupHardware( void ) -{ - /* Initialize board hardware. */ - BOARD_InitBootPins(); - BOARD_InitBootClocks(); - BOARD_InitBootPeripherals(); - - /* Enable clock for GPIO. */ - CLOCK_EnableClock(kCLOCK_Gpio0); - CLOCK_EnableClock(kCLOCK_Gpio1); - - /* Initialize FSL debug console. */ - BOARD_InitDebugConsole(); - - /* Initialize tri-color LED. */ - LED_RED_INIT(LOGIC_LED_OFF); - LED_GREEN_INIT(LOGIC_LED_OFF); - LED_BLUE_INIT(LOGIC_LED_OFF); - - return; -} - -/*-----------------------------------------------------------*/ - -static void prvInitializeHeap( void ) -{ - /* Place the first block of the heap memory in the first bank of RAM. */ - static uint8_t ucHeap1[ configTOTAL_HEAP_SIZE ]; - - /* Place the second block of the heap memory in the second bank of RAM. */ - static uint8_t ucHeap2[ 16 * 1024 ] COMPILER_ATTRIBUTE_PLACE_IN_2ND_MEMORY_BANK; - - /* Memory regions are defined in address order, and terminate with NULL. */ - static HeapRegion_t xHeapRegions[] = - { - { ( unsigned char * ) ucHeap1, sizeof( ucHeap1 ) }, - { ( unsigned char * ) ucHeap2, sizeof( ucHeap2 ) }, - { NULL, 0 } - }; - - vPortDefineHeapRegions( xHeapRegions ); - - return; -} - -/*-----------------------------------------------------------*/ - -void vApplicationMallocFailedHook( void ) -{ - /* vApplicationMallocFailedHook() will only be called if - configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h. It is a hook - function that will get called if a call to pvPortMalloc() fails. - pvPortMalloc() is called internally by the kernel whenever a task, queue, - timer or semaphore is created. It is also called by various parts of the - demo application. If heap_1.c or heap_2.c are used, then the size of the - heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in - FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used - to query the size of free heap space that remains (although it does not - provide information on how the remaining heap might be fragmented). */ - taskDISABLE_INTERRUPTS(); - for( ;; ); -} - -/*-----------------------------------------------------------*/ - -void vApplicationIdleHook( void ) -{ - /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set - to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle - task. It is essential that code added to this hook function never attempts - to block in any way (for example, call xQueueReceive() with a block time - specified, or call vTaskDelay()). If the application makes use of the - vTaskDelete() API function (as this demo application does) then it is also - important that vApplicationIdleHook() is permitted to return to its calling - function, because it is the responsibility of the idle task to clean up - memory allocated by the kernel to any task that has since been deleted. */ -} - -/*-----------------------------------------------------------*/ - -void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) -{ - ( void ) pcTaskName; - ( void ) pxTask; - - /* Run time stack overflow checking is performed if - configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook - function is called if a stack overflow is detected. */ - taskDISABLE_INTERRUPTS(); - for( ;; ); -} - -/*-----------------------------------------------------------*/ - -void vApplicationTickHook( void ) -{ -#if mainCHECK_INTERRUPT_STACK == 1 -extern unsigned long _pvHeapStart[]; - - /* This function will be called by each tick interrupt if - configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be - added here, but the tick hook is called from an interrupt context, so - code must not attempt to block, and only the interrupt safe FreeRTOS API - functions can be used (those that end in FromISR()). */ - - /* Manually check the last few bytes of the interrupt stack to check they - have not been overwritten. Note - the task stacks are automatically - checked for overflow if configCHECK_FOR_STACK_OVERFLOW is set to 1 or 2 - in FreeRTOSConifg.h, but the interrupt stack is not. */ - configASSERT( memcmp( ( void * ) _pvHeapStart, ucExpectedInterruptStackValues, sizeof( ucExpectedInterruptStackValues ) ) == 0U ); -#endif /* mainCHECK_INTERRUPT_STACK */ - - uTickInterruptCounter++; -} - - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/main_blinky.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/main_blinky.c deleted file mode 100644 index 1fd2e2635..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/main_blinky.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky style - * project, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select - * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY - * in main.c. This file implements the simply blinky style version. - * - * NOTE 2: This file only contains the source code that is specific to the - * full demo. Generic functions, such FreeRTOS hook functions, and functions - * required to configure the hardware, are defined in main.c. - ****************************************************************************** - * - * main_blinky() creates one queue, and two tasks. It then starts the - * scheduler. - * - * The Queue Send Task: - * The queue send task is implemented by the prvQueueSendTask() function in - * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly - * block for 200 milliseconds, before sending the value 100 to the queue that - * was created within main_blinky(). Once the value is sent, the task loops - * back around to block for another 200 milliseconds. - * - * The Queue Receive Task: - * The queue receive task is implemented by the prvQueueReceiveTask() function - * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly - * blocks on attempts to read data from the queue that was created within - * main_blinky(). When data is received, the task checks the value of the - * data, and if the value equals the expected 100, toggles the LED. The 'block - * time' parameter passed to the queue receive function specifies that the - * task should be held in the Blocked state indefinitely to wait for data to - * be available on the queue. The queue receive task will only leave the - * Blocked state when the queue send task writes to the queue. As the queue - * send task writes to the queue every 200 milliseconds, the queue receive - * task leaves the Blocked state every 200 milliseconds, and therefore toggles - * the LED every 200 milliseconds. - */ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" - -/* Hardware specific includes. */ - - -/* Priorities at which the tasks are created. */ -#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) -#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) - -/* The rate at which data is sent to the queue. The 200ms value is converted -to ticks using the portTICK_PERIOD_MS constant. */ -#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) - -/* The number of items the queue can hold. This is 1 as the receive task -will remove items as they are added, meaning the send task should always find -the queue empty. */ -#define mainQUEUE_LENGTH ( 1 ) - -/* Values passed to the two tasks just to check the task parameter -functionality. */ -#define mainQUEUE_SEND_PARAMETER ( 0x1111UL ) -#define mainQUEUE_RECEIVE_PARAMETER ( 0x22UL ) -/*-----------------------------------------------------------*/ - -/* - * The tasks as described in the comments at the top of this file. - */ -static void prvQueueReceiveTask( void *pvParameters ); -static void prvQueueSendTask( void *pvParameters ); - -/* - * Called by main() to create the simply blinky style application if - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. - */ -void main_blinky( void ); - -/* - * The hardware only has a single LED. Simply toggle it. - */ -extern void vMainToggleLED( void ); - -/*-----------------------------------------------------------*/ - -/* The queue used by both tasks. */ -static QueueHandle_t xQueue = NULL; - -/*-----------------------------------------------------------*/ - -void main_blinky( void ) -{ - /* Create the queue. */ - xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) ); - - if( xQueue != NULL ) - { - /* Start the two tasks as described in the comments at the top of this - file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ - - xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); - - /* Start the tasks and timer running. */ - vTaskStartScheduler(); - } - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then - there was insufficient FreeRTOS heap memory available for the idle and/or - timer tasks to be created. See the memory management section on the - FreeRTOS web site for more details. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -static void prvQueueSendTask( void *pvParameters ) -{ -TickType_t xNextWakeTime; -const unsigned long ulValueToSend = 100UL; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); - - /* Initialise xNextWakeTime - this only needs to be done once. */ - xNextWakeTime = xTaskGetTickCount(); - - for( ;; ) - { - /* Place this task in the blocked state until it is time to run again. - The block time is specified in ticks, the constant used converts ticks - to ms. While in the Blocked state this task will not consume any CPU - time. */ - vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); - - /* Send to the queue - causing the queue receive task to unblock and - toggle the LED. 0 is used as the block time so the sending operation - will not block - it shouldn't need to block as the queue should always - be empty at this point in the code. */ - xQueueSend( xQueue, &ulValueToSend, 0U ); - } -} -/*-----------------------------------------------------------*/ - -static void prvQueueReceiveTask( void *pvParameters ) -{ -unsigned long ulReceivedValue; - - /* Check the task parameter is as expected. */ - configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_RECEIVE_PARAMETER ); - - for( ;; ) - { - /* Wait until something arrives in the queue - this task will block - indefinitely provided INCLUDE_vTaskSuspend is set to 1 in - FreeRTOSConfig.h. */ - xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); - - /* To get here something must have been received from the queue, but - is it the expected value? If it is, toggle the LED. */ - if( ulReceivedValue == 100UL ) - { - vMainToggleLED(); - ulReceivedValue = 0U; - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/main_full.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/main_full.c deleted file mode 100644 index 286d1be6d..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/app/main_full.c +++ /dev/null @@ -1,283 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/****************************************************************************** - * NOTE 1: This project provides two demo applications. A simple blinky style - * project, and a more comprehensive test and demo application. The - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select - * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY - * in main.c. This file implements the comprehensive test and demo version. - * - * NOTE 2: This file only contains the source code that is specific to the - * full demo. Generic functions, such FreeRTOS hook functions, and functions - * required to configure the hardware, are defined in main.c. - ****************************************************************************** - * - * main_full() creates a set of standard demo tasks (including a set of tasks - * that test the interrupt nesting behaviour), some application specific tasks, - * and a timer. It then starts the scheduler. The web documentation provides - * more details of the standard demo application tasks, which provide no - * particular functionality, but do provide a good example of how to use the - * FreeRTOS API. - * - * The interrupt nesting test tasks require that two timers are configured to - * generate interrupts. The interrupt service routines are defined in - * IntQueueTimer.c, and can be used as examples for application writers. They - * do not, however, directly demonstrate the use of FreeRTOS safe API functions - * (those that end in "FromISR"). Therefore, a dummy interrupt implementation - * called Dummy_IRQHandler() is provided at the end of main.c. - * - * In addition to the standard demo tasks, the following tasks and timer are - * defined and/or created within this file: - * - * "Reg test" tasks - These fill the registers with known values, then check - * that each register maintains its expected value for the lifetime of the - * task. Each task uses a different set of values. The reg test tasks execute - * with a very low priority, so get preempted very frequently. A register - * containing an unexpected value is indicative of an error in the context - * switching mechanism. - * - * "Check" software timer - The check timer period is initially set to three - * seconds. Its callback function checks that all the standard demo tasks, and - * the register check tasks, are not only still executing, but are executing - * without reporting any errors. If the check timer callback discovers that a - * task has either stalled, or reported an error, then it changes the period of - * the check timer from the initial three seconds, to just 200ms. The callback - * function also toggles the LED each time it is called. This provides a visual - * indication of the system status: If the LED toggles every three seconds, - * then no issues have been discovered. If the LED toggles every 200ms, then - * an issue has been discovered with at least one task. - */ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "queue.h" -#include "timers.h" - -/* Common demo includes. */ -#include "blocktim.h" -#include "countsem.h" -#include "recmutex.h" -#include "IntQueue.h" - - -/* The period after which the check timer will expire provided no errors have -been reported by any of the standard demo tasks. ms are converted to the -equivalent in ticks using the portTICK_PERIOD_MS constant. */ -#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_PERIOD_MS ) - -/* The period at which the check timer will expire if an error has been -reported in one of the standard demo tasks. ms are converted to the equivalent -in ticks using the portTICK_PERIOD_MS constant. */ -#define mainERROR_CHECK_TIMER_PERIOD_MS ( 200UL / portTICK_PERIOD_MS ) - -/* A block time of zero simply means "don't block". */ -#define mainDONT_BLOCK ( 0UL ) - -/* Set mainNO_TASK_NO_CHECK to - * 0 -- to include all predefined test tasks and checks, - * 1 -- to exclude all predefined test tasks and checks. - * When set to 1 (with few tasks in system), user could observe how tickless - * idle could minimize tick interrupt. */ -#define mainNO_TASK_NO_CHECK ( 1 ) -/*-----------------------------------------------------------*/ - -/* - * Register check tasks, as described at the top of this file. The nature of - * these files necessitates that they are written in an assembly. - */ -extern void vRegTest1Task( void *pvParameters ); -extern void vRegTest2Task( void *pvParameters ); - -/* - * The hardware only has a single LED. Simply toggle it. - */ -extern void vMainToggleLED( void ); - -/* - * The check timer callback function, as described at the top of this file. - */ -static void prvCheckTimerCallback( TimerHandle_t xTimer ); - -/* - * Called by main() to create the comprehensive test/demo application if - * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is not set to 1. - */ -void main_full( void ); - -/*-----------------------------------------------------------*/ - -/* The following two variables are used to communicate the status of the -register check tasks to the check software timer. If the variables keep -incrementing, then the register check tasks have not discovered any errors. If -a variable stops incrementing, then an error has been found. */ -volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; - -/*-----------------------------------------------------------*/ - -void main_full( void ) -{ -TimerHandle_t xCheckTimer = NULL; - -#if ( mainNO_TASK_NO_CHECK == 0 ) - /* The register test tasks are asm functions that don't use a stack. The - stack allocated just has to be large enough to hold the task context, and - for the additional required for the stack overflow checking to work (if - configured). */ - const size_t xRegTestStackSize = 25U; -#endif /* mainNO_TASK_NO_CHECK */ - -#if ( mainNO_TASK_NO_CHECK == 0 ) - /* Create the standard demo tasks, including the interrupt nesting test - tasks. */ - vStartInterruptQueueTasks(); - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartRecursiveMutexTasks(); - - /* Create the register test tasks as described at the top of this file. - These are naked functions that don't use any stack. A stack still has - to be allocated to hold the task context. */ - xTaskCreate( vRegTest1Task, /* Function that implements the task. */ - "Reg1", /* Text name of the task. */ - xRegTestStackSize, /* Stack allocated to the task. */ - NULL, /* The task parameter is not used. */ - tskIDLE_PRIORITY, /* The priority to assign to the task. */ - NULL ); /* Don't receive a handle back, it is not needed. */ - - xTaskCreate( vRegTest2Task, /* Function that implements the task. */ - "Reg2", /* Text name of the task. */ - xRegTestStackSize, /* Stack allocated to the task. */ - NULL, /* The task parameter is not used. */ - tskIDLE_PRIORITY, /* The priority to assign to the task. */ - NULL ); /* Don't receive a handle back, it is not needed. */ -#endif /* mainNO_TASK_NO_CHECK */ - - /* Create the software timer that performs the 'check' functionality, - as described at the top of this file. */ - xCheckTimer = xTimerCreate( "CheckTimer", /* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); - - /* If the software timer was created successfully, start it. It won't - actually start running until the scheduler starts. A block time of - zero is used in this call, although any value could be used as the block - time will be ignored because the scheduler has not started yet. */ - if( xCheckTimer != NULL ) - { - xTimerStart( xCheckTimer, mainDONT_BLOCK ); - } - - /* Start the kernel. From here on, only tasks and interrupts will run. */ - vTaskStartScheduler(); - - /* If all is well, the scheduler will now be running, and the following - line will never be reached. If the following line does execute, then there - was insufficient FreeRTOS heap memory available for the idle and/or timer - tasks to be created. See the memory management section on the FreeRTOS web - site, or the FreeRTOS tutorial books for more details. */ - for( ;; ); -} -/*-----------------------------------------------------------*/ - -/* See the description at the top of this file. */ -static void prvCheckTimerCallback( TimerHandle_t xTimer ) -{ -static long lChangedTimerPeriodAlready = pdFALSE; -unsigned long ulErrorFound = pdFALSE; - -#if ( mainNO_TASK_NO_CHECK == 0 ) - static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; -#endif /* mainNO_TASK_NO_CHECK */ - -#if ( mainNO_TASK_NO_CHECK == 0 ) - - /* Check all the demo and test tasks to ensure that they are all still - running, and that none have detected an error. */ - if( xAreIntQueueTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 0UL ); - } - - if( xAreBlockTimeTestTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 1UL ); - } - - if( xAreCountingSemaphoreTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 2UL ); - } - - if( xAreRecursiveMutexTasksStillRunning() != pdPASS ) - { - ulErrorFound |= ( 0x01UL << 3UL ); - } - - /* Check that the register test 1 task is still running. */ - if( ulLastRegTest1Value == ulRegTest1LoopCounter ) - { - ulErrorFound |= ( 0x01UL << 4UL ); - } - ulLastRegTest1Value = ulRegTest1LoopCounter; - - /* Check that the register test 2 task is still running. */ - if( ulLastRegTest2Value == ulRegTest2LoopCounter ) - { - ulErrorFound |= ( 0x01UL << 5UL ); - } - ulLastRegTest2Value = ulRegTest2LoopCounter; -#endif /* mainNO_TASK_NO_CHECK */ - - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then - everything is ok. A faster toggle indicates an error. */ - vMainToggleLED(); - - /* Have any errors been latched in ulErrorFound? If so, shorten the - period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds. - This will result in an increase in the rate at which mainCHECK_LED - toggles. */ - if( ulErrorFound != pdFALSE ) - { - if( lChangedTimerPeriodAlready == pdFALSE ) - { - lChangedTimerPeriodAlready = pdTRUE; - - /* This call to xTimerChangePeriod() uses a zero block time. - Functions called from inside of a timer callback function must - *never* attempt to block. */ - xTimerChangePeriod( xTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK ); - } - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/board.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/board.c deleted file mode 100644 index 8806a3936..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/board.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "fsl_common.h" -#include "clock_config.h" -#include "board.h" -#include "fsl_debug_console.h" - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/* Clock rate on the CLKIN pin */ -const uint32_t ExtClockIn = BOARD_EXTCLKINRATE; - -/******************************************************************************* - * Code - ******************************************************************************/ -/* Initialize debug console. */ -status_t BOARD_InitDebugConsole(void) -{ - status_t result; - /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ - CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH); - RESET_PeripheralReset(BOARD_DEBUG_UART_RST); - result = DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, - BOARD_DEBUG_UART_CLK_FREQ); - assert(kStatus_Success == result); - return result; -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/board.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/board.h deleted file mode 100644 index a28ca84d1..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/board.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -#include "clock_config.h" -#include "fsl_common.h" -#include "fsl_gpio.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief The board name */ -#define BOARD_NAME "LPCXPRESSO51U68" - -#define BOARD_EXTCLKINRATE (0) - -/*! @brief The UART to use for debug messages. */ -#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart -#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0 -#define BOARD_DEBUG_UART_INSTANCE 0U -#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFreq(kCLOCK_Flexcomm0) -#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0 -#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn -#define BOARD_UART_IRQ FLEXCOMM0_IRQn -#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler - -#define BOARD_DEBUG_SPI_CLK_FREQ 12000000 - -#ifndef BOARD_DEBUG_UART_BAUDRATE -#define BOARD_DEBUG_UART_BAUDRATE 115200 -#endif /* BOARD_DEBUG_UART_BAUDRATE */ - -#ifndef BOARD_LED_RED_GPIO -#define BOARD_LED_RED_GPIO GPIO -#endif -#define BOARD_LED_RED_GPIO_PORT 0U -#ifndef BOARD_LED_RED_GPIO_PIN -#define BOARD_LED_RED_GPIO_PIN 29U -#endif -#ifndef BOARD_LED_GREEN_GPIO -#define BOARD_LED_GREEN_GPIO GPIO -#endif -#define BOARD_LED_GREEN_GPIO_PORT 1U -#ifndef BOARD_LED_GREEN_GPIO_PIN -#define BOARD_LED_GREEN_GPIO_PIN 10U -#endif -#ifndef BOARD_LED_BLUE_GPIO -#define BOARD_LED_BLUE_GPIO GPIO -#endif -#define BOARD_LED_BLUE_GPIO_PORT 1U -#ifndef BOARD_LED_BLUE_GPIO_PIN -#define BOARD_LED_BLUE_GPIO_PIN 9U -#endif - -#ifndef BOARD_SW1_GPIO -#define BOARD_SW1_GPIO GPIO -#endif -#define BOARD_SW1_GPIO_PORT 0U -#ifndef BOARD_SW1_GPIO_PIN -#define BOARD_SW1_GPIO_PIN 24U -#endif -#define BOARD_SW1_NAME "SW1" -#define BOARD_SW3_IRQ PIN_INT0_IRQn -#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler - -#ifndef BOARD_SW2_GPIO -#define BOARD_SW2_GPIO GPIO -#endif -#define BOARD_SW2_GPIO_PORT 0U -#ifndef BOARD_SW2_GPIO_PIN -#define BOARD_SW2_GPIO_PIN 31U -#endif -#define BOARD_SW2_NAME "SW2" -#define BOARD_SW3_IRQ PIN_INT0_IRQn -#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler - -#ifndef BOARD_SW3_GPIO -#define BOARD_SW3_GPIO GPIO -#endif -#define BOARD_SW3_GPIO_PORT 0U -#ifndef BOARD_SW3_GPIO_PIN -#define BOARD_SW3_GPIO_PIN 4U -#endif -#define BOARD_SW3_NAME "SW3" -#define BOARD_SW3_IRQ PIN_INT0_IRQn -#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler -#define BOARD_SW3_GPIO_PININT_INDEX 0 - -#define BOARD_ARDUINO_INT_IRQ (GINT0_IRQn) -#define BOARD_ARDUINO_I2C_IRQ (FLEXCOMM4_IRQn) -#define BOARD_ARDUINO_I2C_INDEX (4) -/* Board led color mapping */ -#define LOGIC_LED_ON 0U -#define LOGIC_LED_OFF 1U - -#define LED_RED_INIT(output) \ - GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \ - &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_RED */ -#define LED_RED_ON() \ - GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ - 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED_RED */ -#define LED_RED_OFF() \ - GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ - 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED_RED */ -#define LED_RED_TOGGLE() \ - GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ - 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED_RED */ - -#define LED_GREEN_INIT(output) \ - GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \ - &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_GREEN */ -#define LED_GREEN_ON() \ - GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ - 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED_GREEN */ -#define LED_GREEN_OFF() \ - GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ - 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED_GREEN */ -#define LED_GREEN_TOGGLE() \ - GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ - 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED_GREEN */ - -#define LED_BLUE_INIT(output) \ - GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \ - &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_BLUE */ -#define LED_BLUE_ON() \ - GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ - 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED_BLUE */ -#define LED_BLUE_OFF() \ - GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ - 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED_BLUE */ -#define LED_BLUE_TOGGLE() \ - GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ - 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED_BLUE */ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/******************************************************************************* - * API - ******************************************************************************/ - -status_t BOARD_InitDebugConsole(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#endif /* _BOARD_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/clock_config.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/clock_config.c deleted file mode 100644 index 82f4749e9..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/clock_config.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright 2018 NXP. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * How to set up clock using clock driver functions: - * - * 1. Setup clock sources. - * - * 2. Setup voltage for the fastest of the clock outputs - * - * 3. Set up wait states of the flash. - * - * 4. Set up all dividers. - * - * 5. Set up all selectors to provide selected clocks. - */ - -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Clocks v4.1 -processor: LPC51U68 -package_id: LPC51U68JBD64 -mcu_data: ksdk2_0 -processor_version: 3.0.1 -board: LPCXpresso51u68 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -#include "fsl_power.h" -#include "fsl_clock.h" -#include "clock_config.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* System clock frequency. */ -extern uint32_t SystemCoreClock; - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ -void BOARD_InitBootClocks(void) -{ - BOARD_BootClockRUN(); -} - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockRUN -called_from_default_init: true -outputs: -- {id: PLL_clock.outFreq, value: 12 MHz} -- {id: SYSTICK_clock.outFreq, value: 12 MHz} -- {id: System_clock.outFreq, value: 12 MHz} -settings: -- {id: SYSCON.M_MULT.scale, value: '0', locked: true} -- {id: SYSCON.N_DIV.scale, value: '3', locked: true} -- {id: SYSCON.PLL_BYPASS.sel, value: SYSCON.SYSPLLCLKSEL} -- {id: SYSCON.SYSPLLCLKSEL.sel, value: SYSCON.fro_12m} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockRUN configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockRUN configuration - ******************************************************************************/ -void BOARD_BootClockRUN(void) -{ - /*!< Set up the clock sources */ - /*!< Set up FRO */ - POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without - accidentally being below the voltage for current speed */ - POWER_SetVoltageForFreq( - 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up PLL */ - CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Switch PLL clock source selector to FRO12M */ - const pll_setup_t pllSetup = {.syspllctrl = SYSCON_SYSPLLCTRL_UPLIMOFF_MASK | SYSCON_SYSPLLCTRL_BYPASS_MASK, - .syspllndec = SYSCON_SYSPLLNDEC_NDEC(1U), - .syspllpdec = SYSCON_SYSPLLPDEC_PDEC(2U), - .syspllssctrl = {0x0U, (SYSCON_SYSPLLSSCTRL1_MD(0U) | (uint32_t)(kSS_MF_512) | - (uint32_t)(kSS_MR_K0) | (uint32_t)(kSS_MC_NOC))}, - .pllRate = 12000000U, - .flags = PLL_SETUPFLAG_POWERUP}; - CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired values */ - - /* PLL in Fractional/Spread spectrum mode */ - /* SYSTICK is used for waiting for PLL stabilization */ - - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SysTick divider counter and halt it */ - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 3U, false); /*!< Set SysTick divider to value 3 */ - SysTick->LOAD = 27999UL; /*!< Set SysTick count value */ - SysTick->VAL = 0UL; /*!< Reset current count value */ - SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; /*!< Enable SYSTICK */ - while ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != SysTick_CTRL_COUNTFLAG_Msk) - { - } /*!< Waiting for PLL stabilization */ - SysTick->CTRL = 0UL; /*!< Stop SYSTICK */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */ - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ - /*!< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; -} - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO12M ********************** - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFRO12M -outputs: -- {id: SYSTICK_clock.outFreq, value: 12 MHz} -- {id: System_clock.outFreq, value: 12 MHz} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -void BOARD_BootClockFRO12M(void) -{ - /*!< Set up the clock sources */ - /*!< Set up FRO */ - POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without - accidentally being below the voltage for current speed */ - POWER_SetVoltageForFreq( - 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */ - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ - /*!< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; -} - -/******************************************************************************* - ******************* Configuration BOARD_BootClockFROHF48M ********************* - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFROHF48M -outputs: -- {id: SYSTICK_clock.outFreq, value: 48 MHz} -- {id: System_clock.outFreq, value: 48 MHz} -settings: -- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockFROHF48M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFROHF48M configuration - ******************************************************************************/ -void BOARD_BootClockFROHF48M(void) -{ - /*!< Set up the clock sources */ - /*!< Set up FRO */ - POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without - accidentally being below the voltage for current speed */ - POWER_SetVoltageForFreq( - 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */ - - CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */ - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ - /*!< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; -} - -/******************************************************************************* - ******************* Configuration BOARD_BootClockFROHF96M ********************* - ******************************************************************************/ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!Configuration -name: BOARD_BootClockFROHF96M -outputs: -- {id: SYSTICK_clock.outFreq, value: 96 MHz} -- {id: System_clock.outFreq, value: 96 MHz} -settings: -- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} -sources: -- {id: SYSCON.fro_hf.outFreq, value: 96 MHz} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Variables for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -/******************************************************************************* - * Code for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -void BOARD_BootClockFROHF96M(void) -{ - /*!< Set up the clock sources */ - /*!< Set up FRO */ - POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ - CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without - accidentally being below the voltage for current speed */ - POWER_SetVoltageForFreq( - 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ - CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ - - CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */ - - /*!< Set up dividers */ - CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 0U, true); /*!< Reset SYSTICKCLKDIV divider counter and halt it */ - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U, false); /*!< Set SYSTICKCLKDIV divider to value 1 */ - - /*!< Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ - /*!< Set SystemCoreClock variable. */ - SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/clock_config.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/clock_config.h deleted file mode 100644 index e1a03275c..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/clock_config.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright 2018 NXP. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _CLOCK_CONFIG_H_ -#define _CLOCK_CONFIG_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */ -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ - -/******************************************************************************* - ************************ BOARD_InitBootClocks function ************************ - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes default configuration of clocks. - * - */ -void BOARD_InitBootClocks(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ********************** Configuration BOARD_BootClockRUN *********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockRUN configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ - -/******************************************************************************* - * API for BOARD_BootClockRUN configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockRUN(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************** Configuration BOARD_BootClockFRO12M ********************** - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ - -/******************************************************************************* - * API for BOARD_BootClockFRO12M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFRO12M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************* Configuration BOARD_BootClockFROHF48M ********************* - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFROHF48M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */ - -/******************************************************************************* - * API for BOARD_BootClockFROHF48M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFROHF48M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -/******************************************************************************* - ******************* Configuration BOARD_BootClockFROHF96M ********************* - ******************************************************************************/ -/******************************************************************************* - * Definitions for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ - -/******************************************************************************* - * API for BOARD_BootClockFROHF96M configuration - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus*/ - -/*! - * @brief This function executes configuration of clocks. - * - */ -void BOARD_BootClockFROHF96M(void); - -#if defined(__cplusplus) -} -#endif /* __cplusplus*/ - -#endif /* _CLOCK_CONFIG_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/peripherals.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/peripherals.c deleted file mode 100644 index 27ee68aa3..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/peripherals.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Peripherals v1.0 - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ - -/******************************************************************************* - * Included files - ******************************************************************************/ -#include "peripherals.h" - -/******************************************************************************* - * BOARD_InitBootPeripherals function - ******************************************************************************/ -void BOARD_InitBootPeripherals(void) -{ -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/peripherals.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/peripherals.h deleted file mode 100644 index 08ae55e42..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/peripherals.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _PERIPHERALS_H_ -#define _PERIPHERALS_H_ - -#if defined(__cplusplus) -extern "C" { -#endif /*_cplusplus. */ -/******************************************************************************* - * BOARD_InitBootPeripherals function - ******************************************************************************/ -void BOARD_InitBootPeripherals(void); - -#if defined(__cplusplus) -} -#endif /*_cplusplus. */ - -#endif /* _PERIPHERALS_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/pin_mux.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/pin_mux.c deleted file mode 100644 index adb4296e0..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/pin_mux.c +++ /dev/null @@ -1,535 +0,0 @@ -/* - * Copyright 2018 NXP. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -!!GlobalInfo -product: Pins v4.1 -processor: LPC51U68 -package_id: LPC51U68JBD64 -mcu_data: ksdk2_0 -processor_version: 3.0.1 -board: LPCXpresso51u68 -pin_labels: -- {pin_num: '1', pin_signal: PIO0_23/FC1_RTS_SCL_SSEL1/CTIMER0_CAP0/UTICK_CAP1, label: 'J4[9]/JS3[1]/JS4[3]/U10[7]/U12[D6]/BRIDGE_SCL', identifier: BRIDGE_SCL;LINK2MCU_SCL} -- {pin_num: '2', pin_signal: PIO0_24/FC1_CTS_SDA_SSEL0/CTIMER0_CAP1/CTIMER0_MAT0, label: 'J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP', identifier: SW1;BRIDGE_SDA_WAKEUP;LINK2MCU_SDA} -- {pin_num: '13', pin_signal: PIO0_31/FC2_CTS_SDA_SSEL0/CTIMER0_CAP3/CTIMER0_MAT3/ADC0_2, label: 'J2[17]/J3[2]/P1[7]/U3[4]/SW2/P0_31-PDM0_CLK-ISP0_EN', identifier: SW2} -- {pin_num: '38', pin_signal: PIO0_4/FC0_SCK/FC3_SSEL2/CTIMER0_CAP2, label: 'J4[7]/U9[12]/SW3/BRIDGE_T_INTR-ISP1', identifier: SW3;BRIDGE_T_INTR} -- {pin_num: '29', pin_signal: PIO1_9/FC3_RXD_SDA_MOSI/CTIMER0_CAP2/USB0_UP_LED, label: 'J9[5]/D2[3]/P1_9-BLUE_LED', identifier: LED_BLUE} -- {pin_num: '30', pin_signal: PIO1_10/FC6_TXD_SCL_MISO_WS/SCT0_OUT4/FC1_SCK/USB0_FRAME, label: 'J9[8]/D2[4]/P1_10-SCT4-LED_GREEN', identifier: LED_GREEN} -- {pin_num: '11', pin_signal: PIO0_29/FC1_RXD_SDA_MOSI/SCT0_OUT2/CTIMER0_MAT3/CTIMER0_CAP1/CTIMER0_MAT1/ADC0_0, label: 'J2[5]/D2[1]/P0_29-CT32B0_MAT3-RED', identifier: LED_RED} -- {pin_num: '3', pin_signal: PIO0_25/FC4_RTS_SCL_SSEL1/FC6_CTS_SDA_SSEL0/CTIMER0_CAP2/CTIMER1_CAP1, label: 'J1[1]/JS4[1]/U10[7]/P0_25-FC4_SCLX', identifier: FC4_SCLX} -- {pin_num: '4', pin_signal: PIO0_26/FC4_CTS_SDA_SSEL0/CTIMER0_CAP3, label: 'J1[3]/JS5[1]/U10[5]/P0_26-FC4_SDAX', identifier: FC4_SDAX} -- {pin_num: '58', pin_signal: PIO0_18/FC5_TXD_SCL_MISO/SCT0_OUT0/CTIMER0_MAT0, label: 'J1[11]/U5[2]/P0_18-FC5_TXD_SCL_MISO', identifier: SPI_FLASH_MISO} -- {pin_num: '59', pin_signal: PIO0_19/FC5_SCK/SCT0_OUT1/CTIMER0_MAT1, label: 'J1[9]/J2[8]/U5[6]/P0_19-FC5_SCK-SPIFI_CSn', identifier: SPI_FLASH_SCK} -- {pin_num: '60', pin_signal: PIO0_20/FC5_RXD_SDA_MOSI/FC0_SCK/CTIMER3_CAP0, label: 'J1[13]/U5[5]/P0_20-FC5_RXD_SDA_MOSI', identifier: SPI_FLASH_MOSI} -- {pin_num: '16', pin_signal: PIO1_2/MCLK/FC7_SSEL3/SCT0_OUT5/FC5_SSEL3/FC4_RXD_SDA_MOSI/ADC0_5, label: 'J9[7]/JS8[1]/U5[1]/P1_2-FC5_SSEL3', identifier: FC5_SSEL3} -- {pin_num: '46', pin_signal: PIO0_11/FC3_SCK/FC6_RXD_SDA_MOSI_DATA, label: 'J4[4]/U9[13]/BRIDGE_T_SCK', identifier: BRIDGE_T_SCK} -- {pin_num: '47', pin_signal: PIO0_12/FC3_RXD_SDA_MOSI/FC6_TXD_SCL_MISO_WS, label: 'J4[2]/U9[11]/BRIDGE_T_MOSI', identifier: BRIDGE_T_MOSI} -- {pin_num: '48', pin_signal: PIO0_13/FC3_TXD_SCL_MISO/SCT0_OUT4, label: 'J4[3]/U15[4]/BRIDGE_T_MISO', identifier: BRIDGE_T_MISO} -- {pin_num: '63', pin_signal: PIO0_22/CLKIN/FC0_RXD_SDA_MOSI/CTIMER3_MAT3, label: 'J4[8]/P0_22-BRIDGE_GPIO', identifier: BRIDGE_GPIO} -- {pin_num: '31', pin_signal: PIO0_0/FC0_RXD_SDA_MOSI/FC3_CTS_SDA_SSEL0/CTIMER0_CAP0/SCT0_OUT3, label: 'U18[4]/TO_MUX_P0_0-ISP_RX', identifier: DEBUG_UART_RX} -- {pin_num: '5', pin_signal: USB0_DP, label: 'J5[3]/U7[2]/USB_DP', identifier: USB_DP} -- {pin_num: '6', pin_signal: USB0_DM, label: 'J5[2]/U7[3]/USB_DM', identifier: USB_DM} -- {pin_num: '32', pin_signal: PIO0_1/FC0_TXD_SCL_MISO/FC3_RTS_SCL_SSEL1/CTIMER0_CAP1/SCT0_OUT1, label: 'U6[4]/U22[3]/P0_1-ISP_TX', identifier: DEBUG_UART_TX} -- {pin_num: '53', pin_signal: PIO0_17/FC3_SSEL3/FC6_RTS_SCL_SSEL1/CTIMER3_MAT2/SWDIO, label: 'J2[6]/P1[2]/U2[5]/U14[4]/IF_TMS_SWDIO-SPIFI_IO0', identifier: DEBUG_SWD_SWDIO} -- {pin_num: '52', pin_signal: PIO0_16/FC3_SSEL2/FC6_CTS_SDA_SSEL0/CTIMER3_MAT1/SWCLK, label: 'J2[4]/JS28/U4[4]/TCK-SWDCLK_TRGT-SPIFI_IO1', identifier: DEBUG_SWD_SWDCLK} -- {pin_num: '50', pin_signal: PIO0_15/FC3_RTS_SCL_SSEL1/FC4_SCK, label: 'J2[10]/JS30/U4[12]/TDO-SWO_TRGT-SPIFI_IO2', identifier: DEBUG_SWD_SWO} -- {pin_num: '49', pin_signal: PIO0_14/FC3_CTS_SDA_SSEL0/SCT0_OUT5/FC1_SCK, label: 'J2[12]/J4[1]/U9[14]/BRIDGE_T_SSEL-SPIFI_IO3', identifier: BRIDGE_T_SSEL} -- {pin_num: '26', pin_signal: PIO1_6/FC7_SCK/CTIMER1_CAP2/CTIMER1_MAT2/USB0_VBUS/ADC0_9, label: 'J1[14]/J5[1]/JP10[2]/P1_6-FC7_SCK-USB_VBUS', identifier: USB_VBUS} -- {pin_num: '7', pin_signal: PIO1_16/CTIMER0_MAT0/CTIMER0_CAP0/FC7_RTS_SCL_SSEL1, label: 'J1[19]/P1_16-CT32B0_MAT0-GYRO_INT1'} -- {pin_num: '8', pin_signal: VDD8, label: VDD_LPC54u68_IC} -- {pin_num: '9', pin_signal: VSS9, label: GND} -- {pin_num: '10', pin_signal: PIO1_17/MCLK/UTICK_CAP3, label: 'J9[9]/P1_17-IR_LEARN_EN'} -- {pin_num: '12', pin_signal: PIO0_30/FC1_TXD_SCL_MISO/SCT0_OUT3/CTIMER0_MAT2/CTIMER0_CAP2/ADC0_1, label: 'J9[2]/P0_30-ADC1'} -- {pin_num: '14', pin_signal: PIO1_0/FC2_RTS_SCL_SSEL1/CTIMER3_MAT1/CTIMER0_CAP0/ADC0_3, label: 'J2[3]/P1_0-PDM0_DATA-CT32B3_MAT1'} -- {pin_num: '15', pin_signal: PIO1_1/SCT0_OUT4/FC5_SSEL2/FC4_TXD_SCL_MISO/ADC0_4, label: 'J1[15]/P1_1-FC5_SSEL2'} -- {pin_num: '17', pin_signal: PIO1_3/FC7_SSEL2/SCT0_OUT6/FC3_SCK/CTIMER0_CAP1/USB0_UP_LED/ADC0_6, label: 'J2[20]/P1_3-FC7_SSEL2-CT32B0_CAP1'} -- {pin_num: '18', pin_signal: PIO1_4/FC7_RTS_SCL_SSEL1/SCT0_OUT7/FC3_TXD_SCL_MISO/CTIMER0_MAT1/ADC0_7, label: 'J2[18]/J9[10]/P1_4-ADC7-PDM1_CLK-FC7_RTS-FC3_TXD'} -- {pin_num: '19', pin_signal: PIO1_5/FC7_CTS_SDA_SSEL0/CTIMER1_CAP0/CTIMER1_MAT3/USB0_FRAME/ADC0_8, label: 'J2[16]/J9[12]/P1_5-ADC8-PDM1_DAT-FC7_CTS'} -- {pin_num: '20', pin_signal: VSSA, label: GND} -- {pin_num: '21', pin_signal: VREFN, label: 'SJ1[2]/P4[3]/GND'} -- {pin_num: '22', pin_signal: VREFP, label: 'SJ2[2]/P4[1]/VDD_LPC541u68_IC'} -- {pin_num: '23', pin_signal: VDDA, label: VDD_LPC54u68_IC} -- {pin_num: '24', pin_signal: VDD24, label: VDD_LPC54u68_IC} -- {pin_num: '25', pin_signal: VSS25, label: GND} -- {pin_num: '27', pin_signal: PIO1_7/FC7_RXD_SDA_MOSI_DATA/CTIMER1_MAT2/CTIMER1_CAP2/ADC0_10, label: 'J1[10]/P1_7-FC7_RXD_SDA_MOSI_DATA'} -- {pin_num: '28', pin_signal: PIO1_8/FC7_TXD_SCL_MISO_WS/CTIMER1_MAT3/CTIMER1_CAP3/ADC0_11, label: 'J1[12]/J9[6]/P1_8-ADC11-FC7_TXD_SCL_MISO_FRAME'} -- {pin_num: '33', pin_signal: RTCXIN, label: 'JS18[2]/Y1/RTCXIN'} -- {pin_num: '34', pin_signal: VDD34, label: VDD_LPC54u68_IC} -- {pin_num: '35', pin_signal: RTCXOUT, label: JS17/Y1/RTCXOUT} -- {pin_num: '36', pin_signal: PIO0_2/FC0_CTS_SDA_SSEL0/FC2_SSEL3, label: 'J9[1]/P0_2-GPIO_SPI_CS'} -- {pin_num: '37', pin_signal: PIO0_3/FC0_RTS_SCL_SSEL1/FC2_SSEL2/CTIMER1_MAT3, label: 'J9[3]/P0_3-GPIO_SPI_CS'} -- {pin_num: '39', pin_signal: PIO0_5/FC6_RXD_SDA_MOSI_DATA/SCT0_OUT6/CTIMER0_MAT0, label: 'J1[20]/P0_5-FC6_RXD_SDA_MOSI_DATA'} -- {pin_num: '40', pin_signal: PIO0_6/FC6_TXD_SCL_MISO_WS/CTIMER0_MAT1/UTICK_CAP0, label: 'J1[18]/P0_6-FC6_TXD_SCL_MISO_FRAME'} -- {pin_num: '41', pin_signal: PIO0_7/FC6_SCK/SCT0_OUT0/CTIMER0_MAT2/CTIMER0_CAP2, label: 'J1[16]/P0_7-FC6_SCK'} -- {pin_num: '42', pin_signal: PIO1_11/FC6_RTS_SCL_SSEL1/CTIMER1_CAP0/FC4_SCK/USB0_VBUS, label: 'J2[19]/P1_11-FC6_RTS_SSEL1-MAG_DRDY'} -- {pin_num: '43', pin_signal: PIO0_8/FC2_RXD_SDA_MOSI/SCT0_OUT1/CTIMER0_MAT3, label: 'J2[15]/P0_8-FC2_RXD_SDA_MOSI'} -- {pin_num: '44', pin_signal: PIO0_9/FC2_TXD_SCL_MISO/SCT0_OUT2/CTIMER3_CAP0/FC3_CTS_SDA_SSEL0, label: 'J2[13]/P0_9-FC2_TXD_SCL_MISO'} -- {pin_num: '45', pin_signal: PIO0_10/FC2_SCK/SCT0_OUT3/CTIMER3_MAT0, label: 'J2[11]/P0_10-FC2_SCK-CT32B3_MAT0'} -- {pin_num: '51', pin_signal: PIO1_12/FC5_RXD_SDA_MOSI/CTIMER1_MAT0/FC7_SCK/UTICK_CAP2, label: 'J2[9]/P1_12-CT32B1_MAT0-ACCl_INT1'} -- {pin_num: '54', pin_signal: PIO1_13/FC5_TXD_SCL_MISO/CTIMER1_MAT1/FC7_RXD_SDA_MOSI_DATA, label: 'J2[7]/P1_13-CT32B1_MAT1'} -- {pin_num: '55', pin_signal: VSS55, label: GND} -- {pin_num: '56', pin_signal: VDD56, label: VDD_LPC54u68_IC} -- {pin_num: '57', pin_signal: PIO1_14/FC2_RXD_SDA_MOSI/SCT0_OUT7/FC7_TXD_SCL_MISO_WS, label: 'J2[1]/P1_14-SCTO7'} -- {pin_num: '61', pin_signal: PIO0_21/CLKOUT/FC0_TXD_SCL_MISO/CTIMER3_MAT0, label: 'J2[2]/P0_21-CLKOUT-SPIFI_CLK'} -- {pin_num: '62', pin_signal: PIO1_15/SCT0_OUT5/CTIMER1_CAP3/FC7_CTS_SDA_SSEL0, label: 'J1[17]/P1_15-SCTO5-FC7_CTS'} -- {pin_num: '64', pin_signal: RESET, label: 'J3[1]/J8[9]/J8[10]/JP7[1]/JS9[1]/JS12[1]/JS29/D4[1]/U4[8]/U5[7]/U10[22]/SW4/nRESET_TRGT', identifier: RESET} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -#include "fsl_common.h" -#include "pin_mux.h" - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitBootPins - * Description : Calls initialization functions. - * - *END**************************************************************************/ -void BOARD_InitBootPins(void) { - BOARD_InitPins(); - BOARD_InitDEBUG_UARTPins(); -} - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPins: -- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'true'} -- pin_list: [] - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitPins - * Description : Configures pin routing and optionally pin electrical features. - * - *END**************************************************************************/ -void BOARD_InitPins(void) { /* Function assigned for the Cortex-M0P */ -} - - -#define PIO023_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO023_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO023_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ -#define PIO024_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO024_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO024_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitLink2MCUPins: -- options: {prefix: BOARD_, coreID: core0, enableClock: 'false'} -- pin_list: - - {pin_num: '1', peripheral: FLEXCOMM1, signal: RTS_SCL_SSEL1, pin_signal: PIO0_23/FC1_RTS_SCL_SSEL1/CTIMER0_CAP0/UTICK_CAP1, identifier: LINK2MCU_SCL, i2c_slew: i2c} - - {pin_num: '2', peripheral: FLEXCOMM1, signal: CTS_SDA_SSEL0, pin_signal: PIO0_24/FC1_CTS_SDA_SSEL0/CTIMER0_CAP1/CTIMER0_MAT0, identifier: LINK2MCU_SDA, i2c_slew: i2c} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitLink2MCUPins - * Description : Configures pin routing and optionally pin electrical features. - * - *END**************************************************************************/ -void BOARD_InitLink2MCUPins(void) { /* Function assigned for the Cortex-M0P */ - IOCON->PIO[0][23] = ((IOCON->PIO[0][23] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO023_FUNC_ALT1) /* Selects pin function.: PORT023 (pin 1) is configured as FC1_RTS_SCL_SSEL1 */ - | IOCON_PIO_I2CSLEW(PIO023_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ - | IOCON_PIO_DIGIMODE(PIO023_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][24] = ((IOCON->PIO[0][24] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO024_FUNC_ALT1) /* Selects pin function.: PORT024 (pin 2) is configured as FC1_CTS_SDA_SSEL0 */ - | IOCON_PIO_I2CSLEW(PIO024_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ - | IOCON_PIO_DIGIMODE(PIO024_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); -} - - -#define PIO024_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO024_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ -#define PIO031_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO031_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ -#define PIO04_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO04_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitBUTTONsPins: -- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: '2', peripheral: GPIO, signal: 'PIO0, 24', pin_signal: PIO0_24/FC1_CTS_SDA_SSEL0/CTIMER0_CAP1/CTIMER0_MAT0, identifier: SW1, direction: INPUT} - - {pin_num: '13', peripheral: GPIO, signal: 'PIO0, 31', pin_signal: PIO0_31/FC2_CTS_SDA_SSEL0/CTIMER0_CAP3/CTIMER0_MAT3/ADC0_2, direction: INPUT} - - {pin_num: '38', peripheral: GPIO, signal: 'PIO0, 4', pin_signal: PIO0_4/FC0_SCK/FC3_SSEL2/CTIMER0_CAP2, identifier: SW3, direction: INPUT} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitBUTTONsPins - * Description : Configures pin routing and optionally pin electrical features. - * - *END**************************************************************************/ -void BOARD_InitBUTTONsPins(void) { /* Function assigned for the Cortex-M0P */ - CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ - - IOCON->PIO[0][24] = ((IOCON->PIO[0][24] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO024_FUNC_ALT0) /* Selects pin function.: PORT024 (pin 2) is configured as PIO0_24 */ - | IOCON_PIO_DIGIMODE(PIO024_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][31] = ((IOCON->PIO[0][31] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO031_FUNC_ALT0) /* Selects pin function.: PORT031 (pin 13) is configured as PIO0_31 */ - | IOCON_PIO_DIGIMODE(PIO031_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][4] = ((IOCON->PIO[0][4] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO04_FUNC_ALT0) /* Selects pin function.: PORT04 (pin 38) is configured as PIO0_4 */ - | IOCON_PIO_DIGIMODE(PIO04_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); -} - - -#define PIO029_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO029_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ -#define PIO110_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO110_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ -#define PIO19_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO19_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitLEDsPins: -- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: '29', peripheral: GPIO, signal: 'PIO1, 9', pin_signal: PIO1_9/FC3_RXD_SDA_MOSI/CTIMER0_CAP2/USB0_UP_LED, direction: OUTPUT} - - {pin_num: '30', peripheral: GPIO, signal: 'PIO1, 10', pin_signal: PIO1_10/FC6_TXD_SCL_MISO_WS/SCT0_OUT4/FC1_SCK/USB0_FRAME, direction: OUTPUT} - - {pin_num: '11', peripheral: GPIO, signal: 'PIO0, 29', pin_signal: PIO0_29/FC1_RXD_SDA_MOSI/SCT0_OUT2/CTIMER0_MAT3/CTIMER0_CAP1/CTIMER0_MAT1/ADC0_0, direction: OUTPUT} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitLEDsPins - * Description : Configures pin routing and optionally pin electrical features. - * - *END**************************************************************************/ -void BOARD_InitLEDsPins(void) { /* Function assigned for the Cortex-M0P */ - CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ - - IOCON->PIO[0][29] = ((IOCON->PIO[0][29] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO029_FUNC_ALT0) /* Selects pin function.: PORT029 (pin 11) is configured as PIO0_29 */ - | IOCON_PIO_DIGIMODE(PIO029_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[1][10] = ((IOCON->PIO[1][10] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO110_FUNC_ALT0) /* Selects pin function.: PORT110 (pin 30) is configured as PIO1_10 */ - | IOCON_PIO_DIGIMODE(PIO110_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[1][9] = ((IOCON->PIO[1][9] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO19_FUNC_ALT0) /* Selects pin function.: PORT19 (pin 29) is configured as PIO1_9 */ - | IOCON_PIO_DIGIMODE(PIO19_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); -} - - -#define PIO025_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO025_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO025_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ -#define PIO026_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO026_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO026_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitSecureMCUPins: -- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: '3', peripheral: FLEXCOMM4, signal: RTS_SCL_SSEL1, pin_signal: PIO0_25/FC4_RTS_SCL_SSEL1/FC6_CTS_SDA_SSEL0/CTIMER0_CAP2/CTIMER1_CAP1, i2c_slew: i2c} - - {pin_num: '4', peripheral: FLEXCOMM4, signal: CTS_SDA_SSEL0, pin_signal: PIO0_26/FC4_CTS_SDA_SSEL0/CTIMER0_CAP3, i2c_slew: i2c} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitSecureMCUPins - * Description : Configures pin routing and optionally pin electrical features. - * - *END**************************************************************************/ -void BOARD_InitSecureMCUPins(void) { /* Function assigned for the Cortex-M0P */ - CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ - - IOCON->PIO[0][25] = ((IOCON->PIO[0][25] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO025_FUNC_ALT1) /* Selects pin function.: PORT025 (pin 3) is configured as FC4_RTS_SCL_SSEL1 */ - | IOCON_PIO_I2CSLEW(PIO025_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ - | IOCON_PIO_DIGIMODE(PIO025_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][26] = ((IOCON->PIO[0][26] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO026_FUNC_ALT1) /* Selects pin function.: PORT026 (pin 4) is configured as FC4_CTS_SDA_SSEL0 */ - | IOCON_PIO_I2CSLEW(PIO026_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ - | IOCON_PIO_DIGIMODE(PIO026_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); -} - - -#define PIO018_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO018_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO019_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO019_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO020_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO020_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO12_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO12_FUNC_ALT4 0x04u /*!< Selects pin function.: Alternative connection 4. */ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitSPI_FLASHPins: -- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: '58', peripheral: FLEXCOMM5, signal: TXD_SCL_MISO, pin_signal: PIO0_18/FC5_TXD_SCL_MISO/SCT0_OUT0/CTIMER0_MAT0} - - {pin_num: '59', peripheral: FLEXCOMM5, signal: SCK, pin_signal: PIO0_19/FC5_SCK/SCT0_OUT1/CTIMER0_MAT1} - - {pin_num: '60', peripheral: FLEXCOMM5, signal: RXD_SDA_MOSI, pin_signal: PIO0_20/FC5_RXD_SDA_MOSI/FC0_SCK/CTIMER3_CAP0} - - {pin_num: '16', peripheral: FLEXCOMM5, signal: SSEL3, pin_signal: PIO1_2/MCLK/FC7_SSEL3/SCT0_OUT5/FC5_SSEL3/FC4_RXD_SDA_MOSI/ADC0_5} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitSPI_FLASHPins - * Description : Configures pin routing and optionally pin electrical features. - * - *END**************************************************************************/ -void BOARD_InitSPI_FLASHPins(void) { /* Function assigned for the Cortex-M0P */ - CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ - - IOCON->PIO[0][18] = ((IOCON->PIO[0][18] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO018_FUNC_ALT1) /* Selects pin function.: PORT018 (pin 58) is configured as FC5_TXD_SCL_MISO */ - | IOCON_PIO_DIGIMODE(PIO018_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][19] = ((IOCON->PIO[0][19] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO019_FUNC_ALT1) /* Selects pin function.: PORT019 (pin 59) is configured as FC5_SCK */ - | IOCON_PIO_DIGIMODE(PIO019_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][20] = ((IOCON->PIO[0][20] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO020_FUNC_ALT1) /* Selects pin function.: PORT020 (pin 60) is configured as FC5_RXD_SDA_MOSI */ - | IOCON_PIO_DIGIMODE(PIO020_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[1][2] = ((IOCON->PIO[1][2] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO12_FUNC_ALT4) /* Selects pin function.: PORT12 (pin 16) is configured as FC5_SSEL3 */ - | IOCON_PIO_DIGIMODE(PIO12_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); -} - - -#define PIO011_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO011_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO012_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO012_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO013_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO013_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO014_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO014_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO022_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO022_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ -#define PIO023_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO023_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO023_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ -#define PIO024_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO024_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO024_I2CSLEW_I2C_MODE 0x00u /*!< Controls slew rate of I2C pin.: I2C mode. */ -#define PIO04_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO04_FUNC_ALT0 0x00u /*!< Selects pin function.: Alternative connection 0. */ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitPMod_SPI_I2C_BRIDGEPins: -- options: {coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: '38', peripheral: GPIO, signal: 'PIO0, 4', pin_signal: PIO0_4/FC0_SCK/FC3_SSEL2/CTIMER0_CAP2, identifier: BRIDGE_T_INTR} - - {pin_num: '46', peripheral: FLEXCOMM3, signal: SCK, pin_signal: PIO0_11/FC3_SCK/FC6_RXD_SDA_MOSI_DATA, direction: OUTPUT} - - {pin_num: '47', peripheral: FLEXCOMM3, signal: RXD_SDA_MOSI, pin_signal: PIO0_12/FC3_RXD_SDA_MOSI/FC6_TXD_SCL_MISO_WS, direction: OUTPUT} - - {pin_num: '48', peripheral: FLEXCOMM3, signal: TXD_SCL_MISO, pin_signal: PIO0_13/FC3_TXD_SCL_MISO/SCT0_OUT4, direction: INPUT} - - {pin_num: '49', peripheral: FLEXCOMM3, signal: CTS_SDA_SSEL0, pin_signal: PIO0_14/FC3_CTS_SDA_SSEL0/SCT0_OUT5/FC1_SCK, direction: OUTPUT} - - {pin_num: '63', peripheral: GPIO, signal: 'PIO0, 22', pin_signal: PIO0_22/CLKIN/FC0_RXD_SDA_MOSI/CTIMER3_MAT3} - - {pin_num: '1', peripheral: FLEXCOMM1, signal: RTS_SCL_SSEL1, pin_signal: PIO0_23/FC1_RTS_SCL_SSEL1/CTIMER0_CAP0/UTICK_CAP1, identifier: BRIDGE_SCL, i2c_slew: i2c} - - {pin_num: '2', peripheral: FLEXCOMM1, signal: CTS_SDA_SSEL0, pin_signal: PIO0_24/FC1_CTS_SDA_SSEL0/CTIMER0_CAP1/CTIMER0_MAT0, identifier: BRIDGE_SDA_WAKEUP, i2c_slew: i2c} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitPMod_SPI_I2C_BRIDGEPins - * Description : Configures pin routing and optionally pin electrical features. - * - *END**************************************************************************/ -void BOARD_InitPMod_SPI_I2C_BRIDGEPins(void) { /* Function assigned for the Cortex-M0P */ - CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ - - IOCON->PIO[0][11] = ((IOCON->PIO[0][11] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO011_FUNC_ALT1) /* Selects pin function.: PORT011 (pin 46) is configured as FC3_SCK */ - | IOCON_PIO_DIGIMODE(PIO011_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][12] = ((IOCON->PIO[0][12] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO012_FUNC_ALT1) /* Selects pin function.: PORT012 (pin 47) is configured as FC3_RXD_SDA_MOSI */ - | IOCON_PIO_DIGIMODE(PIO012_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][13] = ((IOCON->PIO[0][13] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO013_FUNC_ALT1) /* Selects pin function.: PORT013 (pin 48) is configured as FC3_TXD_SCL_MISO */ - | IOCON_PIO_DIGIMODE(PIO013_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][14] = ((IOCON->PIO[0][14] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO014_FUNC_ALT1) /* Selects pin function.: PORT014 (pin 49) is configured as FC3_CTS_SDA_SSEL0 */ - | IOCON_PIO_DIGIMODE(PIO014_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][22] = ((IOCON->PIO[0][22] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO022_FUNC_ALT0) /* Selects pin function.: PORT022 (pin 63) is configured as PIO0_22 */ - | IOCON_PIO_DIGIMODE(PIO022_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][23] = ((IOCON->PIO[0][23] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO023_FUNC_ALT1) /* Selects pin function.: PORT023 (pin 1) is configured as FC1_RTS_SCL_SSEL1 */ - | IOCON_PIO_I2CSLEW(PIO023_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ - | IOCON_PIO_DIGIMODE(PIO023_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][24] = ((IOCON->PIO[0][24] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_I2CSLEW_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO024_FUNC_ALT1) /* Selects pin function.: PORT024 (pin 2) is configured as FC1_CTS_SDA_SSEL0 */ - | IOCON_PIO_I2CSLEW(PIO024_I2CSLEW_I2C_MODE) /* Controls slew rate of I2C pin.: I2C mode. */ - | IOCON_PIO_DIGIMODE(PIO024_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][4] = ((IOCON->PIO[0][4] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO04_FUNC_ALT0) /* Selects pin function.: PORT04 (pin 38) is configured as PIO0_4 */ - | IOCON_PIO_DIGIMODE(PIO04_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); -} - - -#define PIO16_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO16_FUNC_ALT7 0x07u /*!< Selects pin function.: Alternative connection 7. */ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitUSBPins: -- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: '5', peripheral: USB0, signal: USB_DP, pin_signal: USB0_DP} - - {pin_num: '6', peripheral: USB0, signal: USB_DM, pin_signal: USB0_DM} - - {pin_num: '26', peripheral: USB0, signal: USB_VBUS, pin_signal: PIO1_6/FC7_SCK/CTIMER1_CAP2/CTIMER1_MAT2/USB0_VBUS/ADC0_9} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitUSBPins - * Description : Configures pin routing and optionally pin electrical features. - * - *END**************************************************************************/ -void BOARD_InitUSBPins(void) { /* Function assigned for the Cortex-M0P */ - CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ - - IOCON->PIO[1][6] = ((IOCON->PIO[1][6] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO16_FUNC_ALT7) /* Selects pin function.: PORT16 (pin 26) is configured as USB0_VBUS */ - | IOCON_PIO_DIGIMODE(PIO16_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); -} - - -#define PIO00_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO00_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ -#define PIO01_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO01_FUNC_ALT1 0x01u /*!< Selects pin function.: Alternative connection 1. */ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitDEBUG_UARTPins: -- options: {callFromInitBoot: 'true', prefix: BOARD_, coreID: core0, enableClock: 'false'} -- pin_list: - - {pin_num: '32', peripheral: FLEXCOMM0, signal: TXD_SCL_MISO, pin_signal: PIO0_1/FC0_TXD_SCL_MISO/FC3_RTS_SCL_SSEL1/CTIMER0_CAP1/SCT0_OUT1, direction: OUTPUT} - - {pin_num: '31', peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI, pin_signal: PIO0_0/FC0_RXD_SDA_MOSI/FC3_CTS_SDA_SSEL0/CTIMER0_CAP0/SCT0_OUT3, direction: INPUT} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitDEBUG_UARTPins - * Description : Configures pin routing and optionally pin electrical features. - * - *END**************************************************************************/ -void BOARD_InitDEBUG_UARTPins(void) { /* Function assigned for the Cortex-M0P */ - CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ - - IOCON->PIO[0][0] = ((IOCON->PIO[0][0] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO00_FUNC_ALT1) /* Selects pin function.: PORT00 (pin 31) is configured as FC0_RXD_SDA_MOSI */ - | IOCON_PIO_DIGIMODE(PIO00_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][1] = ((IOCON->PIO[0][1] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO01_FUNC_ALT1) /* Selects pin function.: PORT01 (pin 32) is configured as FC0_TXD_SCL_MISO */ - | IOCON_PIO_DIGIMODE(PIO01_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); -} - - -#define PIO016_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO016_FUNC_ALT5 0x05u /*!< Selects pin function.: Alternative connection 5. */ -#define PIO017_DIGIMODE_DIGITAL 0x01u /*!< Select Analog/Digital mode.: Digital mode. */ -#define PIO017_FUNC_ALT5 0x05u /*!< Selects pin function.: Alternative connection 5. */ - -/* - * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* -BOARD_InitSWD_DEBUGPins: -- options: {prefix: BOARD_, coreID: core0, enableClock: 'true'} -- pin_list: - - {pin_num: '53', peripheral: SWD, signal: SWDIO, pin_signal: PIO0_17/FC3_SSEL3/FC6_RTS_SCL_SSEL1/CTIMER3_MAT2/SWDIO} - - {pin_num: '52', peripheral: SWD, signal: SWCLK, pin_signal: PIO0_16/FC3_SSEL2/FC6_CTS_SDA_SSEL0/CTIMER3_MAT1/SWCLK} - * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** - */ - -/*FUNCTION********************************************************************** - * - * Function Name : BOARD_InitSWD_DEBUGPins - * Description : Configures pin routing and optionally pin electrical features. - * - *END**************************************************************************/ -void BOARD_InitSWD_DEBUGPins(void) { /* Function assigned for the Cortex-M0P */ - CLOCK_EnableClock(kCLOCK_Iocon); /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */ - - IOCON->PIO[0][16] = ((IOCON->PIO[0][16] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO016_FUNC_ALT5) /* Selects pin function.: PORT016 (pin 52) is configured as SWCLK */ - | IOCON_PIO_DIGIMODE(PIO016_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); - IOCON->PIO[0][17] = ((IOCON->PIO[0][17] & - (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK))) /* Mask bits to zero which are setting */ - | IOCON_PIO_FUNC(PIO017_FUNC_ALT5) /* Selects pin function.: PORT017 (pin 53) is configured as SWDIO */ - | IOCON_PIO_DIGIMODE(PIO017_DIGIMODE_DIGITAL) /* Select Analog/Digital mode.: Digital mode. */ - ); -} - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/pin_mux.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/pin_mux.h deleted file mode 100644 index 9a24068b5..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/board/boards/pin_mux.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Copyright 2018 NXP. - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _PIN_MUX_H_ -#define _PIN_MUX_H_ - - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Direction type */ -typedef enum _pin_mux_direction -{ - kPIN_MUX_DirectionInput = 0U, /* Input direction */ - kPIN_MUX_DirectionOutput = 1U, /* Output direction */ - kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */ -} pin_mux_direction_t; - -/*! - * @addtogroup pin_mux - * @{ - */ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Calls initialization functions. - * - */ -void BOARD_InitBootPins(void); - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitPins(void); /* Function assigned for the Cortex-M0P */ - -/* FC1_RTS_SCL_SSEL1 (number 1), J4[9]/JS3[1]/JS4[3]/U10[7]/U12[D6]/BRIDGE_SCL */ -#define BOARD_LINK2MCU_SCL_PERIPHERAL FLEXCOMM1 /*!< Device name: FLEXCOMM1 */ -#define BOARD_LINK2MCU_SCL_SIGNAL RTS_SCL_SSEL1 /*!< FLEXCOMM1 signal: RTS_SCL_SSEL1 */ -#define BOARD_LINK2MCU_SCL_PIN_NAME FC1_RTS_SCL_SSEL1 /*!< Pin name */ -#define BOARD_LINK2MCU_SCL_LABEL "J4[9]/JS3[1]/JS4[3]/U10[7]/U12[D6]/BRIDGE_SCL" /*!< Label */ -#define BOARD_LINK2MCU_SCL_NAME "LINK2MCU_SCL" /*!< Identifier name */ - -/* FC1_CTS_SDA_SSEL0 (number 2), J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP */ -#define BOARD_LINK2MCU_SDA_PERIPHERAL FLEXCOMM1 /*!< Device name: FLEXCOMM1 */ -#define BOARD_LINK2MCU_SDA_SIGNAL CTS_SDA_SSEL0 /*!< FLEXCOMM1 signal: CTS_SDA_SSEL0 */ -#define BOARD_LINK2MCU_SDA_PIN_NAME FC1_CTS_SDA_SSEL0 /*!< Pin name */ -#define BOARD_LINK2MCU_SDA_LABEL "J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP" /*!< Label */ -#define BOARD_LINK2MCU_SDA_NAME "LINK2MCU_SDA" /*!< Identifier name */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitLink2MCUPins(void); /* Function assigned for the Cortex-M0P */ - -/* PIO0_24 (number 2), J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP */ -#define BOARD_SW1_GPIO GPIO /*!< GPIO device name: GPIO */ -#define BOARD_SW1_PORT 0U /*!< PORT device index: 0 */ -#define BOARD_SW1_GPIO_PIN 24U /*!< PIO0 pin index: 24 */ -#define BOARD_SW1_PIN_NAME PIO0_24 /*!< Pin name */ -#define BOARD_SW1_LABEL "J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP" /*!< Label */ -#define BOARD_SW1_NAME "SW1" /*!< Identifier name */ -#define BOARD_SW1_DIRECTION kPIN_MUX_DirectionInput /*!< Direction */ - -/* PIO0_31 (number 13), J2[17]/J3[2]/P1[7]/U3[4]/SW2/P0_31-PDM0_CLK-ISP0_EN */ -#define BOARD_SW2_GPIO GPIO /*!< GPIO device name: GPIO */ -#define BOARD_SW2_PORT 0U /*!< PORT device index: 0 */ -#define BOARD_SW2_GPIO_PIN 31U /*!< PIO0 pin index: 31 */ -#define BOARD_SW2_PIN_NAME PIO0_31 /*!< Pin name */ -#define BOARD_SW2_LABEL "J2[17]/J3[2]/P1[7]/U3[4]/SW2/P0_31-PDM0_CLK-ISP0_EN" /*!< Label */ -#define BOARD_SW2_NAME "SW2" /*!< Identifier name */ -#define BOARD_SW2_DIRECTION kPIN_MUX_DirectionInput /*!< Direction */ - -/* PIO0_4 (number 38), J4[7]/U9[12]/SW3/BRIDGE_T_INTR-ISP1 */ -#define BOARD_SW3_GPIO GPIO /*!< GPIO device name: GPIO */ -#define BOARD_SW3_PORT 0U /*!< PORT device index: 0 */ -#define BOARD_SW3_GPIO_PIN 4U /*!< PIO0 pin index: 4 */ -#define BOARD_SW3_PIN_NAME PIO0_4 /*!< Pin name */ -#define BOARD_SW3_LABEL "J4[7]/U9[12]/SW3/BRIDGE_T_INTR-ISP1" /*!< Label */ -#define BOARD_SW3_NAME "SW3" /*!< Identifier name */ -#define BOARD_SW3_DIRECTION kPIN_MUX_DirectionInput /*!< Direction */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitBUTTONsPins(void); /* Function assigned for the Cortex-M0P */ - -/* PIO1_9 (number 29), J9[5]/D2[3]/P1_9-BLUE_LED */ -#define BOARD_LED_BLUE_GPIO GPIO /*!< GPIO device name: GPIO */ -#define BOARD_LED_BLUE_PORT 1U /*!< PORT device index: 1 */ -#define BOARD_LED_BLUE_GPIO_PIN 9U /*!< PIO1 pin index: 9 */ -#define BOARD_LED_BLUE_PIN_NAME PIO1_9 /*!< Pin name */ -#define BOARD_LED_BLUE_LABEL "J9[5]/D2[3]/P1_9-BLUE_LED" /*!< Label */ -#define BOARD_LED_BLUE_NAME "LED_BLUE" /*!< Identifier name */ -#define BOARD_LED_BLUE_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ - -/* PIO1_10 (number 30), J9[8]/D2[4]/P1_10-SCT4-LED_GREEN */ -#define BOARD_LED_GREEN_GPIO GPIO /*!< GPIO device name: GPIO */ -#define BOARD_LED_GREEN_PORT 1U /*!< PORT device index: 1 */ -#define BOARD_LED_GREEN_GPIO_PIN 10U /*!< PIO1 pin index: 10 */ -#define BOARD_LED_GREEN_PIN_NAME PIO1_10 /*!< Pin name */ -#define BOARD_LED_GREEN_LABEL "J9[8]/D2[4]/P1_10-SCT4-LED_GREEN" /*!< Label */ -#define BOARD_LED_GREEN_NAME "LED_GREEN" /*!< Identifier name */ -#define BOARD_LED_GREEN_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ - -/* PIO0_29 (number 11), J2[5]/D2[1]/P0_29-CT32B0_MAT3-RED */ -#define BOARD_LED_RED_GPIO GPIO /*!< GPIO device name: GPIO */ -#define BOARD_LED_RED_PORT 0U /*!< PORT device index: 0 */ -#define BOARD_LED_RED_GPIO_PIN 29U /*!< PIO0 pin index: 29 */ -#define BOARD_LED_RED_PIN_NAME PIO0_29 /*!< Pin name */ -#define BOARD_LED_RED_LABEL "J2[5]/D2[1]/P0_29-CT32B0_MAT3-RED" /*!< Label */ -#define BOARD_LED_RED_NAME "LED_RED" /*!< Identifier name */ -#define BOARD_LED_RED_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitLEDsPins(void); /* Function assigned for the Cortex-M0P */ - -/* FC4_RTS_SCL_SSEL1 (number 3), J1[1]/JS4[1]/U10[7]/P0_25-FC4_SCLX */ -#define BOARD_FC4_SCLX_PERIPHERAL FLEXCOMM4 /*!< Device name: FLEXCOMM4 */ -#define BOARD_FC4_SCLX_SIGNAL RTS_SCL_SSEL1 /*!< FLEXCOMM4 signal: RTS_SCL_SSEL1 */ -#define BOARD_FC4_SCLX_PIN_NAME FC4_RTS_SCL_SSEL1 /*!< Pin name */ -#define BOARD_FC4_SCLX_LABEL "J1[1]/JS4[1]/U10[7]/P0_25-FC4_SCLX" /*!< Label */ -#define BOARD_FC4_SCLX_NAME "FC4_SCLX" /*!< Identifier name */ - -/* FC4_CTS_SDA_SSEL0 (number 4), J1[3]/JS5[1]/U10[5]/P0_26-FC4_SDAX */ -#define BOARD_FC4_SDAX_PERIPHERAL FLEXCOMM4 /*!< Device name: FLEXCOMM4 */ -#define BOARD_FC4_SDAX_SIGNAL CTS_SDA_SSEL0 /*!< FLEXCOMM4 signal: CTS_SDA_SSEL0 */ -#define BOARD_FC4_SDAX_PIN_NAME FC4_CTS_SDA_SSEL0 /*!< Pin name */ -#define BOARD_FC4_SDAX_LABEL "J1[3]/JS5[1]/U10[5]/P0_26-FC4_SDAX" /*!< Label */ -#define BOARD_FC4_SDAX_NAME "FC4_SDAX" /*!< Identifier name */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitSecureMCUPins(void); /* Function assigned for the Cortex-M0P */ - -/* FC5_TXD_SCL_MISO (number 58), J1[11]/U5[2]/P0_18-FC5_TXD_SCL_MISO */ -#define BOARD_SPI_FLASH_MISO_PERIPHERAL FLEXCOMM5 /*!< Device name: FLEXCOMM5 */ -#define BOARD_SPI_FLASH_MISO_SIGNAL TXD_SCL_MISO /*!< FLEXCOMM5 signal: TXD_SCL_MISO */ -#define BOARD_SPI_FLASH_MISO_PIN_NAME FC5_TXD_SCL_MISO /*!< Pin name */ -#define BOARD_SPI_FLASH_MISO_LABEL "J1[11]/U5[2]/P0_18-FC5_TXD_SCL_MISO" /*!< Label */ -#define BOARD_SPI_FLASH_MISO_NAME "SPI_FLASH_MISO" /*!< Identifier name */ - -/* FC5_SCK (number 59), J1[9]/J2[8]/U5[6]/P0_19-FC5_SCK-SPIFI_CSn */ -#define BOARD_SPI_FLASH_SCK_PERIPHERAL FLEXCOMM5 /*!< Device name: FLEXCOMM5 */ -#define BOARD_SPI_FLASH_SCK_SIGNAL SCK /*!< FLEXCOMM5 signal: SCK */ -#define BOARD_SPI_FLASH_SCK_PIN_NAME FC5_SCK /*!< Pin name */ -#define BOARD_SPI_FLASH_SCK_LABEL "J1[9]/J2[8]/U5[6]/P0_19-FC5_SCK-SPIFI_CSn" /*!< Label */ -#define BOARD_SPI_FLASH_SCK_NAME "SPI_FLASH_SCK" /*!< Identifier name */ - -/* FC5_RXD_SDA_MOSI (number 60), J1[13]/U5[5]/P0_20-FC5_RXD_SDA_MOSI */ -#define BOARD_SPI_FLASH_MOSI_PERIPHERAL FLEXCOMM5 /*!< Device name: FLEXCOMM5 */ -#define BOARD_SPI_FLASH_MOSI_SIGNAL RXD_SDA_MOSI /*!< FLEXCOMM5 signal: RXD_SDA_MOSI */ -#define BOARD_SPI_FLASH_MOSI_PIN_NAME FC5_RXD_SDA_MOSI /*!< Pin name */ -#define BOARD_SPI_FLASH_MOSI_LABEL "J1[13]/U5[5]/P0_20-FC5_RXD_SDA_MOSI" /*!< Label */ -#define BOARD_SPI_FLASH_MOSI_NAME "SPI_FLASH_MOSI" /*!< Identifier name */ - -/* FC5_SSEL3 (number 16), J9[7]/JS8[1]/U5[1]/P1_2-FC5_SSEL3 */ -#define BOARD_FC5_SSEL3_PERIPHERAL FLEXCOMM5 /*!< Device name: FLEXCOMM5 */ -#define BOARD_FC5_SSEL3_SIGNAL SSEL3 /*!< FLEXCOMM5 signal: SSEL3 */ -#define BOARD_FC5_SSEL3_PIN_NAME FC5_SSEL3 /*!< Pin name */ -#define BOARD_FC5_SSEL3_LABEL "J9[7]/JS8[1]/U5[1]/P1_2-FC5_SSEL3" /*!< Label */ -#define BOARD_FC5_SSEL3_NAME "FC5_SSEL3" /*!< Identifier name */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitSPI_FLASHPins(void); /* Function assigned for the Cortex-M0P */ - -/* PIO0_4 (number 38), J4[7]/U9[12]/SW3/BRIDGE_T_INTR-ISP1 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_GPIO GPIO /*!< GPIO device name: GPIO */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_PORT 0U /*!< PORT device index: 0 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_GPIO_PIN 4U /*!< PIO0 pin index: 4 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_PIN_NAME PIO0_4 /*!< Pin name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_LABEL "J4[7]/U9[12]/SW3/BRIDGE_T_INTR-ISP1" /*!< Label */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_INTR_NAME "BRIDGE_T_INTR" /*!< Identifier name */ - -/* FC3_SCK (number 46), J4[4]/U9[13]/BRIDGE_T_SCK */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_PERIPHERAL FLEXCOMM3 /*!< Device name: FLEXCOMM3 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_SIGNAL SCK /*!< FLEXCOMM3 signal: SCK */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_PIN_NAME FC3_SCK /*!< Pin name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_LABEL "J4[4]/U9[13]/BRIDGE_T_SCK" /*!< Label */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_NAME "BRIDGE_T_SCK" /*!< Identifier name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SCK_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ - -/* FC3_RXD_SDA_MOSI (number 47), J4[2]/U9[11]/BRIDGE_T_MOSI */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_PERIPHERAL FLEXCOMM3 /*!< Device name: FLEXCOMM3 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_SIGNAL RXD_SDA_MOSI /*!< FLEXCOMM3 signal: RXD_SDA_MOSI */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_PIN_NAME FC3_RXD_SDA_MOSI /*!< Pin name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_LABEL "J4[2]/U9[11]/BRIDGE_T_MOSI" /*!< Label */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_NAME "BRIDGE_T_MOSI" /*!< Identifier name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MOSI_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ - -/* FC3_TXD_SCL_MISO (number 48), J4[3]/U15[4]/BRIDGE_T_MISO */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_PERIPHERAL FLEXCOMM3 /*!< Device name: FLEXCOMM3 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_SIGNAL TXD_SCL_MISO /*!< FLEXCOMM3 signal: TXD_SCL_MISO */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_PIN_NAME FC3_TXD_SCL_MISO /*!< Pin name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_LABEL "J4[3]/U15[4]/BRIDGE_T_MISO" /*!< Label */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_NAME "BRIDGE_T_MISO" /*!< Identifier name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_MISO_DIRECTION kPIN_MUX_DirectionInput /*!< Direction */ - -/* FC3_CTS_SDA_SSEL0 (number 49), J2[12]/J4[1]/U9[14]/BRIDGE_T_SSEL-SPIFI_IO3 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_PERIPHERAL FLEXCOMM3 /*!< Device name: FLEXCOMM3 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_SIGNAL CTS_SDA_SSEL0 /*!< FLEXCOMM3 signal: CTS_SDA_SSEL0 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_PIN_NAME FC3_CTS_SDA_SSEL0 /*!< Pin name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_LABEL "J2[12]/J4[1]/U9[14]/BRIDGE_T_SSEL-SPIFI_IO3" /*!< Label */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_NAME "BRIDGE_T_SSEL" /*!< Identifier name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_T_SSEL_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ - -/* PIO0_22 (number 63), J4[8]/P0_22-BRIDGE_GPIO */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_GPIO GPIO /*!< GPIO device name: GPIO */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_PORT 0U /*!< PORT device index: 0 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_GPIO_PIN 22U /*!< PIO0 pin index: 22 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_PIN_NAME PIO0_22 /*!< Pin name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_LABEL "J4[8]/P0_22-BRIDGE_GPIO" /*!< Label */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_GPIO_NAME "BRIDGE_GPIO" /*!< Identifier name */ - -/* FC1_RTS_SCL_SSEL1 (number 1), J4[9]/JS3[1]/JS4[3]/U10[7]/U12[D6]/BRIDGE_SCL */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SCL_PERIPHERAL FLEXCOMM1 /*!< Device name: FLEXCOMM1 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SCL_SIGNAL RTS_SCL_SSEL1 /*!< FLEXCOMM1 signal: RTS_SCL_SSEL1 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SCL_PIN_NAME FC1_RTS_SCL_SSEL1 /*!< Pin name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SCL_LABEL "J4[9]/JS3[1]/JS4[3]/U10[7]/U12[D6]/BRIDGE_SCL" /*!< Label */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SCL_NAME "BRIDGE_SCL" /*!< Identifier name */ - -/* FC1_CTS_SDA_SSEL0 (number 2), J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SDA_WAKEUP_PERIPHERAL FLEXCOMM1 /*!< Device name: FLEXCOMM1 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SDA_WAKEUP_SIGNAL CTS_SDA_SSEL0 /*!< FLEXCOMM1 signal: CTS_SDA_SSEL0 */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SDA_WAKEUP_PIN_NAME FC1_CTS_SDA_SSEL0 /*!< Pin name */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SDA_WAKEUP_LABEL "J4[10]/JS2[1]/JS5[3]/U10[5]/U12[E6]/SW1/BRIDGE_SDA-WAKEUP" /*!< Label */ -#define BOARD_INITPMOD_SPI_I2C_BRIDGEPINS_BRIDGE_SDA_WAKEUP_NAME "BRIDGE_SDA_WAKEUP" /*!< Identifier name */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitPMod_SPI_I2C_BRIDGEPins(void); /* Function assigned for the Cortex-M0P */ - -/* USB0_DP (number 5), J5[3]/U7[2]/USB_DP */ -#define BOARD_USB_DP_PERIPHERAL USB0 /*!< Device name: USB0 */ -#define BOARD_USB_DP_SIGNAL USB_DP /*!< USB0 signal: USB_DP */ -#define BOARD_USB_DP_PIN_NAME USB0_DP /*!< Pin name */ -#define BOARD_USB_DP_LABEL "J5[3]/U7[2]/USB_DP" /*!< Label */ -#define BOARD_USB_DP_NAME "USB_DP" /*!< Identifier name */ - -/* USB0_DM (number 6), J5[2]/U7[3]/USB_DM */ -#define BOARD_USB_DM_PERIPHERAL USB0 /*!< Device name: USB0 */ -#define BOARD_USB_DM_SIGNAL USB_DM /*!< USB0 signal: USB_DM */ -#define BOARD_USB_DM_PIN_NAME USB0_DM /*!< Pin name */ -#define BOARD_USB_DM_LABEL "J5[2]/U7[3]/USB_DM" /*!< Label */ -#define BOARD_USB_DM_NAME "USB_DM" /*!< Identifier name */ - -/* USB0_VBUS (number 26), J1[14]/J5[1]/JP10[2]/P1_6-FC7_SCK-USB_VBUS */ -#define BOARD_USB_VBUS_PERIPHERAL USB0 /*!< Device name: USB0 */ -#define BOARD_USB_VBUS_SIGNAL USB_VBUS /*!< USB0 signal: USB_VBUS */ -#define BOARD_USB_VBUS_PIN_NAME USB0_VBUS /*!< Pin name */ -#define BOARD_USB_VBUS_LABEL "J1[14]/J5[1]/JP10[2]/P1_6-FC7_SCK-USB_VBUS" /*!< Label */ -#define BOARD_USB_VBUS_NAME "USB_VBUS" /*!< Identifier name */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitUSBPins(void); /* Function assigned for the Cortex-M0P */ - -/* FC0_TXD_SCL_MISO (number 32), U6[4]/U22[3]/P0_1-ISP_TX */ -#define BOARD_DEBUG_UART_TX_PERIPHERAL FLEXCOMM0 /*!< Device name: FLEXCOMM0 */ -#define BOARD_DEBUG_UART_TX_SIGNAL TXD_SCL_MISO /*!< FLEXCOMM0 signal: TXD_SCL_MISO */ -#define BOARD_DEBUG_UART_TX_PIN_NAME FC0_TXD_SCL_MISO /*!< Pin name */ -#define BOARD_DEBUG_UART_TX_LABEL "U6[4]/U22[3]/P0_1-ISP_TX" /*!< Label */ -#define BOARD_DEBUG_UART_TX_NAME "DEBUG_UART_TX" /*!< Identifier name */ -#define BOARD_DEBUG_UART_TX_DIRECTION kPIN_MUX_DirectionOutput /*!< Direction */ - -/* FC0_RXD_SDA_MOSI (number 31), U18[4]/TO_MUX_P0_0-ISP_RX */ -#define BOARD_DEBUG_UART_RX_PERIPHERAL FLEXCOMM0 /*!< Device name: FLEXCOMM0 */ -#define BOARD_DEBUG_UART_RX_SIGNAL RXD_SDA_MOSI /*!< FLEXCOMM0 signal: RXD_SDA_MOSI */ -#define BOARD_DEBUG_UART_RX_PIN_NAME FC0_RXD_SDA_MOSI /*!< Pin name */ -#define BOARD_DEBUG_UART_RX_LABEL "U18[4]/TO_MUX_P0_0-ISP_RX" /*!< Label */ -#define BOARD_DEBUG_UART_RX_NAME "DEBUG_UART_RX" /*!< Identifier name */ -#define BOARD_DEBUG_UART_RX_DIRECTION kPIN_MUX_DirectionInput /*!< Direction */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M0P */ - -/* SWDIO (number 53), J2[6]/P1[2]/U2[5]/U14[4]/IF_TMS_SWDIO-SPIFI_IO0 */ -#define BOARD_DEBUG_SWD_SWDIO_PERIPHERAL SWD /*!< Device name: SWD */ -#define BOARD_DEBUG_SWD_SWDIO_SIGNAL SWDIO /*!< SWD signal: SWDIO */ -#define BOARD_DEBUG_SWD_SWDIO_PIN_NAME SWDIO /*!< Pin name */ -#define BOARD_DEBUG_SWD_SWDIO_LABEL "J2[6]/P1[2]/U2[5]/U14[4]/IF_TMS_SWDIO-SPIFI_IO0" /*!< Label */ -#define BOARD_DEBUG_SWD_SWDIO_NAME "DEBUG_SWD_SWDIO" /*!< Identifier name */ - -/* SWCLK (number 52), J2[4]/JS28/U4[4]/TCK-SWDCLK_TRGT-SPIFI_IO1 */ -#define BOARD_DEBUG_SWD_SWDCLK_PERIPHERAL SWD /*!< Device name: SWD */ -#define BOARD_DEBUG_SWD_SWDCLK_SIGNAL SWCLK /*!< SWD signal: SWCLK */ -#define BOARD_DEBUG_SWD_SWDCLK_PIN_NAME SWCLK /*!< Pin name */ -#define BOARD_DEBUG_SWD_SWDCLK_LABEL "J2[4]/JS28/U4[4]/TCK-SWDCLK_TRGT-SPIFI_IO1" /*!< Label */ -#define BOARD_DEBUG_SWD_SWDCLK_NAME "DEBUG_SWD_SWDCLK" /*!< Identifier name */ - -/*! - * @brief Configures pin routing and optionally pin electrical features. - * - */ -void BOARD_InitSWD_DEBUGPins(void); /* Function assigned for the Cortex-M0P */ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ -#endif /* _PIN_MUX_H_ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/lists/generic_list.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/lists/generic_list.c deleted file mode 100644 index 8224c8ef8..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/lists/generic_list.c +++ /dev/null @@ -1,423 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/*! ********************************************************************************* -************************************************************************************* -* Include -************************************************************************************* -********************************************************************************** */ -#include "fsl_common.h" -#include "generic_list.h" - -static list_status_t LIST_Scan(list_handle_t list, list_element_handle_t newElement) -{ - list_element_handle_t element = list->head; - - while (element != NULL) - { - if (element == newElement) - { - return kLIST_DuplicateError; - } - element = element->next; - } - return kLIST_Ok; -} - -/*! ********************************************************************************* -************************************************************************************* -* Public functions -************************************************************************************* -********************************************************************************** */ -/*! ********************************************************************************* - * \brief Initialises the list descriptor. - * - * \param[in] list - LIST_ handle to init. - * max - Maximum number of elements in list. 0 for unlimited. - * - * \return void. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -void LIST_Init(list_handle_t list, uint32_t max) -{ - list->head = NULL; - list->tail = NULL; - list->max = (uint16_t)max; - list->size = 0; -} - -/*! ********************************************************************************* - * \brief Gets the list that contains the given element. - * - * \param[in] element - Handle of the element. - * - * \return NULL if element is orphan. - * Handle of the list the element is inserted into. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -list_handle_t LIST_GetList(list_element_handle_t element) -{ - return element->list; -} - -/*! ********************************************************************************* - * \brief Links element to the tail of the list. - * - * \param[in] list - ID of list to insert into. - * element - element to add - * - * \return kLIST_Full if list is full. - * kLIST_Ok if insertion was successful. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element) -{ - uint32_t regPrimask = DisableGlobalIRQ(); - - if ((list->max != 0U) && (list->max == list->size)) - { - EnableGlobalIRQ(regPrimask); - return kLIST_Full; - } - - if (kLIST_DuplicateError == LIST_Scan(list, element)) - { - EnableGlobalIRQ(regPrimask); - return kLIST_DuplicateError; - } - - if (list->size == 0U) - { - list->head = element; - } - else - { - list->tail->next = element; - } - element->prev = list->tail; - element->next = NULL; - element->list = list; - list->tail = element; - list->size++; - - EnableGlobalIRQ(regPrimask); - return kLIST_Ok; -} - -/*! ********************************************************************************* - * \brief Links element to the head of the list. - * - * \param[in] list - ID of list to insert into. - * element - element to add - * - * \return kLIST_Full if list is full. - * kLIST_Ok if insertion was successful. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element) -{ - uint32_t regPrimask = DisableGlobalIRQ(); - - if ((list->max != 0U) && (list->max == list->size)) - { - EnableGlobalIRQ(regPrimask); - return kLIST_Full; - } - - if (kLIST_DuplicateError == LIST_Scan(list, element)) - { - EnableGlobalIRQ(regPrimask); - return kLIST_DuplicateError; - } - - if (list->size == 0U) - { - list->tail = element; - } - else - { - list->head->prev = element; - } - element->next = list->head; - element->prev = NULL; - element->list = list; - list->head = element; - list->size++; - - EnableGlobalIRQ(regPrimask); - return kLIST_Ok; -} - -/*! ********************************************************************************* - * \brief Unlinks element from the head of the list. - * - * \param[in] list - ID of list to remove from. - * - * \return NULL if list is empty. - * ID of removed element(pointer) if removal was successful. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -list_element_handle_t LIST_RemoveHead(list_handle_t list) -{ - list_element_handle_t element; - - uint32_t regPrimask = DisableGlobalIRQ(); - - if ((NULL == list) || (list->size == 0U)) - { - EnableGlobalIRQ(regPrimask); - return NULL; /*LIST_ is empty*/ - } - - element = list->head; - list->size--; - if (list->size == 0U) - { - list->tail = NULL; - } - else - { - element->next->prev = NULL; - } - list->head = element->next; /*Is NULL if element is head*/ - element->list = NULL; - - EnableGlobalIRQ(regPrimask); - return element; -} - -/*! ********************************************************************************* - * \brief Gets head element ID. - * - * \param[in] list - ID of list. - * - * \return NULL if list is empty. - * ID of head element if list is not empty. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -list_element_handle_t LIST_GetHead(list_handle_t list) -{ - return list->head; -} - -/*! ********************************************************************************* - * \brief Gets next element ID. - * - * \param[in] element - ID of the element. - * - * \return NULL if element is tail. - * ID of next element if exists. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -list_element_handle_t LIST_GetNext(list_element_handle_t element) -{ - return element->next; -} - -/*! ********************************************************************************* - * \brief Gets previous element ID. - * - * \param[in] element - ID of the element. - * - * \return NULL if element is head. - * ID of previous element if exists. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -list_element_handle_t LIST_GetPrev(list_element_handle_t element) -{ - return element->prev; -} - -/*! ********************************************************************************* - * \brief Unlinks an element from its list. - * - * \param[in] element - ID of the element to remove. - * - * \return kLIST_OrphanElement if element is not part of any list. - * kLIST_Ok if removal was successful. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -list_status_t LIST_RemoveElement(list_element_handle_t element) -{ - if (element->list == NULL) - { - return kLIST_OrphanElement; /*Element was previusly removed or never added*/ - } - - uint32_t regPrimask = DisableGlobalIRQ(); - - if (element->prev == NULL) /*Element is head or solo*/ - { - element->list->head = element->next; /*is null if solo*/ - } - if (element->next == NULL) /*Element is tail or solo*/ - { - element->list->tail = element->prev; /*is null if solo*/ - } - if (element->prev != NULL) /*Element is not head*/ - { - element->prev->next = element->next; - } - if (element->next != NULL) /*Element is not tail*/ - { - element->next->prev = element->prev; - } - element->list->size--; - element->list = NULL; - - EnableGlobalIRQ(regPrimask); - return kLIST_Ok; -} - -/*! ********************************************************************************* - * \brief Links an element in the previous position relative to a given member - * of a list. - * - * \param[in] element - ID of a member of a list. - * newElement - new element to insert before the given member. - * - * \return kLIST_OrphanElement if element is not part of any list. - * kLIST_Full if list is full. - * kLIST_Ok if insertion was successful. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement) -{ - if (element->list == NULL) - { - return kLIST_OrphanElement; /*Element was previusly removed or never added*/ - } - uint32_t regPrimask = DisableGlobalIRQ(); - - if ((element->list->max != 0U) && (element->list->max == element->list->size)) - { - EnableGlobalIRQ(regPrimask); - return kLIST_Full; - } - - if (kLIST_DuplicateError == LIST_Scan(element->list, newElement)) - { - EnableGlobalIRQ(regPrimask); - return kLIST_DuplicateError; - } - - if (element->prev == NULL) /*Element is list head*/ - { - element->list->head = newElement; - } - else - { - element->prev->next = newElement; - } - newElement->list = element->list; - element->list->size++; - newElement->next = element; - newElement->prev = element->prev; - element->prev = newElement; - - EnableGlobalIRQ(regPrimask); - return kLIST_Ok; -} - -/*! ********************************************************************************* - * \brief Gets the current size of a list. - * - * \param[in] list - ID of the list. - * - * \return Current size of the list. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -uint32_t LIST_GetSize(list_handle_t list) -{ - return list->size; -} - -/*! ********************************************************************************* - * \brief Gets the number of free places in the list. - * - * \param[in] list - ID of the list. - * - * \return Available size of the list. - * - * \pre - * - * \post - * - * \remarks - * - ********************************************************************************** */ -uint32_t LIST_GetAvailableSize(list_handle_t list) -{ - return ((uint32_t)list->max - (uint32_t)list->size); -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/lists/generic_list.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/lists/generic_list.h deleted file mode 100644 index ebcbe2717..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/lists/generic_list.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _GENERIC_LIST_H_ -#define _GENERIC_LIST_H_ - -/*! - * @addtogroup GenericList - * @{ - */ - -/*!********************************************************************************* -************************************************************************************* -* Include -************************************************************************************* -********************************************************************************** */ - -/*! ********************************************************************************* -************************************************************************************* -* Public macro definitions -************************************************************************************* -********************************************************************************** */ - -/*! ********************************************************************************* -************************************************************************************* -* Public type definitions -************************************************************************************* -********************************************************************************** */ -/*! @brief The list status */ -typedef enum _list_status -{ - kLIST_Ok = kStatus_Success, /*!< Success */ - kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */ - kLIST_Full = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */ - kLIST_Empty = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */ - kLIST_OrphanElement = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */ -} list_status_t; - -/*! @brief The list structure*/ -typedef struct list_tag -{ - struct list_element_tag *head; /*!< list head */ - struct list_element_tag *tail; /*!< list tail */ - uint16_t size; /*!< list size */ - uint16_t max; /*!< list max number of elements */ -} list_t, *list_handle_t; - -/*! @brief The list element*/ -typedef struct list_element_tag -{ - struct list_element_tag *next; /*!< next list element */ - struct list_element_tag *prev; /*!< previous list element */ - struct list_tag *list; /*!< pointer to the list */ -} list_element_t, *list_element_handle_t; - -/*! ********************************************************************************* -************************************************************************************* -* Public prototypes -************************************************************************************* -********************************************************************************** */ -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ -/*! - * @brief Initialize the list. - * - * This function initialize the list. - * - * @param list - List handle to initialize. - * @param max - Maximum number of elements in list. 0 for unlimited. - */ -void LIST_Init(list_handle_t list, uint32_t max); - -/*! - * @brief Gets the list that contains the given element. - * - * - * @param element - Handle of the element. - * @retval NULL if element is orphan, Handle of the list the element is inserted into. - */ -list_handle_t LIST_GetList(list_element_handle_t element); - -/*! - * @brief Links element to the head of the list. - * - * @param list - Handle of the list. - * @param element - Handle of the element. - * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. - */ -list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element); - -/*! - * @brief Links element to the tail of the list. - * - * @param list - Handle of the list. - * @param element - Handle of the element. - * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful. - */ -list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element); - -/*! - * @brief Unlinks element from the head of the list. - * - * @param list - Handle of the list. - * - * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. - */ -list_element_handle_t LIST_RemoveHead(list_handle_t list); - -/*! - * @brief Gets head element handle. - * - * @param list - Handle of the list. - * - * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. - */ -list_element_handle_t LIST_GetHead(list_handle_t list); - -/*! - * @brief Gets next element handle for given element handle. - * - * @param element - Handle of the element. - * - * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. - */ -list_element_handle_t LIST_GetNext(list_element_handle_t element); - -/*! - * @brief Gets previous element handle for given element handle. - * - * @param element - Handle of the element. - * - * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful. - */ -list_element_handle_t LIST_GetPrev(list_element_handle_t element); - -/*! - * @brief Unlinks an element from its list. - * - * @param element - Handle of the element. - * - * @retval kLIST_OrphanElement if element is not part of any list. - * @retval kLIST_Ok if removal was successful. - */ -list_status_t LIST_RemoveElement(list_element_handle_t element); - -/*! - * @brief Links an element in the previous position relative to a given member of a list. - * - * @param element - Handle of the element. - * @param newElement - New element to insert before the given member. - * - * @retval kLIST_OrphanElement if element is not part of any list. - * @retval kLIST_Ok if removal was successful. - */ -list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement); - -/*! - * @brief Gets the current size of a list. - * - * @param list - Handle of the list. - * - * @retval Current size of the list. - */ -uint32_t LIST_GetSize(list_handle_t list); - -/*! - * @brief Gets the number of free places in the list. - * - * @param list - Handle of the list. - * - * @retval Available size of the list. - */ -uint32_t LIST_GetAvailableSize(list_handle_t list); - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! @}*/ -#endif /*_GENERIC_LIST_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_manager.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_manager.c deleted file mode 100644 index eca551541..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_manager.c +++ /dev/null @@ -1,1299 +0,0 @@ -/* - * Copyright 2018-2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include - -#include "serial_manager.h" -#include "serial_port_internal.h" -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - -#include "generic_list.h" - -/* - * The OSA_USED macro can only be defined when the OSA component is used. - * If the source code of the OSA component does not exist, the OSA_USED cannot be defined. - * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED - * also cannot be defined. - * The source code path of the OSA component is /components/osa. - * - */ -#if defined(OSA_USED) - -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) -#include "common_task.h" -#else -#include "fsl_os_abstraction.h" -#endif - -#endif - -#endif - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -#ifndef NDEBUG -#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) -#undef assert -#define assert(n) -#endif -#endif - -#define SERIAL_EVENT_DATA_RECEIVED (1U << 0) -#define SERIAL_EVENT_DATA_SENT (1U << 1) - -#define SERIAL_MANAGER_WRITE_TAG 0xAABB5754U -#define SERIAL_MANAGER_READ_TAG 0xBBAA5244U - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -typedef enum _serial_manager_transmission_mode -{ - kSerialManager_TransmissionBlocking = 0x0U, /*!< Blocking transmission*/ - kSerialManager_TransmissionNonBlocking = 0x1U, /*!< None blocking transmission*/ -} serial_manager_transmission_mode_t; - -/* TX transfer structure */ -typedef struct _serial_manager_transfer -{ - uint8_t *buffer; - volatile uint32_t length; - volatile uint32_t soFar; - serial_manager_transmission_mode_t mode; - serial_manager_status_t status; -} serial_manager_transfer_t; -#endif - -/* write handle structure */ -typedef struct _serial_manager_send_handle -{ -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - list_element_t link; /*!< list element of the link */ - serial_manager_transfer_t transfer; -#endif - struct _serial_manager_handle *serialManagerHandle; -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - serial_manager_callback_t callback; - void *callbackParam; - uint32_t tag; -#endif -} serial_manager_write_handle_t; - -typedef serial_manager_write_handle_t serial_manager_read_handle_t; - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -/* receive state structure */ -typedef struct _serial_manager_read_ring_buffer -{ - uint8_t *ringBuffer; - uint32_t ringBufferSize; - volatile uint32_t ringHead; - volatile uint32_t ringTail; -} serial_manager_read_ring_buffer_t; -#endif - -#if defined(__CC_ARM) -#pragma anon_unions -#endif -/* The serial manager handle structure */ -typedef struct _serial_manager_handle -{ -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - list_t runningWriteHandleHead; /*!< The queue of running write handle */ - list_t completedWriteHandleHead; /*!< The queue of completed write handle */ -#endif - serial_manager_read_handle_t *openedReadHandleHead; - uint32_t openedWriteHandleCount; - union - { - uint8_t lowLevelhandleBuffer[1]; -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - uint8_t uartHandleBuffer[SERIAL_PORT_UART_HANDLE_SIZE]; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - uint8_t usbcdcHandleBuffer[SERIAL_PORT_USB_CDC_HANDLE_SIZE]; -#endif -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - uint8_t swoHandleBuffer[SERIAL_PORT_SWO_HANDLE_SIZE]; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - uint8_t usbcdcVirtualHandleBuffer[SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE]; -#endif - }; -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - serial_manager_read_ring_buffer_t ringBuffer; -#endif - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - -#if defined(OSA_USED) - -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) - common_task_message_t commontaskMsg; -#else - uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */ - uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */ -#endif - -#endif - -#endif - - serial_port_type_t type; -} serial_manager_handle_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -static void SerialManager_Task(void *param); -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - -#if defined(OSA_USED) - -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) - -#else - /* - * \brief Defines the serial manager task's stack - */ -OSA_TASK_DEFINE(SerialManager_Task, SERIAL_MANAGER_TASK_PRIORITY, 1, SERIAL_MANAGER_TASK_STACK_SIZE, false); -#endif - -#endif - -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -static void SerialManager_AddTail(list_t *queue, serial_manager_write_handle_t *node) -{ - (void)LIST_AddTail(queue, &node->link); -} - -static void SerialManager_RemoveHead(list_t *queue) -{ - (void)LIST_RemoveHead(queue); -} -#endif - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - -static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle) -{ - serial_manager_status_t status = kStatus_SerialManager_Error; - serial_manager_write_handle_t *writeHandle = - (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead); - - if (writeHandle != NULL) - { - switch (handle->type) - { -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - case kSerialPort_Uart: - status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - writeHandle->transfer.buffer, writeHandle->transfer.length); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - case kSerialPort_UsbCdc: - status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - writeHandle->transfer.buffer, writeHandle->transfer.length); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - case kSerialPort_Swo: - status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - writeHandle->transfer.buffer, writeHandle->transfer.length); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - case kSerialPort_UsbCdcVirtual: - status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - writeHandle->transfer.buffer, writeHandle->transfer.length); - break; -#endif - default: - status = kStatus_SerialManager_Error; - break; - } - } - return status; -} - -static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle, - serial_manager_read_handle_t *readHandle, - uint8_t *buffer, - uint32_t length) -{ - serial_manager_status_t status = kStatus_SerialManager_Error; - - if (readHandle != NULL) - { -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - if (handle->type == kSerialPort_UsbCdc) - { - status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); - } -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - if (handle->type == kSerialPort_UsbCdcVirtual) - { - status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); - } -#endif - } - return status; -} - -#else - -static serial_manager_status_t SerialManager_StartWriting(serial_manager_handle_t *handle, - serial_manager_write_handle_t *writeHandle, - uint8_t *buffer, - uint32_t length) -{ - serial_manager_status_t status = kStatus_SerialManager_Error; - - if (writeHandle != NULL) - { - switch (handle->type) - { -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - case kSerialPort_Uart: - status = Serial_UartWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - case kSerialPort_UsbCdc: - status = Serial_UsbCdcWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - case kSerialPort_Swo: - status = Serial_SwoWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - case kSerialPort_UsbCdcVirtual: - status = Serial_UsbCdcVirtualWrite(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); - break; -#endif - default: - status = kStatus_SerialManager_Error; - break; - } - } - return status; -} - -static serial_manager_status_t SerialManager_StartReading(serial_manager_handle_t *handle, - serial_manager_read_handle_t *readHandle, - uint8_t *buffer, - uint32_t length) -{ - serial_manager_status_t status = kStatus_SerialManager_Error; - - if (readHandle != NULL) - { - switch (handle->type) - { -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - case kSerialPort_Uart: - status = Serial_UartRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - case kSerialPort_UsbCdc: - status = Serial_UsbCdcRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - case kSerialPort_Swo: - status = Serial_SwoRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - case kSerialPort_UsbCdcVirtual: - status = Serial_UsbCdcVirtualRead(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), buffer, length); - break; -#endif - default: - status = kStatus_SerialManager_Error; - break; - } - } - return status; -} -#endif - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -static void SerialManager_IsrFunction(serial_manager_handle_t *handle) -{ - uint32_t regPrimask = DisableGlobalIRQ(); - switch (handle->type) - { -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - case kSerialPort_Uart: - Serial_UartIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - case kSerialPort_UsbCdc: - Serial_UsbCdcIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - case kSerialPort_Swo: - Serial_SwoIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - case kSerialPort_UsbCdcVirtual: - Serial_UsbCdcVirtualIsrFunction(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); - break; -#endif - default: - /*MISRA rule 16.4*/ - break; - } - EnableGlobalIRQ(regPrimask); -} - -static void SerialManager_Task(void *param) -{ - serial_manager_handle_t *handle = (serial_manager_handle_t *)param; - serial_manager_write_handle_t *serialWriteHandle; - serial_manager_read_handle_t *serialReadHandle; - serial_manager_callback_message_t msg; - if (NULL != handle) - { -#if defined(OSA_USED) - -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) -#else - osa_event_flags_t ev = 0; - - do - { - if (KOSA_StatusSuccess == - OSA_EventWait((osa_event_handle_t)handle->event, osaEventFlagsAll_c, false, osaWaitForever_c, &ev)) - { - if (ev & SERIAL_EVENT_DATA_SENT) -#endif - -#endif - { - serialWriteHandle = - (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead); - while (NULL != serialWriteHandle) - { - SerialManager_RemoveHead(&handle->completedWriteHandleHead); - msg.buffer = serialWriteHandle->transfer.buffer; - msg.length = serialWriteHandle->transfer.soFar; - serialWriteHandle->transfer.buffer = NULL; - if (serialWriteHandle->callback != NULL) - { - serialWriteHandle->callback(serialWriteHandle->callbackParam, &msg, - serialWriteHandle->transfer.status); - } - serialWriteHandle = - (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->completedWriteHandleHead); - } - } -#if defined(OSA_USED) - -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) -#else - if (ev & SERIAL_EVENT_DATA_RECEIVED) -#endif - -#endif - { - serialReadHandle = handle->openedReadHandleHead; - if (serialReadHandle != NULL) - { - if (serialReadHandle->transfer.buffer != NULL) - { - if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length) - { - msg.buffer = serialReadHandle->transfer.buffer; - msg.length = serialReadHandle->transfer.soFar; - serialReadHandle->transfer.buffer = NULL; - if (serialReadHandle->callback != NULL) - { - serialReadHandle->callback(serialReadHandle->callbackParam, &msg, - serialReadHandle->transfer.status); - } - } - } - } - } -#if defined(OSA_USED) - -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) -#else - } - } while (gUseRtos_c); -#endif - -#endif - } -} -#endif - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -static void SerialManager_TxCallback(void *callbackParam, - serial_manager_callback_message_t *message, - serial_manager_status_t status) -{ - serial_manager_handle_t *handle; - serial_manager_write_handle_t *writeHandle; - - assert(callbackParam); - assert(message); - - handle = (serial_manager_handle_t *)callbackParam; - - writeHandle = (serial_manager_write_handle_t *)(void *)LIST_GetHead(&handle->runningWriteHandleHead); - - if (NULL != writeHandle) - { - SerialManager_RemoveHead(&handle->runningWriteHandleHead); - (void)SerialManager_StartWriting(handle); - writeHandle->transfer.soFar = message->length; - writeHandle->transfer.status = status; - if (kSerialManager_TransmissionNonBlocking == writeHandle->transfer.mode) - { - SerialManager_AddTail(&handle->completedWriteHandleHead, writeHandle); -#if defined(OSA_USED) - -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) - handle->commontaskMsg.callback = SerialManager_Task; - handle->commontaskMsg.callbackParam = handle; - COMMON_TASK_post_message(&handle->commontaskMsg); -#else - (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_SENT); -#endif - -#else - SerialManager_Task(handle); -#endif - } - else - { - writeHandle->transfer.buffer = NULL; - } - } -} - -static void SerialManager_RxCallback(void *callbackParam, - serial_manager_callback_message_t *message, - serial_manager_status_t status) -{ - serial_manager_handle_t *handle; - uint32_t ringBufferLength; - - assert(callbackParam); - assert(message); - - handle = (serial_manager_handle_t *)callbackParam; - - status = kStatus_SerialManager_Notify; - - for (uint32_t i = 0; i < message->length; i++) - { - handle->ringBuffer.ringBuffer[handle->ringBuffer.ringHead++] = message->buffer[i]; - if (handle->ringBuffer.ringHead >= handle->ringBuffer.ringBufferSize) - { - handle->ringBuffer.ringHead = 0U; - } - if (handle->ringBuffer.ringHead == handle->ringBuffer.ringTail) - { - status = kStatus_SerialManager_RingBufferOverflow; - handle->ringBuffer.ringTail++; - if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) - { - handle->ringBuffer.ringTail = 0U; - } - } - } - - ringBufferLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; - ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize; - - if ((handle->openedReadHandleHead != NULL) && (handle->openedReadHandleHead->transfer.buffer != NULL)) - { - if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar) - { - uint32_t remainLength = - handle->openedReadHandleHead->transfer.length - handle->openedReadHandleHead->transfer.soFar; - for (uint32_t i = 0; i < MIN(ringBufferLength, remainLength); i++) - { - handle->openedReadHandleHead->transfer.buffer[handle->openedReadHandleHead->transfer.soFar] = - handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail]; - handle->ringBuffer.ringTail++; - handle->openedReadHandleHead->transfer.soFar++; - if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) - { - handle->ringBuffer.ringTail = 0U; - } - } - ringBufferLength = ringBufferLength - MIN(ringBufferLength, remainLength); - } - - if (handle->openedReadHandleHead->transfer.length > handle->openedReadHandleHead->transfer.soFar) - { - } - else - { - if (kSerialManager_TransmissionBlocking == handle->openedReadHandleHead->transfer.mode) - { - handle->openedReadHandleHead->transfer.buffer = NULL; - } - else - { - handle->openedReadHandleHead->transfer.status = kStatus_SerialManager_Success; - -#if defined(OSA_USED) - -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) - handle->commontaskMsg.callback = SerialManager_Task; - handle->commontaskMsg.callbackParam = handle; - COMMON_TASK_post_message(&handle->commontaskMsg); -#else - (void)OSA_EventSet((osa_event_handle_t)handle->event, SERIAL_EVENT_DATA_RECEIVED); -#endif - -#else - SerialManager_Task(handle); -#endif - } - } - } - - if (ringBufferLength != 0U) - { - message->buffer = NULL; - message->length = ringBufferLength; - if ((NULL != handle->openedReadHandleHead) && (NULL != handle->openedReadHandleHead->callback)) - { - handle->openedReadHandleHead->callback(handle->openedReadHandleHead->callbackParam, message, status); - } - } - - ringBufferLength = handle->ringBuffer.ringBufferSize - 1U - ringBufferLength; - - if (NULL != handle->openedReadHandleHead) - { - (void)SerialManager_StartReading(handle, handle->openedReadHandleHead, NULL, ringBufferLength); - } -} - -static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, - uint8_t *buffer, - uint32_t length, - serial_manager_transmission_mode_t mode) -{ - serial_manager_write_handle_t *serialWriteHandle; - serial_manager_handle_t *handle; - serial_manager_status_t status = kStatus_SerialManager_Success; - uint32_t primask; - uint8_t isEmpty = 0U; - - assert(writeHandle); - assert(buffer); - assert(length); - - serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; - handle = serialWriteHandle->serialManagerHandle; - - assert(handle); - assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); - assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialWriteHandle->callback))); - - primask = DisableGlobalIRQ(); - if (serialWriteHandle->transfer.buffer != NULL) - { - EnableGlobalIRQ(primask); - return kStatus_SerialManager_Busy; - } - serialWriteHandle->transfer.buffer = buffer; - serialWriteHandle->transfer.length = length; - serialWriteHandle->transfer.soFar = 0U; - serialWriteHandle->transfer.mode = mode; - - if (NULL == LIST_GetHead(&handle->runningWriteHandleHead)) - { - isEmpty = 1U; - } - SerialManager_AddTail(&handle->runningWriteHandleHead, serialWriteHandle); - EnableGlobalIRQ(primask); - - if (isEmpty != 0U) - { - status = SerialManager_StartWriting(handle); - if ((serial_manager_status_t)kStatus_SerialManager_Success != status) - { - return status; - } - } - - if (kSerialManager_TransmissionBlocking == mode) - { - while (serialWriteHandle->transfer.length > serialWriteHandle->transfer.soFar) - { -#if defined(__GIC_PRIO_BITS) - if ((__get_CPSR() & CPSR_M_Msk) == 0x13) -#else - if (__get_IPSR() != 0U) -#endif - { - SerialManager_IsrFunction(handle); - } - } - } - return kStatus_SerialManager_Success; -} - -static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, - uint8_t *buffer, - uint32_t length, - serial_manager_transmission_mode_t mode, - uint32_t *receivedLength) -{ - serial_manager_read_handle_t *serialReadHandle; - serial_manager_handle_t *handle; - uint32_t dataLength; - uint32_t primask; - - assert(readHandle); - assert(buffer); - assert(length); - - serialReadHandle = (serial_manager_read_handle_t *)readHandle; - handle = serialReadHandle->serialManagerHandle; - - assert(handle); - assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); - assert(!((kSerialManager_TransmissionNonBlocking == mode) && (NULL == serialReadHandle->callback))); - - primask = DisableGlobalIRQ(); - if (serialReadHandle->transfer.buffer != NULL) - { - EnableGlobalIRQ(primask); - return kStatus_SerialManager_Busy; - } - serialReadHandle->transfer.buffer = buffer; - serialReadHandle->transfer.length = length; - serialReadHandle->transfer.soFar = 0U; - serialReadHandle->transfer.mode = mode; - - dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; - dataLength = dataLength % handle->ringBuffer.ringBufferSize; - - for (serialReadHandle->transfer.soFar = 0U; serialReadHandle->transfer.soFar < MIN(dataLength, length); - serialReadHandle->transfer.soFar++) - { - buffer[serialReadHandle->transfer.soFar] = handle->ringBuffer.ringBuffer[handle->ringBuffer.ringTail]; - handle->ringBuffer.ringTail++; - if (handle->ringBuffer.ringTail >= handle->ringBuffer.ringBufferSize) - { - handle->ringBuffer.ringTail = 0U; - } - } - - dataLength = handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail; - dataLength = dataLength % handle->ringBuffer.ringBufferSize; - dataLength = handle->ringBuffer.ringBufferSize - 1U - dataLength; - - (void)SerialManager_StartReading(handle, readHandle, NULL, dataLength); - - if (receivedLength != NULL) - { - *receivedLength = serialReadHandle->transfer.soFar; - serialReadHandle->transfer.buffer = NULL; - EnableGlobalIRQ(primask); - } - else - { - if (serialReadHandle->transfer.soFar >= serialReadHandle->transfer.length) - { - serialReadHandle->transfer.buffer = NULL; - EnableGlobalIRQ(primask); - if (kSerialManager_TransmissionNonBlocking == mode) - { - if (serialReadHandle->callback != NULL) - { - serial_manager_callback_message_t msg; - msg.buffer = buffer; - msg.length = serialReadHandle->transfer.soFar; - serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Success); - } - } - } - else - { - EnableGlobalIRQ(primask); - } - - if (kSerialManager_TransmissionBlocking == mode) - { - while (serialReadHandle->transfer.length > serialReadHandle->transfer.soFar) - { - } - } - } - - return kStatus_SerialManager_Success; -} - -#else - -static serial_manager_status_t SerialManager_Write(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length) -{ - serial_manager_write_handle_t *serialWriteHandle; - serial_manager_handle_t *handle; - - assert(writeHandle); - assert(buffer); - assert(length); - - serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; - handle = serialWriteHandle->serialManagerHandle; - - assert(handle); - - return SerialManager_StartWriting(handle, serialWriteHandle, buffer, length); -} - -static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) -{ - serial_manager_read_handle_t *serialReadHandle; - serial_manager_handle_t *handle; - - assert(readHandle); - assert(buffer); - assert(length); - - serialReadHandle = (serial_manager_read_handle_t *)readHandle; - handle = serialReadHandle->serialManagerHandle; - - assert(handle); - - return SerialManager_StartReading(handle, serialReadHandle, buffer, length); -} -#endif - -serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config) -{ - serial_manager_handle_t *handle; - serial_manager_status_t status = kStatus_SerialManager_Error; - - assert(config); -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - assert(config->ringBuffer); - assert(config->ringBufferSize); -#endif - assert(serialHandle); - assert(SERIAL_MANAGER_HANDLE_SIZE >= sizeof(serial_manager_handle_t)); - - handle = (serial_manager_handle_t *)serialHandle; - - (void)memset(handle, 0, SERIAL_MANAGER_HANDLE_SIZE); - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - -#if defined(OSA_USED) - -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) - - COMMON_TASK_init(); - -#else - if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)handle->event, true)) - { - return kStatus_SerialManager_Error; - } - - if (KOSA_StatusSuccess != OSA_TaskCreate((osa_task_handle_t)handle->taskId, OSA_TASK(SerialManager_Task), handle)) - { - return kStatus_SerialManager_Error; - } -#endif - -#endif - -#endif - - handle->type = config->type; - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - handle->ringBuffer.ringBuffer = config->ringBuffer; - handle->ringBuffer.ringBufferSize = config->ringBufferSize; -#endif - - switch (config->type) - { -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - case kSerialPort_Uart: - status = Serial_UartInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - if ((serial_manager_status_t)kStatus_SerialManager_Success == status) - { - status = Serial_UartInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); - if ((serial_manager_status_t)kStatus_SerialManager_Success == status) - { - status = Serial_UartInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_RxCallback, handle); - } - } -#endif - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - case kSerialPort_UsbCdc: - status = Serial_UsbCdcInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - if (kStatus_SerialManager_Success == status) - { - status = Serial_UsbCdcInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); - if (kStatus_SerialManager_Success == status) - { - status = Serial_UsbCdcInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_RxCallback, handle); - } - } -#endif - break; -#endif -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - case kSerialPort_Swo: - status = Serial_SwoInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - if (kStatus_SerialManager_Success == status) - { - status = Serial_SwoInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); - } -#endif - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - case kSerialPort_UsbCdcVirtual: - status = Serial_UsbCdcVirtualInit(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), config->portConfig); -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - if (kStatus_SerialManager_Success == status) - { - status = Serial_UsbCdcVirtualInstallTxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_TxCallback, handle); - if (kStatus_SerialManager_Success == status) - { - status = Serial_UsbCdcVirtualInstallRxCallback(((serial_handle_t)&handle->lowLevelhandleBuffer[0]), - SerialManager_RxCallback, handle); - } - } -#endif - break; -#endif - default: - /*MISRA rule 16.4*/ - break; - } - - return status; -} - -serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle) -{ - serial_manager_handle_t *handle; - - assert(serialHandle); - - handle = (serial_manager_handle_t *)serialHandle; - - if ((handle->openedReadHandleHead != NULL) || (handle->openedWriteHandleCount != 0U)) - { - return kStatus_SerialManager_Busy; - } - - switch (handle->type) - { -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - case kSerialPort_Uart: - (void)Serial_UartDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - case kSerialPort_UsbCdc: - (void)Serial_UsbCdcDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - case kSerialPort_Swo: - (void)Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - case kSerialPort_UsbCdcVirtual: - Serial_UsbCdcVirtualDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); - (void)Serial_SwoDeinit(((serial_handle_t)&handle->lowLevelhandleBuffer[0])); - break; -#endif - default: - /*MISRA rule 16.4*/ - break; - } -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - -#if defined(OSA_USED) - -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) -#else - OSA_EventDestroy((osa_event_handle_t)handle->event); - OSA_TaskDestroy((osa_task_handle_t)handle->taskId); -#endif - -#endif - -#endif - - return kStatus_SerialManager_Success; -} - -serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle) -{ - serial_manager_handle_t *handle; - serial_manager_write_handle_t *serialWriteHandle; - - assert(serialHandle); - assert(writeHandle); - assert(SERIAL_MANAGER_WRITE_HANDLE_SIZE >= sizeof(serial_manager_write_handle_t)); - - handle = (serial_manager_handle_t *)serialHandle; - serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; - - (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); - - handle->openedWriteHandleCount++; - - serialWriteHandle->serialManagerHandle = handle; -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - serialWriteHandle->tag = SERIAL_MANAGER_WRITE_TAG; -#endif - - return kStatus_SerialManager_Success; -} - -serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle) -{ - serial_manager_handle_t *handle; - serial_manager_write_handle_t *serialWriteHandle; - - assert(writeHandle); - - serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; - handle = (serial_manager_handle_t *)(void *)serialWriteHandle->serialManagerHandle; - - assert(handle); -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); -#endif - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - (void)SerialManager_CancelWriting(writeHandle); -#endif - - handle->openedWriteHandleCount--; - (void)memset(writeHandle, 0, SERIAL_MANAGER_WRITE_HANDLE_SIZE); - - return kStatus_SerialManager_Success; -} - -serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle) -{ - serial_manager_handle_t *handle; - serial_manager_read_handle_t *serialReadHandle; - - assert(serialHandle); - assert(readHandle); - assert(SERIAL_MANAGER_READ_HANDLE_SIZE >= sizeof(serial_manager_read_handle_t)); - - handle = (serial_manager_handle_t *)serialHandle; - serialReadHandle = (serial_manager_read_handle_t *)readHandle; - - if (handle->openedReadHandleHead != NULL) - { - return kStatus_SerialManager_Busy; - } - (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); - - handle->openedReadHandleHead = serialReadHandle; - - serialReadHandle->serialManagerHandle = handle; -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - serialReadHandle->tag = SERIAL_MANAGER_READ_TAG; -#endif - - return kStatus_SerialManager_Success; -} - -serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle) -{ - serial_manager_handle_t *handle; - serial_manager_read_handle_t *serialReadHandle; - - assert(readHandle); - - serialReadHandle = (serial_manager_read_handle_t *)readHandle; - handle = (serial_manager_handle_t *)(void *)serialReadHandle->serialManagerHandle; - - assert(handle); -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); -#endif - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - (void)SerialManager_CancelReading(readHandle); -#endif - - handle->openedReadHandleHead = NULL; - (void)memset(readHandle, 0, SERIAL_MANAGER_READ_HANDLE_SIZE); - - return kStatus_SerialManager_Success; -} - -serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, uint8_t *buffer, uint32_t length) -{ -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionBlocking); -#else - return SerialManager_Write(writeHandle, buffer, length); -#endif -} - -serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) -{ -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, NULL); -#else - return SerialManager_Read(readHandle, buffer, length); -#endif -} - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle, - uint8_t *buffer, - uint32_t length) -{ - return SerialManager_Write(writeHandle, buffer, length, kSerialManager_TransmissionNonBlocking); -} - -serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length) -{ - return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionNonBlocking, NULL); -} - -serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle) -{ - serial_manager_write_handle_t *serialWriteHandle; - uint32_t primask; - uint8_t isNotUsed = 0; - - assert(writeHandle); - - serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; - - assert(serialWriteHandle->serialManagerHandle); - assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); - - if ((serialWriteHandle->transfer.buffer != NULL) && - (kSerialManager_TransmissionBlocking == serialWriteHandle->transfer.mode)) - { - return kStatus_SerialManager_Error; - } - - primask = DisableGlobalIRQ(); - if (serialWriteHandle != (serial_manager_write_handle_t *)(void *)LIST_GetHead( - &serialWriteHandle->serialManagerHandle->runningWriteHandleHead)) - { - (void)LIST_RemoveElement(&serialWriteHandle->link); - isNotUsed = 1; - } - EnableGlobalIRQ(primask); - - if (isNotUsed != 0U) - { - serialWriteHandle->transfer.soFar = 0; - serialWriteHandle->transfer.status = kStatus_SerialManager_Canceled; - - SerialManager_AddTail(&serialWriteHandle->serialManagerHandle->completedWriteHandleHead, serialWriteHandle); -#if defined(OSA_USED) - -#if (defined(SERIAL_MANAGER_USE_COMMON_TASK) && (SERIAL_MANAGER_USE_COMMON_TASK > 0U)) - serialWriteHandle->serialManagerHandle->commontaskMsg.callback = SerialManager_Task; - serialWriteHandle->serialManagerHandle->commontaskMsg.callbackParam = serialWriteHandle->serialManagerHandle; - COMMON_TASK_post_message(&serialWriteHandle->serialManagerHandle->commontaskMsg); -#else - (void)OSA_EventSet((osa_event_handle_t)serialWriteHandle->serialManagerHandle->event, SERIAL_EVENT_DATA_SENT); -#endif - -#else - SerialManager_Task(serialWriteHandle->serialManagerHandle); -#endif - } - else - { - switch (serialWriteHandle->serialManagerHandle->type) - { -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - case kSerialPort_Uart: - (void)Serial_UartCancelWrite( - ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - case kSerialPort_UsbCdc: - (void)Serial_UsbCdcCancelWrite( - ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - case kSerialPort_Swo: - (void)Serial_SwoCancelWrite( - ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); - break; -#endif -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - case kSerialPort_UsbCdcVirtual: - Serial_UsbCdcVirtualCancelWrite( - (void)Serial_SwoCancelWrite( - ((serial_handle_t)&serialWriteHandle->serialManagerHandle->lowLevelhandleBuffer[0])); - break; -#endif - default: - /*MISRA rule 16.4*/ - break; - } - } - - (void)SerialManager_StartWriting(serialWriteHandle->serialManagerHandle); - - return kStatus_SerialManager_Success; -} - -serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle) -{ - serial_manager_read_handle_t *serialReadHandle; - serial_manager_callback_message_t msg; - uint8_t *buffer; - uint32_t primask; - - assert(readHandle); - - serialReadHandle = (serial_manager_read_handle_t *)readHandle; - - assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); - - if ((serialReadHandle->transfer.buffer != NULL) && - (kSerialManager_TransmissionBlocking == serialReadHandle->transfer.mode)) - { - return kStatus_SerialManager_Error; - } - - primask = DisableGlobalIRQ(); - buffer = serialReadHandle->transfer.buffer; - serialReadHandle->transfer.buffer = NULL; - serialReadHandle->transfer.length = 0; - msg.buffer = buffer; - msg.length = serialReadHandle->transfer.soFar; - EnableGlobalIRQ(primask); - - if (buffer != NULL) - { - if (serialReadHandle->callback != NULL) - { - serialReadHandle->callback(serialReadHandle->callbackParam, &msg, kStatus_SerialManager_Canceled); - } - } - return kStatus_SerialManager_Success; -} - -serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle, - uint8_t *buffer, - uint32_t length, - uint32_t *receivedLength) -{ - assert(receivedLength); - - return SerialManager_Read(readHandle, buffer, length, kSerialManager_TransmissionBlocking, receivedLength); -} - -serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle, - serial_manager_callback_t callback, - void *callbackParam) -{ - serial_manager_write_handle_t *serialWriteHandle; - - assert(writeHandle); - - serialWriteHandle = (serial_manager_write_handle_t *)writeHandle; - - assert(SERIAL_MANAGER_WRITE_TAG == serialWriteHandle->tag); - - serialWriteHandle->callbackParam = callbackParam; - serialWriteHandle->callback = callback; - - return kStatus_SerialManager_Success; -} - -serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle, - serial_manager_callback_t callback, - void *callbackParam) -{ - serial_manager_read_handle_t *serialReadHandle; - - assert(readHandle); - - serialReadHandle = (serial_manager_read_handle_t *)readHandle; - - assert(SERIAL_MANAGER_READ_TAG == serialReadHandle->tag); - - serialReadHandle->callbackParam = callbackParam; - serialReadHandle->callback = callback; - - return kStatus_SerialManager_Success; -} -#endif - -serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle) -{ - assert(serialHandle); - - return kStatus_SerialManager_Success; -} - -serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle) -{ - assert(serialHandle); - - return kStatus_SerialManager_Success; -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_manager.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_manager.h deleted file mode 100644 index 14af2c07c..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_manager.h +++ /dev/null @@ -1,548 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __SERIAL_MANAGER_H__ -#define __SERIAL_MANAGER_H__ - -/*! - * @addtogroup serialmanager - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */ -#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U) -#else -#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE -#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U) -#endif -#endif - -/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */ -#ifndef SERIAL_PORT_TYPE_UART -#define SERIAL_PORT_TYPE_UART (1U) -#endif - -/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */ -#ifndef SERIAL_PORT_TYPE_USBCDC -#define SERIAL_PORT_TYPE_USBCDC (0U) -#endif - -/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */ -#ifndef SERIAL_PORT_TYPE_SWO -#define SERIAL_PORT_TYPE_SWO (0U) -#endif - -/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */ -#ifndef SERIAL_PORT_TYPE_USBCDC_VIRTUAL -#define SERIAL_PORT_TYPE_USBCDC_VIRTUAL (0U) -#endif - -/*! @brief Set serial manager write handle size */ -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U) -#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U) -#else -#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U) -#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U) -#endif - -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) -#include "serial_port_uart.h" -#endif - -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - -#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -#error The serial manager blocking mode cannot be supported for USB CDC. -#endif - -#include "serial_port_usb.h" -#endif - -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) -#include "serial_port_swo.h" -#endif - -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - -#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -#error The serial manager blocking mode cannot be supported for USB CDC. -#endif - -#include "serial_port_usb_virtual.h" -#endif - -#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - -#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) -#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP -#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE -#endif - -#endif - -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - -#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) -#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP -#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE -#endif - -#endif - -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - -#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) -#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP -#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE -#endif - -#endif - -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - -#if (SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP) -#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP -#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE -#endif - -#endif - -/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */ -#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U))) -#else -#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_USBCDC_VIRTUAL should not be cleared at same time. -#endif - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U) -#else -#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U) -#endif - -#define SERIAL_MANAGER_USE_COMMON_TASK (1U) -#define SERIAL_MANAGER_TASK_PRIORITY (2U) -#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U) - -typedef void *serial_handle_t; -typedef void *serial_write_handle_t; -typedef void *serial_read_handle_t; - -/*! @brief serial port type*/ -typedef enum _serial_port_type -{ - kSerialPort_Uart = 1U, /*!< Serial port UART */ - kSerialPort_UsbCdc, /*!< Serial port USB CDC */ - kSerialPort_Swo, /*!< Serial port SWO */ - kSerialPort_UsbCdcVirtual, /*!< Serial port USB CDC Virtual */ -} serial_port_type_t; - -/*! @brief serial manager config structure*/ -typedef struct _serial_manager_config -{ - uint8_t *ringBuffer; /*!< Ring buffer address, it is used to buffer data received by the hardware. - Besides, the memory space cannot be free during the lifetime of the serial - manager module. */ - uint32_t ringBufferSize; /*!< The size of the ring buffer */ - serial_port_type_t type; /*!< Serial port type */ - void *portConfig; /*!< Serial port configuration */ -} serial_manager_config_t; - -/*! @brief serial manager error code*/ -typedef enum _serial_manager_status -{ - kStatus_SerialManager_Success = kStatus_Success, /*!< Success */ - kStatus_SerialManager_Error = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */ - kStatus_SerialManager_Busy = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */ - kStatus_SerialManager_Notify = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */ - kStatus_SerialManager_Canceled = - MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */ - kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */ - kStatus_SerialManager_RingBufferOverflow = - MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */ -} serial_manager_status_t; - -/*! @brief Callback message structure */ -typedef struct _serial_manager_callback_message -{ - uint8_t *buffer; /*!< Transferred buffer */ - uint32_t length; /*!< Transferred data length */ -} serial_manager_callback_message_t; - -/*! @brief callback function */ -typedef void (*serial_manager_callback_t)(void *callbackParam, - serial_manager_callback_message_t *message, - serial_manager_status_t status); - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure. - * - * This function configures the Serial Manager module with user-defined settings. The user can configure the - * configuration - * structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE - * allocated by the caller. - * The Serial Manager module supports two types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc) and USB - * CDC. - * Please refer to #serial_port_type_t for serial port setting. These two types can be set by using - * #serial_manager_config_t. - * - * Example below shows how to use this API to configure the Serial Manager. - * For UART, - * @code - * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U) - * static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE]; - * static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0]; - * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE]; - * - * serial_manager_config_t config; - * serial_port_uart_config_t uartConfig; - * config.type = kSerialPort_Uart; - * config.ringBuffer = &s_ringBuffer[0]; - * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE; - * uartConfig.instance = 0; - * uartConfig.clockRate = 24000000; - * uartConfig.baudRate = 115200; - * uartConfig.parityMode = kSerialManager_UartParityDisabled; - * uartConfig.stopBitCount = kSerialManager_UartOneStopBit; - * uartConfig.enableRx = 1; - * uartConfig.enableTx = 1; - * config.portConfig = &uartConfig; - * SerialManager_Init(s_serialHandle, &config); - * @endcode - * For USB CDC, - * @code - * #define SERIAL_MANAGER_RING_BUFFER_SIZE (256U) - * static uint8_t s_serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE]; - * static serial_handle_t s_serialHandle = &s_serialHandleBuffer[0]; - * static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE]; - * - * serial_manager_config_t config; - * serial_port_usb_cdc_config_t usbCdcConfig; - * config.type = kSerialPort_UsbCdc; - * config.ringBuffer = &s_ringBuffer[0]; - * config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE; - * usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0; - * config.portConfig = &usbCdcConfig; - * SerialManager_Init(s_serialHandle, &config); - * @endcode - * - * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller. - * @param config Pointer to user-defined configuration structure. - * @retval kStatus_SerialManager_Error An error occurred. - * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed. - */ -serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config); - -/*! - * @brief De-initializes the serial manager module instance. - * - * This function de-initializes the serial manager module instance. If the opened writing or - * reading handle is not closed, the function will return kStatus_SerialManager_Busy. - * - * @param serialHandle The serial manager module handle pointer. - * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed. - * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed. - */ -serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle); - -/*! - * @brief Opens a writing handle for the serial manager module. - * - * This function Opens a writing handle for the serial manager module. If the serial manager needs to - * be used in different tasks, the task should open a dedicated write handle for itself by calling - * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing - * handle at the same time, multiple writing handles need to be opened when the multiple transmission - * is needed for a task. - * - * @param serialHandle The serial manager module handle pointer. - * @param writeHandle The serial manager module writing handle pointer. - * @retval kStatus_SerialManager_Error An error occurred. - * @retval kStatus_SerialManager_HandleConflict The writing handle was opened. - * @retval kStatus_SerialManager_Success The writing handle is opened. - * - * Example below shows how to use this API to write data. - * For task 1, - * @code - * static uint8_t s_serialWriteHandleBuffer1[SERIAL_MANAGER_WRITE_HANDLE_SIZE]; - * static serial_write_handle_t s_serialWriteHandle1 = &s_serialWriteHandleBuffer1[0]; - * static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking writing log for task1!\r\n"; - * SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1); - * SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1); - * SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1); - * @endcode - * For task 2, - * @code - * static uint8_t s_serialWriteHandleBuffer2[SERIAL_MANAGER_WRITE_HANDLE_SIZE]; - * static serial_write_handle_t s_serialWriteHandle2 = &s_serialWriteHandleBuffer2[0]; - * static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking writing log for task2!\r\n"; - * SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2); - * SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2); - * SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1); - * @endcode - */ -serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle); - -/*! - * @brief Closes a writing handle for the serial manager module. - * - * This function Closes a writing handle for the serial manager module. - * - * @param writeHandle The serial manager module writing handle pointer. - * @retval kStatus_SerialManager_Success The writing handle is closed. - */ -serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle); - -/*! - * @brief Opens a reading handle for the serial manager module. - * - * This function Opens a reading handle for the serial manager module. The reading handle can not be - * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when - * the previous reading handle is not closed. And There can only be one buffer for receiving for the - * reading handle at the same time. - * - * @param serialHandle The serial manager module handle pointer. - * @param readHandle The serial manager module reading handle pointer. - * @retval kStatus_SerialManager_Error An error occurred. - * @retval kStatus_SerialManager_Success The reading handle is opened. - * @retval kStatus_SerialManager_Busy Previous reading handle is not closed. - * - * Example below shows how to use this API to read data. - * @code - * static uint8_t s_serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE]; - * static serial_read_handle_t s_serialReadHandle = &s_serialReadHandleBuffer[0]; - * SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle); - * static uint8_t s_nonBlockingBuffer[64]; - * SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle); - * SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer)); - * @endcode - */ -serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle); - -/*! - * @brief Closes a reading for the serial manager module. - * - * This function Closes a reading for the serial manager module. - * - * @param readHandle The serial manager module reading handle pointer. - * @retval kStatus_SerialManager_Success The reading handle is closed. - */ -serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle); - -/*! - * @brief Transmits data with the blocking mode. - * - * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty. - * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled. - * And There can only one buffer for transmission for the writing handle at the same time. - * - * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking - * cannot be used at the same time. - * And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function. - * - * @param writeHandle The serial manager module handle pointer. - * @param buffer Start address of the data to write. - * @param length Length of the data to write. - * @retval kStatus_SerialManager_Success Successfully sent all data. - * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet. - * @retval kStatus_SerialManager_Error An error occurred. - */ -serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle, - uint8_t *buffer, - uint32_t length); - -/*! - * @brief Reads data with the blocking mode. - * - * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full. - * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled. - * And There can only one buffer for receiving for the reading handle at the same time. - * - * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking - * cannot be used at the same time. - * And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function. - * - * @param readHandle The serial manager module handle pointer. - * @param buffer Start address of the data to store the received data. - * @param length The length of the data to be received. - * @retval kStatus_SerialManager_Success Successfully received all data. - * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. - * @retval kStatus_SerialManager_Error An error occurred. - */ -serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length); - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -/*! - * @brief Transmits data with the non-blocking mode. - * - * This is a non-blocking function, which returns directly without waiting for all data to be sent. - * When all data is sent, the module notifies the upper layer through a TX callback function and passes - * the status parameter @ref kStatus_SerialManager_Success. - * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled. - * And There can only one buffer for transmission for the writing handle at the same time. - * - * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking - * cannot be used at the same time. And, the TX callback is mandatory before the function could be used. - * - * @param writeHandle The serial manager module handle pointer. - * @param buffer Start address of the data to write. - * @param length Length of the data to write. - * @retval kStatus_SerialManager_Success Successfully sent all data. - * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet. - * @retval kStatus_SerialManager_Error An error occurred. - */ -serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle, - uint8_t *buffer, - uint32_t length); - -/*! - * @brief Reads data with the non-blocking mode. - * - * This is a non-blocking function, which returns directly without waiting for all data to be received. - * When all data is received, the module driver notifies the upper layer - * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success. - * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled. - * And There can only one buffer for receiving for the reading handle at the same time. - * - * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking - * cannot be used at the same time. And, the RX callback is mandatory before the function could be used. - * - * @param readHandle The serial manager module handle pointer. - * @param buffer Start address of the data to store the received data. - * @param length The length of the data to be received. - * @retval kStatus_SerialManager_Success Successfully received all data. - * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. - * @retval kStatus_SerialManager_Error An error occurred. - */ -serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle, - uint8_t *buffer, - uint32_t length); - -/*! - * @brief Tries to read data. - * - * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be - * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length. - * After the data is copied, the actual data length is passed by the parameter length. - * And There can only one buffer for receiving for the reading handle at the same time. - * - * @param readHandle The serial manager module handle pointer. - * @param buffer Start address of the data to store the received data. - * @param length The length of the data to be received. - * @param receivedLength Length received from the ring buffer directly. - * @retval kStatus_SerialManager_Success Successfully received all data. - * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet. - * @retval kStatus_SerialManager_Error An error occurred. - */ -serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle, - uint8_t *buffer, - uint32_t length, - uint32_t *receivedLength); - -/*! - * @brief Cancels unfinished send transmission. - * - * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer - * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled. - * - * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of - * the function #SerialManager_WriteBlocking. - * - * @param writeHandle The serial manager module handle pointer. - * @retval kStatus_SerialManager_Success Get successfully abort the sending. - * @retval kStatus_SerialManager_Error An error occurred. - */ -serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle); - -/*! - * @brief Cancels unfinished receive transmission. - * - * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper - * layer - * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled. - * - * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of - * the function #SerialManager_ReadBlocking. - * - * @param readHandle The serial manager module handle pointer. - * @retval kStatus_SerialManager_Success Get successfully abort the receiving. - * @retval kStatus_SerialManager_Error An error occurred. - */ -serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle); - -/*! - * @brief Installs a TX callback and callback parameter. - * - * This function is used to install the TX callback and callback parameter for the serial manager module. - * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback - * function. And the status is also passed as status parameter when the callback is called. - * - * @param writeHandle The serial manager module handle pointer. - * @param callback The callback function. - * @param callbackParam The parameter of the callback function. - * @retval kStatus_SerialManager_Success Successfully install the callback. - */ -serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle, - serial_manager_callback_t callback, - void *callbackParam); - -/*! - * @brief Installs a RX callback and callback parameter. - * - * This function is used to install the RX callback and callback parameter for the serial manager module. - * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback - * function. And the status is also passed as status parameter when the callback is called. - * - * @param readHandle The serial manager module handle pointer. - * @param callback The callback function. - * @param callbackParam The parameter of the callback function. - * @retval kStatus_SerialManager_Success Successfully install the callback. - */ -serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle, - serial_manager_callback_t callback, - void *callbackParam); - -#endif - -/*! - * @brief Prepares to enter low power consumption. - * - * This function is used to prepare to enter low power consumption. - * - * @param serialHandle The serial manager module handle pointer. - * @retval kStatus_SerialManager_Success Successful operation. - */ -serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle); - -/*! - * @brief Restores from low power consumption. - * - * This function is used to restore from low power consumption. - * - * @param serialHandle The serial manager module handle pointer. - * @retval kStatus_SerialManager_Success Successful operation. - */ -serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle); - -#if defined(__cplusplus) -} -#endif -/*! @} */ -#endif /* __SERIAL_MANAGER_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_port_internal.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_port_internal.h deleted file mode 100644 index 0534363a0..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_port_internal.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __SERIAL_PORT_INTERNAL_H__ -#define __SERIAL_PORT_INTERNAL_H__ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) -serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig); -serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle); -serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); -#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); -#endif - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle); -serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam); -serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam); -void Serial_UartIsrFunction(serial_handle_t serialHandle); -#endif - -#endif - -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) -serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config); -serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle); -serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); -serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); -serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle); -serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam); -serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam); -void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle); -#endif - -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) -serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config); -serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle); -serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); -#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); -#endif -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle); -serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam); -serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam); -void Serial_SwoIsrFunction(serial_handle_t serialHandle); -#endif -#endif - -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) -serial_manager_status_t Serial_UsbCdcVirtualInit(serial_handle_t serialHandle, void *config); -serial_manager_status_t Serial_UsbCdcVirtualDeinit(serial_handle_t serialHandle); -serial_manager_status_t Serial_UsbCdcVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); -serial_manager_status_t Serial_UsbCdcVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length); -serial_manager_status_t Serial_UsbCdcVirtualCancelWrite(serial_handle_t serialHandle); -serial_manager_status_t Serial_UsbCdcVirtualInstallTxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam); -serial_manager_status_t Serial_UsbCdcVirtualInstallRxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam); -void Serial_UsbCdcVirtualIsrFunction(serial_handle_t serialHandle); -#endif - -#if defined(__cplusplus) -} -#endif - -#endif /* __SERIAL_PORT_INTERNAL_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_port_uart.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_port_uart.c deleted file mode 100644 index 30ee298de..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_port_uart.c +++ /dev/null @@ -1,371 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "serial_manager.h" -#include "serial_port_internal.h" - -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) -#include "uart.h" - -#include "serial_port_uart.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#ifndef NDEBUG -#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) -#undef assert -#define assert(n) -#endif -#endif - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U - -typedef struct _serial_uart_send_state -{ - serial_manager_callback_t callback; - void *callbackParam; - uint8_t *buffer; - uint32_t length; - volatile uint8_t busy; -} serial_uart_send_state_t; - -typedef struct _serial_uart_recv_state -{ - serial_manager_callback_t callback; - void *callbackParam; - volatile uint8_t busy; - uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH]; -} serial_uart_recv_state_t; -#endif - -typedef struct _serial_uart_state -{ -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - serial_uart_send_state_t tx; - serial_uart_recv_state_t rx; -#endif - uint8_t usartHandleBuffer[HAL_UART_HANDLE_SIZE]; -} serial_uart_state_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -/* UART user callback */ -static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData) -{ - serial_uart_state_t *serialUartHandle; - serial_manager_callback_message_t msg; -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - hal_uart_transfer_t transfer; -#endif - - if (NULL == userData) - { - return; - } - - serialUartHandle = (serial_uart_state_t *)userData; - - if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status) - { - if ((NULL != serialUartHandle->rx.callback)) - { - msg.buffer = &serialUartHandle->rx.readBuffer[0]; - msg.length = sizeof(serialUartHandle->rx.readBuffer); - serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &msg, kStatus_SerialManager_Success); - } -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - transfer.data = &serialUartHandle->rx.readBuffer[0]; - transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer); - if (kStatus_HAL_UartSuccess == - HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer)) -#else - if ((hal_uart_status_t)kStatus_HAL_UartSuccess == - HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), - &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer))) -#endif - { - serialUartHandle->rx.busy = 1U; - } - else - { - serialUartHandle->rx.busy = 0U; - } - } - else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status) - { - if (serialUartHandle->tx.busy != 0U) - { - serialUartHandle->tx.busy = 0U; - if ((NULL != serialUartHandle->tx.callback)) - { - msg.buffer = serialUartHandle->tx.buffer; - msg.length = serialUartHandle->tx.length; - serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Success); - } - } - } - else - { - } -} -#endif - -serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig) -{ - serial_uart_state_t *serialUartHandle; - serial_port_uart_config_t *uartConfig; - hal_uart_config_t config; -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - hal_uart_transfer_t transfer; -#endif -#endif - - assert(serialConfig); - assert(serialHandle); - assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t)); - - uartConfig = (serial_port_uart_config_t *)serialConfig; - serialUartHandle = (serial_uart_state_t *)serialHandle; - - config.baudRate_Bps = uartConfig->baudRate; - config.parityMode = (hal_uart_parity_mode_t)uartConfig->parityMode; - config.stopBitCount = (hal_uart_stop_bit_count_t)uartConfig->stopBitCount; - config.enableRx = uartConfig->enableRx; - config.enableTx = uartConfig->enableTx; - config.srcClock_Hz = uartConfig->clockRate; - config.instance = uartConfig->instance; - - if (kStatus_HAL_UartSuccess != HAL_UartInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &config)) - { - return kStatus_SerialManager_Error; - } - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - if (kStatus_HAL_UartSuccess != - HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), - Serial_UartCallback, serialUartHandle)) -#else - if (kStatus_HAL_UartSuccess != HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), - Serial_UartCallback, serialUartHandle)) -#endif - { - return kStatus_SerialManager_Error; - } - - if (uartConfig->enableRx != 0U) - { - serialUartHandle->rx.busy = 1U; -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - transfer.data = &serialUartHandle->rx.readBuffer[0]; - transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer); - if (kStatus_HAL_UartSuccess != - HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer)) -#else - if (kStatus_HAL_UartSuccess != - HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), - &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer))) -#endif - { - serialUartHandle->rx.busy = 0U; - return kStatus_SerialManager_Error; - } - } -#endif - - return kStatus_SerialManager_Success; -} - -serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle) -{ - serial_uart_state_t *serialUartHandle; - - assert(serialHandle); - - serialUartHandle = (serial_uart_state_t *)serialHandle; - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); -#else - (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); -#endif -#endif - (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - serialUartHandle->tx.busy = 0U; - serialUartHandle->rx.busy = 0U; -#endif - - return kStatus_SerialManager_Success; -} - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) - -serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) -{ - serial_uart_state_t *serialUartHandle; -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - hal_uart_transfer_t transfer; -#endif - - assert(serialHandle); - assert(buffer); - assert(length); - - serialUartHandle = (serial_uart_state_t *)serialHandle; - - if (serialUartHandle->tx.busy != 0U) - { - return kStatus_SerialManager_Busy; - } - serialUartHandle->tx.busy = 1U; - - serialUartHandle->tx.buffer = buffer; - serialUartHandle->tx.length = length; - -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - transfer.data = buffer; - transfer.dataSize = length; - if (kStatus_HAL_UartSuccess != - HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer)) -#else - if (kStatus_HAL_UartSuccess != - HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length)) -#endif - { - serialUartHandle->tx.busy = 0U; - return kStatus_SerialManager_Error; - } - return kStatus_SerialManager_Success; -} - -#else - -serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) -{ - serial_uart_state_t *serialUartHandle; - - assert(serialHandle); - assert(buffer); - assert(length); - - serialUartHandle = (serial_uart_state_t *)serialHandle; - - return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), - buffer, length); -} - -serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length) -{ - serial_uart_state_t *serialUartHandle; - - assert(serialHandle); - assert(buffer); - assert(length); - - serialUartHandle = (serial_uart_state_t *)serialHandle; - - return (serial_manager_status_t)HAL_UartReceiveBlocking( - ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length); -} - -#endif - -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle) -{ - serial_uart_state_t *serialUartHandle; - serial_manager_callback_message_t msg; - uint32_t primask; - uint8_t isBusy = 0U; - - assert(serialHandle); - - serialUartHandle = (serial_uart_state_t *)serialHandle; - - primask = DisableGlobalIRQ(); - isBusy = serialUartHandle->tx.busy; - serialUartHandle->tx.busy = 0U; - EnableGlobalIRQ(primask); - -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); -#else - (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); -#endif - if (isBusy != 0U) - { - if ((NULL != serialUartHandle->tx.callback)) - { - msg.buffer = serialUartHandle->tx.buffer; - msg.length = serialUartHandle->tx.length; - serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Canceled); - } - } - return kStatus_SerialManager_Success; -} - -serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam) -{ - serial_uart_state_t *serialUartHandle; - - assert(serialHandle); - - serialUartHandle = (serial_uart_state_t *)serialHandle; - - serialUartHandle->tx.callback = callback; - serialUartHandle->tx.callbackParam = callbackParam; - - return kStatus_SerialManager_Success; -} - -serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle, - serial_manager_callback_t callback, - void *callbackParam) -{ - serial_uart_state_t *serialUartHandle; - - assert(serialHandle); - - serialUartHandle = (serial_uart_state_t *)serialHandle; - - serialUartHandle->rx.callback = callback; - serialUartHandle->rx.callbackParam = callbackParam; - - return kStatus_SerialManager_Success; -} - -void Serial_UartIsrFunction(serial_handle_t serialHandle) -{ - serial_uart_state_t *serialUartHandle; - - assert(serialHandle); - - serialUartHandle = (serial_uart_state_t *)serialHandle; - - HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])); -} -#endif - -#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_port_uart.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_port_uart.h deleted file mode 100644 index 24a717009..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/serial_manager/serial_port_uart.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __SERIAL_PORT_UART_H__ -#define __SERIAL_PORT_UART_H__ - -/*! - * @addtogroup serial_port_uart - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief serial port uart handle size*/ -#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U)) -#define SERIAL_PORT_UART_HANDLE_SIZE (166U) -#else -#define SERIAL_PORT_UART_HANDLE_SIZE (4U) -#endif - -/*! @brief serial port uart parity mode*/ -typedef enum _serial_port_uart_parity_mode -{ - kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */ - kSerialManager_UartParityEven = 0x1U, /*!< Parity even enabled */ - kSerialManager_UartParityOdd = 0x2U, /*!< Parity odd enabled */ -} serial_port_uart_parity_mode_t; - -/*! @brief serial port uart stop bit count*/ -typedef enum _serial_port_uart_stop_bit_count -{ - kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */ - kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */ -} serial_port_uart_stop_bit_count_t; - -/*! @brief serial port uart config struct*/ -typedef struct _serial_port_uart_config -{ - uint32_t clockRate; /*!< clock rate */ - uint32_t baudRate; /*!< baud rate */ - serial_port_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information - please refer to the SOC corresponding RM. */ - uint8_t enableRx; /*!< Enable RX */ - uint8_t enableTx; /*!< Enable TX */ -} serial_port_uart_config_t; -/*! @} */ -#endif /* __SERIAL_PORT_UART_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/uart/uart.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/uart/uart.h deleted file mode 100644 index 8fe377790..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/uart/uart.h +++ /dev/null @@ -1,475 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef __HAL_UART_ADAPTER_H__ -#define __HAL_UART_ADAPTER_H__ - -#if defined(FSL_RTOS_FREE_RTOS) -#include "FreeRTOS.h" -#endif - -/*! - * @addtogroup UART_Adapter - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */ -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -#define UART_ADAPTER_NON_BLOCKING_MODE (1U) -#else -#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE -#define UART_ADAPTER_NON_BLOCKING_MODE (0U) -#else -#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE -#endif -#endif - -#if defined(__GIC_PRIO_BITS) -#define HAL_UART_ISR_PRIORITY (25U) -#else -#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) -#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY) -#else -/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc. - * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum - * priority is 3 (2^2 - 1). So, the default value is 3. - */ -#define HAL_UART_ISR_PRIORITY (3U) -#endif -#endif - -#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) -#define HAL_UART_HANDLE_SIZE (90U) -#else -#define HAL_UART_HANDLE_SIZE (4U) -#endif - -/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */ -#define HAL_UART_TRANSFER_MODE (0U) - -typedef void *hal_uart_handle_t; - -/*! @brief UART status */ -typedef enum _hal_uart_status -{ - kStatus_HAL_UartSuccess = kStatus_Success, /*!< Successfully */ - kStatus_HAL_UartTxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */ - kStatus_HAL_UartRxBusy = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */ - kStatus_HAL_UartTxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */ - kStatus_HAL_UartRxIdle = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */ - kStatus_HAL_UartBaudrateNotSupport = - MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */ - kStatus_HAL_UartProtocolError = MAKE_STATUS( - kStatusGroup_HAL_UART, - 6), /*!< Error occurs for Noise, Framing, Parity, etc. - For transactional transfer, The up layer needs to abort the transfer and then starts again */ - kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */ -} hal_uart_status_t; - -/*! @brief UART parity mode. */ -typedef enum _hal_uart_parity_mode -{ - kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */ - kHAL_UartParityEven = 0x1U, /*!< Parity even enabled */ - kHAL_UartParityOdd = 0x2U, /*!< Parity odd enabled */ -} hal_uart_parity_mode_t; - -/*! @brief UART stop bit count. */ -typedef enum _hal_uart_stop_bit_count -{ - kHAL_UartOneStopBit = 0U, /*!< One stop bit */ - kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */ -} hal_uart_stop_bit_count_t; - -/*! @brief UART configuration structure. */ -typedef struct _hal_uart_config -{ - uint32_t srcClock_Hz; /*!< Source clock */ - uint32_t baudRate_Bps; /*!< Baud rate */ - hal_uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - uint8_t enableRx; /*!< Enable RX */ - uint8_t enableTx; /*!< Enable TX */ - uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the - SOC corresponding RM. - Invalid instance value will cause initialization failure. */ -} hal_uart_config_t; - -/*! @brief UART transfer callback function. */ -typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam); - -/*! @brief UART transfer structure. */ -typedef struct _hal_uart_transfer -{ - uint8_t *data; /*!< The buffer of data to be transfer.*/ - size_t dataSize; /*!< The byte count to be transfer. */ -} hal_uart_transfer_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes a UART instance with the UART handle and the user configuration structure. - * - * This function configures the UART module with user-defined settings. The user can configure the configuration - * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by - * the caller. Example below shows how to use this API to configure the UART. - * @code - * uint8_t g_UartHandleBuffer[HAL_UART_HANDLE_SIZE]; - * hal_uart_handle_t g_UartHandle = &g_UartHandleBuffer[0]; - * hal_uart_config_t config; - * config.srcClock_Hz = 48000000; - * config.baudRate_Bps = 115200U; - * config.parityMode = kHAL_UartParityDisabled; - * config.stopBitCount = kHAL_UartOneStopBit; - * config.enableRx = 1; - * config.enableTx = 1; - * config.instance = 0; - * HAL_UartInit(g_UartHandle, &config); - * @endcode - * - * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller. - * @param config Pointer to user-defined configuration structure. - * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_HAL_UartSuccess UART initialization succeed - */ -hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config); - -/*! - * @brief Deinitializes a UART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the UART clock. - * - * @param handle UART handle pointer. - * @retval kStatus_HAL_UartSuccess UART de-initialization succeed - */ -hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle); - -/*! @}*/ - -/*! - * @name Blocking bus Operations - * @{ - */ - -/*! - * @brief Reads RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data, and reads data from the RX register. - * - * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking - * cannot be used at the same time. - * And, the function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function. - * - * @param handle UART handle pointer. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_HAL_UartError An error occurred while receiving data. - * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data. - * @retval kStatus_HAL_UartSuccess Successfully received all data. - */ -hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); - -/*! - * @brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking - * cannot be used at the same time. - * And, the function #HAL_UartTransferAbortSend cannot be used to abort the transmission of this function. - * - * @param handle UART handle pointer. - * @param data Start address of the data to write. - * @param length Size of the data to write. - * @retval kStatus_HAL_UartSuccess Successfully sent all data. - */ -hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length); - -/*! @}*/ - -#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - -/*! - * @name Transactional - * @note The transactional API and the functional API cannot be used at the same time. The macro - * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the - * functional API with non-blocking mode will be used. Otherwise, transactional API will be used. - * @{ - */ - -/*! - * @brief Installs a callback and callback parameter. - * - * This function is used to install the callback and callback parameter for UART module. - * When any status of the UART changed, the driver will notify the upper layer by the installed callback - * function. And the status is also passed as status parameter when the callback is called. - * - * @param handle UART handle pointer. - * @param callback The callback function. - * @param callbackParam The parameter of the callback function. - * @retval kStatus_HAL_UartSuccess Successfully install the callback. - */ -hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, - hal_uart_transfer_callback_t callback, - void *callbackParam); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be received. - * The receive request is saved by the UART driver. - * When the new data arrives, the receive request is serviced first. - * When all data is received, the UART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. - * - * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking - * cannot be used at the same time. - * - * @param handle UART handle pointer. - * @param transfer UART transfer structure, see #hal_uart_transfer_t. - * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue. - * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished. - * @retval kStatus_HAL_UartError An error occurred. - */ -hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the ISR, the UART driver calls the callback - * function and passes the @ref kStatus_UART_TxIdle as status parameter. - * - * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking - * cannot be used at the same time. - * - * @param handle UART handle pointer. - * @param transfer UART transfer structure. See #hal_uart_transfer_t. - * @retval kStatus_HAL_UartSuccess Successfully start the data transmission. - * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet. - * @retval kStatus_HAL_UartError An error occurred. - */ -hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer); - -/*! - * @brief Gets the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param handle UART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_HAL_UartError An error occurred. - * @retval kStatus_Success Get successfully through the parameter \p count. - */ -hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count); - -/*! - * @brief Gets the number of bytes written to the UART TX register. - * - * This function gets the number of bytes written to the UART TX - * register by using the interrupt method. - * - * @param handle UART handle pointer. - * @param count Send bytes count. - * @retval kStatus_HAL_UartError An error occurred. - * @retval kStatus_Success Get successfully through the parameter \p count. - */ -hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know - * how many bytes are not received yet. - * - * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of - * the function #HAL_UartReceiveBlocking. - * - * @param handle UART handle pointer. - * @retval kStatus_Success Get successfully abort the receiving. - */ -hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle); - -/*! - * @brief Aborts the interrupt-driven data sending. - * - * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out - * how many bytes are not sent out. - * - * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of - * the function #HAL_UartSendBlocking. - * - * @param handle UART handle pointer. - * @retval kStatus_Success Get successfully abort the sending. - */ -hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle); - -/*! @}*/ - -#else - -/*! - * @name Functional API with non-blocking mode. - * @note The functional API and the transactional API cannot be used at the same time. The macro - * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the - * functional API with non-blocking mode will be used. Otherwise, transactional API will be used. - * @{ - */ - -/*! - * @brief Installs a callback and callback parameter. - * - * This function is used to install the callback and callback parameter for UART module. - * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback - * function. And the status is also passed as status parameter when the callback is called. - * - * @param handle UART handle pointer. - * @param callback The callback function. - * @param callbackParam The parameter of the callback function. - * @retval kStatus_HAL_UartSuccess Successfully install the callback. - */ -hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, - hal_uart_transfer_callback_t callback, - void *callbackParam); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be received. - * The receive request is saved by the UART adapter. - * When the new data arrives, the receive request is serviced first. - * When all data is received, the UART adapter notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. - * - * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking - * cannot be used at the same time. - * - * @param handle UART handle pointer. - * @param data Start address of the data to write. - * @param length Size of the data to write. - * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue. - * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished. - * @retval kStatus_HAL_UartError An error occurred. - */ -hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the ISR, the UART driver calls the callback - * function and passes the @ref kStatus_UART_TxIdle as status parameter. - * - * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking - * cannot be used at the same time. - * - * @param handle UART handle pointer. - * @param data Start address of the data to write. - * @param length Size of the data to write. - * @retval kStatus_HAL_UartSuccess Successfully start the data transmission. - * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet. - * @retval kStatus_HAL_UartError An error occurred. - */ -hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length); - -/*! - * @brief Gets the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param handle UART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_HAL_UartError An error occurred. - * @retval kStatus_Success Get successfully through the parameter \p count. - */ -hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount); - -/*! - * @brief Gets the number of bytes written to the UART TX register. - * - * This function gets the number of bytes written to the UART TX - * register by using the interrupt method. - * - * @param handle UART handle pointer. - * @param count Send bytes count. - * @retval kStatus_HAL_UartError An error occurred. - * @retval kStatus_Success Get successfully through the parameter \p count. - */ -hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know - * how many bytes are not received yet. - * - * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of - * the function #HAL_UartReceiveBlocking. - * - * @param handle UART handle pointer. - * @retval kStatus_Success Get successfully abort the receiving. - */ -hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle); - -/*! - * @brief Aborts the interrupt-driven data sending. - * - * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out - * how many bytes are not sent out. - * - * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of - * the function #HAL_UartSendBlocking. - * - * @param handle UART handle pointer. - * @retval kStatus_Success Get successfully abort the sending. - */ -hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle); - -/*! @}*/ - -#endif -#endif - -#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) -/*! - * @brief UART IRQ handle function. - * - * This function handles the UART transmit and receive IRQ request. - * - * @param handle UART handle pointer. - */ -void HAL_UartIsrFunction(hal_uart_handle_t handle); -#endif - -#if defined(__cplusplus) -} -#endif -/*! @}*/ -#endif /* __HAL_UART_ADAPTER_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/uart/usart_adapter.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/uart/usart_adapter.c deleted file mode 100644 index a53fa0e32..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/component/uart/usart_adapter.c +++ /dev/null @@ -1,629 +0,0 @@ -/* - * Copyright 2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_usart.h" -#include "fsl_flexcomm.h" - -#include "uart.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#ifndef NDEBUG -#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) -#undef assert -#define assert(n) -#endif -#endif - -#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) -/*! @brief uart RX state structure. */ -typedef struct _hal_uart_receive_state -{ - volatile uint8_t *buffer; - volatile uint32_t bufferLength; - volatile uint32_t bufferSofar; -} hal_uart_receive_state_t; - -/*! @brief uart TX state structure. */ -typedef struct _hal_uart_send_state -{ - volatile uint8_t *buffer; - volatile uint32_t bufferLength; - volatile uint32_t bufferSofar; -} hal_uart_send_state_t; -#endif -/*! @brief uart state structure. */ -typedef struct _hal_uart_state -{ -#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) - hal_uart_transfer_callback_t callback; - void *callbackParam; -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - usart_handle_t hardwareHandle; -#endif - hal_uart_receive_state_t rx; - hal_uart_send_state_t tx; -#endif - uint8_t instance; -} hal_uart_state_t; - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ -static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS; - -#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) - -#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) -/* Array of USART IRQ number. */ -static const IRQn_Type s_UsartIRQ[] = USART_IRQS; -#endif - -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) -static hal_uart_status_t HAL_UartGetStatus(status_t status) -{ - hal_uart_status_t uartStatus = kStatus_HAL_UartError; - switch (status) - { - case kStatus_Success: - uartStatus = kStatus_HAL_UartSuccess; - break; - case kStatus_USART_TxBusy: - uartStatus = kStatus_HAL_UartTxBusy; - break; - case kStatus_USART_RxBusy: - uartStatus = kStatus_HAL_UartRxBusy; - break; - case kStatus_USART_TxIdle: - uartStatus = kStatus_HAL_UartTxIdle; - break; - case kStatus_USART_RxIdle: - uartStatus = kStatus_HAL_UartRxIdle; - break; - case kStatus_USART_BaudrateNotSupport: - uartStatus = kStatus_HAL_UartBaudrateNotSupport; - break; - case kStatus_USART_NoiseError: - case kStatus_USART_FramingError: - case kStatus_USART_ParityError: - uartStatus = kStatus_HAL_UartProtocolError; - break; - default: - break; - } - return uartStatus; -} -#else -static hal_uart_status_t HAL_UartGetStatus(status_t status) -{ - if (kStatus_Success == status) - { - return kStatus_HAL_UartSuccess; - } - else - { - return kStatus_HAL_UartError; - } -} -#endif - -#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) - -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) -static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam) -{ - hal_uart_state_t *uartHandle; - hal_uart_status_t uartStatus = HAL_UartGetStatus(status); - assert(callbackParam); - - uartHandle = (hal_uart_state_t *)callbackParam; - - if (kStatus_HAL_UartProtocolError == uartStatus) - { - if (uartHandle->hardwareHandle.rxDataSize) - { - uartStatus = kStatus_HAL_UartError; - } - } - - if (uartHandle->callback) - { - uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam); - } -} - -#else - -static void HAL_UartInterruptHandle(USART_Type *base, void *handle) -{ - hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle; - uint32_t status; - uint8_t instance; - - if (NULL == uartHandle) - { - return; - } - instance = uartHandle->instance; - - status = USART_GetStatusFlags(s_UsartAdapterBase[instance]); - - /* Receive data register full */ - if ((USART_FIFOSTAT_RXNOTEMPTY_MASK & status) && - (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK)) - { - if (uartHandle->rx.buffer) - { - uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]); - if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength) - { - USART_DisableInterrupts(s_UsartAdapterBase[instance], - USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK); - uartHandle->rx.buffer = NULL; - if (uartHandle->callback) - { - uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam); - } - } - } - } - - /* Send data register empty and the interrupt is enabled. */ - if ((USART_FIFOSTAT_TXNOTFULL_MASK & status) && - (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK)) - { - if (uartHandle->tx.buffer) - { - USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]); - if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength) - { - USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK); - uartHandle->tx.buffer = NULL; - if (uartHandle->callback) - { - uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam); - } - } - } - } - -#if 1 - USART_ClearStatusFlags(s_UsartAdapterBase[instance], status); -#endif -} -#endif - -#endif - -hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config) -{ - hal_uart_state_t *uartHandle; - usart_config_t usartConfig; - status_t status; - assert(handle); - assert(config); - assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *))); - assert(s_UsartAdapterBase[config->instance]); - - if (HAL_UART_HANDLE_SIZE < sizeof(hal_uart_state_t)) - { - return kStatus_HAL_UartError; - } - - USART_GetDefaultConfig(&usartConfig); - usartConfig.baudRate_Bps = config->baudRate_Bps; - - if (kHAL_UartParityEven == config->parityMode) - { - usartConfig.parityMode = kUSART_ParityEven; - } - else if (kHAL_UartParityOdd == config->parityMode) - { - usartConfig.parityMode = kUSART_ParityOdd; - } - else - { - usartConfig.parityMode = kUSART_ParityDisabled; - } - - if (kHAL_UartTwoStopBit == config->stopBitCount) - { - usartConfig.stopBitCount = kUSART_TwoStopBit; - } - else - { - usartConfig.stopBitCount = kUSART_OneStopBit; - } - usartConfig.enableRx = config->enableRx; - usartConfig.enableTx = config->enableTx; - usartConfig.txWatermark = kUSART_TxFifo0; - usartConfig.rxWatermark = kUSART_RxFifo1; - - status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz); - - if (kStatus_Success != status) - { - return HAL_UartGetStatus(status); - } - - uartHandle = (hal_uart_state_t *)handle; - uartHandle->instance = config->instance; - -#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) - -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle, - (usart_transfer_callback_t)HAL_UartCallback, handle); -#else - /* Enable interrupt in NVIC. */ - FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], (flexcomm_irq_handler_t)HAL_UartInterruptHandle, - handle); - NVIC_SetPriority((IRQn_Type)s_UsartIRQ[config->instance], HAL_UART_ISR_PRIORITY); - EnableIRQ(s_UsartIRQ[config->instance]); -#endif - -#endif - - return kStatus_HAL_UartSuccess; -} - -hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle) -{ - hal_uart_state_t *uartHandle; - - assert(handle); - - uartHandle = (hal_uart_state_t *)handle; - - USART_Deinit(s_UsartAdapterBase[uartHandle->instance]); - - return kStatus_HAL_UartSuccess; -} - -hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) -{ - hal_uart_state_t *uartHandle; - status_t status; - assert(handle); - assert(data); - assert(length); - - uartHandle = (hal_uart_state_t *)handle; - -#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) - if (uartHandle->rx.buffer) - { - return kStatus_HAL_UartRxBusy; - } -#endif - - status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length); - - return HAL_UartGetStatus(status); -} - -hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length) -{ - hal_uart_state_t *uartHandle; - assert(handle); - assert(data); - assert(length); - - uartHandle = (hal_uart_state_t *)handle; - -#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) - if (uartHandle->tx.buffer) - { - return kStatus_HAL_UartTxBusy; - } -#endif - - USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length); - - return kStatus_HAL_UartSuccess; -} - -#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) - -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - -hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, - hal_uart_transfer_callback_t callback, - void *callbackParam) -{ - hal_uart_state_t *uartHandle; - - assert(handle); - assert(HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - uartHandle->callbackParam = callbackParam; - uartHandle->callback = callback; - - return kStatus_HAL_UartSuccess; -} - -hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) -{ - hal_uart_state_t *uartHandle; - status_t status; - assert(handle); - assert(transfer); - assert(HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, - (usart_transfer_t *)transfer, NULL); - - return HAL_UartGetStatus(status); -} - -hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) -{ - hal_uart_state_t *uartHandle; - status_t status; - assert(handle); - assert(transfer); - assert(HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, - (usart_transfer_t *)transfer); - - return HAL_UartGetStatus(status); -} - -hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count) -{ - hal_uart_state_t *uartHandle; - status_t status; - assert(handle); - assert(count); - assert(HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - status = - USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); - - return HAL_UartGetStatus(status); -} - -hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count) -{ - hal_uart_state_t *uartHandle; - status_t status; - assert(handle); - assert(count); - assert(HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); - - return HAL_UartGetStatus(status); -} - -hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle) -{ - hal_uart_state_t *uartHandle; - assert(handle); - assert(HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); - - return kStatus_HAL_UartSuccess; -} - -hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle) -{ - hal_uart_state_t *uartHandle; - assert(handle); - assert(HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); - - return kStatus_HAL_UartSuccess; -} - -#else - -/* None transactional API with non-blocking mode. */ -hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, - hal_uart_transfer_callback_t callback, - void *callbackParam) -{ - hal_uart_state_t *uartHandle; - - assert(handle); - assert(!HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - uartHandle->callbackParam = callbackParam; - uartHandle->callback = callback; - - return kStatus_HAL_UartSuccess; -} - -hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) -{ - hal_uart_state_t *uartHandle; - assert(handle); - assert(data); - assert(length); - assert(!HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - if (uartHandle->rx.buffer) - { - return kStatus_HAL_UartRxBusy; - } - - uartHandle->rx.bufferLength = length; - uartHandle->rx.bufferSofar = 0; - uartHandle->rx.buffer = data; - USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK); - return kStatus_HAL_UartSuccess; -} - -hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) -{ - hal_uart_state_t *uartHandle; - assert(handle); - assert(data); - assert(length); - assert(!HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - if (uartHandle->tx.buffer) - { - return kStatus_HAL_UartTxBusy; - } - uartHandle->tx.bufferLength = length; - uartHandle->tx.bufferSofar = 0; - uartHandle->tx.buffer = (volatile uint8_t *)data; - USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK); - return kStatus_HAL_UartSuccess; -} - -hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount) -{ - hal_uart_state_t *uartHandle; - assert(handle); - assert(reCount); - assert(!HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - if (uartHandle->rx.buffer) - { - *reCount = uartHandle->rx.bufferSofar; - return kStatus_HAL_UartSuccess; - } - return kStatus_HAL_UartError; -} - -hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount) -{ - hal_uart_state_t *uartHandle; - assert(handle); - assert(seCount); - assert(!HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - if (uartHandle->tx.buffer) - { - *seCount = uartHandle->tx.bufferSofar; - return kStatus_HAL_UartSuccess; - } - return kStatus_HAL_UartError; -} - -hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle) -{ - hal_uart_state_t *uartHandle; - assert(handle); - assert(!HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - if (uartHandle->rx.buffer) - { - USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], - USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK); - uartHandle->rx.buffer = NULL; - } - - return kStatus_HAL_UartSuccess; -} - -hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle) -{ - hal_uart_state_t *uartHandle; - assert(handle); - assert(!HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - - if (uartHandle->tx.buffer) - { - USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK); - uartHandle->tx.buffer = NULL; - } - - return kStatus_HAL_UartSuccess; -} - -#endif - -#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) - -void HAL_UartIsrFunction(hal_uart_handle_t handle) -{ - hal_uart_state_t *uartHandle; - assert(handle); - assert(HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - -#if 0 - DisableIRQ(s_UsartIRQ[uartHandle->instance]); -#endif - USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); -#if 0 - NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); - EnableIRQ(s_UsartIRQ[uartHandle->instance]); -#endif -} - -#else - -void HAL_UartIsrFunction(hal_uart_handle_t handle) -{ - hal_uart_state_t *uartHandle; - assert(handle); - assert(!HAL_UART_TRANSFER_MODE); - - uartHandle = (hal_uart_state_t *)handle; - -#if 0 - DisableIRQ(s_UsartIRQ[uartHandle->instance]); -#endif - HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle); -#if 0 - NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); - EnableIRQ(s_UsartIRQ[uartHandle->instance]); -#endif -} - -#endif - -#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/LPC51U68.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/LPC51U68.h deleted file mode 100644 index 6f4e969fb..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/LPC51U68.h +++ /dev/null @@ -1,8088 +0,0 @@ -/* -** ################################################################### -** Processors: LPC51U68JBD48 -** LPC51U68JBD64 -** -** Compilers: GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** Keil ARM C/C++ Compiler -** MCUXpresso Compiler -** -** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 -** Version: rev. 1.0, 2017-12-15 -** Build: b190114 -** -** Abstract: -** CMSIS Peripheral Access Layer for LPC51U68 -** -** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2017-12-15) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file LPC51U68.h - * @version 1.0 - * @date 2017-12-15 - * @brief CMSIS Peripheral Access Layer for LPC51U68 - * - * CMSIS Peripheral Access Layer for LPC51U68 - */ - -#ifndef _LPC51U68_H_ -#define _LPC51U68_H_ /**< Symbol preventing repeated inclusion */ - -/** Memory map major version (memory maps with equal major version number are - * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0100U -/** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U - - -/* ---------------------------------------------------------------------------- - -- Interrupt vector numbers - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Interrupt_vector_numbers Interrupt vector numbers - * @{ - */ - -/** Interrupt Number Definitions */ -#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ - -typedef enum IRQn { - /* Auxiliary constants */ - NotAvail_IRQn = -128, /**< Not available device specific interrupt */ - - /* Core interrupts */ - NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ - HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ - - /* Device specific interrupts */ - WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ - DMA0_IRQn = 1, /**< DMA controller */ - GINT0_IRQn = 2, /**< GPIO group 0 */ - GINT1_IRQn = 3, /**< GPIO group 1 */ - PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ - PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ - PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ - PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ - UTICK0_IRQn = 8, /**< Micro-tick Timer */ - MRT0_IRQn = 9, /**< Multi-rate timer */ - CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ - CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ - SCT0_IRQn = 12, /**< SCTimer/PWM */ - CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ - FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C) */ - FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C) */ - FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C) */ - FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C) */ - FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C) */ - FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C) */ - FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ - FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ - ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ - ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ - ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ - Reserved41_IRQn = 25, /**< Reserved interrupt */ - Reserved42_IRQn = 26, /**< Reserved interrupt */ - USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ - USB0_IRQn = 28, /**< USB device */ - RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ - Reserved46_IRQn = 30, /**< Reserved interrupt */ - Reserved47_IRQn = 31 /**< Reserved interrupt */ -} IRQn_Type; - -/*! - * @} - */ /* end of group Interrupt_vector_numbers */ - - -/* ---------------------------------------------------------------------------- - -- Cortex M0 Core Configuration - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration - * @{ - */ - -#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ -#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ -#define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ -#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ -#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ - -#include "core_cm0plus.h" /* Core Peripheral Access Layer */ -#include "system_LPC51U68.h" /* Device specific configuration file */ - -/*! - * @} - */ /* end of group Cortex_Core_Configuration */ - - -/* ---------------------------------------------------------------------------- - -- Mapping Information - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Mapping_Information Mapping Information - * @{ - */ - -/** Mapping Information */ -/*! - * @addtogroup dma_request - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! - * @brief Enumeration for the DMA hardware request - * - * Defines the enumeration for the DMA hardware request collections. - */ -typedef enum _dma_request_source -{ - kFlexcomm_Interface0_RX_I2C_Slave = 0U, /**< Flexcomm Interface 0 RX/I2C Slave */ - kFlexcomm_Interface0_TX_I2C_Master = 1U, /**< Flexcomm Interface 0 TX/I2C Master */ - kFlexcomm_Interface1_RX_I2C_Slave = 2U, /**< Flexcomm Interface 1 RX/I2C Slave */ - kFlexcomm_Interface1_TX_I2C_Master = 3U, /**< Flexcomm Interface 1 TX/I2C Master */ - kFlexcomm_Interface2_RX_I2C_Slave = 4U, /**< Flexcomm Interface 2 RX/I2C Slave */ - kFlexcomm_Interface2_TX_I2C_Master = 5U, /**< Flexcomm Interface 2 TX/I2C Master */ - kFlexcomm_Interface3_RX_I2C_Slave = 6U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kFlexcomm_Interface3_TX_I2C_Master = 7U, /**< Flexcomm Interface 3 TX/I2C Master */ - kFlexcomm_Interface4_RX_I2C_Slave = 8U, /**< Flexcomm Interface 4 RX/I2C Slave */ - kFlexcomm_Interface4_TX_I2C_Master = 9U, /**< Flexcomm Interface 4 TX/I2C Master */ - kFlexcomm_Interface5_RX_I2C_Slave = 10U, /**< Flexcomm Interface 5 RX/I2C Slave */ - kFlexcomm_Interface5_TX_I2C_Master = 11U, /**< Flexcomm Interface 5 TX/I2C Master */ - kFlexcomm_Interface6_RX_I2C_Slave = 12U, /**< Flexcomm Interface 6 RX/I2C Slave */ - kFlexcomm_Interface6_TX_I2C_Master = 13U, /**< Flexcomm Interface 6 TX/I2C Master */ - kFlexcomm_Interface7_RX_I2C_Slave = 14U, /**< Flexcomm Interface 7 RX/I2C Slave */ - kFlexcomm_Interface7_TX_I2C_Master = 15U, /**< Flexcomm Interface 7 TX/I2C Master */ - kDmaRequestNoDMARequest18 = 18U, /**< No DMA request 18 */ - kDmaRequestNoDMARequest19 = 19U, /**< No DMA request 19 */ -} dma_request_source_t; - -/* @} */ - - -/*! - * @} - */ /* end of group Mapping_Information */ - - -/* ---------------------------------------------------------------------------- - -- Device Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Peripheral_access_layer Device Peripheral Access Layer - * @{ - */ - - -/* -** Start of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #else - #pragma push - #pragma anon_unions - #endif -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=extended -#else - #error Not supported compiler type -#endif - -/* ---------------------------------------------------------------------------- - -- ADC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer - * @{ - */ - -/** ADC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ - __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ - __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ - __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ - uint8_t RESERVED_0[8]; - __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ - __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ - __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ - __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ - __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ - __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ - __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ - __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ - __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ - __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ -} ADC_Type; - -/* ---------------------------------------------------------------------------- - -- ADC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ADC_Register_Masks ADC Register Masks - * @{ - */ - -/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ -/*! @{ */ -#define ADC_CTRL_CLKDIV_MASK (0xFFU) -#define ADC_CTRL_CLKDIV_SHIFT (0U) -#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) -#define ADC_CTRL_ASYNMODE_MASK (0x100U) -#define ADC_CTRL_ASYNMODE_SHIFT (8U) -/*! ASYNMODE - Select clock mode. - * 0b0..Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse. - * 0b1..Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block. - */ -#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) -#define ADC_CTRL_RESOL_MASK (0x600U) -#define ADC_CTRL_RESOL_SHIFT (9U) -/*! RESOL - The number of bits of ADC resolution. Accuracy can be reduced to achieve higher conversion rates. A single conversion (including one conversion in a burst or sequence) requires the selected number of bits of resolution plus 3 ADC clocks. This field must only be altered when the ADC is fully idle. Changing it during any kind of ADC operation may have unpredictable results. ADC clock frequencies for various resolutions must not exceed: - 5x the system clock rate for 12-bit resolution - 4.3x the system clock rate for 10-bit resolution - 3.6x the system clock for 8-bit resolution - 3x the bus clock rate for 6-bit resolution - * 0b00..6-bit resolution. An ADC conversion requires 9 ADC clocks, plus any clocks specified by the TSAMP field. - * 0b01..8-bit resolution. An ADC conversion requires 11 ADC clocks, plus any clocks specified by the TSAMP field. - * 0b10..10-bit resolution. An ADC conversion requires 13 ADC clocks, plus any clocks specified by the TSAMP field. - * 0b11..12-bit resolution. An ADC conversion requires 15 ADC clocks, plus any clocks specified by the TSAMP field. - */ -#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) -#define ADC_CTRL_BYPASSCAL_MASK (0x800U) -#define ADC_CTRL_BYPASSCAL_SHIFT (11U) -/*! BYPASSCAL - Bypass Calibration. This bit may be set to avoid the need to calibrate if offset error is not a concern in the application. - * 0b0..Calibrate. The stored calibration value will be applied to the ADC during conversions to compensated for offset error. A calibration cycle must be performed each time the chip is powered-up. Re-calibration may be warranted periodically - especially if operating conditions have changed. - * 0b1..Bypass calibration. Calibration is not utilized. Less time is required when enabling the ADC - particularly following chip power-up. Attempts to launch a calibration cycle are blocked when this bit is set. - */ -#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) -#define ADC_CTRL_TSAMP_MASK (0x7000U) -#define ADC_CTRL_TSAMP_SHIFT (12U) -#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) -/*! @} */ - -/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ -/*! @{ */ -#define ADC_INSEL_SEL_MASK (0x3U) -#define ADC_INSEL_SEL_SHIFT (0U) -/*! SEL - Selects the input source for channel 0. All other values are reserved. - * 0b00..ADC0_IN0 function. - * 0b11..Internal temperature sensor. - */ -#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) -/*! @} */ - -/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ -/*! @{ */ -#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) -#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) -#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) -#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) -#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) -#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) -#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) -#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) -/*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. - * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input. - * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input. - */ -#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) -#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) -#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) -/*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period. - * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled. - * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled. - */ -#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) -#define ADC_SEQ_CTRL_START_MASK (0x4000000U) -#define ADC_SEQ_CTRL_START_SHIFT (26U) -#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) -#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) -#define ADC_SEQ_CTRL_BURST_SHIFT (27U) -#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) -#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) -#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) -#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) -#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) -#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) -/*! LOWPRIO - Set priority for sequence A. - * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. - * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion currently in progress will be terminated. The A sequence that was interrupted will automatically resume after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the conversion sequence will resume from that point. - */ -#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) -#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) -#define ADC_SEQ_CTRL_MODE_SHIFT (30U) -/*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below. - * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger if enabled. - * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun interrupt/DMA trigger since it is assumed this register may not be utilized in this mode. - */ -#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) -#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) -#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) -/*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. - * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. - * 0b1..Enabled. Sequence n is enabled. - */ -#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) -/*! @} */ - -/* The count of ADC_SEQ_CTRL */ -#define ADC_SEQ_CTRL_COUNT (2U) - -/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ -/*! @{ */ -#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) -#define ADC_SEQ_GDAT_RESULT_SHIFT (4U) -#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) -#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) -#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) -#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) -#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) -#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) -#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) -#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) -#define ADC_SEQ_GDAT_CHN_SHIFT (26U) -#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) -#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) -#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) -#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) -#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) -#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) -#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) -/*! @} */ - -/* The count of ADC_SEQ_GDAT */ -#define ADC_SEQ_GDAT_COUNT (2U) - -/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ -/*! @{ */ -#define ADC_DAT_RESULT_MASK (0xFFF0U) -#define ADC_DAT_RESULT_SHIFT (4U) -#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) -#define ADC_DAT_THCMPRANGE_MASK (0x30000U) -#define ADC_DAT_THCMPRANGE_SHIFT (16U) -#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) -#define ADC_DAT_THCMPCROSS_MASK (0xC0000U) -#define ADC_DAT_THCMPCROSS_SHIFT (18U) -#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) -#define ADC_DAT_CHANNEL_MASK (0x3C000000U) -#define ADC_DAT_CHANNEL_SHIFT (26U) -#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) -#define ADC_DAT_OVERRUN_MASK (0x40000000U) -#define ADC_DAT_OVERRUN_SHIFT (30U) -#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) -#define ADC_DAT_DATAVALID_MASK (0x80000000U) -#define ADC_DAT_DATAVALID_SHIFT (31U) -#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) -/*! @} */ - -/* The count of ADC_DAT */ -#define ADC_DAT_COUNT (12U) - -/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ -/*! @{ */ -#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) -#define ADC_THR0_LOW_THRLOW_SHIFT (4U) -#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) -/*! @} */ - -/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ -/*! @{ */ -#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) -#define ADC_THR1_LOW_THRLOW_SHIFT (4U) -#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) -/*! @} */ - -/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ -/*! @{ */ -#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) -#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) -#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) -/*! @} */ - -/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ -/*! @{ */ -#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) -#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) -#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) -/*! @} */ - -/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ -/*! @{ */ -#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) -#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) -/*! CH0_THRSEL - Threshold select for channel 0. - * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers. - * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers. - */ -#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) -#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) -#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) -#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) -#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) -#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) -#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) -#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) -#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) -#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) -#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) -#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) -#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) -#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) -#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) -#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) -#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) -#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) -#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) -#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) -#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) -#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) -#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) -#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) -/*! @} */ - -/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ -/*! @{ */ -#define ADC_INTEN_SEQA_INTEN_MASK (0x1U) -#define ADC_INTEN_SEQA_INTEN_SHIFT (0U) -/*! SEQA_INTEN - Sequence A interrupt enable. - * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled. - * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of conversions, depending on the MODE bit in the SEQA_CTRL register. - */ -#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) -#define ADC_INTEN_SEQB_INTEN_MASK (0x2U) -#define ADC_INTEN_SEQB_INTEN_SHIFT (1U) -/*! SEQB_INTEN - Sequence B interrupt enable. - * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled. - * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of conversions, depending on the MODE bit in the SEQB_CTRL register. - */ -#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) -#define ADC_INTEN_OVR_INTEN_MASK (0x4U) -#define ADC_INTEN_OVR_INTEN_SHIFT (2U) -/*! OVR_INTEN - Overrun interrupt enable. - * 0b0..Disabled. The overrun interrupt is disabled. - * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular sequence is 0, then an overrun in the global data register for that sequence will also cause this interrupt/DMA trigger to be asserted. - */ -#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) -#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) -#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) -/*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0. - * 0b00..Disabled. - * 0b01..Outside threshold. - * 0b10..Crossing threshold. - * 0b11..Reserved - */ -#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) -#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) -#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) -#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) -#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) -#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) -#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) -#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) -#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) -#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) -#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) -#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) -#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) -#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) -#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) -#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) -#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) -#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) -#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) -#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) -#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) -#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) -#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) -#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) -#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) -#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) -#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) -#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) -#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) -#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) -#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) -#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) -#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) -#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) -/*! @} */ - -/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ -/*! @{ */ -#define ADC_FLAGS_THCMP0_MASK (0x1U) -#define ADC_FLAGS_THCMP0_SHIFT (0U) -#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) -#define ADC_FLAGS_THCMP1_MASK (0x2U) -#define ADC_FLAGS_THCMP1_SHIFT (1U) -#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) -#define ADC_FLAGS_THCMP2_MASK (0x4U) -#define ADC_FLAGS_THCMP2_SHIFT (2U) -#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) -#define ADC_FLAGS_THCMP3_MASK (0x8U) -#define ADC_FLAGS_THCMP3_SHIFT (3U) -#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) -#define ADC_FLAGS_THCMP4_MASK (0x10U) -#define ADC_FLAGS_THCMP4_SHIFT (4U) -#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) -#define ADC_FLAGS_THCMP5_MASK (0x20U) -#define ADC_FLAGS_THCMP5_SHIFT (5U) -#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) -#define ADC_FLAGS_THCMP6_MASK (0x40U) -#define ADC_FLAGS_THCMP6_SHIFT (6U) -#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) -#define ADC_FLAGS_THCMP7_MASK (0x80U) -#define ADC_FLAGS_THCMP7_SHIFT (7U) -#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) -#define ADC_FLAGS_THCMP8_MASK (0x100U) -#define ADC_FLAGS_THCMP8_SHIFT (8U) -#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) -#define ADC_FLAGS_THCMP9_MASK (0x200U) -#define ADC_FLAGS_THCMP9_SHIFT (9U) -#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) -#define ADC_FLAGS_THCMP10_MASK (0x400U) -#define ADC_FLAGS_THCMP10_SHIFT (10U) -#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) -#define ADC_FLAGS_THCMP11_MASK (0x800U) -#define ADC_FLAGS_THCMP11_SHIFT (11U) -#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) -#define ADC_FLAGS_OVERRUN0_MASK (0x1000U) -#define ADC_FLAGS_OVERRUN0_SHIFT (12U) -#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) -#define ADC_FLAGS_OVERRUN1_MASK (0x2000U) -#define ADC_FLAGS_OVERRUN1_SHIFT (13U) -#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) -#define ADC_FLAGS_OVERRUN2_MASK (0x4000U) -#define ADC_FLAGS_OVERRUN2_SHIFT (14U) -#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) -#define ADC_FLAGS_OVERRUN3_MASK (0x8000U) -#define ADC_FLAGS_OVERRUN3_SHIFT (15U) -#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) -#define ADC_FLAGS_OVERRUN4_MASK (0x10000U) -#define ADC_FLAGS_OVERRUN4_SHIFT (16U) -#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) -#define ADC_FLAGS_OVERRUN5_MASK (0x20000U) -#define ADC_FLAGS_OVERRUN5_SHIFT (17U) -#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) -#define ADC_FLAGS_OVERRUN6_MASK (0x40000U) -#define ADC_FLAGS_OVERRUN6_SHIFT (18U) -#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) -#define ADC_FLAGS_OVERRUN7_MASK (0x80000U) -#define ADC_FLAGS_OVERRUN7_SHIFT (19U) -#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) -#define ADC_FLAGS_OVERRUN8_MASK (0x100000U) -#define ADC_FLAGS_OVERRUN8_SHIFT (20U) -#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) -#define ADC_FLAGS_OVERRUN9_MASK (0x200000U) -#define ADC_FLAGS_OVERRUN9_SHIFT (21U) -#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) -#define ADC_FLAGS_OVERRUN10_MASK (0x400000U) -#define ADC_FLAGS_OVERRUN10_SHIFT (22U) -#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) -#define ADC_FLAGS_OVERRUN11_MASK (0x800000U) -#define ADC_FLAGS_OVERRUN11_SHIFT (23U) -#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) -#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) -#define ADC_FLAGS_SEQA_OVR_SHIFT (24U) -#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) -#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) -#define ADC_FLAGS_SEQB_OVR_SHIFT (25U) -#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) -#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) -#define ADC_FLAGS_SEQA_INT_SHIFT (28U) -#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) -#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) -#define ADC_FLAGS_SEQB_INT_SHIFT (29U) -#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) -#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) -#define ADC_FLAGS_THCMP_INT_SHIFT (30U) -#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) -#define ADC_FLAGS_OVR_INT_MASK (0x80000000U) -#define ADC_FLAGS_OVR_INT_SHIFT (31U) -#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) -/*! @} */ - -/*! @name STARTUP - ADC Startup register. */ -/*! @{ */ -#define ADC_STARTUP_ADC_ENA_MASK (0x1U) -#define ADC_STARTUP_ADC_ENA_SHIFT (0U) -#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) -#define ADC_STARTUP_ADC_INIT_MASK (0x2U) -#define ADC_STARTUP_ADC_INIT_SHIFT (1U) -#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) -/*! @} */ - -/*! @name CALIB - ADC Calibration register. */ -/*! @{ */ -#define ADC_CALIB_CALIB_MASK (0x1U) -#define ADC_CALIB_CALIB_SHIFT (0U) -#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) -#define ADC_CALIB_CALREQD_MASK (0x2U) -#define ADC_CALIB_CALREQD_SHIFT (1U) -#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) -#define ADC_CALIB_CALVALUE_MASK (0x1FCU) -#define ADC_CALIB_CALVALUE_SHIFT (2U) -#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ADC_Register_Masks */ - - -/* ADC - Peripheral instance base addresses */ -/** Peripheral ADC0 base address */ -#define ADC0_BASE (0x400A0000u) -/** Peripheral ADC0 base pointer */ -#define ADC0 ((ADC_Type *)ADC0_BASE) -/** Array initializer of ADC peripheral base addresses */ -#define ADC_BASE_ADDRS { ADC0_BASE } -/** Array initializer of ADC peripheral base pointers */ -#define ADC_BASE_PTRS { ADC0 } -/** Interrupt vectors for the ADC peripheral type */ -#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } -#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } - -/*! - * @} - */ /* end of group ADC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ASYNC_SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer - * @{ - */ - -/** ASYNC_SYSCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ - __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ - __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ - __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ - __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ - uint8_t RESERVED_1[4]; - __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ -} ASYNC_SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- ASYNC_SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks - * @{ - */ - -/*! @name ASYNCPRESETCTRL - Async peripheral reset control */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) -#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) -/*! @} */ - -/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) -/*! @} */ - -/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) -#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) -/*! @} */ - -/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ -/*! @{ */ -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) -/*! SEL - Clock source for asynchronous clock source selector A - * 0b00..Main clock - * 0b01..FRO 12 MHz - * 0b10..Reserved setting - * 0b11..Reserved setting - */ -#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ASYNC_SYSCON_Register_Masks */ - - -/* ASYNC_SYSCON - Peripheral instance base addresses */ -/** Peripheral ASYNC_SYSCON base address */ -#define ASYNC_SYSCON_BASE (0x40040000u) -/** Peripheral ASYNC_SYSCON base pointer */ -#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) -/** Array initializer of ASYNC_SYSCON peripheral base addresses */ -#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } -/** Array initializer of ASYNC_SYSCON peripheral base pointers */ -#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } - -/*! - * @} - */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CRC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer - * @{ - */ - -/** CRC - Register Layout Typedef */ -typedef struct { - __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ - __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ - union { /* offset: 0x8 */ - __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ - __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ - }; -} CRC_Type; - -/* ---------------------------------------------------------------------------- - -- CRC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CRC_Register_Masks CRC Register Masks - * @{ - */ - -/*! @name MODE - CRC mode register */ -/*! @{ */ -#define CRC_MODE_CRC_POLY_MASK (0x3U) -#define CRC_MODE_CRC_POLY_SHIFT (0U) -#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) -#define CRC_MODE_BIT_RVS_WR_MASK (0x4U) -#define CRC_MODE_BIT_RVS_WR_SHIFT (2U) -#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) -#define CRC_MODE_CMPL_WR_MASK (0x8U) -#define CRC_MODE_CMPL_WR_SHIFT (3U) -#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) -#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) -#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) -#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) -#define CRC_MODE_CMPL_SUM_MASK (0x20U) -#define CRC_MODE_CMPL_SUM_SHIFT (5U) -#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) -/*! @} */ - -/*! @name SEED - CRC seed register */ -/*! @{ */ -#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) -#define CRC_SEED_CRC_SEED_SHIFT (0U) -#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) -/*! @} */ - -/*! @name SUM - CRC checksum register */ -/*! @{ */ -#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) -#define CRC_SUM_CRC_SUM_SHIFT (0U) -#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) -/*! @} */ - -/*! @name WR_DATA - CRC data register */ -/*! @{ */ -#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) -#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) -#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CRC_Register_Masks */ - - -/* CRC - Peripheral instance base addresses */ -/** Peripheral CRC_ENGINE base address */ -#define CRC_ENGINE_BASE (0x40095000u) -/** Peripheral CRC_ENGINE base pointer */ -#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) -/** Array initializer of CRC peripheral base addresses */ -#define CRC_BASE_ADDRS { CRC_ENGINE_BASE } -/** Array initializer of CRC peripheral base pointers */ -#define CRC_BASE_PTRS { CRC_ENGINE } - -/*! - * @} - */ /* end of group CRC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- CTIMER Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer - * @{ - */ - -/** CTIMER - Register Layout Typedef */ -typedef struct { - __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ - __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ - __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */ - __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */ - __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */ - __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */ - __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ - __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ - __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ - __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ - uint8_t RESERVED_0[48]; - __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ - __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ -} CTIMER_Type; - -/* ---------------------------------------------------------------------------- - -- CTIMER Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CTIMER_Register_Masks CTIMER Register Masks - * @{ - */ - -/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ -/*! @{ */ -#define CTIMER_IR_MR0INT_MASK (0x1U) -#define CTIMER_IR_MR0INT_SHIFT (0U) -#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) -#define CTIMER_IR_MR1INT_MASK (0x2U) -#define CTIMER_IR_MR1INT_SHIFT (1U) -#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) -#define CTIMER_IR_MR2INT_MASK (0x4U) -#define CTIMER_IR_MR2INT_SHIFT (2U) -#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) -#define CTIMER_IR_MR3INT_MASK (0x8U) -#define CTIMER_IR_MR3INT_SHIFT (3U) -#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) -#define CTIMER_IR_CR0INT_MASK (0x10U) -#define CTIMER_IR_CR0INT_SHIFT (4U) -#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) -#define CTIMER_IR_CR1INT_MASK (0x20U) -#define CTIMER_IR_CR1INT_SHIFT (5U) -#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) -#define CTIMER_IR_CR2INT_MASK (0x40U) -#define CTIMER_IR_CR2INT_SHIFT (6U) -#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) -#define CTIMER_IR_CR3INT_MASK (0x80U) -#define CTIMER_IR_CR3INT_SHIFT (7U) -#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) -/*! @} */ - -/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ -/*! @{ */ -#define CTIMER_TCR_CEN_MASK (0x1U) -#define CTIMER_TCR_CEN_SHIFT (0U) -/*! CEN - Counter enable. - * 0b0..Disabled.The counters are disabled. - * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. - */ -#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) -#define CTIMER_TCR_CRST_MASK (0x2U) -#define CTIMER_TCR_CRST_SHIFT (1U) -/*! CRST - Counter reset. - * 0b0..Disabled. Do nothing. - * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero. - */ -#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) -/*! @} */ - -/*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ -/*! @{ */ -#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_TC_TCVAL_SHIFT (0U) -#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) -/*! @} */ - -/*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ -/*! @{ */ -#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PR_PRVAL_SHIFT (0U) -#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) -/*! @} */ - -/*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ -/*! @{ */ -#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) -#define CTIMER_PC_PCVAL_SHIFT (0U) -#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) -/*! @} */ - -/*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ -/*! @{ */ -#define CTIMER_MCR_MR0I_MASK (0x1U) -#define CTIMER_MCR_MR0I_SHIFT (0U) -#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) -#define CTIMER_MCR_MR0R_MASK (0x2U) -#define CTIMER_MCR_MR0R_SHIFT (1U) -#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) -#define CTIMER_MCR_MR0S_MASK (0x4U) -#define CTIMER_MCR_MR0S_SHIFT (2U) -#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) -#define CTIMER_MCR_MR1I_MASK (0x8U) -#define CTIMER_MCR_MR1I_SHIFT (3U) -#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) -#define CTIMER_MCR_MR1R_MASK (0x10U) -#define CTIMER_MCR_MR1R_SHIFT (4U) -#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) -#define CTIMER_MCR_MR1S_MASK (0x20U) -#define CTIMER_MCR_MR1S_SHIFT (5U) -#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) -#define CTIMER_MCR_MR2I_MASK (0x40U) -#define CTIMER_MCR_MR2I_SHIFT (6U) -#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) -#define CTIMER_MCR_MR2R_MASK (0x80U) -#define CTIMER_MCR_MR2R_SHIFT (7U) -#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) -#define CTIMER_MCR_MR2S_MASK (0x100U) -#define CTIMER_MCR_MR2S_SHIFT (8U) -#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) -#define CTIMER_MCR_MR3I_MASK (0x200U) -#define CTIMER_MCR_MR3I_SHIFT (9U) -#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) -#define CTIMER_MCR_MR3R_MASK (0x400U) -#define CTIMER_MCR_MR3R_SHIFT (10U) -#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) -#define CTIMER_MCR_MR3S_MASK (0x800U) -#define CTIMER_MCR_MR3S_SHIFT (11U) -#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) -/*! @} */ - -/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ -/*! @{ */ -#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) -#define CTIMER_MR_MATCH_SHIFT (0U) -#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) -/*! @} */ - -/* The count of CTIMER_MR */ -#define CTIMER_MR_COUNT (4U) - -/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ -/*! @{ */ -#define CTIMER_CCR_CAP0RE_MASK (0x1U) -#define CTIMER_CCR_CAP0RE_SHIFT (0U) -#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) -#define CTIMER_CCR_CAP0FE_MASK (0x2U) -#define CTIMER_CCR_CAP0FE_SHIFT (1U) -#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) -#define CTIMER_CCR_CAP0I_MASK (0x4U) -#define CTIMER_CCR_CAP0I_SHIFT (2U) -#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) -#define CTIMER_CCR_CAP1RE_MASK (0x8U) -#define CTIMER_CCR_CAP1RE_SHIFT (3U) -#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) -#define CTIMER_CCR_CAP1FE_MASK (0x10U) -#define CTIMER_CCR_CAP1FE_SHIFT (4U) -#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) -#define CTIMER_CCR_CAP1I_MASK (0x20U) -#define CTIMER_CCR_CAP1I_SHIFT (5U) -#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) -#define CTIMER_CCR_CAP2RE_MASK (0x40U) -#define CTIMER_CCR_CAP2RE_SHIFT (6U) -#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) -#define CTIMER_CCR_CAP2FE_MASK (0x80U) -#define CTIMER_CCR_CAP2FE_SHIFT (7U) -#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) -#define CTIMER_CCR_CAP2I_MASK (0x100U) -#define CTIMER_CCR_CAP2I_SHIFT (8U) -#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) -#define CTIMER_CCR_CAP3RE_MASK (0x200U) -#define CTIMER_CCR_CAP3RE_SHIFT (9U) -#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) -#define CTIMER_CCR_CAP3FE_MASK (0x400U) -#define CTIMER_CCR_CAP3FE_SHIFT (10U) -#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) -#define CTIMER_CCR_CAP3I_MASK (0x800U) -#define CTIMER_CCR_CAP3I_SHIFT (11U) -#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) -/*! @} */ - -/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ -/*! @{ */ -#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) -#define CTIMER_CR_CAP_SHIFT (0U) -#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) -/*! @} */ - -/* The count of CTIMER_CR */ -#define CTIMER_CR_COUNT (4U) - -/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ -/*! @{ */ -#define CTIMER_EMR_EM0_MASK (0x1U) -#define CTIMER_EMR_EM0_SHIFT (0U) -#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) -#define CTIMER_EMR_EM1_MASK (0x2U) -#define CTIMER_EMR_EM1_SHIFT (1U) -#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) -#define CTIMER_EMR_EM2_MASK (0x4U) -#define CTIMER_EMR_EM2_SHIFT (2U) -#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) -#define CTIMER_EMR_EM3_MASK (0x8U) -#define CTIMER_EMR_EM3_SHIFT (3U) -#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) -#define CTIMER_EMR_EMC0_MASK (0x30U) -#define CTIMER_EMR_EMC0_SHIFT (4U) -/*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) -#define CTIMER_EMR_EMC1_MASK (0xC0U) -#define CTIMER_EMR_EMC1_SHIFT (6U) -/*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) -#define CTIMER_EMR_EMC2_MASK (0x300U) -#define CTIMER_EMR_EMC2_SHIFT (8U) -/*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) -#define CTIMER_EMR_EMC3_MASK (0xC00U) -#define CTIMER_EMR_EMC3_SHIFT (10U) -/*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. - * 0b00..Do Nothing. - * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). - * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). - * 0b11..Toggle. Toggle the corresponding External Match bit/output. - */ -#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) -/*! @} */ - -/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ -/*! @{ */ -#define CTIMER_CTCR_CTMODE_MASK (0x3U) -#define CTIMER_CTCR_CTMODE_SHIFT (0U) -/*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. - * 0b00..Timer Mode. Incremented every rising APB bus clock edge. - * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. - * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. - * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. - */ -#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) -#define CTIMER_CTCR_CINSEL_MASK (0xCU) -#define CTIMER_CTCR_CINSEL_SHIFT (2U) -/*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer. - * 0b00..Channel 0. CAPn.0 for CTIMERn - * 0b01..Channel 1. CAPn.1 for CTIMERn - * 0b10..Channel 2. CAPn.2 for CTIMERn - * 0b11..Channel 3. CAPn.3 for CTIMERn - */ -#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) -#define CTIMER_CTCR_ENCC_MASK (0x10U) -#define CTIMER_CTCR_ENCC_SHIFT (4U) -#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) -#define CTIMER_CTCR_SELCC_MASK (0xE0U) -#define CTIMER_CTCR_SELCC_SHIFT (5U) -/*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 0x3 and 0x6 to 0x7 are reserved. - * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). - * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). - * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). - */ -#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) -/*! @} */ - -/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ -/*! @{ */ -#define CTIMER_PWMC_PWMEN0_MASK (0x1U) -#define CTIMER_PWMC_PWMEN0_SHIFT (0U) -/*! PWMEN0 - PWM mode enable for channel0. - * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. - */ -#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) -#define CTIMER_PWMC_PWMEN1_MASK (0x2U) -#define CTIMER_PWMC_PWMEN1_SHIFT (1U) -/*! PWMEN1 - PWM mode enable for channel1. - * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. - */ -#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) -#define CTIMER_PWMC_PWMEN2_MASK (0x4U) -#define CTIMER_PWMC_PWMEN2_SHIFT (2U) -/*! PWMEN2 - PWM mode enable for channel2. - * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. - * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. - */ -#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) -#define CTIMER_PWMC_PWMEN3_MASK (0x8U) -#define CTIMER_PWMC_PWMEN3_SHIFT (3U) -/*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. - * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. - * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. - */ -#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group CTIMER_Register_Masks */ - - -/* CTIMER - Peripheral instance base addresses */ -/** Peripheral CTIMER0 base address */ -#define CTIMER0_BASE (0x40008000u) -/** Peripheral CTIMER0 base pointer */ -#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) -/** Peripheral CTIMER1 base address */ -#define CTIMER1_BASE (0x40009000u) -/** Peripheral CTIMER1 base pointer */ -#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) -/** Peripheral CTIMER3 base address */ -#define CTIMER3_BASE (0x40048000u) -/** Peripheral CTIMER3 base pointer */ -#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) -/** Array initializer of CTIMER peripheral base addresses */ -#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER3_BASE } -/** Array initializer of CTIMER peripheral base pointers */ -#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER3 } -/** Interrupt vectors for the CTIMER peripheral type */ -#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER3_IRQn } - -/*! - * @} - */ /* end of group CTIMER_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer - * @{ - */ - -/** DMA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ - __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ - __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ - uint8_t RESERVED_0[20]; - struct { /* offset: 0x20, array step: 0x5C */ - __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ - uint8_t RESERVED_0[4]; - __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ - uint8_t RESERVED_1[4]; - __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ - uint8_t RESERVED_2[4]; - __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ - uint8_t RESERVED_4[4]; - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ - uint8_t RESERVED_5[4]; - __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ - uint8_t RESERVED_6[4]; - __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ - uint8_t RESERVED_7[4]; - __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ - uint8_t RESERVED_8[4]; - __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ - uint8_t RESERVED_9[4]; - __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ - uint8_t RESERVED_10[4]; - __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ - } COMMON[1]; - uint8_t RESERVED_1[900]; - struct { /* offset: 0x400, array step: 0x10 */ - __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ - __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ - __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ - uint8_t RESERVED_0[4]; - } CHANNEL[20]; -} DMA_Type; - -/* ---------------------------------------------------------------------------- - -- DMA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup DMA_Register_Masks DMA Register Masks - * @{ - */ - -/*! @name CTRL - DMA control. */ -/*! @{ */ -#define DMA_CTRL_ENABLE_MASK (0x1U) -#define DMA_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - DMA controller master enable. - * 0b0..Disabled. The DMA controller is disabled. This clears any triggers that were asserted at the point when disabled, but does not prevent re-triggering when the DMA controller is re-enabled. - * 0b1..Enabled. The DMA controller is enabled. - */ -#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status. */ -/*! @{ */ -#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) -#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) -/*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. - * 0b0..Not pending. No enabled interrupts are pending. - * 0b1..Pending. At least one enabled interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) -#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) -#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) -/*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. - * 0b0..Not pending. No error interrupts are pending. - * 0b1..Pending. At least one error interrupt is pending. - */ -#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) -/*! @} */ - -/*! @name SRAMBASE - SRAM address of the channel configuration table. */ -/*! @{ */ -#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) -#define DMA_SRAMBASE_OFFSET_SHIFT (9U) -#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) -/*! @} */ - -/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) -#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLESET */ -#define DMA_COMMON_ENABLESET_COUNT (1U) - -/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) -#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ENABLECLR */ -#define DMA_COMMON_ENABLECLR_COUNT (1U) - -/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) -#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ACTIVE */ -#define DMA_COMMON_ACTIVE_COUNT (1U) - -/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) -#define DMA_COMMON_BUSY_BSY_SHIFT (0U) -#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) -/*! @} */ - -/* The count of DMA_COMMON_BUSY */ -#define DMA_COMMON_BUSY_COUNT (1U) - -/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ERRINT_ERR_SHIFT (0U) -#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ERRINT */ -#define DMA_COMMON_ERRINT_COUNT (1U) - -/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) -#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENSET */ -#define DMA_COMMON_INTENSET_COUNT (1U) - -/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) -#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTENCLR */ -#define DMA_COMMON_INTENCLR_COUNT (1U) - -/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTA_IA_SHIFT (0U) -#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTA */ -#define DMA_COMMON_INTA_COUNT (1U) - -/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) -#define DMA_COMMON_INTB_IB_SHIFT (0U) -#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) -/*! @} */ - -/* The count of DMA_COMMON_INTB */ -#define DMA_COMMON_INTB_COUNT (1U) - -/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETVALID_SV_SHIFT (0U) -#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETVALID */ -#define DMA_COMMON_SETVALID_COUNT (1U) - -/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) -#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) -#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) -/*! @} */ - -/* The count of DMA_COMMON_SETTRIG */ -#define DMA_COMMON_SETTRIG_COUNT (1U) - -/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ -/*! @{ */ -#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) -#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) -#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) -/*! @} */ - -/* The count of DMA_COMMON_ABORT */ -#define DMA_COMMON_ABORT_COUNT (1U) - -/*! @name CHANNEL_CFG - Configuration register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) -#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) -/*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory move, any peripheral DMA request associated with that channel can be disabled to prevent any interaction between the peripheral and the DMA controller. - * 0b0..Disabled. Peripheral DMA requests are disabled. - * 0b1..Enabled. Peripheral DMA requests are enabled. - */ -#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) -#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) -#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) -/*! HWTRIGEN - Hardware Triggering Enable for this channel. - * 0b0..Disabled. Hardware triggering is not used. - * 0b1..Enabled. Use hardware triggering. - */ -#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) -#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) -#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) -/*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. - * 0b0..Active low - falling edge. Hardware trigger is active low or falling edge triggered, based on TRIGTYPE. - * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. - */ -#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) -#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) -#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) -/*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. - * 0b0..Edge. Hardware trigger is edge triggered. Transfers will be initiated and completed, as specified for a single trigger. - * 0b1..Level. Hardware trigger is level triggered. Note that when level triggering without burst (BURSTPOWER = 0) is selected, only hardware triggers should be used on that channel. Transfers continue as long as the trigger level is asserted. Once the trigger is de-asserted, the transfer will be paused until the trigger is, again, asserted. However, the transfer will not be paused until any remaining transfers within the current BURSTPOWER length are completed. - */ -#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) -#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) -#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) -/*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. - * 0b0..Single transfer. Hardware trigger causes a single transfer. - * 0b1..Burst transfer. When the trigger for this channel is set to edge triggered, a hardware trigger causes a burst transfer, as defined by BURSTPOWER. When the trigger for this channel is set to level triggered, a hardware trigger causes transfers to continue as long as the trigger is asserted, unless the transfer is complete. - */ -#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) -#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) -#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) -#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) -#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) -/*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is 'wrapped', meaning that the source address range for each burst will be the same. As an example, this could be used to read several sequential registers from a peripheral for each DMA burst, reading the same registers again for each burst. - * 0b0..Disabled. Source burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) -#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) -/*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is 'wrapped', meaning that the destination address range for each burst will be the same. As an example, this could be used to write several sequential registers to a peripheral for each DMA burst, writing the same registers again for each burst. - * 0b0..Disabled. Destination burst wrapping is not enabled for this DMA channel. - * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. - */ -#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) -#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) -#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) -#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (20U) - -/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) -/*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the corresponding bit in the related SETVALID register when CFGVALID = 1 for the same channel. - * 0b0..No effect. No effect on DMA operation. - * 0b1..Valid pending. - */ -#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) -#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) -#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) -/*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is cleared at the end of an entire transfer or upon reload when CLRTRIG = 1. - * 0b0..Not triggered. The trigger for this DMA channel is not set. DMA operations will not be carried out. - * 0b1..Triggered. The trigger for this DMA channel is set. DMA operations will be carried out. - */ -#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (20U) - -/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ -/*! @{ */ -#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) -#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) -/*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled. - * 0b0..Not valid. The channel descriptor is not considered valid until validated by an associated SETVALID0 setting. - * 0b1..Valid. The current channel descriptor is considered valid. - */ -#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) -#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) -#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) -/*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers. - * 0b0..Disabled. Do not reload the channels' control structure when the current descriptor is exhausted. - * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) -#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) -#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) -/*! SWTRIG - Software Trigger. - * 0b0..Not set. When written by software, the trigger for this channel is not set. A new trigger, as defined by the HWTRIGEN, TRIGPOL, and TRIGTYPE will be needed to start the channel. - * 0b1..Set. When written by software, the trigger for this channel is set immediately. This feature should not be used with level triggering when TRIGBURST = 0. - */ -#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) -#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) -/*! CLRTRIG - Clear Trigger. - * 0b0..Not cleared. The trigger is not cleared when this descriptor is exhausted. If there is a reload, the next descriptor will be started. - * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted - */ -#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) -#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) -/*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) -#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) -#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) -/*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed. - * 0b0..No effect. - * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. - */ -#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) -#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) -#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) -/*! WIDTH - Transfer width used for this DMA channel. - * 0b00..8-bit. 8-bit transfers are performed (8-bit source reads and destination writes). - * 0b01..16-bit. 6-bit transfers are performed (16-bit source reads and destination writes). - * 0b10..32-bit. 32-bit transfers are performed (32-bit source reads and destination writes). - * 0b11..Reserved. Reserved setting, do not use. - */ -#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) -#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) -#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) -/*! SRCINC - Determines whether the source address is incremented for each DMA transfer. - * 0b00..No increment. The source address is not incremented for each transfer. This is the usual case when the source is a peripheral device. - * 0b01..1 x width. The source address is incremented by the amount specified by Width for each transfer. This is the usual case when the source is memory. - * 0b10..2 x width. The source address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) -#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) -#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) -/*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. - * 0b00..No increment. The destination address is not incremented for each transfer. This is the usual case when the destination is a peripheral device. - * 0b01..1 x width. The destination address is incremented by the amount specified by Width for each transfer. This is the usual case when the destination is memory. - * 0b10..2 x width. The destination address is incremented by 2 times the amount specified by Width for each transfer. - * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. - */ -#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) -#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) -/*! @} */ - -/* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (20U) - - -/*! - * @} - */ /* end of group DMA_Register_Masks */ - - -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA0 base address */ -#define DMA0_BASE (0x40082000u) -/** Peripheral DMA0 base pointer */ -#define DMA0 ((DMA_Type *)DMA0_BASE) -/** Array initializer of DMA peripheral base addresses */ -#define DMA_BASE_ADDRS { DMA0_BASE } -/** Array initializer of DMA peripheral base pointers */ -#define DMA_BASE_PTRS { DMA0 } -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_IRQS { DMA0_IRQn } - -/*! - * @} - */ /* end of group DMA_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer - * @{ - */ - -/** FLEXCOMM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[4088]; - __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ - __I uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ -} FLEXCOMM_Type; - -/* ---------------------------------------------------------------------------- - -- FLEXCOMM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks - * @{ - */ - -/*! @name PSELID - Peripheral Select and Flexcomm ID register. */ -/*! @{ */ -#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) -#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) -/*! PERSEL - Peripheral Select. This field is writable by software. - * 0b000..No peripheral selected. - * 0b001..USART function selected. - * 0b010..SPI function selected. - * 0b011..I2C function selected. - * 0b100..I2S transmit function selected. - * 0b101..I2S receive function selected. - * 0b110..Reserved - * 0b111..Reserved - */ -#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) -#define FLEXCOMM_PSELID_LOCK_MASK (0x8U) -#define FLEXCOMM_PSELID_LOCK_SHIFT (3U) -/*! LOCK - Lock the peripheral select. This field is writable by software. - * 0b0..Peripheral select can be changed by software. - * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. - */ -#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) -#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) -#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) -/*! USARTPRESENT - USART present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the USART function. - * 0b1..This Flexcomm includes the USART function. - */ -#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) -#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) -#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) -/*! SPIPRESENT - SPI present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the SPI function. - * 0b1..This Flexcomm includes the SPI function. - */ -#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) -#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) -#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) -/*! I2CPRESENT - I2C present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2C function. - * 0b1..This Flexcomm includes the I2C function. - */ -#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) -#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) -#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) -/*! I2SPRESENT - I 2S present indicator. This field is Read-only. - * 0b0..This Flexcomm does not include the I2S function. - * 0b1..This Flexcomm includes the I2S function. - */ -#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) -#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) -#define FLEXCOMM_PSELID_ID_SHIFT (12U) -#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) -/*! @} */ - -/*! @name PID - Peripheral identification register. */ -/*! @{ */ -#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) -#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) -#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) -#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) -#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) -#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) -#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) -#define FLEXCOMM_PID_ID_SHIFT (16U) -#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FLEXCOMM_Register_Masks */ - - -/* FLEXCOMM - Peripheral instance base addresses */ -/** Peripheral FLEXCOMM0 base address */ -#define FLEXCOMM0_BASE (0x40086000u) -/** Peripheral FLEXCOMM0 base pointer */ -#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) -/** Peripheral FLEXCOMM1 base address */ -#define FLEXCOMM1_BASE (0x40087000u) -/** Peripheral FLEXCOMM1 base pointer */ -#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) -/** Peripheral FLEXCOMM2 base address */ -#define FLEXCOMM2_BASE (0x40088000u) -/** Peripheral FLEXCOMM2 base pointer */ -#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) -/** Peripheral FLEXCOMM3 base address */ -#define FLEXCOMM3_BASE (0x40089000u) -/** Peripheral FLEXCOMM3 base pointer */ -#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) -/** Peripheral FLEXCOMM4 base address */ -#define FLEXCOMM4_BASE (0x4008A000u) -/** Peripheral FLEXCOMM4 base pointer */ -#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) -/** Peripheral FLEXCOMM5 base address */ -#define FLEXCOMM5_BASE (0x40096000u) -/** Peripheral FLEXCOMM5 base pointer */ -#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) -/** Peripheral FLEXCOMM6 base address */ -#define FLEXCOMM6_BASE (0x40097000u) -/** Peripheral FLEXCOMM6 base pointer */ -#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) -/** Peripheral FLEXCOMM7 base address */ -#define FLEXCOMM7_BASE (0x40098000u) -/** Peripheral FLEXCOMM7 base pointer */ -#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) -/** Array initializer of FLEXCOMM peripheral base addresses */ -#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE } -/** Array initializer of FLEXCOMM peripheral base pointers */ -#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7 } -/** Interrupt vectors for the FLEXCOMM peripheral type */ -#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- FMC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer - * @{ - */ - -/** FMC - Register Layout Typedef */ -typedef struct { - __IO uint32_t FCTR; /**< Control register, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t FBWST; /**< Wait state register, offset: 0x10 */ - uint8_t RESERVED_1[12]; - __IO uint32_t FMSSTART; /**< Signature start address register, offset: 0x20 */ - __IO uint32_t FMSSTOP; /**< Signature stop-address register, offset: 0x24 */ - uint8_t RESERVED_2[4]; - __I uint32_t FMSW[4]; /**< Words of 128-bit signature word, array offset: 0x2C, array step: 0x4 */ - uint8_t RESERVED_3[4004]; - __I uint32_t FMSTAT; /**< Signature generation status register, offset: 0xFE0 */ - uint8_t RESERVED_4[4]; - __O uint32_t FMSTATCLR; /**< Signature generation status clear register, offset: 0xFE8 */ -} FMC_Type; - -/* ---------------------------------------------------------------------------- - -- FMC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup FMC_Register_Masks FMC Register Masks - * @{ - */ - -/*! @name FCTR - Control register */ -/*! @{ */ -#define FMC_FCTR_FS_RD0_MASK (0x8U) -#define FMC_FCTR_FS_RD0_SHIFT (3U) -#define FMC_FCTR_FS_RD0(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK) -#define FMC_FCTR_FS_RD1_MASK (0x10U) -#define FMC_FCTR_FS_RD1_SHIFT (4U) -#define FMC_FCTR_FS_RD1(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK) -/*! @} */ - -/*! @name FBWST - Wait state register */ -/*! @{ */ -#define FMC_FBWST_WAITSTATES_MASK (0xFFU) -#define FMC_FBWST_WAITSTATES_SHIFT (0U) -#define FMC_FBWST_WAITSTATES(x) (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK) -/*! @} */ - -/*! @name FMSSTART - Signature start address register */ -/*! @{ */ -#define FMC_FMSSTART_START_MASK (0x1FFFFU) -#define FMC_FMSSTART_START_SHIFT (0U) -#define FMC_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK) -/*! @} */ - -/*! @name FMSSTOP - Signature stop-address register */ -/*! @{ */ -#define FMC_FMSSTOP_STOP_MASK (0x1FFFFU) -#define FMC_FMSSTOP_STOP_SHIFT (0U) -#define FMC_FMSSTOP_STOP(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK) -#define FMC_FMSSTOP_SIG_START_MASK (0x20000U) -#define FMC_FMSSTOP_SIG_START_SHIFT (17U) -#define FMC_FMSSTOP_SIG_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK) -/*! @} */ - -/*! @name FMSW - Words of 128-bit signature word */ -/*! @{ */ -#define FMC_FMSW_SW_MASK (0xFFFFFFFFU) -#define FMC_FMSW_SW_SHIFT (0U) -#define FMC_FMSW_SW(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK) -/*! @} */ - -/* The count of FMC_FMSW */ -#define FMC_FMSW_COUNT (4U) - -/*! @name FMSTAT - Signature generation status register */ -/*! @{ */ -#define FMC_FMSTAT_SIG_DONE_MASK (0x4U) -#define FMC_FMSTAT_SIG_DONE_SHIFT (2U) -#define FMC_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK) -/*! @} */ - -/*! @name FMSTATCLR - Signature generation status clear register */ -/*! @{ */ -#define FMC_FMSTATCLR_SIG_DONE_CLR_MASK (0x4U) -#define FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT (2U) -#define FMC_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group FMC_Register_Masks */ - - -/* FMC - Peripheral instance base addresses */ -/** Peripheral FMC base address */ -#define FMC_BASE (0x40034000u) -/** Peripheral FMC base pointer */ -#define FMC ((FMC_Type *)FMC_BASE) -/** Array initializer of FMC peripheral base addresses */ -#define FMC_BASE_ADDRS { FMC_BASE } -/** Array initializer of FMC peripheral base pointers */ -#define FMC_BASE_PTRS { FMC } - -/*! - * @} - */ /* end of group FMC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer - * @{ - */ - -/** GINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ - uint8_t RESERVED_0[28]; - __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ - uint8_t RESERVED_1[24]; - __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ -} GINT_Type; - -/* ---------------------------------------------------------------------------- - -- GINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GINT_Register_Masks GINT Register Masks - * @{ - */ - -/*! @name CTRL - GPIO grouped interrupt control register */ -/*! @{ */ -#define GINT_CTRL_INT_MASK (0x1U) -#define GINT_CTRL_INT_SHIFT (0U) -/*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. - * 0b0..No request. No interrupt request is pending. - * 0b1..Request active. Interrupt request is active. - */ -#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) -#define GINT_CTRL_COMB_MASK (0x2U) -#define GINT_CTRL_COMB_SHIFT (1U) -/*! COMB - Combine enabled inputs for group interrupt - * 0b0..Or. OR functionality: A grouped interrupt is generated when any one of the enabled inputs is active (based on its programmed polarity). - * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). - */ -#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) -#define GINT_CTRL_TRIG_MASK (0x4U) -#define GINT_CTRL_TRIG_SHIFT (2U) -/*! TRIG - Group interrupt trigger - * 0b0..Edge-triggered. - * 0b1..Level-triggered. - */ -#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) -/*! @} */ - -/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ -/*! @{ */ -#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) -#define GINT_PORT_POL_POL_SHIFT (0U) -#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) -/*! @} */ - -/* The count of GINT_PORT_POL */ -#define GINT_PORT_POL_COUNT (2U) - -/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ -/*! @{ */ -#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) -#define GINT_PORT_ENA_ENA_SHIFT (0U) -#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) -/*! @} */ - -/* The count of GINT_PORT_ENA */ -#define GINT_PORT_ENA_COUNT (2U) - - -/*! - * @} - */ /* end of group GINT_Register_Masks */ - - -/* GINT - Peripheral instance base addresses */ -/** Peripheral GINT0 base address */ -#define GINT0_BASE (0x40002000u) -/** Peripheral GINT0 base pointer */ -#define GINT0 ((GINT_Type *)GINT0_BASE) -/** Peripheral GINT1 base address */ -#define GINT1_BASE (0x40003000u) -/** Peripheral GINT1 base pointer */ -#define GINT1 ((GINT_Type *)GINT1_BASE) -/** Array initializer of GINT peripheral base addresses */ -#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } -/** Array initializer of GINT peripheral base pointers */ -#define GINT_BASE_PTRS { GINT0, GINT1 } -/** Interrupt vectors for the GINT peripheral type */ -#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } - -/*! - * @} - */ /* end of group GINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- GPIO Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer - * @{ - */ - -/** GPIO - Register Layout Typedef */ -typedef struct { - __IO uint8_t B[2][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[4032]; - __IO uint32_t W[2][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3840]; - __IO uint32_t DIR[2]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[120]; - __IO uint32_t MASK[2]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[120]; - __IO uint32_t PIN[2]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[120]; - __IO uint32_t MPIN[2]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[120]; - __IO uint32_t SET[2]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[120]; - __O uint32_t CLR[2]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[120]; - __O uint32_t NOT[2]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[120]; - __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[120]; - __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[120]; - __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ -} GPIO_Type; - -/* ---------------------------------------------------------------------------- - -- GPIO Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup GPIO_Register_Masks GPIO Register Masks - * @{ - */ - -/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ -/*! @{ */ -#define GPIO_B_PBYTE_MASK (0x1U) -#define GPIO_B_PBYTE_SHIFT (0U) -#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) -/*! @} */ - -/* The count of GPIO_B */ -#define GPIO_B_COUNT (2U) - -/* The count of GPIO_B */ -#define GPIO_B_COUNT2 (32U) - -/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ -/*! @{ */ -#define GPIO_W_PWORD_MASK (0xFFFFFFFFU) -#define GPIO_W_PWORD_SHIFT (0U) -#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) -/*! @} */ - -/* The count of GPIO_W */ -#define GPIO_W_COUNT (2U) - -/* The count of GPIO_W */ -#define GPIO_W_COUNT2 (32U) - -/*! @name DIR - Direction registers */ -/*! @{ */ -#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) -#define GPIO_DIR_DIRP_SHIFT (0U) -#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) -/*! @} */ - -/* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (2U) - -/*! @name MASK - Mask register */ -/*! @{ */ -#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) -#define GPIO_MASK_MASKP_SHIFT (0U) -#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) -/*! @} */ - -/* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (2U) - -/*! @name PIN - Port pin register */ -/*! @{ */ -#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) -#define GPIO_PIN_PORT_SHIFT (0U) -#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) -/*! @} */ - -/* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (2U) - -/*! @name MPIN - Masked port register */ -/*! @{ */ -#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) -#define GPIO_MPIN_MPORTP_SHIFT (0U) -#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) -/*! @} */ - -/* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (2U) - -/*! @name SET - Write: Set register for port Read: output bits for port */ -/*! @{ */ -#define GPIO_SET_SETP_MASK (0xFFFFFFFFU) -#define GPIO_SET_SETP_SHIFT (0U) -#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) -/*! @} */ - -/* The count of GPIO_SET */ -#define GPIO_SET_COUNT (2U) - -/*! @name CLR - Clear port */ -/*! @{ */ -#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) -#define GPIO_CLR_CLRP_SHIFT (0U) -#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) -/*! @} */ - -/* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (2U) - -/*! @name NOT - Toggle port */ -/*! @{ */ -#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) -#define GPIO_NOT_NOTP_SHIFT (0U) -#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) -/*! @} */ - -/* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (2U) - -/*! @name DIRSET - Set pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) -#define GPIO_DIRSET_DIRSETP_SHIFT (0U) -#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) -/*! @} */ - -/* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (2U) - -/*! @name DIRCLR - Clear pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) -#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) -#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) -/*! @} */ - -/* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (2U) - -/*! @name DIRNOT - Toggle pin direction bits for port */ -/*! @{ */ -#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) -#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) -#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) -/*! @} */ - -/* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (2U) - - -/*! - * @} - */ /* end of group GPIO_Register_Masks */ - - -/* GPIO - Peripheral instance base addresses */ -/** Peripheral GPIO base address */ -#define GPIO_BASE (0x4008C000u) -/** Peripheral GPIO base pointer */ -#define GPIO ((GPIO_Type *)GPIO_BASE) -/** Array initializer of GPIO peripheral base addresses */ -#define GPIO_BASE_ADDRS { GPIO_BASE } -/** Array initializer of GPIO peripheral base pointers */ -#define GPIO_BASE_PTRS { GPIO } - -/*! - * @} - */ /* end of group GPIO_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2C Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer - * @{ - */ - -/** I2C - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2048]; - __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ - __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ - __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ - __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ - __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ - __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ - uint8_t RESERVED_1[4]; - __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ - __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ - __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ - uint8_t RESERVED_2[20]; - __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ - __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ - __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ - __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ - uint8_t RESERVED_3[36]; - __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ - uint8_t RESERVED_4[1912]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} I2C_Type; - -/* ---------------------------------------------------------------------------- - -- I2C Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2C_Register_Masks I2C Register Masks - * @{ - */ - -/*! @name CFG - Configuration for shared functions. */ -/*! @{ */ -#define I2C_CFG_MSTEN_MASK (0x1U) -#define I2C_CFG_MSTEN_SHIFT (0U) -/*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not changed, but the Master function is internally reset. - * 0b0..Disabled. The I2C Master function is disabled. - * 0b1..Enabled. The I2C Master function is enabled. - */ -#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) -#define I2C_CFG_SLVEN_MASK (0x2U) -#define I2C_CFG_SLVEN_SHIFT (1U) -/*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not changed, but the Slave function is internally reset. - * 0b0..Disabled. The I2C slave function is disabled. - * 0b1..Enabled. The I2C slave function is enabled. - */ -#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) -#define I2C_CFG_MONEN_MASK (0x4U) -#define I2C_CFG_MONEN_SHIFT (2U) -/*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not changed, but the Monitor function is internally reset. - * 0b0..Disabled. The I2C Monitor function is disabled. - * 0b1..Enabled. The I2C Monitor function is enabled. - */ -#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) -#define I2C_CFG_TIMEOUTEN_MASK (0x8U) -#define I2C_CFG_TIMEOUTEN_SHIFT (3U) -/*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. - * 0b0..Disabled. Time-out function is disabled. - * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause interrupts if they are enabled. Typically, only one time-out will be used in a system. - */ -#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) -#define I2C_CFG_MONCLKSTR_MASK (0x10U) -#define I2C_CFG_MONCLKSTR_SHIFT (4U) -/*! MONCLKSTR - Monitor function Clock Stretching. - * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able to read data provided by the Monitor function before it is overwritten. This mode may be used when non-invasive monitoring is critical. - * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can read all incoming data supplied by the Monitor function. - */ -#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) -#define I2C_CFG_HSCAPABLE_MASK (0x20U) -#define I2C_CFG_HSCAPABLE_SHIFT (5U) -/*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive and filter, as well as the timing for certain I2C signalling, enabling High-speed mode applies to all functions: Master, Slave, and Monitor. - * 0b0..Fast-mode plus. The I 2C interface will support Standard-mode, Fast-mode, and Fast-mode Plus, to the extent that the pin electronics support these modes. Any changes that need to be made to the pin controls, such as changing the drive strength or filtering, must be made by software via the IOCON register associated with each I2C pin, - * 0b1..High-speed. In addition to Standard-mode, Fast-mode, and Fast-mode Plus, the I 2C interface will support High-speed mode to the extent that the pin electronics support these modes. See Section 25.7.2.2 for more information. - */ -#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) -/*! @} */ - -/*! @name STAT - Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ -#define I2C_STAT_MSTPENDING_MASK (0x1U) -#define I2C_STAT_MSTPENDING_SHIFT (0U) -/*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what type of software service if any the master expects. This flag will cause an interrupt when set if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle state, and no communication is needed, mask this interrupt. - * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. - * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the idle state, it is waiting to receive or transmit data or the NACK bit. - */ -#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) -#define I2C_STAT_MSTSTATE_MASK (0xEU) -#define I2C_STAT_MSTSTATE_SHIFT (1U) -/*! MSTSTATE - Master State code. The master state code reflects the master state when the MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field indicates a specific required service for the Master function. All other values are reserved. See Table 400 for details of state values and appropriate responses. - * 0b000..Idle. The Master function is available to be used for a new transaction. - * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. - * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. - * 0b011..NACK Address. Slave NACKed address. - * 0b100..NACK Data. Slave NACKed transmitted data. - */ -#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) -#define I2C_STAT_MSTARBLOSS_MASK (0x10U) -#define I2C_STAT_MSTARBLOSS_SHIFT (4U) -/*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Arbitration Loss has occurred. - * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. - */ -#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) -#define I2C_STAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_STAT_MSTSTSTPERR_SHIFT (6U) -/*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. - * 0b0..No Start/Stop Error has occurred. - * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an idle state, no action is required. A request for a Start could be made, or software could attempt to insure that the bus has not stalled. - */ -#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) -#define I2C_STAT_SLVPENDING_MASK (0x100U) -#define I2C_STAT_SLVPENDING_SHIFT (8U) -/*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are detected automatically. Due to the requirements of the HS I2C specification, slave addresses must also be detected automatically, since the address must be acknowledged before the clock can be stretched. - * 0b0..In progress. The Slave function does not currently need service. - * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. - */ -#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) -#define I2C_STAT_SLVSTATE_MASK (0x600U) -#define I2C_STAT_SLVSTATE_SHIFT (9U) -/*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for the Slave function. All other values are reserved. See Table 401 for state values and actions. note that the occurrence of some states and how they are handled are affected by DMA mode and Automatic Operation modes. - * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. - * 0b01..Slave receive. Received data is available (Slave Receiver mode). - * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). - */ -#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) -#define I2C_STAT_SLVNOTSTR_MASK (0x800U) -#define I2C_STAT_SLVNOTSTR_SHIFT (11U) -/*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave operation. This read-only flag reflects the slave function status in real time. - * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. - * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or Power-down mode could be entered at this time. - */ -#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) -#define I2C_STAT_SLVIDX_MASK (0x3000U) -#define I2C_STAT_SLVIDX_SHIFT (12U) -/*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been selected by receiving an address that matches one of the slave addresses defined by any enabled slave address registers, and provides an identification of the address that was matched. It is possible that more than one address could be matched, but only one match can be reported here. - * 0b00..Address 0. Slave address 0 was matched. - * 0b01..Address 1. Slave address 1 was matched. - * 0b10..Address 2. Slave address 2 was matched. - * 0b11..Address 3. Slave address 3 was matched. - */ -#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) -#define I2C_STAT_SLVSEL_MASK (0x4000U) -#define I2C_STAT_SLVSEL_SHIFT (14U) -/*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave function to acknowledge the address, or when the address has been automatically acknowledged. It is cleared when another address cycle presents an address that does not match an enabled address on the Slave function, when slave software decides to NACK a matched address, when there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of Automatic Operation. SLVSEL is not cleared if software NACKs data. - * 0b0..Not selected. The Slave function is not currently selected. - * 0b1..Selected. The Slave function is currently selected. - */ -#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) -#define I2C_STAT_SLVDESEL_MASK (0x8000U) -#define I2C_STAT_SLVDESEL_SHIFT (15U) -/*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via INTENSET. This flag can be cleared by writing a 1 to this bit. - * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently selected. That information can be found in the SLVSEL flag. - * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. - */ -#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) -#define I2C_STAT_MONRDY_MASK (0x10000U) -#define I2C_STAT_MONRDY_SHIFT (16U) -/*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. - * 0b0..No data. The Monitor function does not currently have data available. - * 0b1..Data waiting. The Monitor function has data waiting to be read. - */ -#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) -#define I2C_STAT_MONOV_MASK (0x20000U) -#define I2C_STAT_MONOV_SHIFT (17U) -/*! MONOV - Monitor Overflow flag. - * 0b0..No overrun. Monitor data has not overrun. - * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. - */ -#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) -#define I2C_STAT_MONACTIVE_MASK (0x40000U) -#define I2C_STAT_MONACTIVE_SHIFT (18U) -/*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to be active. Active is defined here as when some Master is on the bus: a bus Start has occurred more recently than a bus Stop. - * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. - * 0b1..Active. The Monitor function considers the I2C bus to be active. - */ -#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) -#define I2C_STAT_MONIDLE_MASK (0x80000U) -#define I2C_STAT_MONIDLE_SHIFT (19U) -/*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change from active to inactive. This can be used by software to decide when to process data accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the INTENSET register. The flag can be cleared by writing a 1 to this bit. - * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. - * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. - */ -#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) -#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) -/*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus is idle. - * 0b0..No time-out. I2C bus events have not caused a time-out. - * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. - */ -#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) -#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_STAT_SCLTIMEOUT_SHIFT (25U) -/*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. - * 0b0..No time-out. SCL low time has not caused a time-out. - * 0b1..Time-out. SCL low time has caused a time-out. - */ -#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable Set and read register. */ -/*! @{ */ -#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) -#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) -/*! MSTPENDINGEN - Master Pending interrupt Enable. - * 0b0..Disabled. The MstPending interrupt is disabled. - * 0b1..Enabled. The MstPending interrupt is enabled. - */ -#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) -#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) -#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) -/*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. - * 0b0..Disabled. The MstArbLoss interrupt is disabled. - * 0b1..Enabled. The MstArbLoss interrupt is enabled. - */ -#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) -#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) -#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) -/*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. - * 0b0..Disabled. The MstStStpErr interrupt is disabled. - * 0b1..Enabled. The MstStStpErr interrupt is enabled. - */ -#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) -#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) -#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) -/*! SLVPENDINGEN - Slave Pending interrupt Enable. - * 0b0..Disabled. The SlvPending interrupt is disabled. - * 0b1..Enabled. The SlvPending interrupt is enabled. - */ -#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) -#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) -#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) -/*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. - * 0b0..Disabled. The SlvNotStr interrupt is disabled. - * 0b1..Enabled. The SlvNotStr interrupt is enabled. - */ -#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) -#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) -#define I2C_INTENSET_SLVDESELEN_SHIFT (15U) -/*! SLVDESELEN - Slave Deselect interrupt Enable. - * 0b0..Disabled. The SlvDeSel interrupt is disabled. - * 0b1..Enabled. The SlvDeSel interrupt is enabled. - */ -#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) -#define I2C_INTENSET_MONRDYEN_MASK (0x10000U) -#define I2C_INTENSET_MONRDYEN_SHIFT (16U) -/*! MONRDYEN - Monitor data Ready interrupt Enable. - * 0b0..Disabled. The MonRdy interrupt is disabled. - * 0b1..Enabled. The MonRdy interrupt is enabled. - */ -#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) -#define I2C_INTENSET_MONOVEN_MASK (0x20000U) -#define I2C_INTENSET_MONOVEN_SHIFT (17U) -/*! MONOVEN - Monitor Overrun interrupt Enable. - * 0b0..Disabled. The MonOv interrupt is disabled. - * 0b1..Enabled. The MonOv interrupt is enabled. - */ -#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) -#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) -#define I2C_INTENSET_MONIDLEEN_SHIFT (19U) -/*! MONIDLEEN - Monitor Idle interrupt Enable. - * 0b0..Disabled. The MonIdle interrupt is disabled. - * 0b1..Enabled. The MonIdle interrupt is enabled. - */ -#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) -#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) -#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) -/*! EVENTTIMEOUTEN - Event time-out interrupt Enable. - * 0b0..Disabled. The Event time-out interrupt is disabled. - * 0b1..Enabled. The Event time-out interrupt is enabled. - */ -#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) -#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) -#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) -/*! SCLTIMEOUTEN - SCL time-out interrupt Enable. - * 0b0..Disabled. The SCL time-out interrupt is disabled. - * 0b1..Enabled. The SCL time-out interrupt is enabled. - */ -#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. */ -/*! @{ */ -#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) -#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) -#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) -#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) -#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) -#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) -#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) -#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) -#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) -#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) -#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) -#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) -#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) -#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) -#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) -#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) -#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) -#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) -#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) -#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) -#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) -#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) -#define I2C_INTENCLR_MONOVCLR_SHIFT (17U) -#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) -#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) -#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) -#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) -#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) -#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) -#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) -#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) -/*! @} */ - -/*! @name TIMEOUT - Time-out value register. */ -/*! @{ */ -#define I2C_TIMEOUT_TOMIN_MASK (0xFU) -#define I2C_TIMEOUT_TOMIN_SHIFT (0U) -#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) -#define I2C_TIMEOUT_TO_MASK (0xFFF0U) -#define I2C_TIMEOUT_TO_SHIFT (4U) -#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) -/*! @} */ - -/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ -/*! @{ */ -#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) -#define I2C_CLKDIV_DIVVAL_SHIFT (0U) -#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ -/*! @{ */ -#define I2C_INTSTAT_MSTPENDING_MASK (0x1U) -#define I2C_INTSTAT_MSTPENDING_SHIFT (0U) -#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) -#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) -#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) -#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) -#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) -#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) -#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) -#define I2C_INTSTAT_SLVPENDING_MASK (0x100U) -#define I2C_INTSTAT_SLVPENDING_SHIFT (8U) -#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) -#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) -#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) -#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) -#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) -#define I2C_INTSTAT_SLVDESEL_SHIFT (15U) -#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) -#define I2C_INTSTAT_MONRDY_MASK (0x10000U) -#define I2C_INTSTAT_MONRDY_SHIFT (16U) -#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) -#define I2C_INTSTAT_MONOV_MASK (0x20000U) -#define I2C_INTSTAT_MONOV_SHIFT (17U) -#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) -#define I2C_INTSTAT_MONIDLE_MASK (0x80000U) -#define I2C_INTSTAT_MONIDLE_SHIFT (19U) -#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) -#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) -#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) -#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) -#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) -#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) -#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) -/*! @} */ - -/*! @name MSTCTL - Master control register. */ -/*! @{ */ -#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) -#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) -/*! MSTCONTINUE - Master Continue. This bit is write-only. - * 0b0..No effect. - * 0b1..Continue. Informs the Master function to continue to the next operation. This must done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. - */ -#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) -#define I2C_MSTCTL_MSTSTART_MASK (0x2U) -#define I2C_MSTCTL_MSTSTART_SHIFT (1U) -/*! MSTSTART - Master Start control. This bit is write-only. - * 0b0..No effect. - * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. - */ -#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) -#define I2C_MSTCTL_MSTSTOP_MASK (0x4U) -#define I2C_MSTCTL_MSTSTOP_SHIFT (2U) -/*! MSTSTOP - Master Stop control. This bit is write-only. - * 0b0..No effect. - * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave if the master is receiving data from the slave (Master Receiver mode). - */ -#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) -#define I2C_MSTCTL_MSTDMA_MASK (0x8U) -#define I2C_MSTCTL_MSTDMA_SHIFT (3U) -/*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type operations such as Start, address, Stop, and address match must always be done with software, typically via an interrupt. Address acknowledgement must also be done by software except when the I2C is configured to be HSCAPABLE (and address acknowledgement is handled entirely by hardware) or when Automatic Operation is enabled. When a DMA data transfer is complete, MSTDMA must be cleared prior to beginning the next operation, typically a Start or Stop.This bit is read/write. - * 0b0..Disable. No DMA requests are generated for master operation. - * 0b1..Enable. A DMA request is generated for I2C master data operations. When this I2C master is generating Acknowledge bits in Master Receiver mode, the acknowledge is generated automatically. - */ -#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) -/*! @} */ - -/*! @name MSTTIME - Master timing configuration. */ -/*! @{ */ -#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) -#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) -/*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. - * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. - * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) -#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) -#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) -/*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this master on SCL. Other masters in a multi-master system could shorten this time. This corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. - * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. - * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . - * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. - * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. - * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. - * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. - * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. - * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. - */ -#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) -/*! @} */ - -/*! @name MSTDAT - Combined Master receiver and transmitter data register. */ -/*! @{ */ -#define I2C_MSTDAT_DATA_MASK (0xFFU) -#define I2C_MSTDAT_DATA_SHIFT (0U) -#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVCTL - Slave control register. */ -/*! @{ */ -#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) -#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) -/*! SLVCONTINUE - Slave Continue. - * 0b0..No effect. - * 0b1..Continue. Informs the Slave function to continue to the next operation, by clearing the SLVPENDING flag in the STAT register. This must be done after writing transmit data, reading received data, or any other housekeeping related to the next bus operation. Automatic Operation has different requirements. SLVCONTINUE should not be set unless SLVPENDING = 1. - */ -#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) -#define I2C_SLVCTL_SLVNACK_MASK (0x2U) -#define I2C_SLVCTL_SLVNACK_SHIFT (1U) -/*! SLVNACK - Slave NACK. - * 0b0..No effect. - * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). - */ -#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) -#define I2C_SLVCTL_SLVDMA_MASK (0x8U) -#define I2C_SLVCTL_SLVDMA_SHIFT (3U) -/*! SLVDMA - Slave DMA enable. - * 0b0..Disabled. No DMA requests are issued for Slave mode operation. - * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. - */ -#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) -#define I2C_SLVCTL_AUTOACK_MASK (0x100U) -#define I2C_SLVCTL_AUTOACK_SHIFT (8U) -/*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches SLVADR0 and the direction set by AUTOMATCHREAD to be ACKed immediately; this is used with DMA to allow processing of the data without intervention. If this bit is clear and a header matches SLVADR0, the behavior is controlled by AUTONACK in the SLVADR0 register: allowing NACK or interrupt. - * 0b0..Normal, non-automatic operation. If AUTONACK = 0, an SlvPending interrupt is generated when a matching address is received. If AUTONACK = 1, received addresses are NACKed (ignored). - * 0b1..A header with matching SLVADR0 and matching direction as set by AUTOMATCHREAD will be ACKed immediately, allowing the master to move on to the data bytes. If the address matches SLVADR0, but the direction does not match AUTOMATCHREAD, the behavior will depend on the AUTONACK bit in the SLVADR0 register: if AUTONACK is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. - */ -#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) -#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) -#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) -/*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write request on the next header with an address matching SLVADR0. Since DMA needs to be configured to match the transfer direction, the direction needs to be specified. This bit allows a direction to be chosen for the next operation. - * 0b0..The expected next operation in Automatic Mode is an I2C write. - * 0b1..The expected next operation in Automatic Mode is an I2C read. - */ -#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) -/*! @} */ - -/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ -/*! @{ */ -#define I2C_SLVDAT_DATA_MASK (0xFFU) -#define I2C_SLVDAT_DATA_SHIFT (0U) -#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) -/*! @} */ - -/*! @name SLVADR - Slave address register. */ -/*! @{ */ -#define I2C_SLVADR_SADISABLE_MASK (0x1U) -#define I2C_SLVADR_SADISABLE_SHIFT (0U) -/*! SADISABLE - Slave Address n Disable. - * 0b0..Enabled. Slave Address n is enabled. - * 0b1..Ignored Slave Address n is ignored. - */ -#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) -#define I2C_SLVADR_SLVADR_MASK (0xFEU) -#define I2C_SLVADR_SLVADR_SHIFT (1U) -#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) -#define I2C_SLVADR_AUTONACK_MASK (0x8000U) -#define I2C_SLVADR_AUTONACK_SHIFT (15U) -/*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows software to ignore I2C traffic while handling previous I2C data or other operations. - * 0b0..Normal operation, matching I2C addresses are not ignored. - * 0b1..Automatic-only mode. All incoming addresses are ignored (NACKed), unless AUTOACK is set, it matches SLVADRn, and AUTOMATCHREAD matches the direction. - */ -#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) -/*! @} */ - -/* The count of I2C_SLVADR */ -#define I2C_SLVADR_COUNT (4U) - -/*! @name SLVQUAL0 - Slave Qualification for address 0. */ -/*! @{ */ -#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) -#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) -/*! QUALMODE0 - Qualify mode for slave address 0. - * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. - * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. - */ -#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) -#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) -#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) -#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) -/*! @} */ - -/*! @name MONRXDAT - Monitor receiver data register. */ -/*! @{ */ -#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) -#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) -#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) -#define I2C_MONRXDAT_MONSTART_MASK (0x100U) -#define I2C_MONRXDAT_MONSTART_SHIFT (8U) -/*! MONSTART - Monitor Received Start. - * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. - * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) -#define I2C_MONRXDAT_MONRESTART_MASK (0x200U) -#define I2C_MONRXDAT_MONRESTART_SHIFT (9U) -/*! MONRESTART - Monitor Received Repeated Start. - * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. - * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. - */ -#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) -#define I2C_MONRXDAT_MONNACK_MASK (0x400U) -#define I2C_MONRXDAT_MONNACK_SHIFT (10U) -/*! MONNACK - Monitor Received NACK. - * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. - * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. - */ -#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ -#define I2C_ID_APERTURE_MASK (0xFFU) -#define I2C_ID_APERTURE_SHIFT (0U) -#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) -#define I2C_ID_MINOR_REV_MASK (0xF00U) -#define I2C_ID_MINOR_REV_SHIFT (8U) -#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) -#define I2C_ID_MAJOR_REV_MASK (0xF000U) -#define I2C_ID_MAJOR_REV_SHIFT (12U) -#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) -#define I2C_ID_ID_MASK (0xFFFF0000U) -#define I2C_ID_ID_SHIFT (16U) -#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2C_Register_Masks */ - - -/* I2C - Peripheral instance base addresses */ -/** Peripheral I2C0 base address */ -#define I2C0_BASE (0x40086000u) -/** Peripheral I2C0 base pointer */ -#define I2C0 ((I2C_Type *)I2C0_BASE) -/** Peripheral I2C1 base address */ -#define I2C1_BASE (0x40087000u) -/** Peripheral I2C1 base pointer */ -#define I2C1 ((I2C_Type *)I2C1_BASE) -/** Peripheral I2C2 base address */ -#define I2C2_BASE (0x40088000u) -/** Peripheral I2C2 base pointer */ -#define I2C2 ((I2C_Type *)I2C2_BASE) -/** Peripheral I2C3 base address */ -#define I2C3_BASE (0x40089000u) -/** Peripheral I2C3 base pointer */ -#define I2C3 ((I2C_Type *)I2C3_BASE) -/** Peripheral I2C4 base address */ -#define I2C4_BASE (0x4008A000u) -/** Peripheral I2C4 base pointer */ -#define I2C4 ((I2C_Type *)I2C4_BASE) -/** Peripheral I2C5 base address */ -#define I2C5_BASE (0x40096000u) -/** Peripheral I2C5 base pointer */ -#define I2C5 ((I2C_Type *)I2C5_BASE) -/** Peripheral I2C6 base address */ -#define I2C6_BASE (0x40097000u) -/** Peripheral I2C6 base pointer */ -#define I2C6 ((I2C_Type *)I2C6_BASE) -/** Peripheral I2C7 base address */ -#define I2C7_BASE (0x40098000u) -/** Peripheral I2C7 base pointer */ -#define I2C7 ((I2C_Type *)I2C7_BASE) -/** Array initializer of I2C peripheral base addresses */ -#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE } -/** Array initializer of I2C peripheral base pointers */ -#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7 } -/** Interrupt vectors for the I2C peripheral type */ -#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2C_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- I2S Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer - * @{ - */ - -/** I2S - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[3072]; - __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ - __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ - __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - uint8_t RESERVED_2[480]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ - uint8_t RESERVED_5[8]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ - uint8_t RESERVED_6[8]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ - uint8_t RESERVED_7[436]; - __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ -} I2S_Type; - -/* ---------------------------------------------------------------------------- - -- I2S Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup I2S_Register_Masks I2S Register Masks - * @{ - */ - -/*! @name CFG1 - Configuration register 1 for the primary channel pair. */ -/*! @{ */ -#define I2S_CFG1_MAINENABLE_MASK (0x1U) -#define I2S_CFG1_MAINENABLE_SHIFT (0U) -/*! MAINENABLE - Main enable for I 2S function in this Flexcomm - * 0b0..All I 2S channel pairs in this Flexcomm are disabled and the internal state machines, counters, and flags are reset. No other channel pairs can be enabled. - * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. - */ -#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) -#define I2S_CFG1_DATAPAUSE_MASK (0x2U) -#define I2S_CFG1_DATAPAUSE_SHIFT (1U) -/*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. - * 0b0..Normal operation, or resuming normal operation at the next frame if the I2S has already been paused. - * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. - */ -#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) -#define I2S_CFG1_PAIRCOUNT_MASK (0xCU) -#define I2S_CFG1_PAIRCOUNT_SHIFT (2U) -/*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. - * 0b00..1 I2S channel pairs in this flexcomm - * 0b01..2 I2S channel pairs in this flexcomm - * 0b10..3 I2S channel pairs in this flexcomm - * 0b11..4 I2S channel pairs in this flexcomm - */ -#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) -#define I2S_CFG1_MSTSLVCFG_MASK (0x30U) -#define I2S_CFG1_MSTSLVCFG_SHIFT (4U) -/*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. - * 0b00..Normal slave mode, the default mode. SCK and WS are received from a master and used to transmit or receive data. - * 0b01..WS synchronized master. WS is received from another master and used to synchronize the generation of SCK, when divided from the Flexcomm function clock. - * 0b10..Master using an existing SCK. SCK is received and used directly to generate WS, as well as transmitting or receiving data. - * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. - */ -#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) -#define I2S_CFG1_MODE_MASK (0xC0U) -#define I2S_CFG1_MODE_SHIFT (6U) -/*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. - * 0b00..I2S mode a.k.a. 'classic' mode. WS has a 50% duty cycle, with (for each enabled channel pair) one piece of left channel data occurring during the first phase, and one pieces of right channel data occurring during the second phase. In this mode, the data region begins one clock after the leading WS edge for the frame. For a 50% WS duty cycle, FRAMELEN must define an even number of I2S clocks for the frame. If FRAMELEN defines an odd number of clocks per frame, the extra clock will occur on the right. - * 0b01..DSP mode where WS has a 50% duty cycle. See remark for mode 0. - * 0b10..DSP mode where WS has a one clock long pulse at the beginning of each data frame. - * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. - */ -#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) -#define I2S_CFG1_RIGHTLOW_MASK (0x100U) -#define I2S_CFG1_RIGHTLOW_SHIFT (8U) -/*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. - * 0b0..The right channel is taken from the high part of the FIFO data. For example, when data is 16 bits, FIFO bits 31:16 are used for the right channel. - * 0b1..The right channel is taken from the low part of the FIFO data. For example, when data is 16 bits, FIFO bits 15:0 are used for the right channel. - */ -#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) -#define I2S_CFG1_LEFTJUST_MASK (0x200U) -#define I2S_CFG1_LEFTJUST_SHIFT (9U) -/*! LEFTJUST - Left Justify data. - * 0b0..Data is transferred between the FIFO and the I2S serializer/deserializer right justified, i.e. starting from bit 0 and continuing to the position defined by DATALEN. This would correspond to right justified data in the stream on the data bus. - * 0b1..Data is transferred between the FIFO and the I2S serializer/deserializer left justified, i.e. starting from the MSB of the FIFO entry and continuing for the number of bits defined by DATALEN. This would correspond to left justified data in the stream on the data bus. - */ -#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) -#define I2S_CFG1_ONECHANNEL_MASK (0x400U) -#define I2S_CFG1_ONECHANNEL_SHIFT (10U) -/*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. - * 0b0..I2S data for this channel pair is treated as left and right channels. - * 0b1..I2S data for this channel pair is treated as a single channel, functionally the left channel for this pair. In mode 0 only, the right side of the frame begins at POSITION = 0x100. This is because mode 0 makes a clear distinction between the left and right sides of the frame. When ONECHANNEL = 1, the single channel of data may be placed on the right by setting POSITION to 0x100 + the data position within the right side (e.g. 0x108 would place data starting at the 8th clock after the middle of the frame). In other modes, data for the single channel of data is placed at the clock defined by POSITION. - */ -#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) -#define I2S_CFG1_SCK_POL_MASK (0x1000U) -#define I2S_CFG1_SCK_POL_SHIFT (12U) -/*! SCK_POL - SCK polarity. - * 0b0..Data is launched on SCK falling edges and sampled on SCK rising edges (standard for I2S). - * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. - */ -#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) -#define I2S_CFG1_WS_POL_MASK (0x2000U) -#define I2S_CFG1_WS_POL_SHIFT (13U) -/*! WS_POL - WS polarity. - * 0b0..Data frames begin at a falling edge of WS (standard for classic I2S). - * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). - */ -#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) -#define I2S_CFG1_DATALEN_MASK (0x1F0000U) -#define I2S_CFG1_DATALEN_SHIFT (16U) -#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) -/*! @} */ - -/*! @name CFG2 - Configuration register 2 for the primary channel pair. */ -/*! @{ */ -#define I2S_CFG2_FRAMELEN_MASK (0x1FFU) -#define I2S_CFG2_FRAMELEN_SHIFT (0U) -#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) -#define I2S_CFG2_POSITION_MASK (0x1FF0000U) -#define I2S_CFG2_POSITION_SHIFT (16U) -#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) -/*! @} */ - -/*! @name STAT - Status register for the primary channel pair. */ -/*! @{ */ -#define I2S_STAT_BUSY_MASK (0x1U) -#define I2S_STAT_BUSY_SHIFT (0U) -/*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. - * 0b0..The transmitter/receiver for channel pair is currently idle. - * 0b1..The transmitter/receiver for channel pair is currently processing data. - */ -#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) -#define I2S_STAT_SLVFRMERR_MASK (0x2U) -#define I2S_STAT_SLVFRMERR_SHIFT (1U) -/*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as a slave. An error indicates that the incoming WS signal did not transition as expected due to a mismatch between FRAMELEN and the actual incoming I2S stream. - * 0b0..No error has been recorded. - * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. - */ -#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) -#define I2S_STAT_LR_MASK (0x4U) -#define I2S_STAT_LR_SHIFT (2U) -/*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to be used by an I2S driver. Valid when one channel pair is busy. Indicates left or right data being processed for the currently busy channel pair. - * 0b0..Left channel. - * 0b1..Right channel. - */ -#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) -#define I2S_STAT_DATAPAUSED_MASK (0x8U) -#define I2S_STAT_DATAPAUSED_SHIFT (3U) -/*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels - * 0b0..Data is not currently paused. A data pause may have been requested but is not yet in force, waiting for an allowed pause point. Refer to the description of the DATAPAUSE control bit in the CFG1 register. - * 0b1..A data pause has been requested and is now in force. - */ -#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) -/*! @} */ - -/*! @name DIV - Clock divider, used by all channel pairs. */ -/*! @{ */ -#define I2S_DIV_DIV_MASK (0xFFFU) -#define I2S_DIV_DIV_SHIFT (0U) -#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define I2S_FIFOCFG_ENABLETX_MASK (0x1U) -#define I2S_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) -#define I2S_FIFOCFG_ENABLERX_MASK (0x2U) -#define I2S_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) -#define I2S_FIFOCFG_TXI2SSE0_MASK (0x4U) -#define I2S_FIFOCFG_TXI2SSE0_SHIFT (2U) -/*! TXI2SSE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused. - * 0b0..If the TX FIFO becomes empty, the last value is sent. This setting may be used when the data length is 24 bits or less, or when MONO = 1 for this channel pair. - * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. - */ -#define I2S_FIFOCFG_TXI2SSE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SSE0_SHIFT)) & I2S_FIFOCFG_TXI2SSE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -/*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. - * 0b0..48-bit I2S FIFO entries are handled as all 24-bit values. - * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. - */ -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) -#define I2S_FIFOCFG_SIZE_MASK (0x30U) -#define I2S_FIFOCFG_SIZE_SHIFT (4U) -#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) -#define I2S_FIFOCFG_DMATX_MASK (0x1000U) -#define I2S_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) -#define I2S_FIFOCFG_DMARX_MASK (0x2000U) -#define I2S_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) -#define I2S_FIFOCFG_WAKETX_MASK (0x4000U) -#define I2S_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) -#define I2S_FIFOCFG_WAKERX_MASK (0x8000U) -#define I2S_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) -#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) -#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) -#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define I2S_FIFOSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) -#define I2S_FIFOSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) -#define I2S_FIFOSTAT_PERINT_MASK (0x8U) -#define I2S_FIFOSTAT_PERINT_SHIFT (3U) -#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) -#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) -#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) -#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) -#define I2S_FIFOSTAT_RXFULL_MASK (0x80U) -#define I2S_FIFOSTAT_RXFULL_SHIFT (7U) -#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) -#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define I2S_FIFOSTAT_TXLVL_SHIFT (8U) -#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) -#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define I2S_FIFOSTAT_RXLVL_SHIFT (16U) -#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) -#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) -#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) -#define I2S_FIFOTRIG_TXLVL_SHIFT (8U) -#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) -#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define I2S_FIFOTRIG_RXLVL_SHIFT (16U) -#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define I2S_FIFOINTENSET_TXERR_MASK (0x1U) -#define I2S_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) -#define I2S_FIFOINTENSET_RXERR_MASK (0x2U) -#define I2S_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) -#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) -#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) -#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) -#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) -#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) -#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) -#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) -#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) -#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) -#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) -#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) -#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) -#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) -#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) -#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) -#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) -#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) -#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) -#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFOWR_TXDATA_SHIFT (0U) -#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) -#define I2S_FIFOWR48H_TXDATA_SHIFT (0U) -#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORD_RXDATA_SHIFT (0U) -#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48H_RXDATA_SHIFT (0U) -#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) -#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ -/*! @{ */ -#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) -#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) -#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) -/*! @} */ - -/*! @name ID - I2S Module identification */ -/*! @{ */ -#define I2S_ID_Aperture_MASK (0xFFU) -#define I2S_ID_Aperture_SHIFT (0U) -#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK) -#define I2S_ID_Minor_Rev_MASK (0xF00U) -#define I2S_ID_Minor_Rev_SHIFT (8U) -#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK) -#define I2S_ID_Major_Rev_MASK (0xF000U) -#define I2S_ID_Major_Rev_SHIFT (12U) -#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK) -#define I2S_ID_ID_MASK (0xFFFF0000U) -#define I2S_ID_ID_SHIFT (16U) -#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group I2S_Register_Masks */ - - -/* I2S - Peripheral instance base addresses */ -/** Peripheral I2S0 base address */ -#define I2S0_BASE (0x40097000u) -/** Peripheral I2S0 base pointer */ -#define I2S0 ((I2S_Type *)I2S0_BASE) -/** Peripheral I2S1 base address */ -#define I2S1_BASE (0x40098000u) -/** Peripheral I2S1 base pointer */ -#define I2S1 ((I2S_Type *)I2S1_BASE) -/** Array initializer of I2S peripheral base addresses */ -#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } -/** Array initializer of I2S peripheral base pointers */ -#define I2S_BASE_PTRS { I2S0, I2S1 } -/** Interrupt vectors for the I2S peripheral type */ -#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group I2S_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer - * @{ - */ - -/** INPUTMUX - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[192]; - __IO uint32_t PINTSEL[4]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DMA_ITRIG_INMUX[22]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */ - uint8_t RESERVED_2[40]; - __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */ - uint8_t RESERVED_3[16]; - __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ - __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ -} INPUTMUX_Type; - -/* ---------------------------------------------------------------------------- - -- INPUTMUX Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks - * @{ - */ - -/*! @name PINTSEL - Pin interrupt select register */ -/*! @{ */ -#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) -#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) -#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) -/*! @} */ - -/* The count of INPUTMUX_PINTSEL */ -#define INPUTMUX_PINTSEL_COUNT (4U) - -/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ -/*! @{ */ -#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA_ITRIG_INMUX */ -#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (22U) - -/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ -/*! @{ */ -#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) -#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) -#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) -/*! @} */ - -/* The count of INPUTMUX_DMA_OTRIG_INMUX */ -#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) - -/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ -/*! @{ */ -#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) -/*! @} */ - -/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ -/*! @{ */ -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) -#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group INPUTMUX_Register_Masks */ - - -/* INPUTMUX - Peripheral instance base addresses */ -/** Peripheral INPUTMUX base address */ -#define INPUTMUX_BASE (0x40005000u) -/** Peripheral INPUTMUX base pointer */ -#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) -/** Array initializer of INPUTMUX peripheral base addresses */ -#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } -/** Array initializer of INPUTMUX peripheral base pointers */ -#define INPUTMUX_BASE_PTRS { INPUTMUX } - -/*! - * @} - */ /* end of group INPUTMUX_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- IOCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer - * @{ - */ - -/** IOCON - Register Layout Typedef */ -typedef struct { - __IO uint32_t PIO[2][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ -} IOCON_Type; - -/* ---------------------------------------------------------------------------- - -- IOCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup IOCON_Register_Masks IOCON Register Masks - * @{ - */ - -/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ -/*! @{ */ -#define IOCON_PIO_FUNC_MASK (0x7U) -#define IOCON_PIO_FUNC_SHIFT (0U) -/*! FUNC - Selects pin function. - * 0b000..Alternative connection 0. - * 0b001..Alternative connection 1. - * 0b010..Alternative connection 2. - * 0b011..Alternative connection 3. - * 0b100..Alternative connection 4. - * 0b101..Alternative connection 5. - * 0b110..Alternative connection 6. - * 0b111..Alternative connection 7. - */ -#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) -#define IOCON_PIO_MODE_MASK (0x18U) -#define IOCON_PIO_MODE_SHIFT (3U) -/*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). - * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). - * 0b01..Pull-down. Pull-down resistor enabled. - * 0b10..Pull-up. Pull-up resistor enabled. - * 0b11..Repeater. Repeater mode. - */ -#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) -#define IOCON_PIO_I2CSLEW_MASK (0x20U) -#define IOCON_PIO_I2CSLEW_SHIFT (5U) -/*! I2CSLEW - Controls slew rate of I2C pin. - * 0b0..I2C mode. - * 0b1..GPIO mode. - */ -#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK) -#define IOCON_PIO_INVERT_MASK (0x40U) -#define IOCON_PIO_INVERT_SHIFT (6U) -/*! INVERT - Input polarity. - * 0b0..Disabled. Input function is not inverted. - * 0b1..Enabled. Input is function inverted. - */ -#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) -#define IOCON_PIO_DIGIMODE_MASK (0x80U) -#define IOCON_PIO_DIGIMODE_SHIFT (7U) -/*! DIGIMODE - Select Analog/Digital mode. - * 0b0..Analog mode. - * 0b1..Digital mode. - */ -#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) -#define IOCON_PIO_FILTEROFF_MASK (0x100U) -#define IOCON_PIO_FILTEROFF_SHIFT (8U) -/*! FILTEROFF - Controls input glitch filter. - * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out. - * 0b1..Filter disabled. No input filtering is done. - */ -#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) -#define IOCON_PIO_I2CDRIVE_MASK (0x200U) -#define IOCON_PIO_I2CDRIVE_SHIFT (9U) -/*! I2CDRIVE - Controls the current sink capability of the pin. - * 0b0..Low drive. Output drive sink is 4 mA. This is sufficient for standard and fast mode I2C. - * 0b1..High drive. Output drive sink is 20 mA. This is needed for Fast Mode Plus I 2C. Refer to the appropriate specific device data sheet for details. - */ -#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK) -#define IOCON_PIO_SLEW_MASK (0x200U) -#define IOCON_PIO_SLEW_SHIFT (9U) -/*! SLEW - Driver slew rate. - * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. - * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. - */ -#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) -#define IOCON_PIO_I2CFILTER_MASK (0x400U) -#define IOCON_PIO_I2CFILTER_SHIFT (10U) -/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - * 0b0..Enabled. I2C 50 ns glitch filter enabled. - * 0b1..Disabled. I2C 50 ns glitch filter disabled. - */ -#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) -#define IOCON_PIO_OD_MASK (0x400U) -#define IOCON_PIO_OD_SHIFT (10U) -/*! OD - Controls open-drain mode. - * 0b0..Normal. Normal push-pull output - * 0b1..Open-drain. Simulated open-drain output (high drive disabled). - */ -#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) -/*! @} */ - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT (2U) - -/* The count of IOCON_PIO */ -#define IOCON_PIO_COUNT2 (32U) - - -/*! - * @} - */ /* end of group IOCON_Register_Masks */ - - -/* IOCON - Peripheral instance base addresses */ -/** Peripheral IOCON base address */ -#define IOCON_BASE (0x40001000u) -/** Peripheral IOCON base pointer */ -#define IOCON ((IOCON_Type *)IOCON_BASE) -/** Array initializer of IOCON peripheral base addresses */ -#define IOCON_BASE_ADDRS { IOCON_BASE } -/** Array initializer of IOCON peripheral base pointers */ -#define IOCON_BASE_PTRS { IOCON } - -/*! - * @} - */ /* end of group IOCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- MRT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer - * @{ - */ - -/** MRT - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x10 */ - __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ - __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ - __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ - __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ - } CHANNEL[4]; - uint8_t RESERVED_0[176]; - __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ - __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ - __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ -} MRT_Type; - -/* ---------------------------------------------------------------------------- - -- MRT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup MRT_Register_Masks MRT Register Masks - * @{ - */ - -/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ -/*! @{ */ -#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) -#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) -#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) -#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) -/*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. This bit is write-only. Reading this bit always returns 0. - * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the time interval if the repeat mode is selected. - * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. - */ -#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_INTVAL */ -#define MRT_CHANNEL_INTVAL_COUNT (4U) - -/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ -/*! @{ */ -#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) -#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) -#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_TIMER */ -#define MRT_CHANNEL_TIMER_COUNT (4U) - -/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ -/*! @{ */ -#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) -#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) -/*! INTEN - Enable the TIMERn interrupt. - * 0b0..Disabled. TIMERn interrupt is disabled. - * 0b1..Enabled. TIMERn interrupt is enabled. - */ -#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) -#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) -#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) -/*! MODE - Selects timer mode. - * 0b00..Repeat interrupt mode. - * 0b01..One-shot interrupt mode. - * 0b10..One-shot stall mode. - * 0b11..Reserved. - */ -#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_CTRL */ -#define MRT_CHANNEL_CTRL_COUNT (4U) - -/*! @name CHANNEL_STAT - MRT Status register. */ -/*! @{ */ -#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) -#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) -/*! INTFLAG - Monitors the interrupt flag. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) -#define MRT_CHANNEL_STAT_RUN_MASK (0x2U) -#define MRT_CHANNEL_STAT_RUN_SHIFT (1U) -/*! RUN - Indicates the state of TIMERn. This bit is read-only. - * 0b0..Idle state. TIMERn is stopped. - * 0b1..Running. TIMERn is running. - */ -#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) -#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) -#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) -/*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG register, and affects the use of IDLE_CH. See Idle channel register for details of the two operating modes. - * 0b0..This channel is not in use. - * 0b1..This channel is in use. - */ -#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) -/*! @} */ - -/* The count of MRT_CHANNEL_STAT */ -#define MRT_CHANNEL_STAT_COUNT (4U) - -/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ -/*! @{ */ -#define MRT_MODCFG_NOC_MASK (0xFU) -#define MRT_MODCFG_NOC_SHIFT (0U) -#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) -#define MRT_MODCFG_NOB_MASK (0x1F0U) -#define MRT_MODCFG_NOB_SHIFT (4U) -#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) -#define MRT_MODCFG_MULTITASK_MASK (0x80000000U) -#define MRT_MODCFG_MULTITASK_SHIFT (31U) -/*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. - * 0b0..Hardware status mode. In this mode, the INUSE(n) flags for all channels are reset. - * 0b1..Multi-task mode. - */ -#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) -/*! @} */ - -/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ -/*! @{ */ -#define MRT_IDLE_CH_CHAN_MASK (0xF0U) -#define MRT_IDLE_CH_CHAN_SHIFT (4U) -#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) -/*! @} */ - -/*! @name IRQ_FLAG - Global interrupt flag register */ -/*! @{ */ -#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) -#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) -/*! GFLAG0 - Monitors the interrupt flag of TIMER0. - * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. - * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global interrupt are raised. Writing a 1 to this bit clears the interrupt request. - */ -#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) -#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) -#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) -#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) -#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) -#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) -#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) -#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) -#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) -#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group MRT_Register_Masks */ - - -/* MRT - Peripheral instance base addresses */ -/** Peripheral MRT0 base address */ -#define MRT0_BASE (0x4000D000u) -/** Peripheral MRT0 base pointer */ -#define MRT0 ((MRT_Type *)MRT0_BASE) -/** Array initializer of MRT peripheral base addresses */ -#define MRT_BASE_ADDRS { MRT0_BASE } -/** Array initializer of MRT peripheral base pointers */ -#define MRT_BASE_PTRS { MRT0 } -/** Interrupt vectors for the MRT peripheral type */ -#define MRT_IRQS { MRT0_IRQn } - -/*! - * @} - */ /* end of group MRT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- PINT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer - * @{ - */ - -/** PINT - Register Layout Typedef */ -typedef struct { - __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ - __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ - __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ - __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ - __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ - __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ - __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ - __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ - __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ - __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ - __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ - __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ - __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ -} PINT_Type; - -/* ---------------------------------------------------------------------------- - -- PINT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup PINT_Register_Masks PINT Register Masks - * @{ - */ - -/*! @name ISEL - Pin Interrupt Mode register */ -/*! @{ */ -#define PINT_ISEL_PMODE_MASK (0xFFU) -#define PINT_ISEL_PMODE_SHIFT (0U) -#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) -/*! @} */ - -/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ -/*! @{ */ -#define PINT_IENR_ENRL_MASK (0xFFU) -#define PINT_IENR_ENRL_SHIFT (0U) -#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) -/*! @} */ - -/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ -/*! @{ */ -#define PINT_SIENR_SETENRL_MASK (0xFFU) -#define PINT_SIENR_SETENRL_SHIFT (0U) -#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) -/*! @} */ - -/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ -/*! @{ */ -#define PINT_CIENR_CENRL_MASK (0xFFU) -#define PINT_CIENR_CENRL_SHIFT (0U) -#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) -/*! @} */ - -/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ -/*! @{ */ -#define PINT_IENF_ENAF_MASK (0xFFU) -#define PINT_IENF_ENAF_SHIFT (0U) -#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) -/*! @} */ - -/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ -/*! @{ */ -#define PINT_SIENF_SETENAF_MASK (0xFFU) -#define PINT_SIENF_SETENAF_SHIFT (0U) -#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) -/*! @} */ - -/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ -/*! @{ */ -#define PINT_CIENF_CENAF_MASK (0xFFU) -#define PINT_CIENF_CENAF_SHIFT (0U) -#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) -/*! @} */ - -/*! @name RISE - Pin interrupt rising edge register */ -/*! @{ */ -#define PINT_RISE_RDET_MASK (0xFFU) -#define PINT_RISE_RDET_SHIFT (0U) -#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) -/*! @} */ - -/*! @name FALL - Pin interrupt falling edge register */ -/*! @{ */ -#define PINT_FALL_FDET_MASK (0xFFU) -#define PINT_FALL_FDET_SHIFT (0U) -#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) -/*! @} */ - -/*! @name IST - Pin interrupt status register */ -/*! @{ */ -#define PINT_IST_PSTAT_MASK (0xFFU) -#define PINT_IST_PSTAT_SHIFT (0U) -#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) -/*! @} */ - -/*! @name PMCTRL - Pattern match interrupt control register */ -/*! @{ */ -#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) -#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) -/*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. - * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. - * 0b1..Pattern match. Interrupts are driven in response to pattern matches. - */ -#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) -#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) -#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) -/*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. - * 0b0..Disabled. RXEV output to the CPU is disabled. - * 0b1..Enabled. RXEV output to the CPU is enabled. - */ -#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) -#define PINT_PMCTRL_PMAT_MASK (0xFF000000U) -#define PINT_PMCTRL_PMAT_SHIFT (24U) -#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) -/*! @} */ - -/*! @name PMSRC - Pattern match interrupt bit-slice source register */ -/*! @{ */ -#define PINT_PMSRC_SRC0_MASK (0x700U) -#define PINT_PMSRC_SRC0_SHIFT (8U) -/*! SRC0 - Selects the input source for bit slice 0 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. - */ -#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) -#define PINT_PMSRC_SRC1_MASK (0x3800U) -#define PINT_PMSRC_SRC1_SHIFT (11U) -/*! SRC1 - Selects the input source for bit slice 1 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. - */ -#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) -#define PINT_PMSRC_SRC2_MASK (0x1C000U) -#define PINT_PMSRC_SRC2_SHIFT (14U) -/*! SRC2 - Selects the input source for bit slice 2 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. - */ -#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) -#define PINT_PMSRC_SRC3_MASK (0xE0000U) -#define PINT_PMSRC_SRC3_SHIFT (17U) -/*! SRC3 - Selects the input source for bit slice 3 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. - */ -#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) -#define PINT_PMSRC_SRC4_MASK (0x700000U) -#define PINT_PMSRC_SRC4_SHIFT (20U) -/*! SRC4 - Selects the input source for bit slice 4 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. - */ -#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) -#define PINT_PMSRC_SRC5_MASK (0x3800000U) -#define PINT_PMSRC_SRC5_SHIFT (23U) -/*! SRC5 - Selects the input source for bit slice 5 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. - */ -#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) -#define PINT_PMSRC_SRC6_MASK (0x1C000000U) -#define PINT_PMSRC_SRC6_SHIFT (26U) -/*! SRC6 - Selects the input source for bit slice 6 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. - */ -#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) -#define PINT_PMSRC_SRC7_MASK (0xE0000000U) -#define PINT_PMSRC_SRC7_SHIFT (29U) -/*! SRC7 - Selects the input source for bit slice 7 - * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. - * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. - * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. - * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. - * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. - * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. - * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. - * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. - */ -#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) -/*! @} */ - -/*! @name PMCFG - Pattern match interrupt bit slice configuration register */ -/*! @{ */ -#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) -#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) -/*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. - * 0b0..No effect. Slice 0 is not an endpoint. - * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) -#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) -#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) -/*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. - * 0b0..No effect. Slice 1 is not an endpoint. - * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) -#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) -#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) -/*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. - * 0b0..No effect. Slice 2 is not an endpoint. - * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) -#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) -#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) -/*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. - * 0b0..No effect. Slice 3 is not an endpoint. - * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) -#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) -#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) -/*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. - * 0b0..No effect. Slice 4 is not an endpoint. - * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) -#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) -#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) -/*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. - * 0b0..No effect. Slice 5 is not an endpoint. - * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) -#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) -#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) -/*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. - * 0b0..No effect. Slice 6 is not an endpoint. - * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. - */ -#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) -#define PINT_PMCFG_CFG0_MASK (0x700U) -#define PINT_PMCFG_CFG0_SHIFT (8U) -/*! CFG0 - Specifies the match contribution condition for bit slice 0. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) -#define PINT_PMCFG_CFG1_MASK (0x3800U) -#define PINT_PMCFG_CFG1_SHIFT (11U) -/*! CFG1 - Specifies the match contribution condition for bit slice 1. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) -#define PINT_PMCFG_CFG2_MASK (0x1C000U) -#define PINT_PMCFG_CFG2_SHIFT (14U) -/*! CFG2 - Specifies the match contribution condition for bit slice 2. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) -#define PINT_PMCFG_CFG3_MASK (0xE0000U) -#define PINT_PMCFG_CFG3_SHIFT (17U) -/*! CFG3 - Specifies the match contribution condition for bit slice 3. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) -#define PINT_PMCFG_CFG4_MASK (0x700000U) -#define PINT_PMCFG_CFG4_SHIFT (20U) -/*! CFG4 - Specifies the match contribution condition for bit slice 4. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) -#define PINT_PMCFG_CFG5_MASK (0x3800000U) -#define PINT_PMCFG_CFG5_SHIFT (23U) -/*! CFG5 - Specifies the match contribution condition for bit slice 5. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) -#define PINT_PMCFG_CFG6_MASK (0x1C000000U) -#define PINT_PMCFG_CFG6_SHIFT (26U) -/*! CFG6 - Specifies the match contribution condition for bit slice 6. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) -#define PINT_PMCFG_CFG7_MASK (0xE0000000U) -#define PINT_PMCFG_CFG7_SHIFT (29U) -/*! CFG7 - Specifies the match contribution condition for bit slice 7. - * 0b000..Constant HIGH. This bit slice always contributes to a product term match. - * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input has occurred since the last time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the PMSRC registers are written to. - * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. - * 0b101..Low level. Match occurs when there is a low level on the specified input. - * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). - * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit is cleared after one clock cycle. - */ -#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group PINT_Register_Masks */ - - -/* PINT - Peripheral instance base addresses */ -/** Peripheral PINT base address */ -#define PINT_BASE (0x40004000u) -/** Peripheral PINT base pointer */ -#define PINT ((PINT_Type *)PINT_BASE) -/** Array initializer of PINT peripheral base addresses */ -#define PINT_BASE_ADDRS { PINT_BASE } -/** Array initializer of PINT peripheral base pointers */ -#define PINT_BASE_PTRS { PINT } -/** Interrupt vectors for the PINT peripheral type */ -#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn } - -/*! - * @} - */ /* end of group PINT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- RTC Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer - * @{ - */ - -/** RTC - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ - __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ - __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ - __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ -} RTC_Type; - -/* ---------------------------------------------------------------------------- - -- RTC Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup RTC_Register_Masks RTC Register Masks - * @{ - */ - -/*! @name CTRL - RTC control register */ -/*! @{ */ -#define RTC_CTRL_SWRESET_MASK (0x1U) -#define RTC_CTRL_SWRESET_SHIFT (0U) -/*! SWRESET - Software reset control - * 0b0..Not in reset. The RTC is not held in reset. This bit must be cleared prior to configuring or initiating any operation of the RTC. - * 0b1..In reset. The RTC is held in reset. All register bits within the RTC will be forced to their reset value except the OFD bit. This bit must be cleared before writing to any register in the RTC - including writes to set any of the other bits within this register. Do not attempt to write to any bits of this register at the same time that the reset bit is being cleared. - */ -#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) -#define RTC_CTRL_ALARM1HZ_MASK (0x4U) -#define RTC_CTRL_ALARM1HZ_SHIFT (2U) -/*! ALARM1HZ - RTC 1 Hz timer alarm flag status. - * 0b0..No match. No match has occurred on the 1 Hz RTC timer. Writing a 0 has no effect. - * 0b1..Match. A match condition has occurred on the 1 Hz RTC timer. This flag generates an RTC alarm interrupt request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) -#define RTC_CTRL_WAKE1KHZ_MASK (0x8U) -#define RTC_CTRL_WAKE1KHZ_SHIFT (3U) -/*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. - * 0b0..Run. The RTC 1 kHz timer is running. Writing a 0 has no effect. - * 0b1..Time-out. The 1 kHz high-resolution/wake-up timer has timed out. This flag generates an RTC wake-up interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. - */ -#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) -#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) -#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) -/*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. - * 0b0..Disable. A match on the 1 Hz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) -#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) -#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) -/*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. - */ -#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) -#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) -#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) -/*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz timer is not used. This bit has no effect when the RTC is disabled (bit 7 of this register is 0). - * 0b0..Disable. A match on the 1 kHz RTC timer will not bring the part out of Deep power-down mode. - * 0b1..Enable. The 1 kHz RTC timer is enabled. - */ -#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) -#define RTC_CTRL_RTC_EN_MASK (0x80U) -#define RTC_CTRL_RTC_EN_SHIFT (7U) -/*! RTC_EN - RTC enable. - * 0b0..Disable. The RTC 1 Hz and 1 kHz clocks are shut down and the RTC operation is disabled. This bit should be 0 when writing to load a value in the RTC counter register. - * 0b1..Enable. The 1 Hz RTC clock is running and RTC operation is enabled. This bit must be set to initiate operation of the RTC. The first clock to the RTC counter occurs 1 s after this bit is set. To also enable the high-resolution, 1 kHz clock, set bit 6 in this register. - */ -#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) -#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) -#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) -/*! RTC_OSC_PD - RTC oscillator power-down control. - * 0b0..RTC oscillator is powered-up and can output a clock if a crystal is correctly connected externally - * 0b1..RTC oscillator is powered-down. - */ -#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) -/*! @} */ - -/*! @name MATCH - RTC match register */ -/*! @{ */ -#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) -#define RTC_MATCH_MATVAL_SHIFT (0U) -#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) -/*! @} */ - -/*! @name COUNT - RTC counter register */ -/*! @{ */ -#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) -#define RTC_COUNT_VAL_SHIFT (0U) -#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) -/*! @} */ - -/*! @name WAKE - High-resolution/wake-up timer control register */ -/*! @{ */ -#define RTC_WAKE_VAL_MASK (0xFFFFU) -#define RTC_WAKE_VAL_SHIFT (0U) -#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group RTC_Register_Masks */ - - -/* RTC - Peripheral instance base addresses */ -/** Peripheral RTC base address */ -#define RTC_BASE (0x4002C000u) -/** Peripheral RTC base pointer */ -#define RTC ((RTC_Type *)RTC_BASE) -/** Array initializer of RTC peripheral base addresses */ -#define RTC_BASE_ADDRS { RTC_BASE } -/** Array initializer of RTC peripheral base pointers */ -#define RTC_BASE_PTRS { RTC } -/** Interrupt vectors for the RTC peripheral type */ -#define RTC_IRQS { RTC_IRQn } - -/*! - * @} - */ /* end of group RTC_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SCT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer - * @{ - */ - -/** SCT - Register Layout Typedef */ -typedef struct { - __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ - uint8_t RESERVED_0[40]; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ - __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ - __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ - __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ - __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ - uint8_t RESERVED_1[140]; - __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ - __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ - __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ - __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ - union { /* offset: 0x100 */ - __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ - }; - uint8_t RESERVED_2[216]; - union { /* offset: 0x200 */ - __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ - }; - uint8_t RESERVED_3[216]; - struct { /* offset: 0x300, array step: 0x8 */ - __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ - __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EVENT[10]; - uint8_t RESERVED_4[432]; - struct { /* offset: 0x500, array step: 0x8 */ - __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ - __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ - } OUT[8]; -} SCT_Type; - -/* ---------------------------------------------------------------------------- - -- SCT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SCT_Register_Masks SCT Register Masks - * @{ - */ - -/*! @name CONFIG - SCT configuration register */ -/*! @{ */ -#define SCT_CONFIG_UNIFY_MASK (0x1U) -#define SCT_CONFIG_UNIFY_SHIFT (0U) -/*! UNIFY - SCT operation - * 0b0..The SCT operates as two 16-bit counters named COUNTER_L and COUNTER_H. - * 0b1..The SCT operates as a unified 32-bit counter. - */ -#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) -#define SCT_CONFIG_CLKMODE_MASK (0x6U) -#define SCT_CONFIG_CLKMODE_SHIFT (1U) -/*! CLKMODE - SCT clock mode - * 0b00..System Clock Mode. The system clock clocks the entire SCT module including the counter(s) and counter prescalers. - * 0b01..Sampled System Clock Mode. The system clock clocks the SCT module, but the counter and prescalers are only enabled to count when the designated edge is detected on the input selected by the CKSEL field. The minimum pulse width on the selected clock-gate input is 1 bus clock period. This mode is the high-performance, sampled-clock mode. - * 0b10..SCT Input Clock Mode. The input/edge selected by the CKSEL field clocks the SCT module, including the counters and prescalers, after first being synchronized to the system clock. The minimum pulse width on the clock input is 1 bus clock period. This mode is the low-power, sampled-clock mode. - * 0b11..Asynchronous Mode. The entire SCT module is clocked directly by the input/edge selected by the CKSEL field. In this mode, the SCT outputs are switched synchronously to the SCT input clock - not the system clock. The input clock rate must be at least half the system clock rate and can be the same or faster than the system clock. - */ -#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) -#define SCT_CONFIG_CKSEL_MASK (0x78U) -#define SCT_CONFIG_CKSEL_SHIFT (3U) -/*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent on the CLKMODE bit selection in this register. - * 0b0000..Rising edges on input 0. - * 0b0001..Falling edges on input 0. - * 0b0010..Rising edges on input 1. - * 0b0011..Falling edges on input 1. - * 0b0100..Rising edges on input 2. - * 0b0101..Falling edges on input 2. - * 0b0110..Rising edges on input 3. - * 0b0111..Falling edges on input 3. - */ -#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) -#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) -#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) -#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) -#define SCT_CONFIG_NORELOAD_H_MASK (0x100U) -#define SCT_CONFIG_NORELOAD_H_SHIFT (8U) -#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) -#define SCT_CONFIG_INSYNC_MASK (0x1E00U) -#define SCT_CONFIG_INSYNC_SHIFT (9U) -#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) -#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) -#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) -#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) -#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) -#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) -#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) -/*! @} */ - -/*! @name CTRL - SCT control register */ -/*! @{ */ -#define SCT_CTRL_DOWN_L_MASK (0x1U) -#define SCT_CTRL_DOWN_L_SHIFT (0U) -#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) -#define SCT_CTRL_STOP_L_MASK (0x2U) -#define SCT_CTRL_STOP_L_SHIFT (1U) -#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) -#define SCT_CTRL_HALT_L_MASK (0x4U) -#define SCT_CTRL_HALT_L_SHIFT (2U) -#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) -#define SCT_CTRL_CLRCTR_L_MASK (0x8U) -#define SCT_CTRL_CLRCTR_L_SHIFT (3U) -#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) -#define SCT_CTRL_BIDIR_L_MASK (0x10U) -#define SCT_CTRL_BIDIR_L_SHIFT (4U) -/*! BIDIR_L - L or unified counter direction select - * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. - * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) -#define SCT_CTRL_PRE_L_MASK (0x1FE0U) -#define SCT_CTRL_PRE_L_SHIFT (5U) -#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) -#define SCT_CTRL_DOWN_H_MASK (0x10000U) -#define SCT_CTRL_DOWN_H_SHIFT (16U) -#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) -#define SCT_CTRL_STOP_H_MASK (0x20000U) -#define SCT_CTRL_STOP_H_SHIFT (17U) -#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) -#define SCT_CTRL_HALT_H_MASK (0x40000U) -#define SCT_CTRL_HALT_H_SHIFT (18U) -#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) -#define SCT_CTRL_CLRCTR_H_MASK (0x80000U) -#define SCT_CTRL_CLRCTR_H_SHIFT (19U) -#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) -#define SCT_CTRL_BIDIR_H_MASK (0x100000U) -#define SCT_CTRL_BIDIR_H_SHIFT (20U) -/*! BIDIR_H - Direction select - * 0b0..The H counter counts up to its limit condition, then is cleared to zero. - * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. - */ -#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) -#define SCT_CTRL_PRE_H_MASK (0x1FE00000U) -#define SCT_CTRL_PRE_H_SHIFT (21U) -#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) -/*! @} */ - -/*! @name LIMIT - SCT limit event select register */ -/*! @{ */ -#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) -#define SCT_LIMIT_LIMMSK_L_SHIFT (0U) -#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) -#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) -#define SCT_LIMIT_LIMMSK_H_SHIFT (16U) -#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) -/*! @} */ - -/*! @name HALT - SCT halt event select register */ -/*! @{ */ -#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) -#define SCT_HALT_HALTMSK_L_SHIFT (0U) -#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) -#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) -#define SCT_HALT_HALTMSK_H_SHIFT (16U) -#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) -/*! @} */ - -/*! @name STOP - SCT stop event select register */ -/*! @{ */ -#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) -#define SCT_STOP_STOPMSK_L_SHIFT (0U) -#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) -#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) -#define SCT_STOP_STOPMSK_H_SHIFT (16U) -#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) -/*! @} */ - -/*! @name START - SCT start event select register */ -/*! @{ */ -#define SCT_START_STARTMSK_L_MASK (0xFFFFU) -#define SCT_START_STARTMSK_L_SHIFT (0U) -#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) -#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) -#define SCT_START_STARTMSK_H_SHIFT (16U) -#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) -/*! @} */ - -/*! @name COUNT - SCT counter register */ -/*! @{ */ -#define SCT_COUNT_CTR_L_MASK (0xFFFFU) -#define SCT_COUNT_CTR_L_SHIFT (0U) -#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) -#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) -#define SCT_COUNT_CTR_H_SHIFT (16U) -#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) -/*! @} */ - -/*! @name STATE - SCT state register */ -/*! @{ */ -#define SCT_STATE_STATE_L_MASK (0x1FU) -#define SCT_STATE_STATE_L_SHIFT (0U) -#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) -#define SCT_STATE_STATE_H_MASK (0x1F0000U) -#define SCT_STATE_STATE_H_SHIFT (16U) -#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) -/*! @} */ - -/*! @name INPUT - SCT input register */ -/*! @{ */ -#define SCT_INPUT_AIN0_MASK (0x1U) -#define SCT_INPUT_AIN0_SHIFT (0U) -#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) -#define SCT_INPUT_AIN1_MASK (0x2U) -#define SCT_INPUT_AIN1_SHIFT (1U) -#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) -#define SCT_INPUT_AIN2_MASK (0x4U) -#define SCT_INPUT_AIN2_SHIFT (2U) -#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) -#define SCT_INPUT_AIN3_MASK (0x8U) -#define SCT_INPUT_AIN3_SHIFT (3U) -#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) -#define SCT_INPUT_AIN4_MASK (0x10U) -#define SCT_INPUT_AIN4_SHIFT (4U) -#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) -#define SCT_INPUT_AIN5_MASK (0x20U) -#define SCT_INPUT_AIN5_SHIFT (5U) -#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) -#define SCT_INPUT_AIN6_MASK (0x40U) -#define SCT_INPUT_AIN6_SHIFT (6U) -#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) -#define SCT_INPUT_AIN7_MASK (0x80U) -#define SCT_INPUT_AIN7_SHIFT (7U) -#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) -#define SCT_INPUT_AIN8_MASK (0x100U) -#define SCT_INPUT_AIN8_SHIFT (8U) -#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) -#define SCT_INPUT_AIN9_MASK (0x200U) -#define SCT_INPUT_AIN9_SHIFT (9U) -#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) -#define SCT_INPUT_AIN10_MASK (0x400U) -#define SCT_INPUT_AIN10_SHIFT (10U) -#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) -#define SCT_INPUT_AIN11_MASK (0x800U) -#define SCT_INPUT_AIN11_SHIFT (11U) -#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) -#define SCT_INPUT_AIN12_MASK (0x1000U) -#define SCT_INPUT_AIN12_SHIFT (12U) -#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) -#define SCT_INPUT_AIN13_MASK (0x2000U) -#define SCT_INPUT_AIN13_SHIFT (13U) -#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) -#define SCT_INPUT_AIN14_MASK (0x4000U) -#define SCT_INPUT_AIN14_SHIFT (14U) -#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) -#define SCT_INPUT_AIN15_MASK (0x8000U) -#define SCT_INPUT_AIN15_SHIFT (15U) -#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) -#define SCT_INPUT_SIN0_MASK (0x10000U) -#define SCT_INPUT_SIN0_SHIFT (16U) -#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) -#define SCT_INPUT_SIN1_MASK (0x20000U) -#define SCT_INPUT_SIN1_SHIFT (17U) -#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) -#define SCT_INPUT_SIN2_MASK (0x40000U) -#define SCT_INPUT_SIN2_SHIFT (18U) -#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) -#define SCT_INPUT_SIN3_MASK (0x80000U) -#define SCT_INPUT_SIN3_SHIFT (19U) -#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) -#define SCT_INPUT_SIN4_MASK (0x100000U) -#define SCT_INPUT_SIN4_SHIFT (20U) -#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) -#define SCT_INPUT_SIN5_MASK (0x200000U) -#define SCT_INPUT_SIN5_SHIFT (21U) -#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) -#define SCT_INPUT_SIN6_MASK (0x400000U) -#define SCT_INPUT_SIN6_SHIFT (22U) -#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) -#define SCT_INPUT_SIN7_MASK (0x800000U) -#define SCT_INPUT_SIN7_SHIFT (23U) -#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) -#define SCT_INPUT_SIN8_MASK (0x1000000U) -#define SCT_INPUT_SIN8_SHIFT (24U) -#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) -#define SCT_INPUT_SIN9_MASK (0x2000000U) -#define SCT_INPUT_SIN9_SHIFT (25U) -#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) -#define SCT_INPUT_SIN10_MASK (0x4000000U) -#define SCT_INPUT_SIN10_SHIFT (26U) -#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) -#define SCT_INPUT_SIN11_MASK (0x8000000U) -#define SCT_INPUT_SIN11_SHIFT (27U) -#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) -#define SCT_INPUT_SIN12_MASK (0x10000000U) -#define SCT_INPUT_SIN12_SHIFT (28U) -#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) -#define SCT_INPUT_SIN13_MASK (0x20000000U) -#define SCT_INPUT_SIN13_SHIFT (29U) -#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) -#define SCT_INPUT_SIN14_MASK (0x40000000U) -#define SCT_INPUT_SIN14_SHIFT (30U) -#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) -#define SCT_INPUT_SIN15_MASK (0x80000000U) -#define SCT_INPUT_SIN15_SHIFT (31U) -#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) -/*! @} */ - -/*! @name REGMODE - SCT match/capture mode register */ -/*! @{ */ -#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) -#define SCT_REGMODE_REGMOD_L_SHIFT (0U) -#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) -#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) -#define SCT_REGMODE_REGMOD_H_SHIFT (16U) -#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) -/*! @} */ - -/*! @name OUTPUT - SCT output register */ -/*! @{ */ -#define SCT_OUTPUT_OUT_MASK (0xFFFFU) -#define SCT_OUTPUT_OUT_SHIFT (0U) -#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) -/*! @} */ - -/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ -/*! @{ */ -#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) -#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) -/*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) -#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) -/*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) -#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) -/*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) -#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) -/*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) -#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) -/*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) -#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) -/*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) -#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) -/*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) -#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) -/*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) -#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) -/*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) -#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) -/*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) -#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) -/*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) -#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) -/*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) -/*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) -/*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) -/*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) -#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) -#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) -/*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. - * 0b00..Set and clear do not depend on the direction of any counter. - * 0b01..Set and clear are reversed when counter L or the unified counter is counting down. - * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. - */ -#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) -/*! @} */ - -/*! @name RES - SCT conflict resolution register */ -/*! @{ */ -#define SCT_RES_O0RES_MASK (0x3U) -#define SCT_RES_O0RES_SHIFT (0U) -/*! O0RES - Effect of simultaneous set and clear on output 0. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR0 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR0 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) -#define SCT_RES_O1RES_MASK (0xCU) -#define SCT_RES_O1RES_SHIFT (2U) -/*! O1RES - Effect of simultaneous set and clear on output 1. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR1 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR1 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) -#define SCT_RES_O2RES_MASK (0x30U) -#define SCT_RES_O2RES_SHIFT (4U) -/*! O2RES - Effect of simultaneous set and clear on output 2. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR2 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR2 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) -#define SCT_RES_O3RES_MASK (0xC0U) -#define SCT_RES_O3RES_SHIFT (6U) -/*! O3RES - Effect of simultaneous set and clear on output 3. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR3 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR3 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) -#define SCT_RES_O4RES_MASK (0x300U) -#define SCT_RES_O4RES_SHIFT (8U) -/*! O4RES - Effect of simultaneous set and clear on output 4. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR4 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR4 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) -#define SCT_RES_O5RES_MASK (0xC00U) -#define SCT_RES_O5RES_SHIFT (10U) -/*! O5RES - Effect of simultaneous set and clear on output 5. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR5 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR5 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) -#define SCT_RES_O6RES_MASK (0x3000U) -#define SCT_RES_O6RES_SHIFT (12U) -/*! O6RES - Effect of simultaneous set and clear on output 6. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR6 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR6 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) -#define SCT_RES_O7RES_MASK (0xC000U) -#define SCT_RES_O7RES_SHIFT (14U) -/*! O7RES - Effect of simultaneous set and clear on output 7. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR7 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output n (or set based on the SETCLR7 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) -#define SCT_RES_O8RES_MASK (0x30000U) -#define SCT_RES_O8RES_SHIFT (16U) -/*! O8RES - Effect of simultaneous set and clear on output 8. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR8 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR8 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) -#define SCT_RES_O9RES_MASK (0xC0000U) -#define SCT_RES_O9RES_SHIFT (18U) -/*! O9RES - Effect of simultaneous set and clear on output 9. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR9 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR9 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) -#define SCT_RES_O10RES_MASK (0x300000U) -#define SCT_RES_O10RES_SHIFT (20U) -/*! O10RES - Effect of simultaneous set and clear on output 10. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR10 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR10 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) -#define SCT_RES_O11RES_MASK (0xC00000U) -#define SCT_RES_O11RES_SHIFT (22U) -/*! O11RES - Effect of simultaneous set and clear on output 11. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR11 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR11 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) -#define SCT_RES_O12RES_MASK (0x3000000U) -#define SCT_RES_O12RES_SHIFT (24U) -/*! O12RES - Effect of simultaneous set and clear on output 12. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR12 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR12 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) -#define SCT_RES_O13RES_MASK (0xC000000U) -#define SCT_RES_O13RES_SHIFT (26U) -/*! O13RES - Effect of simultaneous set and clear on output 13. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR13 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR13 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) -#define SCT_RES_O14RES_MASK (0x30000000U) -#define SCT_RES_O14RES_SHIFT (28U) -/*! O14RES - Effect of simultaneous set and clear on output 14. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR14 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR14 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) -#define SCT_RES_O15RES_MASK (0xC0000000U) -#define SCT_RES_O15RES_SHIFT (30U) -/*! O15RES - Effect of simultaneous set and clear on output 15. - * 0b00..No change. - * 0b01..Set output (or clear based on the SETCLR15 field in the OUTPUTDIRCTRL register). - * 0b10..Clear output (or set based on the SETCLR15 field). - * 0b11..Toggle output. - */ -#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) -/*! @} */ - -/*! @name DMA0REQUEST - SCT DMA request 0 register */ -/*! @{ */ -#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) -#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) -#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) -#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) -#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) -#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) -#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) -#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) -#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) -/*! @} */ - -/*! @name DMA1REQUEST - SCT DMA request 1 register */ -/*! @{ */ -#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) -#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) -#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) -#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) -#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) -#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) -#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) -#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) -#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) -/*! @} */ - -/*! @name EVEN - SCT event interrupt enable register */ -/*! @{ */ -#define SCT_EVEN_IEN_MASK (0xFFFFU) -#define SCT_EVEN_IEN_SHIFT (0U) -#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) -/*! @} */ - -/*! @name EVFLAG - SCT event flag register */ -/*! @{ */ -#define SCT_EVFLAG_FLAG_MASK (0xFFFFU) -#define SCT_EVFLAG_FLAG_SHIFT (0U) -#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) -/*! @} */ - -/*! @name CONEN - SCT conflict interrupt enable register */ -/*! @{ */ -#define SCT_CONEN_NCEN_MASK (0xFFFFU) -#define SCT_CONEN_NCEN_SHIFT (0U) -#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) -/*! @} */ - -/*! @name CONFLAG - SCT conflict flag register */ -/*! @{ */ -#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) -#define SCT_CONFLAG_NCFLAG_SHIFT (0U) -#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) -#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) -#define SCT_CONFLAG_BUSERRL_SHIFT (30U) -#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) -#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) -#define SCT_CONFLAG_BUSERRH_SHIFT (31U) -#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) -/*! @} */ - -/*! @name SCTCAP - SCT capture register of capture channel */ -/*! @{ */ -#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) -#define SCT_SCTCAP_CAPn_L_SHIFT (0U) -#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) -#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAP_CAPn_H_SHIFT (16U) -#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTCAP */ -#define SCT_SCTCAP_COUNT (10U) - -/*! @name SCTMATCH - SCT match value register of match channels */ -/*! @{ */ -#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) -#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) -#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) -#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTMATCH */ -#define SCT_SCTMATCH_COUNT (10U) - -/*! @name SCTCAPCTRL - SCT capture control register */ -/*! @{ */ -#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) -#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) -#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) -#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTCAPCTRL */ -#define SCT_SCTCAPCTRL_COUNT (10U) - -/*! @name SCTMATCHREL - SCT match reload value register */ -/*! @{ */ -#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) -#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) -#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) -#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) -/*! @} */ - -/* The count of SCT_SCTMATCHREL */ -#define SCT_SCTMATCHREL_COUNT (10U) - -/*! @name EVENT_STATE - SCT event state register 0 */ -/*! @{ */ -#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) -#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) -/*! @} */ - -/* The count of SCT_EVENT_STATE */ -#define SCT_EVENT_STATE_COUNT (10U) - -/*! @name EVENT_CTRL - SCT event control register 0 */ -/*! @{ */ -#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) -#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) -#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) -#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) -/*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. - * 0b0..Selects the L state and the L match register selected by MATCHSEL. - * 0b1..Selects the H state and the H match register selected by MATCHSEL. - */ -#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) -#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) -/*! OUTSEL - Input/output select - * 0b0..Selects the inputs selected by IOSEL. - * 0b1..Selects the outputs selected by IOSEL. - */ -#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) -#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) -#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) -#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) -/*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state detection, an input must have a minimum pulse width of at least one SCT clock period . - * 0b00..LOW - * 0b01..Rise - * 0b10..Fall - * 0b11..HIGH - */ -#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) -#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) -/*! COMBMODE - Selects how the specified match and I/O condition are used and combined. - * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. - * 0b01..MATCH. Uses the specified match only. - * 0b10..IO. Uses the specified I/O condition only. - * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. - */ -#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) -#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) -#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) -/*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this event is the highest-numbered event occurring for that state. - * 0b0..STATEV value is added into STATE (the carry-out is ignored). - * 0b1..STATEV value is loaded into STATE. - */ -#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) -#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) -#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) -#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) -#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) -#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) -/*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. - * 0b00..Direction independent. This event is triggered regardless of the count direction. - * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. - * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. - */ -#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) -/*! @} */ - -/* The count of SCT_EVENT_CTRL */ -#define SCT_EVENT_CTRL_COUNT (10U) - -/*! @name OUT_SET - SCT output 0 set register */ -/*! @{ */ -#define SCT_OUT_SET_SET_MASK (0xFFFFU) -#define SCT_OUT_SET_SET_SHIFT (0U) -#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) -/*! @} */ - -/* The count of SCT_OUT_SET */ -#define SCT_OUT_SET_COUNT (8U) - -/*! @name OUT_CLR - SCT output 0 clear register */ -/*! @{ */ -#define SCT_OUT_CLR_CLR_MASK (0xFFFFU) -#define SCT_OUT_CLR_CLR_SHIFT (0U) -#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) -/*! @} */ - -/* The count of SCT_OUT_CLR */ -#define SCT_OUT_CLR_COUNT (8U) - - -/*! - * @} - */ /* end of group SCT_Register_Masks */ - - -/* SCT - Peripheral instance base addresses */ -/** Peripheral SCT0 base address */ -#define SCT0_BASE (0x40085000u) -/** Peripheral SCT0 base pointer */ -#define SCT0 ((SCT_Type *)SCT0_BASE) -/** Array initializer of SCT peripheral base addresses */ -#define SCT_BASE_ADDRS { SCT0_BASE } -/** Array initializer of SCT peripheral base pointers */ -#define SCT_BASE_PTRS { SCT0 } -/** Interrupt vectors for the SCT peripheral type */ -#define SCT_IRQS { SCT0_IRQn } - -/*! - * @} - */ /* end of group SCT_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SPI Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer - * @{ - */ - -/** SPI - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1024]; - __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ - __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ - __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ - __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ - __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ - uint8_t RESERVED_1[16]; - __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ - __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ - uint8_t RESERVED_2[2516]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_3[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_4[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_6[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_7[440]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} SPI_Type; - -/* ---------------------------------------------------------------------------- - -- SPI Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SPI_Register_Masks SPI Register Masks - * @{ - */ - -/*! @name CFG - SPI Configuration register */ -/*! @{ */ -#define SPI_CFG_ENABLE_MASK (0x1U) -#define SPI_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - SPI enable. - * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. - * 0b1..Enabled. The SPI is enabled for operation. - */ -#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) -#define SPI_CFG_MASTER_MASK (0x4U) -#define SPI_CFG_MASTER_SHIFT (2U) -/*! MASTER - Master mode select. - * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. - * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. - */ -#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) -#define SPI_CFG_LSBF_MASK (0x8U) -#define SPI_CFG_LSBF_SHIFT (3U) -/*! LSBF - LSB First mode enable. - * 0b0..Standard. Data is transmitted and received in standard MSB first order. - * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). - */ -#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) -#define SPI_CFG_CPHA_MASK (0x10U) -#define SPI_CFG_CPHA_SHIFT (4U) -/*! CPHA - Clock Phase select. - * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is changed on the following edge. - * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock changes away from the rest state). Data is captured on the following edge. - */ -#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) -#define SPI_CFG_CPOL_MASK (0x20U) -#define SPI_CFG_CPOL_SHIFT (5U) -/*! CPOL - Clock Polarity select. - * 0b0..Low. The rest state of the clock (between transfers) is low. - * 0b1..High. The rest state of the clock (between transfers) is high. - */ -#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) -#define SPI_CFG_LOOP_MASK (0x80U) -#define SPI_CFG_LOOP_SHIFT (7U) -/*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit and receive data connected together to allow simple software testing. - * 0b0..Disabled. - * 0b1..Enabled. - */ -#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) -#define SPI_CFG_SPOL0_MASK (0x100U) -#define SPI_CFG_SPOL0_SHIFT (8U) -/*! SPOL0 - SSEL0 Polarity select. - * 0b0..Low. The SSEL0 pin is active low. - * 0b1..High. The SSEL0 pin is active high. - */ -#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) -#define SPI_CFG_SPOL1_MASK (0x200U) -#define SPI_CFG_SPOL1_SHIFT (9U) -/*! SPOL1 - SSEL1 Polarity select. - * 0b0..Low. The SSEL1 pin is active low. - * 0b1..High. The SSEL1 pin is active high. - */ -#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) -#define SPI_CFG_SPOL2_MASK (0x400U) -#define SPI_CFG_SPOL2_SHIFT (10U) -/*! SPOL2 - SSEL2 Polarity select. - * 0b0..Low. The SSEL2 pin is active low. - * 0b1..High. The SSEL2 pin is active high. - */ -#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) -#define SPI_CFG_SPOL3_MASK (0x800U) -#define SPI_CFG_SPOL3_SHIFT (11U) -/*! SPOL3 - SSEL3 Polarity select. - * 0b0..Low. The SSEL3 pin is active low. - * 0b1..High. The SSEL3 pin is active high. - */ -#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) -/*! @} */ - -/*! @name DLY - SPI Delay register */ -/*! @{ */ -#define SPI_DLY_PRE_DELAY_MASK (0xFU) -#define SPI_DLY_PRE_DELAY_SHIFT (0U) -#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) -#define SPI_DLY_POST_DELAY_MASK (0xF0U) -#define SPI_DLY_POST_DELAY_SHIFT (4U) -#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) -#define SPI_DLY_FRAME_DELAY_MASK (0xF00U) -#define SPI_DLY_FRAME_DELAY_SHIFT (8U) -#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) -#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) -#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) -#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) -/*! @} */ - -/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ -/*! @{ */ -#define SPI_STAT_SSA_MASK (0x10U) -#define SPI_STAT_SSA_SHIFT (4U) -#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) -#define SPI_STAT_SSD_MASK (0x20U) -#define SPI_STAT_SSD_SHIFT (5U) -#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) -#define SPI_STAT_STALLED_MASK (0x40U) -#define SPI_STAT_STALLED_SHIFT (6U) -#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) -#define SPI_STAT_ENDTRANSFER_MASK (0x80U) -#define SPI_STAT_ENDTRANSFER_SHIFT (7U) -#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) -#define SPI_STAT_MSTIDLE_MASK (0x100U) -#define SPI_STAT_MSTIDLE_SHIFT (8U) -#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ -#define SPI_INTENSET_SSAEN_MASK (0x10U) -#define SPI_INTENSET_SSAEN_SHIFT (4U) -/*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. - * 0b0..Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted. - * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. - */ -#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) -#define SPI_INTENSET_SSDEN_MASK (0x20U) -#define SPI_INTENSET_SSDEN_SHIFT (5U) -/*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. - * 0b0..Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted. - * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. - */ -#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) -#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) -#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) -/*! MSTIDLEEN - Master idle interrupt enable. - * 0b0..No interrupt will be generated when the SPI master function is idle. - * 0b1..An interrupt will be generated when the SPI master function is fully idle. - */ -#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) -/*! @} */ - -/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ -/*! @{ */ -#define SPI_INTENCLR_SSAEN_MASK (0x10U) -#define SPI_INTENCLR_SSAEN_SHIFT (4U) -#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) -#define SPI_INTENCLR_SSDEN_MASK (0x20U) -#define SPI_INTENCLR_SSDEN_SHIFT (5U) -#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) -#define SPI_INTENCLR_MSTIDLE_MASK (0x100U) -#define SPI_INTENCLR_MSTIDLE_SHIFT (8U) -#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) -/*! @} */ - -/*! @name DIV - SPI clock Divider */ -/*! @{ */ -#define SPI_DIV_DIVVAL_MASK (0xFFFFU) -#define SPI_DIV_DIVVAL_SHIFT (0U) -#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - SPI Interrupt Status */ -/*! @{ */ -#define SPI_INTSTAT_SSA_MASK (0x10U) -#define SPI_INTSTAT_SSA_SHIFT (4U) -#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) -#define SPI_INTSTAT_SSD_MASK (0x20U) -#define SPI_INTSTAT_SSD_SHIFT (5U) -#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) -#define SPI_INTSTAT_MSTIDLE_MASK (0x100U) -#define SPI_INTSTAT_MSTIDLE_SHIFT (8U) -#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define SPI_FIFOCFG_ENABLETX_MASK (0x1U) -#define SPI_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) -#define SPI_FIFOCFG_ENABLERX_MASK (0x2U) -#define SPI_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) -#define SPI_FIFOCFG_SIZE_MASK (0x30U) -#define SPI_FIFOCFG_SIZE_SHIFT (4U) -#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) -#define SPI_FIFOCFG_DMATX_MASK (0x1000U) -#define SPI_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) -#define SPI_FIFOCFG_DMARX_MASK (0x2000U) -#define SPI_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) -#define SPI_FIFOCFG_WAKETX_MASK (0x4000U) -#define SPI_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) -#define SPI_FIFOCFG_WAKERX_MASK (0x8000U) -#define SPI_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) -#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) -#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) -#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define SPI_FIFOSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) -#define SPI_FIFOSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) -#define SPI_FIFOSTAT_PERINT_MASK (0x8U) -#define SPI_FIFOSTAT_PERINT_SHIFT (3U) -#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) -#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) -#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) -#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) -#define SPI_FIFOSTAT_RXFULL_MASK (0x80U) -#define SPI_FIFOSTAT_RXFULL_SHIFT (7U) -#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) -#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define SPI_FIFOSTAT_TXLVL_SHIFT (8U) -#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) -#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define SPI_FIFOSTAT_RXLVL_SHIFT (16U) -#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) -#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) -#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) -#define SPI_FIFOTRIG_TXLVL_SHIFT (8U) -#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) -#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define SPI_FIFOTRIG_RXLVL_SHIFT (16U) -#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define SPI_FIFOINTENSET_TXERR_MASK (0x1U) -#define SPI_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) -#define SPI_FIFOINTENSET_RXERR_MASK (0x2U) -#define SPI_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) -#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) -#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) -#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) -#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) -#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) -#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) -#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) -#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) -#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) -#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) -#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) -#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) -#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) -#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) -#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) -#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) -#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) -#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) -#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) -#define SPI_FIFOWR_TXDATA_SHIFT (0U) -#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) -#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) -#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) -/*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL0 asserted. - * 0b1..SSEL0 not asserted. - */ -#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) -#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) -#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) -/*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL1 asserted. - * 0b1..SSEL1 not asserted. - */ -#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) -#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) -#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) -/*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL2 asserted. - * 0b1..SSEL2 not asserted. - */ -#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) -#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) -#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) -/*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. - * 0b0..SSEL3 asserted. - * 0b1..SSEL3 not asserted. - */ -#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) -#define SPI_FIFOWR_EOT_MASK (0x100000U) -#define SPI_FIFOWR_EOT_SHIFT (20U) -/*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain so far at least the time specified by the Transfer_delay value in the DLY register. - * 0b0..SSEL not deasserted. This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. - * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. - */ -#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) -#define SPI_FIFOWR_EOF_MASK (0x200000U) -#define SPI_FIFOWR_EOF_SHIFT (21U) -/*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value in the DLY register. The end of a frame may not be particularly meaningful if the Frame_delay value = 0. This control can be used as part of the support for frame lengths greater than 16 bits. - * 0b0..Data not EOF. This piece of data transmitted is not treated as the end of a frame. - * 0b1..Data EOF. This piece of data is treated as the end of a frame, causing the Frame_delay time to be inserted before subsequent data is transmitted. - */ -#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) -#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) -#define SPI_FIFOWR_RXIGNORE_SHIFT (22U) -/*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to read unneeded data from the receiver. Setting this bit simplifies the transmit process and can be used with the DMA. - * 0b0..Read received data. Received data must be read in order to allow transmission to progress. SPI transmit will halt when the receive data FIFO is full. In slave mode, an overrun error will occur if received data is not read before new data is received. - * 0b1..Ignore received data. Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. - */ -#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) -#define SPI_FIFOWR_LEN_MASK (0xF000000U) -#define SPI_FIFOWR_LEN_SHIFT (24U) -#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define SPI_FIFORD_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORD_RXDATA_SHIFT (0U) -#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) -#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) -#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) -#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) -#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) -#define SPI_FIFORD_SOT_MASK (0x100000U) -#define SPI_FIFORD_SOT_SHIFT (20U) -#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) -#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) -#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) -#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) -#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) -#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) -#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) -#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) -#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) -#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) -#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) -#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) -#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) -#define SPI_FIFORDNOPOP_SOT_SHIFT (20U) -#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ -#define SPI_ID_APERTURE_MASK (0xFFU) -#define SPI_ID_APERTURE_SHIFT (0U) -#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) -#define SPI_ID_MINOR_REV_MASK (0xF00U) -#define SPI_ID_MINOR_REV_SHIFT (8U) -#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) -#define SPI_ID_MAJOR_REV_MASK (0xF000U) -#define SPI_ID_MAJOR_REV_SHIFT (12U) -#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) -#define SPI_ID_ID_MASK (0xFFFF0000U) -#define SPI_ID_ID_SHIFT (16U) -#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SPI_Register_Masks */ - - -/* SPI - Peripheral instance base addresses */ -/** Peripheral SPI0 base address */ -#define SPI0_BASE (0x40086000u) -/** Peripheral SPI0 base pointer */ -#define SPI0 ((SPI_Type *)SPI0_BASE) -/** Peripheral SPI1 base address */ -#define SPI1_BASE (0x40087000u) -/** Peripheral SPI1 base pointer */ -#define SPI1 ((SPI_Type *)SPI1_BASE) -/** Peripheral SPI2 base address */ -#define SPI2_BASE (0x40088000u) -/** Peripheral SPI2 base pointer */ -#define SPI2 ((SPI_Type *)SPI2_BASE) -/** Peripheral SPI3 base address */ -#define SPI3_BASE (0x40089000u) -/** Peripheral SPI3 base pointer */ -#define SPI3 ((SPI_Type *)SPI3_BASE) -/** Peripheral SPI4 base address */ -#define SPI4_BASE (0x4008A000u) -/** Peripheral SPI4 base pointer */ -#define SPI4 ((SPI_Type *)SPI4_BASE) -/** Peripheral SPI5 base address */ -#define SPI5_BASE (0x40096000u) -/** Peripheral SPI5 base pointer */ -#define SPI5 ((SPI_Type *)SPI5_BASE) -/** Peripheral SPI6 base address */ -#define SPI6_BASE (0x40097000u) -/** Peripheral SPI6 base pointer */ -#define SPI6 ((SPI_Type *)SPI6_BASE) -/** Peripheral SPI7 base address */ -#define SPI7_BASE (0x40098000u) -/** Peripheral SPI7 base pointer */ -#define SPI7 ((SPI_Type *)SPI7_BASE) -/** Array initializer of SPI peripheral base addresses */ -#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE } -/** Array initializer of SPI peripheral base pointers */ -#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7 } -/** Interrupt vectors for the SPI peripheral type */ -#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group SPI_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- SYSCON Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer - * @{ - */ - -/** SYSCON - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[16]; - __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ - uint8_t RESERVED_1[44]; - __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */ - uint8_t RESERVED_2[4]; - __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ - __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */ - uint8_t RESERVED_3[112]; - __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_4[8]; - __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */ - uint8_t RESERVED_5[40]; - __IO uint32_t PRESETCTRL[2]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_6[24]; - __O uint32_t PRESETCTRLSET[2]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */ - uint8_t RESERVED_7[24]; - __O uint32_t PRESETCTRLCLR[2]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */ - uint8_t RESERVED_8[168]; - __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */ - uint8_t RESERVED_9[12]; - __IO uint32_t AHBCLKCTRL[2]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */ - uint8_t RESERVED_10[24]; - __O uint32_t AHBCLKCTRLSET[2]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */ - uint8_t RESERVED_11[24]; - __O uint32_t AHBCLKCTRLCLR[2]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */ - uint8_t RESERVED_12[56]; - __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ - __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ - __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */ - uint8_t RESERVED_13[4]; - __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */ - uint8_t RESERVED_14[16]; - __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ - __IO uint32_t USBCLKSEL; /**< USB clock source select, offset: 0x2A8 */ - uint8_t RESERVED_15[4]; - __IO uint32_t FXCOMCLKSEL[8]; /**< Flexcomm0 clock source select..Flexcomm7 clock source select, array offset: 0x2B0, array step: 0x4 */ - uint8_t RESERVED_16[16]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ - uint8_t RESERVED_17[4]; - __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */ - uint8_t RESERVED_18[20]; - __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */ - uint8_t RESERVED_19[124]; - __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */ - __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ - uint8_t RESERVED_20[12]; - __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ - __IO uint32_t USBCLKDIV; /**< USB clock divider, offset: 0x398 */ - uint8_t RESERVED_21[4]; - __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */ - uint8_t RESERVED_22[8]; - __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_23[80]; - __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */ - uint8_t RESERVED_24[8]; - __IO uint32_t USBCLKCTRL; /**< USB clock control, offset: 0x40C */ - __IO uint32_t USBCLKSTAT; /**< USB clock status, offset: 0x410 */ - uint8_t RESERVED_25[4]; - __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */ - uint8_t RESERVED_26[4]; - __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */ - uint8_t RESERVED_27[220]; - __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */ - uint8_t RESERVED_28[4]; - __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */ - __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */ - uint8_t RESERVED_29[112]; - __IO uint32_t SYSPLLCTRL; /**< PLL control, offset: 0x580 */ - __I uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */ - __IO uint32_t SYSPLLNDEC; /**< PLL N decoder, offset: 0x588 */ - __IO uint32_t SYSPLLPDEC; /**< PLL P decoder, offset: 0x58C */ - __IO uint32_t SYSPLLSSCTRL0; /**< PLL spread spectrum control 0, offset: 0x590 */ - __IO uint32_t SYSPLLSSCTRL1; /**< PLL spread spectrum control 1, offset: 0x594 */ - uint8_t RESERVED_30[104]; - __IO uint32_t PDSLEEPCFG[2]; /**< Sleep configuration register n, array offset: 0x600, array step: 0x4 */ - uint8_t RESERVED_31[8]; - __IO uint32_t PDRUNCFG[1]; /**< Power configuration register 0, array offset: 0x610, array step: 0x4 */ - uint8_t RESERVED_32[12]; - __O uint32_t PDRUNCFGSET[1]; /**< Set bits in PDRUNCFGn, array offset: 0x620, array step: 0x4 */ - uint8_t RESERVED_33[12]; - __O uint32_t PDRUNCFGCLR[1]; /**< Clear bits in PDRUNCFGn, array offset: 0x630, array step: 0x4 */ - uint8_t RESERVED_34[76]; - __IO uint32_t STARTER[1]; /**< Start logic n wake-up enable register, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_35[28]; - __O uint32_t STARTERSET[1]; /**< Set bits in STARTERn, array offset: 0x6A0, array step: 0x4 */ - uint8_t RESERVED_36[28]; - __O uint32_t STARTERCLR[1]; /**< Clear bits in STARTERn, array offset: 0x6C0, array step: 0x4 */ - uint8_t RESERVED_37[188]; - __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ - uint8_t RESERVED_38[2160]; - __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */ - __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */ - __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */ - uint8_t RESERVED_39[127044]; - __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */ -} SYSCON_Type; - -/* ---------------------------------------------------------------------------- - -- SYSCON Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SYSCON_Register_Masks SYSCON Register Masks - * @{ - */ - -/*! @name AHBMATPRIO - AHB multilayer matrix priority control */ -/*! @{ */ -#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) -#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) -#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U) -#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK) -#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U) -#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK) -#define SYSCON_AHBMATPRIO_PRI_M0_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_M0_SHIFT (6U) -#define SYSCON_AHBMATPRIO_PRI_M0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_M0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_M0_MASK) -#define SYSCON_AHBMATPRIO_PRI_USB_MASK (0x300U) -#define SYSCON_AHBMATPRIO_PRI_USB_SHIFT (8U) -#define SYSCON_AHBMATPRIO_PRI_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_MASK) -#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0xC00U) -#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (10U) -#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) -/*! @} */ - -/*! @name SYSTCKCAL - System tick counter calibration */ -/*! @{ */ -#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) -#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) -#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U) -#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK) -#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) -#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) -/*! @} */ - -/*! @name NMISRC - NMI Source Select */ -/*! @{ */ -#define SYSCON_NMISRC_IRQM4_MASK (0x3FU) -#define SYSCON_NMISRC_IRQM4_SHIFT (0U) -#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) -#define SYSCON_NMISRC_IRQM0_MASK (0x3F00U) -#define SYSCON_NMISRC_IRQM0_SHIFT (8U) -#define SYSCON_NMISRC_IRQM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM0_SHIFT)) & SYSCON_NMISRC_IRQM0_MASK) -#define SYSCON_NMISRC_NMIENM0_MASK (0x40000000U) -#define SYSCON_NMISRC_NMIENM0_SHIFT (30U) -#define SYSCON_NMISRC_NMIENM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM0_SHIFT)) & SYSCON_NMISRC_NMIENM0_MASK) -#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) -#define SYSCON_NMISRC_NMIENM4_SHIFT (31U) -#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) -/*! @} */ - -/*! @name ASYNCAPBCTRL - Asynchronous APB Control */ -/*! @{ */ -#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) -#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) -/*! ENABLE - Enables the asynchronous APB bridge and subsystem. - * 0b0..Disabled. Asynchronous APB bridge is disabled. - * 0b1..Enabled. Asynchronous APB bridge is enabled. - */ -#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) -/*! @} */ - -/*! @name PIOPORCAP - POR captured value of port n */ -/*! @{ */ -#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) -#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) -#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) -/*! @} */ - -/* The count of SYSCON_PIOPORCAP */ -#define SYSCON_PIOPORCAP_COUNT (2U) - -/*! @name PIORESCAP - Reset captured value of port n */ -/*! @{ */ -#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) -#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) -#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) -/*! @} */ - -/* The count of SYSCON_PIORESCAP */ -#define SYSCON_PIORESCAP_COUNT (2U) - -/*! @name PRESETCTRL - Peripheral reset control n */ -/*! @{ */ -#define SYSCON_PRESETCTRL_MRT0_RST_MASK (0x1U) -#define SYSCON_PRESETCTRL_MRT0_RST_SHIFT (0U) -#define SYSCON_PRESETCTRL_MRT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT0_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT0_RST_MASK) -#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U) -#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK) -#define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U) -#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U) -#define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK) -#define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U) -#define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U) -#define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK) -#define SYSCON_PRESETCTRL_UTICK0_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL_UTICK0_RST_SHIFT (10U) -#define SYSCON_PRESETCTRL_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK0_RST_MASK) -#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) -#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) -#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) -#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) -#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) -#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) -#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U) -#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK) -#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U) -#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U) -#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK) -#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U) -#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U) -#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK) -#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U) -#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK) -#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U) -#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U) -#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK) -#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U) -#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U) -#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK) -#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U) -#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U) -#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK) -#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U) -#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK) -#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) -#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) -#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) -#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) -#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) -#define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) -#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) -#define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) -#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U) -#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U) -#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK) -#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U) -#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U) -#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK) -#define SYSCON_PRESETCTRL_USB0_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL_USB0_RST_SHIFT (25U) -#define SYSCON_PRESETCTRL_USB0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) -#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) -#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) -#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) -#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) -#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) -#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) -#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRL */ -#define SYSCON_PRESETCTRL_COUNT (2U) - -/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ -/*! @{ */ -#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) -#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLSET */ -#define SYSCON_PRESETCTRLSET_COUNT (2U) - -/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ -/*! @{ */ -#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) -#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_PRESETCTRLCLR */ -#define SYSCON_PRESETCTRLCLR_COUNT (2U) - -/*! @name SYSRSTSTAT - System reset status register */ -/*! @{ */ -#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) -#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) -/*! POR - POR reset status - * 0b0..No POR detected - * 0b1..POR detected. Writing a one clears this reset. - */ -#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) -#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) -#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) -/*! EXTRST - Status of the external RESET pin. External reset status - * 0b0..No reset event detected. - * 0b1..Reset detected. Writing a one clears this reset. - */ -#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) -#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) -#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) -/*! WDT - Status of the Watchdog reset - * 0b0..No WDT reset detected - * 0b1..WDT reset detected. Writing a one clears this reset. - */ -#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) -#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) -#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) -/*! BOD - Status of the Brown-out detect reset - * 0b0..No BOD reset detected - * 0b1..BOD reset detected. Writing a one clears this reset. - */ -#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) -#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) -#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) -/*! SYSRST - Status of the software system reset - * 0b0..No System reset detected - * 0b1..System reset detected. Writing a one clears this reset. - */ -#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) -/*! @} */ - -/*! @name AHBCLKCTRL - AHB Clock control n */ -/*! @{ */ -#define SYSCON_AHBCLKCTRL_MRT0_MASK (0x1U) -#define SYSCON_AHBCLKCTRL_MRT0_SHIFT (0U) -#define SYSCON_AHBCLKCTRL_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT0_SHIFT)) & SYSCON_AHBCLKCTRL_MRT0_MASK) -#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U) -#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U) -#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK) -#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U) -#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U) -#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK) -#define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U) -#define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U) -#define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK) -#define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U) -#define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U) -#define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK) -#define SYSCON_AHBCLKCTRL_UTICK0_MASK (0x400U) -#define SYSCON_AHBCLKCTRL_UTICK0_SHIFT (10U) -#define SYSCON_AHBCLKCTRL_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK0_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK) -#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U) -#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U) -#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) -#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) -#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) -#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) -#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) -#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) -#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U) -#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U) -#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U) -#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK) -#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) -#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) -#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) -#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) -#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) -#define SYSCON_AHBCLKCTRL_DMA0_MASK (0x100000U) -#define SYSCON_AHBCLKCTRL_DMA0_SHIFT (20U) -#define SYSCON_AHBCLKCTRL_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL_DMA0_MASK) -#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U) -#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U) -#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK) -#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U) -#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U) -#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK) -#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U) -#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U) -#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK) -#define SYSCON_AHBCLKCTRL_USB0_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL_USB0_SHIFT (25U) -#define SYSCON_AHBCLKCTRL_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0_SHIFT)) & SYSCON_AHBCLKCTRL_USB0_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U) -#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U) -#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK) -#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) -#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) -#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) -#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) -#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRL */ -#define SYSCON_AHBCLKCTRL_COUNT (2U) - -/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) -#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLSET */ -#define SYSCON_AHBCLKCTRLSET_COUNT (2U) - -/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ -/*! @{ */ -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) -#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_AHBCLKCTRLCLR */ -#define SYSCON_AHBCLKCTRLCLR_COUNT (2U) - -/*! @name MAINCLKSELA - Main clock source select A */ -/*! @{ */ -#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) -#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) -/*! SEL - Clock source for main clock source selector A - * 0b00..FRO 12 MHz (fro_12m) - * 0b01..CLKIN (clk_in) - * 0b10..Watchdog oscillator (wdt_clk) - * 0b11..FRO 96 or 48 MHz (fro_hf) - */ -#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) -/*! @} */ - -/*! @name MAINCLKSELB - Main clock source select B */ -/*! @{ */ -#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) -#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) -/*! SEL - Clock source for main clock source selector B. Selects the clock source for the main clock. - * 0b00..MAINCLKSELA. Use the clock source selected in MAINCLKSELA register. - * 0b01..Reserved setting - * 0b10..System PLL output (pll_clk) - * 0b11..RTC oscillator 32 kHz output (32k_clk) - */ -#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) -/*! @} */ - -/*! @name CLKOUTSELA - CLKOUT clock source select A */ -/*! @{ */ -#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) -#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) -/*! SEL - CLKOUT clock source selection - * 0b000..Main clock (main_clk) - * 0b001..CLKIN (clk_in) - * 0b010..Watchdog oscillator (wdt_clk) - * 0b011..FRO 96 or 48 MHz (fro_hf) - * 0b100..PLL output (pll_clk) - * 0b101..FRO 12 MHz (fro_12m) - * 0b110..RTC oscillator 32 kHz output (32k_clk) - * 0b111..None, this may be selected in order to reduce power when no output is needed. - */ -#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) -/*! @} */ - -/*! @name SYSPLLCLKSEL - PLL clock source select */ -/*! @{ */ -#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) -#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) -/*! SEL - System PLL clock source selection - * 0b000..FRO 12 MHz (fro_12m) - * 0b001..CLKIN (clk_in) - * 0b011..RTC 32 kHz clock (32k_clk) - * 0b111..None, this may be selected in order to reduce power when no output is needed. - */ -#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name ADCCLKSEL - ADC clock source select */ -/*! @{ */ -#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) -#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) -/*! SEL - ADC clock source selection - * 0b000..Main clock (main_clk) - * 0b001..System PLL output (pll_clk) - * 0b010..FRO 96 or 48 MHz (fro_hf) - * 0b111..None, this may be selected in order to reduce power when no output is needed. - */ -#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name USBCLKSEL - USB clock source select */ -/*! @{ */ -#define SYSCON_USBCLKSEL_SEL_MASK (0x7U) -#define SYSCON_USBCLKSEL_SEL_SHIFT (0U) -/*! SEL - USB device clock source selection - * 0b000..FRO 96 or 48 MHz (fro_hf) - * 0b001..System PLL output (pll_clk) - * 0b010..Main clock (main_clk) - * 0b111..None, this may be selected in order to reduce power when no output is needed. - */ -#define SYSCON_USBCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSEL_SEL_SHIFT)) & SYSCON_USBCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FXCOMCLKSEL - Flexcomm0 clock source select..Flexcomm7 clock source select */ -/*! @{ */ -#define SYSCON_FXCOMCLKSEL_SEL_MASK (0x7U) -#define SYSCON_FXCOMCLKSEL_SEL_SHIFT (0U) -/*! SEL - Flexcomm clock source selection. One per Flexcomm. - * 0b000..FRO 12 MHz (fro_12m) - * 0b001..FRO 96 or 48 MHz (fro_hf) - * 0b010..System PLL output (pll_clk) - * 0b011..MCLK pin input, when selected in IOCON (mclk_in) - * 0b100..FRG clock, the output of the fractional rate generator (frg_clk) - * 0b111..None, this may be selected in order to reduce power when no output is needed. - */ -#define SYSCON_FXCOMCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FXCOMCLKSEL_SEL_SHIFT)) & SYSCON_FXCOMCLKSEL_SEL_MASK) -/*! @} */ - -/* The count of SYSCON_FXCOMCLKSEL */ -#define SYSCON_FXCOMCLKSEL_COUNT (8U) - -/*! @name MCLKCLKSEL - MCLK clock source select */ -/*! @{ */ -#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) -#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) -/*! SEL - MCLK source select. This may be used by Flexcomms that support I2S, and/or by the digital microphone subsystem. - * 0b000..FRO 96 or 48 MHz (fro_hf) - * 0b001..System PLL output (pll_clk) - * 0b010..Main clock (main_clk) - * 0b111..None, this may be selected in order to reduce power when no output is needed. - */ -#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ -/*! @{ */ -#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) -#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) -/*! SEL - Fractional Rate Generator clock source select. - * 0b000..Main clock (main_clk) - * 0b001..System PLL output (pll_clk) - * 0b010..FRO 12 MHz (fro_12m) - * 0b011..FRO 96 or 48 MHz (fro_hf) - * 0b111..None, this may be selected in order to reduce power when no output is needed. - */ -#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) -/*! @} */ - -/*! @name SYSTICKCLKDIV - SYSTICK clock divider */ -/*! @{ */ -#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) -#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) -/*! @} */ - -/*! @name AHBCLKDIV - AHB clock divider */ -/*! @{ */ -#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) -#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) -/*! @} */ - -/*! @name CLKOUTDIV - CLKOUT clock divider */ -/*! @{ */ -#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) -#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) -#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) -/*! @} */ - -/*! @name ADCCLKDIV - ADC clock divider */ -/*! @{ */ -#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) -#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) -/*! @} */ - -/*! @name USBCLKDIV - USB clock divider */ -/*! @{ */ -#define SYSCON_USBCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_USBCLKDIV_DIV_SHIFT (0U) -#define SYSCON_USBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKDIV_DIV_SHIFT)) & SYSCON_USBCLKDIV_DIV_MASK) -/*! @} */ - -/*! @name FRGCTRL - Fractional rate divider */ -/*! @{ */ -#define SYSCON_FRGCTRL_DIV_MASK (0xFFU) -#define SYSCON_FRGCTRL_DIV_SHIFT (0U) -#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) -#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) -#define SYSCON_FRGCTRL_MULT_SHIFT (8U) -#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) -/*! @} */ - -/*! @name MCLKDIV - I2S MCLK clock divider */ -/*! @{ */ -#define SYSCON_MCLKDIV_DIV_MASK (0xFFU) -#define SYSCON_MCLKDIV_DIV_SHIFT (0U) -#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) -/*! @} */ - -/*! @name FLASHCFG - Flash wait states configuration */ -/*! @{ */ -#define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) -#define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) -/*! FETCHCFG - Instruction fetch configuration. This field determines how flash accelerator buffers are used for instruction fetches. - * 0b00..Instruction fetches from flash are not buffered. Every fetch request from the CPU results in a read of the flash memory. This setting may use significantly more power than when buffering is enabled. - * 0b01..One buffer is used for all instruction fetches. - * 0b10..All buffers may be used for instruction fetches. - * 0b11..Reserved setting, do not use. - */ -#define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) -#define SYSCON_FLASHCFG_DATACFG_MASK (0xCU) -#define SYSCON_FLASHCFG_DATACFG_SHIFT (2U) -/*! DATACFG - Data read configuration. This field determines how flash accelerator buffers are used for data accesses. - * 0b00..Data accesses from flash are not buffered. Every data access from the CPU results in a read of the flash memory. - * 0b01..One buffer is used for all data accesses. - * 0b10..All buffers may be used for data accesses. - * 0b11..Reserved setting, do not use. - */ -#define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK) -#define SYSCON_FLASHCFG_ACCEL_MASK (0x10U) -#define SYSCON_FLASHCFG_ACCEL_SHIFT (4U) -/*! ACCEL - Acceleration enable. - * 0b0..Flash acceleration is disabled. Every flash read (including those fulfilled from a buffer) takes FLASHTIM + 1 system clocks. This allows more determinism at a cost of performance. - * 0b1..Flash acceleration is enabled. Performance is enhanced, dependent on other FLASHCFG settings. - */ -#define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK) -#define SYSCON_FLASHCFG_PREFEN_MASK (0x20U) -#define SYSCON_FLASHCFG_PREFEN_SHIFT (5U) -/*! PREFEN - Prefetch enable. - * 0b0..No instruction prefetch is performed. - * 0b1..If the FETCHCFG field is not 0, the next flash line following the current execution address is automatically prefetched if it is not already buffered. - */ -#define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK) -#define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U) -#define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U) -/*! PREFOVR - Prefetch override. This bit only applies when PREFEN = 1 and a buffered instruction is completing for which the next flash line is not already buffered or being prefetched. - * 0b0..Any previously initiated prefetch will be completed. - * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered. - */ -#define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK) -#define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) -#define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) -/*! FLASHTIM - Flash memory access time. The number of system clocks used for flash accesses is equal to FLASHTIM +1. - * 0b0000..1 system clock flash access time (for system clock rates up to 12 MHz). - * 0b0001..2 system clocks flash access time (for system clock rates up to 30 MHz). - * 0b0010..3 system clocks flash access time (for system clock rates up to 60 MHz). - * 0b0011..4 system clocks flash access time (for system clock rates up to 85 MHz). - * 0b0100..5 system clocks flash access time (for system clock rates up to 100 MHz). - */ -#define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) -/*! @} */ - -/*! @name USBCLKCTRL - USB clock control */ -/*! @{ */ -#define SYSCON_USBCLKCTRL_POL_CLK_MASK (0x2U) -#define SYSCON_USBCLKCTRL_POL_CLK_SHIFT (1U) -/*! POL_CLK - USB_NEED_CLK polarity for triggering the USB wake-up interrupt - * 0b0..Falling edge of the USB_NEED_CLK triggers the USB wake-up (default). - * 0b1..Rising edge of the USB_NEED_CLK triggers the USB wake-up. - */ -#define SYSCON_USBCLKCTRL_POL_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKCTRL_POL_CLK_SHIFT)) & SYSCON_USBCLKCTRL_POL_CLK_MASK) -/*! @} */ - -/*! @name USBCLKSTAT - USB clock status */ -/*! @{ */ -#define SYSCON_USBCLKSTAT_NEED_CLKST_MASK (0x1U) -#define SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT (0U) -/*! NEED_CLKST - USB_NEED_CLK signal status - * 0b0..Low - * 0b1..High - */ -#define SYSCON_USBCLKSTAT_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBCLKSTAT_NEED_CLKST_SHIFT)) & SYSCON_USBCLKSTAT_NEED_CLKST_MASK) -/*! @} */ - -/*! @name FREQMECTRL - Frequency measure register */ -/*! @{ */ -#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) -#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) -#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) -#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) -#define SYSCON_FREQMECTRL_PROG_SHIFT (31U) -#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) -/*! @} */ - -/*! @name MCLKIO - MCLK input/output control */ -/*! @{ */ -#define SYSCON_MCLKIO_DIR_MASK (0x1U) -#define SYSCON_MCLKIO_DIR_SHIFT (0U) -/*! DIR - MCLK direction control. - * 0b0..The MCLK function is an input. - * 0b1..The MCLK function is an output. - */ -#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) -/*! @} */ - -/*! @name FROCTRL - FRO oscillator control */ -/*! @{ */ -#define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) -#define SYSCON_FROCTRL_TRIM_SHIFT (0U) -#define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) -#define SYSCON_FROCTRL_SEL_MASK (0x4000U) -#define SYSCON_FROCTRL_SEL_SHIFT (14U) -/*! SEL - Select the fro_hf output frequency. This bit can only be changed by software when the WRTRIM bit = 1. Note that the factory trim values are for the 96 MHz FRO only. - * 0b0..48 MHz - * 0b1..96 MHz - */ -#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK) -#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U) -#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U) -#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK) -#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U) -#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U) -/*! USBCLKADJ - USB clock adjust mode. - * 0b0..Normal operation. - * 0b1..Automatic USB rate adjustment mode. If the USB FS device peripheral is enabled and connected to a USB host, it provides clock adjustment information to the FRO based on SOF packets. USB rate adjustment requires a number of cycles to take place. the USBMODCHG bit (see below) indicates when initial adjustment is complete, and when later adjustments are in progress. software must not alter TRIM and FREQTRIM while USBCLKADJ = 1. see USBCLKADJ usage notes below this table. - */ -#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK) -#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U) -#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U) -#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK) -#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U) -#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U) -/*! HSPDCLK - High speed clock enable. Allows disabling the highs-speed FRO output if it is not needed. - * 0b0..The high-speed FRO output is disabled. - * 0b1..The selected high-speed FRO output (48 MHz or 96 MHz) is enabled. - */ -#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK) -#define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) -#define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) -#define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) -/*! @} */ - -/*! @name WDTOSCCTRL - Watchdog oscillator control */ -/*! @{ */ -#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) -#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) -#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) -#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) -#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) -#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) -/*! @} */ - -/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ -/*! @{ */ -#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) -#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) -/*! EN - RTC 32 kHz clock enable. - * 0b0..Disabled. RTC clock off. - * 0b1..Enabled. RTC clock on. - */ -#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) -/*! @} */ - -/*! @name SYSPLLCTRL - PLL control */ -/*! @{ */ -#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) -#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) -#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) -#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U) -#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U) -#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK) -#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U) -#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U) -#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK) -#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U) -#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U) -/*! BYPASS - PLL bypass control. - * 0b0..Bypass disabled. PLL CCO is sent to the PLL post-dividers. - * 0b1..Bypass enabled. PLL input clock is sent directly to the PLL output (default). - */ -#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK) -#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK (0x10000U) -#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT (16U) -/*! BYPASSCCODIV2 - Bypass feedback clock divide by 2. - * 0b0..Divide by 2. The CCO feedback clock is divided by 2 in addition to the programmed M divide. - * 0b1..Bypass. The CCO feedback clock is divided only by the programmed M divide. - */ -#define SYSCON_SYSPLLCTRL_BYPASSCCODIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) -#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U) -#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U) -/*! UPLIMOFF - Disable upper frequency limiter. - * 0b0..Normal mode. - * 0b1..Upper frequency limiter disabled. - */ -#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK) -#define SYSCON_SYSPLLCTRL_BANDSEL_MASK (0x40000U) -#define SYSCON_SYSPLLCTRL_BANDSEL_SHIFT (18U) -/*! BANDSEL - PLL filter control. Set this bit to one when the spread spectrum controller is disabled or at low frequencies. For spread spectrum mode: SEL_EXT = 0, BANDSEL = 0, and UPLIMOFF = 1. - * 0b0..SSCG control. The PLL filter uses the parameters derived from the spread spectrum controller. - * 0b1..MDEC control. The PLL filter uses the programmable fields SELP, SELR, and SELI in this register to control the filter constants. - */ -#define SYSCON_SYSPLLCTRL_BANDSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT)) & SYSCON_SYSPLLCTRL_BANDSEL_MASK) -#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U) -#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U) -/*! DIRECTI - PLL0 direct input enable - * 0b0..Disabled. The PLL input divider (N divider) output is used to drive the PLL CCO. - * 0b1..Enabled. The PLL input divider (N divider) is bypassed. the PLL input clock is used directly to drive the PLL CCO input. - */ -#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK) -#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) -#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) -/*! DIRECTO - PLL0 direct output enable. - * 0b0..Disabled. The PLL output divider (P divider) is used to create the PLL output. - * 0b1..Enabled. The PLL output divider (P divider) is bypassed, the PLL CCO output is used as the PLL output. - */ -#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) -/*! @} */ - -/*! @name SYSPLLSTAT - PLL status */ -/*! @{ */ -#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) -#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) -#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) -/*! @} */ - -/*! @name SYSPLLNDEC - PLL N decoder */ -/*! @{ */ -#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) -#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) -#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) -#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) -#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) -#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) -/*! @} */ - -/*! @name SYSPLLPDEC - PLL P decoder */ -/*! @{ */ -#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) -#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) -#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) -#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) -#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) -#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) -/*! @} */ - -/*! @name SYSPLLSSCTRL0 - PLL spread spectrum control 0 */ -/*! @{ */ -#define SYSCON_SYSPLLSSCTRL0_MDEC_MASK (0x1FFFFU) -#define SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT (0U) -#define SYSCON_SYSPLLSSCTRL0_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MDEC_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MDEC_MASK) -#define SYSCON_SYSPLLSSCTRL0_MREQ_MASK (0x20000U) -#define SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT (17U) -#define SYSCON_SYSPLLSSCTRL0_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL0_MREQ_MASK) -#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK (0x40000U) -#define SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT (18U) -#define SYSCON_SYSPLLSSCTRL0_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)) & SYSCON_SYSPLLSSCTRL0_SEL_EXT_MASK) -/*! @} */ - -/*! @name SYSPLLSSCTRL1 - PLL spread spectrum control 1 */ -/*! @{ */ -#define SYSCON_SYSPLLSSCTRL1_MD_MASK (0x7FFFFU) -#define SYSCON_SYSPLLSSCTRL1_MD_SHIFT (0U) -#define SYSCON_SYSPLLSSCTRL1_MD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MD_MASK) -#define SYSCON_SYSPLLSSCTRL1_MDREQ_MASK (0x80000U) -#define SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT (19U) -#define SYSCON_SYSPLLSSCTRL1_MDREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MDREQ_MASK) -#define SYSCON_SYSPLLSSCTRL1_MF_MASK (0x700000U) -#define SYSCON_SYSPLLSSCTRL1_MF_SHIFT (20U) -#define SYSCON_SYSPLLSSCTRL1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MF_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MF_MASK) -#define SYSCON_SYSPLLSSCTRL1_MR_MASK (0x3800000U) -#define SYSCON_SYSPLLSSCTRL1_MR_SHIFT (23U) -#define SYSCON_SYSPLLSSCTRL1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MR_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MR_MASK) -#define SYSCON_SYSPLLSSCTRL1_MC_MASK (0xC000000U) -#define SYSCON_SYSPLLSSCTRL1_MC_SHIFT (26U) -#define SYSCON_SYSPLLSSCTRL1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_MC_SHIFT)) & SYSCON_SYSPLLSSCTRL1_MC_MASK) -#define SYSCON_SYSPLLSSCTRL1_PD_MASK (0x10000000U) -#define SYSCON_SYSPLLSSCTRL1_PD_SHIFT (28U) -/*! PD - Spread spectrum power-down. - * 0b0..Enabled. Spread spectrum controller is enabled - * 0b1..Disabled. Spread spectrum controller is disabled. - */ -#define SYSCON_SYSPLLSSCTRL1_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_PD_SHIFT)) & SYSCON_SYSPLLSSCTRL1_PD_MASK) -#define SYSCON_SYSPLLSSCTRL1_DITHER_MASK (0x20000000U) -#define SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT (29U) -/*! DITHER - Select modulation frequency. - * 0b0..Fixed. Fixed modulation frequency. - * 0b1..Dither. Randomly dither between two modulation frequencies. - */ -#define SYSCON_SYSPLLSSCTRL1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT)) & SYSCON_SYSPLLSSCTRL1_DITHER_MASK) -/*! @} */ - -/*! @name PDSLEEPCFG - Sleep configuration register n */ -/*! @{ */ -#define SYSCON_PDSLEEPCFG_PD_SLEEP_MASK (0xFFFFFFFFU) -#define SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT (0U) -#define SYSCON_PDSLEEPCFG_PD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PD_SLEEP_SHIFT)) & SYSCON_PDSLEEPCFG_PD_SLEEP_MASK) -/*! @} */ - -/* The count of SYSCON_PDSLEEPCFG */ -#define SYSCON_PDSLEEPCFG_COUNT (2U) - -/*! @name PDRUNCFG - Power configuration register 0 */ -/*! @{ */ -#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) -#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) -#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) -#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U) -#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U) -#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U) -#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U) -#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK) -#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U) -#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U) -#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x2000U) -#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (13U) -#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK) -#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x10000U) -#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (16U) -#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK) -#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U) -#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U) -#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK) -#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U) -#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U) -#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U) -#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) -#define SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK (0x200000U) -#define SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT (21U) -#define SYSCON_PDRUNCFG_PDEN_USB_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_PHY_MASK) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) -#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) -#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U) -#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U) -#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK) -/*! @} */ - -/* The count of SYSCON_PDRUNCFG */ -#define SYSCON_PDRUNCFG_COUNT (1U) - -/*! @name PDRUNCFGSET - Set bits in PDRUNCFGn */ -/*! @{ */ -#define SYSCON_PDRUNCFGSET_PD_SET_MASK (0xFFFFFFFFU) -#define SYSCON_PDRUNCFGSET_PD_SET_SHIFT (0U) -#define SYSCON_PDRUNCFGSET_PD_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PD_SET_SHIFT)) & SYSCON_PDRUNCFGSET_PD_SET_MASK) -/*! @} */ - -/* The count of SYSCON_PDRUNCFGSET */ -#define SYSCON_PDRUNCFGSET_COUNT (1U) - -/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFGn */ -/*! @{ */ -#define SYSCON_PDRUNCFGCLR_PD_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT (0U) -#define SYSCON_PDRUNCFGCLR_PD_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PD_CLR_SHIFT)) & SYSCON_PDRUNCFGCLR_PD_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_PDRUNCFGCLR */ -#define SYSCON_PDRUNCFGCLR_COUNT (1U) - -/*! @name STARTER - Start logic n wake-up enable register */ -/*! @{ */ -#define SYSCON_STARTER_WDT_BOD_MASK (0x1U) -#define SYSCON_STARTER_WDT_BOD_SHIFT (0U) -#define SYSCON_STARTER_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK) -#define SYSCON_STARTER_DMA0_MASK (0x2U) -#define SYSCON_STARTER_DMA0_SHIFT (1U) -#define SYSCON_STARTER_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA0_SHIFT)) & SYSCON_STARTER_DMA0_MASK) -#define SYSCON_STARTER_GINT0_MASK (0x4U) -#define SYSCON_STARTER_GINT0_SHIFT (2U) -#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) -#define SYSCON_STARTER_GINT1_MASK (0x8U) -#define SYSCON_STARTER_GINT1_SHIFT (3U) -#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) -#define SYSCON_STARTER_PIN_INT0_MASK (0x10U) -#define SYSCON_STARTER_PIN_INT0_SHIFT (4U) -#define SYSCON_STARTER_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK) -#define SYSCON_STARTER_PIN_INT1_MASK (0x20U) -#define SYSCON_STARTER_PIN_INT1_SHIFT (5U) -#define SYSCON_STARTER_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK) -#define SYSCON_STARTER_PIN_INT2_MASK (0x40U) -#define SYSCON_STARTER_PIN_INT2_SHIFT (6U) -#define SYSCON_STARTER_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK) -#define SYSCON_STARTER_PIN_INT3_MASK (0x80U) -#define SYSCON_STARTER_PIN_INT3_SHIFT (7U) -#define SYSCON_STARTER_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK) -#define SYSCON_STARTER_UTICK0_MASK (0x100U) -#define SYSCON_STARTER_UTICK0_SHIFT (8U) -#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK) -#define SYSCON_STARTER_MRT0_MASK (0x200U) -#define SYSCON_STARTER_MRT0_SHIFT (9U) -#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK) -#define SYSCON_STARTER_CTIMER0_MASK (0x400U) -#define SYSCON_STARTER_CTIMER0_SHIFT (10U) -#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) -#define SYSCON_STARTER_CTIMER1_MASK (0x800U) -#define SYSCON_STARTER_CTIMER1_SHIFT (11U) -#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) -#define SYSCON_STARTER_SCT0_MASK (0x1000U) -#define SYSCON_STARTER_SCT0_SHIFT (12U) -#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) -#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) -#define SYSCON_STARTER_CTIMER3_SHIFT (13U) -#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) -#define SYSCON_STARTER_FLEXCOMM0_MASK (0x4000U) -#define SYSCON_STARTER_FLEXCOMM0_SHIFT (14U) -#define SYSCON_STARTER_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK) -#define SYSCON_STARTER_FLEXCOMM1_MASK (0x8000U) -#define SYSCON_STARTER_FLEXCOMM1_SHIFT (15U) -#define SYSCON_STARTER_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK) -#define SYSCON_STARTER_FLEXCOMM2_MASK (0x10000U) -#define SYSCON_STARTER_FLEXCOMM2_SHIFT (16U) -#define SYSCON_STARTER_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK) -#define SYSCON_STARTER_FLEXCOMM3_MASK (0x20000U) -#define SYSCON_STARTER_FLEXCOMM3_SHIFT (17U) -#define SYSCON_STARTER_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK) -#define SYSCON_STARTER_FLEXCOMM4_MASK (0x40000U) -#define SYSCON_STARTER_FLEXCOMM4_SHIFT (18U) -#define SYSCON_STARTER_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK) -#define SYSCON_STARTER_FLEXCOMM5_MASK (0x80000U) -#define SYSCON_STARTER_FLEXCOMM5_SHIFT (19U) -#define SYSCON_STARTER_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK) -#define SYSCON_STARTER_FLEXCOMM6_MASK (0x100000U) -#define SYSCON_STARTER_FLEXCOMM6_SHIFT (20U) -#define SYSCON_STARTER_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK) -#define SYSCON_STARTER_FLEXCOMM7_MASK (0x200000U) -#define SYSCON_STARTER_FLEXCOMM7_SHIFT (21U) -#define SYSCON_STARTER_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK) -#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) -#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) -#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) -#define SYSCON_STARTER_USB0_MASK (0x10000000U) -#define SYSCON_STARTER_USB0_SHIFT (28U) -#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) -#define SYSCON_STARTER_RTC_MASK (0x20000000U) -#define SYSCON_STARTER_RTC_SHIFT (29U) -#define SYSCON_STARTER_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK) -/*! @} */ - -/* The count of SYSCON_STARTER */ -#define SYSCON_STARTER_COUNT (1U) - -/*! @name STARTERSET - Set bits in STARTERn */ -/*! @{ */ -#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) -#define SYSCON_STARTERSET_START_SET_SHIFT (0U) -#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERSET */ -#define SYSCON_STARTERSET_COUNT (1U) - -/*! @name STARTERCLR - Clear bits in STARTERn */ -/*! @{ */ -#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) -#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERCLR */ -#define SYSCON_STARTERCLR_COUNT (1U) - -/*! @name HWWAKE - Configures special cases of hardware wake-up */ -/*! @{ */ -#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) -#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) -#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) -#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U) -#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U) -#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK) -#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) -#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) -#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) -/*! @} */ - -/*! @name JTAGIDCODE - JTAG ID code register */ -/*! @{ */ -#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) -#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) -#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) -/*! @} */ - -/*! @name DEVICE_ID0 - Part ID register */ -/*! @{ */ -#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) -#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) -#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) -/*! @} */ - -/*! @name DEVICE_ID1 - Boot ROM and die revision register */ -/*! @{ */ -#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) -#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) -#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) -/*! @} */ - -/*! @name BODCTRL - Brown-Out Detect control */ -/*! @{ */ -#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) -#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) -/*! BODRSTLEV - BOD reset level - * 0b00..Level 0: 1.5 V - * 0b01..Level 1: 1.85 V - * 0b10..Level 2: 2.0 V - * 0b11..Level 3: 2.3 V - */ -#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) -#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U) -#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U) -/*! BODRSTENA - BOD reset enable - * 0b0..Disable reset function. - * 0b1..Enable reset function. - */ -#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) -#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U) -#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U) -/*! BODINTLEV - BOD interrupt level - * 0b00..Level 0: 2.05 V - * 0b01..Level 1: 2.45 V - * 0b10..Level 2: 2.75 V - * 0b11..Level 3: 3.05 V - */ -#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK) -#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U) -#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U) -/*! BODINTENA - BOD interrupt enable - * 0b0..Disable interrupt function. - * 0b1..Enable interrupt function. - */ -#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK) -#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U) -#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U) -#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK) -#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) -#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) -#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SYSCON_Register_Masks */ - - -/* SYSCON - Peripheral instance base addresses */ -/** Peripheral SYSCON base address */ -#define SYSCON_BASE (0x40000000u) -/** Peripheral SYSCON base pointer */ -#define SYSCON ((SYSCON_Type *)SYSCON_BASE) -/** Array initializer of SYSCON peripheral base addresses */ -#define SYSCON_BASE_ADDRS { SYSCON_BASE } -/** Array initializer of SYSCON peripheral base pointers */ -#define SYSCON_BASE_PTRS { SYSCON } - -/*! - * @} - */ /* end of group SYSCON_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USART Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer - * @{ - */ - -/** USART - Register Layout Typedef */ -typedef struct { - __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ - __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ - __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ - __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ - __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ - uint8_t RESERVED_0[12]; - __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ - __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ - __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ - __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ - uint8_t RESERVED_1[3536]; - __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ - __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ - __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ - uint8_t RESERVED_2[4]; - __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ - __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ - __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ - uint8_t RESERVED_3[4]; - __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ - uint8_t RESERVED_4[12]; - __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ - uint8_t RESERVED_5[12]; - __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_6[440]; - __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ -} USART_Type; - -/* ---------------------------------------------------------------------------- - -- USART Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USART_Register_Masks USART Register Masks - * @{ - */ - -/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ -/*! @{ */ -#define USART_CFG_ENABLE_MASK (0x1U) -#define USART_CFG_ENABLE_SHIFT (0U) -/*! ENABLE - USART Enable. - * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the transmitter has been reset and is therefore available. - * 0b1..Enabled. The USART is enabled for operation. - */ -#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) -#define USART_CFG_DATALEN_MASK (0xCU) -#define USART_CFG_DATALEN_SHIFT (2U) -/*! DATALEN - Selects the data size for the USART. - * 0b00..7 bit Data length. - * 0b01..8 bit Data length. - * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. - * 0b11..Reserved. - */ -#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) -#define USART_CFG_PARITYSEL_MASK (0x30U) -#define USART_CFG_PARITYSEL_SHIFT (4U) -/*! PARITYSEL - Selects what type of parity is used by the USART. - * 0b00..No parity. - * 0b01..Reserved. - * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even. - * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd. - */ -#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) -#define USART_CFG_STOPLEN_MASK (0x40U) -#define USART_CFG_STOPLEN_SHIFT (6U) -/*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. - * 0b0..1 stop bit. - * 0b1..2 stop bits. This setting should only be used for asynchronous communication. - */ -#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) -#define USART_CFG_MODE32K_MASK (0x80U) -#define USART_CFG_MODE32K_SHIFT (7U) -/*! MODE32K - Selects standard or 32 kHz clocking mode. - * 0b0..Disabled. USART uses standard clocking. - * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. - */ -#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) -#define USART_CFG_LINMODE_MASK (0x100U) -#define USART_CFG_LINMODE_SHIFT (8U) -/*! LINMODE - LIN break mode enable. - * 0b0..Disabled. Break detect and generate is configured for normal operation. - * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. - */ -#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) -#define USART_CFG_CTSEN_MASK (0x200U) -#define USART_CFG_CTSEN_SHIFT (9U) -/*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART's own RTS if loopback mode is enabled. - * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. - * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. - */ -#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) -#define USART_CFG_SYNCEN_MASK (0x800U) -#define USART_CFG_SYNCEN_SHIFT (11U) -/*! SYNCEN - Selects synchronous or asynchronous operation. - * 0b0..Asynchronous mode. - * 0b1..Synchronous mode. - */ -#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) -#define USART_CFG_CLKPOL_MASK (0x1000U) -#define USART_CFG_CLKPOL_SHIFT (12U) -/*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. - * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. - * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. - */ -#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) -#define USART_CFG_SYNCMST_MASK (0x4000U) -#define USART_CFG_SYNCMST_SHIFT (14U) -/*! SYNCMST - Synchronous mode Master select. - * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. - * 0b1..Master. When synchronous mode is enabled, the USART is a master. - */ -#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) -#define USART_CFG_LOOP_MASK (0x8000U) -#define USART_CFG_LOOP_SHIFT (15U) -/*! LOOP - Selects data loopback mode. - * 0b0..Normal operation. - * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. - */ -#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) -#define USART_CFG_OETA_MASK (0x40000U) -#define USART_CFG_OETA_SHIFT (18U) -/*! OETA - Output Enable Turnaround time enable for RS-485 operation. - * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. - * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted. - */ -#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) -#define USART_CFG_AUTOADDR_MASK (0x80000U) -#define USART_CFG_AUTOADDR_SHIFT (19U) -/*! AUTOADDR - Automatic Address matching enable. - * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address). - * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match. - */ -#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) -#define USART_CFG_OESEL_MASK (0x100000U) -#define USART_CFG_OESEL_SHIFT (20U) -/*! OESEL - Output Enable Select. - * 0b0..Standard. The RTS signal is used as the standard flow control function. - * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. - */ -#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) -#define USART_CFG_OEPOL_MASK (0x200000U) -#define USART_CFG_OEPOL_SHIFT (21U) -/*! OEPOL - Output Enable Polarity. - * 0b0..Low. If selected by OESEL, the output enable is active low. - * 0b1..High. If selected by OESEL, the output enable is active high. - */ -#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) -#define USART_CFG_RXPOL_MASK (0x400000U) -#define USART_CFG_RXPOL_SHIFT (22U) -/*! RXPOL - Receive data polarity. - * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) -#define USART_CFG_TXPOL_MASK (0x800000U) -#define USART_CFG_TXPOL_SHIFT (23U) -/*! TXPOL - Transmit data polarity. - * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1. - * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0. - */ -#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) -/*! @} */ - -/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ -/*! @{ */ -#define USART_CTL_TXBRKEN_MASK (0x2U) -#define USART_CTL_TXBRKEN_SHIFT (1U) -/*! TXBRKEN - Break Enable. - * 0b0..Normal operation. - * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit is cleared. A break may be sent without danger of corrupting any currently transmitting character if the transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. - */ -#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) -#define USART_CTL_ADDRDET_MASK (0x4U) -#define USART_CTL_ADDRDET_SHIFT (2U) -/*! ADDRDET - Enable address detect mode. - * 0b0..Disabled. The USART presents all incoming data. - * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, generating a received data interrupt. Software can then check the data to see if this is an address that should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled normally. - */ -#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) -#define USART_CTL_TXDIS_MASK (0x40U) -#define USART_CTL_TXDIS_SHIFT (6U) -/*! TXDIS - Transmit Disable. - * 0b0..Not disabled. USART transmitter is not disabled. - * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This feature can be used to facilitate software flow control. - */ -#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) -#define USART_CTL_CC_MASK (0x100U) -#define USART_CTL_CC_SHIFT (8U) -/*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. - * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to complete a character that is being received. - * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on Un_RxD independently from transmission on Un_TXD). - */ -#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) -#define USART_CTL_CLRCCONRX_MASK (0x200U) -#define USART_CTL_CLRCCONRX_SHIFT (9U) -/*! CLRCCONRX - Clear Continuous Clock. - * 0b0..No effect. No effect on the CC bit. - * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. - */ -#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) -#define USART_CTL_AUTOBAUD_MASK (0x10000U) -#define USART_CTL_AUTOBAUD_SHIFT (16U) -/*! AUTOBAUD - Autobaud enable. - * 0b0..Disabled. USART is in normal operating mode. - * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The first start bit of RX is measured and used the update the BRG register to match the received data rate. AUTOBAUD is cleared once this process is complete, or if there is an AERR. - */ -#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) -/*! @} */ - -/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ -/*! @{ */ -#define USART_STAT_RXIDLE_MASK (0x2U) -#define USART_STAT_RXIDLE_SHIFT (1U) -#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) -#define USART_STAT_TXIDLE_MASK (0x8U) -#define USART_STAT_TXIDLE_SHIFT (3U) -#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) -#define USART_STAT_CTS_MASK (0x10U) -#define USART_STAT_CTS_SHIFT (4U) -#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) -#define USART_STAT_DELTACTS_MASK (0x20U) -#define USART_STAT_DELTACTS_SHIFT (5U) -#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) -#define USART_STAT_TXDISSTAT_MASK (0x40U) -#define USART_STAT_TXDISSTAT_SHIFT (6U) -#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) -#define USART_STAT_RXBRK_MASK (0x400U) -#define USART_STAT_RXBRK_SHIFT (10U) -#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) -#define USART_STAT_DELTARXBRK_MASK (0x800U) -#define USART_STAT_DELTARXBRK_SHIFT (11U) -#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) -#define USART_STAT_START_MASK (0x1000U) -#define USART_STAT_START_SHIFT (12U) -#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) -#define USART_STAT_FRAMERRINT_MASK (0x2000U) -#define USART_STAT_FRAMERRINT_SHIFT (13U) -#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) -#define USART_STAT_PARITYERRINT_MASK (0x4000U) -#define USART_STAT_PARITYERRINT_SHIFT (14U) -#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) -#define USART_STAT_RXNOISEINT_MASK (0x8000U) -#define USART_STAT_RXNOISEINT_SHIFT (15U) -#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) -#define USART_STAT_ABERR_MASK (0x10000U) -#define USART_STAT_ABERR_SHIFT (16U) -#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) -/*! @} */ - -/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ -/*! @{ */ -#define USART_INTENSET_TXIDLEEN_MASK (0x8U) -#define USART_INTENSET_TXIDLEEN_SHIFT (3U) -#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) -#define USART_INTENSET_DELTACTSEN_MASK (0x20U) -#define USART_INTENSET_DELTACTSEN_SHIFT (5U) -#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) -#define USART_INTENSET_TXDISEN_MASK (0x40U) -#define USART_INTENSET_TXDISEN_SHIFT (6U) -#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) -#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) -#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) -#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) -#define USART_INTENSET_STARTEN_MASK (0x1000U) -#define USART_INTENSET_STARTEN_SHIFT (12U) -#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) -#define USART_INTENSET_FRAMERREN_MASK (0x2000U) -#define USART_INTENSET_FRAMERREN_SHIFT (13U) -#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) -#define USART_INTENSET_PARITYERREN_MASK (0x4000U) -#define USART_INTENSET_PARITYERREN_SHIFT (14U) -#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) -#define USART_INTENSET_RXNOISEEN_MASK (0x8000U) -#define USART_INTENSET_RXNOISEEN_SHIFT (15U) -#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) -#define USART_INTENSET_ABERREN_MASK (0x10000U) -#define USART_INTENSET_ABERREN_SHIFT (16U) -#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) -/*! @} */ - -/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ -/*! @{ */ -#define USART_INTENCLR_TXIDLECLR_MASK (0x8U) -#define USART_INTENCLR_TXIDLECLR_SHIFT (3U) -#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) -#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) -#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) -#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) -#define USART_INTENCLR_TXDISCLR_MASK (0x40U) -#define USART_INTENCLR_TXDISCLR_SHIFT (6U) -#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) -#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) -#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) -#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) -#define USART_INTENCLR_STARTCLR_MASK (0x1000U) -#define USART_INTENCLR_STARTCLR_SHIFT (12U) -#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) -#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) -#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) -#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) -#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) -#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) -#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) -#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) -#define USART_INTENCLR_RXNOISECLR_SHIFT (15U) -#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) -#define USART_INTENCLR_ABERRCLR_MASK (0x10000U) -#define USART_INTENCLR_ABERRCLR_SHIFT (16U) -#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) -/*! @} */ - -/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ -/*! @{ */ -#define USART_BRG_BRGVAL_MASK (0xFFFFU) -#define USART_BRG_BRGVAL_SHIFT (0U) -#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) -/*! @} */ - -/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ -/*! @{ */ -#define USART_INTSTAT_TXIDLE_MASK (0x8U) -#define USART_INTSTAT_TXIDLE_SHIFT (3U) -#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) -#define USART_INTSTAT_DELTACTS_MASK (0x20U) -#define USART_INTSTAT_DELTACTS_SHIFT (5U) -#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) -#define USART_INTSTAT_TXDISINT_MASK (0x40U) -#define USART_INTSTAT_TXDISINT_SHIFT (6U) -#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) -#define USART_INTSTAT_DELTARXBRK_MASK (0x800U) -#define USART_INTSTAT_DELTARXBRK_SHIFT (11U) -#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) -#define USART_INTSTAT_START_MASK (0x1000U) -#define USART_INTSTAT_START_SHIFT (12U) -#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) -#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) -#define USART_INTSTAT_FRAMERRINT_SHIFT (13U) -#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) -#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) -#define USART_INTSTAT_PARITYERRINT_SHIFT (14U) -#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) -#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) -#define USART_INTSTAT_RXNOISEINT_SHIFT (15U) -#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) -#define USART_INTSTAT_ABERRINT_MASK (0x10000U) -#define USART_INTSTAT_ABERRINT_SHIFT (16U) -#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) -/*! @} */ - -/*! @name OSR - Oversample selection register for asynchronous communication. */ -/*! @{ */ -#define USART_OSR_OSRVAL_MASK (0xFU) -#define USART_OSR_OSRVAL_SHIFT (0U) -#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) -/*! @} */ - -/*! @name ADDR - Address register for automatic address matching. */ -/*! @{ */ -#define USART_ADDR_ADDRESS_MASK (0xFFU) -#define USART_ADDR_ADDRESS_SHIFT (0U) -#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) -/*! @} */ - -/*! @name FIFOCFG - FIFO configuration and enable register. */ -/*! @{ */ -#define USART_FIFOCFG_ENABLETX_MASK (0x1U) -#define USART_FIFOCFG_ENABLETX_SHIFT (0U) -/*! ENABLETX - Enable the transmit FIFO. - * 0b0..The transmit FIFO is not enabled. - * 0b1..The transmit FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) -#define USART_FIFOCFG_ENABLERX_MASK (0x2U) -#define USART_FIFOCFG_ENABLERX_SHIFT (1U) -/*! ENABLERX - Enable the receive FIFO. - * 0b0..The receive FIFO is not enabled. - * 0b1..The receive FIFO is enabled. - */ -#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) -#define USART_FIFOCFG_SIZE_MASK (0x30U) -#define USART_FIFOCFG_SIZE_SHIFT (4U) -#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) -#define USART_FIFOCFG_DMATX_MASK (0x1000U) -#define USART_FIFOCFG_DMATX_SHIFT (12U) -/*! DMATX - DMA configuration for transmit. - * 0b0..DMA is not used for the transmit function. - * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) -#define USART_FIFOCFG_DMARX_MASK (0x2000U) -#define USART_FIFOCFG_DMARX_SHIFT (13U) -/*! DMARX - DMA configuration for receive. - * 0b0..DMA is not used for the receive function. - * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. - */ -#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) -#define USART_FIFOCFG_WAKETX_MASK (0x4000U) -#define USART_FIFOCFG_WAKETX_SHIFT (14U) -/*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the transmit FIFO level reaches the value specified by TXLVL in FIFOTRIG, even when the TXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) -#define USART_FIFOCFG_WAKERX_MASK (0x8000U) -#define USART_FIFOCFG_WAKERX_SHIFT (15U) -/*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register. - * 0b0..Only enabled interrupts will wake up the device form reduced power modes. - * 0b1..A device wake-up for DMA will occur if the receive FIFO level reaches the value specified by RXLVL in FIFOTRIG, even when the RXLVL interrupt is not enabled. - */ -#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) -#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) -#define USART_FIFOCFG_EMPTYTX_SHIFT (16U) -#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) -#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) -#define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -/*! @} */ - -/*! @name FIFOSTAT - FIFO status register. */ -/*! @{ */ -#define USART_FIFOSTAT_TXERR_MASK (0x1U) -#define USART_FIFOSTAT_TXERR_SHIFT (0U) -#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) -#define USART_FIFOSTAT_RXERR_MASK (0x2U) -#define USART_FIFOSTAT_RXERR_SHIFT (1U) -#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) -#define USART_FIFOSTAT_PERINT_MASK (0x8U) -#define USART_FIFOSTAT_PERINT_SHIFT (3U) -#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) -#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) -#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) -#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) -#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) -#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) -#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) -#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) -#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) -#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) -#define USART_FIFOSTAT_RXFULL_MASK (0x80U) -#define USART_FIFOSTAT_RXFULL_SHIFT (7U) -#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) -#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) -#define USART_FIFOSTAT_TXLVL_SHIFT (8U) -#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) -#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) -#define USART_FIFOSTAT_RXLVL_SHIFT (16U) -#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ -/*! @{ */ -#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) -#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) -/*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMATX in FIFOCFG is set. - * 0b0..Transmit FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. - */ -#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) -#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) -#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) -/*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled in FIFOINTENSET, or a DMA trigger if DMARX in FIFOCFG is set. - * 0b0..Receive FIFO level does not generate a FIFO level trigger. - * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. - */ -#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) -#define USART_FIFOTRIG_TXLVL_MASK (0xF00U) -#define USART_FIFOTRIG_TXLVL_SHIFT (8U) -#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) -#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) -#define USART_FIFOTRIG_RXLVL_SHIFT (16U) -#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ -/*! @{ */ -#define USART_FIFOINTENSET_TXERR_MASK (0x1U) -#define USART_FIFOINTENSET_TXERR_SHIFT (0U) -/*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a transmit error. - * 0b1..An interrupt will be generated when a transmit error occurs. - */ -#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) -#define USART_FIFOINTENSET_RXERR_MASK (0x2U) -#define USART_FIFOINTENSET_RXERR_SHIFT (1U) -/*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. - * 0b0..No interrupt will be generated for a receive error. - * 0b1..An interrupt will be generated when a receive error occurs. - */ -#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) -#define USART_FIFOINTENSET_TXLVL_MASK (0x4U) -#define USART_FIFOINTENSET_TXLVL_SHIFT (2U) -/*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the TX FIFO level. - * 0b1..If TXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the TX FIFO level decreases to the level specified by TXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) -#define USART_FIFOINTENSET_RXLVL_MASK (0x8U) -#define USART_FIFOINTENSET_RXLVL_SHIFT (3U) -/*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. - * 0b0..No interrupt will be generated based on the RX FIFO level. - * 0b1..If RXLVLENA in the FIFOTRIG register = 1, an interrupt will be generated when the when the RX FIFO level increases to the level specified by RXLVL in the FIFOTRIG register. - */ -#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ -/*! @{ */ -#define USART_FIFOINTENCLR_TXERR_MASK (0x1U) -#define USART_FIFOINTENCLR_TXERR_SHIFT (0U) -#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) -#define USART_FIFOINTENCLR_RXERR_MASK (0x2U) -#define USART_FIFOINTENCLR_RXERR_SHIFT (1U) -#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) -#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) -#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) -#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) -#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) -#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) -#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) -/*! @} */ - -/*! @name FIFOINTSTAT - FIFO interrupt status register. */ -/*! @{ */ -#define USART_FIFOINTSTAT_TXERR_MASK (0x1U) -#define USART_FIFOINTSTAT_TXERR_SHIFT (0U) -#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) -#define USART_FIFOINTSTAT_RXERR_MASK (0x2U) -#define USART_FIFOINTSTAT_RXERR_SHIFT (1U) -#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) -#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) -#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) -#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) -#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) -#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) -#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) -#define USART_FIFOINTSTAT_PERINT_MASK (0x10U) -#define USART_FIFOINTSTAT_PERINT_SHIFT (4U) -#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) -/*! @} */ - -/*! @name FIFOWR - FIFO write data. */ -/*! @{ */ -#define USART_FIFOWR_TXDATA_MASK (0x1FFU) -#define USART_FIFOWR_TXDATA_SHIFT (0U) -#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) -/*! @} */ - -/*! @name FIFORD - FIFO read data. */ -/*! @{ */ -#define USART_FIFORD_RXDATA_MASK (0x1FFU) -#define USART_FIFORD_RXDATA_SHIFT (0U) -#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) -#define USART_FIFORD_FRAMERR_MASK (0x2000U) -#define USART_FIFORD_FRAMERR_SHIFT (13U) -#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) -#define USART_FIFORD_PARITYERR_MASK (0x4000U) -#define USART_FIFORD_PARITYERR_SHIFT (14U) -#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) -#define USART_FIFORD_RXNOISE_MASK (0x8000U) -#define USART_FIFORD_RXNOISE_SHIFT (15U) -#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) -/*! @} */ - -/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ -/*! @{ */ -#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) -#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) -#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) -#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) -#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) -#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) -#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) -#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) -#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) -#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) -#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) -#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) -/*! @} */ - -/*! @name ID - Peripheral identification register. */ -/*! @{ */ -#define USART_ID_APERTURE_MASK (0xFFU) -#define USART_ID_APERTURE_SHIFT (0U) -#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) -#define USART_ID_MINOR_REV_MASK (0xF00U) -#define USART_ID_MINOR_REV_SHIFT (8U) -#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) -#define USART_ID_MAJOR_REV_MASK (0xF000U) -#define USART_ID_MAJOR_REV_SHIFT (12U) -#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) -#define USART_ID_ID_MASK (0xFFFF0000U) -#define USART_ID_ID_SHIFT (16U) -#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USART_Register_Masks */ - - -/* USART - Peripheral instance base addresses */ -/** Peripheral USART0 base address */ -#define USART0_BASE (0x40086000u) -/** Peripheral USART0 base pointer */ -#define USART0 ((USART_Type *)USART0_BASE) -/** Peripheral USART1 base address */ -#define USART1_BASE (0x40087000u) -/** Peripheral USART1 base pointer */ -#define USART1 ((USART_Type *)USART1_BASE) -/** Peripheral USART2 base address */ -#define USART2_BASE (0x40088000u) -/** Peripheral USART2 base pointer */ -#define USART2 ((USART_Type *)USART2_BASE) -/** Peripheral USART3 base address */ -#define USART3_BASE (0x40089000u) -/** Peripheral USART3 base pointer */ -#define USART3 ((USART_Type *)USART3_BASE) -/** Peripheral USART4 base address */ -#define USART4_BASE (0x4008A000u) -/** Peripheral USART4 base pointer */ -#define USART4 ((USART_Type *)USART4_BASE) -/** Peripheral USART5 base address */ -#define USART5_BASE (0x40096000u) -/** Peripheral USART5 base pointer */ -#define USART5 ((USART_Type *)USART5_BASE) -/** Peripheral USART6 base address */ -#define USART6_BASE (0x40097000u) -/** Peripheral USART6 base pointer */ -#define USART6 ((USART_Type *)USART6_BASE) -/** Peripheral USART7 base address */ -#define USART7_BASE (0x40098000u) -/** Peripheral USART7 base pointer */ -#define USART7 ((USART_Type *)USART7_BASE) -/** Array initializer of USART peripheral base addresses */ -#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE } -/** Array initializer of USART peripheral base pointers */ -#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7 } -/** Interrupt vectors for the USART peripheral type */ -#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } - -/*! - * @} - */ /* end of group USART_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer - * @{ - */ - -/** USB - Register Layout Typedef */ -typedef struct { - __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ - __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ - __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ - __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ - __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ - __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ - __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ - __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ - __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ - __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ - __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ - uint8_t RESERVED_0[8]; - __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ -} USB_Type; - -/* ---------------------------------------------------------------------------- - -- USB Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_Register_Masks USB Register Masks - * @{ - */ - -/*! @name DEVCMDSTAT - USB Device Command/Status register */ -/*! @{ */ -#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) -#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) -#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) -#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) -#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) -#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) -#define USB_DEVCMDSTAT_SETUP_MASK (0x100U) -#define USB_DEVCMDSTAT_SETUP_SHIFT (8U) -#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) -#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) -/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: - * 0b0..USB_NEEDCLK has normal function. - * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. - */ -#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) -#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) -#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) -/*! LPM_SUP - LPM Supported: - * 0b0..LPM not supported. - * 0b1..LPM supported. - */ -#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) -#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) -/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) -#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) -/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) -#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) -/*! INTONNAK_CO - Interrupt on NAK for control OUT EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) -#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) -#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) -/*! INTONNAK_CI - Interrupt on NAK for control IN EP - * 0b0..Only acknowledged packets generate an interrupt - * 0b1..Both acknowledged and NAKed packets generate interrupts. - */ -#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) -#define USB_DEVCMDSTAT_DCON_MASK (0x10000U) -#define USB_DEVCMDSTAT_DCON_SHIFT (16U) -#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) -#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) -#define USB_DEVCMDSTAT_DSUS_SHIFT (17U) -#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) -#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) -#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) -#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) -#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) -#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) -#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) -#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) -#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) -#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) -#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) -#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) -#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) -#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) -#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) -#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) -#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) -/*! @} */ - -/*! @name INFO - USB Info register */ -/*! @{ */ -#define USB_INFO_FRAME_NR_MASK (0x7FFU) -#define USB_INFO_FRAME_NR_SHIFT (0U) -#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) -#define USB_INFO_ERR_CODE_MASK (0x7800U) -#define USB_INFO_ERR_CODE_SHIFT (11U) -/*! ERR_CODE - The error code which last occurred: - * 0b0000..No error - * 0b0001..PID encoding error - * 0b0010..PID unknown - * 0b0011..Packet unexpected - * 0b0100..Token CRC error - * 0b0101..Data CRC error - * 0b0110..Time out - * 0b0111..Babble - * 0b1000..Truncated EOP - * 0b1001..Sent/Received NAK - * 0b1010..Sent Stall - * 0b1011..Overrun - * 0b1100..Sent empty packet - * 0b1101..Bitstuff error - * 0b1110..Sync error - * 0b1111..Wrong data toggle - */ -#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) -/*! @} */ - -/*! @name EPLISTSTART - USB EP Command/Status List start address */ -/*! @{ */ -#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) -#define USB_EPLISTSTART_EP_LIST_SHIFT (8U) -#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) -/*! @} */ - -/*! @name DATABUFSTART - USB Data buffer start address */ -/*! @{ */ -#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) -#define USB_DATABUFSTART_DA_BUF_SHIFT (22U) -#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) -/*! @} */ - -/*! @name LPM - USB Link Power Management register */ -/*! @{ */ -#define USB_LPM_HIRD_HW_MASK (0xFU) -#define USB_LPM_HIRD_HW_SHIFT (0U) -#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) -#define USB_LPM_HIRD_SW_MASK (0xF0U) -#define USB_LPM_HIRD_SW_SHIFT (4U) -#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) -#define USB_LPM_DATA_PENDING_MASK (0x100U) -#define USB_LPM_DATA_PENDING_SHIFT (8U) -#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) -/*! @} */ - -/*! @name EPSKIP - USB Endpoint skip */ -/*! @{ */ -#define USB_EPSKIP_SKIP_MASK (0x3FFFFFFFU) -#define USB_EPSKIP_SKIP_SHIFT (0U) -#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) -/*! @} */ - -/*! @name EPINUSE - USB Endpoint Buffer in use */ -/*! @{ */ -#define USB_EPINUSE_BUF_MASK (0x3FCU) -#define USB_EPINUSE_BUF_SHIFT (2U) -#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) -/*! @} */ - -/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ -/*! @{ */ -#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) -#define USB_EPBUFCFG_BUF_SB_SHIFT (2U) -#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) -/*! @} */ - -/*! @name INTSTAT - USB interrupt status register */ -/*! @{ */ -#define USB_INTSTAT_EP0OUT_MASK (0x1U) -#define USB_INTSTAT_EP0OUT_SHIFT (0U) -#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) -#define USB_INTSTAT_EP0IN_MASK (0x2U) -#define USB_INTSTAT_EP0IN_SHIFT (1U) -#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) -#define USB_INTSTAT_EP1OUT_MASK (0x4U) -#define USB_INTSTAT_EP1OUT_SHIFT (2U) -#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) -#define USB_INTSTAT_EP1IN_MASK (0x8U) -#define USB_INTSTAT_EP1IN_SHIFT (3U) -#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) -#define USB_INTSTAT_EP2OUT_MASK (0x10U) -#define USB_INTSTAT_EP2OUT_SHIFT (4U) -#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) -#define USB_INTSTAT_EP2IN_MASK (0x20U) -#define USB_INTSTAT_EP2IN_SHIFT (5U) -#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) -#define USB_INTSTAT_EP3OUT_MASK (0x40U) -#define USB_INTSTAT_EP3OUT_SHIFT (6U) -#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) -#define USB_INTSTAT_EP3IN_MASK (0x80U) -#define USB_INTSTAT_EP3IN_SHIFT (7U) -#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) -#define USB_INTSTAT_EP4OUT_MASK (0x100U) -#define USB_INTSTAT_EP4OUT_SHIFT (8U) -#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) -#define USB_INTSTAT_EP4IN_MASK (0x200U) -#define USB_INTSTAT_EP4IN_SHIFT (9U) -#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) -#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) -#define USB_INTSTAT_FRAME_INT_SHIFT (30U) -#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) -#define USB_INTSTAT_DEV_INT_MASK (0x80000000U) -#define USB_INTSTAT_DEV_INT_SHIFT (31U) -#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) -/*! @} */ - -/*! @name INTEN - USB interrupt enable register */ -/*! @{ */ -#define USB_INTEN_EP_INT_EN_MASK (0x3FFU) -#define USB_INTEN_EP_INT_EN_SHIFT (0U) -#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) -#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) -#define USB_INTEN_FRAME_INT_EN_SHIFT (30U) -#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) -#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) -#define USB_INTEN_DEV_INT_EN_SHIFT (31U) -#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) -/*! @} */ - -/*! @name INTSETSTAT - USB set interrupt status register */ -/*! @{ */ -#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) -#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) -#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) -#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) -#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) -#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) -#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) -#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) -#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) -/*! @} */ - -/*! @name EPTOGGLE - USB Endpoint toggle register */ -/*! @{ */ -#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) -#define USB_EPTOGGLE_TOGGLE_SHIFT (0U) -#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_Register_Masks */ - - -/* USB - Peripheral instance base addresses */ -/** Peripheral USB0 base address */ -#define USB0_BASE (0x40084000u) -/** Peripheral USB0 base pointer */ -#define USB0 ((USB_Type *)USB0_BASE) -/** Array initializer of USB peripheral base addresses */ -#define USB_BASE_ADDRS { USB0_BASE } -/** Array initializer of USB peripheral base pointers */ -#define USB_BASE_PTRS { USB0 } -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { USB0_IRQn } -#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } - -/*! - * @} - */ /* end of group USB_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- UTICK Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer - * @{ - */ - -/** UTICK - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ - __IO uint32_t STAT; /**< Status register., offset: 0x4 */ - __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ - __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ - __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ -} UTICK_Type; - -/* ---------------------------------------------------------------------------- - -- UTICK Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup UTICK_Register_Masks UTICK Register Masks - * @{ - */ - -/*! @name CTRL - Control register. */ -/*! @{ */ -#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) -#define UTICK_CTRL_DELAYVAL_SHIFT (0U) -#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) -#define UTICK_CTRL_REPEAT_MASK (0x80000000U) -#define UTICK_CTRL_REPEAT_SHIFT (31U) -#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) -/*! @} */ - -/*! @name STAT - Status register. */ -/*! @{ */ -#define UTICK_STAT_INTR_MASK (0x1U) -#define UTICK_STAT_INTR_SHIFT (0U) -#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) -#define UTICK_STAT_ACTIVE_MASK (0x2U) -#define UTICK_STAT_ACTIVE_SHIFT (1U) -#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) -/*! @} */ - -/*! @name CFG - Capture configuration register. */ -/*! @{ */ -#define UTICK_CFG_CAPEN0_MASK (0x1U) -#define UTICK_CFG_CAPEN0_SHIFT (0U) -#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) -#define UTICK_CFG_CAPEN1_MASK (0x2U) -#define UTICK_CFG_CAPEN1_SHIFT (1U) -#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) -#define UTICK_CFG_CAPEN2_MASK (0x4U) -#define UTICK_CFG_CAPEN2_SHIFT (2U) -#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) -#define UTICK_CFG_CAPEN3_MASK (0x8U) -#define UTICK_CFG_CAPEN3_SHIFT (3U) -#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) -#define UTICK_CFG_CAPPOL0_MASK (0x100U) -#define UTICK_CFG_CAPPOL0_SHIFT (8U) -#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) -#define UTICK_CFG_CAPPOL1_MASK (0x200U) -#define UTICK_CFG_CAPPOL1_SHIFT (9U) -#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) -#define UTICK_CFG_CAPPOL2_MASK (0x400U) -#define UTICK_CFG_CAPPOL2_SHIFT (10U) -#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) -#define UTICK_CFG_CAPPOL3_MASK (0x800U) -#define UTICK_CFG_CAPPOL3_SHIFT (11U) -#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) -/*! @} */ - -/*! @name CAPCLR - Capture clear register. */ -/*! @{ */ -#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) -#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) -#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) -#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) -#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) -#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) -#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) -#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) -#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) -#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) -#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) -#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) -/*! @} */ - -/*! @name CAP - Capture register . */ -/*! @{ */ -#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) -#define UTICK_CAP_CAP_VALUE_SHIFT (0U) -#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) -#define UTICK_CAP_VALID_MASK (0x80000000U) -#define UTICK_CAP_VALID_SHIFT (31U) -#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) -/*! @} */ - -/* The count of UTICK_CAP */ -#define UTICK_CAP_COUNT (4U) - - -/*! - * @} - */ /* end of group UTICK_Register_Masks */ - - -/* UTICK - Peripheral instance base addresses */ -/** Peripheral UTICK0 base address */ -#define UTICK0_BASE (0x4000E000u) -/** Peripheral UTICK0 base pointer */ -#define UTICK0 ((UTICK_Type *)UTICK0_BASE) -/** Array initializer of UTICK peripheral base addresses */ -#define UTICK_BASE_ADDRS { UTICK0_BASE } -/** Array initializer of UTICK peripheral base pointers */ -#define UTICK_BASE_PTRS { UTICK0 } -/** Interrupt vectors for the UTICK peripheral type */ -#define UTICK_IRQS { UTICK0_IRQn } - -/*! - * @} - */ /* end of group UTICK_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- WWDT Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer - * @{ - */ - -/** WWDT - Register Layout Typedef */ -typedef struct { - __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ - __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ - __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ - __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ - uint8_t RESERVED_0[4]; - __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ - __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ -} WWDT_Type; - -/* ---------------------------------------------------------------------------- - -- WWDT Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup WWDT_Register_Masks WWDT Register Masks - * @{ - */ - -/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ -/*! @{ */ -#define WWDT_MOD_WDEN_MASK (0x1U) -#define WWDT_MOD_WDEN_SHIFT (0U) -/*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the watchdog timer will run permanently. - * 0b0..Stop. The watchdog timer is stopped. - * 0b1..Run. The watchdog timer is running. - */ -#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) -#define WWDT_MOD_WDRESET_MASK (0x2U) -#define WWDT_MOD_WDRESET_SHIFT (1U) -/*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. - * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. - * 0b1..Reset. A watchdog time-out will cause a chip reset. - */ -#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) -#define WWDT_MOD_WDTOF_MASK (0x4U) -#define WWDT_MOD_WDTOF_SHIFT (2U) -#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) -#define WWDT_MOD_WDINT_MASK (0x8U) -#define WWDT_MOD_WDINT_SHIFT (3U) -#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) -#define WWDT_MOD_WDPROTECT_MASK (0x10U) -#define WWDT_MOD_WDPROTECT_SHIFT (4U) -/*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. - * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. - * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. - */ -#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) -#define WWDT_MOD_LOCK_MASK (0x20U) -#define WWDT_MOD_LOCK_SHIFT (5U) -#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) -/*! @} */ - -/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ -/*! @{ */ -#define WWDT_TC_COUNT_MASK (0xFFFFFFU) -#define WWDT_TC_COUNT_SHIFT (0U) -#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) -/*! @} */ - -/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ -/*! @{ */ -#define WWDT_FEED_FEED_MASK (0xFFU) -#define WWDT_FEED_FEED_SHIFT (0U) -#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) -/*! @} */ - -/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ -/*! @{ */ -#define WWDT_TV_COUNT_MASK (0xFFFFFFU) -#define WWDT_TV_COUNT_SHIFT (0U) -#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) -/*! @} */ - -/*! @name WARNINT - Watchdog Warning Interrupt compare value. */ -/*! @{ */ -#define WWDT_WARNINT_WARNINT_MASK (0x3FFU) -#define WWDT_WARNINT_WARNINT_SHIFT (0U) -#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) -/*! @} */ - -/*! @name WINDOW - Watchdog Window compare value. */ -/*! @{ */ -#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) -#define WWDT_WINDOW_WINDOW_SHIFT (0U) -#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group WWDT_Register_Masks */ - - -/* WWDT - Peripheral instance base addresses */ -/** Peripheral WWDT base address */ -#define WWDT_BASE (0x4000C000u) -/** Peripheral WWDT base pointer */ -#define WWDT ((WWDT_Type *)WWDT_BASE) -/** Array initializer of WWDT peripheral base addresses */ -#define WWDT_BASE_ADDRS { WWDT_BASE } -/** Array initializer of WWDT peripheral base pointers */ -#define WWDT_BASE_PTRS { WWDT } -/** Interrupt vectors for the WWDT peripheral type */ -#define WWDT_IRQS { WDT_BOD_IRQn } - -/*! - * @} - */ /* end of group WWDT_Peripheral_Access_Layer */ - - -/* -** End of section using anonymous unions -*/ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop - #else - #pragma pop - #endif -#elif defined(__GNUC__) - /* leave anonymous unions enabled */ -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma language=default -#else - #error Not supported compiler type -#endif - -/*! - * @} - */ /* end of group Peripheral_access_layer */ - - -/* ---------------------------------------------------------------------------- - -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). - * @{ - */ - -#if defined(__ARMCC_VERSION) - #if (__ARMCC_VERSION >= 6010050) - #pragma clang system_header - #endif -#elif defined(__IAR_SYSTEMS_ICC__) - #pragma system_include -#endif - -/** - * @brief Mask and left-shift a bit field value for use in a register bit range. - * @param field Name of the register bit field. - * @param value Value of the bit field. - * @return Masked and shifted value. - */ -#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) -/** - * @brief Mask and right-shift a register value to extract a bit field value. - * @param field Name of the register bit field. - * @param value Value of the register. - * @return Masked and shifted bit field value. - */ -#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) - -/*! - * @} - */ /* end of group Bit_Field_Generic_Macros */ - - -/* ---------------------------------------------------------------------------- - -- SDK Compatibility - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SDK_Compatibility_Symbols SDK Compatibility - * @{ - */ - -/* No SDK compatibility issues. */ - -/*! - * @} - */ /* end of group SDK_Compatibility_Symbols */ - - -#endif /* _LPC51U68_H_ */ - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/LPC51U68_features.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/LPC51U68_features.h deleted file mode 100644 index ac3633f58..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/LPC51U68_features.h +++ /dev/null @@ -1,236 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.0, 2017-12-15 -** Build: b190225 -** -** Abstract: -** Chip specific module features. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2017-12-15) -** Initial version. -** -** ################################################################### -*/ - -#ifndef _LPC51U68_FEATURES_H_ -#define _LPC51U68_FEATURES_H_ - -/* SOC module features */ - -/* @brief ADC availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC_COUNT (1) -/* @brief ASYNC_SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (3) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (1) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (8) -/* @brief FMC availability on the SoC. */ -#define FSL_FEATURE_SOC_FMC_COUNT (1) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (8) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (2) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (8) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (8) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (1) - -/* ADC module features */ - -/* @brief Do not has input select (register INSEL). */ -#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) -/* @brief Has ASYNMODE bitfile in CTRL reigster. */ -#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) -/* @brief Has startup register. */ -#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) -/* @brief Has ADTrim register */ -#define FSL_FEATURE_ADC_HAS_TRIM_REG (0) -/* @brief Has Calibration register. */ -#define FSL_FEATURE_ADC_HAS_CALIB_REG (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (18) -/* @brief Align size of DMA descriptor */ -#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) -/* @brief DMA head link descriptor table align size */ -#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) - -/* FLEXCOMM module features */ - -/* @brief FLEXCOMM0 USART INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) -/* @brief FLEXCOMM0 SPI INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) -/* @brief FLEXCOMM0 I2C INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) -/* @brief FLEXCOMM1 USART INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) -/* @brief FLEXCOMM1 SPI INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) -/* @brief FLEXCOMM1 I2C INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) -/* @brief FLEXCOMM2 USART INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) -/* @brief FLEXCOMM2 SPI INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) -/* @brief FLEXCOMM2 I2C INDEX 2 */ -#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) -/* @brief FLEXCOMM3 USART INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) -/* @brief FLEXCOMM3 SPI INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) -/* @brief FLEXCOMM3 I2C INDEX 3 */ -#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) -/* @brief FLEXCOMM4 USART INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) -/* @brief FLEXCOMM4 SPI INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) -/* @brief FLEXCOMM4 I2C INDEX 4 */ -#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) -/* @brief FLEXCOMM5 USART INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) -/* @brief FLEXCOMM5 SPI INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) -/* @brief FLEXCOMM5 I2C INDEX 5 */ -#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) -/* @brief FLEXCOMM6 USART INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) -/* @brief FLEXCOMM6 SPI INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) -/* @brief FLEXCOMM6 I2C INDEX 6 */ -#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) -/* @brief FLEXCOMM7 I2S INDEX 0 */ -#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) -/* @brief FLEXCOMM7 USART INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) -/* @brief FLEXCOMM7 SPI INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) -/* @brief FLEXCOMM7 I2C INDEX 7 */ -#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) -/* @brief FLEXCOMM7 I2S INDEX 1 */ -#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) - -/* I2S module features */ - -/* @brief I2S support dual channel transfer */ -#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) -/* @brief I2S has DMIC interconnection */ -#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) - -/* MRT module features */ - -/* @brief number of channels. */ -#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) - -/* interrupt module features */ - -/* @brief Lowest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) -/* @brief Highest interrupt request number. */ -#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4) - -/* RTC module features */ - -/* @brief RTC has no reset control */ -#define FSL_FEATURE_RTC_HAS_NO_RESET (1) - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) -/* @brief Number of outputs */ -#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8) - -/* SYSCON module features */ - -/* @brief Pointer to ROM IAP entry functions */ -#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144) -/* @brief IAP has Flash read & write function */ -#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) -/* @brief IAP has read Flash signature function */ -#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (1) -/* @brief IAP has read extended Flash signature function */ -#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (0) - -/* SysTick module features */ - -/* @brief Systick has external reference clock. */ -#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) -/* @brief Systick external reference clock is core clock divided by this value. */ -#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) - -/* USB module features */ - -/* @brief Number of the endpoint in USB FS */ -#define FSL_FEATURE_USB_EP_NUM (5) - -#endif /* _LPC51U68_FEATURES_H_ */ - diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/fsl_device_registers.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/fsl_device_registers.h deleted file mode 100644 index 54354b263..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/fsl_device_registers.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __FSL_DEVICE_REGISTERS_H__ -#define __FSL_DEVICE_REGISTERS_H__ - -/* - * Include the cpu specific register header files. - * - * The CPU macro should be declared in the project or makefile. - */ -#if (defined(CPU_LPC51U68JBD48) || defined(CPU_LPC51U68JBD64)) - -#define LPC51U68_SERIES - -/* CMSIS-style register definitions */ -#include "LPC51U68.h" -/* CPU specific feature definitions */ -#include "LPC51U68_features.h" - -#else - #error "No valid CPU defined!" -#endif - -#endif /* __FSL_DEVICE_REGISTERS_H__ */ - -/******************************************************************************* - * EOF - ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/system_LPC51U68.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/system_LPC51U68.c deleted file mode 100644 index ce0256636..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/system_LPC51U68.c +++ /dev/null @@ -1,343 +0,0 @@ -/* -** ################################################################### -** Processors: LPC51U68JBD48 -** LPC51U68JBD64 -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 -** Version: rev. 1.0, 2017-12-15 -** Build: b180802 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2017-12-15) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file LPC51U68 - * @version 1.0 - * @date 2017-12-15 - * @brief Device specific configuration file for LPC51U68 (implementation file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#include -#include "fsl_device_registers.h" - -#define NVALMAX (0x100) -#define PVALMAX (0x20) -#define MVALMAX (0x8000) -#define PLL_SSCG0_MDEC_VAL_P (0) /* MDEC is in bits 16 downto 0 */ -#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ -#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P) - -extern void *__Vectors; - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - - -static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, - 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; - -static uint32_t GetWdtOscFreq(void) -{ - uint8_t freq_sel, div_sel; - div_sel = ((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1) << 1; - freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; - return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); -} - -/* Find decoded N value for raw NDEC value */ -static uint32_t pllDecodeN(uint32_t NDEC) -{ - uint32_t n, x, i; - - /* Find NDec */ - switch (NDEC) - { - case 0xFFF: - n = 0; - break; - case 0x302: - n = 1; - break; - case 0x202: - n = 2; - break; - default: - x = 0x080; - n = 0xFFFFFFFF; - for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F); - if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) - { - /* Decoded value of NDEC */ - n = i; - } - } - break; - } - return n; -} - -/* Find decoded P value for raw PDEC value */ -static uint32_t pllDecodeP(uint32_t PDEC) -{ - uint32_t p, x, i; - /* Find PDec */ - switch (PDEC) - { - case 0xFF: - p = 0; - break; - case 0x62: - p = 1; - break; - case 0x42: - p = 2; - break; - default: - x = 0x10; - p = 0xFFFFFFFF; - for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xF); - if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) - { - /* Decoded value of PDEC */ - p = i; - } - } - break; - } - return p; -} - -/* Find decoded M value for raw MDEC value */ -static uint32_t pllDecodeM(uint32_t MDEC) -{ - uint32_t m, i, x; - - /* Find MDec */ - switch (MDEC) - { - case 0xFFFFF: - m = 0; - break; - case 0x18003: - m = 1; - break; - case 0x10003: - m = 2; - break; - default: - x = 0x04000; - m = 0xFFFFFFFF; - for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFF)); i--) - { - x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF); - if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) - { - /* Decoded value of MDEC */ - m = i; - } - } - break; - } - return m; -} - -/* Get predivider (N) from PLL NDEC setting */ -static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0) - { - /* Decode NDEC value to get (N) pre divider */ - preDiv = pllDecodeN(nDecReg & 0x3FF); - if (preDiv == 0) - { - preDiv = 1; - } - } - /* Adjusted by 1, directi is used to bypass */ - return preDiv; -} - -/* Get postdivider (P) from PLL PDEC setting */ -static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) -{ - uint32_t postDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0) - { - /* Decode PDEC value to get (P) post divider */ - postDiv = 2 * pllDecodeP(pDecReg & 0x7F); - if (postDiv == 0) - { - postDiv = 2; - } - } - /* Adjusted by 1, directo is used to bypass */ - return postDiv; -} - -/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ -static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) -{ - uint32_t mMult = 1; - - /* Decode MDEC value to get (M) multiplier */ - mMult = pllDecodeM(mDecReg & 0x1FFFF); - /* Extra multiply by 2 needed? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK) == 0) - { - mMult = mMult << 1; - } - if (mMult == 0) - { - mMult = 1; - } - return mMult; -} - - - -/* ---------------------------------------------------------------------------- - -- Core clock - ---------------------------------------------------------------------------- */ - -uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; - -/* ---------------------------------------------------------------------------- - -- SystemInit() - ---------------------------------------------------------------------------- */ - -void SystemInit (void) { - -#if defined(__CODE_RED) - extern void(*const g_pfnVectors[]) (void); - SCB->VTOR = (uint32_t) &g_pfnVectors; -#else - extern void *__Vectors; - SCB->VTOR = (uint32_t) &__Vectors; -#endif - -} - -/* ---------------------------------------------------------------------------- - -- SystemCoreClockUpdate() - ---------------------------------------------------------------------------- */ - -void SystemCoreClockUpdate (void) { - uint32_t clkRate = 0; - uint32_t prediv, postdiv; - uint64_t workRate; - - switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) - { - case 0x00: /* MAINCLKSELA clock (main_clk_a)*/ - switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLK_FRO_12MHZ; - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = CLK_CLK_IN; - break; - case 0x02: /* Watchdog oscillator (wdt_clk) */ - clkRate = GetWdtOscFreq(); - break; - default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */ - if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) - { - clkRate = CLK_FRO_96MHZ; - } - else - { - clkRate = CLK_FRO_48MHZ; - } - break; - } - break; - case 0x02: /* System PLL clock (pll_clk)*/ - switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) - { - case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLK_FRO_12MHZ; - break; - case 0x01: /* CLKIN (clk_in) */ - clkRate = CLK_CLK_IN; - break; - case 0x02: /* Watchdog oscillator (wdt_clk) */ - clkRate = GetWdtOscFreq(); - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLK_RTC_32K_CLK; - break; - default: - break; - } - if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC); - postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC); - /* Adjust input clock */ - clkRate = clkRate / prediv; - /* If using the SS, use the multiplier */ - if (SYSCON->SYSPLLSSCTRL1 & SYSCON_SYSPLLSSCTRL1_PD_MASK) - { - /* MDEC used for rate */ - workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLSSCTRL0); - } - else - { - /* SS multipler used for rate */ - workRate = 0; - /* Adjust by fractional */ - workRate = workRate + ((clkRate * (uint64_t)((SYSCON->SYSPLLSSCTRL1 & 0x7FF) >> 0)) / 0x800); - } - clkRate = workRate / ((uint64_t)postdiv); - } - break; - case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLK_RTC_32K_CLK; - break; - default: - break; - } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); - -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/system_LPC51U68.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/system_LPC51U68.h deleted file mode 100644 index 23a14cc72..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/device/system_LPC51U68.h +++ /dev/null @@ -1,97 +0,0 @@ -/* -** ################################################################### -** Processors: LPC51U68JBD48 -** LPC51U68JBD64 -** -** Compilers: Keil ARM C/C++ Compiler -** GNU C Compiler -** IAR ANSI C/C++ Compiler for ARM -** MCUXpresso Compiler -** -** Reference manual: LPC51U68 User manual User manual Rev. 1.0 13 Dec 2017 -** Version: rev. 1.0, 2017-12-15 -** Build: b180802 -** -** Abstract: -** Provides a system configuration function and a global variable that -** contains the system frequency. It configures the device and initializes -** the oscillator (PLL) that is part of the microcontroller device. -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2017-12-15) -** Initial version. -** -** ################################################################### -*/ - -/*! - * @file LPC51U68 - * @version 1.0 - * @date 2017-12-15 - * @brief Device specific configuration file for LPC51U68 (header file) - * - * Provides a system configuration function and a global variable that contains - * the system frequency. It configures the device and initializes the oscillator - * (PLL) that is part of the microcontroller device. - */ - -#ifndef _SYSTEM_LPC51U68_H_ -#define _SYSTEM_LPC51U68_H_ /**< Symbol preventing repeated inclusion */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */ -#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */ -#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */ -#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */ -#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */ -#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */ - - -/** - * @brief System clock frequency (core clock) - * - * The system clock frequency supplied to the SysTick timer and the processor - * core clock. This variable can be used by the user application to setup the - * SysTick timer or configure other parameters. It may also be used by debugger to - * query the frequency of the debug timer or configure the trace clock speed - * SystemCoreClock is initialized with a correct predefined value. - */ -extern uint32_t SystemCoreClock; - -/** - * @brief Setup the microcontroller system. - * - * Typically this function configures the oscillator (PLL) that is part of the - * microcontroller device. For systems with variable clock speed it also updates - * the variable SystemCoreClock. SystemInit is called from startup_device file. - */ -void SystemInit (void); - -/** - * @brief Updates the SystemCoreClock variable. - * - * It must be called whenever the core clock is changed during program - * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates - * the current core clock. - */ -void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* _SYSTEM_LPC51U68_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_clock.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_clock.c deleted file mode 100644 index 96d1ec02e..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_clock.c +++ /dev/null @@ -1,1672 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2019 , NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_clock.h" -#include "fsl_power.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.clock" -#endif -#define NVALMAX (0x100U) -#define PVALMAX (0x20U) -#define MVALMAX (0x8000U) - -#define PLL_MAX_N_DIV 0x100U - -#define INDEX_SECTOR_TRIM48 ((uint32_t *)0x01000444U) -#define INDEX_SECTOR_TRIM96 ((uint32_t *)0x01000430U) -/*-------------------------------------------------------------------------- -!!! If required these #defines can be moved to chip library file -----------------------------------------------------------------------------*/ - -#define PLL_SSCG0_MDEC_VAL_P (0U) /* MDEC is in bits 16 downto 0 */ -#define PLL_SSCG0_MDEC_VAL_M (0x1FFFFUL << PLL_SSCG0_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ -#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P) - -#define PLL_MIN_CCO_FREQ_MHZ (75000000U) -#define PLL_MAX_CCO_FREQ_MHZ (150000000U) -#define PLL_LOWER_IN_LIMIT (4000U) /*!< Minimum PLL input rate */ -#define PLL_MIN_IN_SSMODE (2000000U) -#define PLL_MAX_IN_SSMODE (4000000U) - -/* Middle of the range values for spread-spectrum */ -#define PLL_SSCG_MF_FREQ_VALUE 4U -#define PLL_SSCG_MC_COMP_VALUE 2U -#define PLL_SSCG_MR_DEPTH_VALUE 4U -#define PLL_SSCG_DITHER_VALUE 0U - -/* PLL NDEC reg */ -#define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) -/* PLL PDEC reg */ -#define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) -/* SSCG control0 */ -#define PLL_SSCG0_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_SSCG0_MDEC_VAL_P) & PLL_SSCG0_MDEC_VAL_M) - -/* SSCG control1 */ -#define PLL_SSCG1_MD_FRACT_P 0U -#define PLL_SSCG1_MD_INT_P 11U -#define PLL_SSCG1_MD_FRACT_M (0x7FFUL << PLL_SSCG1_MD_FRACT_P) -#define PLL_SSCG1_MD_INT_M (0xFFUL << PLL_SSCG1_MD_INT_P) - -#define PLL_SSCG1_MD_FRACT_SET(value) (((unsigned long)(value) << PLL_SSCG1_MD_FRACT_P) & PLL_SSCG1_MD_FRACT_M) -#define PLL_SSCG1_MD_INT_SET(value) (((unsigned long)(value) << PLL_SSCG1_MD_INT_P) & PLL_SSCG1_MD_INT_M) - -/* Saved value of PLL output rate, computed whenever needed to save run-time - computation on each call to retrive the PLL rate. */ -static uint32_t s_Pll_Freq; - -uint32_t g_I2S_Mclk_Freq = 0U; - -/** External clock rate on the CLKIN pin in Hz. If not used, - set this to 0. Otherwise, set it to the exact rate in Hz this pin is - being driven at. */ -const uint32_t g_Ext_Clk_Freq = 0U; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/* Find encoded NDEC value for raw N value, max N = NVALMAX */ -static uint32_t pllEncodeN(uint32_t N); -/* Find decoded N value for raw NDEC value */ -static uint32_t pllDecodeN(uint32_t NDEC); -/* Find encoded PDEC value for raw P value, max P = PVALMAX */ -static uint32_t pllEncodeP(uint32_t P); -/* Find decoded P value for raw PDEC value */ -static uint32_t pllDecodeP(uint32_t PDEC); -/* Find encoded MDEC value for raw M value, max M = MVALMAX */ -static uint32_t pllEncodeM(uint32_t M); -/* Find decoded M value for raw MDEC value */ -static uint32_t pllDecodeM(uint32_t MDEC); -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR); -/* Get predivider (N) from PLL NDEC setting */ -static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg); -/* Get postdivider (P) from PLL PDEC setting */ -static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg); -/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ -static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg); -/* Get the greatest common divisor */ -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPllConfig( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS); -/* Update local PLL rate variable */ -static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup); - -static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, - 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; -/******************************************************************************* - * Code - ******************************************************************************/ - -/** - * brief Configure the clock selection muxes. - * param connection : Clock to be configured. - * return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection) -{ - uint8_t mux; - uint8_t sel; - uint16_t item; - uint32_t tmp32 = (uint32_t)connection; - uint32_t i; - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->MAINCLKSELA); - - if (kNONE_to_NONE != connection) - { - for (i = 0U; i < 2U; i++) - { - if (tmp32 == 0U) - { - break; - } - item = (uint16_t)GET_ID_ITEM(tmp32); - if (item) - { - mux = GET_ID_ITEM_MUX(item); - sel = GET_ID_ITEM_SEL(item); - if (mux == CM_ASYNCAPB) - { - ASYNC_SYSCON->ASYNCAPBCLKSELA = sel; - } - else - { - pClkSel[mux] = sel; - } - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ - } - } -} - -/* Return the actual clock attach id */ -/** - * brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * param attachId : Clock attach id to get. - * return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) -{ - uint8_t mux; - uint8_t actualSel; - uint32_t tmp32 = (uint32_t)attachId; - uint32_t i; - uint32_t actualAttachId = 0U; - uint32_t selector = GET_ID_SELECTOR(tmp32); - volatile uint32_t *pClkSel; - - pClkSel = &(SYSCON->MAINCLKSELA); - - if (kNONE_to_NONE == attachId) - { - return kNONE_to_NONE; - } - - for (i = 0U; i < 2U; i++) - { - mux = GET_ID_ITEM_MUX(tmp32); - if (tmp32) - { - if (mux == CM_ASYNCAPB) - { - actualSel = ASYNC_SYSCON->ASYNCAPBCLKSELA; - } - else - { - actualSel = pClkSel[mux]; - } - - /* Consider the combination of two registers */ - actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); - } - tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ - } - - actualAttachId |= selector; - - return (clock_attach_id_t)actualAttachId; -} - -/** - * brief Setup peripheral clock dividers. - * param div_name : Clock divider name - * param divided_by_value: Value to be divided - * param reset : Whether to reset the divider counter. - * return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) -{ - volatile uint32_t *pClkDiv; - - pClkDiv = &(SYSCON->SYSTICKCLKDIV); - if (reset) - { - pClkDiv[div_name] = 1U << 29U; - } - if (divided_by_value == 0U) /* halt */ - { - pClkDiv[div_name] = 1U << 30U; - } - else - { - pClkDiv[div_name] = (divided_by_value - 1U); - } -} - -/* Set FRO Clocking */ -/** - * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) - * return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq) -{ - uint32_t usb_adj; - if ((iFreq != 12000000U) && (iFreq != 48000000U) && (iFreq != 96000000U)) - { - return kStatus_Fail; - } - /* Power up the FRO and set this as the base clock */ - POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); - /* back up the value of whether USB adj is selected, in which case we will have a value of 1 else 0 */ - usb_adj = ((SYSCON->FROCTRL) & SYSCON_FROCTRL_USBCLKADJ_MASK) >> SYSCON_FROCTRL_USBCLKADJ_SHIFT; - if (iFreq > 12000000U) - { - if (iFreq == 96000000U) - { - SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM96) | - SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | - SYSCON_FROCTRL_HSPDCLK(1); - } - else - { - SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM48) | - SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | - SYSCON_FROCTRL_HSPDCLK(1); - } - } - else - { - SYSCON->FROCTRL &= ~SYSCON_FROCTRL_HSPDCLK(1); - } - - return 0U; -} - -/*! brief Return Frequency of FRO 12MHz - * return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void) -{ - return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U; -} - -/*! brief Return Frequency of External Clock - * return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void) -{ - return (g_Ext_Clk_Freq); -} -/*! brief Return Frequency of Watchdog Oscillator - * return Frequency of Watchdog Oscillator - */ -uint32_t CLOCK_GetWdtOscFreq(void) -{ - uint8_t freq_sel, div_sel; - if (SYSCON->PDRUNCFG[0] & (1UL << (kPDRUNCFG_PD_WDT_OSC & 0xffU))) - { - return 0U; - } - else - { - div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1; - freq_sel = - wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; - return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel); - } -} - -/*! brief Return Frequency of High-Freq output of FRO - * return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void) -{ - return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? - 0 : - !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ? - 0 : - (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ? 96000000U : 48000000U; -} - -/*! brief Return Frequency of PLL - * return Frequency of PLL - */ -uint32_t CLOCK_GetPllOutFreq(void) -{ - return s_Pll_Freq; -} - -/*! brief Return Frequency of 32kHz osc - * return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void) -{ - return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */ -} -/*! brief Return Frequency of Core System - * return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void) -{ - return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ? - CLOCK_GetFro12MFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ? - CLOCK_GetExtClkFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ? - CLOCK_GetWdtOscFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ? - CLOCK_GetFroHfFreq() : - (SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() : - (SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U; -} -/*! brief Return Frequency of I2S MCLK Clock - * return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void) -{ - return g_I2S_Mclk_Freq; -} - -/*! brief Return Frequency of Asynchronous APB Clock - * return Frequency of Asynchronous APB Clock Clock - */ -uint32_t CLOCK_GetAsyncApbClkFreq(void) -{ - async_clock_src_t clkSrc; - uint32_t clkRate; - - clkSrc = CLOCK_GetAsyncApbClkSrc(); - - switch (clkSrc) - { - case kCLOCK_AsyncMainClk: - clkRate = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_AsyncFro12Mhz: - clkRate = CLK_FRO_12MHZ; - break; - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/*! brief Return Frequency of Flexcomm functional Clock - * return Frequency of Flexcomm functional Clock - */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) -{ - return (SYSCON->FXCOMCLKSEL[id] == 0U) ? - CLOCK_GetFro12MFreq() : - (SYSCON->FXCOMCLKSEL[id] == 1U) ? - CLOCK_GetFroHfFreq() : - (SYSCON->FXCOMCLKSEL[id] == 2U) ? - CLOCK_GetPllOutFreq() : - (SYSCON->FXCOMCLKSEL[id] == 3U) ? CLOCK_GetI2SMClkFreq() : - (SYSCON->FXCOMCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U; -} - -/* Get ADC Clk */ -/*! brief Return Frequency of Adc Clock - * return Frequency of Adc Clock. - */ -uint32_t CLOCK_GetAdcClkFreq(void) -{ - uint32_t freq = 0U; - - switch (SYSCON->ADCCLKSEL) - { - case 0U: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case 1U: - freq = CLOCK_GetPllOutFreq(); - break; - case 2U: - freq = CLOCK_GetFroHfFreq(); - break; - case 7U: - freq = 0U; - break; - default: - break; - } - - return freq / ((SYSCON->ADCCLKDIV & 0xffU) + 1U); -} - -/*! brief Return Input frequency for the Fractional baud rate generator - * return Input Frequency for FRG - */ -uint32_t CLOCK_GetFRGInputClock(void) -{ - return (SYSCON->FRGCLKSEL == 0U) ? - CLOCK_GetCoreSysClkFreq() : - (SYSCON->FRGCLKSEL == 1U) ? - CLOCK_GetPllOutFreq() : - (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : - (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U; -} - -/*! brief Set output of the Fractional baud rate generator - * param freq : Desired output frequency - * return Error Code 0 - fail 1 - success - */ -uint32_t CLOCK_SetFRGClock(uint32_t freq) -{ - uint32_t input = CLOCK_GetFRGInputClock(); - uint32_t mul; - - if ((freq > 48000000) || (freq > input) || (input / freq >= 2)) - { - /* FRG output frequency should be less than equal to 48MHz */ - return 0; - } - else - { - mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); - SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK; - return 1; - } -} - -/*! brief Return Frequency of selected clock - * return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName) -{ - uint32_t freq; - switch (clockName) - { - case kCLOCK_CoreSysClk: - freq = CLOCK_GetCoreSysClkFreq(); - break; - case kCLOCK_BusClk: - freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_FroHf: - freq = CLOCK_GetFroHfFreq(); - break; - case kCLOCK_Fro12M: - freq = CLOCK_GetFro12MFreq(); - break; - case kCLOCK_PllOut: - freq = CLOCK_GetPllOutFreq(); - break; - case kCLOCK_UsbClk: - freq = (SYSCON->USBCLKSEL == 0U) ? CLOCK_GetFroHfFreq() : - (SYSCON->USBCLKSEL == 1) ? CLOCK_GetPllOutFreq() : 0U; - freq = freq / ((SYSCON->USBCLKDIV & 0xffU) + 1U); - break; - case kCLOCK_WdtOsc: - freq = CLOCK_GetWdtOscFreq(); - break; - case kCLOCK_Frg: - freq = ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK) ? - ((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) / - ((SYSCON_FRGCTRL_DIV_MASK + 1) + - ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)) : - 0; - break; - - case kCLOCK_AsyncApbClk: - freq = CLOCK_GetAsyncApbClkFreq(); - break; - - case kCLOCK_FlexI2S: - freq = CLOCK_GetI2SMClkFreq(); - break; - - case kCLOCK_Flexcomm0: - freq = CLOCK_GetFlexCommClkFreq(0U); - break; - case kCLOCK_Flexcomm1: - freq = CLOCK_GetFlexCommClkFreq(1U); - break; - case kCLOCK_Flexcomm2: - freq = CLOCK_GetFlexCommClkFreq(2U); - break; - case kCLOCK_Flexcomm3: - freq = CLOCK_GetFlexCommClkFreq(3U); - break; - case kCLOCK_Flexcomm4: - freq = CLOCK_GetFlexCommClkFreq(4U); - break; - case kCLOCK_Flexcomm5: - freq = CLOCK_GetFlexCommClkFreq(5U); - break; - case kCLOCK_Flexcomm6: - freq = CLOCK_GetFlexCommClkFreq(6U); - break; - case kCLOCK_Flexcomm7: - freq = CLOCK_GetFlexCommClkFreq(7U); - break; - default: - freq = 0U; - break; - } - - return freq; -} - -/* Set the FLASH wait states for the passed frequency */ -/** - * brief Set the flash wait states for the input freuqency. - * param iFreq : Input frequency - * return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) -{ - if (iFreq <= 12000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash1Cycle); - } - else if (iFreq <= 24000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash2Cycle); - } - else if (iFreq <= 48000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash3Cycle); - } - else if (iFreq <= 72000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash4Cycle); - } - else if (iFreq <= 84000000U) - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash5Cycle); - } - else - { - CLOCK_SetFLASHAccessCycles(kCLOCK_Flash6Cycle); - } -} - -/* Find encoded NDEC value for raw N value, max N = NVALMAX */ -static uint32_t pllEncodeN(uint32_t N) -{ - uint32_t x, i; - - /* Find NDec */ - switch (N) - { - case 0U: - x = 0x3FFU; - break; - - case 1U: - x = 0x302U; - break; - - case 2U: - x = 0x202U; - break; - - default: - x = 0x080U; - for (i = N; i <= NVALMAX; i++) - { - x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); - } - break; - } - - return x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P); -} - -/* Find decoded N value for raw NDEC value */ -static uint32_t pllDecodeN(uint32_t NDEC) -{ - uint32_t n, x, i; - - /* Find NDec */ - switch (NDEC) - { - case 0x3FFU: - n = 0U; - break; - - case 0x302U: - n = 1U; - break; - - case 0x202U: - n = 2U; - break; - - default: - x = 0x080U; - n = 0xFFFFFFFFU; - for (i = NVALMAX; ((i >= 3U) && (n == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 2U) ^ (x >> 3U) ^ (x >> 4U)) & 1U) << 7U) | ((x >> 1U) & 0x7FU); - if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC) - { - /* Decoded value of NDEC */ - n = i; - } - } - break; - } - - return n; -} - -/* Find encoded PDEC value for raw P value, max P = PVALMAX */ -static uint32_t pllEncodeP(uint32_t P) -{ - uint32_t x, i; - - /* Find PDec */ - switch (P) - { - case 0U: - x = 0x7FU; - break; - - case 1U: - x = 0x62U; - break; - - case 2U: - x = 0x42U; - break; - - default: - x = 0x10U; - for (i = P; i <= PVALMAX; i++) - { - x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); - } - break; - } - - return x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P); -} - -/* Find decoded P value for raw PDEC value */ -static uint32_t pllDecodeP(uint32_t PDEC) -{ - uint32_t p, x, i; - - /* Find PDec */ - switch (PDEC) - { - case 0x7FU: - p = 0U; - break; - - case 0x62U: - p = 1U; - break; - - case 0x42U: - p = 2U; - break; - - default: - x = 0x10U; - p = 0xFFFFFFFFU; - for (i = PVALMAX; ((i >= 3U) && (p == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 2U)) & 1U) << 4U) | ((x >> 1U) & 0xFU); - if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC) - { - /* Decoded value of PDEC */ - p = i; - } - } - break; - } - - return p; -} - -/* Find encoded MDEC value for raw M value, max M = MVALMAX */ -static uint32_t pllEncodeM(uint32_t M) -{ - uint32_t i, x; - - /* Find MDec */ - switch (M) - { - case 0U: - x = 0x1FFFFU; - break; - - case 1U: - x = 0x18003U; - break; - - case 2U: - x = 0x10003U; - break; - - default: - x = 0x04000U; - for (i = M; i <= MVALMAX; i++) - { - x = (((x ^ (x >> 1U)) & 1U) << 14U) | ((x >> 1U) & 0x3FFFU); - } - break; - } - - return x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P); -} - -/* Find decoded M value for raw MDEC value */ -static uint32_t pllDecodeM(uint32_t MDEC) -{ - uint32_t m, i, x; - - /* Find MDec */ - switch (MDEC) - { - case 0x1FFFFU: - m = 0U; - break; - - case 0x18003U: - m = 1U; - break; - - case 0x10003U: - m = 2U; - break; - - default: - x = 0x04000U; - m = 0xFFFFFFFFU; - for (i = MVALMAX; ((i >= 3U) && (m == 0xFFFFFFFFU)); i--) - { - x = (((x ^ (x >> 1U)) & 1) << 14U) | ((x >> 1U) & 0x3FFFU); - if ((x & (PLL_SSCG0_MDEC_VAL_M >> PLL_SSCG0_MDEC_VAL_P)) == MDEC) - { - /* Decoded value of MDEC */ - m = i; - } - } - break; - } - - return m; -} - -/* Find SELP, SELI, and SELR values for raw M value, max M = MVALMAX */ -static void pllFindSel(uint32_t M, bool bypassFBDIV2, uint32_t *pSelP, uint32_t *pSelI, uint32_t *pSelR) -{ - /* bandwidth: compute selP from Multiplier */ - if (M < 60U) - { - *pSelP = (M >> 1U) + 1U; - } - else - { - *pSelP = PVALMAX - 1U; - } - - /* bandwidth: compute selI from Multiplier */ - if (M > 16384U) - { - *pSelI = 1U; - } - else if (M > 8192U) - { - *pSelI = 2U; - } - else if (M > 2048U) - { - *pSelI = 4U; - } - else if (M >= 501U) - { - *pSelI = 8U; - } - else if (M >= 60U) - { - *pSelI = 4U * (1024U / (M + 9U)); - } - else - { - *pSelI = (M & 0x3CU) + 4U; - } - - if (*pSelI > ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT)) - { - *pSelI = ((0x3FUL << SYSCON_SYSPLLCTRL_SELI_SHIFT) >> SYSCON_SYSPLLCTRL_SELI_SHIFT); - } - - *pSelR = 0U; -} - -/* Get predivider (N) from PLL NDEC setting */ -static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg) -{ - uint32_t preDiv = 1; - - /* Direct input is not used? */ - if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) == 0U) - { - /* Decode NDEC value to get (N) pre divider */ - preDiv = pllDecodeN(nDecReg & 0x3FFU); - if (preDiv == 0U) - { - preDiv = 1U; - } - } - - /* Adjusted by 1, directi is used to bypass */ - return preDiv; -} - -/* Get postdivider (P) from PLL PDEC setting */ -static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) -{ - uint32_t postDiv = 1U; - - /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U) - { - /* Decode PDEC value to get (P) post divider */ - postDiv = 2U * pllDecodeP(pDecReg & 0x7FU); - if (postDiv == 0U) - { - postDiv = 2U; - } - } - - /* Adjusted by 1, directo is used to bypass */ - return postDiv; -} - -/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */ -static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) -{ - uint32_t mMult = 1U; - - /* Decode MDEC value to get (M) multiplier */ - mMult = pllDecodeM(mDecReg & 0x1FFFFU); - - /* Extra multiply by 2 needed? */ - if ((ctrlReg & (SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK)) == 0U) - { - mMult = mMult << 1U; - } - - if (mMult == 0U) - { - mMult = 1U; - } - - return mMult; -} - -static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) -{ - uint32_t tmp; - - while (n != 0U) - { - tmp = n; - n = m % n; - m = tmp; - } - - return m; -} - -/* - * Set PLL output based on desired output rate. - * In this function, the it calculates the PLL setting for output frequency from input clock - * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. - * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. - */ -static pll_error_t CLOCK_GetPllConfigInternal( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) -{ - uint32_t nDivOutHz, fccoHz, multFccoDiv; - uint32_t pllPreDivider, pllMultiplier, pllBypassFBDIV2, pllPostDivider; - uint32_t pllDirectInput, pllDirectOutput; - uint32_t pllSelP, pllSelI, pllSelR, bandsel, uplimoff; - - /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 0U; /* 0 implies post-divider will be disabled */ - pllDirectOutput = 1U; - if (useFeedbackDiv2) - { - /* Using feedback divider for M, so disable bypass */ - pllBypassFBDIV2 = 0U; - } - else - { - pllBypassFBDIV2 = 1U; - } - multFccoDiv = (2U - pllBypassFBDIV2); - - /* Verify output rate parameter */ - if (foutHz > PLL_MAX_CCO_FREQ_MHZ) - { - /* Maximum PLL output with post divider=1 cannot go above this frequency */ - return kStatus_PLL_OutputTooHigh; - } - if (foutHz < (PLL_MIN_CCO_FREQ_MHZ / (PVALMAX << 1U))) - { - /* Minmum PLL output with maximum post divider cannot go below this frequency */ - return kStatus_PLL_OutputTooLow; - } - - /* If using SS mode, input clock needs to be between 2MHz and 4MHz */ - if (useSS) - { - /* Verify input rate parameter */ - if (finHz < PLL_MIN_IN_SSMODE) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - /* PLL input in SS mode must be under 4MHz */ - pllPreDivider = finHz / ((PLL_MIN_IN_SSMODE + PLL_MAX_IN_SSMODE) / 2); - if (pllPreDivider > NVALMAX) - { - return kStatus_PLL_InputTooHigh; - } - } - else - { - /* Verify input rate parameter */ - if (finHz < PLL_LOWER_IN_LIMIT) - { - /* Input clock into the PLL cannot be lower than this */ - return kStatus_PLL_InputTooLow; - } - } - - /* Find the optimal CCO frequency for the output and input that - will keep it inside the PLL CCO range. This may require - tweaking the post-divider for the PLL. */ - fccoHz = foutHz; - while (fccoHz < PLL_MIN_CCO_FREQ_MHZ) - { - /* CCO output is less than minimum CCO range, so the CCO output - needs to be bumped up and the post-divider is used to bring - the PLL output back down. */ - pllPostDivider++; - if (pllPostDivider > PVALMAX) - { - return kStatus_PLL_OutsideIntLimit; - } - - /* Target CCO goes up, PLL output goes down */ - fccoHz = foutHz * (pllPostDivider * 2U); - pllDirectOutput = 0U; - } - - /* Determine if a pre-divider is needed to get the best frequency */ - if ((finHz > PLL_LOWER_IN_LIMIT) && (fccoHz >= finHz) && (useSS == false)) - { - uint32_t a = FindGreatestCommonDivisor(fccoHz, (multFccoDiv * finHz)); - - if (a > 20000U) - { - a = (multFccoDiv * finHz) / a; - if ((a != 0U) && (a < PLL_MAX_N_DIV)) - { - pllPreDivider = a; - } - } - } - - /* Bypass pre-divider hardware if pre-divider is 1 */ - if (pllPreDivider > 1U) - { - pllDirectInput = 0U; - } - else - { - pllDirectInput = 1U; - } - - /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); - pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv; - - /* Find optimal values for filter */ - if (useSS == false) - { - /* Will bumping up M by 1 get us closer to the desired CCO frequency? */ - if ((nDivOutHz * ((multFccoDiv * pllMultiplier * 2U) + 1U)) < (fccoHz * 2U)) - { - pllMultiplier++; - } - - /* Setup filtering */ - pllFindSel(pllMultiplier, pllBypassFBDIV2, &pllSelP, &pllSelI, &pllSelR); - bandsel = 1U; - uplimoff = 0U; - - /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->syspllssctrl[0] = - (PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) | (1U << SYSCON_SYSPLLSSCTRL0_SEL_EXT_SHIFT)); - - /* Power down SSC, not used */ - pSetup->syspllssctrl[1] = (1U << SYSCON_SYSPLLSSCTRL1_PD_SHIFT); - } - else - { - uint64_t fc; - - /* Filtering will be handled by SSC */ - pllSelR = pllSelI = pllSelP = 0U; - bandsel = 0U; - uplimoff = 1U; - - /* The PLL multiplier will get very close and slightly under the - desired target frequency. A small fractional component can be - added to fine tune the frequency upwards to the target. */ - fc = ((uint64_t)(fccoHz % (multFccoDiv * nDivOutHz)) << 11U) / (multFccoDiv * nDivOutHz); - - /* MDEC set by SSC */ - pSetup->syspllssctrl[0U] = 0U; - - /* Set multiplier */ - pSetup->syspllssctrl[1] = PLL_SSCG1_MD_INT_SET(pllMultiplier) | PLL_SSCG1_MD_FRACT_SET((uint32_t)fc); - } - - /* Get encoded values for N (prediv) and P (postdiv) */ - pSetup->syspllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider)); - pSetup->syspllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider)); - - /* PLL control */ - pSetup->syspllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) | /* Filter coefficient */ - (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) | /* Filter coefficient */ - (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) | /* Filter coefficient */ - (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) | /* PLL bypass mode disabled */ - (pllBypassFBDIV2 << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT) | /* Extra M / 2 divider? */ - (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) | /* SS/fractional mode disabled */ - (bandsel << SYSCON_SYSPLLCTRL_BANDSEL_SHIFT) | /* Manual bandwidth selection enabled */ - (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */ - (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */ - - return kStatus_PLL_Success; -} - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) -/* Alloct the static buffer for cache. */ -pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; -uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -bool gUseFeedbackDiv2Cache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; -bool gUseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; -uint32_t gPllSetupCacheIdx = 0U; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - -/* - * Calculate the PLL setting values from input clock freq to output freq. - */ -static pll_error_t CLOCK_GetPllConfig( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) -{ - pll_error_t retErr; -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - uint32_t i; - - for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) - { - if ((finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]) && (useFeedbackDiv2 == gUseFeedbackDiv2Cache[i]) && - (useSS == gUseSSCache[i])) - { - /* Hit the target in cache buffer. */ - pSetup->syspllctrl = gPllSetupCacheStruct[i].syspllctrl; - pSetup->syspllndec = gPllSetupCacheStruct[i].syspllndec; - pSetup->syspllpdec = gPllSetupCacheStruct[i].syspllpdec; - pSetup->syspllssctrl[0] = gPllSetupCacheStruct[i].syspllssctrl[0]; - pSetup->syspllssctrl[1] = gPllSetupCacheStruct[i].syspllssctrl[1]; - retErr = kStatus_PLL_Success; - break; - } - } - - if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - { - return retErr; - } -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup, useFeedbackDiv2, useSS); - -#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) - /* Cache the most recent calulation result into buffer. */ - gFinHzCache[gPllSetupCacheIdx] = finHz; - gFoutHzCache[gPllSetupCacheIdx] = foutHz; - gUseFeedbackDiv2Cache[gPllSetupCacheIdx] = useFeedbackDiv2; - gUseSSCache[gPllSetupCacheIdx] = useSS; - - gPllSetupCacheStruct[gPllSetupCacheIdx].syspllctrl = pSetup->syspllctrl; - gPllSetupCacheStruct[gPllSetupCacheIdx].syspllndec = pSetup->syspllndec; - gPllSetupCacheStruct[gPllSetupCacheIdx].syspllpdec = pSetup->syspllpdec; - gPllSetupCacheStruct[gPllSetupCacheIdx].syspllssctrl[0] = pSetup->syspllssctrl[0]; - gPllSetupCacheStruct[gPllSetupCacheIdx].syspllssctrl[1] = pSetup->syspllssctrl[1]; - /* Update the index for next available buffer. */ - gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; -#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ - - return retErr; -} - -/* Update local PLL rate variable */ -static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup) -{ - s_Pll_Freq = CLOCK_GetSystemPLLOutFromSetup(pSetup); -} - -/* Return System PLL input clock rate */ -/*! brief Return System PLL input clock rate - * return System PLL input clock rate - */ -uint32_t CLOCK_GetSystemPLLInClockRate(void) -{ - uint32_t clkRate = 0U; - - switch ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)) - { - case 0x00U: - clkRate = CLK_FRO_12MHZ; - break; - - case 0x01U: - clkRate = CLOCK_GetExtClkFreq(); - break; - - case 0x02U: - clkRate = CLOCK_GetWdtOscFreq(); - break; - - case 0x03U: - clkRate = CLOCK_GetOsc32KFreq(); - break; - - default: - clkRate = 0U; - break; - } - - return clkRate; -} - -/* Return System PLL output clock rate from setup structure */ -/*! brief Return System PLL output clock rate from setup structure - * param pSetup : Pointer to a PLL setup structure - * return System PLL output clock rate calculated from the setup structure - */ -uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) -{ - uint32_t prediv, postdiv, mMult, inPllRate; - uint64_t workRate; - - /* Get the input clock frequency of PLL. */ - inPllRate = CLOCK_GetSystemPLLInClockRate(); - - /* - * If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock. - */ - if ((pSetup->syspllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U) - { - /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */ - /* - * 1. Pre-divider - * Pre-divider is only available when the DIRECTI is disabled. - */ - if (0U == (pSetup->syspllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK)) - { - prediv = findPllPreDiv(pSetup->syspllctrl, pSetup->syspllndec); - } - else - { - prediv = 1U; /* The pre-divider is bypassed. */ - } - /* Adjust input clock */ - inPllRate = inPllRate / prediv; - - /* - * 2. M divider - * If using the SS, use the multiplier. - */ - if (pSetup->syspllssctrl[1] & (SYSCON_SYSPLLSSCTRL1_PD_MASK)) - { - /* MDEC used for rate */ - mMult = findPllMMult(pSetup->syspllctrl, pSetup->syspllssctrl[0]); - workRate = (uint64_t)inPllRate * (uint64_t)mMult; - } - else - { - uint64_t fract; - - /* SS multipler used for rate */ - mMult = (pSetup->syspllssctrl[1] & PLL_SSCG1_MD_INT_M) >> PLL_SSCG1_MD_INT_P; - workRate = (uint64_t)inPllRate * (uint64_t)mMult; - - /* Adjust by fractional */ - fract = (uint64_t)(pSetup->syspllssctrl[1] & PLL_SSCG1_MD_FRACT_M) >> PLL_SSCG1_MD_FRACT_P; - workRate = workRate + ((inPllRate * fract) / 0x800U); - } - - /* - * 3. Post-divider - * Post-divider is only available when the DIRECTO is disabled. - */ - if (0U == (pSetup->syspllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK)) - { - postdiv = findPllPostDiv(pSetup->syspllctrl, pSetup->syspllpdec); - } - else - { - postdiv = 1U; /* The post-divider is bypassed. */ - } - workRate = workRate / ((uint64_t)postdiv); - } - else - { - /* In bypass mode */ - workRate = (uint64_t)inPllRate; - } - - return (uint32_t)workRate; -} - -/* Set the current PLL Rate */ -/*! brief Store the current PLL rate - * param rate: Current rate of the PLL - * return Nothing - **/ -void CLOCK_SetStoredPLLClockRate(uint32_t rate) -{ - s_Pll_Freq = rate; -} - -/* Return System PLL output clock rate */ -/*! brief Return System PLL output clock rate - * param recompute : Forces a PLL rate recomputation if true - * return System PLL output clock rate - * note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) -{ - pll_setup_t Setup; - uint32_t rate; - - if ((recompute) || (s_Pll_Freq == 0U)) - { - Setup.syspllctrl = SYSCON->SYSPLLCTRL; - Setup.syspllndec = SYSCON->SYSPLLNDEC; - Setup.syspllpdec = SYSCON->SYSPLLPDEC; - Setup.syspllssctrl[0] = SYSCON->SYSPLLSSCTRL0; - Setup.syspllssctrl[1] = SYSCON->SYSPLLSSCTRL1; - - CLOCK_GetSystemPLLOutFromSetupUpdate(&Setup); - } - - rate = s_Pll_Freq; - - return rate; -} - -/* Set PLL output based on the passed PLL setup data */ -/*! brief Set PLL output based on the passed PLL setup data - * param pControl : Pointer to populated PLL control structure to generate setup with - * param pSetup : Pointer to PLL setup structure to be filled - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) -{ - uint32_t inRate; - bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); - bool useFbDiv2; - - pll_error_t pllError; - - /* Determine input rate for the PLL */ - if ((pControl->flags & PLL_CONFIGFLAG_USEINRATE) != 0U) - { - inRate = pControl->inputRate; - } - else - { - inRate = CLOCK_GetSystemPLLInClockRate(); - } - - if ((pSetup->flags & PLL_SETUPFLAG_USEFEEDBACKDIV2) != 0U) - { - useFbDiv2 = true; - } - else - { - useFbDiv2 = false; - } - - /* PLL flag options */ - pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup, useFbDiv2, useSS); - if ((useSS) && (pllError == kStatus_PLL_Success)) - { - /* If using SS mode, then some tweaks are made to the generated setup */ - pSetup->syspllssctrl[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; - if (pControl->mfDither) - { - pSetup->syspllssctrl[1] |= (1U << SYSCON_SYSPLLSSCTRL1_DITHER_SHIFT); - } - } - - return pllError; -} - -/* Set PLL output from PLL setup structure */ -/*! brief Set PLL output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * param flagcfg : Flag configuration for PLL config structure - * return PLL_ERROR_SUCCESS on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) -{ - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); - - pSetup->flags = flagcfg; - - /* Write PLL setup data */ - SYSCON->SYSPLLCTRL = pSetup->syspllctrl; - SYSCON->SYSPLLNDEC = pSetup->syspllndec; - SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ - SYSCON->SYSPLLPDEC = pSetup->syspllpdec; - SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ - SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0]; - SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */ - SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1]; - SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1] | (1U << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT); /* latch */ - - /* Flags for lock or power on */ - if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U) - { - /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ - volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ - uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U); - - /* Initialize and power up PLL */ - SYSCON->SYSPLLSSCTRL0 = maxCCO; - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - - /* Set mreq to activate */ - SYSCON->SYSPLLSSCTRL0 = maxCCO | (1U << 17U); - - /* Delay for 72 uSec @ 12Mhz */ - for (delayX = 0U; delayX < 172U; ++delayX) - { - } - - /* clear mreq to prepare for restoring mreq */ - SYSCON->SYSPLLSSCTRL0 = curSSCTRL; - - /* set original value back and activate */ - SYSCON->SYSPLLSSCTRL0 = curSSCTRL | (1U << 17U); - - /* Enable peripheral states by setting low */ - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - } - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - while (CLOCK_IsSystemPLLLocked() == false) - { - } - } - - /* Update current programmed PLL rate var */ - CLOCK_GetSystemPLLOutFromSetupUpdate(pSetup); - - /* System voltage adjustment, occurs prior to setting main system clock */ - if ((pSetup->flags & PLL_SETUPFLAG_ADGVOLT) != 0U) - { - POWER_SetVoltageForFreq(s_Pll_Freq); - } - - return kStatus_PLL_Success; -} - -/* Setup PLL Frequency from pre-calculated value */ -/** - * brief Set PLL output from PLL setup structure (precise frequency) - * param pSetup : Pointer to populated PLL setup structure - * return kStatus_PLL_Success on success, or PLL setup error code - * note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) -{ - /* Power off PLL during setup changes */ - POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); - - /* Write PLL setup data */ - SYSCON->SYSPLLCTRL = pSetup->syspllctrl; - SYSCON->SYSPLLNDEC = pSetup->syspllndec; - SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ - SYSCON->SYSPLLPDEC = pSetup->syspllpdec; - SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ - SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0]; - SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */ - SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1]; - SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1] | (1U << SYSCON_SYSPLLSSCTRL1_MDREQ_SHIFT); /* latch */ - - /* Flags for lock or power on */ - if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) - { - /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ - volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ - uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U); - - /* Initialize and power up PLL */ - SYSCON->SYSPLLSSCTRL0 = maxCCO; - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - - /* Set mreq to activate */ - SYSCON->SYSPLLSSCTRL0 = maxCCO | (1U << 17U); - - /* Delay for 72 uSec @ 12Mhz */ - for (delayX = 0U; delayX < 172U; ++delayX) - { - } - - /* clear mreq to prepare for restoring mreq */ - SYSCON->SYSPLLSSCTRL0 = curSSCTRL; - - /* set original value back and activate */ - SYSCON->SYSPLLSSCTRL0 = curSSCTRL | (1U << 17U); - - /* Enable peripheral states by setting low */ - POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); - } - if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) - { - while (CLOCK_IsSystemPLLLocked() == false) - { - } - } - - /* Update current programmed PLL rate var */ - s_Pll_Freq = pSetup->pllRate; - - return kStatus_PLL_Success; -} - -/* Set System PLL clock based on the input frequency and multiplier */ -/*! brief Set PLL output based on the multiplier and input frequency - * param multiply_by : multiplier - * param input_freq : Clock input frequency of the PLL - * return Nothing - * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this - * function does not disable or enable PLL power, wait for PLL lock, - * or adjust system voltages. These must be done in the application. - * The function will not alter any source clocks (ie, main systen clock) - * that may use the PLL, so these should be setup prior to and after - * exiting the function. - */ -void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) -{ - uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1U; - uint32_t selr; - uint32_t seli; - uint32_t selp; - uint32_t mdec, ndec; - - uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1); - - while (cco_freq < 75000000U) - { - multiply_by <<= 1U; /* double value in each iteration */ - pdec <<= 1U; /* correspondingly double pdec to cancel effect of double msel */ - cco_freq = input_freq * multiply_by; - } - selr = 0U; - if (multiply_by < 60U) - { - seli = (multiply_by & 0x3cU) + 4U; - selp = (multiply_by >> 1U) + 1U; - } - else - { - selp = 31U; - if (multiply_by > 16384U) - { - seli = 1U; - } - else if (multiply_by > 8192U) - { - seli = 2U; - } - else if (multiply_by > 2048U) - { - seli = 4U; - } - else if (multiply_by >= 501U) - { - seli = 8U; - } - else - { - seli = 4U * (1024U / (multiply_by + 9U)); - } - } - - if (pdec > 1U) - { - directo = 0U; /* use post divider */ - pdec = pdec / 2U; /* Account for minus 1 encoding */ - /* Translate P value */ - switch (pdec) - { - case 1U: - pdec = 0x62U; /* 1 * 2 */ - break; - case 2U: - pdec = 0x42U; /* 2 * 2 */ - break; - case 4U: - pdec = 0x02U; /* 4 * 2 */ - break; - case 8U: - pdec = 0x0bU; /* 8 * 2 */ - break; - case 16U: - pdec = 0x11U; /* 16 * 2 */ - break; - case 32U: - pdec = 0x08U; /* 32 * 2 */ - break; - default: - pdec = 0x08U; - break; - } - } - - mdec = PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(multiply_by)); - ndec = 0x302U; /* pre divide by 1 (hardcoded) */ - - SYSCON->SYSPLLCTRL = SYSCON_SYSPLLCTRL_BANDSEL(1) | directo | SYSCON_SYSPLLCTRL_BYPASSCCODIV2(1) | - (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) | - (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT); - SYSCON->SYSPLLPDEC = pdec | (1U << 7U); /* set Pdec value and assert preq */ - SYSCON->SYSPLLNDEC = ndec | (1U << 10U); /* set Pdec value and assert preq */ - SYSCON->SYSPLLSSCTRL0 = - (1U << 18U) | (1U << 17U) | mdec; /* select non sscg MDEC value, assert mreq and select mdec value */ -} -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) -{ - bool ret = true; - - CLOCK_DisableClock(kCLOCK_Usbd0); - - if (kCLOCK_UsbSrcFro == src) - { - switch (freq) - { - case 96000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsbClk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ - break; - case 48000000U: - CLOCK_SetClkDiv(kCLOCK_DivUsbClk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ - break; - default: - ret = false; - break; - } - /* Turn ON FRO HF and let it adjust TRIM value based on USB SOF */ - SYSCON->FROCTRL = (SYSCON->FROCTRL & ~((0x01U << 15U) | (0xFU << 26U))) | SYSCON_FROCTRL_HSPDCLK_MASK | - SYSCON_FROCTRL_USBCLKADJ_MASK; - /* select FRO 96 or 48 MHz */ - CLOCK_AttachClk(kFRO_HF_to_USB_CLK); - } - else - { - /*TODO , we only implement FRO as usb clock source*/ - ret = false; - } - - CLOCK_EnableClock(kCLOCK_Usbd0); - - return ret; -} - -/*! - * brief Delay at least for several microseconds. - * Please note that, this API will calculate the microsecond period with the maximum devices - * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise - * delay count was needed, please implement a new timer count to achieve this function. - * - * param delay_us Delay time in unit of microsecond. - */ -__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us) -{ - assert(0U != delay_us); - - uint32_t count = (uint32_t)USEC_TO_COUNT(delay_us, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - - /* - * Calculate the real delay count depend on the excute instructions cycles, - * users can change the divider value to adapt to the real IDE optimise level. - */ - count = (count / 4U); - - for (; count > 0UL; count--) - { - __NOP(); - } -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_clock.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_clock.h deleted file mode 100644 index 697440948..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_clock.h +++ /dev/null @@ -1,850 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016 - 2019 , NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CLOCK_H_ -#define _FSL_CLOCK_H_ - -#include "fsl_common.h" - -/*! @addtogroup clock */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - *****************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.2.0. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) -/*@}*/ - -/* Definition for delay API in clock driver, users can redefine it to the real application. */ -#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY -#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (96000000UL) -#endif - -/*! - * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. - * - * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function - * would cache the recent calulation and accelerate the execution to get the - * right settings. - */ -#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT -#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U -#endif - -/*! @brief Clock ip name array for FLEXCOMM. */ -#define FLEXCOMM_CLOCKS \ - { \ - kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ - kCLOCK_FlexComm6, kCLOCK_FlexComm7 \ - } -/*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ - kCLOCK_MinUart6, kCLOCK_MinUart7 \ - } - -/*! @brief Clock ip name array for BI2C. */ -#define BI2C_CLOCKS \ - { \ - kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \ - } -/*! @brief Clock ip name array for LSPI. */ -#define LPSI_CLOCKS \ - { \ - kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \ - } -/*! @brief Clock ip name array for FLEXI2S. */ -#define FLEXI2S_CLOCKS \ - { \ - kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ - kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ - } -/*! @brief Clock ip name array for UTICK. */ -#define UTICK_CLOCKS \ - { \ - kCLOCK_Utick \ - } -/*! @brief Clock ip name array for DMA. */ -#define DMA_CLOCKS \ - { \ - kCLOCK_Dma \ - } -/*! @brief Clock ip name array for CT32B. */ -#define CTIMER_CLOCKS \ - { \ - kCLOCK_Ctimer0, kCLOCK_Ctimer1, kCLOCK_Ctimer3 \ - } - -/*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0, kCLOCK_Gpio1 \ - } -/*! @brief Clock ip name array for ADC. */ -#define ADC_CLOCKS \ - { \ - kCLOCK_Adc0 \ - } -/*! @brief Clock ip name array for MRT. */ -#define MRT_CLOCKS \ - { \ - kCLOCK_Mrt \ - } -/*! @brief Clock ip name array for MRT. */ -#define SCT_CLOCKS \ - { \ - kCLOCK_Sct0 \ - } -/*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc \ - } -/*! @brief Clock ip name array for WWDT. */ -#define WWDT_CLOCKS \ - { \ - kCLOCK_Wwdt \ - } -/*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc \ - } -/*! @brief Clock ip name array for USBD. */ -#define USBD_CLOCKS \ - { \ - kCLOCK_Usbd0 \ - } - -/*! @brief Clock ip name array for GINT. GINT0 & GINT1 share same slot */ -#define GINT_CLOCKS \ - { \ - kCLOCK_Gint, kCLOCK_Gint \ - } - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -/*------------------------------------------------------------------------------ - clock_ip_name_t definition: -------------------------------------------------------------------------------*/ - -#define CLK_GATE_REG_OFFSET_SHIFT 8U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU - -#define CLK_GATE_DEFINE(reg_offset, bit_shift) \ - ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ - (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK)) - -#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT) -#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT) - -#define AHB_CLK_CTRL0 0 -#define AHB_CLK_CTRL1 1 -#define ASYNC_CLK_CTRL0 2 - -/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ -typedef enum _clock_ip_name -{ - kCLOCK_IpInvalid = 0U, - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot */ - kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), - kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), - kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), - kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), - kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), - kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), - kCLOCK_Ctimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), - kCLOCK_Ctimer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), - - kCLOCK_Ctimer3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13), -} clock_ip_name_t; - -/*! @brief Clock name used to get clock frequency. */ -typedef enum _clock_name -{ - kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */ - kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ - kCLOCK_FroHf, /*!< FRO48/96 */ - kCLOCK_Fro12M, /*!< FRO12M */ - kCLOCK_ExtClk, /*!< External Clock */ - kCLOCK_PllOut, /*!< PLL Output */ - kCLOCK_UsbClk, /*!< USB input */ - kCLOCK_WdtOsc, /*!< Watchdog Oscillator */ - kCLOCK_Frg, /*!< Frg Clock */ - kCLOCK_AsyncApbClk, /*!< Async APB clock */ - kCLOCK_FlexI2S, /*!< FlexI2S clock */ - kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */ - kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */ - kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */ - kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */ - kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */ - kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */ - kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */ - kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */ -} clock_name_t; - -/** - * Clock source selections for the asynchronous APB clock - */ -typedef enum _async_clock_src -{ - kCLOCK_AsyncMainClk = 0, /*!< Main System clock */ - kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */ -} async_clock_src_t; - -/*! @brief Clock Mux Switches - * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable - * starting from LSB upwards - * - * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* - * - */ - -#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U)) -#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U) -#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U)) - -#define GET_ID_ITEM(connection) ((connection)&0xFFFU) -#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) -#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU) -#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U) -#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) - -#define CM_MAINCLKSELA 0 -#define CM_MAINCLKSELB 1 -#define CM_CLKOUTCLKSELA 2 -#define CM_CLKOUTCLKSELB 3 -#define CM_SYSPLLCLKSEL 4 -#define CM_USBPLLCLKSEL 5 -#define CM_AUDPLLCLKSEL 6 -#define CM_SCTPLLCLKSEL 7 -#define CM_ADCASYNCCLKSEL 9 -#define CM_USBCLKSEL 10 -#define CM_USB1CLKSEL 11 -#define CM_FXCOMCLKSEL0 12 -#define CM_FXCOMCLKSEL1 13 -#define CM_FXCOMCLKSEL2 14 -#define CM_FXCOMCLKSEL3 15 -#define CM_FXCOMCLKSEL4 16 -#define CM_FXCOMCLKSEL5 17 -#define CM_FXCOMCLKSEL6 18 -#define CM_FXCOMCLKSEL7 19 -#define CM_FXCOMCLKSEL8 20 -#define CM_FXCOMCLKSEL9 21 -#define CM_FXCOMCLKSEL10 22 -#define CM_FXCOMCLKSEL11 23 -#define CM_FXI2S0MCLKCLKSEL 24 -#define CM_FXI2S1MCLKCLKSEL 25 -#define CM_FRGCLKSEL 26 - -#define CM_ASYNCAPB 28 - -typedef enum _clock_attach_id -{ - - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), - kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), - kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), - - kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), - kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), - kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), - kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), - kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), - - kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), - kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), - - kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), - kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), - kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), - kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), - - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), - kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), - kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), - kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), - kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), - - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), - kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), - kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), - kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), - kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), - - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), - kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), - kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), - kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), - kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), - - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), - kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), - kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), - kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), - kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), - - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), - kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), - kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), - kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), - kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), - - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), - kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), - kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), - kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), - kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), - - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), - kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), - kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), - kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), - kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), - - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), - kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), - kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), - kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), - kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), - - kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), - kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), - kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), - kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), - kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), - - kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0), - kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1), - kMAIN_CLK_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 2), - kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7), - - kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0), - kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1), - kMAIN_CLK_to_USB_CLK = MUX_A(CM_USBCLKSEL, 2), - kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7), - - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), - kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), - kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), - kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), - kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), - kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), - kNONE_to_NONE = (int)0x80000000U, -} clock_attach_id_t; - -/* Clock dividers */ -typedef enum _clock_div_name -{ - kCLOCK_DivSystickClk = 0, - kCLOCK_DivTraceClk = 1, - kCLOCK_DivAhbClk = 32, - kCLOCK_DivClkOut = 33, - kCLOCK_DivAdcAsyncClk = 37, - kCLOCK_DivUsbClk = 38, - kCLOCK_DivFrg = 40, - kCLOCK_DivFxI2s0MClk = 43 -} clock_div_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -static inline void CLOCK_EnableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - if (index < 2) - { - SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - } - else - { - ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - } -} - -static inline void CLOCK_DisableClock(clock_ip_name_t clk) -{ - uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - if (index < 2) - { - SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - } - else - { - ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - } -} -/** - * @brief FLASH Access time definitions - */ -typedef enum _clock_flashtim -{ - kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clock */ - kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */ - kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */ - kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */ - kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */ - kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */ -} clock_flashtim_t; - -/** - * @brief Set FLASH memory access time in clocks - * @param clks : Clock cycles for FLASH access - * @return Nothing - */ -static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks) -{ - uint32_t tmp; - - tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK); - - /* Don't alter lower bits */ - SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT); -} - -/** - * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). - * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is - * enabled. - * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) - * @return returns success or fail status. - */ -status_t CLOCK_SetupFROClocking(uint32_t iFreq); -/** - * @brief Configure the clock selection muxes. - * @param connection : Clock to be configured. - * @return Nothing - */ -void CLOCK_AttachClk(clock_attach_id_t connection); -/** - * @brief Get the actual clock attach id. - * This fuction uses the offset in input attach id, then it reads the actual source value in - * the register and combine the offset to obtain an actual attach id. - * @param attachId : Clock attach id to get. - * @return Clock source value. - */ -clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); -/** - * @brief Setup peripheral clock dividers. - * @param div_name : Clock divider name - * @param divided_by_value: Value to be divided - * @param reset : Whether to reset the divider counter. - * @return Nothing - */ -void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset); -/** - * @brief Set the flash wait states for the input freuqency. - * @param iFreq : Input frequency - * @return Nothing - */ -void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); -/*! @brief Return Frequency of selected clock - * @return Frequency of selected clock - */ -uint32_t CLOCK_GetFreq(clock_name_t clockName); - -/*! @brief Return Input frequency for the Fractional baud rate generator - * @return Input Frequency for FRG - */ -uint32_t CLOCK_GetFRGInputClock(void); - -/*! @brief Set output of the Fractional baud rate generator - * @param freq : Desired output frequency - * @return Error Code 0 - fail 1 - success - */ -uint32_t CLOCK_SetFRGClock(uint32_t freq); - -/*! @brief Return Frequency of FRO 12MHz - * @return Frequency of FRO 12MHz - */ -uint32_t CLOCK_GetFro12MFreq(void); -/*! @brief Return Frequency of External Clock - * @return Frequency of External Clock. If no external clock is used returns 0. - */ -uint32_t CLOCK_GetExtClkFreq(void); -/*! @brief Return Frequency of Watchdog Oscillator - * @return Frequency of Watchdog Oscillator - */ -uint32_t CLOCK_GetWdtOscFreq(void); -/*! @brief Return Frequency of High-Freq output of FRO - * @return Frequency of High-Freq output of FRO - */ -uint32_t CLOCK_GetFroHfFreq(void); -/*! @brief Return Frequency of PLL - * @return Frequency of PLL - */ -uint32_t CLOCK_GetPllOutFreq(void); -/*! @brief Return Frequency of 32kHz osc - * @return Frequency of 32kHz osc - */ -uint32_t CLOCK_GetOsc32KFreq(void); -/*! @brief Return Frequency of Core System - * @return Frequency of Core System - */ -uint32_t CLOCK_GetCoreSysClkFreq(void); -/*! @brief Return Frequency of I2S MCLK Clock - * @return Frequency of I2S MCLK Clock - */ -uint32_t CLOCK_GetI2SMClkFreq(void); -/*! @brief Return Frequency of Flexcomm functional Clock - * @return Frequency of Flexcomm functional Clock - */ -uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); -/*! @brief Return Frequency of Adc Clock - * @return Frequency of Adc Clock. - */ -uint32_t CLOCK_GetAdcClkFreq(void); -/*! @brief Return Asynchronous APB Clock source - * @return Asynchronous APB CLock source - */ -__STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void) -{ - return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3); -} -/*! @brief Return Frequency of Asynchronous APB Clock - * @return Frequency of Asynchronous APB Clock Clock - */ -uint32_t CLOCK_GetAsyncApbClkFreq(void); -/*! @brief Return System PLL input clock rate - * @return System PLL input clock rate - */ -uint32_t CLOCK_GetSystemPLLInClockRate(void); - -/*! @brief Return System PLL output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return System PLL output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute); - -/*! @brief Enables and disables PLL bypass mode - * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass - * @return System PLL output clock rate - */ -__STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass) -{ - if (bypass) - { - SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); - } - else - { - SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT); - } -} - -/*! @brief Check if PLL is locked or not - * @return true if the PLL is locked, false if not locked - */ -__STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void) -{ - return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0); -} - -/*! @brief Store the current PLL rate - * @param rate: Current rate of the PLL - * @return Nothing - **/ -void CLOCK_SetStoredPLLClockRate(uint32_t rate); - -/*! @brief PLL configuration structure flags for 'flags' field - * These flags control how the PLL configuration function sets up the PLL setup structure.
- * - * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the - * configuration structure must be assigned with the expected PLL frequency. If the - * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration - * function and the driver will determine the PLL rate from the currently selected - * PLL source. This flag might be used to configure the PLL input clock more accurately - * when using the WDT oscillator or a more dyanmic CLKIN source.
- * - * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the - * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider - * are not used.
- */ -#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ -#define PLL_CONFIGFLAG_FORCENOFRACT \ - (1 \ - << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \ - \ \ \ \ - \ \ \ \ \ \ - \ \ \ \ \ \ \ \ - \ \ \ \ \ \ \ \ \ \ - \ \ \ \ \ \ \ \ \ \ \ \ - hardware */ - -/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency - * See (MF) field in the SYSPLLSSCTRL1 register in the UM. - */ -typedef enum _ss_progmodfm -{ - kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */ - kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ - kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ - kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ - kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ - kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ - kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ - kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ -} ss_progmodfm_t; - -/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth - * See (MR) field in the SYSPLLSSCTRL1 register in the UM. - */ -typedef enum _ss_progmoddp -{ - kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ - kSS_MR_K1 = (1 << 23), /*!< k = 1 */ - kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ - kSS_MR_K2 = (3 << 23), /*!< k = 2 */ - kSS_MR_K3 = (4 << 23), /*!< k = 3 */ - kSS_MR_K4 = (5 << 23), /*!< k = 4 */ - kSS_MR_K6 = (6 << 23), /*!< k = 6 */ - kSS_MR_K8 = (7 << 23) /*!< k = 8 */ -} ss_progmoddp_t; - -/*! @brief PLL Spread Spectrum (SS) Modulation waveform control - * See (MC) field in the SYSPLLSSCTRL1 register in the UM.
- * Compensation for low pass filtering of the PLL to get a triangular - * modulation at the output of the PLL, giving a flat frequency spectrum. - */ -typedef enum _ss_modwvctrl -{ - kSS_MC_NOC = (0 << 26), /*!< no compensation */ - kSS_MC_RECC = (2 << 26), /*!< recommended setting */ - kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ -} ss_modwvctrl_t; - -/*! @brief PLL configuration structure - * - * This structure can be used to configure the settings for a PLL - * setup structure. Fill in the desired configuration for the PLL - * and call the PLL setup function to fill in a PLL setup structure. - */ -typedef struct _pll_config -{ - uint32_t desiredRate; /*!< Desired PLL rate in Hz */ - uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */ - uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */ - ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - ss_modwvctrl_t - ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */ - bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using - PLL_CONFIGFLAG_FORCENOFRACT flag */ - -} pll_config_t; - -/*! @brief PLL setup structure flags for 'flags' field - * These flags control how the PLL setup function sets up the PLL - */ -#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ -#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */ - -/*! @brief PLL setup structure - * This structure can be used to pre-build a PLL setup configuration - * at run-time and quickly set the PLL to the configuration. It can be - * populated with the PLL setup function. If powering up or waiting - * for PLL lock, the PLL input clock source should be configured prior - * to PLL setup. - */ -typedef struct _pll_setup -{ - uint32_t syspllctrl; /*!< PLL control register SYSPLLCTRL */ - uint32_t syspllndec; /*!< PLL NDEC register SYSPLLNDEC */ - uint32_t syspllpdec; /*!< PLL PDEC register SYSPLLPDEC */ - uint32_t syspllssctrl[2]; /*!< PLL SSCTL registers SYSPLLSSCTRL */ - uint32_t pllRate; /*!< Acutal PLL rate */ - uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ -} pll_setup_t; - -/*! @brief PLL status definitions - */ -typedef enum _pll_error -{ - kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ - kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ - kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ - kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ - kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ - kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */ -} pll_error_t; - -/*! @brief USB clock source definition. */ -typedef enum _clock_usb_src -{ - kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */ - kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */ - kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ - kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL( - 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */ -} clock_usb_src_t; - -/*! @brief Return System PLL output clock rate from setup structure - * @param pSetup : Pointer to a PLL setup structure - * @return System PLL output clock rate calculated from the setup structure - */ -uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup); - -/*! @brief Set PLL output based on the passed PLL setup data - * @param pControl : Pointer to populated PLL control structure to generate setup with - * @param pSetup : Pointer to PLL setup structure to be filled - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note Actual frequency for setup may vary from the desired frequency based on the - * accuracy of input clocks, rounding, non-fractional PLL mode, etc. - */ -pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup); - -/*! @brief Set PLL output from PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure - * @param flagcfg : Flag configuration for PLL config structure - * @return PLL_ERROR_SUCCESS on success, or PLL setup error code - * @note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); - -/** - * @brief Set PLL output from PLL setup structure (precise frequency) - * @param pSetup : Pointer to populated PLL setup structure - * @return kStatus_PLL_Success on success, or PLL setup error code - * @note This function will power off the PLL, setup the PLL with the - * new setup data, and then optionally powerup the PLL, wait for PLL lock, - * and adjust system voltages to the new PLL rate. The function will not - * alter any source clocks (ie, main systen clock) that may use the PLL, - * so these should be setup prior to and after exiting the function. - */ -pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup); - -/*! @brief Set PLL output based on the multiplier and input frequency - * @param multiply_by : multiplier - * @param input_freq : Clock input frequency of the PLL - * @return Nothing - * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this - * function does not disable or enable PLL power, wait for PLL lock, - * or adjust system voltages. These must be done in the application. - * The function will not alter any source clocks (ie, main systen clock) - * that may use the PLL, so these should be setup prior to and after - * exiting the function. - */ -void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq); - -/*! @brief Disable USB FS clock. - * - * Disable USB FS clock. - */ -static inline void CLOCK_DisableUsbfs0Clock(void) -{ - CLOCK_DisableClock(kCLOCK_Usbd0); -} -bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); - -/*! - * @brief Use DWT to delay at least for some time. - * Please note that, this API will calculate the microsecond period with the maximum devices - * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise - * delay count was needed, please implement a new timer count to achieve this function. - * - * @param delay_us Delay time in unit of microsecond. - */ -void SDK_DelayAtLeastUs(uint32_t delay_us); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_CLOCK_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_common.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_common.c deleted file mode 100644 index 9ecb8385d..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_common.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#define SDK_MEM_MAGIC_NUMBER 12345U - -typedef struct _mem_align_control_block -{ - uint16_t identifier; /*!< Identifier for the memory control block. */ - uint16_t offset; /*!< offset from aligned address to real address */ -} mem_align_cb_t; - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.common" -#endif - -#ifndef __GIC_PRIO_BITS -#if defined(ENABLE_RAM_VECTOR_TABLE) -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif - - return ret; -} -#endif /* ENABLE_RAM_VECTOR_TABLE. */ -#endif /* __GIC_PRIO_BITS. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) -#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1u << intNumber; - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERCLR[index] = 1u << intNumber; -} -#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - -void *SDK_Malloc(size_t size, size_t alignbytes) -{ - mem_align_cb_t *p_cb = NULL; - uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); - void *p_align_addr, *p_addr = malloc(alignedsize); - - if (!p_addr) - { - return NULL; - } - - p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); - - p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U); - p_cb->identifier = SDK_MEM_MAGIC_NUMBER; - p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; - - return (void *)p_align_addr; -} - -void SDK_Free(void *ptr) -{ - mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U); - - if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) - { - return; - } - - free((void *)((uint32_t)ptr - p_cb->offset)); -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_common.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_common.h deleted file mode 100644 index a29c9e78c..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_common.h +++ /dev/null @@ -1,597 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_COMMON_H_ -#define _FSL_COMMON_H_ - -#include -#include -#include -#include -#include - -#if defined(__ICCARM__) -#include -#endif - -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Construct the version number for drivers. */ -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) - -/*! @name Driver version */ -/*@{*/ -/*! @brief common driver version 2.0.1. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -/* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ - -/*! @brief Status group numbers. */ -enum _status_groups -{ - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ - kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ - kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ - kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ - kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ - kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ - kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ - kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ - kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ - kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ - kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ - kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ - kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ - kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ - - kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ - kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ - kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ - kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ - kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ - kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ - kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ - kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ - kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ - kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ - kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ - kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ - kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ - kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ - kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ - kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ - kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ - kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ - kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ - kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ - kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ - kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ -}; - -/*! @brief Generic status return codes. */ -enum _generic_status -{ - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), - kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), -}; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; - -/* - * Macro guard for whether to use default weak IRQ implementation in drivers - */ -#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 -#endif - -/*! @name Min/max macros */ -/* @{ */ -#if !defined(MIN) -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) -#endif - -#if !defined(MAX) -#define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#endif -/* @} */ - -/*! @brief Computes the number of elements in an array. */ -#if !defined(ARRAY_SIZE) -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) -#endif - -/*! @name UINT16_MAX/UINT32_MAX value */ -/* @{ */ -#if !defined(UINT16_MAX) -#define UINT16_MAX ((uint16_t)-1) -#endif - -#if !defined(UINT32_MAX) -#define UINT32_MAX ((uint32_t)-1) -#endif -/* @} */ - -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) -/* @} */ - -/*! @name Alignment variable definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -/** - * Workaround to disable MISRA C message suppress warnings for IAR compiler. - * http://supp.iar.com/Support/?note=24725 - */ -_Pragma("diag_suppress=Pm120") -#define SDK_PRAGMA(x) _Pragma(#x) - _Pragma("diag_error=Pm120") -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var -#endif -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var -#endif -#elif defined(__GNUC__) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) -#endif -#else -#error Toolchain not supported -#define SDK_ALIGN(var, alignbytes) var -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var -#endif -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var -#endif -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) -/* @} */ - -/*! @name Non-cacheable region definition macros */ -/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or - * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, - * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables - * will be initialized to zero in system startup. - */ -/* @{ */ -#if (defined(__ICCARM__)) -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) -#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#endif -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var -#endif -#elif(defined(__GNUC__)) -/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" - * in your projects to make sure the non-cacheable section variables will be initialized in system startup. - */ -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) -#endif -#else -#error Toolchain not supported. -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var -#endif -/* @} */ - -/*! @name Time sensitive region */ -/* @{ */ -#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -#else -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#else -#error Toolchain not supported. -#endif -#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ -/* @} */ - -/*! @name Ram Function */ -#if (defined(__ICCARM__)) -#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#elif(defined(__GNUC__)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -/* @} */ - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) - extern "C" -{ -#endif - - /*! - * @brief Enable specific interrupt. - * - * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt enabled successfully - * @retval kStatus_Fail Failed to enable the interrupt - */ - static inline status_t EnableIRQ(IRQn_Type interrupt) - { - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } -#endif - -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - return kStatus_Success; - } - - /*! - * @brief Disable specific interrupt. - * - * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt disabled successfully - * @retval kStatus_Fail Failed to disable the interrupt - */ - static inline status_t DisableIRQ(IRQn_Type interrupt) - { - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } -#endif - -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - return kStatus_Success; - } - - /*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ - static inline uint32_t DisableGlobalIRQ(void) - { -#if defined (__XCC__) - return 0; -#else -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif -#endif - } - - /*! - * @brief Enable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ - static inline void EnableGlobalIRQ(uint32_t primask) - { -#if defined (__XCC__) -#else -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif -#endif - } - -#if defined(ENABLE_RAM_VECTOR_TABLE) - /*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ - uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); -#endif /* ENABLE_RAM_VECTOR_TABLE. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - /*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ - void EnableDeepSleepIRQ(IRQn_Type interrupt); - - /*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ - void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - - /*! - * @brief Allocate memory with given alignment and aligned size. - * - * This is provided to support the dynamically allocated memory - * used in cache-able region. - * @param size The length required to malloc. - * @param alignbytes The alignment size. - * @retval The allocated memory. - */ - void *SDK_Malloc(size_t size, size_t alignbytes); - - /*! - * @brief Free memory. - * - * @param ptr The memory to be release. - */ - void SDK_Free(void *ptr); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_COMMON_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_ctimer.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_ctimer.c deleted file mode 100644 index 96e997253..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_ctimer.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_ctimer.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.ctimer" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Gets the instance from the base address - * - * @param base Ctimer peripheral base address - * - * @return The Timer instance - */ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Pointers to Timer bases for each instance. */ -static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Pointers to Timer clocks for each instance. */ -static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_CTIMER_WRITE_ZERO_ASSERT_RESET -/*! @brief Pointers to Timer resets for each instance, writing a zero asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS_N; -#else -/*! @brief Pointers to Timer resets for each instance, writing a one asserts the reset */ -static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; -#endif -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/*! @brief Pointers real ISRs installed by drivers for each instance. */ -static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0}; - -/*! @brief Callback type installed by drivers for each instance. */ -static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback}; - -/*! @brief Array to map timer instance to IRQ number. */ -static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; - -/******************************************************************************* - * Code - ******************************************************************************/ -static uint32_t CTIMER_GetInstance(CTIMER_Type *base) -{ - uint32_t instance; - uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])); - - /* Find the instance index from base address mappings. */ - for (instance = 0; instance < ctimerArrayCount; instance++) - { - if (s_ctimerBases[instance] == base) - { - break; - } - } - - assert(instance < ctimerArrayCount); - - return instance; -} - -/*! - * brief Ungates the clock and configures the peripheral for basic operation. - * - * note This API should be called at the beginning of the application before using the driver. - * - * param base Ctimer peripheral base address - * param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) -{ - assert(config); - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the timer clock*/ - CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -/* Reset the module. */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_RESET) && (FSL_FEATURE_CTIMER_HAS_NO_RESET)) - RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]); -#endif -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -/* Setup the cimer mode and count select */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input); -#endif - /* Setup the timer prescale value */ - base->PR = CTIMER_PR_PRVAL(config->prescale); -} - -/*! - * brief Gates the timer clock. - * - * param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base) -{ - uint32_t index = CTIMER_GetInstance(base); - /* Stop the timer */ - base->TCR &= ~CTIMER_TCR_CEN_MASK; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the timer clock*/ - CLOCK_DisableClock(s_ctimerClocks[index]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - - /* Disable IRQ at NVIC Level */ - DisableIRQ(s_ctimerIRQ[index]); -} - -/*! - * brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * endcode - * param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config) -{ - assert(config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - /* Run as a timer */ - config->mode = kCTIMER_TimerMode; - /* This field is ignored when mode is timer */ - config->input = kCTIMER_Capture_0; - /* Timer counter is incremented on every APB bus clock */ - config->prescale = 0; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * param base Ctimer peripheral base address - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * param pwmFreq_Hz PWM signal frequency in Hz - * param srcClock_Hz Timer counter clock in Hz - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt) -{ - assert(pwmFreq_Hz > 0); - - uint32_t reg; - uint32_t period, pulsePeriod = 0; - uint32_t timerClock = srcClock_Hz / (base->PR + 1); - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == kCTIMER_Match_3) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the channel */ - base->PWMC |= (1U << matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); - } - - /* Reset the counter when match on channel 3 */ - reg |= CTIMER_MCR_MR3R_MASK; - - base->MCR = reg; - - /* Calculate PWM period match value */ - period = (timerClock / pwmFreq_Hz) - 1; - - /* Calculate pulse width match value */ - if (dutyCyclePercent == 0) - { - pulsePeriod = period + 1; - } - else - { - pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; - } - - /* Match on channel 3 will define the PWM period */ - base->MR[kCTIMER_Match_3] = period; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. - * - * note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * param base Ctimer peripheral base address - * param matchChannel Match pin to be used to output the PWM signal - * param pwmPeriod PWM period match value - * param pulsePeriod Pulse width match value - * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period - */ -status_t CTIMER_SetupPwmPeriod( - CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!((FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32) && (pulsePeriod > 0xFFFFU))); -#endif - - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - if (matchChannel == kCTIMER_Match_3) - { - return kStatus_Fail; - } - - /* Enable PWM mode on the channel */ - base->PWMC |= (1U << matchChannel); - - /* Clear the stop, reset and interrupt bits for this channel */ - reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - - /* If call back function is valid then enable match interrupt for the channel */ - if (enableInt) - { - reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); - } - - /* Reset the counter when match on channel 3 */ - reg |= CTIMER_MCR_MR3R_MASK; - - base->MCR = reg; - - /* Match on channel 3 will define the PWM period */ - base->MR[kCTIMER_Match_3] = pwmPeriod; - - /* This will define the PWM pulse period */ - base->MR[matchChannel] = pulsePeriod; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); - /* If call back function is valid then enable interrupt and update the call back function */ - if (enableInt) - { - EnableIRQ(s_ctimerIRQ[index]); - } - - return kStatus_Success; -} - -/*! - * brief Updates the duty cycle of an active PWM signal. - * - * note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. - * - * param base Ctimer peripheral base address - * param matchChannel Match pin to be used to output the PWM signal - * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent) -{ - uint32_t pulsePeriod = 0, period; - - /* Match channel 3 defines the PWM period */ - period = base->MR[kCTIMER_Match_3]; - - /* Calculate pulse width match value */ - pulsePeriod = (period * dutyCyclePercent) / 100; - - /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent == 0) - { - pulsePeriod = period + 1; - } - else - { - pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; - } - - /* Update dutycycle */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * param base Ctimer peripheral base address - * param matchChannel Match register to configure - * param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config) -{ -/* Some CTimers only have 16bits , so the value is limited*/ -#if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B - assert(!(FSL_FEATURE_CTIMER_BIT_SIZEn(base) < 32 && config->matchValue > 0xFFFFU)); -#endif - uint32_t reg; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the counter operation when a match on this channel occurs */ - reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3))); - reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3))); - reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); - base->MCR = reg; - - reg = base->EMR; - /* Set the match output operation when a match on this channel occurs */ - reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2)); - reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2)); - - /* Set the initial state of the EM bit/output */ - reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel); - reg |= (uint32_t)config->outPinInitState << matchChannel; - base->EMR = reg; - - /* Set the match value */ - base->MR[matchChannel] = config->matchValue; - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); - /* If interrupt is enabled then enable interrupt and update the call back function */ - if (config->enableInterrupt) - { - EnableIRQ(s_ctimerIRQ[index]); - } -} - -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) -/*! - * brief Setup the capture. - * - * param base Ctimer peripheral base address - * param capture Capture channel to configure - * param edge Edge on the channel that will trigger a capture - * param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt) -{ - uint32_t reg = base->CCR; - uint32_t index = CTIMER_GetInstance(base); - - /* Set the capture edge */ - reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3)); - reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3)); - /* Clear status flags */ - CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture)); - /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ - if (enableInt) - { - reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3); - EnableIRQ(s_ctimerIRQ[index]); - } - base->CCR = reg; -} -#endif - -/*! - * brief Register callback. - * - * param base Ctimer peripheral base address - * param cb_func callback function - * param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type) -{ - uint32_t index = CTIMER_GetInstance(base); - s_ctimerCallback[index] = cb_func; - ctimerCallbackType[index] = cb_type; -} - -void CTIMER_GenericIRQHandler(uint32_t index) -{ - uint32_t int_stat, i, mask; - /* Get Interrupt status flags */ - int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]); - /* Clear the status flags that were set */ - CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); - if (ctimerCallbackType[index] == kCTIMER_SingleCallback) - { - if (s_ctimerCallback[index][0]) - { - s_ctimerCallback[index][0](int_stat); - } - } - else - { -#if defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE - for (i = 0; i <= CTIMER_IR_MR3INT_SHIFT; i++) -#else -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) -#else - for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif - { - mask = 0x01 << i; - /* For each status flag bit that was set call the callback function if it is valid */ - if ((int_stat & mask) && (s_ctimerCallback[index][i])) - { - s_ctimerCallback[index][i](int_stat); - } - } - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(CTIMER0) -void CTIMER0_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(0); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER1) -void CTIMER1_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(1); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER2) -void CTIMER2_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(2); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER3) -void CTIMER3_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(3); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(CTIMER4) -void CTIMER4_DriverIRQHandler(void) -{ - CTIMER_GenericIRQHandler(4); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_ctimer.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_ctimer.h deleted file mode 100644 index 7ad216855..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_ctimer.h +++ /dev/null @@ -1,488 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_CTIMER_H_ -#define _FSL_CTIMER_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup ctimer - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ -/*@}*/ - -/*! @brief List of Timer capture channels */ -typedef enum _ctimer_capture_channel -{ - kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ - kCTIMER_Capture_1, /*!< Timer capture channel 1 */ - kCTIMER_Capture_2, /*!< Timer capture channel 2 */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture_3 /*!< Timer capture channel 3 */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -} ctimer_capture_channel_t; - -/*! @brief List of capture edge options */ -typedef enum _ctimer_capture_edge -{ - kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */ - kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */ - kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */ -} ctimer_capture_edge_t; - -/*! @brief List of Timer match registers */ -typedef enum _ctimer_match -{ - kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */ - kCTIMER_Match_1, /*!< Timer match register 1 */ - kCTIMER_Match_2, /*!< Timer match register 2 */ - kCTIMER_Match_3 /*!< Timer match register 3 */ -} ctimer_match_t; - -/*! @brief List of output control options */ -typedef enum _ctimer_match_output_control -{ - kCTIMER_Output_NoAction = 0U, /*!< No action is taken */ - kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */ - kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */ - kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */ -} ctimer_match_output_control_t; - -/*! @brief List of Timer modes */ -typedef enum _ctimer_timer_mode -{ - kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */ - kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */ - kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */ - kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */ -} ctimer_timer_mode_t; - -/*! @brief List of Timer interrupts */ -typedef enum _ctimer_interrupt_enable -{ - kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */ - kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */ - kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */ - kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ - kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ - kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ -#endif -} ctimer_interrupt_enable_t; - -/*! @brief List of Timer flags */ -typedef enum _ctimer_status_flags -{ - kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */ - kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */ - kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */ - kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ - kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ - kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ -#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT - kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ -#endif -} ctimer_status_flags_t; - -typedef void (*ctimer_callback_t)(uint32_t flags); - -/*! @brief Callback type when registering for a callback. When registering a callback - * an array of function pointers is passed the size could be 1 or 8, the callback - * type will tell that. - */ -typedef enum -{ - kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer. - based on the status flags different channels needs to be handled differently */ - kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel. - for both match/capture */ -} ctimer_callback_type_t; - -/*! - * @brief Match configuration - * - * This structure holds the configuration settings for each match register. - */ -typedef struct _ctimer_match_config -{ - uint32_t matchValue; /*!< This is stored in the match register */ - bool enableCounterReset; /*!< true: Match will reset the counter - false: Match will not reser the counter */ - bool enableCounterStop; /*!< true: Match will stop the counter - false: Match will not stop the counter */ - ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */ - bool outPinInitState; /*!< Initial value of the EM bit/output */ - bool enableInterrupt; /*!< true: Generate interrupt upon match - false: Do not generate interrupt on match */ - -} ctimer_match_config_t; - -/*! - * @brief Timer configuration structure - * - * This structure holds the configuration settings for the Timer peripheral. To initialize this - * structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a - * pointer to the configuration structure instance. - * - * The configuration structure can be made constant so as to reside in flash. - */ -typedef struct _ctimer_config -{ - ctimer_timer_mode_t mode; /*!< Timer mode */ - ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer - modes that rely on this input signal to increment TC */ - uint32_t prescale; /*!< Prescale value */ -} ctimer_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Ungates the clock and configures the peripheral for basic operation. - * - * @note This API should be called at the beginning of the application before using the driver. - * - * @param base Ctimer peripheral base address - * @param config Pointer to the user configuration structure. - */ -void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config); - -/*! - * @brief Gates the timer clock. - * - * @param base Ctimer peripheral base address - */ -void CTIMER_Deinit(CTIMER_Type *base); - -/*! - * @brief Fills in the timers configuration structure with the default settings. - * - * The default values are: - * @code - * config->mode = kCTIMER_TimerMode; - * config->input = kCTIMER_Capture_0; - * config->prescale = 0; - * @endcode - * @param config Pointer to the user configuration structure. - */ -void CTIMER_GetDefaultConfig(ctimer_config_t *config); - -/*! @}*/ - -/*! - * @name PWM setup operations - * @{ - */ - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * period - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param pwmPeriod PWM period match value - * @param pulsePeriod Pulse width match value - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * @return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period - */ -status_t CTIMER_SetupPwmPeriod( - CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt); - -/*! - * @brief Configures the PWM signal parameters. - * - * Enables PWM mode on the match channel passed in and will then setup the match value - * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. - * - * @note When setting PWM output from multiple output pins, all should use the same PWM - * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 - * @param pwmFreq_Hz PWM signal frequency in Hz - * @param srcClock_Hz Timer counter clock in Hz - * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * @return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle - */ -status_t CTIMER_SetupPwm(CTIMER_Type *base, - ctimer_match_t matchChannel, - uint8_t dutyCyclePercent, - uint32_t pwmFreq_Hz, - uint32_t srcClock_Hz, - bool enableInt); - -/*! - * @brief Updates the pulse period of an active PWM signal. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param pulsePeriod New PWM pulse width match value - */ -static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pulsePeriod) -{ - /* Update PWM pulse period match value */ - base->MR[matchChannel] = pulsePeriod; -} - -/*! - * @brief Updates the duty cycle of an active PWM signal. - * - * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match pin to be used to output the PWM signal - * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 - */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent); - -/*! @}*/ - -/*! - * @brief Setup the match register. - * - * User configuration is used to setup the match value and action to be taken when a match occurs. - * - * @param base Ctimer peripheral base address - * @param matchChannel Match register to configure - * @param config Pointer to the match configuration structure - */ -void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); - -/*! - * @brief Setup the capture. - * - * @param base Ctimer peripheral base address - * @param capture Capture channel to configure - * @param edge Edge on the channel that will trigger a capture - * @param enableInt Flag to enable channel interrupts, if enabled then the registered call back - * is called upon capture - */ -void CTIMER_SetupCapture(CTIMER_Type *base, - ctimer_capture_channel_t capture, - ctimer_capture_edge_t edge, - bool enableInt); - -/*! - * @brief Get the timer count value from TC register. - * - * @param base Ctimer peripheral base address. - * @return return the timer count value. - */ -static inline uint32_t CTIMER_GetTimerCountValue(CTIMER_Type *base) -{ - return (base->TC); -} - -/*! - * @brief Register callback. - * - * @param base Ctimer peripheral base address - * @param cb_func callback function - * @param cb_type callback function type, singular or multiple - */ -void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type); - -/*! - * @name Interrupt Interface - * @{ - */ - -/*! - * @brief Enables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Enable match interrupts */ - base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Enable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif -} - -/*! - * @brief Disables the selected Timer interrupts. - * - * @param base Ctimer peripheral base address - * @param mask The interrupts to enable. This is a logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) -{ - /* Disable match interrupts */ - base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK)); - -/* Disable capture interrupts */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - )); -#endif -} - -/*! - * @brief Gets the enabled Timer interrupts. - * - * @param base Ctimer peripheral base address - * - * @return The enabled interrupts. This is the logical OR of members of the - * enumeration ::ctimer_interrupt_enable_t - */ -static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) -{ - uint32_t enabledIntrs = 0; - - /* Get all the match interrupts enabled */ - enabledIntrs = - base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK); - -/* Get all the capture interrupts enabled */ -#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK -#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 - | CTIMER_CCR_CAP3I_MASK -#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ - ); -#endif - - return enabledIntrs; -} - -/*! @}*/ - -/*! - * @name Status Interface - * @{ - */ - -/*! - * @brief Gets the Timer status flags. - * - * @param base Ctimer peripheral base address - * - * @return The status flags. This is the logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base) -{ - return base->IR; -} - -/*! - * @brief Clears the Timer status flags. - * - * @param base Ctimer peripheral base address - * @param mask The status flags to clear. This is a logical OR of members of the - * enumeration ::ctimer_status_flags_t - */ -static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) -{ - base->IR = mask; -} - -/*! @}*/ - -/*! - * @name Counter Start and Stop - * @{ - */ - -/*! - * @brief Starts the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StartTimer(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CEN_MASK; -} - -/*! - * @brief Stops the Timer counter. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_StopTimer(CTIMER_Type *base) -{ - base->TCR &= ~CTIMER_TCR_CEN_MASK; -} - -/*! @}*/ - -/*! - * @brief Reset the counter. - * - * The timer counter and prescale counter are reset on the next positive edge of the APB clock. - * - * @param base Ctimer peripheral base address - */ -static inline void CTIMER_Reset(CTIMER_Type *base) -{ - base->TCR |= CTIMER_TCR_CRST_MASK; - base->TCR &= ~CTIMER_TCR_CRST_MASK; -} - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_CTIMER_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_flexcomm.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_flexcomm.c deleted file mode 100644 index 8c3754493..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_flexcomm.c +++ /dev/null @@ -1,400 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_flexcomm.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm" -#endif - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! @brief Set the FLEXCOMM mode . */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock); - -/*! @brief check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph); - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ -static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; - -/*! @brief Pointers to handles for each instance to provide context to interrupt routines */ -static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; - -/*! @brief Array to map FLEXCOMM instance number to IRQ number. */ -IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; - -/*! @brief Array to map FLEXCOMM instance number to base address. */ -static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS; - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief IDs of clock for each FLEXCOMM module */ -static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) -/*! @brief Pointers to FLEXCOMM resets for each instance. */ -static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS; -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* check whether flexcomm supports peripheral type */ -static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph) -{ - if (periph == FLEXCOMM_PERIPH_NONE) - { - return true; - } - else if (periph <= FLEXCOMM_PERIPH_I2S_TX) - { - return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false; - } - else if (periph == FLEXCOMM_PERIPH_I2S_RX) - { - return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false; - } - else - { - return false; - } -} - -/* Get the index corresponding to the FLEXCOMM */ -/*! brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base) -{ - int i; - - for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) - { - if ((uint32_t)base == s_flexcommBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0; -} - -/* Changes FLEXCOMM mode */ -static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock) -{ - /* Check whether peripheral type is present */ - if (!FLEXCOMM_PeripheralIsPresent(base, periph)) - { - return kStatus_OutOfRange; - } - - /* Flexcomm is locked to different peripheral type than expected */ - if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph)) - { - return kStatus_Fail; - } - - /* Check if we are asked to lock */ - if (lock) - { - base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; - } - else - { - base->PSELID = (uint32_t)periph; - } - - return kStatus_Success; -} - -/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) -{ - int idx = FLEXCOMM_GetInstance(base); - - if (idx < 0) - { - return kStatus_InvalidArgument; - } - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the peripheral clock */ - CLOCK_EnableClock(s_flexcommClocks[idx]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) - /* Reset the FLEXCOMM module */ - RESET_PeripheralReset(s_flexcommResets[idx]); -#endif - - /* Set the FLEXCOMM to given peripheral */ - return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0); -} - -/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(base); - - /* Clear handler first to avoid execution of the handler with wrong handle */ - s_flexcommIrqHandler[instance] = NULL; - s_flexcommHandle[instance] = handle; - s_flexcommIrqHandler[instance] = handler; -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -/* IRQ handler functions overloading weak symbols in the startup */ -#if defined(FLEXCOMM0) -void FLEXCOMM0_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[0]); - s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM1) -void FLEXCOMM1_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[1]); - s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM2) -void FLEXCOMM2_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[2]); - s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM3) -void FLEXCOMM3_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[3]); - s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM4) -void FLEXCOMM4_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[4]); - s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#endif - -#if defined(FLEXCOMM5) -void FLEXCOMM5_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[5]); - s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM6) -void FLEXCOMM6_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[6]); - s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM7) -void FLEXCOMM7_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[7]); - s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM8) -void FLEXCOMM8_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[8]); - s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM9) -void FLEXCOMM9_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[9]); - s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM10) -void FLEXCOMM10_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[10]); - s_flexcommIrqHandler[10]((void *)s_flexcommBaseAddrs[10], s_flexcommHandle[10]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM11) -void FLEXCOMM11_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[11]); - s_flexcommIrqHandler[11]((void *)s_flexcommBaseAddrs[11], s_flexcommHandle[11]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM12) -void FLEXCOMM12_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[12]); - s_flexcommIrqHandler[12]((void *)s_flexcommBaseAddrs[12], s_flexcommHandle[12]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM13) -void FLEXCOMM13_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[13]); - s_flexcommIrqHandler[13]((void *)s_flexcommBaseAddrs[13], s_flexcommHandle[13]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM14) -void FLEXCOMM14_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM14); - assert(s_flexcommIrqHandler[instance]); - s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM15) -void FLEXCOMM15_DriverIRQHandler(void) -{ - uint32_t instance; - - /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM14); - assert(s_flexcommIrqHandler[instance]); - s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if defined(FLEXCOMM16) -void FLEXCOMM16_DriverIRQHandler(void) -{ - assert(s_flexcommIrqHandler[16]); - s_flexcommIrqHandler[16]((void *)s_flexcommBaseAddrs[16], s_flexcommHandle[16]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_flexcomm.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_flexcomm.h deleted file mode 100644 index 7018e8c32..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_flexcomm.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_FLEXCOMM_H_ -#define _FSL_FLEXCOMM_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup flexcomm_driver - * @{ - */ - -/*! @name Driver version */ -/*@{*/ -/*! @brief FlexCOMM driver version 2.0.1. */ -#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! @brief FLEXCOMM peripheral modes. */ -typedef enum -{ - FLEXCOMM_PERIPH_NONE, /*!< No peripheral */ - FLEXCOMM_PERIPH_USART, /*!< USART peripheral */ - FLEXCOMM_PERIPH_SPI, /*!< SPI Peripheral */ - FLEXCOMM_PERIPH_I2C, /*!< I2C Peripheral */ - FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */ - FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */ -} FLEXCOMM_PERIPH_T; - -/*! @brief Typedef for interrupt handler. */ -typedef void (*flexcomm_irq_handler_t)(void *base, void *handle); - -/*! @brief Array with IRQ number for each FLEXCOMM module. */ -extern IRQn_Type const kFlexcommIrqs[]; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! @brief Returns instance number for FLEXCOMM module with given base address. */ -uint32_t FLEXCOMM_GetInstance(void *base); - -/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ -status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); - -/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM - * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle); - -#if defined(__cplusplus) -} -#endif - -/*@}*/ - -#endif /* _FSL_FLEXCOMM_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_gpio.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_gpio.c deleted file mode 100644 index dca3c291b..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_gpio.c +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_gpio.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) -/*! @brief Array to map FGPIO instance number to clock name. */ -static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS; -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) -/*! @brief Pointers to GPIO resets for each instance. */ -static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; -#endif -/******************************************************************************* - * Prototypes - ************ ******************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * param base GPIO peripheral base pointer. - * param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - assert(port < ARRAY_SIZE(s_gpioClockName)); - - /* Upgate the GPIO clock */ - CLOCK_EnableClock(s_gpioClockName[port]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) - /* Reset the GPIO module */ - RESET_PeripheralReset(s_gpioResets[port]); -#endif -} - -/*! - * brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * endcode - * - * param base GPIO peripheral base pointer(Typically GPIO) - * param port GPIO port number - * param pin GPIO pin number - * param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) -{ - if (config->pinDirection == kGPIO_DigitalInput) - { -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRCLR[port] = 1U << pin; -#else - base->DIR[port] &= ~(1U << pin); -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } - else - { - /* Set default output value */ - if (config->outputLogic == 0U) - { - base->CLR[port] = (1U << pin); - } - else - { - base->SET[port] = (1U << pin); - } -/* Set pin direction */ -#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRSET[port] = 1U << pin; -#else - base->DIR[port] |= 1U << pin; -#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ - } -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Configures the gpio pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) -{ - base->INTEDG[port] = base->INTEDG[port] | (config->mode << pin); - - base->INTPOL[port] = base->INTPOL[port] | (config->polarity << pin); -} - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if (kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | mask; - } - else if (kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if (kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~mask; - } - else if (kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears multiple pins interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) -{ - if (kGPIO_InterruptA == index) - { - base->INTSTATA[port] = mask; - } - else if (kGPIO_InterruptB == index) - { - base->INTSTATB[port] = mask; - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index) -{ - uint32_t status = 0U; - - if (kGPIO_InterruptA == index) - { - status = base->INTSTATA[port]; - } - else if (kGPIO_InterruptB == index) - { - status = base->INTSTATB[port]; - } - else - { - /*Should not enter here*/ - } - return status; - -} - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if (kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] | (1U << pin); - } - else if (kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] | (1U << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if (kGPIO_InterruptA == index) - { - base->INTENA[port] = base->INTENA[port] & ~(1U << pin); - } - else if (kGPIO_InterruptB == index) - { - base->INTENB[port] = base->INTENB[port] & ~(1U << pin); - } - else - { - /*Should not enter here*/ - } -} - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) -{ - if (kGPIO_InterruptA == index) - { - base->INTSTATA[port] = 1U << pin; - } - else if (kGPIO_InterruptB == index) - { - base->INTSTATB[port] = 1U << pin; - } - else - { - /*Should not enter here*/ - } -} -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_gpio.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_gpio.h deleted file mode 100644 index c2935292a..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_gpio.h +++ /dev/null @@ -1,365 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _LPC_GPIO_H_ -#define _LPC_GPIO_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_gpio - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief LPC GPIO driver version 2.1.3. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) -/*@}*/ - -/*! @brief LPC GPIO direction definition */ -typedef enum _gpio_pin_direction -{ - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ - kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ -} gpio_pin_direction_t; - -/*! - * @brief The GPIO pin configuration structure. - * - * Every pin can only be configured as either output pin or input pin at a time. - * If configured as a input pin, then leave the outputConfig unused. - */ -typedef struct _gpio_pin_config -{ - gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ - /* Output configurations, please ignore if configured as a input one */ - uint8_t outputLogic; /*!< Set default output logic, no use in input */ -} gpio_pin_config_t; - -#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) -#define GPIO_PIN_INT_LEVEL 0x00U -#define GPIO_PIN_INT_EDGE 0x01U - -#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U -#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U - -/*! @brief GPIO Pin Interrupt enable mode */ -typedef enum _gpio_pin_enable_mode -{ - kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ - kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ -} gpio_pin_enable_mode_t; - -/*! @brief GPIO Pin Interrupt enable polarity */ -typedef enum _gpio_pin_enable_polarity -{ - kGPIO_PinIntEnableHighOrRise = - PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */ - kGPIO_PinIntEnableLowOrFall = - PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */ -} gpio_pin_enable_polarity_t; - -/*! @brief LPC GPIO interrupt index definition */ -typedef enum _gpio_interrupt_index -{ - kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/ - kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/ -} gpio_interrupt_index_t; - -/*! @brief Configures the interrupt generation condition. */ -typedef struct _gpio_interrupt_config -{ - uint8_t mode; /* The trigger mode of GPIO interrupts */ - uint8_t polarity; /* The polarity of GPIO interrupts */ -} gpio_interrupt_config_t; -#endif - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" -{ -#endif - -/*! @name GPIO Configuration */ -/*@{*/ - -/*! - * @brief Initializes the GPIO peripheral. - * - * This function ungates the GPIO clock. - * - * @param base GPIO peripheral base pointer. - * @param port GPIO port number. - */ -void GPIO_PortInit(GPIO_Type *base, uint32_t port); - -/*! - * @brief Initializes a GPIO pin used by the board. - * - * To initialize the GPIO, define a pin configuration, either input or output, in the user file. - * Then, call the GPIO_PinInit() function. - * - * This is an example to define an input pin or output pin configuration: - * @code - * // Define a digital input pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalInput, - * 0, - * } - * //Define a digital output pin configuration, - * gpio_pin_config_t config = - * { - * kGPIO_DigitalOutput, - * 0, - * } - * @endcode - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param config GPIO pin configuration pointer - */ -void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config); - -/*@}*/ - -/*! @name GPIO Output Operations */ -/*@{*/ - -/*! - * @brief Sets the output level of the one GPIO pin to the logic 1 or 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @param output GPIO pin output logic level. - * - 0: corresponding pin output low-logic level. - * - 1: corresponding pin output high-logic level. - */ -static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) -{ - base->B[port][pin] = output; -} - -/*@}*/ -/*! @name GPIO Input Operations */ -/*@{*/ - -/*! - * @brief Reads the current input value of the GPIO PIN. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param pin GPIO pin number - * @retval GPIO port input value - * - 0: corresponding pin input low-logic level. - * - 1: corresponding pin input high-logic level. - */ -static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) -{ - return (uint32_t)base->B[port][pin]; -} - -/*@}*/ - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 1. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->SET[port] = mask; -} - -/*! - * @brief Sets the output level of the multiple GPIO pins to the logic 0. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->CLR[port] = mask; -} - -/*! - * @brief Reverses current output logic of the multiple GPIO pins. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->NOT[port] = mask; -} - -/*@}*/ - -/*! - * @brief Reads the current input value of the whole GPIO port. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - */ -static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->PIN[port]; -} - -/*@}*/ -/*! @name GPIO Mask Operations */ -/*@{*/ - -/*! - * @brief Sets port mask, 0 - enable pin, 1 - disable pin. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param mask GPIO pin number macro - */ -static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) -{ - base->MASK[port] = mask; -} - -/*! - * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @param output GPIO port output value. - */ -static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output) -{ - base->MPIN[port] = output; -} - -/*! - * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be - * affected. - * - * @param base GPIO peripheral base pointer(Typically GPIO) - * @param port GPIO port number - * @retval masked GPIO port value - */ -static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) -{ - return (uint32_t)base->MPIN[port]; -} - -#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT -/*! - * @brief Configures the gpio pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param pin GPIO pin number. - * @param config GPIO pin interrupt configuration.. - */ -void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config); - -/*! - * @brief Enables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Disables multiple pins interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @brief Clears pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param index GPIO interrupt number. - * @param mask GPIO pin number macro. - */ -void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask); - -/*! - * @ Read port interrupt status. - * - * @param base GPIO base pointer. - * @param port GPIO port number - * @param index GPIO interrupt number. - * @retval masked GPIO status value - */ -uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index); - -/*! - * @brief Enables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Disables the specific pin interrupt. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -/*! - * @brief Clears the specific pin interrupt flag. Status flags are cleared by - * writing a 1 to the corresponding bit position. - * - * @param base GPIO base pointer. - * @param port GPIO port number. - * @param pin GPIO pin number. - * @param index GPIO interrupt number. - */ -void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index); - -#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */ - -/*@}*/ - -#if defined(__cplusplus) -} -#endif - -/*! - * @} - */ - -#endif /* _LPC_GPIO_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_iocon.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_iocon.h deleted file mode 100644 index ec9709371..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_iocon.h +++ /dev/null @@ -1,288 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_IOCON_H_ -#define _FSL_IOCON_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup lpc_iocon - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" -#endif - -/*! @name Driver version */ -/*@{*/ -/*! @brief IOCON driver version 2.1.1. */ -#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) -/*@}*/ - -/** - * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format - */ -typedef struct _iocon_group -{ - uint32_t port : 8; /* Pin port */ - uint32_t pin : 8; /* Pin number */ - uint32_t ionumber : 8; /* IO number */ - uint32_t modefunc : 16; /* Function and mode */ -} iocon_group_t; - -/** - * @brief IOCON function and mode selection definitions - * @note See the User Manual for specific modes and functions supported by the various pins. - */ -#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ -#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ -#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ -#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ -#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ -#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ -#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ -#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ -#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ -#if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ -#endif - -#if defined(IOCON_PIO_I2CSLEW_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_EGP_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_SLEW_SHIFT) -#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_INVERT_SHIFT) -#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ -#endif - -#if defined(IOCON_PIO_DIGIMODE_SHIFT) -#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN \ - (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ -#endif - -#if defined(IOCON_PIO_FILTEROFF_SHIFT) -#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ -#endif - -#if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ -#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ -#endif - -#if defined(IOCON_PIO_OD_SHIFT) -#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ -#endif - -#if defined(IOCON_PIO_I2CFILTER_SHIFT) -#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ -#endif - -#if defined(IOCON_PIO_ASW_SHIFT) -#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */ -#endif - -#if defined(IOCON_PIO_SSEL_SHIFT) -#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */ -#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */ -#endif - -#if defined(IOCON_PIO_ECS_SHIFT) -#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ -#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ -#endif - -#if defined(IOCON_PIO_S_MODE_SHIFT) -#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK \ - (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_2CLK \ - (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_3CLK \ - (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ -#endif - -#if defined(IOCON_PIO_CLK_DIV_SHIFT) -#define IOCON_CLKDIV(div) \ - ((div) \ - << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif - -#else -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ - -#if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ -#endif - -#if defined(IOCON_PIO_I2CSLEW_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_EGP_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_INVERT_SHIFT) -#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ -#endif - -#if defined(IOCON_PIO_DIGIMODE_SHIFT) -#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN \ - (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ -#endif - -#if defined(IOCON_PIO_FILTEROFF_SHIFT) -#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ -#endif - -#if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ -#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ -#endif - -#if defined(IOCON_PIO_OD_SHIFT) -#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ -#endif - -#if defined(IOCON_PIO_I2CFILTER_SHIFT) -#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */ -#endif - -#if defined(IOCON_PIO_S_MODE_SHIFT) -#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK \ - (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_2CLK \ - (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_3CLK \ - (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ -#endif - -#if defined(IOCON_PIO_CLK_DIV_SHIFT) -#define IOCON_CLKDIV(div) \ - ((div) \ - << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif - -#endif -#if defined(__cplusplus) -extern "C" { -#endif - -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param ionumber : GPIO number to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc) -{ - base->PIO[ionumber] = modefunc; -} -#else -/** - * @brief Sets I/O Control pin mux - * @param base : The base of IOCON peripheral on the chip - * @param port : GPIO port to mux - * @param pin : GPIO pin to mux - * @param modefunc : OR'ed values of type IOCON_* - * @return Nothing - */ -__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc) -{ - base->PIO[port][pin] = modefunc; -} -#endif - -/** - * @brief Set all I/O Control pin muxing - * @param base : The base of IOCON peripheral on the chip - * @param pinArray : Pointer to array of pin mux selections - * @param arrayLength : Number of entries in pinArray - * @return Nothing - */ -__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength) -{ - uint32_t i; - - for (i = 0; i < arrayLength; i++) - { -#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1)) - IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc); -#else - IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); -#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */ - } -} - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_IOCON_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_pint.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_pint.c deleted file mode 100644 index ae9db698b..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_pint.c +++ /dev/null @@ -1,855 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_pint.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.pint" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + - FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; - -/*! @brief Callback function array for PINT(s). */ -static pint_cb_t - s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; -#else -/*! @brief Irq number array */ -static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; - -/*! @brief Callback function array for PINT(s). */ -static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ - -/******************************************************************************* - * Code - ******************************************************************************/ - -/*! - * brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Init(PINT_Type *base) -{ - uint32_t i; - uint32_t pmcfg; - uint8_t pintcount; - assert(base); - pmcfg = 0; - -#if defined(SECPINT) - pintcount = SEC_PINT_PIN_INT_COUNT; -#else - pintcount = PINT_PIN_INT_COUNT; -#endif /* SECPINT */ - - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - - /* Disable all bit slices for pint*/ - for (i = 0; i < pintcount; i++) - { - pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if defined(SECPINT) -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* SECPINT */ -#else - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } -#if defined(SECPINT) - else if (base == SECPINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - } -#endif /* SECPINT */ -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ - - /* Disable all pattern match bit slices */ - base->PMCFG = pmcfg; -} - -/*! - * brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param intr Pin interrupt. - * param enable Selects detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) -{ - assert(base); - - /* Clear Rise and Fall flags first */ - PINT_PinInterruptClrRiseFlag(base, intr); - PINT_PinInterruptClrFallFlag(base, intr); - - /* select level or edge sensitive */ - base->ISEL = - (base->ISEL & ~(1UL << (uint32_t)intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1UL << (uint32_t)intr) : 0U); - - /* enable rising or level interrupt */ - if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) - { - base->SIENR = 1UL << (uint32_t)intr; - } - else - { - base->CIENR = 1UL << (uint32_t)intr; - } - - /* Enable falling or select high level */ - if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - { - base->SIENF = 1UL << (uint32_t)intr; - } - else - { - base->CIENF = 1UL << (uint32_t)intr; - } - - s_pintCallback[intr] = callback; -} - -/*! - * brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * param base Base address of the PINT peripheral. - * param pintr Pin interrupt. - * param enable Pointer to store the detection logic. - * param callback Callback. - * - * retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback) -{ - uint32_t mask; - bool level; - - assert(base); - - *enable = kPINT_PinIntEnableNone; - level = false; - - mask = 1UL << (uint32_t)pintr; - if ((base->ISEL & mask) != 0U) - { - /* Pin interrupt is level sensitive */ - level = true; - } - - if ((base->IENR & mask) != 0U) - { - if (level) - { - /* Level interrupt is enabled */ - *enable = kPINT_PinIntEnableLowLevel; - } - else - { - /* Rising edge interrupt */ - *enable = kPINT_PinIntEnableRiseEdge; - } - } - - if ((base->IENF & mask) != 0U) - { - if (level) - { - /* Level interrupt is active high */ - *enable = kPINT_PinIntEnableHighLevel; - } - else - { - /* Either falling or both edge */ - if (*enable == kPINT_PinIntEnableRiseEdge) - { - /* Rising and faling edge */ - *enable = kPINT_PinIntEnableBothEdges; - } - else - { - /* Falling edge */ - *enable = kPINT_PinIntEnableFallEdge; - } - } - } - - *callback = s_pintCallback[pintr]; -} - -/*! - * brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t pmcfg; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - /* Input source selection for selected bit slice */ - base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | (cfg->bs_src << src_shift); - - /* Bit slice configuration */ - pmcfg = base->PMCFG; - pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | (cfg->bs_cfg << cfg_shift); - - /* If end point is true, enable the bits */ - if ((uint32_t)bslice != 7UL) - { - if (cfg->end_point) - { - pmcfg |= (1UL << (uint32_t)bslice); - } - else - { - pmcfg &= ~(1UL << (uint32_t)bslice); - } - } - - base->PMCFG = pmcfg; - - /* Save callback pointer */ - s_pintCallback[bslice] = cfg->callback; -} - -/*! - * brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * param base Base address of the PINT peripheral. - * param bslice Pattern match bit slice number. - * param cfg Pointer to bit slice configuration. - * - * retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg) -{ - uint32_t src_shift; - uint32_t cfg_shift; - uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; - uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - - assert(base); - - src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); - cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - - cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); - cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); - - if ((uint32_t)bslice == 7U) - { - cfg->end_point = true; - } - else - { - cfg->end_point = ((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice); - } - cfg->callback = s_pintCallback[bslice]; -} - -/*! - * brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * param base Base address of the PINT peripheral. - * - * retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base) -{ - uint32_t pmctrl; - uint32_t pmstatus; - uint32_t pmsrc; - - pmctrl = base->PMCTRL; - pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; - if (pmstatus != 0UL) - { - /* Reset Pattern match engine detection logic */ - pmsrc = base->PMSRC; - base->PMSRC = pmsrc; - } - return (pmstatus); -} - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - uint32_t pinIntMode = base->ISEL & (1UL << (uint32_t)pintr); - uint32_t pinIntStatus = base->IST & (1UL << (uint32_t)pintr); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - base->IST = (1UL << (uint32_t)pintr); - } -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base) -{ - uint32_t pinIntMode = 0; - uint32_t pinIntStatus = 0; - uint32_t mask = 0; - uint32_t i; - - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - pinIntMode = base->ISEL & (1UL << i); - pinIntStatus = base->IST & (1UL << i); - - /* Edge sensitive and pin interrupt that is currently requesting an interrupt. */ - if ((pinIntMode == 0x0UL) && (pinIntStatus != 0x0UL)) - { - mask |= 1UL << i; - } - } - - base->IST = mask; -} - -/*! - * brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_EnableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - (void)EnableIRQ(s_pintIRQ[i]); - } -} - -/*! - * brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base); - - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - (void)EnableIRQ(s_pintIRQ[pintIdx]); -} - -/*! - * brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * param base Base address of the peripheral. - * - * retval None. - */ -void PINT_DisableCallback(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - (void)DisableIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - } -} - -/*! - * brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * param base Base address of the peripheral. - * param pinIdx pin index. - * - * retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) -{ - assert(base); - - (void)DisableIRQ(s_pintIRQ[pintIdx]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); -} - -/*! - * brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * param base Base address of the PINT peripheral. - * - * retval None. - */ -void PINT_Deinit(PINT_Type *base) -{ - uint32_t i; - - assert(base); - - /* Cleanup */ - PINT_DisableCallback(base); - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) - { - s_pintCallback[i] = NULL; - } - -#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(SECPINT) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* SECPINT */ -#else - if (base == PINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - } -#if defined(SECPINT) - else if (base == SECPINT) - { -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - } -#endif /* SECPINT */ -#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ -} -#if defined(SECPINT) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) -{ - uint32_t pmstatus = 0; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_pintCallback[kPINT_SecPinInt0] != NULL) - { - s_pintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -/* IRQ handler functions overloading weak symbols in the startup */ -void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); - /* Call user function */ - if (s_pintCallback[kPINT_SecPinInt1] != NULL) - { - s_pintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); - } - if ((SECPINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ -#endif /* SECPINT */ - -/* IRQ handler functions overloading weak symbols in the startup */ -void PIN_INT0_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt0] != NULL) - { - s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus); - } - if ((PINT->ISEL & 0x1U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) -void PIN_INT1_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt1] != NULL) - { - s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus); - } - if ((PINT->ISEL & 0x2U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) -void PIN_INT2_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt2] != NULL) - { - s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus); - } - if ((PINT->ISEL & 0x4U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) -void PIN_INT3_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt3] != NULL) - { - s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus); - } - if ((PINT->ISEL & 0x8U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) -void PIN_INT4_DriverIRQHandler(void) -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt4] != NULL) - { - s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus); - } - if ((PINT->ISEL & 0x10U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT5_DAC1_IRQHandler(void) -#else -void PIN_INT5_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt5] != NULL) - { - s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus); - } - if ((PINT->ISEL & 0x20U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT6_USART3_IRQHandler(void) -#else -void PIN_INT6_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt6] != NULL) - { - s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus); - } - if ((PINT->ISEL & 0x40U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif - -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) -#if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER -void PIN_INT7_USART4_IRQHandler(void) -#else -void PIN_INT7_DriverIRQHandler(void) -#endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ -{ - uint32_t pmstatus; - - /* Reset pattern match detection */ - pmstatus = PINT_PatternMatchResetDetectLogic(PINT); - /* Call user function */ - if (s_pintCallback[kPINT_PinInt7] != NULL) - { - s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus); - } - if ((PINT->ISEL & 0x80U) == 0x0U) - { - /* Edge sensitive: clear Pin interrupt after callback */ - PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); - } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif -} -#endif diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_pint.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_pint.h deleted file mode 100644 index 0e31210ec..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_pint.h +++ /dev/null @@ -1,579 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_PINT_H_ -#define _FSL_PINT_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup pint_driver - * @{ - */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*!< Version 2.1.3 */ -/*@}*/ - -/* Number of interrupt line supported by PINT */ -#define PINT_PIN_INT_COUNT 8U - -/* Number of interrupt line supported by SECURE PINT */ -#define SEC_PINT_PIN_INT_COUNT 2U - -/* Number of input sources supported by PINT */ -#define PINT_INPUT_COUNT 8U - -/* PININT Bit slice source register bits */ -#define PININT_BITSLICE_SRC_START 8U -#define PININT_BITSLICE_SRC_MASK 7U - -/* PININT Bit slice configuration register bits */ -#define PININT_BITSLICE_CFG_START 8U -#define PININT_BITSLICE_CFG_MASK 7U -#define PININT_BITSLICE_ENDP_MASK 7U - -#define PINT_PIN_INT_LEVEL 0x10U -#define PINT_PIN_INT_EDGE 0x00U -#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U -#define PINT_PIN_INT_RISE 0x01U -#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) -#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) -#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) - -/*! @brief PINT Pin Interrupt enable type */ -typedef enum _pint_pin_enable -{ - kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ - kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ - kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ - kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ - kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ - kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ -} pint_pin_enable_t; - -/*! @brief PINT Pin Interrupt type */ -typedef enum _pint_int -{ - kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ -#endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPinInt0 = 8U, /*!< Secure Pin Interrupt 0 */ -#endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPinInt1 = 9U, /*!< Secure Pin Interrupt 1 */ -#endif -} pint_pin_int_t; - -/*! @brief PINT Pattern Match bit slice input source type */ -typedef enum _pint_pmatch_input_src -{ - kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ - kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ - kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ - kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ - kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ - kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ - kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ -} pint_pmatch_input_src_t; - -/*! @brief PINT Pattern Match bit slice type */ -typedef enum _pint_pmatch_bslice -{ - kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) - kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) - kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) - kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) - kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) - kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ -#endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) - kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ -#endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kSECPINT_PatternMatchBSlice0 = 8U, /*!< Bit slice 0 */ -#endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kSECPINT_PatternMatchBSlice1 = 9U, /*!< Bit slice 1 */ -#endif -} pint_pmatch_bslice_t; - -/*! @brief PINT Pattern Match configuration type */ -typedef enum _pint_pmatch_bslice_cfg -{ - kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ - kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ - kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ - kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ - kPINT_PatternMatchHigh = 4U, /*!< High level */ - kPINT_PatternMatchLow = 5U, /*!< Low level */ - kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ - kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ -} pint_pmatch_bslice_cfg_t; - -/*! @brief PINT Callback function. */ -typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status); - -typedef struct _pint_pmatch_cfg -{ - pint_pmatch_input_src_t bs_src; - pint_pmatch_bslice_cfg_t bs_cfg; - bool end_point; - pint_cb_t callback; -} pint_pmatch_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Initialize PINT peripheral. - - * This function initializes the PINT peripheral and enables the clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Init(PINT_Type *base); - -/*! - * @brief Configure PINT peripheral pin interrupt. - - * This function configures a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param intr Pin interrupt. - * @param enable Selects detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback); - -/*! - * @brief Get PINT peripheral pin interrupt configuration. - - * This function returns the configuration of a given pin interrupt. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * @param enable Pointer to store the detection logic. - * @param callback Callback. - * - * @retval None. - */ -void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback); - -/*! - * @brief Clear Selected pin interrupt status only when the pin was triggered by edge-sensitive. - - * This function clears the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr); - -/*! - * @brief Get Selected pin interrupt status. - - * This function returns the selected pin interrupt status. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->IST & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupts status only when pins were triggered by edge-sensitive. - - * This function clears the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_PinInterruptClrStatusAll(PINT_Type *base); - -/*! - * @brief Get all pin interrupts status. - - * This function returns the status of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the status of corresponding pin interrupt. - * = 0 No pin interrupt request. = 1 Pin interrupt request active. - */ -static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base) -{ - return (base->IST); -} - -/*! - * @brief Clear Selected pin interrupt fall flag. - - * This function clears the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->FALL = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt fall flag. - - * This function returns the selected pin interrupt fall flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->FALL & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt fall flags. - - * This function clears the fall flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base) -{ - base->FALL = PINT_FALL_FDET_MASK; -} - -/*! - * @brief Get all pin interrupt fall flags. - - * This function returns the fall flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt. - * 0 Falling edge has not been detected. = 1 Falling edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base) -{ - return (base->FALL); -} - -/*! - * @brief Clear Selected pin interrupt rise flag. - - * This function clears the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - base->RISE = (1UL << (uint32_t)pintr); -} - -/*! - * @brief Get selected pin interrupt rise flag. - - * This function returns the selected pin interrupt rise flag. - * - * @param base Base address of the PINT peripheral. - * @param pintr Pin interrupt. - * - * @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr) -{ - return ((base->RISE & (1UL << (uint32_t)pintr)) != 0U ? 1U : 0U); -} - -/*! - * @brief Clear all pin interrupt rise flags. - - * This function clears the rise flag for all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base) -{ - base->RISE = PINT_RISE_RDET_MASK; -} - -/*! - * @brief Get all pin interrupt rise flags. - - * This function returns the rise flag of all pin interrupts. - * - * @param base Base address of the PINT peripheral. - * - * @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt. - * 0 Rising edge has not been detected. = 1 Rising edge has been detected. - */ -static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base) -{ - return (base->RISE); -} - -/*! - * @brief Configure PINT pattern match. - - * This function configures a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get PINT pattern match configuration. - - * This function returns the configuration of a given pattern match bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * @param cfg Pointer to bit slice configuration. - * - * @retval None. - */ -void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg); - -/*! - * @brief Get pattern match bit slice status. - - * This function returns the status of selected bit slice. - * - * @param base Base address of the PINT peripheral. - * @param bslice Pattern match bit slice number. - * - * @retval status = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice) -{ - return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice; -} - -/*! - * @brief Get status of all pattern match bit slices. - - * This function returns the status of all bit slices. - * - * @param base Base address of the PINT peripheral. - * - * @retval status Each bit position indicates the match status of corresponding bit slice. - * = 0 Match has not been detected. = 1 Match has been detected. - */ -static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base) -{ - return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT; -} - -/*! - * @brief Reset pattern match detection logic. - - * This function resets the pattern match detection logic if any of the product term is matching. - * - * @param base Base address of the PINT peripheral. - * - * @retval pmstatus Each bit position indicates the match status of corresponding bit slice. - * = 0 Match was detected. = 1 Match was not detected. - */ -uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base); - -/*! - * @brief Enable pattern match function. - - * This function enables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Disable pattern match function. - - * This function disables the pattern match function. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisable(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK; -} - -/*! - * @brief Enable RXEV output. - - * This function enables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Disable RXEV output. - - * This function disables the pattern match RXEV output. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base) -{ - base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK; -} - -/*! - * @brief Enable callback. - - * This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored - * as soon as they are enabled, the callback function is not enabled until this function is called. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_EnableCallback(PINT_Type *base); - -/*! - * @brief Disable callback. - - * This function disables the interrupt for the selected PINT peripheral. Although the pins are still - * being monitored but the callback function is not called. - * - * @param base Base address of the peripheral. - * - * @retval None. - */ -void PINT_DisableCallback(PINT_Type *base); - -/*! - * @brief Deinitialize PINT peripheral. - - * This function disables the PINT clock. - * - * @param base Base address of the PINT peripheral. - * - * @retval None. - */ -void PINT_Deinit(PINT_Type *base); - -/*! - * @brief enable callback by pin index. - - * This function enables callback by pin index instead of enabling all pins. - * - * @param base Base address of the peripheral. - * @param pinIdx pin index. - * - * @retval None. - */ -void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -/*! - * @brief disable callback by pin index. - - * This function disables callback by pin index instead of disabling all pins. - * - * @param base Base address of the peripheral. - * @param pinIdx pin index. - * - * @retval None. - */ -void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* _FSL_PINT_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_power.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_power.c deleted file mode 100644 index 79266e66e..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_power.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_common.h" -#include "fsl_power.h" -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.power" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Empty file since implementation is in header file and power library */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_power.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_power.h deleted file mode 100644 index 0417a7fff..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_power.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_POWER_H_ -#define _FSL_POWER_H_ - -#include "fsl_common.h" - -/*! @addtogroup power */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief power driver version 2.0.0. */ -#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -#define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot) -#define PDRCFG0 0x0U -#define PDRCFG1 0x1U - -typedef enum pd_bits -{ - kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U), - kPDRUNCFG_PD_FLASH = MAKE_PD_BITS(PDRCFG0, 5U), - kPDRUNCFG_PD_TEMPS = MAKE_PD_BITS(PDRCFG0, 6U), - kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U), - kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U), - kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U), - kPDRUNCFG_PD_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 11U), - kPDRUNCFG_LP_VDDFLASH = MAKE_PD_BITS(PDRCFG0, 12U), - kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U), - kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U), - kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U), - kPDRUNCFG_PD_RAMX = MAKE_PD_BITS(PDRCFG0, 16U), - kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U), - kPDRUNCFG_PD_VDDHV_ENA = MAKE_PD_BITS(PDRCFG0, 18U), - kPDRUNCFG_PD_VD7_ENA = MAKE_PD_BITS(PDRCFG0, 19U), - kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U), - kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U), - kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U), - kPDRUNCFG_PD_VREFP_SW = MAKE_PD_BITS(PDRCFG0, 23U), - kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U), - - kPDRUNCFG_PD_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 28U), - kPDRUNCFG_SEL_ALT_FLASH_IBG = MAKE_PD_BITS(PDRCFG1, 29U), - - kPDRUNCFG_ForceUnsigned = (int)0x80000000U -} pd_bit_t; - -/* Power mode configuration API parameter */ -typedef enum _power_mode_config -{ - kPmu_Sleep = 0U, - kPmu_Deep_Sleep = 1U, - kPmu_Deep_PowerDown = 2U, -} power_mode_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -/*! -* @name Power Configuration -* @{ -*/ - -/*! - * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral - * - * @param en peripheral for which to enable the PDRUNCFG bit - * @return none - */ -static inline void POWER_EnablePD(pd_bit_t en) -{ - /* PDRUNCFGSET */ - SYSCON->PDRUNCFGSET[(en >> 8UL)] = (1UL << (en & 0xffU)); -} - -/*! - * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral - * - * @param en peripheral for which to disable the PDRUNCFG bit - * @return none - */ -static inline void POWER_DisablePD(pd_bit_t en) -{ - /* PDRUNCFGCLR */ - SYSCON->PDRUNCFGCLR[(en >> 8UL)] = (1UL << (en & 0xffU)); -} - -/*! - * @brief API to enable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_EnableDeepSleep(void) -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to disable deep sleep bit in the ARM Core. - * - * @return none - */ -static inline void POWER_DisableDeepSleep(void) -{ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; -} - -/*! - * @brief API to power down flash controller. - * - * @return none - */ -static inline void POWER_PowerDownFlash(void) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* TURN OFF clock for Flash Controller (only needed for FLASH programming, will be turned on by ROM API) */ - CLOCK_DisableClock(kCLOCK_Flash); - - /* TURN OFF clock for Flash Accelerator */ - CLOCK_DisableClock(kCLOCK_Fmc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief API to power up flash controller. - * - * @return none - */ -static inline void POWER_PowerUpFlash(void) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* TURN ON clock for flash Accelerator */ - CLOCK_EnableClock(kCLOCK_Fmc); - - /* TURN ON clock for flash Controller */ - CLOCK_EnableClock(kCLOCK_Flash); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief Power Library API to enter different power mode. - * - * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep - * @return none - */ -void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd); - -/*! - * @brief Power Library API to enter sleep mode. - * - * @return none - */ -void POWER_EnterSleep(void); - -/*! - * @brief Power Library API to enter deep sleep mode. - * - * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep - * @return none - */ -void POWER_EnterDeepSleep(uint64_t exclude_from_pd); - -/*! - * @brief Power Library API to enter deep power down mode. - * - * @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep power down mode, - * but this is has no effect as the voltages are cut off. - * @return none - */ -void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd); - -/*! - * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. - * - * @param freq - The desired frequency at which the part would like to operate, - * note that the voltage and flash wait states should be set before changing frequency - * @return none - */ -void POWER_SetVoltageForFreq(uint32_t freq); - -/*! - * @brief Power Library API to choose low power regulation and set the voltage for the desired operating frequency. - * - * @param freq - The desired frequency at which the part would like to operate, - * note only 12MHz and 48Mhz are supported - * @return none - */ -void POWER_SetLowPowerVoltageForFreq(uint32_t freq); - -/*! - * @brief Power Library API to return the library version. - * - * @return version number of the power library - */ -uint32_t POWER_GetLibVersion(void); - -/* @} */ - -#ifdef __cplusplus -} -#endif - -/*! @} */ - -#endif /* _FSL_POWER_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_reset.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_reset.c deleted file mode 100644 index 29bbc5b97..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_reset.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_reset.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.reset" -#endif - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ - -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) - -/*! - * brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1u << bitPos; - - assert(bitPos < 32u); - - /* ASYNC_SYSCON registers have offset 1024 */ - if (regIndex >= SYSCON_PRESETCTRL_COUNT) - { - /* reset register is in ASYNC_SYSCON */ - - /* set bit */ - ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask; - /* wait until it reads 0b1 */ - while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) - { - } - } - else - { - /* reset register is in SYSCON */ - - /* set bit */ - SYSCON->PRESETCTRLSET[regIndex] = bitMask; - /* wait until it reads 0b1 */ - while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask)) - { - } - } -} - -/*! - * brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) -{ - const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1u << bitPos; - - assert(bitPos < 32u); - - /* ASYNC_SYSCON registers have offset 1024 */ - if (regIndex >= SYSCON_PRESETCTRL_COUNT) - { - /* reset register is in ASYNC_SYSCON */ - - /* clear bit */ - ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask)) - { - } - } - else - { - /* reset register is in SYSCON */ - - /* clear bit */ - SYSCON->PRESETCTRLCLR[regIndex] = bitMask; - /* wait until it reads 0b0 */ - while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask)) - { - } - } -} - -/*! - * brief Reset peripheral module. - * - * Reset peripheral module. - * - * param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral) -{ - RESET_SetPeripheralReset(peripheral); - RESET_ClearPeripheralReset(peripheral); -} - -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_reset.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_reset.h deleted file mode 100644 index 43b498729..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_reset.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016, NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_RESET_H_ -#define _FSL_RESET_H_ - -#include -#include -#include -#include -#include "fsl_device_registers.h" - -/*! - * @addtogroup ksdk_common - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief reset driver version 2.0.1. */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) -/*@}*/ - -/*! - * @brief Enumeration for peripheral reset control bits - * - * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers - */ -typedef enum _SYSCON_RSTn -{ - kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ - kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ - kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */ - kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ - kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ - kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ - kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ - kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ - kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ - kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ - kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ - kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ - kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ - kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ - kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ - kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ - kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ - kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ - kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ - kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ - kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ - kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ - kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ - kUSB_RST_SHIFT_RSTn = 65536 | 25U, /**< USB reset control */ - kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer0 reset control */ - kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer1 reset control */ - kCTIMER3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CTimer3 reset control */ -} SYSCON_RSTn_t; - -/** Array initializers with peripheral reset bits **/ -#define ADC_RSTS \ - { \ - kADC0_RST_SHIFT_RSTn \ - } /* Reset bits for ADC peripheral */ -#define CRC_RSTS \ - { \ - kCRC_RST_SHIFT_RSTn \ - } /* Reset bits for CRC peripheral */ -#define DMA_RSTS_N \ - { \ - kDMA_RST_SHIFT_RSTn \ - } /* Reset bits for DMA peripheral */ -#define FLEXCOMM_RSTS \ - { \ - kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \ - kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn \ - } /* Reset bits for FLEXCOMM peripheral */ -#define GINT_RSTS \ - { \ - kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \ - } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */ -#define GPIO_RSTS_N \ - { \ - kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \ - } /* Reset bits for GPIO peripheral */ -#define INPUTMUX_RSTS \ - { \ - kMUX_RST_SHIFT_RSTn \ - } /* Reset bits for INPUTMUX peripheral */ -#define IOCON_RSTS \ - { \ - kIOCON_RST_SHIFT_RSTn \ - } /* Reset bits for IOCON peripheral */ -#define FLASH_RSTS \ - { \ - kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \ - } /* Reset bits for Flash peripheral */ -#define MRT_RSTS \ - { \ - kMRT_RST_SHIFT_RSTn \ - } /* Reset bits for MRT peripheral */ -#define PINT_RSTS \ - { \ - kPINT_RST_SHIFT_RSTn \ - } /* Reset bits for PINT peripheral */ -#define SCT_RSTS \ - { \ - kSCT0_RST_SHIFT_RSTn \ - } /* Reset bits for SCT peripheral */ -#define CTIMER_RSTS \ - { \ - kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn \ - } /* Reset bits for TIMER peripheral */ -#define USB_RSTS \ - { \ - kUSB_RST_SHIFT_RSTn \ - } /* Reset bits for USB peripheral */ -#define UTICK_RSTS \ - { \ - kUTICK_RST_SHIFT_RSTn \ - } /* Reset bits for UTICK peripheral */ -#define WWDT_RSTS \ - { \ - kWWDT_RST_SHIFT_RSTn \ - } /* Reset bits for WWDT peripheral */ - -typedef SYSCON_RSTn_t reset_ip_name_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Assert reset to peripheral. - * - * Asserts reset signal to specified peripheral module. - * - * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_SetPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Clear reset to peripheral. - * - * Clears reset signal to specified peripheral module, allows it to operate. - * - * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_ClearPeripheralReset(reset_ip_name_t peripheral); - -/*! - * @brief Reset peripheral module. - * - * Reset peripheral module. - * - * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register - * and reset bit position in the reset register. - */ -void RESET_PeripheralReset(reset_ip_name_t peripheral); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_RESET_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_usart.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_usart.c deleted file mode 100644 index ce643d1e9..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_usart.c +++ /dev/null @@ -1,939 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_usart.h" -#include "fsl_device_registers.h" -#include "fsl_flexcomm.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" -#endif - -enum _usart_transfer_states -{ - kUSART_TxIdle, /* TX idle. */ - kUSART_TxBusy, /* TX busy. */ - kUSART_RxIdle, /* RX idle. */ - kUSART_RxBusy /* RX busy. */ -}; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief IRQ name array */ -static const IRQn_Type s_usartIRQ[] = USART_IRQS; - -/*! @brief Array to map USART instance number to base address. */ -static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS; - -/******************************************************************************* - * Code - ******************************************************************************/ - -/* Get the index corresponding to the USART */ -/*! brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base) -{ - int i; - - for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++) - { - if ((uint32_t)base == s_usartBaseAddrs[i]) - { - return i; - } - } - - assert(false); - return 0; -} - -/*! - * brief Get the length of received data in RX ring buffer. - * - * param handle USART handle pointer. - * return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) -{ - size_t size; - - /* Check arguments */ - assert(NULL != handle); - - if (handle->rxRingBufferTail > handle->rxRingBufferHead) - { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); - } - else - { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); - } - return size; -} - -static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle) -{ - bool full; - - /* Check arguments */ - assert(NULL != handle); - - if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U)) - { - full = true; - } - else - { - full = false; - } - return full; -} - -/*! - * brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - assert(NULL != ringBuffer); - - /* Setup the ringbuffer address */ - handle->rxRingBuffer = ringBuffer; - handle->rxRingBufferSize = ringBufferSize; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; - /* ring buffer is ready we can start receiving data */ - base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; -} - -/*! - * brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert(NULL != base); - assert(NULL != handle); - - if (handle->rxState == kUSART_RxIdle) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; - } - handle->rxRingBuffer = NULL; - handle->rxRingBufferSize = 0U; - handle->rxRingBufferHead = 0U; - handle->rxRingBufferTail = 0U; -} - -/*! - * brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param config Pointer to user-defined configuration structure. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_InvalidArgument USART base address is not valid - * retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz) -{ - int result; - - /* check arguments */ - assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* initialize flexcomm to USART mode */ - result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART); - if (kStatus_Success != result) - { - return result; - } - - if (config->enableTx) - { - /* empty and enable txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK; - } - - /* empty and enable rxFIFO */ - if (config->enableRx) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK; - /* setup trigger level */ - base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK); - base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark); - /* enable trigger interrupt */ - base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK; - } - /* setup configuration and enable USART */ - base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | - USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | - USART_CFG_SYNCEN(config->syncMode >> 1) | USART_CFG_SYNCMST(config->syncMode) | - USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_ENABLE_MASK; - - /* Setup baudrate */ - result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) - { - return result; - } - /* Setting continuous Clock configuration. used for synchronous mode. */ - USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); - - return kStatus_Success; -} - -/*! - * brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base) -{ - /* Check arguments */ - assert(NULL != base); - while (!(base->STAT & USART_STAT_TXIDLE_MASK)) - { - } - /* Disable interrupts, disable dma requests, disable peripheral */ - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK | - USART_FIFOINTENCLR_RXLVL_MASK; - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK); - base->CFG &= ~(USART_CFG_ENABLE_MASK); -} - -/*! - * brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config) -{ - /* Check arguments */ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - /* Set always all members ! */ - config->baudRate_Bps = 115200U; - config->parityMode = kUSART_ParityDisabled; - config->stopBitCount = kUSART_OneStopBit; - config->bitCountPerChar = kUSART_8BitsPerChar; - config->loopback = false; - config->enableRx = false; - config->enableTx = false; - config->txWatermark = kUSART_TxFifo0; - config->rxWatermark = kUSART_RxFifo1; - config->syncMode = kUSART_SyncModeDisabled; - config->enableContinuousSCLK = false; - config->clockPolarity = kUSART_RxSampleOnFallingEdge; -} - -/*! - * brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * endcode - * - * param base USART peripheral base address. - * param baudrate_Bps USART baudrate to be set. - * param srcClock_Hz USART clock source frequency in HZ. - * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * retval kStatus_Success Set baudrate succeed. - * retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) -{ - uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1; - uint32_t osrval, brgval, diff, baudrate; - - /* check arguments */ - assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); - if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) - { - return kStatus_InvalidArgument; - } - - /* If synchronous master mode is enabled, only configure the BRG value. */ - if (base->CFG & USART_CFG_SYNCEN_MASK) - { - if (base->CFG & USART_CFG_SYNCMST_MASK) - { - brgval = srcClock_Hz / baudrate_Bps; - base->BRG = brgval - 1; - } - } - else - { - /* - * Smaller values of OSR can make the sampling position within a data bit less accurate and may - * potentially cause more noise errors or incorrect data. - */ - for (osrval = best_osrval; osrval >= 8; osrval--) - { - brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1; - if (brgval > 0xFFFF) - { - continue; - } - baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1)); - diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate; - if (diff < best_diff) - { - best_diff = diff; - best_osrval = osrval; - best_brgval = brgval; - } - } - - /* value over range */ - if (best_brgval > 0xFFFF) - { - return kStatus_USART_BaudrateNotSupport; - } - - base->OSR = best_osrval; - base->BRG = best_brgval; - } - - return kStatus_Success; -} - -/*! - * brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * param base USART peripheral base address. - * param data Start address of the data to write. - * param length Size of the data to write. - */ -void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return; - } - /* Check whether txFIFO is enabled */ - if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) - { - return; - } - for (; length > 0; length--) - { - /* Loop until txFIFO get some space for new data */ - while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) - { - } - base->FIFOWR = *data; - data++; - } - /* Wait to finish transfer */ - while (!(base->STAT & USART_STAT_TXIDLE_MASK)) - { - } -} - -/*! - * brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * param base USART peripheral base address. - * param data Start address of the buffer to store the received data. - * param length Size of the buffer. - * retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * retval kStatus_USART_ParityError Noise error happened while receiving data. - * retval kStatus_USART_NoiseError Framing error happened while receiving data. - * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) -{ - uint32_t status; - - /* check arguments */ - assert(!((NULL == base) || (NULL == data))); - if ((NULL == base) || (NULL == data)) - { - return kStatus_InvalidArgument; - } - - /* Check whether rxFIFO is enabled */ - if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK)) - { - return kStatus_Fail; - } - for (; length > 0; length--) - { - /* loop until rxFIFO have some data to read */ - while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) - { - } - /* check receive status */ - status = base->STAT; - if (status & USART_STAT_FRAMERRINT_MASK) - { - base->STAT |= USART_STAT_FRAMERRINT_MASK; - return kStatus_USART_FramingError; - } - if (status & USART_STAT_PARITYERRINT_MASK) - { - base->STAT |= USART_STAT_PARITYERRINT_MASK; - return kStatus_USART_ParityError; - } - if (status & USART_STAT_RXNOISEINT_MASK) - { - base->STAT |= USART_STAT_RXNOISEINT_MASK; - return kStatus_USART_NoiseError; - } - /* check rxFIFO status */ - if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) - { - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - return kStatus_USART_RxError; - } - - *data = base->FIFORD; - data++; - } - return kStatus_Success; -} - -/*! - * brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param callback The callback function. - * param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData) -{ - int32_t instance = 0; - - /* Check 'base' */ - assert(!((NULL == base) || (NULL == handle))); - if ((NULL == base) || (NULL == handle)) - { - return kStatus_InvalidArgument; - } - - instance = USART_GetInstance(base); - - memset(handle, 0, sizeof(*handle)); - /* Set the TX/RX state. */ - handle->rxState = kUSART_RxIdle; - handle->txState = kUSART_TxIdle; - /* Set the callback and user data. */ - handle->callback = callback; - handle->userData = userData; - handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base); - handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base); - - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)USART_TransferHandleIRQ, handle); - - /* Enable interrupt in NVIC. */ - EnableIRQ(s_usartIRQ[instance]); - - return kStatus_Success; -} - -/*! - * brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the ref kStatus_USART_TxIdle as status parameter. - * - * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure. See #usart_transfer_t. - * retval kStatus_Success Successfully start the data transmission. - * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer) -{ - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); - if ((0 == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* Return error if current TX busy. */ - if (kUSART_TxBusy == handle->txState) - { - return kStatus_USART_TxBusy; - } - else - { - handle->txData = xfer->data; - handle->txDataSize = xfer->dataSize; - handle->txDataSizeAll = xfer->dataSize; - handle->txState = kUSART_TxBusy; - /* Enable transmiter interrupt. */ - base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK; - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Disable interrupts */ - USART_DisableInterrupts(base, kUSART_TxLevelInterruptEnable); - /* Empty txFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; - - handle->txDataSize = 0; - handle->txState = kUSART_TxIdle; -} - -/*! - * brief Get the number of bytes that have been written to USART TX register. - * - * This function gets the number of bytes that have been written to USART TX - * register by interrupt method. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Send bytes count. - * retval kStatus_NoTransferInProgress No send in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if (kUSART_TxIdle == handle->txState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->txDataSizeAll - handle->txDataSize; - - return kStatus_Success; -} - -/*! - * brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param xfer USART transfer structure, see #usart_transfer_t. - * param receivedBytes Bytes received from the ring buffer directly. - * retval kStatus_Success Successfully queue the transfer into transmit queue. - * retval kStatus_USART_RxBusy Previous receive request is not finished. - * retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes) -{ - uint32_t i; - /* How many bytes to copy from ring buffer to user memory. */ - size_t bytesToCopy = 0U; - /* How many bytes to receive. */ - size_t bytesToReceive; - /* How many bytes currently have received. */ - size_t bytesCurrentReceived; - uint32_t regPrimask = 0U; - - /* Check arguments */ - assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); - if ((NULL == base) || (NULL == handle) || (NULL == xfer)) - { - return kStatus_InvalidArgument; - } - /* Check xfer members */ - assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); - if ((0 == xfer->dataSize) || (NULL == xfer->data)) - { - return kStatus_InvalidArgument; - } - - /* How to get data: - 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize - to uart handle, enable interrupt to store received data to xfer->data. When - all data received, trigger callback. - 2. If RX ring buffer is enabled and not empty, get data from ring buffer first. - If there are enough data in ring buffer, copy them to xfer->data and return. - If there are not enough data in ring buffer, copy all of them to xfer->data, - save the xfer->data remained empty space to uart handle, receive data - to this empty space and trigger callback when finished. */ - if (kUSART_RxBusy == handle->rxState) - { - return kStatus_USART_RxBusy; - } - else - { - bytesToReceive = xfer->dataSize; - bytesCurrentReceived = 0U; - /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) - { - /* Disable IRQ, protect ring buffer. */ - regPrimask = DisableGlobalIRQ(); - /* How many bytes in RX ring buffer currently. */ - bytesToCopy = USART_TransferGetRxRingBufferLength(handle); - if (bytesToCopy) - { - bytesToCopy = MIN(bytesToReceive, bytesToCopy); - bytesToReceive -= bytesToCopy; - /* Copy data from ring buffer to user memory. */ - for (i = 0U; i < bytesToCopy; i++) - { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; - /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - } - /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) - { - /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUSART_RxBusy; - } - /* Enable IRQ if previously enabled. */ - EnableGlobalIRQ(regPrimask); - /* Call user callback since all data are received. */ - if (0 == bytesToReceive) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Ring buffer not used. */ - else - { - handle->rxData = xfer->data + bytesCurrentReceived; - handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUSART_RxBusy; - - /* Enable RX interrupt. */ - base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK; - } - /* Return the how many bytes have read. */ - if (receivedBytes) - { - *receivedBytes = bytesCurrentReceived; - } - } - return kStatus_Success; -} - -/*! - * brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) -{ - assert(NULL != handle); - - /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) - { - /* Disable interrupts */ - USART_DisableInterrupts(base, kUSART_RxLevelInterruptEnable); - /* Empty rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - } - - handle->rxDataSize = 0U; - handle->rxState = kUSART_RxIdle; -} - -/*! - * brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - * param count Receive bytes count. - * retval kStatus_NoTransferInProgress No receive in progress. - * retval kStatus_InvalidArgument Parameter is invalid. - * retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count) -{ - assert(NULL != handle); - assert(NULL != count); - - if (kUSART_RxIdle == handle->rxState) - { - return kStatus_NoTransferInProgress; - } - - *count = handle->rxDataSizeAll - handle->rxDataSize; - - return kStatus_Success; -} - -/*! - * brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * param base USART peripheral base address. - * param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) -{ - /* Check arguments */ - assert((NULL != base) && (NULL != handle)); - - bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer); - bool sendEnabled = handle->txDataSize; - - /* If RX overrun. */ - if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) - { - /* Clear rx error state. */ - base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - /* clear rxFIFO */ - base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; - /* Trigger callback. */ - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxError, handle->userData); - } - } - while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) || - (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))) - { - /* Receive data */ - if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) - { - /* Receive to app bufffer if app buffer is present */ - if (handle->rxDataSize) - { - *handle->rxData = base->FIFORD; - handle->rxDataSize--; - handle->rxData++; - receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer)); - if (!handle->rxDataSize) - { - if (!handle->rxRingBuffer) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; - } - handle->rxState = kUSART_RxIdle; - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); - } - } - } - /* Otherwise receive to ring buffer if ring buffer is present */ - else - { - if (handle->rxRingBuffer) - { - /* If RX ring buffer is full, trigger callback to notify over run. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); - } - } - /* If ring buffer is still full after callback function, the oldest data is overridden. */ - if (USART_TransferIsRxRingBufferFull(handle)) - { - /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferTail = 0U; - } - else - { - handle->rxRingBufferTail++; - } - } - /* Read data. */ - handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD; - /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) - { - handle->rxRingBufferHead = 0U; - } - else - { - handle->rxRingBufferHead++; - } - } - } - } - /* Send data */ - if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) - { - base->FIFOWR = *handle->txData; - handle->txDataSize--; - handle->txData++; - sendEnabled = handle->txDataSize != 0; - if (!sendEnabled) - { - base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; - handle->txState = kUSART_TxIdle; - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } - } - } - } - - /* ring buffer is not used */ - if (NULL == handle->rxRingBuffer) - { - /* restore if rx transfer ends and rxLevel is different from default value */ - if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); - } - /* decrease level if rx transfer is bellow */ - if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1))) - { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1)); - } - } -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_usart.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_usart.h deleted file mode 100644 index c0d64285e..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/drivers/fsl_usart.h +++ /dev/null @@ -1,718 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_USART_H_ -#define _FSL_USART_H_ - -#include "fsl_common.h" - -/*! - * @addtogroup usart_driver - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief USART driver version 2.1.0. */ -#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) -#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) - -/*! @brief Error codes for the USART driver. */ -enum _usart_status -{ - kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ - kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ - kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */ - kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */ - kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */ - kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */ - kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */ - kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */ - kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */ - kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ - kStatus_USART_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ -}; - -/*! @brief USART synchronous mode. */ -typedef enum _usart_sync_mode -{ - kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode. */ - kUSART_SyncModeSlave = 0x2U, /*!< Synchronous slave mode. */ - kUSART_SyncModeMaster = 0x3U, /*!< Synchronous master mode. */ -} usart_sync_mode_t; - -/*! @brief USART parity mode. */ -typedef enum _usart_parity_mode -{ - kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */ - kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ - kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ -} usart_parity_mode_t; - -/*! @brief USART stop bit count. */ -typedef enum _usart_stop_bit_count -{ - kUSART_OneStopBit = 0U, /*!< One stop bit */ - kUSART_TwoStopBit = 1U, /*!< Two stop bits */ -} usart_stop_bit_count_t; - -/*! @brief USART data size. */ -typedef enum _usart_data_len -{ - kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */ - kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */ -} usart_data_len_t; - -/*! @brief USART clock polarity configuration, used in sync mode.*/ -typedef enum _usart_clock_polarity -{ - kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */ - kUSART_RxSampleOnRisingEdge = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */ -} usart_clock_polarity_t; - -/*! @brief txFIFO watermark values */ -typedef enum _usart_txfifo_watermark -{ - kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */ - kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */ - kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */ - kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */ - kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */ - kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */ - kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */ - kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */ -} usart_txfifo_watermark_t; - -/*! @brief rxFIFO watermark values */ -typedef enum _usart_rxfifo_watermark -{ - kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */ - kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */ - kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */ - kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */ - kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */ - kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */ - kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */ - kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */ -} usart_rxfifo_watermark_t; - -/*! - * @brief USART interrupt configuration structure, default settings all disabled. - */ -enum _usart_interrupt_enable -{ - kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK), - kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), - kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), - kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), -}; - -/*! - * @brief USART status flags. - * - * This provides constants for the USART status flags for use in the USART functions. - */ -enum _usart_flags -{ - kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ - kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ - kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ - kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ - kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ - kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ -}; - -/*! @brief USART configuration structure. */ -typedef struct _usart_config -{ - uint32_t baudRate_Bps; /*!< USART baud rate */ - usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ - usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ - usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */ - bool loopback; /*!< Enable peripheral loopback */ - bool enableRx; /*!< Enable RX */ - bool enableTx; /*!< Enable TX */ - bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ - usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ - usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */ -} usart_config_t; - -/*! @brief USART transfer structure. */ -typedef struct _usart_transfer -{ - uint8_t *data; /*!< The buffer of data to be transfer.*/ - size_t dataSize; /*!< The byte count to be transfer. */ -} usart_transfer_t; - -/* Forward declaration of the handle typedef. */ -typedef struct _usart_handle usart_handle_t; - -/*! @brief USART transfer callback function. */ -typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData); - -/*! @brief USART handle structure. */ -struct _usart_handle -{ - uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ - - uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ - size_t rxRingBufferSize; /*!< Size of the ring buffer. */ - volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ - volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ - - usart_transfer_callback_t callback; /*!< Callback function. */ - void *userData; /*!< USART callback function parameter.*/ - - volatile uint8_t txState; /*!< TX transfer state. */ - volatile uint8_t rxState; /*!< RX transfer state */ - - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* _cplusplus */ - -/*! @brief Returns instance number for USART peripheral base address. */ -uint32_t USART_GetInstance(USART_Type *base); - -/*! - * @name Initialization and deinitialization - * @{ - */ - -/*! - * @brief Initializes a USART instance with user configuration structure and peripheral clock. - * - * This function configures the USART module with the user-defined settings. The user can configure the configuration - * structure and also get the default configuration by using the USART_GetDefaultConfig() function. - * Example below shows how to use this API to configure USART. - * @code - * usart_config_t usartConfig; - * usartConfig.baudRate_Bps = 115200U; - * usartConfig.parityMode = kUSART_ParityDisabled; - * usartConfig.stopBitCount = kUSART_OneStopBit; - * USART_Init(USART1, &usartConfig, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param config Pointer to user-defined configuration structure. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_InvalidArgument USART base address is not valid - * @retval kStatus_Success Status USART initialize succeed - */ -status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz); - -/*! - * @brief Deinitializes a USART instance. - * - * This function waits for TX complete, disables TX and RX, and disables the USART clock. - * - * @param base USART peripheral base address. - */ -void USART_Deinit(USART_Type *base); - -/*! - * @brief Gets the default configuration structure. - * - * This function initializes the USART configuration structure to a default value. The default - * values are: - * usartConfig->baudRate_Bps = 115200U; - * usartConfig->parityMode = kUSART_ParityDisabled; - * usartConfig->stopBitCount = kUSART_OneStopBit; - * usartConfig->bitCountPerChar = kUSART_8BitsPerChar; - * usartConfig->loopback = false; - * usartConfig->enableTx = false; - * usartConfig->enableRx = false; - * - * @param config Pointer to configuration structure. - */ -void USART_GetDefaultConfig(usart_config_t *config); - -/*! - * @brief Sets the USART instance baud rate. - * - * This function configures the USART module baud rate. This function is used to update - * the USART module baud rate after the USART module is initialized by the USART_Init. - * @code - * USART_SetBaudRate(USART1, 115200U, 20000000U); - * @endcode - * - * @param base USART peripheral base address. - * @param baudrate_Bps USART baudrate to be set. - * @param srcClock_Hz USART clock source frequency in HZ. - * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. - * @retval kStatus_Success Set baudrate succeed. - * @retval kStatus_InvalidArgument One or more arguments are invalid. - */ -status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); - -/* @} */ - -/*! - * @name Status - * @{ - */ - -/*! - * @brief Get USART status flags. - * - * This function get all USART status flags, the flags are returned as the logical - * OR value of the enumerators @ref _usart_flags. To check a specific status, - * compare the return value with enumerators in @ref _usart_flags. - * For example, to check whether the TX is empty: - * @code - * if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1)) - * { - * ... - * } - * @endcode - * - * @param base USART peripheral base address. - * @return USART status flags which are ORed by the enumerators in the _usart_flags. - */ -static inline uint32_t USART_GetStatusFlags(USART_Type *base) -{ - return base->FIFOSTAT; -} - -/*! - * @brief Clear USART status flags. - * - * This function clear supported USART status flags - * Flags that can be cleared or set are: - * kUSART_TxError - * kUSART_RxError - * For example: - * @code - * USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError) - * @endcode - * - * @param base USART peripheral base address. - * @param mask status flags to be cleared. - */ -static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) -{ - /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ - base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); -} - -/* @} */ - -/*! - * @name Interrupts - * @{ - */ - -/*! - * @brief Enables USART interrupts according to the provided mask. - * - * This function enables the USART interrupts according to the provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * For example, to enable TX empty interrupt and RX full interrupt: - * @code - * USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) -{ - base->FIFOINTENSET = mask & 0xF; -} - -/*! - * @brief Disables USART interrupts according to a provided mask. - * - * This function disables the USART interrupts according to a provided mask. The mask - * is a logical OR of enumeration members. See @ref _usart_interrupt_enable. - * This example shows how to disable the TX empty interrupt and RX full interrupt: - * @code - * USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable); - * @endcode - * - * @param base USART peripheral base address. - * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable. - */ -static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) -{ - base->FIFOINTENCLR = mask & 0xF; -} - -/*! - * @brief Returns enabled USART interrupts. - * - * This function returns the enabled USART interrupts. - * - * @param base USART peripheral base address. - */ -static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) -{ - return base->FIFOINTENSET; -} - -/*! - * @brief Enable DMA for Tx - */ -static inline void USART_EnableTxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK); - } -} - -/*! - * @brief Enable DMA for Rx - */ -static inline void USART_EnableRxDMA(USART_Type *base, bool enable) -{ - if (enable) - { - base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK; - } - else - { - base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK); - } -} - -/*! - * @brief Enable CTS. - * This function will determine whether CTS is used for flow control. - * - * @param base USART peripheral base address. - * @param enable Enable CTS or not, true for enable and false for disable. - */ -static inline void USART_EnableCTS(USART_Type *base, bool enable) -{ - if (enable) - { - base->CFG |= USART_CFG_CTSEN_MASK; - } - else - { - base->CFG &= ~USART_CFG_CTSEN_MASK; - } -} - -/*! - * @brief Continuous Clock generation. - * By default, SCLK is only output while data is being transmitted in synchronous mode. - * Enable this funciton, SCLK will run continuously in synchronous mode, allowing - * characters to be received on Un_RxD independently from transmission on Un_TXD). - * - * @param base USART peripheral base address. - * @param enable Enable Continuous Clock generation mode or not, true for enable and false for disable. - */ -static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CC_MASK; - } - else - { - base->CTL &= ~USART_CTL_CC_MASK; - } -} - -/*! - * @brief Enable Continuous Clock generation bit auto clear. - * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete - * character has been received. This bit is cleared at the same time. - * - * @param base USART peripheral base address. - * @param enable Enable auto clear or not, true for enable and false for disable. - */ -static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) -{ - if (enable) - { - base->CTL |= USART_CTL_CLRCCONRX_MASK; - } - else - { - base->CTL &= ~USART_CTL_CLRCCONRX_MASK; - } -} -/* @} */ - -/*! - * @name Bus Operations - * @{ - */ - -/*! - * @brief Writes to the FIFOWR register. - * - * This function writes data to the txFIFO directly. The upper layer must ensure - * that txFIFO has space for data to write before calling this function. - * - * @param base USART peripheral base address. - * @param data The byte to write. - */ -static inline void USART_WriteByte(USART_Type *base, uint8_t data) -{ - base->FIFOWR = data; -} - -/*! - * @brief Reads the FIFORD register directly. - * - * This function reads data from the rxFIFO directly. The upper layer must - * ensure that the rxFIFO is not empty before calling this function. - * - * @param base USART peripheral base address. - * @return The byte read from USART data register. - */ -static inline uint8_t USART_ReadByte(USART_Type *base) -{ - return base->FIFORD; -} - -/*! - * @brief Writes to the TX register using a blocking method. - * - * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO - * to have room and writes data to the TX buffer. - * - * @param base USART peripheral base address. - * @param data Start address of the data to write. - * @param length Size of the data to write. - */ -void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); - -/*! - * @brief Read RX data register using a blocking method. - * - * This function polls the RX register, waits for the RX register to be full or for RX FIFO to - * have data and read data from the TX register. - * - * @param base USART peripheral base address. - * @param data Start address of the buffer to store the received data. - * @param length Size of the buffer. - * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data. - * @retval kStatus_USART_ParityError Noise error happened while receiving data. - * @retval kStatus_USART_NoiseError Framing error happened while receiving data. - * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. - * @retval kStatus_Success Successfully received all data. - */ -status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); - -/* @} */ - -/*! - * @name Transactional - * @{ - */ - -/*! - * @brief Initializes the USART handle. - * - * This function initializes the USART handle which can be used for other USART - * transactional APIs. Usually, for a specified USART instance, - * call this API once to get the initialized handle. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param callback The callback function. - * @param userData The parameter of the callback function. - */ -status_t USART_TransferCreateHandle(USART_Type *base, - usart_handle_t *handle, - usart_transfer_callback_t callback, - void *userData); - -/*! - * @brief Transmits a buffer of data using the interrupt method. - * - * This function sends data using an interrupt method. This is a non-blocking function, which - * returns directly without waiting for all data to be written to the TX register. When - * all data is written to the TX register in the IRQ handler, the USART driver calls the callback - * function and passes the @ref kStatus_USART_TxIdle as status parameter. - * - * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure. See #usart_transfer_t. - * @retval kStatus_Success Successfully start the data transmission. - * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer); - -/*! - * @brief Sets up the RX ring buffer. - * - * This function sets up the RX ring buffer to a specific USART handle. - * - * When the RX ring buffer is used, data received are stored into the ring buffer even when the - * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received - * in the ring buffer, the user can get the received data from the ring buffer directly. - * - * @note When using the RX ring buffer, one byte is reserved for internal use. In other - * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. - * @param ringBufferSize size of the ring buffer. - */ -void USART_TransferStartRingBuffer(USART_Type *base, - usart_handle_t *handle, - uint8_t *ringBuffer, - size_t ringBufferSize); - -/*! - * @brief Aborts the background transfer and uninstalls the ring buffer. - * - * This function aborts the background transfer and uninstalls the ring buffer. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the length of received data in RX ring buffer. - * - * @param handle USART handle pointer. - * @return Length of received data in RX ring buffer. - */ -size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); - -/*! - * @brief Aborts the interrupt-driven data transmit. - * - * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out - * how many bytes are still not sent out. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been written to USART TX register. - * - * This function gets the number of bytes that have been written to USART TX - * register by interrupt method. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Send bytes count. - * @retval kStatus_NoTransferInProgress No send in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief Receives a buffer of data using an interrupt method. - * - * This function receives data using an interrupt method. This is a non-blocking function, which - * returns without waiting for all data to be received. - * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and - * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. - * After copying, if the data in the ring buffer is not enough to read, the receive - * request is saved by the USART driver. When the new data arrives, the receive request - * is serviced first. When all data is received, the USART driver notifies the upper layer - * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle. - * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. - * The 5 bytes are copied to the xfer->data and this function returns with the - * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is - * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer. - * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt - * to receive data to the xfer->data. When all data is received, the upper layer is notified. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param xfer USART transfer structure, see #usart_transfer_t. - * @param receivedBytes Bytes received from the ring buffer directly. - * @retval kStatus_Success Successfully queue the transfer into transmit queue. - * @retval kStatus_USART_RxBusy Previous receive request is not finished. - * @retval kStatus_InvalidArgument Invalid argument. - */ -status_t USART_TransferReceiveNonBlocking(USART_Type *base, - usart_handle_t *handle, - usart_transfer_t *xfer, - size_t *receivedBytes); - -/*! - * @brief Aborts the interrupt-driven data receiving. - * - * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out - * how many bytes not received yet. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle); - -/*! - * @brief Get the number of bytes that have been received. - * - * This function gets the number of bytes that have been received. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - * @param count Receive bytes count. - * @retval kStatus_NoTransferInProgress No receive in progress. - * @retval kStatus_InvalidArgument Parameter is invalid. - * @retval kStatus_Success Get successfully through the parameter \p count; - */ -status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count); - -/*! - * @brief USART IRQ handle function. - * - * This function handles the USART transmit and receive IRQ request. - * - * @param base USART peripheral base address. - * @param handle USART handle pointer. - */ -void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -/*! @}*/ - -#endif /* _FSL_USART_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/readme.txt b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/readme.txt deleted file mode 100644 index fb06ed3a5..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/readme.txt +++ /dev/null @@ -1,6 +0,0 @@ -This directory contains projects for GCC/IAR/Keil compilers. The targeted MCU is NXP LPC51U68, which is CM0+. - -todo: -- clean up IAR compiler warnings. (Though the warnings are in vendor's driver code, see if we can clean it up. ) -- finalize Keil linker script.(Two heap blocks shall be placed in intended RAM banks. Currently, both goes to a same RAM bank.) -- GCC project folder directory name is not consistent with the other two. diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_assert.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_assert.c deleted file mode 100644 index c07b55c6b..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_assert.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_common.h" -#include "fsl_debug_console.h" - -#ifndef NDEBUG -#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__)) -void __aeabi_assert(const char *failedExpr, const char *file, int line) -{ - PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); - for (;;) - { - __BKPT(0); - } -} -#elif (defined(__GNUC__)) -void __assert_func(const char *file, int line, const char *func, const char *failedExpr) -{ - PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func); - for (;;) - { - __BKPT(0); - } -} -#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ -#endif /* NDEBUG */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_debug_console.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_debug_console.c deleted file mode 100644 index b6d628a09..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_debug_console.c +++ /dev/null @@ -1,1123 +0,0 @@ -/* - * This is a modified version of the file printf.c, which was distributed - * by Motorola as part of the M5407C3BOOT.zip package used to initialize - * the M5407C3 evaluation board. - * - * Copyright: - * 1999-2000 MOTOROLA, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Motorola, Inc. This - * software is provided on an "AS IS" basis and without warranty. - * - * To the maximum extent permitted by applicable law, MOTOROLA - * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING - * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR - * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE - * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY - * ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING - * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS - * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY - * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Motorola assumes no responsibility for the maintenance and support - * of this software - - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) -#include -#endif - -#ifdef FSL_RTOS_FREE_RTOS -#include "FreeRTOS.h" -#include "semphr.h" -#include "task.h" -#endif - -#include "fsl_debug_console_conf.h" -#include "fsl_str.h" - -#include "fsl_common.h" -#include "serial_manager.h" - -#include "fsl_debug_console.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#ifndef NDEBUG -#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) -#undef assert -#define assert(n) -#endif -#endif - -#if SDK_DEBUGCONSOLE -#define DEBUG_CONSOLE_FUNCTION_PREFIX -#else -#define DEBUG_CONSOLE_FUNCTION_PREFIX static -#endif - -/*! @brief character backspace ASCII value */ -#define DEBUG_CONSOLE_BACKSPACE 127U - -/* lock definition */ -#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) - -static SemaphoreHandle_t s_debugConsoleReadSemaphore; -#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) -static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore; -#endif - -#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) - -#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) -static volatile uint8_t s_debugConsoleReadWaitSemaphore; -#endif - -#else - -#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ - -/*! @brief get current runing environment is ISR or not */ -#ifdef __CA7_REV -#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel() -#else -#define IS_RUNNING_IN_ISR() __get_IPSR() -#endif /* __CA7_REV */ - -/* semaphore definition */ -#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) - -/* mutex semaphore */ -#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex()) - -/* clang-format off */ -#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \ -{ \ - if (IS_RUNNING_IN_ISR() == 0U) \ - { \ - (void)xSemaphoreGive(mutex); \ - } \ -} - -#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \ -{ \ - if (IS_RUNNING_IN_ISR() == 0U) \ - { \ - (void)xSemaphoreTake(mutex, portMAX_DELAY); \ - } \ -} - -#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \ -{ \ - if (IS_RUNNING_IN_ISR() == 0U) \ - { \ - result = xSemaphoreTake(mutex, 0U); \ - } \ - else \ - { \ - result = 1U; \ - } \ -} -/* clang-format on */ - -/* Binary semaphore */ -#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary()) -#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake(binary, portMAX_DELAY)) -#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR(binary, NULL)) - -#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE) - -#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) -#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) -#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) -#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) - -#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \ - { \ - while (!binary) \ - { \ - } \ - binary = false; \ - } -#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true) -#else -#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) -#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -/* add other implementation here - *such as : - * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx) - */ - -#else - -#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE. - -#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/* receive state structure */ -typedef struct _debug_console_write_ring_buffer -{ - uint32_t ringBufferSize; - volatile uint32_t ringHead; - volatile uint32_t ringTail; - uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; -} debug_console_write_ring_buffer_t; -#endif - -typedef struct _debug_console_state_struct -{ - uint8_t serialHandleBuffer[SERIAL_MANAGER_HANDLE_SIZE]; - serial_handle_t serialHandle; /*!< serial manager handle */ -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING - debug_console_write_ring_buffer_t writeRingBuffer; - uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; -#endif - uint8_t serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE]; - uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE]; -} debug_console_state_struct_t; - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/*! @brief Debug console state information. */ -static debug_console_state_struct_t s_debugConsoleState; -serial_handle_t g_serialHandle; /*!< serial manager handle */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief This is a printf call back function which is used to relocate the log to buffer - * or print the log immediately when the local buffer is full. - * - * @param[in] buf Buffer to store log. - * @param[in] indicator Buffer index. - * @param[in] val Target character to store. - * @param[in] len length of the character - * - */ -#if SDK_DEBUGCONSOLE -static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len); -#endif - -status_t DbgConsole_ReadOneCharacter(uint8_t *ch); -int DbgConsole_SendData(uint8_t *ch, size_t size); -int DbgConsole_SendDataReliable(uint8_t *ch, size_t size); -int DbgConsole_ReadLine(uint8_t *buf, size_t size); -int DbgConsole_ReadCharacter(uint8_t *ch); - -#if ((SDK_DEBUGCONSOLE > 0U) || \ - ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ - (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) -DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void); -#endif -/******************************************************************************* - * Code - ******************************************************************************/ - -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) - -static void DbgConsole_SerialManagerTxCallback(void *callbackParam, - serial_manager_callback_message_t *message, - serial_manager_status_t status) -{ - debug_console_state_struct_t *ioState; - uint32_t sendDataLength; - - if ((NULL == callbackParam) || (NULL == message)) - { - return; - } - - ioState = (debug_console_state_struct_t *)callbackParam; - - ioState->writeRingBuffer.ringTail += message->length; - if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize) - { - ioState->writeRingBuffer.ringTail = 0U; - } - - if (kStatus_SerialManager_Success == status) - { - if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead) - { - if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail) - { - sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail; - } - else - { - sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail; - } - - (void)SerialManager_WriteNonBlocking( - ((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]), - &ioState->writeRingBuffer.ringBuffer[ioState->writeRingBuffer.ringTail], sendDataLength); - } - } - else if (kStatus_SerialManager_Canceled == status) - { - ioState->writeRingBuffer.ringTail = 0U; - ioState->writeRingBuffer.ringHead = 0U; - } - else - { - /*MISRA rule 16.4*/ - } -} - -#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) - -static void DbgConsole_SerialManagerRxCallback(void *callbackParam, - serial_manager_callback_message_t *message, - serial_manager_status_t status) -{ - if ((NULL == callbackParam) || (NULL == message)) - { - return; - } - - if (kStatus_SerialManager_Notify == status) - { - } - else if (kStatus_SerialManager_Success == status) - { - /* release s_debugConsoleReadWaitSemaphore from RX callback */ - DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore); - } - else - { - /*MISRA rule 16.4*/ - } -} -#endif - -#endif - -status_t DbgConsole_ReadOneCharacter(uint8_t *ch) -{ -#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) - -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ - (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) - return kStatus_Fail; -#else - status_t status = (status_t)kStatus_SerialManager_Error; - -/* recieve one char every time */ -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) - status = (status_t)SerialManager_ReadNonBlocking( - ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); -#else - status = (status_t)SerialManager_ReadBlocking( - ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); -#endif - if ((status_t)kStatus_SerialManager_Success != status) - { - return (status_t)kStatus_Fail; - } - /* wait s_debugConsoleReadWaitSemaphore from RX callback */ - DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore); - - return (status_t)kStatus_Success; -#endif - -#else - - return (status_t)kStatus_Fail; - -#endif -} - -#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION -static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index) -{ - /* Due to scanf take \n and \r as end of string,should not echo */ - if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar)) - { - /* recieve one char every time */ - if (1 != DbgConsole_SendDataReliable(ch, 1U)) - { - return (status_t)kStatus_Fail; - } - } - - if ((!isGetChar) && (index != NULL)) - { - if (DEBUG_CONSOLE_BACKSPACE == *ch) - { - if ((*index >= 2)) - { - *index -= 2; - } - else - { - *index = 0; - } - } - } - - return (status_t)kStatus_Success; -} -#endif - -int DbgConsole_SendData(uint8_t *ch, size_t size) -{ - status_t status = (status_t)kStatus_SerialManager_Error; -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) - uint32_t sendDataLength; - int txBusy = 0; -#endif - assert(NULL != ch); - assert(0 != size); - -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) - uint32_t regPrimask = DisableGlobalIRQ(); - if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) - { - txBusy = 1; - sendDataLength = - (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - - s_debugConsoleState.writeRingBuffer.ringTail) % - s_debugConsoleState.writeRingBuffer.ringBufferSize; - } - else - { - sendDataLength = 0U; - } - sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1; - if (sendDataLength <= size) - { - EnableGlobalIRQ(regPrimask); - return -1; - } - for (int i = 0; i < (int)size; i++) - { - s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i]; - if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize) - { - s_debugConsoleState.writeRingBuffer.ringHead = 0U; - } - } - - status = (status_t)kStatus_SerialManager_Success; - - if (txBusy == 0) - { - if (s_debugConsoleState.writeRingBuffer.ringHead > s_debugConsoleState.writeRingBuffer.ringTail) - { - sendDataLength = - s_debugConsoleState.writeRingBuffer.ringHead - s_debugConsoleState.writeRingBuffer.ringTail; - } - else - { - sendDataLength = - s_debugConsoleState.writeRingBuffer.ringBufferSize - s_debugConsoleState.writeRingBuffer.ringTail; - } - - status = (status_t)SerialManager_WriteNonBlocking( - ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), - &s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringTail], - sendDataLength); - } - EnableGlobalIRQ(regPrimask); -#else - status = (status_t)SerialManager_WriteBlocking( - ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); -#endif - return (((status_t)kStatus_Success == status) ? (int)size : -1); -} - -int DbgConsole_SendDataReliable(uint8_t *ch, size_t size) -{ -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) -#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) - status_t status = kStatus_SerialManager_Error; - uint32_t sendDataLength; - uint32_t totalLength = size; - int sentLength; -#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ -#else - status_t status = kStatus_SerialManager_Error; -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - - assert(NULL != ch); - assert(0 != size); - -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) - -#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) - do - { - uint32_t regPrimask = DisableGlobalIRQ(); - if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) - { - sendDataLength = - (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - - s_debugConsoleState.writeRingBuffer.ringTail) % - s_debugConsoleState.writeRingBuffer.ringBufferSize; - } - else - { - sendDataLength = 0U; - } - sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U; - - if (sendDataLength > 0U) - { - if (sendDataLength > totalLength) - { - sendDataLength = totalLength; - } - - sentLength = DbgConsole_SendData(&ch[size - totalLength], sendDataLength); - if (sentLength > 0) - { - totalLength = totalLength - (uint32_t)sentLength; - } - } - EnableGlobalIRQ(regPrimask); - - if (totalLength != 0U) - { - status = DbgConsole_Flush(); - if ((status_t)kStatus_Success != status) - { - break; - } - } - } while (totalLength != 0U); - return (status_t)(uint32_t)((uint32_t)size - totalLength); -#else - return DbgConsole_SendData(ch, size); -#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ - -#else - status = (status_t)SerialManager_WriteBlocking( - ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); - return (((status_t)kStatus_Success == status) ? (int)size : -1); -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ -} - -int DbgConsole_ReadLine(uint8_t *buf, size_t size) -{ - int i = 0; - - assert(buf != NULL); - - /* take mutex lock function */ - DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); - - do - { - /* recieve one char every time */ - if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i])) - { - /* release mutex lock function */ - DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); - i = -1; - break; - } -#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION - (void)DbgConsole_EchoCharacter(&buf[i], false, &i); -#endif - /* analysis data */ - if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i])) - { - /* End of Line. */ - if (0 == i) - { - buf[i] = (uint8_t)'\0'; - continue; - } - else - { - break; - } - } - i++; - } while (i < (int)size); - - /* get char should not add '\0'*/ - if (i == (int)size) - { - buf[i] = (uint8_t)'\0'; - } - else - { - buf[i + 1] = (uint8_t)'\0'; - } - - /* release mutex lock function */ - DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); - - return i; -} - -int DbgConsole_ReadCharacter(uint8_t *ch) -{ - int ret; - - assert(ch); - - /* take mutex lock function */ - DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); - /* read one character */ - if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch)) - { - ret = 1; -#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION - (void)DbgConsole_EchoCharacter(ch, true, NULL); -#endif - } - else - { - ret = -1; - } - - /* release mutex lock function */ - DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); - - return ret; -} - -#if SDK_DEBUGCONSOLE -static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len) -{ - int i = 0; - - for (i = 0; i < len; i++) - { - if (((uint32_t)*indicator + 1UL) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN) - { - (void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator)); - *indicator = 0; - } - - buf[*indicator] = dbgVal; - (*indicator)++; - } -} -#endif - -/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ - -/* See fsl_debug_console.h for documentation of this function. */ -status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq) -{ - serial_manager_config_t serialConfig; - status_t status = (status_t)kStatus_SerialManager_Error; - -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - serial_port_uart_config_t uartConfig = { - .instance = instance, - .clockRate = clkSrcFreq, - .baudRate = baudRate, - .parityMode = kSerialManager_UartParityDisabled, - .stopBitCount = kSerialManager_UartOneStopBit, - .enableRx = 1, - .enableTx = 1, - }; -#endif - -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - serial_port_usb_cdc_config_t usbCdcConfig = { - .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance, - }; -#endif - -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - serial_port_swo_config_t swoConfig = { - .clockRate = clkSrcFreq, - .baudRate = baudRate, - .port = instance, - .protocol = kSerialManager_SwoProtocolNrz, - }; -#endif - -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - serial_port_usb_cdc_virtual_config_t usbCdcVirtualConfig = { - .controllerIndex = (serial_port_usb_cdc_virtual_controller_index_t)instance, - }; -#endif - serialConfig.type = device; -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) - serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0]; - serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN; -#endif - - if (kSerialPort_Uart == device) - { -#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) - serialConfig.portConfig = &uartConfig; -#else - return status; -#endif - } - else if (kSerialPort_UsbCdc == device) - { -#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) - serialConfig.portConfig = &usbCdcConfig; -#else - return status; -#endif - } - else if (kSerialPort_Swo == device) - { -#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) - serialConfig.portConfig = &swoConfig; -#else - return status; -#endif - } - else if (kSerialPort_UsbCdcVirtual == device) - { -#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U)) - serialConfig.portConfig = &usbCdcVirtualConfig; -#else - return status; -#endif - } - else - { - return status; - } - - (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState)); - -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) - s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; -#endif - - s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0]; - status = (status_t)SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig); - - assert(kStatus_SerialManager_Success == status); - - DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); -#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) - DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore); -#endif - - { - status = (status_t)SerialManager_OpenWriteHandle( - s_debugConsoleState.serialHandle, ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); - assert(kStatus_SerialManager_Success == status); -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) - (void)SerialManager_InstallTxCallback(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), - DbgConsole_SerialManagerTxCallback, &s_debugConsoleState); -#endif - } - -#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) - { - status = (status_t)SerialManager_OpenReadHandle( - s_debugConsoleState.serialHandle, ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); - assert(kStatus_SerialManager_Success == status); -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) - (void)SerialManager_InstallRxCallback(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), - DbgConsole_SerialManagerRxCallback, &s_debugConsoleState); -#endif - } -#endif - - g_serialHandle = s_debugConsoleState.serialHandle; - - return kStatus_Success; -} - -/* See fsl_debug_console.h for documentation of this function. */ -status_t DbgConsole_Deinit(void) -{ - { - if (s_debugConsoleState.serialHandle != NULL) - { - (void)SerialManager_CloseWriteHandle( - ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); - } - } -#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) - { - if (s_debugConsoleState.serialHandle != NULL) - { - (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); - } - } -#endif - return (status_t)kStatus_Success; -} - -#if ((SDK_DEBUGCONSOLE > 0U) || \ - ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ - (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) -DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void) -{ -#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) - -#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) - - if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) - { - return (status_t)kStatus_Fail; - } - -#else - - while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) - { -#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) - if (0U == IS_RUNNING_IN_ISR()) - { - if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState()) - { - vTaskDelay(1); - } - } - else - { - return (status_t)kStatus_Fail; - } -#endif - } - -#endif - -#endif - return (status_t)kStatus_Success; -} -#endif - -#if SDK_DEBUGCONSOLE -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Printf(const char *formatString, ...) -{ - va_list ap; - int logLength = 0, dbgResult = 0; - char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'}; - - if (NULL == g_serialHandle) - { - return 0; - } - - va_start(ap, formatString); - /* format print log first */ - logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback); - /* print log */ - dbgResult = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength); - - va_end(ap); - - return dbgResult; -} - -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Putchar(int ch) -{ - /* print char */ - return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U); -} - -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Scanf(char *formatString, ...) -{ - va_list ap; - int formatResult; - char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'}; - - /* scanf log */ - (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN); - /* get va_list */ - va_start(ap, formatString); - /* format scanf log */ - formatResult = StrFormatScanf(scanfBuf, formatString, ap); - - va_end(ap); - - return formatResult; -} - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -status_t DbgConsole_TryGetchar(char *ch) -{ -#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) - uint32_t length = 0; - status_t status = (status_t)kStatus_Fail; - - assert(ch); - - /* take mutex lock function */ - DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); - - if (kStatus_SerialManager_Success == - SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1, - &length)) - { - if (length != 0U) - { -#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION - (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL); -#endif - status = (status_t)kStatus_Success; - } - } - /* release mutex lock function */ - DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); - return status; -#else - return (status_t)kStatus_Fail; -#endif -} -#endif - -/* See fsl_debug_console.h for documentation of this function. */ -int DbgConsole_Getchar(void) -{ - uint8_t ch = 0U; - - /* Get char */ - (void)DbgConsole_ReadCharacter(&ch); - - return (int)ch; -} - -#endif /* SDK_DEBUGCONSOLE */ - -/*************Code to support toolchain's printf, scanf *******************************/ -/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ -#if (defined(__ICCARM__)) -#if defined(SDK_DEBUGCONSOLE_UART) -#pragma weak __write -size_t __write(int handle, const unsigned char *buffer, size_t size) -{ - if (buffer == 0) - { - /* - * This means that we should flush internal buffers. Since we don't we just return. - * (Remember, "handle" == -1 means that all handles should be flushed.) - */ - return 0; - } - - /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ - if ((handle != 1) && (handle != 2)) - { - return ((size_t)-1); - } - - /* Send data. */ - DbgConsole_SendDataReliable((uint8_t *)buffer, size); - - return size; -} - -#pragma weak __read -size_t __read(int handle, unsigned char *buffer, size_t size) -{ - uint8_t ch = 0U; - int actualSize = 0U; - - /* This function only reads from "standard in", for all other file handles it returns failure. */ - if (handle != 0) - { - return ((size_t)-1); - } - - /* Receive data.*/ - for (; size > 0; size--) - { - DbgConsole_ReadCharacter(&ch); - if (ch == 0) - { - break; - } - - *buffer++ = ch; - actualSize++; - } - - return actualSize; -} -#endif /* SDK_DEBUGCONSOLE_UART */ - -/* support LPC Xpresso with RedLib */ -#elif (defined(__REDLIB__)) - -#if (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)) -int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) -{ - if (buffer == 0) - { - /* return -1 if error. */ - return -1; - } - - /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ - if ((handle != 1) && (handle != 2)) - { - return -1; - } - - /* Send data. */ - DbgConsole_SendDataReliable((uint8_t *)buffer, size); - - return 0; -} - -int __attribute__((weak)) __sys_readc(void) -{ - char tmp; - - /* Receive data. */ - DbgConsole_ReadCharacter((uint8_t *)&tmp); - - return tmp; -} -#endif - -/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -#if defined(SDK_DEBUGCONSOLE_UART) -#if defined(__CC_ARM) -struct __FILE -{ - int handle; - /* - * Whatever you require here. If the only file you are using is standard output using printf() for debugging, - * no file handling is required. - */ -}; -#endif - -/* FILE is typedef in stdio.h. */ -#pragma weak __stdout -#pragma weak __stdin -FILE __stdout; -FILE __stdin; - -#pragma weak fputc -int fputc(int ch, FILE *f) -{ - /* Send data. */ - return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1); -} - -#pragma weak fgetc -int fgetc(FILE *f) -{ - char ch; - - /* Receive data. */ - DbgConsole_ReadCharacter((uint8_t *)&ch); - - return ch; -} - -/* - * Terminate the program, passing a return code back to the user. - * This function may not return. - */ -void _sys_exit(int returncode) -{ - while (1) - { - } -} - -/* - * Writes a character to the output channel. This function is used - * for last-resort error message output. - */ -void _ttywrch(int ch) -{ - char ench = ch; - DbgConsole_SendDataReliable((uint8_t *)(&ench), 1); -} - -char *_sys_command_string(char *cmd, int len) -{ - return (cmd); -} -#endif /* SDK_DEBUGCONSOLE_UART */ - -/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ -#elif (defined(__GNUC__)) - -#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ - (defined(__MCUXPRESSO) && (!SDK_DEBUGCONSOLE) && (defined(SDK_DEBUGCONSOLE_UART)))) -int __attribute__((weak)) _write(int handle, char *buffer, int size); -int __attribute__((weak)) _write(int handle, char *buffer, int size) -{ - if (buffer == NULL) - { - /* return -1 if error. */ - return -1; - } - - /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ - if ((handle != 1) && (handle != 2)) - { - return -1; - } - - /* Send data. */ - (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size); - - return size; -} - -int __attribute__((weak)) _read(int handle, char *buffer, int size); -int __attribute__((weak)) _read(int handle, char *buffer, int size) -{ - uint8_t ch = 0U; - int actualSize = 0; - - /* This function only reads from "standard in", for all other file handles it returns failure. */ - if (handle != 0) - { - return -1; - } - - /* Receive data. */ - for (; size > 0; size--) - { - if (DbgConsole_ReadCharacter(&ch) < 0) - { - break; - } - - *buffer++ = (char)ch; - actualSize++; - - if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r')) - { - break; - } - } - - return (actualSize > 0) ? actualSize : -1; -} -#endif - -#endif /* __ICCARM__ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_debug_console.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_debug_console.h deleted file mode 100644 index 500bb7bf4..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_debug_console.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Debug console shall provide input and output functions to scan and print formatted data. - * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" - * - [flags] :'-', '+', '#', ' ', '0' - * - [width]: number (0,1...) - * - [.precision]: number (0,1...) - * - [length]: do not support - * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' - * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" - * - [*]: is supported. - * - [width]: number (0,1...) - * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') - * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' - */ - -#ifndef _FSL_DEBUGCONSOLE_H_ -#define _FSL_DEBUGCONSOLE_H_ - -#include "fsl_common.h" -#include "serial_manager.h" - -/*! - * @addtogroup debugconsole - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -extern serial_handle_t g_serialHandle; /*!< serial manager handle */ - -/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */ -#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */ -#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */ -#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */ - -/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support - * to be redefined in project setting. - */ -#ifndef SDK_DEBUGCONSOLE -#define SDK_DEBUGCONSOLE 1U -#endif - -/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. */ -#ifndef SDK_DEBUGCONSOLE_UART -/* mcux will handle this macro, not define it here */ -#if (!defined(__MCUXPRESSO)) -#define SDK_DEBUGCONSOLE_UART -#endif -#endif - -#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) -#include -#endif - -/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. - * - * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf. - * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf. - * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function. - */ -#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */ -#define PRINTF -#define SCANF -#define PUTCHAR -#define GETCHAR -#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */ -#define PRINTF DbgConsole_Printf -#define SCANF DbgConsole_Scanf -#define PUTCHAR DbgConsole_Putchar -#define GETCHAR DbgConsole_Getchar -#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \ - */ -#define PRINTF printf -#define SCANF scanf -#define PUTCHAR putchar -#define GETCHAR getchar -#endif /* SDK_DEBUGCONSOLE */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! @name Initialization*/ -/* @{ */ - -/*! - * @brief Initializes the peripheral used for debug messages. - * - * Call this function to enable debug log messages to be output via the specified peripheral - * initialized by the serial manager module. - * After this function has returned, stdout and stdin are connected to the selected peripheral. - * - * @param instance The instance of the module. - * @param baudRate The desired baud rate in bits per second. - * @param device Low level device type for the debug console, can be one of the following. - * @arg kSerialPort_Uart, - * @arg kSerialPort_UsbCdc - * @arg kSerialPort_UsbCdcVirtual. - * @param clkSrcFreq Frequency of peripheral source clock. - * - * @return Indicates whether initialization was successful or not. - * @retval kStatus_Success Execution successfully - */ -status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq); - -/*! - * @brief De-initializes the peripheral used for debug messages. - * - * Call this function to disable debug log messages to be output via the specified peripheral - * initialized by the serial manager module. - * - * @return Indicates whether de-initialization was successful or not. - */ -status_t DbgConsole_Deinit(void); - -#if SDK_DEBUGCONSOLE -/*! - * @brief Writes formatted output to the standard output stream. - * - * Call this function to write a formatted output to the standard output stream. - * - * @param formatString Format control string. - * @return Returns the number of characters printed or a negative value if an error occurs. - */ -int DbgConsole_Printf(const char *formatString, ...); - -/*! - * @brief Writes a character to stdout. - * - * Call this function to write a character to stdout. - * - * @param ch Character to be written. - * @return Returns the character written. - */ -int DbgConsole_Putchar(int ch); - -/*! - * @brief Reads formatted data from the standard input stream. - * - * Call this function to read formatted data from the standard input stream. - * - * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, - * other tasks will not be scheduled), the function cannot be used when the - * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. - * And an error is returned when the function called in this case. The suggestion - * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. - * - * @param formatString Format control string. - * @return Returns the number of fields successfully converted and assigned. - */ -int DbgConsole_Scanf(char *formatString, ...); - -/*! - * @brief Reads a character from standard input. - * - * Call this function to read a character from standard input. - * - * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, - * other tasks will not be scheduled), the function cannot be used when the - * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. - * And an error is returned when the function called in this case. The suggestion - * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. - * - * @return Returns the character read. - */ -int DbgConsole_Getchar(void); - -/*! - * @brief Debug console flush. - * - * Call this function to wait the tx buffer empty. - * If interrupt transfer is using, make sure the global IRQ is enable before call this function - * This function should be called when - * 1, before enter power down mode - * 2, log is required to print to terminal immediately - * @return Indicates whether wait idle was successful or not. - */ -status_t DbgConsole_Flush(void); - -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/*! - * @brief Debug console try to get char - * This function provides a API which will not block current task, if character is - * available return it, otherwise return fail. - * @param ch the address of char to receive - * @return Indicates get char was successful or not. - */ -status_t DbgConsole_TryGetchar(char *ch); -#endif - -#endif /* SDK_DEBUGCONSOLE */ - -/*! @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_debug_console_conf.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_debug_console_conf.h deleted file mode 100644 index 4c36a7dd8..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_debug_console_conf.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright 2017 - 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ -#define _FSL_DEBUG_CONSOLE_CONF_H_ - -/****************Debug console configuration********************/ - -/*! @brief If Non-blocking mode is needed, please define it at project setting, - * otherwise blocking mode is the default transfer mode. - * Warning: If you want to use non-blocking transfer,please make sure the corresponding - * IO interrupt is enable, otherwise there is no output. - * And non-blocking is combine with buffer, no matter bare-metal or rtos. - * Below shows how to configure in your project if you want to use non-blocking mode. - * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols". - * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define". - * For ARMGCC, open CmakeLists.txt and add the following lines, - * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target. - * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target. - * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C - * Complier->Preprocessor". - * - */ -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically - * when - * non-blocking transfer is using, - * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. - * If it is configured too small, log maybe missed , because the log will not be - * buffered if the buffer is full, and the print will return immediately with -1. - * And this value should be multiple of 4 to meet memory alignment. - * - */ -#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN -#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) -#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ - -/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when - * non-blocking transfer is using, - * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. - * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. - * And this value should be multiple of 4 to meet memory alignment. - * - */ -#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN -#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U) -#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ - -/*!@ brief Whether enable the reliable TX function - * If the macro is zero, the reliable TX function of the debug console is disabled. - * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full. - */ -#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE -#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U) -#endif /* DEBUG_CONSOLE_RX_ENABLE */ - -#else -#define DEBUG_CONSOLE_TRANSFER_BLOCKING -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ - -/*!@ brief Whether enable the RX function - * If the macro is zero, the receive function of the debug console is disabled. - */ -#ifndef DEBUG_CONSOLE_RX_ENABLE -#define DEBUG_CONSOLE_RX_ENABLE (1U) -#endif /* DEBUG_CONSOLE_RX_ENABLE */ - -/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log - * length can not bigger than this value. - * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if - * the buffer is too big and current task stack size not big enough. - */ -#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN -#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) -#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ - -/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log - * length can not bigger than this value. - * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. - */ -#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN -#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) -#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ - -/*! @brief Debug console synchronization - * User should not change these macro for synchronization mode, but add the - * corresponding synchronization mechanism per different software environment. - * Such as, if another RTOS is used, - * add: - * #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 - * in this configuration file and implement the synchronization in fsl.log.c. - */ -/*! @brief synchronization for baremetal software */ -#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 -/*! @brief synchronization for freertos software */ -#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 - -/*! @brief RTOS synchronization mechanism disable - * If not defined, default is enable, to avoid multitask log print mess. - * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c - * If synchronization is disabled, log maybe messed on terminal. - */ -#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION -#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING -#ifdef FSL_RTOS_FREE_RTOS -#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS -#else -#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM -#endif /* FSL_RTOS_FREE_RTOS */ -#else -#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM -#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ -#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ - -/*! @brief echo function support - * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO - * at your project setting. - */ -#ifndef DEBUG_CONSOLE_ENABLE_ECHO -#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 -#else -#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 -#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ - -/*********************************************************************/ - -/***************Debug console other configuration*********************/ -/*! @brief Definition to printf the float number. */ -#ifndef PRINTF_FLOAT_ENABLE -#define PRINTF_FLOAT_ENABLE 0U -#endif /* PRINTF_FLOAT_ENABLE */ - -/*! @brief Definition to scanf the float number. */ -#ifndef SCANF_FLOAT_ENABLE -#define SCANF_FLOAT_ENABLE 0U -#endif /* SCANF_FLOAT_ENABLE */ - -/*! @brief Definition to support advanced format specifier for printf. */ -#ifndef PRINTF_ADVANCED_ENABLE -#define PRINTF_ADVANCED_ENABLE 0U -#endif /* PRINTF_ADVANCED_ENABLE */ - -/*! @brief Definition to support advanced format specifier for scanf. */ -#ifndef SCANF_ADVANCED_ENABLE -#define SCANF_ADVANCED_ENABLE 0U -#endif /* SCANF_ADVANCED_ENABLE */ - -/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ -#ifndef BOARD_USE_VIRTUALCOM -#define BOARD_USE_VIRTUALCOM 0U -#endif -/*******************************************************************/ - -#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_str.c b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_str.c deleted file mode 100644 index 1a49a45e9..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_str.c +++ /dev/null @@ -1,1324 +0,0 @@ -/* - * Copyright 2017 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include -#include -#include -#include "fsl_str.h" -#include "fsl_debug_console_conf.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief The overflow value.*/ -#ifndef HUGE_VAL -#define HUGE_VAL (99.e99) -#endif /* HUGE_VAL */ - -#if PRINTF_ADVANCED_ENABLE -/*! @brief Specification modifier flags for printf. */ -enum _debugconsole_printf_flag -{ - kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ - kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ - kPRINTF_Space = 0x04U, /*!< Space Flag. */ - kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ - kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ - kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ - kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ - kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ - kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ -}; -#endif /* PRINTF_ADVANCED_ENABLE */ - -/*! @brief Specification modifier flags for scanf. */ -enum _debugconsole_scanf_flag -{ - kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ - kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ - kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ - kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ - kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ - kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ - kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ - kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ -#if SCANF_ADVANCED_ENABLE - kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ - kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ - kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ - kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ -#endif /* SCANF_ADVANCED_ENABLE */ -#if SCANF_FLOAT_ENABLE - kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ -#endif /*PRINTF_FLOAT_ENABLE */ - kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ -}; - -/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ -#if defined(__CC_ARM) -#pragma diag_suppress 1256 -#endif /* __CC_ARM */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Scanline function which ignores white spaces. - * - * @param[in] s The address of the string pointer to update. - * @return String without white spaces. - */ -static uint32_t ScanIgnoreWhiteSpace(const char **s); - -/*! - * @brief Converts a radix number to a string and return its length. - * - * @param[in] numstr Converted string of the number. - * @param[in] nump Pointer to the number. - * @param[in] neg Polarity of the number. - * @param[in] radix The radix to be converted to. - * @param[in] use_caps Used to identify %x/X output format. - - * @return Length of the converted string. - */ -static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps); - -#if PRINTF_FLOAT_ENABLE -/*! - * @brief Converts a floating radix number to a string and return its length. - * - * @param[in] numstr Converted string of the number. - * @param[in] nump Pointer to the number. - * @param[in] radix The radix to be converted to. - * @param[in] precision_width Specify the precision width. - - * @return Length of the converted string. - */ -static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width); -#endif /* PRINTF_FLOAT_ENABLE */ - -/*! - * - */ -double modf(double input_dbl, double *intpart_ptr); - -/*************Code for process formatted data*******************************/ - -static uint32_t ScanIgnoreWhiteSpace(const char **s) -{ - uint8_t count = 0; - uint8_t c; - - c = **s; - while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) - { - count++; - (*s)++; - c = **s; - } - return count; -} - -static int32_t ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps) -{ -#if PRINTF_ADVANCED_ENABLE - int64_t a; - int64_t b; - int64_t c; - - uint64_t ua; - uint64_t ub; - uint64_t uc; -#else - int32_t a; - int32_t b; - int32_t c; - - uint32_t ua; - uint32_t ub; - uint32_t uc; -#endif /* PRINTF_ADVANCED_ENABLE */ - - int32_t nlen; - char *nstrp; - - nlen = 0; - nstrp = numstr; - *nstrp++ = '\0'; - - if (neg) - { -#if PRINTF_ADVANCED_ENABLE - a = *(int64_t *)nump; -#else - a = *(int32_t *)nump; -#endif /* PRINTF_ADVANCED_ENABLE */ - if (a == 0) - { - *nstrp = '0'; - ++nlen; - return nlen; - } - while (a != 0) - { -#if PRINTF_ADVANCED_ENABLE - b = (int64_t)a / (int64_t)radix; - c = (int64_t)a - ((int64_t)b * (int64_t)radix); - if (c < 0) - { - uc = (uint64_t)c; - c = (int64_t)(~uc) + 1 + '0'; - } -#else - b = a / radix; - c = a - (b * radix); - if (c < 0) - { - uc = (uint32_t)c; - c = (uint32_t)(~uc) + 1 + '0'; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - else - { - c = c + '0'; - } - a = b; - *nstrp++ = (char)c; - ++nlen; - } - } - else - { -#if PRINTF_ADVANCED_ENABLE - ua = *(uint64_t *)nump; -#else - ua = *(uint32_t *)nump; -#endif /* PRINTF_ADVANCED_ENABLE */ - if (ua == 0) - { - *nstrp = '0'; - ++nlen; - return nlen; - } - while (ua != 0) - { -#if PRINTF_ADVANCED_ENABLE - ub = (uint64_t)ua / (uint64_t)radix; - uc = (uint64_t)ua - ((uint64_t)ub * (uint64_t)radix); -#else - ub = ua / (uint32_t)radix; - uc = ua - (ub * (uint32_t)radix); -#endif /* PRINTF_ADVANCED_ENABLE */ - - if (uc < 10) - { - uc = uc + '0'; - } - else - { - uc = uc - 10 + (use_caps ? 'A' : 'a'); - } - ua = ub; - *nstrp++ = (char)uc; - ++nlen; - } - } - return nlen; -} - -#if PRINTF_FLOAT_ENABLE -static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width) -{ - int32_t a; - int32_t b; - int32_t c; - int32_t i; - uint32_t uc; - double fa; - double dc; - double fb; - double r; - double fractpart; - double intpart; - - int32_t nlen; - char *nstrp; - nlen = 0; - nstrp = numstr; - *nstrp++ = '\0'; - r = *(double *)nump; - if (!r) - { - *nstrp = '0'; - ++nlen; - return nlen; - } - fractpart = modf((double)r, (double *)&intpart); - /* Process fractional part. */ - for (i = 0; i < precision_width; i++) - { - fractpart *= radix; - } - if (r >= 0) - { - fa = fractpart + (double)0.5; - if (fa >= pow(10, precision_width)) - { - intpart++; - } - } - else - { - fa = fractpart - (double)0.5; - if (fa <= -pow(10, precision_width)) - { - intpart--; - } - } - for (i = 0; i < precision_width; i++) - { - fb = fa / (int32_t)radix; - dc = (fa - (int64_t)fb * (int32_t)radix); - c = (int32_t)dc; - if (c < 0) - { - uc = (uint32_t)c; - c = (int32_t)(~uc) + 1 + '0'; - } - else - { - c = c + '0'; - } - fa = fb; - *nstrp++ = (char)c; - ++nlen; - } - *nstrp++ = (char)'.'; - ++nlen; - a = (int32_t)intpart; - if (a == 0) - { - *nstrp++ = '0'; - ++nlen; - } - else - { - while (a != 0) - { - b = (int32_t)a / (int32_t)radix; - c = (int32_t)a - ((int32_t)b * (int32_t)radix); - if (c < 0) - { - uc = (uint32_t)c; - c = (int32_t)(~uc) + 1 + '0'; - } - else - { - c = c + '0'; - } - a = b; - *nstrp++ = (char)c; - ++nlen; - } - } - return nlen; -} -#endif /* PRINTF_FLOAT_ENABLE */ - -/*! - * brief This function outputs its parameters according to a formatted string. - * - * note I/O is performed by calling given function pointer using following - * (*func_ptr)(c); - * - * param[in] fmt_ptr Format string for printf. - * param[in] args_ptr Arguments to printf. - * param[in] buf pointer to the buffer - * param cb print callback function pointer - * - * return Number of characters to be print - */ -int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb) -{ - /* va_list ap; */ - char *p; - int32_t c; - - char vstr[33]; - char *vstrp = NULL; - int32_t vlen = 0; - - int32_t done; - int32_t count = 0; - - uint32_t field_width; - uint32_t precision_width; - char *sval; - int32_t cval; - bool use_caps; - uint8_t radix = 0; - -#if PRINTF_ADVANCED_ENABLE - uint32_t flags_used; - int32_t schar, dschar; - int64_t ival; - uint64_t uval = 0; - bool valid_precision_width; -#else - int32_t ival; - uint32_t uval = 0; -#endif /* PRINTF_ADVANCED_ENABLE */ - -#if PRINTF_FLOAT_ENABLE - double fval; -#endif /* PRINTF_FLOAT_ENABLE */ - - /* Start parsing apart the format string and display appropriate formats and data. */ - for (p = (char *)fmt; (c = *p) != 0; p++) - { - /* - * All formats begin with a '%' marker. Special chars like - * '\n' or '\t' are normally converted to the appropriate - * character by the __compiler__. Thus, no need for this - * routine to account for the '\' character. - */ - if (c != '%') - { - cb(buf, &count, c, 1); - /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ - continue; - } - - use_caps = true; - -#if PRINTF_ADVANCED_ENABLE - /* First check for specification modifier flags. */ - flags_used = 0; - done = false; - while (!done) - { - switch (*++p) - { - case '-': - flags_used |= kPRINTF_Minus; - break; - case '+': - flags_used |= kPRINTF_Plus; - break; - case ' ': - flags_used |= kPRINTF_Space; - break; - case '0': - flags_used |= kPRINTF_Zero; - break; - case '#': - flags_used |= kPRINTF_Pound; - break; - default: - /* We've gone one char too far. */ - --p; - done = true; - break; - } - } -#endif /* PRINTF_ADVANCED_ENABLE */ - - /* Next check for minimum field width. */ - field_width = 0; - done = false; - while (!done) - { - c = *++p; - if ((c >= '0') && (c <= '9')) - { - field_width = (field_width * 10) + (c - '0'); - } -#if PRINTF_ADVANCED_ENABLE - else if (c == '*') - { - field_width = (uint32_t)va_arg(ap, uint32_t); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - else - { - /* We've gone one char too far. */ - --p; - done = true; - } - } - /* Next check for the width and precision field separator. */ - precision_width = 6; -#if PRINTF_ADVANCED_ENABLE - valid_precision_width = false; -#endif /* PRINTF_ADVANCED_ENABLE */ - if (*++p == '.') - { - /* Must get precision field width, if present. */ - precision_width = 0; - done = false; - while (!done) - { - c = *++p; - if ((c >= '0') && (c <= '9')) - { - precision_width = (precision_width * 10) + (c - '0'); -#if PRINTF_ADVANCED_ENABLE - valid_precision_width = true; -#endif /* PRINTF_ADVANCED_ENABLE */ - } -#if PRINTF_ADVANCED_ENABLE - else if (c == '*') - { - precision_width = (uint32_t)va_arg(ap, uint32_t); - valid_precision_width = true; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - else - { - /* We've gone one char too far. */ - --p; - done = true; - } - } - } - else - { - /* We've gone one char too far. */ - --p; - } -#if PRINTF_ADVANCED_ENABLE - /* - * Check for the length modifier. - */ - switch (/* c = */ *++p) - { - case 'h': - if (*++p != 'h') - { - flags_used |= kPRINTF_LengthShortInt; - --p; - } - else - { - flags_used |= kPRINTF_LengthChar; - } - break; - case 'l': - if (*++p != 'l') - { - flags_used |= kPRINTF_LengthLongInt; - --p; - } - else - { - flags_used |= kPRINTF_LengthLongLongInt; - } - break; - default: - /* we've gone one char too far */ - --p; - break; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - /* Now we're ready to examine the format. */ - c = *++p; - { - if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') || - (c == 'b') || (c == 'p') || (c == 'u')) - { - if ((c == 'd') || (c == 'i')) - { -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_LengthLongLongInt) - { - ival = (int64_t)va_arg(ap, int64_t); - } - else -#endif /* PRINTF_ADVANCED_ENABLE */ - { - ival = (int32_t)va_arg(ap, int32_t); - } - vlen = ConvertRadixNumToString(vstr, &ival, true, 10, use_caps); - vstrp = &vstr[vlen]; -#if PRINTF_ADVANCED_ENABLE - if (ival < 0) - { - schar = '-'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Plus) - { - schar = '+'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Space) - { - schar = ' '; - ++vlen; - } - else - { - schar = 0; - } - } - } - dschar = false; - /* Do the ZERO pad. */ - if (flags_used & kPRINTF_Zero) - { - if (schar) - { - cb(buf, &count, schar, 1); - } - dschar = true; - - cb(buf, &count, '0', field_width - vlen); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - cb(buf, &count, ' ', field_width - vlen); - if (schar) - { - cb(buf, &count, schar, 1); - } - dschar = true; - } - } - /* The string was built in reverse order, now display in correct order. */ - if ((!dschar) && schar) - { - cb(buf, &count, schar, 1); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - -#if PRINTF_FLOAT_ENABLE - if ((c == 'f') || (c == 'F')) - { - fval = (double)va_arg(ap, double); - vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); - vstrp = &vstr[vlen]; - -#if PRINTF_ADVANCED_ENABLE - if (fval < 0) - { - schar = '-'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Plus) - { - schar = '+'; - ++vlen; - } - else - { - if (flags_used & kPRINTF_Space) - { - schar = ' '; - ++vlen; - } - else - { - schar = 0; - } - } - } - dschar = false; - if (flags_used & kPRINTF_Zero) - { - if (schar) - { - cb(buf, &count, schar, 1); - } - dschar = true; - cb(buf, &count, '0', field_width - vlen); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - cb(buf, &count, ' ', field_width - vlen); - if (schar) - { - cb(buf, &count, schar, 1); - } - dschar = true; - } - } - if ((!dschar) && schar) - { - cb(buf, &count, schar, 1); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } -#endif /* PRINTF_FLOAT_ENABLE */ - if ((c == 'X') || (c == 'x')) - { - if (c == 'x') - { - use_caps = false; - } -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_LengthLongLongInt) - { - uval = (uint64_t)va_arg(ap, uint64_t); - } - else -#endif /* PRINTF_ADVANCED_ENABLE */ - { - uval = (uint32_t)va_arg(ap, uint32_t); - } - vlen = ConvertRadixNumToString(vstr, &uval, false, 16, use_caps); - vstrp = &vstr[vlen]; - -#if PRINTF_ADVANCED_ENABLE - dschar = false; - if (flags_used & kPRINTF_Zero) - { - if (flags_used & kPRINTF_Pound) - { - cb(buf, &count, '0', 1); - cb(buf, &count, (use_caps ? 'X' : 'x'), 1); - dschar = true; - } - cb(buf, &count, '0', field_width - vlen); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - if (flags_used & kPRINTF_Pound) - { - vlen += 2; - } - cb(buf, &count, ' ', field_width - vlen); - if (flags_used & kPRINTF_Pound) - { - cb(buf, &count, '0', 1); - cb(buf, &count, (use_caps ? 'X' : 'x'), 1); - dschar = true; - } - } - } - - if ((flags_used & kPRINTF_Pound) && (!dschar)) - { - cb(buf, &count, '0', 1); - cb(buf, &count, (use_caps ? 'X' : 'x'), 1); - vlen += 2; - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) - { -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_LengthLongLongInt) - { - uval = (uint64_t)va_arg(ap, uint64_t); - } - else -#endif /* PRINTF_ADVANCED_ENABLE */ - { - uval = (uint32_t)va_arg(ap, uint32_t); - } - - if (c == 'o') - { - radix = 8; - } - else if (c == 'b') - { - radix = 2; - } - else if (c == 'p') - { - radix = 16; - } - else - { - radix = 10; - } - - vlen = ConvertRadixNumToString(vstr, &uval, false, radix, use_caps); - vstrp = &vstr[vlen]; -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_Zero) - { - cb(buf, &count, '0', field_width - vlen); - vlen = field_width; - } - else - { - if (!(flags_used & kPRINTF_Minus)) - { - cb(buf, &count, ' ', field_width - vlen); - } - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } -#if !PRINTF_ADVANCED_ENABLE - cb(buf, &count, ' ', field_width - vlen); -#endif /* !PRINTF_ADVANCED_ENABLE */ - if (vstrp != NULL) - { - while (*vstrp) - { - cb(buf, &count, *vstrp--, 1); - } - } -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_Minus) - { - cb(buf, &count, ' ', field_width - vlen); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - else if (c == 'c') - { - cval = (char)va_arg(ap, uint32_t); - cb(buf, &count, cval, 1); - } - else if (c == 's') - { - sval = (char *)va_arg(ap, char *); - if (sval) - { -#if PRINTF_ADVANCED_ENABLE - if (valid_precision_width) - { - vlen = precision_width; - } - else - { - vlen = strlen(sval); - } -#else - vlen = strlen(sval); -#endif /* PRINTF_ADVANCED_ENABLE */ -#if PRINTF_ADVANCED_ENABLE - if (!(flags_used & kPRINTF_Minus)) -#endif /* PRINTF_ADVANCED_ENABLE */ - { - cb(buf, &count, ' ', field_width - vlen); - } - -#if PRINTF_ADVANCED_ENABLE - if (valid_precision_width) - { - while ((*sval) && (vlen > 0)) - { - cb(buf, &count, *sval++, 1); - vlen--; - } - /* In case that vlen sval is shorter than vlen */ - vlen = precision_width - vlen; - } - else - { -#endif /* PRINTF_ADVANCED_ENABLE */ - while (*sval) - { - cb(buf, &count, *sval++, 1); - } -#if PRINTF_ADVANCED_ENABLE - } -#endif /* PRINTF_ADVANCED_ENABLE */ - -#if PRINTF_ADVANCED_ENABLE - if (flags_used & kPRINTF_Minus) - { - cb(buf, &count, ' ', field_width - vlen); - } -#endif /* PRINTF_ADVANCED_ENABLE */ - } - } - else - { - cb(buf, &count, c, 1); - } - } - } - - return count; -} - -/*! - * brief Converts an input line of ASCII characters based upon a provided - * string format. - * - * param[in] line_ptr The input line of ASCII data. - * param[in] format Format first points to the format string. - * param[in] args_ptr The list of parameters. - * - * return Number of input items converted and assigned. - * retval IO_EOF When line_ptr is empty string "". - */ -int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) -{ - uint8_t base; - int8_t neg; - /* Identifier for the format string. */ - char *c = format; - char temp; - char *buf; - /* Flag telling the conversion specification. */ - uint32_t flag = 0; - /* Filed width for the matching input streams. */ - uint32_t field_width; - /* How many arguments are assigned except the suppress. */ - uint32_t nassigned = 0; - /* How many characters are read from the input streams. */ - uint32_t n_decode = 0; - - int32_t val; - - const char *s; - /* Identifier for the input string. */ - const char *p = line_ptr; - -#if SCANF_FLOAT_ENABLE - double fnum = 0.0; -#endif /* SCANF_FLOAT_ENABLE */ - /* Return EOF error before any conversion. */ - if (*p == '\0') - { - return -1; - } - - /* Decode directives. */ - while ((*c) && (*p)) - { - /* Ignore all white-spaces in the format strings. */ - if (ScanIgnoreWhiteSpace((const char **)&c)) - { - n_decode += ScanIgnoreWhiteSpace(&p); - } - else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%'))) - { - /* Ordinary characters. */ - c++; - if (*p == *c) - { - n_decode++; - p++; - c++; - } - else - { - /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. - * However, it is deserted now. */ - break; - } - } - else - { - /* convernsion specification */ - c++; - /* Reset. */ - flag = 0; - field_width = 0; - base = 0; - - /* Loop to get full conversion specification. */ - while ((*c) && (!(flag & kSCANF_DestMask))) - { - switch (*c) - { -#if SCANF_ADVANCED_ENABLE - case '*': - if (flag & kSCANF_Suppress) - { - /* Match failure. */ - return nassigned; - } - flag |= kSCANF_Suppress; - c++; - break; - case 'h': - if (flag & kSCANF_LengthMask) - { - /* Match failure. */ - return nassigned; - } - - if (c[1] == 'h') - { - flag |= kSCANF_LengthChar; - c++; - } - else - { - flag |= kSCANF_LengthShortInt; - } - c++; - break; - case 'l': - if (flag & kSCANF_LengthMask) - { - /* Match failure. */ - return nassigned; - } - - if (c[1] == 'l') - { - flag |= kSCANF_LengthLongLongInt; - c++; - } - else - { - flag |= kSCANF_LengthLongInt; - } - c++; - break; -#endif /* SCANF_ADVANCED_ENABLE */ -#if SCANF_FLOAT_ENABLE - case 'L': - if (flag & kSCANF_LengthMask) - { - /* Match failure. */ - return nassigned; - } - flag |= kSCANF_LengthLongLongDouble; - c++; - break; -#endif /* SCANF_FLOAT_ENABLE */ - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - if (field_width) - { - /* Match failure. */ - return nassigned; - } - do - { - field_width = field_width * 10 + *c - '0'; - c++; - } while ((*c >= '0') && (*c <= '9')); - break; - case 'd': - base = 10; - flag |= kSCANF_TypeSinged; - flag |= kSCANF_DestInt; - c++; - break; - case 'u': - base = 10; - flag |= kSCANF_DestInt; - c++; - break; - case 'o': - base = 8; - flag |= kSCANF_DestInt; - c++; - break; - case 'x': - case 'X': - base = 16; - flag |= kSCANF_DestInt; - c++; - break; - case 'i': - base = 0; - flag |= kSCANF_DestInt; - c++; - break; -#if SCANF_FLOAT_ENABLE - case 'a': - case 'A': - case 'e': - case 'E': - case 'f': - case 'F': - case 'g': - case 'G': - flag |= kSCANF_DestFloat; - c++; - break; -#endif /* SCANF_FLOAT_ENABLE */ - case 'c': - flag |= kSCANF_DestChar; - if (!field_width) - { - field_width = 1; - } - c++; - break; - case 's': - flag |= kSCANF_DestString; - c++; - break; - default: - return nassigned; - } - } - - if (!(flag & kSCANF_DestMask)) - { - /* Format strings are exhausted. */ - return nassigned; - } - - if (!field_width) - { - /* Large than length of a line. */ - field_width = 99; - } - - /* Matching strings in input streams and assign to argument. */ - switch (flag & kSCANF_DestMask) - { - case kSCANF_DestChar: - s = (const char *)p; - buf = va_arg(args_ptr, char *); - while ((field_width--) && (*p)) - { - if (!(flag & kSCANF_Suppress)) - { - *buf++ = *p++; - } - else - { - p++; - } - n_decode++; - } - - if ((!(flag & kSCANF_Suppress)) && (s != p)) - { - nassigned++; - } - break; - case kSCANF_DestString: - n_decode += ScanIgnoreWhiteSpace(&p); - s = p; - buf = va_arg(args_ptr, char *); - while ((field_width--) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') && - (*p != '\r') && (*p != '\v') && (*p != '\f')) - { - if (flag & kSCANF_Suppress) - { - p++; - } - else - { - *buf++ = *p++; - } - n_decode++; - } - - if ((!(flag & kSCANF_Suppress)) && (s != p)) - { - /* Add NULL to end of string. */ - *buf = '\0'; - nassigned++; - } - break; - case kSCANF_DestInt: - n_decode += ScanIgnoreWhiteSpace(&p); - s = p; - val = 0; - if ((base == 0) || (base == 16)) - { - if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) - { - base = 16; - if (field_width >= 1) - { - p += 2; - n_decode += 2; - field_width -= 2; - } - } - } - - if (base == 0) - { - if (s[0] == '0') - { - base = 8; - } - else - { - base = 10; - } - } - - neg = 1; - switch (*p) - { - case '-': - neg = -1; - n_decode++; - p++; - field_width--; - break; - case '+': - neg = 1; - n_decode++; - p++; - field_width--; - break; - default: - break; - } - - while ((*p) && (field_width--)) - { - if ((*p <= '9') && (*p >= '0')) - { - temp = *p - '0'; - } - else if ((*p <= 'f') && (*p >= 'a')) - { - temp = *p - 'a' + 10; - } - else if ((*p <= 'F') && (*p >= 'A')) - { - temp = *p - 'A' + 10; - } - else - { - temp = base; - } - - if (temp >= base) - { - break; - } - else - { - val = base * val + temp; - } - p++; - n_decode++; - } - val *= neg; - if (!(flag & kSCANF_Suppress)) - { -#if SCANF_ADVANCED_ENABLE - switch (flag & kSCANF_LengthMask) - { - case kSCANF_LengthChar: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed char *) = (signed char)val; - } - else - { - *va_arg(args_ptr, unsigned char *) = (unsigned char)val; - } - break; - case kSCANF_LengthShortInt: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed short *) = (signed short)val; - } - else - { - *va_arg(args_ptr, unsigned short *) = (unsigned short)val; - } - break; - case kSCANF_LengthLongInt: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed long int *) = (signed long int)val; - } - else - { - *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val; - } - break; - case kSCANF_LengthLongLongInt: - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed long long int *) = (signed long long int)val; - } - else - { - *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val; - } - break; - default: - /* The default type is the type int. */ - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed int *) = (signed int)val; - } - else - { - *va_arg(args_ptr, unsigned int *) = (unsigned int)val; - } - break; - } -#else - /* The default type is the type int. */ - if (flag & kSCANF_TypeSinged) - { - *va_arg(args_ptr, signed int *) = (signed int)val; - } - else - { - *va_arg(args_ptr, unsigned int *) = (unsigned int)val; - } -#endif /* SCANF_ADVANCED_ENABLE */ - nassigned++; - } - break; -#if SCANF_FLOAT_ENABLE - case kSCANF_DestFloat: - n_decode += ScanIgnoreWhiteSpace(&p); - fnum = strtod(p, (char **)&s); - - if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL)) - { - break; - } - - n_decode += (int)(s) - (int)(p); - p = s; - if (!(flag & kSCANF_Suppress)) - { - if (flag & kSCANF_LengthLongLongDouble) - { - *va_arg(args_ptr, double *) = fnum; - } - else - { - *va_arg(args_ptr, float *) = (float)fnum; - } - nassigned++; - } - break; -#endif /* SCANF_FLOAT_ENABLE */ - default: - return nassigned; - } - } - } - return nassigned; -} diff --git a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_str.h b/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_str.h deleted file mode 100644 index 8255aec40..000000000 --- a/FreeRTOS/Demo/CORTEX_M0+_LPC51U68_LPCXpresso/utilities/fsl_str.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright 2017 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _FSL_STR_H -#define _FSL_STR_H - -#include "fsl_common.h" - -/*! - * @addtogroup debugconsole - * @{ - */ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*! - * @brief A function pointer which is used when format printf log. - */ -typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len); - -/*! - * @brief This function outputs its parameters according to a formatted string. - * - * @note I/O is performed by calling given function pointer using following - * (*func_ptr)(c); - * - * @param[in] fmt Format string for printf. - * @param[in] ap Arguments to printf. - * @param[in] buf pointer to the buffer - * @param cb print callbck function pointer - * - * @return Number of characters to be print - */ -int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb); - -/*! - * @brief Converts an input line of ASCII characters based upon a provided - * string format. - * - * @param[in] line_ptr The input line of ASCII data. - * @param[in] format Format first points to the format string. - * @param[in] args_ptr The list of parameters. - * - * @return Number of input items converted and assigned. - * @retval IO_EOF When line_ptr is empty string "". - */ -int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -#endif /* _FSL_STR_H */ diff --git a/FreeRTOS/Demo/Common/Minimal/QueueSet.c b/FreeRTOS/Demo/Common/Minimal/QueueSet.c index 0dc592823..ad34a50e5 100644 --- a/FreeRTOS/Demo/Common/Minimal/QueueSet.c +++ b/FreeRTOS/Demo/Common/Minimal/QueueSet.c @@ -51,6 +51,10 @@ /* Demo includes. */ #include "QueueSet.h" + +#if( configUSE_QUEUE_SETS == 1 ) /* Remove the tests if queue sets are not defined. */ + + /* The number of queues that are created and added to the queue set. */ #define queuesetNUM_QUEUES_IN_SET 3 @@ -149,6 +153,13 @@ static void prvChangeRelativePriorities( void ); */ static void prvTestQueueOverwriteWithQueueSet( void ); +/* + * Test the case where two queues within a set are written to with + * xQueueOverwrite(). + */ +static void prvTestQueueOverwriteOnTwoQueusInQueueSet( void ); +static void prvTestQueueOverwriteFromISROnTwoQueusInQueueSet( void ); + /* * Local pseudo random number seed and return functions. Used to avoid calls * to the standard library. @@ -616,13 +627,14 @@ const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1; /* Create a queue that has a length of one - a requirement in order to call xQueueOverwrite. This will get deleted again when this test completes. */ xQueueHandle = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) ); + configASSERT( xQueueHandle ); if( xQueueHandle != NULL ) { xQueueAddToSet( xQueueHandle, xQueueSet ); /* Add an item to the queue then ensure the queue set correctly - indicates that one item is available, and that that item is indeed the + indicates that one item is available, and that item is indeed the queue written to. */ xQueueOverwrite( xQueueHandle, ( void * ) &ulValueToSend ); if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 ) @@ -661,7 +673,18 @@ const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1; xQueueReceive( xQueueHandle, &ulValueReceived, queuesetDONT_BLOCK ); if( ulValueReceived != ulValueToSend ) { - /* Unexpected value recevied from the queue. */ + /* Unexpected value received from the queue. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* Should be anything in the queue set now. */ + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 ) + { + xQueueSetTasksStatus = pdFAIL; + } + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + if( xReceivedHandle != NULL ) + { xQueueSetTasksStatus = pdFAIL; } @@ -672,6 +695,316 @@ const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1; } /*-----------------------------------------------------------*/ +static void prvTestQueueOverwriteOnTwoQueusInQueueSet( void ) +{ +uint32_t ulValueToSend1 = 1, ulValueToSend2 = 2UL, ulValueReceived = 0; +QueueHandle_t xQueueHandle1 = NULL, xQueueHandle2 = NULL, xReceivedHandle = NULL; +const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1; + + /* Create two queues that have a length of one - a requirement in order to call + xQueueOverwrite. These will get deleted again when this test completes. */ + xQueueHandle1 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) ); + configASSERT( xQueueHandle1 ); + xQueueHandle2 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) ); + configASSERT( xQueueHandle2 ); + + if( ( xQueueHandle1 != NULL ) && ( xQueueHandle2 != NULL ) ) + { + /* Add both queues to the queue set. */ + xQueueAddToSet( xQueueHandle1, xQueueSet ); + xQueueAddToSet( xQueueHandle2, xQueueSet ); + + /* Add an item using the first queue. */ + xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend1 ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 ) + { + /* Expected one item in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK ); + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle so expected xQueueHandle to be the handle + held in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + + /* Next add an item to the second queue. */ + xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend2 ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* The head of the queue set should not have changed though. */ + xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK ); + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle so expected xQueueHandle to be the handle + held in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + + + + /* Now overwrite the value in the queue and ensure the queue set state + doesn't change as the number of items in the queues within the set have + not changed. NOTE: after this queue 1 should hold ulValueToSend2 and queue + 2 should hold the value ulValueToSend1. */ + xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend2 ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend1 ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + + /* Repeat the above to ensure the queue set state doesn't change. */ + xQueueOverwrite( xQueueHandle1, ( void * ) &ulValueToSend2 ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + xQueueOverwrite( xQueueHandle2, ( void * ) &ulValueToSend1 ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + + /* Now when reading from the queue set we expect the handle to the first + queue to be received first, and for that queue to hold ulValueToSend2 as the + originally written value was overwritten. Likewise the second handle received + from the set should be that of the second queue, and that queue should hold + ulValueToSend1 as the originally written value was overwritten. */ + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle1 first so expected that handle to be read from + the set first. */ + xQueueSetTasksStatus = pdFAIL; + } + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 ) + { + /* One value was read from the set, so now only expect a single value + in the set. */ + xQueueSetTasksStatus = pdFAIL; + } + xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK ); + if( ulValueReceived != ulValueToSend2 ) + { + /* Unexpected value received from the queue. ulValueToSend1 was written + first, but then overwritten with ulValueToSend2; */ + xQueueSetTasksStatus = pdFAIL; + } + + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + if( xReceivedHandle != xQueueHandle2 ) + { + /* xQueueHandle1 has already been removed from the set so expect only + xQueueHandle2 to be left. */ + xQueueSetTasksStatus = pdFAIL; + } + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 ) + { + /* The last value was read from the set so don't expect any more. */ + xQueueSetTasksStatus = pdFAIL; + } + xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK ); + if( ulValueReceived != ulValueToSend1 ) + { + /* Unexpected value received from the queue. ulValueToSend2 was written + first, but then overwritten with ulValueToSend1. */ + xQueueSetTasksStatus = pdFAIL; + } + + + + + /* Should be anything in the queue set now. */ + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + if( xReceivedHandle != NULL ) + { + xQueueSetTasksStatus = pdFAIL; + } + + /* Clean up. */ + xQueueRemoveFromSet( xQueueHandle1, xQueueSet ); + xQueueRemoveFromSet( xQueueHandle2, xQueueSet ); + vQueueDelete( xQueueHandle1 ); + vQueueDelete( xQueueHandle2 ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTestQueueOverwriteFromISROnTwoQueusInQueueSet( void ) +{ +uint32_t ulValueToSend1 = 1, ulValueToSend2 = 2UL, ulValueReceived = 0; +QueueHandle_t xQueueHandle1 = NULL, xQueueHandle2 = NULL, xReceivedHandle = NULL; +const UBaseType_t xLengthOfOne = ( UBaseType_t ) 1; + + /* Create two queues that have a length of one - a requirement in order to call + xQueueOverwrite. These will get deleted again when this test completes. */ + xQueueHandle1 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) ); + configASSERT( xQueueHandle1 ); + xQueueHandle2 = xQueueCreate( xLengthOfOne, sizeof( uint32_t ) ); + configASSERT( xQueueHandle2 ); + + if( ( xQueueHandle1 != NULL ) && ( xQueueHandle2 != NULL ) ) + { + /* Add both queues to the queue set. */ + xQueueAddToSet( xQueueHandle1, xQueueSet ); + xQueueAddToSet( xQueueHandle2, xQueueSet ); + + /* Add an item using the first queue using the 'FromISR' version of the + overwrite function. */ + xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend1, NULL ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 ) + { + /* Expected one item in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK ); + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle so expected xQueueHandle to be the handle + held in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + + /* Next add an item to the second queue using the 'FromISR' version of the + overwrite function. */ + xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend2, NULL ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + /* The head of the queue set should not have changed though. */ + xQueuePeek( xQueueSet, &xReceivedHandle, queuesetDONT_BLOCK ); + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle so expected xQueueHandle to be the handle + held in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + + + + /* Now overwrite the value in the queue and ensure the queue set state + doesn't change as the number of items in the queues within the set have + not changed. NOTE: after this queue 1 should hold ulValueToSend2 and queue + 2 should hold the value ulValueToSend1. */ + xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend2, NULL ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend1, NULL ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + + /* Repeat the above to ensure the queue set state doesn't change. */ + xQueueOverwriteFromISR( xQueueHandle1, ( void * ) &ulValueToSend2, NULL ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + xQueueOverwriteFromISR( xQueueHandle2, ( void * ) &ulValueToSend1, NULL ); + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 2 ) + { + /* Still expected two items in the queue set. */ + xQueueSetTasksStatus = pdFAIL; + } + + + /* Now when reading from the queue set we expect the handle to the first + queue to be received first, and for that queue to hold ulValueToSend2 as the + originally written value was overwritten. Likewise the second handle received + from the set should be that of the second queue, and that queue should hold + ulValueToSend1 as the originally written value was overwritten. */ + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + if( xReceivedHandle != xQueueHandle1 ) + { + /* Wrote to xQueueHandle1 first so expected that handle to be read from + the set first. */ + xQueueSetTasksStatus = pdFAIL; + } + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 1 ) + { + /* One value was read from the set, so now only expect a single value + in the set. */ + xQueueSetTasksStatus = pdFAIL; + } + xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK ); + if( ulValueReceived != ulValueToSend2 ) + { + /* Unexpected value received from the queue. ulValueToSend1 was written + first, but then overwritten with ulValueToSend2; */ + xQueueSetTasksStatus = pdFAIL; + } + + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + if( xReceivedHandle != xQueueHandle2 ) + { + /* xQueueHandle1 has already been removed from the set so expect only + xQueueHandle2 to be left. */ + xQueueSetTasksStatus = pdFAIL; + } + if( uxQueueMessagesWaiting( xQueueSet ) != ( UBaseType_t ) 0 ) + { + /* The last value was read from the set so don't expect any more. */ + xQueueSetTasksStatus = pdFAIL; + } + xQueueReceive( xReceivedHandle, &ulValueReceived, queuesetDONT_BLOCK ); + if( ulValueReceived != ulValueToSend1 ) + { + /* Unexpected value received from the queue. ulValueToSend2 was written + first, but then overwritten with ulValueToSend1. */ + xQueueSetTasksStatus = pdFAIL; + } + + + + + /* Should be anything in the queue set now. */ + xReceivedHandle = xQueueSelectFromSet( xQueueSet, queuesetDONT_BLOCK ); + if( xReceivedHandle != NULL ) + { + xQueueSetTasksStatus = pdFAIL; + } + + /* Clean up. */ + xQueueRemoveFromSet( xQueueHandle1, xQueueSet ); + xQueueRemoveFromSet( xQueueHandle2, xQueueSet ); + vQueueDelete( xQueueHandle1 ); + vQueueDelete( xQueueHandle2 ); + } +} +/*-----------------------------------------------------------*/ + static void prvSetupTest( void ) { BaseType_t x; @@ -753,6 +1086,14 @@ uint32_t ulValueToSend = 0; be performed on queues that have a length of 1. */ prvTestQueueOverwriteWithQueueSet(); + /* Test the case where two queues within a set are written to with + xQueueOverwrite(). */ + prvTestQueueOverwriteOnTwoQueusInQueueSet(); + prvTestQueueOverwriteFromISROnTwoQueusInQueueSet(); + + /* In case any of the above have already indicated a failure. */ + configASSERT( xQueueSetTasksStatus != pdFAIL ); + /* Resume the task that writes to the queues. */ vTaskResume( xQueueSetSendingTask ); @@ -773,3 +1114,4 @@ static void prvSRand( size_t uxSeed ) uxNextRand = uxSeed; } +#endif /* ( configUSE_QUEUE_SETS == 1 ) */ diff --git a/FreeRTOS/Demo/Common/Minimal/QueueSetPolling.c b/FreeRTOS/Demo/Common/Minimal/QueueSetPolling.c index 7815d731a..e5e57d43c 100644 --- a/FreeRTOS/Demo/Common/Minimal/QueueSetPolling.c +++ b/FreeRTOS/Demo/Common/Minimal/QueueSetPolling.c @@ -51,6 +51,8 @@ /* Demo includes. */ #include "QueueSetPolling.h" +#if( configUSE_QUEUE_SETS == 1 ) /* Remove tests if queue sets are not defined. */ + /* The length of each created queue. */ #define setpollQUEUE_LENGTH 10 @@ -177,3 +179,4 @@ static uint32_t ulLastCycleCounter = 0; /*-----------------------------------------------------------*/ +#endif /* ( configUSE_QUEUE_SETS == 1 ) */