From: Patrice Chotard <patrice.chotard@st.com>
Date: Tue, 18 Jul 2017 07:29:10 +0000 (+0200)
Subject: clk: stm32f7: remove clock_get()
X-Git-Tag: v2017.09-rc1~103
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=81d0128d2bec6aaa69d7f41c96a5a659075f79f7;p=u-boot

clk: stm32f7: remove clock_get()

All drivers which was using clock_get() are now using
clk_get_rate() from clock framework, now it's safe to
remove clock_get().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
---

diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index 12efee5d48..87aee6057b 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -57,11 +57,6 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
 	[5 ... 7] =	256 * 1024
 };
 
-enum clock {
-	CLOCK_AHB,
-	CLOCK_APB1,
-	CLOCK_APB2
-};
 #define STM32_BUS_MASK		GENMASK(31, 16)
 
 struct stm32_rcc_regs {
@@ -108,7 +103,6 @@ struct stm32_pwr_regs {
 };
 #define STM32_PWR		((struct stm32_pwr_regs *)PWR_BASE)
 
-unsigned long clock_get(enum clock clck);
 void stm32_flash_latency_cfg(int latency);
 
 #endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c
index 5bc650a7dd..255a583c95 100644
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f7.c
@@ -171,54 +171,6 @@ static int configure_clocks(struct udevice *dev)
 	return 0;
 }
 
-unsigned long clock_get(enum clock clck)
-{
-	u32 sysclk = 0;
-	u32 shift = 0;
-	/* Prescaler table lookups for clock computation */
-	u8 ahb_psc_table[16] = {
-		0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
-	};
-	u8 apb_psc_table[8] = {
-		0, 0, 0, 0, 1, 2, 3, 4
-	};
-
-	if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
-			RCC_CFGR_SWS_PLL) {
-		u16 pllm, plln, pllp;
-		pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
-		plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
-			>> RCC_PLLCFGR_PLLN_SHIFT);
-		pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
-			>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
-		sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
-	}
-
-	switch (clck) {
-	case CLOCK_AHB:
-		shift = ahb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
-			>> RCC_CFGR_HPRE_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	case CLOCK_APB1:
-		shift = apb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
-			>> RCC_CFGR_PPRE1_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	case CLOCK_APB2:
-		shift = apb_psc_table[(
-			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
-			>> RCC_CFGR_PPRE2_SHIFT)];
-		return sysclk >>= shift;
-		break;
-	default:
-		return 0;
-		break;
-	}
-}
-
 static unsigned long stm32_clk_get_rate(struct clk *clk)
 {
 	struct stm32_clk *priv = dev_get_priv(clk->dev);