From: Sricharan R Date: Thu, 30 May 2013 03:19:35 +0000 (+0000) Subject: ARM: DRA7xx: Correct SRAM END address X-Git-Tag: v2013.07-rc1~2^2~3^2~11 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=81ede187c3e4233c08ab30900e86f5e0ec2c4624;p=u-boot ARM: DRA7xx: Correct SRAM END address NON SECURE SRAM is 512KB in DRA7xx devices. So fixing it here. Signed-off-by: Sricharan R Signed-off-by: Lokesh Vutla --- diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 43a629f353..06171d017b 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -169,13 +169,14 @@ struct s32ktimer { #define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */ -/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ +#ifdef CONFIG_DRA7XX +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ +#else #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ +#endif + /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000