From: rtel Date: Sun, 30 Dec 2018 23:11:40 +0000 (+0000) Subject: Update RSIC-V port layer after testing saving and receiving of chip specific registers. X-Git-Tag: V10.2.0~25 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=829657a8119bfebf67c1f8a845652dcd5ca7262c;p=freertos Update RSIC-V port layer after testing saving and receiving of chip specific registers. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2617 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h index 2448d8a78..5121abab1 100644 --- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h +++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h @@ -75,7 +75,7 @@ /* Save additional registers found on the Pulpino. */ .macro portasmSAVE_ADDITIONAL_REGISTERS - addi sp, sp, -portasmADDITIONAL_CONTEXT_SIZE /* Make room for the additional registers. */ + addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */ csrr t0, lpstart0 /* Load additional registers into accessable temporary registers. */ csrr t1, lpend0 csrr t2, lpcount0 @@ -104,7 +104,7 @@ csrw lpstart1, t3 csrw lpend1, t4 csrw lpcount1, t5 - addi sp, sp, -portasmADDITIONAL_CONTEXT_SIZE /* Remove space added for additional registers. */ + addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */ .endm #endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */ diff --git a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S index 12cc49b4d..5d9e5f307 100644 --- a/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S +++ b/FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S @@ -363,22 +363,13 @@ xPortStartFirstTask: * x6 * x5 * portTASK_RETURN_ADDRESS + * [chip specific registers go here] * pxCode */ .align 8 .func pxPortInitialiseStack: - addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */ - -chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */ - beq t0, x0, standard_stack_frame /* No more chip specific registers to save. */ - addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */ - sw x0, 0(a0) /* Give the chip specific register an initial value of zero. */ - addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */ - j chip_specific_stack_frame /* Until no more chip specific registers. */ - -standard_stack_frame: /* Now create the stack frame for the standard registers. */ csrr t0, mstatus /* Obtain current mstatus value. */ addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */ slli t1, t1, 4 @@ -390,6 +381,14 @@ standard_stack_frame: /* Now create the stack frame for the standard registe sw a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */ addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */ sw x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */ + addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */ +chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */ + beq t0, x0, 1f /* No more chip specific registers to save. */ + addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */ + sw x0, 0(a0) /* Give the chip specific register an initial value of zero. */ + addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */ + j chip_specific_stack_frame /* Until no more chip specific registers. */ +1: addi a0, a0, -portWORD_SIZE sw a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */ ret