From: Spencer Oliver <spen@spen-soft.co.uk>
Date: Mon, 5 Aug 2013 16:46:09 +0000 (+0100)
Subject: armv7m: use consistent arm.cpsr member
X-Git-Tag: v0.8.0-rc1~297
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=83f1c6f9169bdae920ce18108590d8dffad99126;p=openocd

armv7m: use consistent arm.cpsr member

We already set cpsr in armv7m_build_reg_cache, so lets use it for all other
accesses to this field.

Change-Id: I19b3b21ecf1571bbea12e1be664845e6544f6fa1
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1539
Tested-by: jenkins
---

diff --git a/src/target/arm.h b/src/target/arm.h
index e2d26461..c7c8dc0f 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -97,7 +97,7 @@ struct arm {
 	/** Handle to the PC; valid in all core modes. */
 	struct reg *pc;
 
-	/** Handle to the CPSR; valid in all core modes. */
+	/** Handle to the CPSR/xPSR; valid in all core modes. */
 	struct reg *cpsr;
 
 	/** Handle to the SPSR; valid only in core modes with an SPSR. */
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 1d08c95f..fbe635bd 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -430,7 +430,7 @@ static int cortex_m3_debug_entry(struct target *target)
 			arm->read_core_reg(target, r, i, ARM_MODE_ANY);
 	}
 
-	r = arm->core_cache->reg_list + ARMV7M_xPSR;
+	r = arm->cpsr;
 	xPSR = buf_get_u32(r->value, 0, 32);
 
 #ifdef ARMV7_GDB_HACKS
@@ -732,7 +732,7 @@ static int cortex_m3_resume(struct target *target, int current,
 		r->valid = true;
 
 		/* Make sure we are in Thumb mode */
-		r = armv7m->arm.core_cache->reg_list + ARMV7M_xPSR;
+		r = armv7m->arm.cpsr;
 		buf_set_u32(r->value, 24, 1, 1);
 		r->dirty = true;
 		r->valid = true;
diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 41fe45e6..078ac647 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -427,7 +427,7 @@ static int adapter_debug_entry(struct target *target)
 	/* make sure we clear the vector catch bit */
 	adapter->layout->api->write_debug_reg(adapter->fd, DCB_DEMCR, TRCENA);
 
-	r = arm->core_cache->reg_list + ARMV7M_xPSR;
+	r = arm->cpsr;
 	xPSR = buf_get_u32(r->value, 0, 32);
 
 	/* Are we in an exception handler */