From: richardbarry Date: Fri, 30 Aug 2013 18:05:16 +0000 (+0000) Subject: Continue work on XCM1200 Keil demo. X-Git-Tag: V7.5.3~57 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8586dec7b57c034f6a46bdfefc6ed2ce8504bb80;p=freertos Continue work on XCM1200 Keil demo. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2009 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/FreeRTOSConfig.h index 9078de778..0ee780c82 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/FreeRTOSConfig.h @@ -83,19 +83,19 @@ extern uint32_t SystemCoreClock; #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 1 +#define configUSE_TICK_HOOK 0 #define configCPU_CLOCK_HZ ( SystemCoreClock ) #define configTICK_RATE_HZ ( ( portTickType ) 1000 ) #define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 60 ) -#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 6500 ) ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 3000 ) ) #define configMAX_TASK_NAME_LEN ( 5 ) #define configUSE_TRACE_FACILITY 1 #define configUSE_16_BIT_TICKS 0 #define configIDLE_SHOULD_YIELD 1 #define configUSE_MUTEXES 1 #define configQUEUE_REGISTRY_SIZE 8 -#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_FOR_STACK_OVERFLOW 1 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_MALLOC_FAILED_HOOK 1 #define configUSE_APPLICATION_TASK_TAG 0 diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/ParTest.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/ParTest.c deleted file mode 100644 index fbad4ad47..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/ParTest.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. - - VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. - - *************************************************************************** - * * - * FreeRTOS provides completely free yet professionally developed, * - * robust, strictly quality controlled, supported, and cross * - * platform software that has become a de facto standard. * - * * - * Help yourself get started quickly and support the FreeRTOS * - * project by purchasing a FreeRTOS tutorial book, reference * - * manual, or both from: http://www.FreeRTOS.org/Documentation * - * * - * Thank you! * - * * - *************************************************************************** - - This file is part of the FreeRTOS distribution. - - FreeRTOS is free software; you can redistribute it and/or modify it under - the terms of the GNU General Public License (version 2) as published by the - Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. - - >>! NOTE: The modification to the GPL is included to allow you to distribute - >>! a combined work that includes FreeRTOS without being obliged to provide - >>! the source code for proprietary components outside of the FreeRTOS - >>! kernel. - - FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY - WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS - FOR A PARTICULAR PURPOSE. Full license text is available from the following - link: http://www.freertos.org/a00114.html - - 1 tab == 4 spaces! - - *************************************************************************** - * * - * Having a problem? Start by reading the FAQ "My application does * - * not run, what could be wrong?" * - * * - * http://www.FreeRTOS.org/FAQHelp.html * - * * - *************************************************************************** - - http://www.FreeRTOS.org - Documentation, books, training, latest versions, - license and Real Time Engineers Ltd. contact details. - - http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, - including FreeRTOS+Trace - an indispensable productivity tool, a DOS - compatible FAT file system, and our tiny thread aware UDP/IP stack. - - http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High - Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS - licenses offer ticketed support, indemnification and middleware. - - http://www.SafeRTOS.com - High Integrity Systems also provide a safety - engineered and independently SIL3 certified version for use in safety and - mission critical applications that require provable dependability. - - 1 tab == 4 spaces! -*/ - -/*----------------------------------------------------------- - * Simple GPIO (parallel port) IO routines. - *-----------------------------------------------------------*/ - -/* Kernel includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Hardware includes. */ -#include - -/* Standard demo include. */ -#include "partest.h" - -/* The port bits on which LEDs are connected. */ -static const unsigned long ulLEDBits[] = -{ - 1UL << 0, /* P0.0 */ - 1UL << 2, /* P0.2 */ - 1UL << 5, /* P0.5 */ - 1UL << 6, /* P0.6 */ - 1UL << 7 /* P0.7 */ -}; - -#define partstNUM_LEDS ( sizeof( ulLEDBits ) / sizeof( unsigned long ) ) - -/* Shift the LED bit into the correct position within the POW register to -perform the desired operation. */ -#define partstON_SHIFT ( 16UL ) -#define partstOFF_SHIFT ( 0UL ) - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ - /* Configure relevant port P0 to push pull output to drive LEDs. */ - - /* P0.0 */ - PORT0->IOCR0 &= ~( ( 0xFFUL << 0 ) ); - PORT0->IOCR0 |= ( 0x80UL << 0 ); - - /* P0.2 */ - PORT0->IOCR0 &= ~( ( 0xFFUL << 16 ) ); - PORT0->IOCR0 |= ( 0x80UL << 16 ); - - /* P0.5 */ - PORT0->IOCR4 &= ~( ( 0xFFUL << 8 ) ); - PORT0->IOCR4 |= ( 0x80UL << 8 ); - - /* P0.6 */ - PORT0->IOCR4 &= ~( ( 0xFFUL << 16 ) ); - PORT0->IOCR4 |= ( 0x80UL << 16 ); - - /* P0.7 */ - PORT0->IOCR4 &= ~( ( 0xFFUL << 24 ) ); - PORT0->IOCR4 |= ( 0x80UL << 24 ); -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( unsigned long ulLED, signed portBASE_TYPE xValue ) -{ - if( ulLED < partstNUM_LEDS ) - { - if( xValue == pdTRUE ) - { - /* Turn the LED on. */ - PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT ); - } - else - { - /* Turn the LED off. */ - PORT0->OMR = ( ulLEDBits[ ulLED ] << partstOFF_SHIFT ); - } - } -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned long ulLED ) -{ - if( ulLED < partstNUM_LEDS ) - { - /* Setting both the ON and OFF bits simultaneously results in the bit - being toggled. */ - PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT ) | ( ulLEDBits[ ulLED ] << partstOFF_SHIFT ); - } -} -/*-----------------------------------------------------------*/ - diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/ParTest_XMC1200.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/ParTest_XMC1200.c new file mode 100644 index 000000000..aa2ba14b7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/ParTest_XMC1200.c @@ -0,0 +1,152 @@ +/* + FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd. + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to distribute + >>! a combined work that includes FreeRTOS without being obliged to provide + >>! the source code for proprietary components outside of the FreeRTOS + >>! kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/*----------------------------------------------------------- + * Simple GPIO (parallel port) IO routines. + *-----------------------------------------------------------*/ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Hardware includes. */ +#include + +/* Standard demo include. */ +#include "partest.h" + +/* The port bits on which LEDs are connected. */ +static const unsigned long ulLEDBits[] = +{ + 1UL << 0, /* P0.0 */ + 1UL << 2, /* P0.2 */ + 1UL << 5, /* P0.5 */ + 1UL << 6, /* P0.6 */ + 1UL << 7 /* P0.7 */ +}; + +#define partstNUM_LEDS ( sizeof( ulLEDBits ) / sizeof( unsigned long ) ) + +/* Shift the LED bit into the correct position within the POW register to +perform the desired operation. */ +#define partstON_SHIFT ( 16UL ) +#define partstOFF_SHIFT ( 0UL ) + +/*-----------------------------------------------------------*/ + +void vParTestInitialise( void ) +{ + /* Configure relevant port P0 to push pull output to drive LEDs. */ + + /* P0.0 */ + PORT0->IOCR0 &= ~( ( 0xFFUL << 0 ) ); + PORT0->IOCR0 |= ( 0x80UL << 0 ); + + /* P0.2 */ + PORT0->IOCR0 &= ~( ( 0xFFUL << 16 ) ); + PORT0->IOCR0 |= ( 0x80UL << 16 ); + + /* P0.5 */ + PORT0->IOCR4 &= ~( ( 0xFFUL << 8 ) ); + PORT0->IOCR4 |= ( 0x80UL << 8 ); + + /* P0.6 */ + PORT0->IOCR4 &= ~( ( 0xFFUL << 16 ) ); + PORT0->IOCR4 |= ( 0x80UL << 16 ); + + /* P0.7 */ + PORT0->IOCR4 &= ~( ( 0xFFUL << 24 ) ); + PORT0->IOCR4 |= ( 0x80UL << 24 ); +} +/*-----------------------------------------------------------*/ + +void vParTestSetLED( unsigned long ulLED, signed portBASE_TYPE xValue ) +{ + if( ulLED < partstNUM_LEDS ) + { + if( xValue == pdTRUE ) + { + /* Turn the LED on. */ + PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT ); + } + else + { + /* Turn the LED off. */ + PORT0->OMR = ( ulLEDBits[ ulLED ] << partstOFF_SHIFT ); + } + } +} +/*-----------------------------------------------------------*/ + +void vParTestToggleLED( unsigned long ulLED ) +{ + if( ulLED < partstNUM_LEDS ) + { + /* Setting both the ON and OFF bits simultaneously results in the bit + being toggled. */ + PORT0->OMR = ( ulLEDBits[ ulLED ] << partstON_SHIFT ) | ( ulLEDBits[ ulLED ] << partstOFF_SHIFT ); + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvopt b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvopt index 465ee288d..7669131c2 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvopt +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvopt @@ -73,7 +73,7 @@ 1 0 - 1 + 0 255 @@ -158,24 +158,202 @@ UL2CM3(-O207 -S0 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0XMC1300_200 -FL032000 -FS010001000 - - + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + XMC1200 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + + 0 + Data Sheet + DATASHTS\Infineon\XMC1200\xmc1100_ds.pdf + + + 1 + User Manual + DATASHTS\Infineon\XMC1200\xmc1100_ds.pdf + + + 2 + Technical Reference Manual + datashts\arm\cortex_m0\r0p0\DDI0432C_CORTEX_M0_R0P0_TRM.PDF + + + 3 + Generic User Guide + datashts\arm\cortex_m0\r0p0\DUI0497A_CORTEX_M0_R0P0_GENERIC_UG.PDF + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 7 + + + + + + + + + + + Segger\JL2CM3.dll + + + 0 - 0 - 132 - 1 -
0
- 0 - 0 - 0 - 0 - 0 - 0 - C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil\startup_XMC1300.s - - - - + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + DLGUARM + + + + 0 + JL2CM3 + -U591005602 -O207 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1200_200 -FS010001000 -FL032000 + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + UL2CM3 + -O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1200_200 -FS010001000 -FL032000) + + + + + + 0 + 1 + uxCriticalNesting + + 0 @@ -219,16 +397,16 @@ 1 1 - 2 + 1 0 0 0 0 - 130 - 132 + 1 + 1 0 - .\startup_XMC1300.s - startup_XMC1300.s + .\System_Keil\system_XMC1300.c + system_XMC1300.c 0 0 @@ -240,11 +418,27 @@ 0 0 0 - 0 - 0 + 1 + 1 0 - .\system_XMC1300.c - system_XMC1300.c + .\System_Keil\system_XMC1100.c + system_XMC1100.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + .\System_Keil\system_XMC1200.c + system_XMC1200.c 0 0 @@ -258,14 +452,14 @@ 0 2 - 3 + 4 1 0 0 0 0 - 0 - 0 + 346 + 369 0 ..\..\Source\timers.c timers.c @@ -274,14 +468,14 @@ 2 - 4 + 5 1 0 0 0 0 - 0 - 0 + 150 + 198 0 ..\..\Source\list.c list.c @@ -290,14 +484,14 @@ 2 - 5 + 6 1 0 0 0 0 - 1242 - 1259 + 0 + 0 0 ..\..\Source\queue.c queue.c @@ -306,14 +500,14 @@ 2 - 6 + 7 1 0 0 0 0 - 0 - 0 + 1824 + 1847 0 ..\..\Source\tasks.c tasks.c @@ -322,14 +516,14 @@ 2 - 7 + 8 1 0 0 - 9 + 0 0 - 265 - 279 + 291 + 292 0 ..\..\Source\portable\RVDS\ARM_CM0\port.c port.c @@ -338,7 +532,7 @@ 2 - 8 + 9 1 0 0 @@ -360,32 +554,16 @@ 0 0 0 - - 3 - 9 - 1 - 0 - 0 - 9 - 0 - 115 - 134 - 0 - .\ParTest.c - ParTest.c - 0 - 0 - 3 10 1 0 0 - 42 + 0 0 - 73 - 94 + 112 + 122 0 .\main.c main.c @@ -398,10 +576,10 @@ 1 0 0 - 44 + 0 0 - 203 - 128 + 186 + 194 0 .\main-blinky.c main-blinky.c @@ -414,10 +592,10 @@ 5 0 0 - 0 + 41 0 - 0 - 0 + 74 + 98 0 .\FreeRTOSConfig.h FreeRTOSConfig.h @@ -430,10 +608,10 @@ 1 0 0 - 36 + 0 0 - 293 - 311 + 0 + 0 0 .\main-full.c main-full.c @@ -446,16 +624,32 @@ 2 0 0 - 5 + 14 0 - 142 - 143 + 0 + 0 0 .\RegTest.s RegTest.s 0 0 + + 3 + 15 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + .\ParTest_XMC1200.c + ParTest_XMC1200.c + 0 + 0 + @@ -466,7 +660,7 @@ 0 4 - 15 + 16 1 0 0 @@ -482,7 +676,7 @@ 4 - 16 + 17 1 0 0 @@ -498,7 +692,7 @@ 4 - 17 + 18 1 0 0 @@ -514,7 +708,7 @@ 4 - 18 + 19 1 0 0 diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvproj b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvproj index 3fea34439..0be45b573 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvproj +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/RTOSDemo.uvproj @@ -393,14 +393,19 @@ System - startup_XMC1300.s - 2 - .\startup_XMC1300.s + system_XMC1300.c + 1 + .\System_Keil\system_XMC1300.c - system_XMC1300.c + system_XMC1100.c 1 - .\system_XMC1300.c + .\System_Keil\system_XMC1100.c + + + system_XMC1200.c + 1 + .\System_Keil\system_XMC1200.c @@ -443,10 +448,625 @@ Demo App Source - ParTest.c + main.c + 1 + .\main.c + + + main-blinky.c 1 - .\ParTest.c + .\main-blinky.c + + FreeRTOSConfig.h + 5 + .\FreeRTOSConfig.h + + + main-full.c + 1 + .\main-full.c + + + RegTest.s + 2 + .\RegTest.s + + + ParTest_XMC1200.c + 1 + .\ParTest_XMC1200.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + + + Common Demo Tasks + + + dynamic.c + 1 + ..\Common\Minimal\dynamic.c + + + recmutex.c + 1 + ..\Common\Minimal\recmutex.c + + + blocktim.c + 1 + ..\Common\Minimal\blocktim.c + + + countsem.c + 1 + ..\Common\Minimal\countsem.c + + + + + + + XMC1200 + 0x4 + ARM-ADS + + + XMC1200-200 + Infineon + IRAM(0x20000000-0x20003FFF) IROM(0x10001000-0x10032FFF) CLOCK(12000000) CPUTYPE("Cortex-M0") + + "STARTUP\Infineon\XMC1200\startup_XMC1200.s" ("Infineon XMC1200 Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0XMC1200_200 -FS010001000 -FL032000) + 6777 + XMC1200.h + + + + + + + + + + SFD\Infineon\XMC1200\xmc1200.SFR + 0 + + + + Infineon\XMC1200\ + Infineon\XMC1200\ + + 0 + 0 + 0 + 0 + 1 + + .\Output\ + RTOSDemo + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 7 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x10001000 + 0x32000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10001000 + 0x32000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + ..\CORTEX_M0_Infineon_Boot_Kits_IAR_Keil;..\..\Source\include;..\..\Source\portable\RVDS\ARM_CM0;..\Common\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x10001000 + 0x20000000 + .\Output\RTOSDemo.sct + + + + + + + + + + + System + + + system_XMC1300.c + 1 + .\System_Keil\system_XMC1300.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + system_XMC1100.c + 1 + .\System_Keil\system_XMC1100.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + system_XMC1200.c + 1 + .\System_Keil\system_XMC1200.c + + + + + FreeRTOS source + + + timers.c + 1 + ..\..\Source\timers.c + + + list.c + 1 + ..\..\Source\list.c + + + queue.c + 1 + ..\..\Source\queue.c + + + tasks.c + 1 + ..\..\Source\tasks.c + + + port.c + 1 + ..\..\Source\portable\RVDS\ARM_CM0\port.c + + + heap_4.c + 1 + ..\..\Source\portable\MemMang\heap_4.c + + + + + Demo App Source + main.c 1 @@ -472,6 +1092,51 @@ 2 .\RegTest.s + + ParTest_XMC1200.c + 1 + .\ParTest_XMC1200.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/startup_XMC1300.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/startup_XMC1300.s new file mode 100644 index 000000000..24c7cbab9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/startup_XMC1300.s @@ -0,0 +1,397 @@ +;*****************************************************************************/ +; * @file startup_XMC1300.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Infineon XMC1300 Device Series +; * @version V1.00 +; * @date 21. Jan. 2013 +; * +; * @note +; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + + +;* <<< Use Configuration Wizard in Context Menu >>> + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + +; Clock system handling by SSW +; CLK_VAL1 Configuration +; FDIV Fractional Divider Selection +; IDIV Divider Selection +; <0=> Divider is bypassed +; <1=> MCLK = 32 MHz +; <2=> MCLK = 16 MHz +; <3=> MCLK = 10.67 MHz +; <4=> MCLK = 8 MHz +; <254=> MCLK = 126 kHz +; <255=> MCLK = 125.5 kHz +; PCLKSEL PCLK Clock Select +; <0=> PCLK = MCLK +; <1=> PCLK = 2 x MCLK +; RTCCLKSEL RTC Clock Select +; <0=> 32.768kHz standby clock +; <1=> 32.768kHz external clock from ERU0.IOUT0 +; <2=> 32.768kHz external clock from ACMP0.OUT +; <3=> 32.768kHz external clock from ACMP1.OUT +; <4=> 32.768kHz external clock from ACMP2.OUT +; <5=> Reserved +; <6=> Reserved +; <7=> Reserved +; do not move CLK_VAL1 to SCU_CLKCR[0..19] +; +CLK_VAL1_Val EQU 0x80000000 ; 0xF0000000 + +; CLK_VAL2 Configuration +; disable VADC and SHS Gating +; disable CCU80 Gating +; disable CCU40 Gating +; disable USIC0 Gating +; disable BCCU0 Gating +; disable LEDTS0 Gating +; disable LEDTS1 Gating +; disable POSIF0 Gating +; disable MATH Gating +; disable WDT Gating +; disable RTC Gating +; do not move CLK_VAL2 to SCU_CGATCLR0[0..10] +; +CLK_VAL2_Val EQU 0x80000000 ; 0xF0000000 +; + + PRESERVE8 + THUMB + +;* ================== START OF VECTOR TABLE DEFINITION ====================== */ +;* Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + + + +__Vectors + DCD __initial_sp ;* Top of Stack + DCD Reset_Handler ;* Reset Handler + DCD 0 ;* Not used + DCD 0 ;* Not Used + DCD CLK_VAL1_Val ;* CLK_VAL1 + DCD CLK_VAL2_Val ;* CLK_VAL2 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +;* ================== END OF VECTOR TABLE DEFINITION ======================== */ + + +;* ================== START OF VECTOR ROUTINES ============================== */ + AREA |.text|, CODE, READONLY + +;* Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + + ;* C routines are likely to be called. Setup the stack now + LDR R0, =__initial_sp + MOV SP, R0 + + ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself" + ; The real veneers will be copied later from the scatter loader before reaching main. + ; This init code should handle an exception before the real veneers are copied. +SRAM_BASE EQU 0x20000000 +VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B . + + LDR R1, =SRAM_BASE + LDR R2, =VENEER_INIT_CODE + MOVS R0, #48 ; Veneer 0..47 +Init_Veneers + STR R2, [R1] + ADDS R1, #4 + SUBS R0, R0, #1 + BNE Init_Veneers + + + LDR R0, =SystemInit + BLX R0 + + + ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is + ; weakly defined here though for a potential override. + + LDR R0, = SystemInit_DAVE3 + BLX R0 + + + LDR R0, =__main + BX R0 + + + ALIGN + ENDP + +;* ========================================================================== */ + + + +;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */ +;* Default exception Handlers - Users may override this default functionality + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ + + +;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ +;* IRQ Handlers + +Default_Handler PROC + EXPORT SCU_0_IRQHandler [WEAK] + EXPORT SCU_1_IRQHandler [WEAK] + EXPORT SCU_2_IRQHandler [WEAK] + EXPORT ERU0_0_IRQHandler [WEAK] + EXPORT ERU0_1_IRQHandler [WEAK] + EXPORT ERU0_2_IRQHandler [WEAK] + EXPORT ERU0_3_IRQHandler [WEAK] + EXPORT MATH0_0_IRQHandler [WEAK] + EXPORT USIC0_0_IRQHandler [WEAK] + EXPORT USIC0_1_IRQHandler [WEAK] + EXPORT USIC0_2_IRQHandler [WEAK] + EXPORT USIC0_3_IRQHandler [WEAK] + EXPORT USIC0_4_IRQHandler [WEAK] + EXPORT USIC0_5_IRQHandler [WEAK] + EXPORT VADC0_C0_0_IRQHandler [WEAK] + EXPORT VADC0_C0_1_IRQHandler [WEAK] + EXPORT VADC0_G0_0_IRQHandler [WEAK] + EXPORT VADC0_G0_1_IRQHandler [WEAK] + EXPORT VADC0_G1_0_IRQHandler [WEAK] + EXPORT VADC0_G1_1_IRQHandler [WEAK] + EXPORT CCU40_0_IRQHandler [WEAK] + EXPORT CCU40_1_IRQHandler [WEAK] + EXPORT CCU40_2_IRQHandler [WEAK] + EXPORT CCU40_3_IRQHandler [WEAK] + EXPORT CCU80_0_IRQHandler [WEAK] + EXPORT CCU80_1_IRQHandler [WEAK] + EXPORT POSIF0_0_IRQHandler [WEAK] + EXPORT POSIF0_1_IRQHandler [WEAK] + EXPORT LEDTS0_0_IRQHandler [WEAK] + EXPORT LEDTS1_0_IRQHandler [WEAK] + EXPORT BCCU0_0_IRQHandler [WEAK] + +SCU_0_IRQHandler +SCU_1_IRQHandler +SCU_2_IRQHandler +ERU0_0_IRQHandler +ERU0_1_IRQHandler +ERU0_2_IRQHandler +ERU0_3_IRQHandler +MATH0_0_IRQHandler +USIC0_0_IRQHandler +USIC0_1_IRQHandler +USIC0_2_IRQHandler +USIC0_3_IRQHandler +USIC0_4_IRQHandler +USIC0_5_IRQHandler +VADC0_C0_0_IRQHandler +VADC0_C0_1_IRQHandler +VADC0_G0_0_IRQHandler +VADC0_G0_1_IRQHandler +VADC0_G1_0_IRQHandler +VADC0_G1_1_IRQHandler +CCU40_0_IRQHandler +CCU40_1_IRQHandler +CCU40_2_IRQHandler +CCU40_3_IRQHandler +CCU80_0_IRQHandler +CCU80_1_IRQHandler +POSIF0_0_IRQHandler +POSIF0_1_IRQHandler +LEDTS0_0_IRQHandler +LEDTS1_0_IRQHandler +BCCU0_0_IRQHandler + + B . + + ENDP + + ALIGN + +;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ + +;* Definition of the default weak SystemInit_DAVE3 function. +;* This function will be called by the CMSIS SystemInit function. +;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3 +;* which will overule this weak definition +SystemInit_DAVE3 PROC + EXPORT SystemInit_DAVE3 [WEAK] + NOP + BX LR + ENDP + +;* Definition of the default weak DAVE3 function for clock App usage. +;* AllowClkInitByStartup Handler */ +AllowClkInitByStartup PROC + EXPORT AllowClkInitByStartup [WEAK] + MOVS R0,#1 + BX LR + ENDP + + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + +;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */ +; Veneers are located to fix SRAM Address 0x2000'0000 + AREA |.ARM.__at_0x20000000|, CODE, READWRITE + +; Each Veneer has exactly a lengs of 4 Byte + + MACRO + STAYHERE $IrqNumber + LDR R0, =$IrqNumber + B . + MEND + + MACRO + JUMPTO $Handler + LDR R0, =$Handler + BX R0 + MEND + + STAYHERE 0x0 ;* Reserved + STAYHERE 0x1 ;* Reserved + STAYHERE 0x2 ;* Reserved + JUMPTO HardFault_Handler ;* HardFault Veneer + STAYHERE 0x4 ;* Reserved + STAYHERE 0x5 ;* Reserved + STAYHERE 0x6 ;* Reserved + STAYHERE 0x7 ;* Reserved + STAYHERE 0x8 ;* Reserved + STAYHERE 0x9 ;* Reserved + STAYHERE 0xA ;* Reserved + JUMPTO SVC_Handler ;* SVC Veneer + STAYHERE 0xC ;* Reserved + STAYHERE 0xD ;* Reserved + JUMPTO PendSV_Handler ;* PendSV Veneer + JUMPTO SysTick_Handler ;* SysTick Veneer + JUMPTO SCU_0_IRQHandler ;* SCU_0 Veneer + JUMPTO SCU_1_IRQHandler ;* SCU_1 Veneer + JUMPTO SCU_2_IRQHandler ;* SCU_2 Veneer + JUMPTO ERU0_0_IRQHandler ;* SCU_3 Veneer + JUMPTO ERU0_1_IRQHandler ;* SCU_4 Veneer + JUMPTO ERU0_2_IRQHandler ;* SCU_5 Veneer + JUMPTO ERU0_3_IRQHandler ;* SCU_6 Veneer + JUMPTO MATH0_0_IRQHandler ;* SCU_7 Veneer + STAYHERE 0x18 ;* Reserved + JUMPTO USIC0_0_IRQHandler ;* USIC0_0 Veneer + JUMPTO USIC0_1_IRQHandler ;* USIC0_1 Veneer + JUMPTO USIC0_2_IRQHandler ;* USIC0_2 Veneer + JUMPTO USIC0_3_IRQHandler ;* USIC0_3 Veneer + JUMPTO USIC0_4_IRQHandler ;* USIC0_4 Veneer + JUMPTO LEDTS0_0_IRQHandler ;* USIC0_5 Veneer + JUMPTO VADC0_C0_0_IRQHandler ;* VADC0_C0_0 Veneer + JUMPTO VADC0_C0_1_IRQHandler ;* VADC0_C0_1 Veneer + JUMPTO VADC0_G0_0_IRQHandler ;* VADC0_G0_0 Veneer + JUMPTO VADC0_G0_1_IRQHandler ;* VADC0_G0_1 Veneer + JUMPTO VADC0_G1_0_IRQHandler ;* VADC0_G1_0 Veneer + JUMPTO VADC0_G1_1_IRQHandler ;* VADC0_G1_1 Veneer + JUMPTO CCU40_0_IRQHandler ;* CCU40_0 Veneer + JUMPTO CCU40_1_IRQHandler ;* CCU40_1 Veneer + JUMPTO CCU40_2_IRQHandler ;* CCU40_2 Veneer + JUMPTO CCU40_3_IRQHandler ;* CCU40_3 Veneer + JUMPTO CCU80_0_IRQHandler ;* CCU80_0 Veneer + JUMPTO CCU80_1_IRQHandler ;* CCU80_1 Veneer + JUMPTO POSIF0_0_IRQHandler ;* POSIF0_0 Veneer + JUMPTO POSIF0_1_IRQHandler ;* POSIF0_1 Veneer + JUMPTO LEDTS0_0_IRQHandler ;* LEDTS0_0 Veneer + JUMPTO LEDTS1_0_IRQHandler ;* LEDTS1_0 Veneer + JUMPTO BCCU0_0_IRQHandler ;* BCCU0_0 Veneer + + ALIGN + +;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */ + + END diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1100.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1100.c new file mode 100644 index 000000000..99884b3e9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1100.c @@ -0,0 +1,99 @@ +/****************************************************************************** + * @file system_XMC1100.c + * @brief Device specific initialization for the XMC1100-Series according + * to CMSIS + * @version V1.2 + * @date 13 Dec 2012 + * + * @note + * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon’s microcontrollers. + * + * This file can be freely distributed within development tools that are + * supporting such microcontrollers. + * + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/* + * *************************** Change history ******************************** + * V1.2, 13 Dec 2012, PKB : Created change history table + */ + +#include "system_XMC1100.h" +#include + +/*--------------------------------------------------------------------------- + Extern definitions + *--------------------------------------------------------------------------*/ +extern uint32_t AllowClkInitByStartup(void); + +/*---------------------------------------------------------------------------- + Clock Global defines + *----------------------------------------------------------------------------*/ +#define DCO_DCLK 64000000UL + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* + * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE + * Clock app. + */ + if(AllowClkInitByStartup()){ + /* Do not change default values of IDIV,FDIV and RTCCLKSEL */ + /* ====== Default configuration ======= */ + /* + * MCLK = DCO_DCLK + * PCLK = MCLK + * RTC CLK = Standby clock + */ + } +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t IDIV, CLKCR; + + CLKCR = SCU_CLOCK -> CLKCR; + + IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos; + + if(IDIV) + { + SystemCoreClock = DCO_DCLK / (2 * IDIV ); + } + else + { + /* Divider bypassed */ + SystemCoreClock = DCO_DCLK; + } +} + diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1200.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1200.c new file mode 100644 index 000000000..5b06bc4c1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1200.c @@ -0,0 +1,99 @@ +/****************************************************************************** + * @file system_XMC1200.c + * @brief Device specific initialization for the XMC1200-Series according + * to CMSIS + * @version V1.2 + * @date 13 Dec 2012 + * + * @note + * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon’s microcontrollers. + * + * This file can be freely distributed within development tools that are + * supporting such microcontrollers. + * + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/* + * *************************** Change history ******************************** + * V1.2, 13 Dec 2012, PKB : Created change history table + */ + +#include "System_XMC1200.h" +#include + +/*--------------------------------------------------------------------------- + Extern definitions + *--------------------------------------------------------------------------*/ +extern uint32_t AllowClkInitByStartup(void); + +/*---------------------------------------------------------------------------- + Clock Global defines + *----------------------------------------------------------------------------*/ +#define DCO_DCLK 64000000UL + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* + * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE + * Clock app. + */ + if(AllowClkInitByStartup()){ + /* Do not change default values of IDIV,FDIV and RTCCLKSEL */ + /* ====== Default configuration ======= */ + /* + * MCLK = DCO_DCLK + * PCLK = MCLK + * RTC CLK = Standby clock + */ + } +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t IDIV, CLKCR; + + CLKCR = SCU_CLOCK -> CLKCR; + + IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos; + + if(IDIV) + { + SystemCoreClock = DCO_DCLK / (2 * IDIV ); + } + else + { + /* Divider bypassed */ + SystemCoreClock = DCO_DCLK; + } +} + diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1300.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1300.c new file mode 100644 index 000000000..c83e3fec6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/System_Keil/system_XMC1300.c @@ -0,0 +1,99 @@ +/****************************************************************************** + * @file system_XMC1300.c + * @brief Device specific initialization for the XMC1300-Series according + * to CMSIS + * @version V1.2 + * @date 13 Dec 2012 + * + * @note + * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. + + * + * @par + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon’s microcontrollers. + * + * This file can be freely distributed within development tools that are + * supporting such microcontrollers. + * + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +/* + * ************************** Change history ********************************* + * V1.2, 13 Dec 2012, PKB, Created this table, Changed System_ to system_ + */ + +#include "system_XMC1300.h" +#include + +/*--------------------------------------------------------------------------- + Extern definitions + *--------------------------------------------------------------------------*/ +extern uint32_t AllowClkInitByStartup(void); + +/*---------------------------------------------------------------------------- + Clock Global defines + *----------------------------------------------------------------------------*/ +#define DCO_DCLK 64000000UL + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/*!< System Clock Frequency (Core Clock)*/ +uint32_t SystemCoreClock; + + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* + * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE + * Clock app. + */ + if(AllowClkInitByStartup()){ + /* Do not change default values of IDIV,FDIV and RTCCLKSEL */ + /* ====== Default configuration ======= */ + /* + * MCLK = DCO_DCLK + * PCLK = MCLK + * RTC CLK = Standby clock + */ + } +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t IDIV, CLKCR; + + CLKCR = SCU_CLOCK -> CLKCR; + + IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos; + + if(IDIV) + { + SystemCoreClock = DCO_DCLK / (2 * IDIV ); + } + else + { + /* Divider bypassed */ + SystemCoreClock = DCO_DCLK; + } +} + diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main-blinky.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main-blinky.c index fd925c5a2..c590e4627 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main-blinky.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main-blinky.c @@ -162,12 +162,12 @@ void main_blinky( void ) { /* Start the two tasks as described in the comments at the top of this file. */ - xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ - ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ - configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ - ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ - mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ - NULL ); /* The task handle is not required, so NULL is passed. */ +// xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ +// ( signed char * ) "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ +// configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ +// ( void * ) mainQUEUE_RECEIVE_PARAMETER, /* The parameter passed to the task - just to check the functionality. */ +// mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ +// NULL ); /* The task handle is not required, so NULL is passed. */ xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, ( void * ) mainQUEUE_SEND_PARAMETER, mainQUEUE_SEND_TASK_PRIORITY, NULL ); @@ -189,6 +189,12 @@ static void prvQueueSendTask( void *pvParameters ) portTickType xNextWakeTime; const unsigned long ulValueToSend = 100UL; +for( ;; ) +{ + vTaskDelay( 100 ); + vParTestToggleLED( 0 ); +} + /* Check the task parameter is as expected. */ configASSERT( ( ( unsigned long ) pvParameters ) == mainQUEUE_SEND_PARAMETER ); diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main-full.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main-full.c index 3f38cd058..09bb24d15 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main-full.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main-full.c @@ -194,10 +194,10 @@ configured). */ const size_t xRegTestStackSize = 25U; /* Create the standard demo tasks */ - vCreateBlockTimeTasks(); - vStartCountingSemaphoreTasks(); - vStartRecursiveMutexTasks(); - vStartDynamicPriorityTasks(); +// vCreateBlockTimeTasks(); +// vStartCountingSemaphoreTasks(); +// vStartRecursiveMutexTasks(); +// vStartDynamicPriorityTasks(); /* Create the register test tasks as described at the top of this file. These are naked functions that don't use any stack. A stack still has @@ -228,18 +228,18 @@ const size_t xRegTestStackSize = 25U; if( xTimer != NULL ) { - xTimerStart( xTimer, mainDONT_BLOCK ); +// xTimerStart( xTimer, mainDONT_BLOCK ); } } /* Create the software timer that performs the 'check' functionality, as described at the top of this file. */ - xTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */ - ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ - pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ - ( void * ) 0, /* The ID is not used, so can be set to anything. */ - prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ - ); +// xTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */ +// ( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */ +// pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */ +// ( void * ) 0, /* The ID is not used, so can be set to anything. */ +// prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */ +// ); /* If the software timer was created successfully, start it. It won't actually start running until the scheduler starts. A block time of @@ -247,7 +247,7 @@ const size_t xRegTestStackSize = 25U; time will be ignored because the scheduler has not started yet. */ if( xTimer != NULL ) { - xTimerStart( xTimer, mainDONT_BLOCK ); +// xTimerStart( xTimer, mainDONT_BLOCK ); } /* Start the kernel. From here on, only tasks and interrupts will run. */ diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main.c index 08d2e4e4b..2eccfa9f1 100644 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main.c +++ b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/main.c @@ -102,11 +102,18 @@ or 0 to run the more comprehensive test and demo application. */ */ static void prvSetupHardware( void ); -/* main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. -main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. */ +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ extern void main_blinky( void ); extern void main_full( void ); +/* + * CMSIS clock configuration function. + */ +extern void SystemCoreClockUpdate( void ); + /*-----------------------------------------------------------*/ int main( void ) @@ -132,6 +139,7 @@ int main( void ) static void prvSetupHardware( void ) { + SystemCoreClockUpdate(); vParTestInitialise(); } /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/startup_XMC1300.s b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/startup_XMC1300.s deleted file mode 100644 index 24c7cbab9..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/startup_XMC1300.s +++ /dev/null @@ -1,397 +0,0 @@ -;*****************************************************************************/ -; * @file startup_XMC1300.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Infineon XMC1300 Device Series -; * @version V1.00 -; * @date 21. Jan. 2013 -; * -; * @note -; * Copyright (C) 2009-2013 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - -;* <<< Use Configuration Wizard in Context Menu >>> - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - -; Clock system handling by SSW -; CLK_VAL1 Configuration -; FDIV Fractional Divider Selection -; IDIV Divider Selection -; <0=> Divider is bypassed -; <1=> MCLK = 32 MHz -; <2=> MCLK = 16 MHz -; <3=> MCLK = 10.67 MHz -; <4=> MCLK = 8 MHz -; <254=> MCLK = 126 kHz -; <255=> MCLK = 125.5 kHz -; PCLKSEL PCLK Clock Select -; <0=> PCLK = MCLK -; <1=> PCLK = 2 x MCLK -; RTCCLKSEL RTC Clock Select -; <0=> 32.768kHz standby clock -; <1=> 32.768kHz external clock from ERU0.IOUT0 -; <2=> 32.768kHz external clock from ACMP0.OUT -; <3=> 32.768kHz external clock from ACMP1.OUT -; <4=> 32.768kHz external clock from ACMP2.OUT -; <5=> Reserved -; <6=> Reserved -; <7=> Reserved -; do not move CLK_VAL1 to SCU_CLKCR[0..19] -; -CLK_VAL1_Val EQU 0x80000000 ; 0xF0000000 - -; CLK_VAL2 Configuration -; disable VADC and SHS Gating -; disable CCU80 Gating -; disable CCU40 Gating -; disable USIC0 Gating -; disable BCCU0 Gating -; disable LEDTS0 Gating -; disable LEDTS1 Gating -; disable POSIF0 Gating -; disable MATH Gating -; disable WDT Gating -; disable RTC Gating -; do not move CLK_VAL2 to SCU_CGATCLR0[0..10] -; -CLK_VAL2_Val EQU 0x80000000 ; 0xF0000000 -; - - PRESERVE8 - THUMB - -;* ================== START OF VECTOR TABLE DEFINITION ====================== */ -;* Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - - - -__Vectors - DCD __initial_sp ;* Top of Stack - DCD Reset_Handler ;* Reset Handler - DCD 0 ;* Not used - DCD 0 ;* Not Used - DCD CLK_VAL1_Val ;* CLK_VAL1 - DCD CLK_VAL2_Val ;* CLK_VAL2 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -;* ================== END OF VECTOR TABLE DEFINITION ======================== */ - - -;* ================== START OF VECTOR ROUTINES ============================== */ - AREA |.text|, CODE, READONLY - -;* Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - - ;* C routines are likely to be called. Setup the stack now - LDR R0, =__initial_sp - MOV SP, R0 - - ; Following code initializes the Veneers at address 0x20000000 with a "branch to itself" - ; The real veneers will be copied later from the scatter loader before reaching main. - ; This init code should handle an exception before the real veneers are copied. -SRAM_BASE EQU 0x20000000 -VENEER_INIT_CODE EQU 0xE7FEBF00 ; NOP, B . - - LDR R1, =SRAM_BASE - LDR R2, =VENEER_INIT_CODE - MOVS R0, #48 ; Veneer 0..47 -Init_Veneers - STR R2, [R1] - ADDS R1, #4 - SUBS R0, R0, #1 - BNE Init_Veneers - - - LDR R0, =SystemInit - BLX R0 - - - ; SystemInit_DAVE3() is provided by DAVE3 code generation engine. It is - ; weakly defined here though for a potential override. - - LDR R0, = SystemInit_DAVE3 - BLX R0 - - - LDR R0, =__main - BX R0 - - - ALIGN - ENDP - -;* ========================================================================== */ - - - -;* ========== START OF EXCEPTION HANDLER DEFINITION ========================= */ -;* Default exception Handlers - Users may override this default functionality - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -;* ============= END OF EXCEPTION HANDLER DEFINITION ======================== */ - - -;* ============= START OF INTERRUPT HANDLER DEFINITION ====================== */ -;* IRQ Handlers - -Default_Handler PROC - EXPORT SCU_0_IRQHandler [WEAK] - EXPORT SCU_1_IRQHandler [WEAK] - EXPORT SCU_2_IRQHandler [WEAK] - EXPORT ERU0_0_IRQHandler [WEAK] - EXPORT ERU0_1_IRQHandler [WEAK] - EXPORT ERU0_2_IRQHandler [WEAK] - EXPORT ERU0_3_IRQHandler [WEAK] - EXPORT MATH0_0_IRQHandler [WEAK] - EXPORT USIC0_0_IRQHandler [WEAK] - EXPORT USIC0_1_IRQHandler [WEAK] - EXPORT USIC0_2_IRQHandler [WEAK] - EXPORT USIC0_3_IRQHandler [WEAK] - EXPORT USIC0_4_IRQHandler [WEAK] - EXPORT USIC0_5_IRQHandler [WEAK] - EXPORT VADC0_C0_0_IRQHandler [WEAK] - EXPORT VADC0_C0_1_IRQHandler [WEAK] - EXPORT VADC0_G0_0_IRQHandler [WEAK] - EXPORT VADC0_G0_1_IRQHandler [WEAK] - EXPORT VADC0_G1_0_IRQHandler [WEAK] - EXPORT VADC0_G1_1_IRQHandler [WEAK] - EXPORT CCU40_0_IRQHandler [WEAK] - EXPORT CCU40_1_IRQHandler [WEAK] - EXPORT CCU40_2_IRQHandler [WEAK] - EXPORT CCU40_3_IRQHandler [WEAK] - EXPORT CCU80_0_IRQHandler [WEAK] - EXPORT CCU80_1_IRQHandler [WEAK] - EXPORT POSIF0_0_IRQHandler [WEAK] - EXPORT POSIF0_1_IRQHandler [WEAK] - EXPORT LEDTS0_0_IRQHandler [WEAK] - EXPORT LEDTS1_0_IRQHandler [WEAK] - EXPORT BCCU0_0_IRQHandler [WEAK] - -SCU_0_IRQHandler -SCU_1_IRQHandler -SCU_2_IRQHandler -ERU0_0_IRQHandler -ERU0_1_IRQHandler -ERU0_2_IRQHandler -ERU0_3_IRQHandler -MATH0_0_IRQHandler -USIC0_0_IRQHandler -USIC0_1_IRQHandler -USIC0_2_IRQHandler -USIC0_3_IRQHandler -USIC0_4_IRQHandler -USIC0_5_IRQHandler -VADC0_C0_0_IRQHandler -VADC0_C0_1_IRQHandler -VADC0_G0_0_IRQHandler -VADC0_G0_1_IRQHandler -VADC0_G1_0_IRQHandler -VADC0_G1_1_IRQHandler -CCU40_0_IRQHandler -CCU40_1_IRQHandler -CCU40_2_IRQHandler -CCU40_3_IRQHandler -CCU80_0_IRQHandler -CCU80_1_IRQHandler -POSIF0_0_IRQHandler -POSIF0_1_IRQHandler -LEDTS0_0_IRQHandler -LEDTS1_0_IRQHandler -BCCU0_0_IRQHandler - - B . - - ENDP - - ALIGN - -;* ============= END OF INTERRUPT HANDLER DEFINITION ======================== */ - -;* Definition of the default weak SystemInit_DAVE3 function. -;* This function will be called by the CMSIS SystemInit function. -;* If DAVE3 requires an extended SystemInit it will create its own SystemInit_DAVE3 -;* which will overule this weak definition -SystemInit_DAVE3 PROC - EXPORT SystemInit_DAVE3 [WEAK] - NOP - BX LR - ENDP - -;* Definition of the default weak DAVE3 function for clock App usage. -;* AllowClkInitByStartup Handler */ -AllowClkInitByStartup PROC - EXPORT AllowClkInitByStartup [WEAK] - MOVS R0,#1 - BX LR - ENDP - - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - -;* ================== START OF INTERRUPT HANDLER VENEERS ==================== */ -; Veneers are located to fix SRAM Address 0x2000'0000 - AREA |.ARM.__at_0x20000000|, CODE, READWRITE - -; Each Veneer has exactly a lengs of 4 Byte - - MACRO - STAYHERE $IrqNumber - LDR R0, =$IrqNumber - B . - MEND - - MACRO - JUMPTO $Handler - LDR R0, =$Handler - BX R0 - MEND - - STAYHERE 0x0 ;* Reserved - STAYHERE 0x1 ;* Reserved - STAYHERE 0x2 ;* Reserved - JUMPTO HardFault_Handler ;* HardFault Veneer - STAYHERE 0x4 ;* Reserved - STAYHERE 0x5 ;* Reserved - STAYHERE 0x6 ;* Reserved - STAYHERE 0x7 ;* Reserved - STAYHERE 0x8 ;* Reserved - STAYHERE 0x9 ;* Reserved - STAYHERE 0xA ;* Reserved - JUMPTO SVC_Handler ;* SVC Veneer - STAYHERE 0xC ;* Reserved - STAYHERE 0xD ;* Reserved - JUMPTO PendSV_Handler ;* PendSV Veneer - JUMPTO SysTick_Handler ;* SysTick Veneer - JUMPTO SCU_0_IRQHandler ;* SCU_0 Veneer - JUMPTO SCU_1_IRQHandler ;* SCU_1 Veneer - JUMPTO SCU_2_IRQHandler ;* SCU_2 Veneer - JUMPTO ERU0_0_IRQHandler ;* SCU_3 Veneer - JUMPTO ERU0_1_IRQHandler ;* SCU_4 Veneer - JUMPTO ERU0_2_IRQHandler ;* SCU_5 Veneer - JUMPTO ERU0_3_IRQHandler ;* SCU_6 Veneer - JUMPTO MATH0_0_IRQHandler ;* SCU_7 Veneer - STAYHERE 0x18 ;* Reserved - JUMPTO USIC0_0_IRQHandler ;* USIC0_0 Veneer - JUMPTO USIC0_1_IRQHandler ;* USIC0_1 Veneer - JUMPTO USIC0_2_IRQHandler ;* USIC0_2 Veneer - JUMPTO USIC0_3_IRQHandler ;* USIC0_3 Veneer - JUMPTO USIC0_4_IRQHandler ;* USIC0_4 Veneer - JUMPTO LEDTS0_0_IRQHandler ;* USIC0_5 Veneer - JUMPTO VADC0_C0_0_IRQHandler ;* VADC0_C0_0 Veneer - JUMPTO VADC0_C0_1_IRQHandler ;* VADC0_C0_1 Veneer - JUMPTO VADC0_G0_0_IRQHandler ;* VADC0_G0_0 Veneer - JUMPTO VADC0_G0_1_IRQHandler ;* VADC0_G0_1 Veneer - JUMPTO VADC0_G1_0_IRQHandler ;* VADC0_G1_0 Veneer - JUMPTO VADC0_G1_1_IRQHandler ;* VADC0_G1_1 Veneer - JUMPTO CCU40_0_IRQHandler ;* CCU40_0 Veneer - JUMPTO CCU40_1_IRQHandler ;* CCU40_1 Veneer - JUMPTO CCU40_2_IRQHandler ;* CCU40_2 Veneer - JUMPTO CCU40_3_IRQHandler ;* CCU40_3 Veneer - JUMPTO CCU80_0_IRQHandler ;* CCU80_0 Veneer - JUMPTO CCU80_1_IRQHandler ;* CCU80_1 Veneer - JUMPTO POSIF0_0_IRQHandler ;* POSIF0_0 Veneer - JUMPTO POSIF0_1_IRQHandler ;* POSIF0_1 Veneer - JUMPTO LEDTS0_0_IRQHandler ;* LEDTS0_0 Veneer - JUMPTO LEDTS1_0_IRQHandler ;* LEDTS1_0 Veneer - JUMPTO BCCU0_0_IRQHandler ;* BCCU0_0 Veneer - - ALIGN - -;* ================== END OF INTERRUPT HANDLER VENEERS ====================== */ - - END diff --git a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/system_XMC1300.c b/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/system_XMC1300.c deleted file mode 100644 index c83e3fec6..000000000 --- a/FreeRTOS/Demo/CORTEX_M0_Infineon_Boot_Kits_IAR_Keil/system_XMC1300.c +++ /dev/null @@ -1,99 +0,0 @@ -/****************************************************************************** - * @file system_XMC1300.c - * @brief Device specific initialization for the XMC1300-Series according - * to CMSIS - * @version V1.2 - * @date 13 Dec 2012 - * - * @note - * Copyright (C) 2012-2013 Infineon Technologies AG. All rights reserved. - - * - * @par - * Infineon Technologies AG (Infineon) is supplying this software for use with - * Infineon’s microcontrollers. - * - * This file can be freely distributed within development tools that are - * supporting such microcontrollers. - * - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, - * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -/* - * ************************** Change history ********************************* - * V1.2, 13 Dec 2012, PKB, Created this table, Changed System_ to system_ - */ - -#include "system_XMC1300.h" -#include - -/*--------------------------------------------------------------------------- - Extern definitions - *--------------------------------------------------------------------------*/ -extern uint32_t AllowClkInitByStartup(void); - -/*---------------------------------------------------------------------------- - Clock Global defines - *----------------------------------------------------------------------------*/ -#define DCO_DCLK 64000000UL - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -/*!< System Clock Frequency (Core Clock)*/ -uint32_t SystemCoreClock; - - -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* - * Clock tree setup by CMSIS routines is allowed only in the absence of DAVE - * Clock app. - */ - if(AllowClkInitByStartup()){ - /* Do not change default values of IDIV,FDIV and RTCCLKSEL */ - /* ====== Default configuration ======= */ - /* - * MCLK = DCO_DCLK - * PCLK = MCLK - * RTC CLK = Standby clock - */ - } -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t IDIV, CLKCR; - - CLKCR = SCU_CLOCK -> CLKCR; - - IDIV = (CLKCR & SCU_CLOCK_CLKCR_IDIV_Msk) >> SCU_CLOCK_CLKCR_IDIV_Pos; - - if(IDIV) - { - SystemCoreClock = DCO_DCLK / (2 * IDIV ); - } - else - { - /* Divider bypassed */ - SystemCoreClock = DCO_DCLK; - } -} -