From: Simon Glass <sjg@chromium.org>
Date: Sun, 17 Jan 2016 23:11:33 +0000 (-0700)
Subject: x86: ivybridge: Drop unnecessary northbridge setup
X-Git-Tag: v2016.03-rc1~105
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=887cba8f38e237735bb1d84b34dfbbf032e5b6b6;p=u-boot

x86: ivybridge: Drop unnecessary northbridge setup

This is done by default with PCI auto-config. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
index 8af99b4447..b081469c96 100644
--- a/arch/x86/cpu/ivybridge/pci.c
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -19,32 +19,12 @@
 
 static int pci_ivybridge_probe(struct udevice *bus)
 {
-	struct pci_controller *hose = dev_get_uclass_priv(bus);
-	pci_dev_t dev;
-	u16 reg16;
-
 	if (!(gd->flags & GD_FLG_RELOC))
 		return 0;
 	post_code(0x50);
 	bd82x6x_init_extra();
 	post_code(0x51);
 
-	reg16 = 0xff;
-	dev = PCH_DEV;
-	reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
-	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	x86_pci_write_config16(dev, PCI_COMMAND, reg16);
-
-	/*
-	* Clear non-reserved bits in status register.
-	*/
-	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
-	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
-	pci_write_bar32(hose, dev, 0, 0xf0000000);
-	post_code(0x52);
-
 	return 0;
 }