From: Chandan Nath <chandan.nath@ti.com>
Date: Tue, 24 Jul 2012 12:22:18 +0000 (+0000)
Subject: am33xx: pin mux defintions for CPSW switch
X-Git-Tag: v2012.10-rc1~329
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=89017e150e2e142c1b6d3239797bcfac47f7f098;p=u-boot

am33xx: pin mux defintions for CPSW switch

This patch adds pin mux settings for CPSW switch found on
TI AM335X based boards (MII and RGMII modes).

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
[Ilya: split pinmux into separate patch]
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
---

diff --git a/arch/arm/include/asm/arch-am33xx/common_def.h b/arch/arm/include/asm/arch-am33xx/common_def.h
index aa3b554536..5a7b0f3d34 100644
--- a/arch/arm/include/asm/arch-am33xx/common_def.h
+++ b/arch/arm/include/asm/arch-am33xx/common_def.h
@@ -19,5 +19,7 @@
 extern void enable_uart0_pin_mux(void);
 extern void enable_mmc0_pin_mux(void);
 extern void enable_i2c0_pin_mux(void);
+extern void enable_mii1_pin_mux(void);
+extern void enable_rgmii1_pin_mux(void);
 
 #endif/*__COMMON_DEF_H__ */
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index c696c0fe95..a1661e6130 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -288,6 +288,43 @@ static struct module_pin_mux i2c1_pin_mux[] = {
 	{-1},
 };
 
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
+	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
+	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
+	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
 /*
  * Configure the pin mux for the module
  */
@@ -323,3 +360,13 @@ void enable_i2c1_pin_mux(void)
 {
 	configure_module_pin_mux(i2c1_pin_mux);
 }
+
+void enable_rgmii1_pin_mux(void)
+{
+	configure_module_pin_mux(rgmii1_pin_mux);
+}
+
+void enable_mii1_pin_mux(void)
+{
+	configure_module_pin_mux(mii1_pin_mux);
+}