From: York Sun Date: Fri, 29 Jul 2016 16:02:29 +0000 (-0700) Subject: driver/ddr/fsl: Fix timing_cfg_2 X-Git-Tag: v2016.09-rc2~139^2~4 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8936691ba69bc322201c62e977e2803cfe67fc40;p=u-boot driver/ddr/fsl: Fix timing_cfg_2 Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the change was wrong. wr_lat has 5 bits with MSB at [13] and lower 4 bits at [9:12], in big-endian convention. Signed-off-by: York Sun Reported-by: Thomas Schaefer --- diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index abd576b935..24fd36602d 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num, | ((add_lat_mclk & 0xf) << 28) | ((cpo & 0x1f) << 23) | ((wr_lat & 0xf) << 19) - | ((wr_lat & 0x10) << 18) + | (((wr_lat & 0x10) >> 4) << 18) | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) | ((cke_pls & 0x7) << 6)