From: Stefan Roese Date: Wed, 21 Jul 2010 09:08:16 +0000 (+0200) Subject: ppc4xx: Only define DDR2 registers for the correct PowerPC variants X-Git-Tag: v2010.09-rc1~76^2^2~5 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=897d6abc50e95fb57fa6952c27deae5776ba08cc;p=u-boot ppc4xx: Only define DDR2 registers for the correct PowerPC variants Make sure that some SDRAM/DDR2 registers are only defined for the PPC variants really implementing those registers. Signed-off-by: Stefan Roese --- diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index d9506e27c1..42eac4531f 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -363,6 +363,7 @@ /* * Memory controller registers */ +#ifdef CONFIG_405EX #define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */ #define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */ #define SDRAM_BEARL 0x02 /* PLB bus error address low */ @@ -371,11 +372,10 @@ #define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */ #define SDRAM_PLBOPT 0x08 /* PLB slave options */ #define SDRAM_PUABA 0x09 /* PLB upper address base */ -#ifndef CONFIG_405EX -#define SDRAM_MCSTAT 0x14 /* memory controller status */ -#else #define SDRAM_MCSTAT 0x1F /* memory controller status */ -#endif +#else /* CONFIG_405EX */ +#define SDRAM_MCSTAT 0x14 /* memory controller status */ +#endif /* CONFIG_405EX */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */