From: Fabio Estevam <fabio.estevam@freescale.com>
Date: Tue, 3 Dec 2013 20:26:13 +0000 (-0200)
Subject: mx6: clock: Fix the calculation of PLL_ENET frequency
X-Git-Tag: v2014.01-rc3~9^2~47^2~20
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=89cfd0f5757413093ad179478b80367d7bd34ecc;p=u-boot

mx6: clock: Fix the calculation of PLL_ENET frequency

According to the mx6 quad reference manual, the DIV_SELECT field of register
CCM_ANALOG_PLL_ENETn has the following meaning:

"Controls the frequency of the ethernet reference clock.
- 00 - 25MHz
- 01 - 50MHz
- 10 - 100MHz
- 11 - 125MHz"

Current logic does not handle the 25MHz case correctly, so fix it.

Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 873d9d0fd8..20c7e70a78 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -94,7 +94,7 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 		div = __raw_readl(&imx_ccm->analog_pll_enet);
 		div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
 
-		return (div == 3 ? 125000000 : 25000000 * (div << 1));
+		return 25000000 * (div + (div >> 1) + 1);
 	default:
 		return 0;
 	}