From: Wolfgang Denk Date: Tue, 24 Feb 2009 21:52:16 +0000 (+0100) Subject: Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx X-Git-Tag: v2009.03-rc2~15 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=89e372cd3d520ed20fab543f2cbba2dbb9490cf8;hp=bd76729bcbfd64b5d016a9b936f058931fc06eaf;p=u-boot Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx --- diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c index 8bb31fc741..83e89cf2ec 100644 --- a/board/freescale/mpc837xerdb/pci.c +++ b/board/freescale/mpc837xerdb/pci.c @@ -13,6 +13,7 @@ #include #include #include +#include #if defined(CONFIG_PCI) static struct pci_region pci_regions[] = { @@ -36,12 +37,46 @@ static struct pci_region pci_regions[] = { } }; +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + void pci_init_board(void) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile sysconf83xx_t *sysconf = &immr->sysconf; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile law83xx_t *pcie_law = sysconf->pcielaw; struct pci_region *reg[] = { pci_regions }; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; + u32 spridr = in_be32(&immr->sysconf.spridr); /* Enable all 5 PCI_CLK_OUTPUTS */ clk->occr |= 0xf8000000; @@ -55,5 +90,27 @@ void pci_init_board(void) pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; mpc83xx_pci_init(1, reg, 0); + + /* There is no PEX in MPC8379 parts. */ + if (PARTID_NO_E(spridr) == SPR_8379) + return; + + /* Configure the clock for PCIE controller */ + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, + SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(2, pcie_reg, 0); } #endif /* CONFIG_PCI */ diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c index 5fe89646c0..a42b230ff3 100644 --- a/cpu/mpc83xx/pci.c +++ b/cpu/mpc83xx/pci.c @@ -91,7 +91,7 @@ static void pci_init_bus(int bus, struct pci_region *reg) hose->regions[i].size = gd->ram_size; hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; - hose->first_busno = 0; + hose->first_busno = pci_last_busno() + 1; hose->last_busno = 0xff; pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80, @@ -227,8 +227,8 @@ void ft_pci_setup(void *blob, bd_t *bd) path = fdt_getprop(blob, nodeoffset, "pci1", NULL); if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); + tmp[0] = cpu_to_be32(pci_hose[1].first_busno); + tmp[1] = cpu_to_be32(pci_hose[1].last_busno); do_fixup_by_path(blob, path, "bus-range", &tmp, sizeof(tmp), 1); diff --git a/cpu/mpc83xx/pcie.c b/cpu/mpc83xx/pcie.c index 12b5f69ced..77f8906b9f 100644 --- a/cpu/mpc83xx/pcie.c +++ b/cpu/mpc83xx/pcie.c @@ -60,6 +60,9 @@ static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) #define cfg_write(val, addr, type, op) \ do { op((type *)(addr), (val)); } while (0) +#define cfg_read_err(val) do { *val = -1; } while (0) +#define cfg_write_err(val) do { } while (0) + #define PCIE_OP(rw, size, type, op) \ static int pcie_##rw##_config_##size(struct pci_controller *hose, \ pci_dev_t dev, int offset, \ @@ -68,8 +71,10 @@ static int pcie_##rw##_config_##size(struct pci_controller *hose, \ int ret; \ \ ret = mpc83xx_pcie_remap_cfg(hose, dev); \ - if (ret) \ - return ret; \ + if (ret) { \ + cfg_##rw##_err(val); \ + return ret; \ + } \ cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \ return 0; \ } @@ -86,7 +91,6 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, { extern void disable_addr_trans(void); /* start.S */ static struct pci_controller pcie_hose[PCIE_MAX_BUSES]; - static int max_bus; struct pci_controller *hose = &pcie_hose[bus]; int i; @@ -117,7 +121,7 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, hose->regions[i].size = 0x100000; hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; - hose->first_busno = max_bus; + hose->first_busno = pci_last_busno() + 1; hose->last_busno = 0xff; if (bus == 0) @@ -145,7 +149,6 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, * Hose scan. */ hose->last_busno = pci_hose_scan(hose); - max_bus = hose->last_busno + 1; } #else diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index fffca49fce..d6d2d6e4ad 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -165,6 +165,19 @@ struct pci_controller *pci_bus_to_hose (int bus) return NULL; } +int pci_last_busno(void) +{ + struct pci_controller *hose = hose_head; + + if (!hose) + return -1; + + while (hose->next) + hose = hose->next; + + return hose->last_busno; +} + #ifndef CONFIG_IXP425 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index) { diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 14cbc45715..5e1ddaedd6 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -78,6 +78,7 @@ #ifdef CONFIG_MPC8349ITX #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ +#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ #endif #define CONFIG_PCI @@ -141,7 +142,16 @@ #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ -#define CONFIG_DOS_PARTITION +#endif + +/* + * SATA + */ +#ifdef CONFIG_SATA_SIL3114 + +#define CONFIG_SYS_SATA_MAX_DEVICE 4 +#define CONFIG_LIBATA +#define CONFIG_LBA48 #endif @@ -449,9 +459,18 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_CMD_PING #define CONFIG_CMD_SDRAM +#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) + #define CONFIG_DOS_PARTITION + #define CONFIG_CMD_FAT +#endif + #ifdef CONFIG_COMPACT_FLASH #define CONFIG_CMD_IDE - #define CONFIG_CMD_FAT +#endif + +#ifdef CONFIG_SATA_SIL3114 + #define CONFIG_CMD_SATA + #define CONFIG_CMD_EXT2 #endif #ifdef CONFIG_PCI diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 2e31dd00a8..8d0c93b715 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -49,6 +49,7 @@ #else #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ #define CONFIG_83XX_GENERIC_PCI 1 +#define CONFIG_83XX_GENERIC_PCIE 1 #endif #ifndef CONFIG_SYS_CLK_FREQ @@ -375,6 +376,26 @@ #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +#define CONFIG_SYS_PCIE2_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 +#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 + #ifdef CONFIG_PCI #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 3554fdd4ed..fab37516cf 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -890,6 +890,8 @@ #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ +#define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */ +#define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ diff --git a/include/pci.h b/include/pci.h index d0594e316c..aaa4554344 100644 --- a/include/pci.h +++ b/include/pci.h @@ -535,6 +535,8 @@ extern int pci_hose_config_device(struct pci_controller *hose, pci_addr_t mem, unsigned long command); +int pci_last_busno(void); + #ifdef CONFIG_MPC824X extern void pci_mpc824x_init (struct pci_controller *hose); #endif