From: Spencer Oliver Date: Thu, 28 Jul 2011 10:45:09 +0000 (+0100) Subject: cfg: update scripts to use new stm32 driver names X-Git-Tag: v0.5.0~8 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=89f593d8cbd74eb1db5d6beb2e60e9844504db6e;p=openocd cfg: update scripts to use new stm32 driver names Signed-off-by: Spencer Oliver --- diff --git a/tcl/board/hitex_stm32-performancestick.cfg b/tcl/board/hitex_stm32-performancestick.cfg index 515f7e08..0ec4076b 100644 --- a/tcl/board/hitex_stm32-performancestick.cfg +++ b/tcl/board/hitex_stm32-performancestick.cfg @@ -5,7 +5,7 @@ reset_config trst_and_srst source [find interface/stm32-stick.cfg] set CHIPNAME stm32_hitex -source [find target/stm32.cfg] +source [find target/stm32f1x.cfg] # configure str750 connected to jtag chain # FIXME -- source [find target/str750.cfg] after cleaning that up diff --git a/tcl/board/olimex_stm32_h103.cfg b/tcl/board/olimex_stm32_h103.cfg index 98b0b658..ec03034c 100644 --- a/tcl/board/olimex_stm32_h103.cfg +++ b/tcl/board/olimex_stm32_h103.cfg @@ -4,4 +4,4 @@ # Work-area size (RAM size) = 20kB for STM32F103RB device set WORKAREASIZE 0x5000 -source [find target/stm32.cfg] +source [find target/stm32f1x.cfg] diff --git a/tcl/board/olimex_stm32_h107.cfg b/tcl/board/olimex_stm32_h107.cfg index c21e19bd..1d34a234 100644 --- a/tcl/board/olimex_stm32_h107.cfg +++ b/tcl/board/olimex_stm32_h107.cfg @@ -5,4 +5,4 @@ # Work-area size (RAM size) = 64kB for STM32F107VC device set WORKAREASIZE 0x10000 -source [find target/stm32.cfg] +source [find target/stm32f1x.cfg] diff --git a/tcl/board/stm32100b_eval.cfg b/tcl/board/stm32100b_eval.cfg index e04b612b..41153e55 100644 --- a/tcl/board/stm32100b_eval.cfg +++ b/tcl/board/stm32100b_eval.cfg @@ -4,4 +4,4 @@ # The chip has only 8KB sram set WORKAREASIZE 0x2000 -source [find target/stm32.cfg] +source [find target/stm32f1x.cfg] diff --git a/tcl/board/stm3210b_eval.cfg b/tcl/board/stm3210b_eval.cfg index 70798c18..ff3f7771 100644 --- a/tcl/board/stm3210b_eval.cfg +++ b/tcl/board/stm3210b_eval.cfg @@ -4,4 +4,4 @@ # increase working area to 32KB for faster flash programming set WORKAREASIZE 0x8000 -source [find target/stm32.cfg] +source [find target/stm32f1x.cfg] diff --git a/tcl/board/stm3210c_eval.cfg b/tcl/board/stm3210c_eval.cfg index 27684f0d..e069c049 100644 --- a/tcl/board/stm3210c_eval.cfg +++ b/tcl/board/stm3210c_eval.cfg @@ -4,4 +4,4 @@ # increase working area to 32KB for faster flash programming set WORKAREASIZE 0x8000 -source [find target/stm32.cfg] +source [find target/stm32f1x.cfg] diff --git a/tcl/board/stm3210e_eval.cfg b/tcl/board/stm3210e_eval.cfg index 786d0279..91807ce3 100644 --- a/tcl/board/stm3210e_eval.cfg +++ b/tcl/board/stm3210e_eval.cfg @@ -4,7 +4,7 @@ # increase working area to 32KB for faster flash programming set WORKAREASIZE 0x8000 -source [find target/stm32.cfg] +source [find target/stm32f1x.cfg] # # configure FSMC Bank 1 (NOR/PSRAM Bank 2) NOR flash diff --git a/tcl/board/stm3220g_eval.cfg b/tcl/board/stm3220g_eval.cfg index e836f0ed..48b57c13 100644 --- a/tcl/board/stm3220g_eval.cfg +++ b/tcl/board/stm3220g_eval.cfg @@ -8,4 +8,4 @@ set WORKAREASIZE 0x20000 # chip name set CHIPNAME STM32F207IGT6 -source [find target/stm32f2xxx.cfg] +source [find target/stm32f2x.cfg] diff --git a/tcl/target/stm32.cfg b/tcl/target/stm32.cfg deleted file mode 100644 index 9879c045..00000000 --- a/tcl/target/stm32.cfg +++ /dev/null @@ -1,75 +0,0 @@ -# script for stm32 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32 -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -# By default use 16kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x4000 -} - -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz -adapter_khz 1000 - -adapter_nsrst_delay 100 -jtag_ntrst_delay 100 - -#jtag scan chain -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - # See STM Document RM0008 - # Section 26.6.3 - set _CPUTAPID 0x3ba00477 -} -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID ] } { - # FIXME this never gets used to override defaults... - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0008 - # Section 29.6.2 - # Low density devices, Rev A - set _BSTAPID1 0x06412041 - # Medium density devices, Rev A - set _BSTAPID2 0x06410041 - # Medium density devices, Rev B and Rev Z - set _BSTAPID3 0x16410041 - set _BSTAPID4 0x06420041 - # High density devices, Rev A - set _BSTAPID5 0x06414041 - # Connectivity line devices, Rev A and Rev Z - set _BSTAPID6 0x06418041 - # XL line devices, Rev A - set _BSTAPID7 0x06430041 -} -jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ - -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ - -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \ - -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -# flash size will be probed -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32x 0x08000000 0 0 0 $_TARGETNAME - -# if srst is not fitted use SYSRESETREQ to -# perform a soft reset -cortex_m3 reset_config sysresetreq diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg new file mode 100644 index 00000000..8007ff57 --- /dev/null +++ b/tcl/target/stm32f1x.cfg @@ -0,0 +1,75 @@ +# script for stm32 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 16kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x4000 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +adapter_khz 1000 + +adapter_nsrst_delay 100 +jtag_ntrst_delay 100 + +#jtag scan chain +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0008 + # Section 26.6.3 + set _CPUTAPID 0x3ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + # FIXME this never gets used to override defaults... + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0008 + # Section 29.6.2 + # Low density devices, Rev A + set _BSTAPID1 0x06412041 + # Medium density devices, Rev A + set _BSTAPID2 0x06410041 + # Medium density devices, Rev B and Rev Z + set _BSTAPID3 0x16410041 + set _BSTAPID4 0x06420041 + # High density devices, Rev A + set _BSTAPID5 0x06414041 + # Connectivity line devices, Rev A and Rev Z + set _BSTAPID6 0x06418041 + # XL line devices, Rev A + set _BSTAPID7 0x06430041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ + -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \ + -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \ + -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m3 reset_config sysresetreq diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg new file mode 100644 index 00000000..b8de3843 --- /dev/null +++ b/tcl/target/stm32f2x.cfg @@ -0,0 +1,61 @@ +# script for stm32f2xxx + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f2xxx +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 64kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x10000 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. +jtag_khz 1000 + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#jtag scan chain +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0033 + # Section 32.6.3 - corresponds to Cortex-M3 r2p0 + set _CPUTAPID 0x4ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0033 + # Section 32.6.2 + # + set _BSTAPID 0x06411041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME + diff --git a/tcl/target/stm32f2xxx.cfg b/tcl/target/stm32f2xxx.cfg deleted file mode 100644 index 8a857244..00000000 --- a/tcl/target/stm32f2xxx.cfg +++ /dev/null @@ -1,61 +0,0 @@ -# script for stm32f2xxx - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME stm32f2xxx -} - -if { [info exists ENDIAN] } { - set _ENDIAN $ENDIAN -} else { - set _ENDIAN little -} - -# Work-area is a space in RAM used for flash programming -# By default use 64kB -if { [info exists WORKAREASIZE] } { - set _WORKAREASIZE $WORKAREASIZE -} else { - set _WORKAREASIZE 0x10000 -} - -# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz -# -# Since we may be running of an RC oscilator, we crank down the speed a -# bit more to be on the safe side. Perhaps superstition, but if are -# running off a crystal, we can run closer to the limit. Note -# that there can be a pretty wide band where things are more or less stable. -jtag_khz 1000 - -jtag_nsrst_delay 100 -jtag_ntrst_delay 100 - -#jtag scan chain -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - # See STM Document RM0033 - # Section 32.6.3 - corresponds to Cortex-M3 r2p0 - set _CPUTAPID 0x4ba00477 -} -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID - -if { [info exists BSTAPID ] } { - set _BSTAPID $BSTAPID -} else { - # See STM Document RM0033 - # Section 32.6.2 - # - set _BSTAPID 0x06411041 -} -jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID - -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME - -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 - -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stm32f2xxx 0 0 0 0 $_TARGETNAME - diff --git a/tcl/target/stm32xl.cfg b/tcl/target/stm32xl.cfg index cde07df2..f72896d3 100644 --- a/tcl/target/stm32xl.cfg +++ b/tcl/target/stm32xl.cfg @@ -1,6 +1,6 @@ # script for stm32xl family (dual flash bank) -source [find target/stm32.cfg] +source [find target/stm32f1x.cfg] # flash size will be probed set _FLASHNAME $_CHIPNAME.flash1 -flash bank $_FLASHNAME stm32x 0x08080000 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME