From: Marek Vasut <marek.vasut+renesas@gmail.com>
Date: Thu, 1 Mar 2018 20:52:19 +0000 (+0100)
Subject: ARM: dts: rmobile: Add SDHI nodes to R8A77965 M3N DT
X-Git-Tag: v2018.03-rc4~1^2~3
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=89fcfd1f58e1208afe8b6f9ac09a0bcf76c82cc4;p=u-boot

ARM: dts: rmobile: Add SDHI nodes to R8A77965 M3N DT

Add SDHI nodes to r8a77965.dtsi to get eMMC and SD slots operational.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---

diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi
index bb29843d31..7eb4e65ea4 100644
--- a/arch/arm/dts/r8a77965.dtsi
+++ b/arch/arm/dts/r8a77965.dtsi
@@ -749,19 +749,47 @@
 		};
 
 		sdhi0: sd@ee100000 {
-			/* placeholder */
+			compatible = "renesas,sdhi-r8a77965";
+			reg = <0 0xee100000 0 0x2000>;
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 314>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 314>;
+			status = "disabled";
 		};
 
 		sdhi1: sd@ee120000 {
-			/* placeholder */
+			compatible = "renesas,sdhi-r8a77965";
+			reg = <0 0xee120000 0 0x2000>;
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 313>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 313>;
+			status = "disabled";
 		};
 
 		sdhi2: sd@ee140000 {
-			/* placeholder */
+			compatible = "renesas,sdhi-r8a77965";
+			reg = <0 0xee140000 0 0x2000>;
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 312>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 312>;
+			status = "disabled";
 		};
 
 		sdhi3: sd@ee160000 {
-			/* placeholder */
+			compatible = "renesas,sdhi-r8a77965";
+			reg = <0 0xee160000 0 0x2000>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 311>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc 32>;
+			resets = <&cpg 311>;
+			status = "disabled";
 		};
 
 		usb3_phy0: usb-phy@e65ee000 {