From: Chen-Yu Tsai Date: Thu, 31 Aug 2017 13:57:48 +0000 (+0800) Subject: mmc: sunxi: Only update timing mode bit when enabling new timing mode X-Git-Tag: v2017.09-rc4~42^2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8a647fc3ca2a93e2b6c965999ac2e0316191a755;p=u-boot mmc: sunxi: Only update timing mode bit when enabling new timing mode When enabling the new mmc timing mode, we inadvertently clear all the remaining bits in the new timing mode register. The bits cleared include a default phase delay on the output clock. The BSP kernel states that the default values are supposed to be used. Clearing them results in decreased performance or transfer errors on some boards. Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode") Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Reviewed-by: Jagan Teki --- diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index a76e763bfd..4edb4be46c 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -167,7 +167,7 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz) if (new_mode) { #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE val = CCM_MMC_CTRL_MODE_SEL_NEW; - writel(SUNXI_MMC_NTSR_MODE_SEL_NEW, &priv->reg->ntsr); + setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW); #endif } else { val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |