From: Keerthy Date: Thu, 15 May 2014 05:38:39 +0000 (+0530) Subject: ARM: DRA72x: volt: Update the pmic offsets X-Git-Tag: v2014.07-rc2~2^2^2~13 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=8b0d1bbc7e181945d84db667d63081a96ea40a47;p=u-boot ARM: DRA72x: volt: Update the pmic offsets TPS65917 is used in DRA722 evm. Update the address offsets accordingly. Signed-off-by: Lokesh Vutla Signed-off-by: Keerthy Acked-by: Tom Rini --- diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ad971327bf..802b155f32 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -372,6 +372,38 @@ struct vcores_data dra752_volts = { .iva.pmic = &tps659038, }; +struct vcores_data dra722_volts = { + .mpu.value = 1000, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = 0x23, + .mpu.pmic = &tps659038, + + .eve.value = 1000, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = 0x2f, + .eve.pmic = &tps659038, + + .gpu.value = 1000, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = 0x2f, + .gpu.pmic = &tps659038, + + .core.value = 1000, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = 0x27, + .core.pmic = &tps659038, + + .iva.value = 1000, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = 0x2f, + .iva.pmic = &tps659038, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed